| 1 | /*===- TableGen'erated file -------------------------------------*- C++ -*-===*\ |
|---|---|
| 2 | |* *| |
| 3 | |* Global Instruction Selector for the AMDGPU target *| |
| 4 | |* *| |
| 5 | |* Automatically generated file, do not edit! *| |
| 6 | |* *| |
| 7 | \*===----------------------------------------------------------------------===*/ |
| 8 | |
| 9 | #ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 10 | const unsigned MAX_SUBTARGET_PREDICATES = 116; |
| 11 | using PredicateBitset = llvm::Bitset<MAX_SUBTARGET_PREDICATES>; |
| 12 | #endif // ifdef GET_GLOBALISEL_PREDICATE_BITSET |
| 13 | |
| 14 | #ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 15 | mutable MatcherState State; |
| 16 | typedef ComplexRendererFns(AMDGPUInstructionSelector::*ComplexMatcherMemFn)(MachineOperand &) const; |
| 17 | typedef void(AMDGPUInstructionSelector::*CustomRendererFn)(MachineInstrBuilder &, const MachineInstr &, int) const; |
| 18 | const ExecInfoTy<PredicateBitset, ComplexMatcherMemFn, CustomRendererFn> ExecInfo; |
| 19 | static AMDGPUInstructionSelector::ComplexMatcherMemFn ComplexPredicateFns[]; |
| 20 | static AMDGPUInstructionSelector::CustomRendererFn CustomRenderers[]; |
| 21 | bool testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const override; |
| 22 | bool testImmPredicate_APInt(unsigned PredicateID, const APInt &Imm) const override; |
| 23 | bool testImmPredicate_APFloat(unsigned PredicateID, const APFloat &Imm) const override; |
| 24 | const uint8_t *getMatchTable() const override; |
| 25 | bool testMIPredicate_MI(unsigned PredicateID, const MachineInstr &MI, const MatcherState &State) const override; |
| 26 | bool testSimplePredicate(unsigned PredicateID) const override; |
| 27 | bool runCustomAction(unsigned FnID, const MatcherState &State, NewMIVector &OutMIs) const override; |
| 28 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_DECL |
| 29 | |
| 30 | #ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 31 | , State(6), |
| 32 | ExecInfo(TypeObjects, NumTypeObjects, FeatureBitsets, ComplexPredicateFns, CustomRenderers) |
| 33 | #endif // ifdef GET_GLOBALISEL_TEMPORARIES_INIT |
| 34 | |
| 35 | #ifdef GET_GLOBALISEL_IMPL |
| 36 | // LLT Objects. |
| 37 | enum { |
| 38 | GILLT_p0s64, |
| 39 | GILLT_p1s64, |
| 40 | GILLT_p2s32, |
| 41 | GILLT_p3s32, |
| 42 | GILLT_p4s64, |
| 43 | GILLT_p5s32, |
| 44 | GILLT_p6s32, |
| 45 | GILLT_s1, |
| 46 | GILLT_s16, |
| 47 | GILLT_s32, |
| 48 | GILLT_s64, |
| 49 | GILLT_v2s16, |
| 50 | GILLT_v2s32, |
| 51 | GILLT_v2s64, |
| 52 | GILLT_v3s32, |
| 53 | GILLT_v3s64, |
| 54 | GILLT_v4s16, |
| 55 | GILLT_v4s32, |
| 56 | GILLT_v4s64, |
| 57 | GILLT_v5s32, |
| 58 | GILLT_v6s32, |
| 59 | GILLT_v7s32, |
| 60 | GILLT_v8s16, |
| 61 | GILLT_v8s32, |
| 62 | GILLT_v8s64, |
| 63 | GILLT_v9s32, |
| 64 | GILLT_v10s32, |
| 65 | GILLT_v11s32, |
| 66 | GILLT_v12s32, |
| 67 | GILLT_v16s16, |
| 68 | GILLT_v16s32, |
| 69 | GILLT_v16s64, |
| 70 | GILLT_v32s16, |
| 71 | GILLT_v32s32, |
| 72 | }; |
| 73 | const static size_t NumTypeObjects = 34; |
| 74 | const static LLT TypeObjects[] = { |
| 75 | LLT::pointer(0, 64), |
| 76 | LLT::pointer(1, 64), |
| 77 | LLT::pointer(2, 32), |
| 78 | LLT::pointer(3, 32), |
| 79 | LLT::pointer(4, 64), |
| 80 | LLT::pointer(5, 32), |
| 81 | LLT::pointer(6, 32), |
| 82 | LLT::scalar(1), |
| 83 | LLT::scalar(16), |
| 84 | LLT::scalar(32), |
| 85 | LLT::scalar(64), |
| 86 | LLT::vector(ElementCount::getFixed(2), 16), |
| 87 | LLT::vector(ElementCount::getFixed(2), 32), |
| 88 | LLT::vector(ElementCount::getFixed(2), 64), |
| 89 | LLT::vector(ElementCount::getFixed(3), 32), |
| 90 | LLT::vector(ElementCount::getFixed(3), 64), |
| 91 | LLT::vector(ElementCount::getFixed(4), 16), |
| 92 | LLT::vector(ElementCount::getFixed(4), 32), |
| 93 | LLT::vector(ElementCount::getFixed(4), 64), |
| 94 | LLT::vector(ElementCount::getFixed(5), 32), |
| 95 | LLT::vector(ElementCount::getFixed(6), 32), |
| 96 | LLT::vector(ElementCount::getFixed(7), 32), |
| 97 | LLT::vector(ElementCount::getFixed(8), 16), |
| 98 | LLT::vector(ElementCount::getFixed(8), 32), |
| 99 | LLT::vector(ElementCount::getFixed(8), 64), |
| 100 | LLT::vector(ElementCount::getFixed(9), 32), |
| 101 | LLT::vector(ElementCount::getFixed(10), 32), |
| 102 | LLT::vector(ElementCount::getFixed(11), 32), |
| 103 | LLT::vector(ElementCount::getFixed(12), 32), |
| 104 | LLT::vector(ElementCount::getFixed(16), 16), |
| 105 | LLT::vector(ElementCount::getFixed(16), 32), |
| 106 | LLT::vector(ElementCount::getFixed(16), 64), |
| 107 | LLT::vector(ElementCount::getFixed(32), 16), |
| 108 | LLT::vector(ElementCount::getFixed(32), 32), |
| 109 | }; |
| 110 | |
| 111 | // Bits for subtarget features that participate in instruction matching. |
| 112 | enum SubtargetFeatureBits : uint8_t { |
| 113 | Feature_FalsePredicateBit = 101, |
| 114 | Feature_isGFX6Bit = 41, |
| 115 | Feature_isGFX6GFX7Bit = 8, |
| 116 | Feature_isGFX6GFX7GFX10Bit = 99, |
| 117 | Feature_isGFX7OnlyBit = 72, |
| 118 | Feature_isGFX7GFX8GFX9Bit = 36, |
| 119 | Feature_isGFX6GFX7GFX8GFX9Bit = 57, |
| 120 | Feature_isGFX6GFX7GFX8GFX9GFX10Bit = 112, |
| 121 | Feature_isNotGFX12PlusBit = 19, |
| 122 | Feature_isGFX8GFX9GFX10GFX11Bit = 20, |
| 123 | Feature_isGFX7PlusBit = 12, |
| 124 | Feature_isGFX8PlusBit = 4, |
| 125 | Feature_isGFX8OnlyBit = 21, |
| 126 | Feature_isGFX9PlusBit = 0, |
| 127 | Feature_isNotGFX9PlusBit = 47, |
| 128 | Feature_isGFX9OnlyBit = 50, |
| 129 | Feature_isGFX90APlusBit = 32, |
| 130 | Feature_isNotGFX90APlusBit = 22, |
| 131 | Feature_isGFX908orGFX90ABit = 31, |
| 132 | Feature_isGFX940PlusBit = 33, |
| 133 | Feature_isGFX8GFX9Bit = 15, |
| 134 | Feature_isGFX10OnlyBit = 53, |
| 135 | Feature_isGFX10PlusBit = 5, |
| 136 | Feature_isGFX9GFX10Bit = 48, |
| 137 | Feature_isGFX11OnlyBit = 54, |
| 138 | Feature_isGFX11PlusBit = 1, |
| 139 | Feature_isGFX12OnlyBit = 55, |
| 140 | Feature_isGFX12PlusBit = 3, |
| 141 | Feature_HasFlatAddressSpaceBit = 74, |
| 142 | Feature_HasFlatBufferGlobalAtomicFaddF64InstBit = 90, |
| 143 | Feature_HasAtomicFMinFMaxF32GlobalInstsBit = 84, |
| 144 | Feature_HasAtomicFMinFMaxF64GlobalInstsBit = 89, |
| 145 | Feature_HasAtomicFMinFMaxF32FlatInstsBit = 80, |
| 146 | Feature_HasAtomicFMinFMaxF64FlatInstsBit = 81, |
| 147 | Feature_HasLdsAtomicAddF64Bit = 115, |
| 148 | Feature_HasFlatGlobalInstsBit = 75, |
| 149 | Feature_HasFlatScratchInstsBit = 78, |
| 150 | Feature_HasD16LoadStoreBit = 83, |
| 151 | Feature_HasFlatScratchSVSModeBit = 79, |
| 152 | Feature_HasGFX10_BEncodingBit = 40, |
| 153 | Feature_HasUnpackedD16VMemBit = 95, |
| 154 | Feature_HasPackedD16VMemBit = 96, |
| 155 | Feature_HasUnrestrictedSOffsetBit = 94, |
| 156 | Feature_D16PreservesUnusedBitsBit = 76, |
| 157 | Feature_LDSRequiresM0InitBit = 108, |
| 158 | Feature_NotLDSRequiresM0InitBit = 109, |
| 159 | Feature_HasExportInstsBit = 7, |
| 160 | Feature_HasLDSFPAtomicAddF32Bit = 114, |
| 161 | Feature_HasAddNoCarryInstsBit = 56, |
| 162 | Feature_NotHasAddNoCarryInstsBit = 106, |
| 163 | Feature_HasXNACKEnabledBit = 71, |
| 164 | Feature_Has16BitInstsBit = 9, |
| 165 | Feature_HasTrue16BitInstsBit = 11, |
| 166 | Feature_NotHasTrue16BitInstsBit = 10, |
| 167 | Feature_UseRealTrue16InstsBit = 13, |
| 168 | Feature_UseFakeTrue16InstsBit = 14, |
| 169 | Feature_HasVOP3PInstsBit = 65, |
| 170 | Feature_HasMed3_16Bit = 107, |
| 171 | Feature_HasMinMaxDenormModesBit = 100, |
| 172 | Feature_NotHasMinMaxDenormModesBit = 102, |
| 173 | Feature_HasPackedFP32OpsBit = 34, |
| 174 | Feature_HasImageInstsBit = 6, |
| 175 | Feature_HasIntClampBit = 62, |
| 176 | Feature_HasMadMixInstsBit = 66, |
| 177 | Feature_HasScalarStoresBit = 37, |
| 178 | Feature_has16BankLDSBit = 42, |
| 179 | Feature_has32BankLDSBit = 23, |
| 180 | Feature_HasFmaMixInstsBit = 68, |
| 181 | Feature_HasDLInstsBit = 16, |
| 182 | Feature_HasFmacF64InstBit = 105, |
| 183 | Feature_HasDot1InstsBit = 29, |
| 184 | Feature_HasDot2InstsBit = 26, |
| 185 | Feature_HasDot3InstsBit = 61, |
| 186 | Feature_HasDot4InstsBit = 60, |
| 187 | Feature_HasDot5InstsBit = 58, |
| 188 | Feature_HasDot6InstsBit = 59, |
| 189 | Feature_HasDot7InstsBit = 28, |
| 190 | Feature_HasDot8InstsBit = 69, |
| 191 | Feature_HasDot9InstsBit = 24, |
| 192 | Feature_HasDot10InstsBit = 27, |
| 193 | Feature_HasDot11InstsBit = 70, |
| 194 | Feature_HasGetWaveIdInstBit = 39, |
| 195 | Feature_HasMAIInstsBit = 30, |
| 196 | Feature_HasSMemRealTimeBit = 38, |
| 197 | Feature_HasSMemTimeInstBit = 35, |
| 198 | Feature_HasShaderCyclesRegisterBit = 73, |
| 199 | Feature_HasShaderCyclesHiLoRegistersBit = 45, |
| 200 | Feature_HasFP8ConversionInstsBit = 52, |
| 201 | Feature_HasMadMacF32InstsBit = 17, |
| 202 | Feature_HasFmaLegacy32Bit = 18, |
| 203 | Feature_HasAtomicDsPkAdd16InstsBit = 113, |
| 204 | Feature_HasAtomicFlatPkAdd16InstsBit = 92, |
| 205 | Feature_HasAtomicFaddRtnInstsBit = 87, |
| 206 | Feature_HasAtomicFaddNoRtnInstsBit = 85, |
| 207 | Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit = 86, |
| 208 | Feature_HasAtomicBufferGlobalPkAddF16InstsBit = 88, |
| 209 | Feature_HasAtomicGlobalPkAddBF16InstBit = 93, |
| 210 | Feature_HasAtomicBufferPkAddBF16InstBit = 97, |
| 211 | Feature_HasFlatAtomicFaddF32InstBit = 91, |
| 212 | Feature_EnableLateCFGStructurizeBit = 46, |
| 213 | Feature_EnableFlatScratchBit = 77, |
| 214 | Feature_DisableFlatScratchBit = 98, |
| 215 | Feature_HasUnalignedAccessModeBit = 110, |
| 216 | Feature_HasMADIntraFwdBugBit = 64, |
| 217 | Feature_HasNotMADIntraFwdBugBit = 63, |
| 218 | Feature_HasSALUFloatInstsBit = 2, |
| 219 | Feature_HasPseudoScalarTransBit = 25, |
| 220 | Feature_HasGDSBit = 111, |
| 221 | Feature_HasCvtFP8VOP1BugBit = 49, |
| 222 | Feature_HasNoCvtFP8VOP1BugBit = 51, |
| 223 | Feature_HasAtomicCSubNoRtnInstsBit = 82, |
| 224 | Feature_FP16DenormalsBit = 104, |
| 225 | Feature_FP64DenormalsBit = 103, |
| 226 | Feature_NoFP32DenormalsBit = 67, |
| 227 | Feature_isWave32Bit = 43, |
| 228 | Feature_isWave64Bit = 44, |
| 229 | }; |
| 230 | |
| 231 | PredicateBitset AMDGPUInstructionSelector:: |
| 232 | computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const { |
| 233 | PredicateBitset Features{}; |
| 234 | if (false) |
| 235 | Features.set(Feature_FalsePredicateBit); |
| 236 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS) |
| 237 | Features.set(Feature_isGFX6Bit); |
| 238 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) |
| 239 | Features.set(Feature_isGFX6GFX7Bit); |
| 240 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10) |
| 241 | Features.set(Feature_isGFX6GFX7GFX10Bit); |
| 242 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS) |
| 243 | Features.set(Feature_isGFX7OnlyBit); |
| 244 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9) |
| 245 | Features.set(Feature_isGFX7GFX8GFX9Bit); |
| 246 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9) |
| 247 | Features.set(Feature_isGFX6GFX7GFX8GFX9Bit); |
| 248 | if (Subtarget->getGeneration() == AMDGPUSubtarget::SOUTHERN_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::SEA_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10) |
| 249 | Features.set(Feature_isGFX6GFX7GFX8GFX9GFX10Bit); |
| 250 | if (Subtarget->getGeneration() <= AMDGPUSubtarget::GFX11) |
| 251 | Features.set(Feature_isNotGFX12PlusBit); |
| 252 | if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX11) |
| 253 | Features.set(Feature_isGFX8GFX9GFX10GFX11Bit); |
| 254 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::SEA_ISLANDS) |
| 255 | Features.set(Feature_isGFX7PlusBit); |
| 256 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::VOLCANIC_ISLANDS) |
| 257 | Features.set(Feature_isGFX8PlusBit); |
| 258 | if (Subtarget->getGeneration() ==AMDGPUSubtarget::VOLCANIC_ISLANDS) |
| 259 | Features.set(Feature_isGFX8OnlyBit); |
| 260 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX9) |
| 261 | Features.set(Feature_isGFX9PlusBit); |
| 262 | if (Subtarget->getGeneration() < AMDGPUSubtarget::GFX9) |
| 263 | Features.set(Feature_isNotGFX9PlusBit); |
| 264 | if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX9) |
| 265 | Features.set(Feature_isGFX9OnlyBit); |
| 266 | if (Subtarget->hasGFX90AInsts()) |
| 267 | Features.set(Feature_isGFX90APlusBit); |
| 268 | if (!Subtarget->hasGFX90AInsts()) |
| 269 | Features.set(Feature_isNotGFX90APlusBit); |
| 270 | if (Subtarget->hasMAIInsts() && !Subtarget->hasGFX940Insts()) |
| 271 | Features.set(Feature_isGFX908orGFX90ABit); |
| 272 | if (Subtarget->hasGFX940Insts()) |
| 273 | Features.set(Feature_isGFX940PlusBit); |
| 274 | if (Subtarget->getGeneration() == AMDGPUSubtarget::VOLCANIC_ISLANDS ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX9) |
| 275 | Features.set(Feature_isGFX8GFX9Bit); |
| 276 | if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX10) |
| 277 | Features.set(Feature_isGFX10OnlyBit); |
| 278 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX10) |
| 279 | Features.set(Feature_isGFX10PlusBit); |
| 280 | if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX9 ||Subtarget->getGeneration() == AMDGPUSubtarget::GFX10) |
| 281 | Features.set(Feature_isGFX9GFX10Bit); |
| 282 | if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX11) |
| 283 | Features.set(Feature_isGFX11OnlyBit); |
| 284 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX11) |
| 285 | Features.set(Feature_isGFX11PlusBit); |
| 286 | if (Subtarget->getGeneration() == AMDGPUSubtarget::GFX12) |
| 287 | Features.set(Feature_isGFX12OnlyBit); |
| 288 | if (Subtarget->getGeneration() >= AMDGPUSubtarget::GFX12) |
| 289 | Features.set(Feature_isGFX12PlusBit); |
| 290 | if (Subtarget->hasFlatAddressSpace()) |
| 291 | Features.set(Feature_HasFlatAddressSpaceBit); |
| 292 | if (Subtarget->hasFlatBufferGlobalAtomicFaddF64Inst()) |
| 293 | Features.set(Feature_HasFlatBufferGlobalAtomicFaddF64InstBit); |
| 294 | if (Subtarget->hasAtomicFMinFMaxF32GlobalInsts()) |
| 295 | Features.set(Feature_HasAtomicFMinFMaxF32GlobalInstsBit); |
| 296 | if (Subtarget->hasAtomicFMinFMaxF64GlobalInsts()) |
| 297 | Features.set(Feature_HasAtomicFMinFMaxF64GlobalInstsBit); |
| 298 | if (Subtarget->hasAtomicFMinFMaxF32FlatInsts()) |
| 299 | Features.set(Feature_HasAtomicFMinFMaxF32FlatInstsBit); |
| 300 | if (Subtarget->hasAtomicFMinFMaxF64FlatInsts()) |
| 301 | Features.set(Feature_HasAtomicFMinFMaxF64FlatInstsBit); |
| 302 | if (Subtarget->hasLdsAtomicAddF64()) |
| 303 | Features.set(Feature_HasLdsAtomicAddF64Bit); |
| 304 | if (Subtarget->hasFlatGlobalInsts()) |
| 305 | Features.set(Feature_HasFlatGlobalInstsBit); |
| 306 | if (Subtarget->hasFlatScratchInsts()) |
| 307 | Features.set(Feature_HasFlatScratchInstsBit); |
| 308 | if (Subtarget->hasD16LoadStore()) |
| 309 | Features.set(Feature_HasD16LoadStoreBit); |
| 310 | if (Subtarget->hasFlatScratchSVSMode()) |
| 311 | Features.set(Feature_HasFlatScratchSVSModeBit); |
| 312 | if (Subtarget->hasGFX10_BEncoding()) |
| 313 | Features.set(Feature_HasGFX10_BEncodingBit); |
| 314 | if (Subtarget->hasUnpackedD16VMem()) |
| 315 | Features.set(Feature_HasUnpackedD16VMemBit); |
| 316 | if (!Subtarget->hasUnpackedD16VMem()) |
| 317 | Features.set(Feature_HasPackedD16VMemBit); |
| 318 | if (!Subtarget->hasRestrictedSOffset()) |
| 319 | Features.set(Feature_HasUnrestrictedSOffsetBit); |
| 320 | if (Subtarget->d16PreservesUnusedBits()) |
| 321 | Features.set(Feature_D16PreservesUnusedBitsBit); |
| 322 | if (Subtarget->ldsRequiresM0Init()) |
| 323 | Features.set(Feature_LDSRequiresM0InitBit); |
| 324 | if (!Subtarget->ldsRequiresM0Init()) |
| 325 | Features.set(Feature_NotLDSRequiresM0InitBit); |
| 326 | if (Subtarget->hasExportInsts()) |
| 327 | Features.set(Feature_HasExportInstsBit); |
| 328 | if (Subtarget->hasLDSFPAtomicAddF32()) |
| 329 | Features.set(Feature_HasLDSFPAtomicAddF32Bit); |
| 330 | if (Subtarget->hasAddNoCarry()) |
| 331 | Features.set(Feature_HasAddNoCarryInstsBit); |
| 332 | if (!Subtarget->hasAddNoCarry()) |
| 333 | Features.set(Feature_NotHasAddNoCarryInstsBit); |
| 334 | if (Subtarget->isXNACKEnabled()) |
| 335 | Features.set(Feature_HasXNACKEnabledBit); |
| 336 | if (Subtarget->has16BitInsts()) |
| 337 | Features.set(Feature_Has16BitInstsBit); |
| 338 | if (Subtarget->hasTrue16BitInsts()) |
| 339 | Features.set(Feature_HasTrue16BitInstsBit); |
| 340 | if (!Subtarget->hasTrue16BitInsts()) |
| 341 | Features.set(Feature_NotHasTrue16BitInstsBit); |
| 342 | if (Subtarget->useRealTrue16Insts()) |
| 343 | Features.set(Feature_UseRealTrue16InstsBit); |
| 344 | if (Subtarget->hasTrue16BitInsts() && !Subtarget->useRealTrue16Insts()) |
| 345 | Features.set(Feature_UseFakeTrue16InstsBit); |
| 346 | if (Subtarget->hasVOP3PInsts()) |
| 347 | Features.set(Feature_HasVOP3PInstsBit); |
| 348 | if (Subtarget->hasMed3_16()) |
| 349 | Features.set(Feature_HasMed3_16Bit); |
| 350 | if (Subtarget->supportsMinMaxDenormModes()) |
| 351 | Features.set(Feature_HasMinMaxDenormModesBit); |
| 352 | if (!Subtarget->supportsMinMaxDenormModes()) |
| 353 | Features.set(Feature_NotHasMinMaxDenormModesBit); |
| 354 | if (Subtarget->hasPackedFP32Ops()) |
| 355 | Features.set(Feature_HasPackedFP32OpsBit); |
| 356 | if (Subtarget->hasImageInsts()) |
| 357 | Features.set(Feature_HasImageInstsBit); |
| 358 | if (Subtarget->hasIntClamp()) |
| 359 | Features.set(Feature_HasIntClampBit); |
| 360 | if (Subtarget->hasMadMixInsts()) |
| 361 | Features.set(Feature_HasMadMixInstsBit); |
| 362 | if (Subtarget->hasScalarStores()) |
| 363 | Features.set(Feature_HasScalarStoresBit); |
| 364 | if (Subtarget->getLDSBankCount() == 16) |
| 365 | Features.set(Feature_has16BankLDSBit); |
| 366 | if (Subtarget->getLDSBankCount() == 32) |
| 367 | Features.set(Feature_has32BankLDSBit); |
| 368 | if (Subtarget->hasFmaMixInsts()) |
| 369 | Features.set(Feature_HasFmaMixInstsBit); |
| 370 | if (Subtarget->hasDLInsts()) |
| 371 | Features.set(Feature_HasDLInstsBit); |
| 372 | if (Subtarget->hasFmacF64Inst()) |
| 373 | Features.set(Feature_HasFmacF64InstBit); |
| 374 | if (Subtarget->hasDot1Insts()) |
| 375 | Features.set(Feature_HasDot1InstsBit); |
| 376 | if (Subtarget->hasDot2Insts()) |
| 377 | Features.set(Feature_HasDot2InstsBit); |
| 378 | if (Subtarget->hasDot3Insts()) |
| 379 | Features.set(Feature_HasDot3InstsBit); |
| 380 | if (Subtarget->hasDot4Insts()) |
| 381 | Features.set(Feature_HasDot4InstsBit); |
| 382 | if (Subtarget->hasDot5Insts()) |
| 383 | Features.set(Feature_HasDot5InstsBit); |
| 384 | if (Subtarget->hasDot6Insts()) |
| 385 | Features.set(Feature_HasDot6InstsBit); |
| 386 | if (Subtarget->hasDot7Insts()) |
| 387 | Features.set(Feature_HasDot7InstsBit); |
| 388 | if (Subtarget->hasDot8Insts()) |
| 389 | Features.set(Feature_HasDot8InstsBit); |
| 390 | if (Subtarget->hasDot9Insts()) |
| 391 | Features.set(Feature_HasDot9InstsBit); |
| 392 | if (Subtarget->hasDot10Insts()) |
| 393 | Features.set(Feature_HasDot10InstsBit); |
| 394 | if (Subtarget->hasDot11Insts()) |
| 395 | Features.set(Feature_HasDot11InstsBit); |
| 396 | if (Subtarget->hasGetWaveIdInst()) |
| 397 | Features.set(Feature_HasGetWaveIdInstBit); |
| 398 | if (Subtarget->hasMAIInsts()) |
| 399 | Features.set(Feature_HasMAIInstsBit); |
| 400 | if (Subtarget->hasSMemRealTime()) |
| 401 | Features.set(Feature_HasSMemRealTimeBit); |
| 402 | if (Subtarget->hasSMemTimeInst()) |
| 403 | Features.set(Feature_HasSMemTimeInstBit); |
| 404 | if (Subtarget->hasShaderCyclesRegister()) |
| 405 | Features.set(Feature_HasShaderCyclesRegisterBit); |
| 406 | if (Subtarget->hasShaderCyclesHiLoRegisters()) |
| 407 | Features.set(Feature_HasShaderCyclesHiLoRegistersBit); |
| 408 | if (Subtarget->hasFP8ConversionInsts()) |
| 409 | Features.set(Feature_HasFP8ConversionInstsBit); |
| 410 | if (Subtarget->hasMadMacF32Insts()) |
| 411 | Features.set(Feature_HasMadMacF32InstsBit); |
| 412 | if (Subtarget->hasGFX10_3Insts()) |
| 413 | Features.set(Feature_HasFmaLegacy32Bit); |
| 414 | if (Subtarget->hasAtomicDsPkAdd16Insts()) |
| 415 | Features.set(Feature_HasAtomicDsPkAdd16InstsBit); |
| 416 | if (Subtarget->hasAtomicFlatPkAdd16Insts()) |
| 417 | Features.set(Feature_HasAtomicFlatPkAdd16InstsBit); |
| 418 | if (Subtarget->hasAtomicFaddRtnInsts()) |
| 419 | Features.set(Feature_HasAtomicFaddRtnInstsBit); |
| 420 | if (Subtarget->hasAtomicFaddNoRtnInsts()) |
| 421 | Features.set(Feature_HasAtomicFaddNoRtnInstsBit); |
| 422 | if (Subtarget->hasAtomicBufferGlobalPkAddF16NoRtnInsts() || Subtarget->hasAtomicBufferGlobalPkAddF16Insts()) |
| 423 | Features.set(Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit); |
| 424 | if (Subtarget->hasAtomicBufferGlobalPkAddF16Insts()) |
| 425 | Features.set(Feature_HasAtomicBufferGlobalPkAddF16InstsBit); |
| 426 | if (Subtarget->hasAtomicGlobalPkAddBF16Inst()) |
| 427 | Features.set(Feature_HasAtomicGlobalPkAddBF16InstBit); |
| 428 | if (Subtarget->hasAtomicBufferPkAddBF16Inst()) |
| 429 | Features.set(Feature_HasAtomicBufferPkAddBF16InstBit); |
| 430 | if (Subtarget->hasFlatAtomicFaddF32Inst()) |
| 431 | Features.set(Feature_HasFlatAtomicFaddF32InstBit); |
| 432 | if (EnableLateStructurizeCFG) |
| 433 | Features.set(Feature_EnableLateCFGStructurizeBit); |
| 434 | if (Subtarget->enableFlatScratch()) |
| 435 | Features.set(Feature_EnableFlatScratchBit); |
| 436 | if (!Subtarget->enableFlatScratch()) |
| 437 | Features.set(Feature_DisableFlatScratchBit); |
| 438 | if (Subtarget->hasUnalignedAccessMode()) |
| 439 | Features.set(Feature_HasUnalignedAccessModeBit); |
| 440 | if (Subtarget->hasMADIntraFwdBug()) |
| 441 | Features.set(Feature_HasMADIntraFwdBugBit); |
| 442 | if (!Subtarget->hasMADIntraFwdBug()) |
| 443 | Features.set(Feature_HasNotMADIntraFwdBugBit); |
| 444 | if (Subtarget->hasSALUFloatInsts()) |
| 445 | Features.set(Feature_HasSALUFloatInstsBit); |
| 446 | if (Subtarget->hasPseudoScalarTrans()) |
| 447 | Features.set(Feature_HasPseudoScalarTransBit); |
| 448 | if (Subtarget->hasGDS()) |
| 449 | Features.set(Feature_HasGDSBit); |
| 450 | if (Subtarget->hasCvtFP8VOP1Bug()) |
| 451 | Features.set(Feature_HasCvtFP8VOP1BugBit); |
| 452 | if (!Subtarget->hasCvtFP8VOP1Bug()) |
| 453 | Features.set(Feature_HasNoCvtFP8VOP1BugBit); |
| 454 | if (Subtarget->hasAtomicCSubNoRtnInsts()) |
| 455 | Features.set(Feature_HasAtomicCSubNoRtnInstsBit); |
| 456 | if (Subtarget->getWavefrontSize() == 32) |
| 457 | Features.set(Feature_isWave32Bit); |
| 458 | if (Subtarget->getWavefrontSize() == 64) |
| 459 | Features.set(Feature_isWave64Bit); |
| 460 | return Features; |
| 461 | } |
| 462 | |
| 463 | void AMDGPUInstructionSelector::setupGeneratedPerFunctionState(MachineFunction &MF) { |
| 464 | AvailableFunctionFeatures = computeAvailableFunctionFeatures((const AMDGPUSubtarget *)&MF.getSubtarget(), &MF); |
| 465 | } |
| 466 | PredicateBitset AMDGPUInstructionSelector:: |
| 467 | computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, const MachineFunction *MF) const { |
| 468 | PredicateBitset Features{}; |
| 469 | if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign()) |
| 470 | Features.set(Feature_FP16DenormalsBit); |
| 471 | if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP64FP16Denormals != DenormalMode::getPreserveSign()) |
| 472 | Features.set(Feature_FP64DenormalsBit); |
| 473 | if (MF->getInfo<SIMachineFunctionInfo>()->getMode().FP32Denormals == DenormalMode::getPreserveSign()) |
| 474 | Features.set(Feature_NoFP32DenormalsBit); |
| 475 | return Features; |
| 476 | } |
| 477 | |
| 478 | // Feature bitsets. |
| 479 | enum { |
| 480 | GIFBS_Invalid, |
| 481 | GIFBS_DisableFlatScratch, |
| 482 | GIFBS_EnableLateCFGStructurize, |
| 483 | GIFBS_Has16BitInsts, |
| 484 | GIFBS_HasAddNoCarryInsts, |
| 485 | GIFBS_HasAtomicBufferGlobalPkAddF16Insts, |
| 486 | GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts, |
| 487 | GIFBS_HasAtomicBufferPkAddBF16Inst, |
| 488 | GIFBS_HasAtomicCSubNoRtnInsts, |
| 489 | GIFBS_HasAtomicFMinFMaxF32GlobalInsts, |
| 490 | GIFBS_HasAtomicFMinFMaxF64GlobalInsts, |
| 491 | GIFBS_HasAtomicFaddNoRtnInsts, |
| 492 | GIFBS_HasAtomicFaddRtnInsts, |
| 493 | GIFBS_HasAtomicFlatPkAdd16Insts, |
| 494 | GIFBS_HasAtomicGlobalPkAddBF16Inst, |
| 495 | GIFBS_HasD16LoadStore, |
| 496 | GIFBS_HasDLInsts, |
| 497 | GIFBS_HasDot10Insts, |
| 498 | GIFBS_HasDot1Insts, |
| 499 | GIFBS_HasDot2Insts, |
| 500 | GIFBS_HasDot3Insts, |
| 501 | GIFBS_HasDot4Insts, |
| 502 | GIFBS_HasDot5Insts, |
| 503 | GIFBS_HasDot6Insts, |
| 504 | GIFBS_HasDot7Insts, |
| 505 | GIFBS_HasDot8Insts, |
| 506 | GIFBS_HasDot9Insts, |
| 507 | GIFBS_HasFlatAddressSpace, |
| 508 | GIFBS_HasFlatAtomicFaddF32Inst, |
| 509 | GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst, |
| 510 | GIFBS_HasFlatGlobalInsts, |
| 511 | GIFBS_HasFmaLegacy32, |
| 512 | GIFBS_HasFmaMixInsts, |
| 513 | GIFBS_HasFmacF64Inst, |
| 514 | GIFBS_HasGDS, |
| 515 | GIFBS_HasGFX10_BEncoding, |
| 516 | GIFBS_HasGetWaveIdInst, |
| 517 | GIFBS_HasIntClamp, |
| 518 | GIFBS_HasLdsAtomicAddF64, |
| 519 | GIFBS_HasMAIInsts, |
| 520 | GIFBS_HasMadMacF32Insts, |
| 521 | GIFBS_HasMed3_16, |
| 522 | GIFBS_HasMinMaxDenormModes, |
| 523 | GIFBS_HasPackedD16VMem, |
| 524 | GIFBS_HasPackedFP32Ops, |
| 525 | GIFBS_HasPseudoScalarTrans, |
| 526 | GIFBS_HasSALUFloatInsts, |
| 527 | GIFBS_HasSMemRealTime, |
| 528 | GIFBS_HasSMemTimeInst, |
| 529 | GIFBS_HasShaderCyclesHiLoRegisters, |
| 530 | GIFBS_HasShaderCyclesRegister, |
| 531 | GIFBS_HasTrue16BitInsts, |
| 532 | GIFBS_HasUnpackedD16VMem, |
| 533 | GIFBS_HasUnrestrictedSOffset, |
| 534 | GIFBS_HasVOP3PInsts, |
| 535 | GIFBS_HasXNACKEnabled, |
| 536 | GIFBS_LDSRequiresM0Init, |
| 537 | GIFBS_NotHasAddNoCarryInsts, |
| 538 | GIFBS_NotHasTrue16BitInsts, |
| 539 | GIFBS_NotLDSRequiresM0Init, |
| 540 | GIFBS_UseFakeTrue16Insts, |
| 541 | GIFBS_UseRealTrue16Insts, |
| 542 | GIFBS_isGFX10Only, |
| 543 | GIFBS_isGFX10Plus, |
| 544 | GIFBS_isGFX11Only, |
| 545 | GIFBS_isGFX11Plus, |
| 546 | GIFBS_isGFX12Only, |
| 547 | GIFBS_isGFX12Plus, |
| 548 | GIFBS_isGFX6, |
| 549 | GIFBS_isGFX6GFX7, |
| 550 | GIFBS_isGFX6GFX7GFX8GFX9, |
| 551 | GIFBS_isGFX7GFX8GFX9, |
| 552 | GIFBS_isGFX7Only, |
| 553 | GIFBS_isGFX7Plus, |
| 554 | GIFBS_isGFX8GFX9, |
| 555 | GIFBS_isGFX8GFX9GFX10GFX11, |
| 556 | GIFBS_isGFX8Plus, |
| 557 | GIFBS_isGFX908orGFX90A, |
| 558 | GIFBS_isGFX90APlus, |
| 559 | GIFBS_isGFX940Plus, |
| 560 | GIFBS_isGFX9GFX10, |
| 561 | GIFBS_isGFX9Only, |
| 562 | GIFBS_isGFX9Plus, |
| 563 | GIFBS_isNotGFX12Plus, |
| 564 | GIFBS_isNotGFX90APlus, |
| 565 | GIFBS_isNotGFX9Plus, |
| 566 | GIFBS_isWave32, |
| 567 | GIFBS_isWave64, |
| 568 | GIFBS_DisableFlatScratch_HasD16LoadStore, |
| 569 | GIFBS_DisableFlatScratch_HasUnrestrictedSOffset, |
| 570 | GIFBS_EnableFlatScratch_HasFlatScratchInsts, |
| 571 | GIFBS_FP16Denormals_NotHasMinMaxDenormModes, |
| 572 | GIFBS_FalsePredicate_NotHasMinMaxDenormModes, |
| 573 | GIFBS_Has16BitInsts_HasIntClamp, |
| 574 | GIFBS_Has16BitInsts_HasTrue16BitInsts, |
| 575 | GIFBS_Has16BitInsts_NotHasTrue16BitInsts, |
| 576 | GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9, |
| 577 | GIFBS_Has16BitInsts_isGFX8GFX9, |
| 578 | GIFBS_Has16BitInsts_isGFX8Only, |
| 579 | GIFBS_Has16BitInsts_isNotGFX90APlus, |
| 580 | GIFBS_HasAddNoCarryInsts_HasIntClamp, |
| 581 | GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset, |
| 582 | GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset, |
| 583 | GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset, |
| 584 | GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus, |
| 585 | GIFBS_HasAtomicDsPkAdd16Insts_HasGDS, |
| 586 | GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init, |
| 587 | GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init, |
| 588 | GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace, |
| 589 | GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts, |
| 590 | GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts, |
| 591 | GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset, |
| 592 | GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace, |
| 593 | GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGlobalInsts, |
| 594 | GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts, |
| 595 | GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset, |
| 596 | GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset, |
| 597 | GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset, |
| 598 | GIFBS_HasCvtFP8VOP1Bug_isGFX9Only, |
| 599 | GIFBS_HasDot11Insts_isGFX12Plus, |
| 600 | GIFBS_HasExportInsts_isGFX12Plus, |
| 601 | GIFBS_HasFP8ConversionInsts_isGFX12Plus, |
| 602 | GIFBS_HasFP8ConversionInsts_isGFX940Plus, |
| 603 | GIFBS_HasFP8ConversionInsts_isGFX9Plus, |
| 604 | GIFBS_HasFlatAddressSpace_isGFX12Plus, |
| 605 | GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset, |
| 606 | GIFBS_HasFlatGlobalInsts_isGFX12Plus, |
| 607 | GIFBS_HasGDS_HasLDSFPAtomicAddF32, |
| 608 | GIFBS_HasGDS_isGFX11Plus, |
| 609 | GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10, |
| 610 | GIFBS_HasImageInsts_isGFX12Plus, |
| 611 | GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init, |
| 612 | GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init, |
| 613 | GIFBS_HasMADIntraFwdBug_isGFX11Only, |
| 614 | GIFBS_HasMadMacF32Insts_NoFP32Denormals, |
| 615 | GIFBS_HasMadMixInsts_NoFP32Denormals, |
| 616 | GIFBS_HasMinMaxDenormModes_isGFX12Plus, |
| 617 | GIFBS_HasMinMaxDenormModes_isNotGFX12Plus, |
| 618 | GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only, |
| 619 | GIFBS_HasNotMADIntraFwdBug_isGFX9Plus, |
| 620 | GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset, |
| 621 | GIFBS_HasScalarStores_isGFX8Plus, |
| 622 | GIFBS_HasTrue16BitInsts_isGFX10Plus, |
| 623 | GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init, |
| 624 | GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init, |
| 625 | GIFBS_HasXNACKEnabled_isGFX7Only, |
| 626 | GIFBS_HasXNACKEnabled_isGFX9Plus, |
| 627 | GIFBS_HasXNACKEnabled_isNotGFX9Plus, |
| 628 | GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10, |
| 629 | GIFBS_LDSRequiresM0Init_isGFX7Plus, |
| 630 | GIFBS_NotHasTrue16BitInsts_isGFX10Plus, |
| 631 | GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10, |
| 632 | GIFBS_NotLDSRequiresM0Init_isGFX7Plus, |
| 633 | GIFBS_has16BankLDS_isNotGFX90APlus, |
| 634 | GIFBS_has32BankLDS_isNotGFX90APlus, |
| 635 | GIFBS_isGFX11Only_isWave32, |
| 636 | GIFBS_isGFX11Only_isWave64, |
| 637 | GIFBS_isGFX12Plus_isWave32, |
| 638 | GIFBS_isGFX12Plus_isWave64, |
| 639 | GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset, |
| 640 | GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts, |
| 641 | GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode, |
| 642 | GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus, |
| 643 | GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus, |
| 644 | GIFBS_Has16BitInsts_HasMinMaxDenormModes_HasTrue16BitInsts, |
| 645 | GIFBS_Has16BitInsts_HasMinMaxDenormModes_NotHasTrue16BitInsts, |
| 646 | GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus, |
| 647 | GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10, |
| 648 | GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode, |
| 649 | GIFBS_FP16Denormals_Has16BitInsts_HasTrue16BitInsts_NotHasMinMaxDenormModes, |
| 650 | GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_NotHasTrue16BitInsts, |
| 651 | }; |
| 652 | constexpr static PredicateBitset FeatureBitsets[] { |
| 653 | {}, // GIFBS_Invalid |
| 654 | {Feature_DisableFlatScratchBit, }, |
| 655 | {Feature_EnableLateCFGStructurizeBit, }, |
| 656 | {Feature_Has16BitInstsBit, }, |
| 657 | {Feature_HasAddNoCarryInstsBit, }, |
| 658 | {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, }, |
| 659 | {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, }, |
| 660 | {Feature_HasAtomicBufferPkAddBF16InstBit, }, |
| 661 | {Feature_HasAtomicCSubNoRtnInstsBit, }, |
| 662 | {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, }, |
| 663 | {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, }, |
| 664 | {Feature_HasAtomicFaddNoRtnInstsBit, }, |
| 665 | {Feature_HasAtomicFaddRtnInstsBit, }, |
| 666 | {Feature_HasAtomicFlatPkAdd16InstsBit, }, |
| 667 | {Feature_HasAtomicGlobalPkAddBF16InstBit, }, |
| 668 | {Feature_HasD16LoadStoreBit, }, |
| 669 | {Feature_HasDLInstsBit, }, |
| 670 | {Feature_HasDot10InstsBit, }, |
| 671 | {Feature_HasDot1InstsBit, }, |
| 672 | {Feature_HasDot2InstsBit, }, |
| 673 | {Feature_HasDot3InstsBit, }, |
| 674 | {Feature_HasDot4InstsBit, }, |
| 675 | {Feature_HasDot5InstsBit, }, |
| 676 | {Feature_HasDot6InstsBit, }, |
| 677 | {Feature_HasDot7InstsBit, }, |
| 678 | {Feature_HasDot8InstsBit, }, |
| 679 | {Feature_HasDot9InstsBit, }, |
| 680 | {Feature_HasFlatAddressSpaceBit, }, |
| 681 | {Feature_HasFlatAtomicFaddF32InstBit, }, |
| 682 | {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, }, |
| 683 | {Feature_HasFlatGlobalInstsBit, }, |
| 684 | {Feature_HasFmaLegacy32Bit, }, |
| 685 | {Feature_HasFmaMixInstsBit, }, |
| 686 | {Feature_HasFmacF64InstBit, }, |
| 687 | {Feature_HasGDSBit, }, |
| 688 | {Feature_HasGFX10_BEncodingBit, }, |
| 689 | {Feature_HasGetWaveIdInstBit, }, |
| 690 | {Feature_HasIntClampBit, }, |
| 691 | {Feature_HasLdsAtomicAddF64Bit, }, |
| 692 | {Feature_HasMAIInstsBit, }, |
| 693 | {Feature_HasMadMacF32InstsBit, }, |
| 694 | {Feature_HasMed3_16Bit, }, |
| 695 | {Feature_HasMinMaxDenormModesBit, }, |
| 696 | {Feature_HasPackedD16VMemBit, }, |
| 697 | {Feature_HasPackedFP32OpsBit, }, |
| 698 | {Feature_HasPseudoScalarTransBit, }, |
| 699 | {Feature_HasSALUFloatInstsBit, }, |
| 700 | {Feature_HasSMemRealTimeBit, }, |
| 701 | {Feature_HasSMemTimeInstBit, }, |
| 702 | {Feature_HasShaderCyclesHiLoRegistersBit, }, |
| 703 | {Feature_HasShaderCyclesRegisterBit, }, |
| 704 | {Feature_HasTrue16BitInstsBit, }, |
| 705 | {Feature_HasUnpackedD16VMemBit, }, |
| 706 | {Feature_HasUnrestrictedSOffsetBit, }, |
| 707 | {Feature_HasVOP3PInstsBit, }, |
| 708 | {Feature_HasXNACKEnabledBit, }, |
| 709 | {Feature_LDSRequiresM0InitBit, }, |
| 710 | {Feature_NotHasAddNoCarryInstsBit, }, |
| 711 | {Feature_NotHasTrue16BitInstsBit, }, |
| 712 | {Feature_NotLDSRequiresM0InitBit, }, |
| 713 | {Feature_UseFakeTrue16InstsBit, }, |
| 714 | {Feature_UseRealTrue16InstsBit, }, |
| 715 | {Feature_isGFX10OnlyBit, }, |
| 716 | {Feature_isGFX10PlusBit, }, |
| 717 | {Feature_isGFX11OnlyBit, }, |
| 718 | {Feature_isGFX11PlusBit, }, |
| 719 | {Feature_isGFX12OnlyBit, }, |
| 720 | {Feature_isGFX12PlusBit, }, |
| 721 | {Feature_isGFX6Bit, }, |
| 722 | {Feature_isGFX6GFX7Bit, }, |
| 723 | {Feature_isGFX6GFX7GFX8GFX9Bit, }, |
| 724 | {Feature_isGFX7GFX8GFX9Bit, }, |
| 725 | {Feature_isGFX7OnlyBit, }, |
| 726 | {Feature_isGFX7PlusBit, }, |
| 727 | {Feature_isGFX8GFX9Bit, }, |
| 728 | {Feature_isGFX8GFX9GFX10GFX11Bit, }, |
| 729 | {Feature_isGFX8PlusBit, }, |
| 730 | {Feature_isGFX908orGFX90ABit, }, |
| 731 | {Feature_isGFX90APlusBit, }, |
| 732 | {Feature_isGFX940PlusBit, }, |
| 733 | {Feature_isGFX9GFX10Bit, }, |
| 734 | {Feature_isGFX9OnlyBit, }, |
| 735 | {Feature_isGFX9PlusBit, }, |
| 736 | {Feature_isNotGFX12PlusBit, }, |
| 737 | {Feature_isNotGFX90APlusBit, }, |
| 738 | {Feature_isNotGFX9PlusBit, }, |
| 739 | {Feature_isWave32Bit, }, |
| 740 | {Feature_isWave64Bit, }, |
| 741 | {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, }, |
| 742 | {Feature_DisableFlatScratchBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 743 | {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, }, |
| 744 | {Feature_FP16DenormalsBit, Feature_NotHasMinMaxDenormModesBit, }, |
| 745 | {Feature_FalsePredicateBit, Feature_NotHasMinMaxDenormModesBit, }, |
| 746 | {Feature_Has16BitInstsBit, Feature_HasIntClampBit, }, |
| 747 | {Feature_Has16BitInstsBit, Feature_HasTrue16BitInstsBit, }, |
| 748 | {Feature_Has16BitInstsBit, Feature_NotHasTrue16BitInstsBit, }, |
| 749 | {Feature_Has16BitInstsBit, Feature_isGFX6GFX7GFX8GFX9Bit, }, |
| 750 | {Feature_Has16BitInstsBit, Feature_isGFX8GFX9Bit, }, |
| 751 | {Feature_Has16BitInstsBit, Feature_isGFX8OnlyBit, }, |
| 752 | {Feature_Has16BitInstsBit, Feature_isNotGFX90APlusBit, }, |
| 753 | {Feature_HasAddNoCarryInstsBit, Feature_HasIntClampBit, }, |
| 754 | {Feature_HasAtomicBufferGlobalPkAddF16InstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 755 | {Feature_HasAtomicBufferGlobalPkAddF16NoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 756 | {Feature_HasAtomicBufferPkAddBF16InstBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 757 | {Feature_HasAtomicCSubNoRtnInstsBit, Feature_isGFX12PlusBit, }, |
| 758 | {Feature_HasAtomicDsPkAdd16InstsBit, Feature_HasGDSBit, }, |
| 759 | {Feature_HasAtomicDsPkAdd16InstsBit, Feature_LDSRequiresM0InitBit, }, |
| 760 | {Feature_HasAtomicDsPkAdd16InstsBit, Feature_NotLDSRequiresM0InitBit, }, |
| 761 | {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatAddressSpaceBit, }, |
| 762 | {Feature_HasAtomicFMinFMaxF32FlatInstsBit, Feature_HasFlatGlobalInstsBit, }, |
| 763 | {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasFlatGlobalInstsBit, }, |
| 764 | {Feature_HasAtomicFMinFMaxF32GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 765 | {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatAddressSpaceBit, }, |
| 766 | {Feature_HasAtomicFMinFMaxF64FlatInstsBit, Feature_HasFlatGlobalInstsBit, }, |
| 767 | {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasFlatGlobalInstsBit, }, |
| 768 | {Feature_HasAtomicFMinFMaxF64GlobalInstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 769 | {Feature_HasAtomicFaddNoRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 770 | {Feature_HasAtomicFaddRtnInstsBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 771 | {Feature_HasCvtFP8VOP1BugBit, Feature_isGFX9OnlyBit, }, |
| 772 | {Feature_HasDot11InstsBit, Feature_isGFX12PlusBit, }, |
| 773 | {Feature_HasExportInstsBit, Feature_isGFX12PlusBit, }, |
| 774 | {Feature_HasFP8ConversionInstsBit, Feature_isGFX12PlusBit, }, |
| 775 | {Feature_HasFP8ConversionInstsBit, Feature_isGFX940PlusBit, }, |
| 776 | {Feature_HasFP8ConversionInstsBit, Feature_isGFX9PlusBit, }, |
| 777 | {Feature_HasFlatAddressSpaceBit, Feature_isGFX12PlusBit, }, |
| 778 | {Feature_HasFlatBufferGlobalAtomicFaddF64InstBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 779 | {Feature_HasFlatGlobalInstsBit, Feature_isGFX12PlusBit, }, |
| 780 | {Feature_HasGDSBit, Feature_HasLDSFPAtomicAddF32Bit, }, |
| 781 | {Feature_HasGDSBit, Feature_isGFX11PlusBit, }, |
| 782 | {Feature_HasGDSBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, }, |
| 783 | {Feature_HasImageInstsBit, Feature_isGFX12PlusBit, }, |
| 784 | {Feature_HasLDSFPAtomicAddF32Bit, Feature_LDSRequiresM0InitBit, }, |
| 785 | {Feature_HasLDSFPAtomicAddF32Bit, Feature_NotLDSRequiresM0InitBit, }, |
| 786 | {Feature_HasMADIntraFwdBugBit, Feature_isGFX11OnlyBit, }, |
| 787 | {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, }, |
| 788 | {Feature_HasMadMixInstsBit, Feature_NoFP32DenormalsBit, }, |
| 789 | {Feature_HasMinMaxDenormModesBit, Feature_isGFX12PlusBit, }, |
| 790 | {Feature_HasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, }, |
| 791 | {Feature_HasNoCvtFP8VOP1BugBit, Feature_isGFX9OnlyBit, }, |
| 792 | {Feature_HasNotMADIntraFwdBugBit, Feature_isGFX9PlusBit, }, |
| 793 | {Feature_HasPackedD16VMemBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 794 | {Feature_HasScalarStoresBit, Feature_isGFX8PlusBit, }, |
| 795 | {Feature_HasTrue16BitInstsBit, Feature_isGFX10PlusBit, }, |
| 796 | {Feature_HasUnalignedAccessModeBit, Feature_LDSRequiresM0InitBit, }, |
| 797 | {Feature_HasUnalignedAccessModeBit, Feature_NotLDSRequiresM0InitBit, }, |
| 798 | {Feature_HasXNACKEnabledBit, Feature_isGFX7OnlyBit, }, |
| 799 | {Feature_HasXNACKEnabledBit, Feature_isGFX9PlusBit, }, |
| 800 | {Feature_HasXNACKEnabledBit, Feature_isNotGFX9PlusBit, }, |
| 801 | {Feature_LDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, }, |
| 802 | {Feature_LDSRequiresM0InitBit, Feature_isGFX7PlusBit, }, |
| 803 | {Feature_NotHasTrue16BitInstsBit, Feature_isGFX10PlusBit, }, |
| 804 | {Feature_NotLDSRequiresM0InitBit, Feature_isGFX6GFX7GFX8GFX9GFX10Bit, }, |
| 805 | {Feature_NotLDSRequiresM0InitBit, Feature_isGFX7PlusBit, }, |
| 806 | {Feature_has16BankLDSBit, Feature_isNotGFX90APlusBit, }, |
| 807 | {Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, }, |
| 808 | {Feature_isGFX11OnlyBit, Feature_isWave32Bit, }, |
| 809 | {Feature_isGFX11OnlyBit, Feature_isWave64Bit, }, |
| 810 | {Feature_isGFX12PlusBit, Feature_isWave32Bit, }, |
| 811 | {Feature_isGFX12PlusBit, Feature_isWave64Bit, }, |
| 812 | {Feature_DisableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasUnrestrictedSOffsetBit, }, |
| 813 | {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, }, |
| 814 | {Feature_EnableFlatScratchBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, }, |
| 815 | {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isGFX12PlusBit, }, |
| 816 | {Feature_FP64DenormalsBit, Feature_NotHasMinMaxDenormModesBit, Feature_isNotGFX12PlusBit, }, |
| 817 | {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_HasTrue16BitInstsBit, }, |
| 818 | {Feature_Has16BitInstsBit, Feature_HasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, }, |
| 819 | {Feature_Has16BitInstsBit, Feature_has32BankLDSBit, Feature_isNotGFX90APlusBit, }, |
| 820 | {Feature_HasMadMacF32InstsBit, Feature_NoFP32DenormalsBit, Feature_isGFX6GFX7GFX10Bit, }, |
| 821 | {Feature_EnableFlatScratchBit, Feature_HasD16LoadStoreBit, Feature_HasFlatScratchInstsBit, Feature_HasFlatScratchSVSModeBit, }, |
| 822 | {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_HasTrue16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, }, |
| 823 | {Feature_FP16DenormalsBit, Feature_Has16BitInstsBit, Feature_NotHasMinMaxDenormModesBit, Feature_NotHasTrue16BitInstsBit, }, |
| 824 | }; |
| 825 | |
| 826 | // ComplexPattern predicates. |
| 827 | enum { |
| 828 | GICP_Invalid, |
| 829 | GICP_gi_buf_soffset, |
| 830 | GICP_gi_ds_128bit_8byte_aligned, |
| 831 | GICP_gi_ds_1addr_1offset, |
| 832 | GICP_gi_ds_64bit_4byte_aligned, |
| 833 | GICP_gi_flat_offset, |
| 834 | GICP_gi_flat_scratch_offset, |
| 835 | GICP_gi_flat_scratch_saddr, |
| 836 | GICP_gi_flat_scratch_svaddr, |
| 837 | GICP_gi_global_offset, |
| 838 | GICP_gi_global_saddr, |
| 839 | GICP_gi_mubuf_addr64, |
| 840 | GICP_gi_mubuf_offset, |
| 841 | GICP_gi_mubuf_scratch_offen, |
| 842 | GICP_gi_mubuf_scratch_offset, |
| 843 | GICP_gi_smrd_buffer_imm, |
| 844 | GICP_gi_smrd_buffer_imm32, |
| 845 | GICP_gi_smrd_buffer_sgpr_imm, |
| 846 | GICP_gi_smrd_imm, |
| 847 | GICP_gi_smrd_imm32, |
| 848 | GICP_gi_smrd_sgpr, |
| 849 | GICP_gi_smrd_sgpr_imm, |
| 850 | GICP_gi_swmmacindex16, |
| 851 | GICP_gi_swmmacindex8, |
| 852 | GICP_gi_vcsrc, |
| 853 | GICP_gi_vinterpmods, |
| 854 | GICP_gi_vinterpmods_hi, |
| 855 | GICP_gi_vop3_mad_mix_mods, |
| 856 | GICP_gi_vop3_mad_mix_mods_ext, |
| 857 | GICP_gi_vop3_no_mods, |
| 858 | GICP_gi_vop3mods, |
| 859 | GICP_gi_vop3mods0, |
| 860 | GICP_gi_vop3modsnoncanonicalizing, |
| 861 | GICP_gi_vop3omods, |
| 862 | GICP_gi_vop3opsel, |
| 863 | GICP_gi_vop3opselmods, |
| 864 | GICP_gi_vop3pmods, |
| 865 | GICP_gi_vop3pmodsdot, |
| 866 | GICP_gi_vop3pmodsneg, |
| 867 | GICP_gi_vsrc0, |
| 868 | GICP_gi_wmmamods, |
| 869 | GICP_gi_wmmamodsf16Neg, |
| 870 | GICP_gi_wmmamodsf16NegAbs, |
| 871 | GICP_gi_wmmaopselvop3pmods, |
| 872 | GICP_gi_wmmavisrc, |
| 873 | }; |
| 874 | // See constructor for table contents |
| 875 | |
| 876 | AMDGPUInstructionSelector::ComplexMatcherMemFn |
| 877 | AMDGPUInstructionSelector::ComplexPredicateFns[] = { |
| 878 | nullptr, // GICP_Invalid |
| 879 | &AMDGPUInstructionSelector::selectBUFSOffset, // gi_buf_soffset |
| 880 | &AMDGPUInstructionSelector::selectDS128Bit8ByteAligned, // gi_ds_128bit_8byte_aligned |
| 881 | &AMDGPUInstructionSelector::selectDS1Addr1Offset, // gi_ds_1addr_1offset |
| 882 | &AMDGPUInstructionSelector::selectDS64Bit4ByteAligned, // gi_ds_64bit_4byte_aligned |
| 883 | &AMDGPUInstructionSelector::selectFlatOffset, // gi_flat_offset |
| 884 | &AMDGPUInstructionSelector::selectScratchOffset, // gi_flat_scratch_offset |
| 885 | &AMDGPUInstructionSelector::selectScratchSAddr, // gi_flat_scratch_saddr |
| 886 | &AMDGPUInstructionSelector::selectScratchSVAddr, // gi_flat_scratch_svaddr |
| 887 | &AMDGPUInstructionSelector::selectGlobalOffset, // gi_global_offset |
| 888 | &AMDGPUInstructionSelector::selectGlobalSAddr, // gi_global_saddr |
| 889 | &AMDGPUInstructionSelector::selectMUBUFAddr64, // gi_mubuf_addr64 |
| 890 | &AMDGPUInstructionSelector::selectMUBUFOffset, // gi_mubuf_offset |
| 891 | &AMDGPUInstructionSelector::selectMUBUFScratchOffen, // gi_mubuf_scratch_offen |
| 892 | &AMDGPUInstructionSelector::selectMUBUFScratchOffset, // gi_mubuf_scratch_offset |
| 893 | &AMDGPUInstructionSelector::selectSMRDBufferImm, // gi_smrd_buffer_imm |
| 894 | &AMDGPUInstructionSelector::selectSMRDBufferImm32, // gi_smrd_buffer_imm32 |
| 895 | &AMDGPUInstructionSelector::selectSMRDBufferSgprImm, // gi_smrd_buffer_sgpr_imm |
| 896 | &AMDGPUInstructionSelector::selectSmrdImm, // gi_smrd_imm |
| 897 | &AMDGPUInstructionSelector::selectSmrdImm32, // gi_smrd_imm32 |
| 898 | &AMDGPUInstructionSelector::selectSmrdSgpr, // gi_smrd_sgpr |
| 899 | &AMDGPUInstructionSelector::selectSmrdSgprImm, // gi_smrd_sgpr_imm |
| 900 | &AMDGPUInstructionSelector::selectSWMMACIndex16, // gi_swmmacindex16 |
| 901 | &AMDGPUInstructionSelector::selectSWMMACIndex8, // gi_swmmacindex8 |
| 902 | &AMDGPUInstructionSelector::selectVCSRC, // gi_vcsrc |
| 903 | &AMDGPUInstructionSelector::selectVINTERPMods, // gi_vinterpmods |
| 904 | &AMDGPUInstructionSelector::selectVINTERPModsHi, // gi_vinterpmods_hi |
| 905 | &AMDGPUInstructionSelector::selectVOP3PMadMixMods, // gi_vop3_mad_mix_mods |
| 906 | &AMDGPUInstructionSelector::selectVOP3PMadMixModsExt, // gi_vop3_mad_mix_mods_ext |
| 907 | &AMDGPUInstructionSelector::selectVOP3NoMods, // gi_vop3_no_mods |
| 908 | &AMDGPUInstructionSelector::selectVOP3Mods, // gi_vop3mods |
| 909 | &AMDGPUInstructionSelector::selectVOP3Mods0, // gi_vop3mods0 |
| 910 | &AMDGPUInstructionSelector::selectVOP3ModsNonCanonicalizing, // gi_vop3modsnoncanonicalizing |
| 911 | &AMDGPUInstructionSelector::selectVOP3OMods, // gi_vop3omods |
| 912 | &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opsel |
| 913 | &AMDGPUInstructionSelector::selectVOP3OpSelMods, // gi_vop3opselmods |
| 914 | &AMDGPUInstructionSelector::selectVOP3PMods, // gi_vop3pmods |
| 915 | &AMDGPUInstructionSelector::selectVOP3PModsDOT, // gi_vop3pmodsdot |
| 916 | &AMDGPUInstructionSelector::selectVOP3PModsNeg, // gi_vop3pmodsneg |
| 917 | &AMDGPUInstructionSelector::selectVSRC0, // gi_vsrc0 |
| 918 | &AMDGPUInstructionSelector::selectWMMAModsF32NegAbs, // gi_wmmamods |
| 919 | &AMDGPUInstructionSelector::selectWMMAModsF16Neg, // gi_wmmamodsf16Neg |
| 920 | &AMDGPUInstructionSelector::selectWMMAModsF16NegAbs, // gi_wmmamodsf16NegAbs |
| 921 | &AMDGPUInstructionSelector::selectWMMAOpSelVOP3PMods, // gi_wmmaopselvop3pmods |
| 922 | &AMDGPUInstructionSelector::selectWMMAVISrc, // gi_wmmavisrc |
| 923 | }; |
| 924 | |
| 925 | // PatFrag predicates. |
| 926 | enum { |
| 927 | GICXXPred_MI_Predicate_aligned_smrd_load = GICXXPred_Invalid + 1, |
| 928 | GICXXPred_MI_Predicate_anonymous_18476, |
| 929 | GICXXPred_MI_Predicate_anonymous_18479, |
| 930 | GICXXPred_MI_Predicate_anonymous_18480, |
| 931 | GICXXPred_MI_Predicate_anonymous_18481, |
| 932 | GICXXPred_MI_Predicate_anonymous_18482, |
| 933 | GICXXPred_MI_Predicate_anonymous_18483, |
| 934 | GICXXPred_MI_Predicate_anonymous_18486, |
| 935 | GICXXPred_MI_Predicate_anonymous_18487, |
| 936 | GICXXPred_MI_Predicate_anonymous_18488, |
| 937 | GICXXPred_MI_Predicate_anonymous_18489, |
| 938 | GICXXPred_MI_Predicate_anonymous_18490, |
| 939 | GICXXPred_MI_Predicate_anonymous_18491, |
| 940 | GICXXPred_MI_Predicate_anonymous_18492, |
| 941 | GICXXPred_MI_Predicate_anonymous_18493, |
| 942 | GICXXPred_MI_Predicate_anonymous_18494, |
| 943 | GICXXPred_MI_Predicate_anonymous_18495, |
| 944 | GICXXPred_MI_Predicate_anonymous_18496, |
| 945 | GICXXPred_MI_Predicate_anonymous_18497, |
| 946 | GICXXPred_MI_Predicate_anonymous_18498, |
| 947 | GICXXPred_MI_Predicate_anonymous_18499, |
| 948 | GICXXPred_MI_Predicate_anonymous_18500, |
| 949 | GICXXPred_MI_Predicate_anonymous_18501, |
| 950 | GICXXPred_MI_Predicate_anonymous_18502, |
| 951 | GICXXPred_MI_Predicate_anonymous_18503, |
| 952 | GICXXPred_MI_Predicate_anonymous_18504, |
| 953 | GICXXPred_MI_Predicate_anonymous_18505, |
| 954 | GICXXPred_MI_Predicate_anonymous_18506, |
| 955 | GICXXPred_MI_Predicate_anonymous_18507, |
| 956 | GICXXPred_MI_Predicate_anonymous_18508, |
| 957 | GICXXPred_MI_Predicate_anonymous_18509, |
| 958 | GICXXPred_MI_Predicate_anonymous_18510, |
| 959 | GICXXPred_MI_Predicate_anonymous_18511, |
| 960 | GICXXPred_MI_Predicate_anonymous_18512, |
| 961 | GICXXPred_MI_Predicate_anonymous_18513, |
| 962 | GICXXPred_MI_Predicate_anonymous_18514, |
| 963 | GICXXPred_MI_Predicate_anonymous_18515, |
| 964 | GICXXPred_MI_Predicate_anonymous_18516, |
| 965 | GICXXPred_MI_Predicate_anonymous_18517, |
| 966 | GICXXPred_MI_Predicate_anonymous_18518, |
| 967 | GICXXPred_MI_Predicate_anonymous_18519, |
| 968 | GICXXPred_MI_Predicate_anonymous_18520, |
| 969 | GICXXPred_MI_Predicate_anonymous_18521, |
| 970 | GICXXPred_MI_Predicate_anonymous_18522, |
| 971 | GICXXPred_MI_Predicate_anonymous_18523, |
| 972 | GICXXPred_MI_Predicate_anonymous_18524, |
| 973 | GICXXPred_MI_Predicate_anonymous_18525, |
| 974 | GICXXPred_MI_Predicate_anonymous_18526, |
| 975 | GICXXPred_MI_Predicate_anonymous_18527, |
| 976 | GICXXPred_MI_Predicate_anonymous_18534, |
| 977 | GICXXPred_MI_Predicate_anonymous_18546, |
| 978 | GICXXPred_MI_Predicate_anonymous_22135, |
| 979 | GICXXPred_MI_Predicate_anonymous_23233, |
| 980 | GICXXPred_MI_Predicate_anonymous_23235, |
| 981 | GICXXPred_MI_Predicate_anonymous_23237, |
| 982 | GICXXPred_MI_Predicate_anonymous_23239, |
| 983 | GICXXPred_MI_Predicate_anonymous_23241, |
| 984 | GICXXPred_MI_Predicate_anonymous_23245, |
| 985 | GICXXPred_MI_Predicate_anonymous_23247, |
| 986 | GICXXPred_MI_Predicate_anonymous_23249, |
| 987 | GICXXPred_MI_Predicate_anonymous_23251, |
| 988 | GICXXPred_MI_Predicate_anonymous_23253, |
| 989 | GICXXPred_MI_Predicate_anonymous_23412, |
| 990 | GICXXPred_MI_Predicate_anonymous_23414, |
| 991 | GICXXPred_MI_Predicate_anonymous_23638, |
| 992 | GICXXPred_MI_Predicate_anonymous_23648, |
| 993 | GICXXPred_MI_Predicate_anonymous_23651, |
| 994 | GICXXPred_MI_Predicate_anonymous_23739, |
| 995 | GICXXPred_MI_Predicate_anonymous_24022, |
| 996 | GICXXPred_MI_Predicate_anonymous_24025, |
| 997 | GICXXPred_MI_Predicate_anonymous_24028, |
| 998 | GICXXPred_MI_Predicate_anonymous_24030, |
| 999 | GICXXPred_MI_Predicate_anonymous_24033, |
| 1000 | GICXXPred_MI_Predicate_anonymous_24035, |
| 1001 | GICXXPred_MI_Predicate_anonymous_24038, |
| 1002 | GICXXPred_MI_Predicate_anonymous_24041, |
| 1003 | GICXXPred_MI_Predicate_anonymous_24045, |
| 1004 | GICXXPred_MI_Predicate_anonymous_24053, |
| 1005 | GICXXPred_MI_Predicate_anonymous_24088, |
| 1006 | GICXXPred_MI_Predicate_anonymous_24193, |
| 1007 | GICXXPred_MI_Predicate_anonymous_24196, |
| 1008 | GICXXPred_MI_Predicate_anonymous_24198, |
| 1009 | GICXXPred_MI_Predicate_anonymous_24200, |
| 1010 | GICXXPred_MI_Predicate_anonymous_24202, |
| 1011 | GICXXPred_MI_Predicate_anonymous_24204, |
| 1012 | GICXXPred_MI_Predicate_anonymous_24206, |
| 1013 | GICXXPred_MI_Predicate_anonymous_25064, |
| 1014 | GICXXPred_MI_Predicate_anonymous_25066, |
| 1015 | GICXXPred_MI_Predicate_anonymous_25070, |
| 1016 | GICXXPred_MI_Predicate_anonymous_25072, |
| 1017 | GICXXPred_MI_Predicate_anonymous_25074, |
| 1018 | GICXXPred_MI_Predicate_anonymous_25076, |
| 1019 | GICXXPred_MI_Predicate_anonymous_25080, |
| 1020 | GICXXPred_MI_Predicate_anonymous_25082, |
| 1021 | GICXXPred_MI_Predicate_anonymous_25084, |
| 1022 | GICXXPred_MI_Predicate_anonymous_25086, |
| 1023 | GICXXPred_MI_Predicate_anonymous_25088, |
| 1024 | GICXXPred_MI_Predicate_anonymous_25090, |
| 1025 | GICXXPred_MI_Predicate_anonymous_25092, |
| 1026 | GICXXPred_MI_Predicate_anonymous_25094, |
| 1027 | GICXXPred_MI_Predicate_anonymous_25098, |
| 1028 | GICXXPred_MI_Predicate_anonymous_25100, |
| 1029 | GICXXPred_MI_Predicate_anonymous_25102, |
| 1030 | GICXXPred_MI_Predicate_anonymous_25104, |
| 1031 | GICXXPred_MI_Predicate_anonymous_25108, |
| 1032 | GICXXPred_MI_Predicate_anonymous_25110, |
| 1033 | GICXXPred_MI_Predicate_anonymous_25114, |
| 1034 | GICXXPred_MI_Predicate_anonymous_25116, |
| 1035 | GICXXPred_MI_Predicate_anonymous_25118, |
| 1036 | GICXXPred_MI_Predicate_anonymous_25120, |
| 1037 | GICXXPred_MI_Predicate_anonymous_25124, |
| 1038 | GICXXPred_MI_Predicate_anonymous_25126, |
| 1039 | GICXXPred_MI_Predicate_anonymous_25128, |
| 1040 | GICXXPred_MI_Predicate_anonymous_25130, |
| 1041 | GICXXPred_MI_Predicate_anonymous_25132, |
| 1042 | GICXXPred_MI_Predicate_anonymous_25134, |
| 1043 | GICXXPred_MI_Predicate_anonymous_25136, |
| 1044 | GICXXPred_MI_Predicate_anonymous_25138, |
| 1045 | GICXXPred_MI_Predicate_anonymous_25142, |
| 1046 | GICXXPred_MI_Predicate_anonymous_25144, |
| 1047 | GICXXPred_MI_Predicate_anonymous_25146, |
| 1048 | GICXXPred_MI_Predicate_anonymous_25148, |
| 1049 | GICXXPred_MI_Predicate_anonymous_25152, |
| 1050 | GICXXPred_MI_Predicate_anonymous_25154, |
| 1051 | GICXXPred_MI_Predicate_anonymous_25156, |
| 1052 | GICXXPred_MI_Predicate_anonymous_25158, |
| 1053 | GICXXPred_MI_Predicate_anonymous_25162, |
| 1054 | GICXXPred_MI_Predicate_anonymous_25164, |
| 1055 | GICXXPred_MI_Predicate_anonymous_25168, |
| 1056 | GICXXPred_MI_Predicate_anonymous_25170, |
| 1057 | GICXXPred_MI_Predicate_anonymous_25172, |
| 1058 | GICXXPred_MI_Predicate_anonymous_25174, |
| 1059 | GICXXPred_MI_Predicate_anonymous_25176, |
| 1060 | GICXXPred_MI_Predicate_anonymous_25178, |
| 1061 | GICXXPred_MI_Predicate_anonymous_25180, |
| 1062 | GICXXPred_MI_Predicate_anonymous_25182, |
| 1063 | GICXXPred_MI_Predicate_anonymous_25186, |
| 1064 | GICXXPred_MI_Predicate_anonymous_25188, |
| 1065 | GICXXPred_MI_Predicate_anonymous_25190, |
| 1066 | GICXXPred_MI_Predicate_anonymous_25192, |
| 1067 | GICXXPred_MI_Predicate_anonymous_25196, |
| 1068 | GICXXPred_MI_Predicate_anonymous_25198, |
| 1069 | GICXXPred_MI_Predicate_anonymous_25200, |
| 1070 | GICXXPred_MI_Predicate_anonymous_25202, |
| 1071 | GICXXPred_MI_Predicate_anonymous_25204, |
| 1072 | GICXXPred_MI_Predicate_anonymous_25206, |
| 1073 | GICXXPred_MI_Predicate_anonymous_25210, |
| 1074 | GICXXPred_MI_Predicate_anonymous_25212, |
| 1075 | GICXXPred_MI_Predicate_anonymous_25214, |
| 1076 | GICXXPred_MI_Predicate_anonymous_25216, |
| 1077 | GICXXPred_MI_Predicate_anonymous_25218, |
| 1078 | GICXXPred_MI_Predicate_anonymous_25220, |
| 1079 | GICXXPred_MI_Predicate_anonymous_25222, |
| 1080 | GICXXPred_MI_Predicate_anonymous_25224, |
| 1081 | GICXXPred_MI_Predicate_anonymous_25226, |
| 1082 | GICXXPred_MI_Predicate_anonymous_25228, |
| 1083 | GICXXPred_MI_Predicate_anonymous_25232, |
| 1084 | GICXXPred_MI_Predicate_anonymous_25234, |
| 1085 | GICXXPred_MI_Predicate_anonymous_25236, |
| 1086 | GICXXPred_MI_Predicate_anonymous_25238, |
| 1087 | GICXXPred_MI_Predicate_anonymous_25240, |
| 1088 | GICXXPred_MI_Predicate_anonymous_25242, |
| 1089 | GICXXPred_MI_Predicate_anonymous_25244, |
| 1090 | GICXXPred_MI_Predicate_anonymous_25246, |
| 1091 | GICXXPred_MI_Predicate_anonymous_35622, |
| 1092 | GICXXPred_MI_Predicate_anonymous_35929, |
| 1093 | GICXXPred_MI_Predicate_anonymous_35931, |
| 1094 | GICXXPred_MI_Predicate_anonymous_35965, |
| 1095 | GICXXPred_MI_Predicate_anonymous_36140, |
| 1096 | GICXXPred_MI_Predicate_anonymous_36143, |
| 1097 | GICXXPred_MI_Predicate_anonymous_36148, |
| 1098 | GICXXPred_MI_Predicate_anonymous_36152, |
| 1099 | GICXXPred_MI_Predicate_anonymous_36198, |
| 1100 | GICXXPred_MI_Predicate_anonymous_36200, |
| 1101 | GICXXPred_MI_Predicate_anonymous_36239, |
| 1102 | GICXXPred_MI_Predicate_anonymous_36262, |
| 1103 | GICXXPred_MI_Predicate_anonymous_36264, |
| 1104 | GICXXPred_MI_Predicate_anonymous_36272, |
| 1105 | GICXXPred_MI_Predicate_anonymous_36274, |
| 1106 | GICXXPred_MI_Predicate_anonymous_36291, |
| 1107 | GICXXPred_MI_Predicate_anonymous_36293, |
| 1108 | GICXXPred_MI_Predicate_anonymous_36295, |
| 1109 | GICXXPred_MI_Predicate_anonymous_36297, |
| 1110 | GICXXPred_MI_Predicate_anonymous_36299, |
| 1111 | GICXXPred_MI_Predicate_csh_mask_16, |
| 1112 | GICXXPred_MI_Predicate_csh_mask_32, |
| 1113 | GICXXPred_MI_Predicate_csh_mask_64, |
| 1114 | GICXXPred_MI_Predicate_fmaxnum_like_nnan, |
| 1115 | GICXXPred_MI_Predicate_fminnum_like_nnan, |
| 1116 | GICXXPred_MI_Predicate_is_canonicalized, |
| 1117 | GICXXPred_MI_Predicate_load_align_less_than_4_local, |
| 1118 | GICXXPred_MI_Predicate_load_align_less_than_4_local_m0, |
| 1119 | GICXXPred_MI_Predicate_shl1_add, |
| 1120 | GICXXPred_MI_Predicate_shl2_add, |
| 1121 | GICXXPred_MI_Predicate_shl3_add, |
| 1122 | GICXXPred_MI_Predicate_shl4_add, |
| 1123 | GICXXPred_MI_Predicate_shl_0_to_4, |
| 1124 | GICXXPred_MI_Predicate_smrd_extloadi8, |
| 1125 | GICXXPred_MI_Predicate_smrd_extloadi16, |
| 1126 | GICXXPred_MI_Predicate_smrd_load, |
| 1127 | GICXXPred_MI_Predicate_smrd_prefetch, |
| 1128 | GICXXPred_MI_Predicate_smrd_sextloadi8, |
| 1129 | GICXXPred_MI_Predicate_smrd_sextloadi16, |
| 1130 | GICXXPred_MI_Predicate_smrd_zextloadi8, |
| 1131 | GICXXPred_MI_Predicate_smrd_zextloadi16, |
| 1132 | GICXXPred_MI_Predicate_store_align_less_than_4_local, |
| 1133 | GICXXPred_MI_Predicate_store_align_less_than_4_local_m0, |
| 1134 | }; |
| 1135 | bool AMDGPUInstructionSelector::testMIPredicate_MI(unsigned PredicateID, const MachineInstr & MI, const MatcherState &State) const { |
| 1136 | const MachineFunction &MF = *MI.getParent()->getParent(); |
| 1137 | const MachineRegisterInfo &MRI = MF.getRegInfo(); |
| 1138 | const auto &Operands = State.RecordedOperands; |
| 1139 | (void)Operands; |
| 1140 | (void)MRI; |
| 1141 | switch (PredicateID) { |
| 1142 | case GICXXPred_MI_Predicate_aligned_smrd_load: { |
| 1143 | |
| 1144 | auto &Ld = cast<GLoad>(MI); |
| 1145 | TypeSize Size = Ld.getMMO().getSize().getValue(); |
| 1146 | return Size <= 4 || Ld.getMMO().getAlign().value() >= Size; |
| 1147 | |
| 1148 | llvm_unreachable("aligned_smrd_load should have returned"); |
| 1149 | } |
| 1150 | case GICXXPred_MI_Predicate_anonymous_18476: { |
| 1151 | return true; |
| 1152 | } |
| 1153 | case GICXXPred_MI_Predicate_anonymous_18479: { |
| 1154 | return true; |
| 1155 | } |
| 1156 | case GICXXPred_MI_Predicate_anonymous_18480: { |
| 1157 | return true; |
| 1158 | } |
| 1159 | case GICXXPred_MI_Predicate_anonymous_18481: { |
| 1160 | return true; |
| 1161 | } |
| 1162 | case GICXXPred_MI_Predicate_anonymous_18482: { |
| 1163 | return true; |
| 1164 | } |
| 1165 | case GICXXPred_MI_Predicate_anonymous_18483: { |
| 1166 | return true; |
| 1167 | } |
| 1168 | case GICXXPred_MI_Predicate_anonymous_18486: { |
| 1169 | return true; |
| 1170 | } |
| 1171 | case GICXXPred_MI_Predicate_anonymous_18487: { |
| 1172 | return true; |
| 1173 | } |
| 1174 | case GICXXPred_MI_Predicate_anonymous_18488: { |
| 1175 | return true; |
| 1176 | } |
| 1177 | case GICXXPred_MI_Predicate_anonymous_18489: { |
| 1178 | return true; |
| 1179 | } |
| 1180 | case GICXXPred_MI_Predicate_anonymous_18490: { |
| 1181 | return true; |
| 1182 | } |
| 1183 | case GICXXPred_MI_Predicate_anonymous_18491: { |
| 1184 | return true; |
| 1185 | } |
| 1186 | case GICXXPred_MI_Predicate_anonymous_18492: { |
| 1187 | return true; |
| 1188 | } |
| 1189 | case GICXXPred_MI_Predicate_anonymous_18493: { |
| 1190 | return true; |
| 1191 | } |
| 1192 | case GICXXPred_MI_Predicate_anonymous_18494: { |
| 1193 | return true; |
| 1194 | } |
| 1195 | case GICXXPred_MI_Predicate_anonymous_18495: { |
| 1196 | return true; |
| 1197 | } |
| 1198 | case GICXXPred_MI_Predicate_anonymous_18496: { |
| 1199 | return true; |
| 1200 | } |
| 1201 | case GICXXPred_MI_Predicate_anonymous_18497: { |
| 1202 | return true; |
| 1203 | } |
| 1204 | case GICXXPred_MI_Predicate_anonymous_18498: { |
| 1205 | return true; |
| 1206 | } |
| 1207 | case GICXXPred_MI_Predicate_anonymous_18499: { |
| 1208 | return true; |
| 1209 | } |
| 1210 | case GICXXPred_MI_Predicate_anonymous_18500: { |
| 1211 | return true; |
| 1212 | } |
| 1213 | case GICXXPred_MI_Predicate_anonymous_18501: { |
| 1214 | return true; |
| 1215 | } |
| 1216 | case GICXXPred_MI_Predicate_anonymous_18502: { |
| 1217 | return true; |
| 1218 | } |
| 1219 | case GICXXPred_MI_Predicate_anonymous_18503: { |
| 1220 | return true; |
| 1221 | } |
| 1222 | case GICXXPred_MI_Predicate_anonymous_18504: { |
| 1223 | return true; |
| 1224 | } |
| 1225 | case GICXXPred_MI_Predicate_anonymous_18505: { |
| 1226 | return true; |
| 1227 | } |
| 1228 | case GICXXPred_MI_Predicate_anonymous_18506: { |
| 1229 | return true; |
| 1230 | } |
| 1231 | case GICXXPred_MI_Predicate_anonymous_18507: { |
| 1232 | return true; |
| 1233 | } |
| 1234 | case GICXXPred_MI_Predicate_anonymous_18508: { |
| 1235 | return true; |
| 1236 | } |
| 1237 | case GICXXPred_MI_Predicate_anonymous_18509: { |
| 1238 | return true; |
| 1239 | } |
| 1240 | case GICXXPred_MI_Predicate_anonymous_18510: { |
| 1241 | return true; |
| 1242 | } |
| 1243 | case GICXXPred_MI_Predicate_anonymous_18511: { |
| 1244 | return true; |
| 1245 | } |
| 1246 | case GICXXPred_MI_Predicate_anonymous_18512: { |
| 1247 | return true; |
| 1248 | } |
| 1249 | case GICXXPred_MI_Predicate_anonymous_18513: { |
| 1250 | return true; |
| 1251 | } |
| 1252 | case GICXXPred_MI_Predicate_anonymous_18514: { |
| 1253 | return true; |
| 1254 | } |
| 1255 | case GICXXPred_MI_Predicate_anonymous_18515: { |
| 1256 | return true; |
| 1257 | } |
| 1258 | case GICXXPred_MI_Predicate_anonymous_18516: { |
| 1259 | return true; |
| 1260 | } |
| 1261 | case GICXXPred_MI_Predicate_anonymous_18517: { |
| 1262 | return true; |
| 1263 | } |
| 1264 | case GICXXPred_MI_Predicate_anonymous_18518: { |
| 1265 | return true; |
| 1266 | } |
| 1267 | case GICXXPred_MI_Predicate_anonymous_18519: { |
| 1268 | return true; |
| 1269 | } |
| 1270 | case GICXXPred_MI_Predicate_anonymous_18520: { |
| 1271 | return true; |
| 1272 | } |
| 1273 | case GICXXPred_MI_Predicate_anonymous_18521: { |
| 1274 | return true; |
| 1275 | } |
| 1276 | case GICXXPred_MI_Predicate_anonymous_18522: { |
| 1277 | return true; |
| 1278 | } |
| 1279 | case GICXXPred_MI_Predicate_anonymous_18523: { |
| 1280 | return true; |
| 1281 | } |
| 1282 | case GICXXPred_MI_Predicate_anonymous_18524: { |
| 1283 | return true; |
| 1284 | } |
| 1285 | case GICXXPred_MI_Predicate_anonymous_18525: { |
| 1286 | return true; |
| 1287 | } |
| 1288 | case GICXXPred_MI_Predicate_anonymous_18526: { |
| 1289 | return true; |
| 1290 | } |
| 1291 | case GICXXPred_MI_Predicate_anonymous_18527: { |
| 1292 | return true; |
| 1293 | } |
| 1294 | case GICXXPred_MI_Predicate_anonymous_18534: { |
| 1295 | return true; |
| 1296 | } |
| 1297 | case GICXXPred_MI_Predicate_anonymous_18546: { |
| 1298 | return true; |
| 1299 | } |
| 1300 | case GICXXPred_MI_Predicate_anonymous_22135: { |
| 1301 | return true; |
| 1302 | } |
| 1303 | case GICXXPred_MI_Predicate_anonymous_23233: { |
| 1304 | return true; |
| 1305 | } |
| 1306 | case GICXXPred_MI_Predicate_anonymous_23235: { |
| 1307 | return true; |
| 1308 | } |
| 1309 | case GICXXPred_MI_Predicate_anonymous_23237: { |
| 1310 | return true; |
| 1311 | } |
| 1312 | case GICXXPred_MI_Predicate_anonymous_23239: { |
| 1313 | return true; |
| 1314 | } |
| 1315 | case GICXXPred_MI_Predicate_anonymous_23241: { |
| 1316 | return true; |
| 1317 | } |
| 1318 | case GICXXPred_MI_Predicate_anonymous_23245: { |
| 1319 | return true; |
| 1320 | } |
| 1321 | case GICXXPred_MI_Predicate_anonymous_23247: { |
| 1322 | return true; |
| 1323 | } |
| 1324 | case GICXXPred_MI_Predicate_anonymous_23249: { |
| 1325 | return true; |
| 1326 | } |
| 1327 | case GICXXPred_MI_Predicate_anonymous_23251: { |
| 1328 | return true; |
| 1329 | } |
| 1330 | case GICXXPred_MI_Predicate_anonymous_23253: { |
| 1331 | return true; |
| 1332 | } |
| 1333 | case GICXXPred_MI_Predicate_anonymous_23412: { |
| 1334 | return true; |
| 1335 | } |
| 1336 | case GICXXPred_MI_Predicate_anonymous_23414: { |
| 1337 | return true; |
| 1338 | } |
| 1339 | case GICXXPred_MI_Predicate_anonymous_23638: { |
| 1340 | return true; |
| 1341 | } |
| 1342 | case GICXXPred_MI_Predicate_anonymous_23648: { |
| 1343 | return true; |
| 1344 | } |
| 1345 | case GICXXPred_MI_Predicate_anonymous_23651: { |
| 1346 | return true; |
| 1347 | } |
| 1348 | case GICXXPred_MI_Predicate_anonymous_23739: { |
| 1349 | return true; |
| 1350 | } |
| 1351 | case GICXXPred_MI_Predicate_anonymous_24022: { |
| 1352 | |
| 1353 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1354 | int ConstantBusUses = 0; |
| 1355 | for (unsigned i = 0; i < 3; ++i) { |
| 1356 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1357 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1358 | if (++ConstantBusUses > ConstantBusLimit) |
| 1359 | return false; |
| 1360 | } |
| 1361 | } |
| 1362 | return true; |
| 1363 | |
| 1364 | llvm_unreachable("anonymous_24022 should have returned"); |
| 1365 | } |
| 1366 | case GICXXPred_MI_Predicate_anonymous_24025: { |
| 1367 | |
| 1368 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1369 | int ConstantBusUses = 0; |
| 1370 | for (unsigned i = 0; i < 3; ++i) { |
| 1371 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1372 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1373 | if (++ConstantBusUses > ConstantBusLimit) |
| 1374 | return false; |
| 1375 | } |
| 1376 | } |
| 1377 | return true; |
| 1378 | |
| 1379 | llvm_unreachable("anonymous_24025 should have returned"); |
| 1380 | } |
| 1381 | case GICXXPred_MI_Predicate_anonymous_24028: { |
| 1382 | |
| 1383 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1384 | int ConstantBusUses = 0; |
| 1385 | for (unsigned i = 0; i < 3; ++i) { |
| 1386 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1387 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1388 | if (++ConstantBusUses > ConstantBusLimit) |
| 1389 | return false; |
| 1390 | } |
| 1391 | } |
| 1392 | return true; |
| 1393 | |
| 1394 | llvm_unreachable("anonymous_24028 should have returned"); |
| 1395 | } |
| 1396 | case GICXXPred_MI_Predicate_anonymous_24030: { |
| 1397 | |
| 1398 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1399 | int ConstantBusUses = 0; |
| 1400 | for (unsigned i = 0; i < 3; ++i) { |
| 1401 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1402 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1403 | if (++ConstantBusUses > ConstantBusLimit) |
| 1404 | return false; |
| 1405 | } |
| 1406 | } |
| 1407 | return true; |
| 1408 | |
| 1409 | llvm_unreachable("anonymous_24030 should have returned"); |
| 1410 | } |
| 1411 | case GICXXPred_MI_Predicate_anonymous_24033: { |
| 1412 | |
| 1413 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1414 | int ConstantBusUses = 0; |
| 1415 | for (unsigned i = 0; i < 3; ++i) { |
| 1416 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1417 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1418 | if (++ConstantBusUses > ConstantBusLimit) |
| 1419 | return false; |
| 1420 | } |
| 1421 | } |
| 1422 | return true; |
| 1423 | |
| 1424 | llvm_unreachable("anonymous_24033 should have returned"); |
| 1425 | } |
| 1426 | case GICXXPred_MI_Predicate_anonymous_24035: { |
| 1427 | |
| 1428 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1429 | int ConstantBusUses = 0; |
| 1430 | for (unsigned i = 0; i < 3; ++i) { |
| 1431 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1432 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1433 | if (++ConstantBusUses > ConstantBusLimit) |
| 1434 | return false; |
| 1435 | } |
| 1436 | } |
| 1437 | return true; |
| 1438 | |
| 1439 | llvm_unreachable("anonymous_24035 should have returned"); |
| 1440 | } |
| 1441 | case GICXXPred_MI_Predicate_anonymous_24038: { |
| 1442 | |
| 1443 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1444 | int ConstantBusUses = 0; |
| 1445 | for (unsigned i = 0; i < 3; ++i) { |
| 1446 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1447 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1448 | if (++ConstantBusUses > ConstantBusLimit) |
| 1449 | return false; |
| 1450 | } |
| 1451 | } |
| 1452 | return true; |
| 1453 | |
| 1454 | llvm_unreachable("anonymous_24038 should have returned"); |
| 1455 | } |
| 1456 | case GICXXPred_MI_Predicate_anonymous_24041: { |
| 1457 | |
| 1458 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1459 | int ConstantBusUses = 0; |
| 1460 | for (unsigned i = 0; i < 3; ++i) { |
| 1461 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1462 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1463 | if (++ConstantBusUses > ConstantBusLimit) |
| 1464 | return false; |
| 1465 | } |
| 1466 | } |
| 1467 | return true; |
| 1468 | |
| 1469 | llvm_unreachable("anonymous_24041 should have returned"); |
| 1470 | } |
| 1471 | case GICXXPred_MI_Predicate_anonymous_24045: { |
| 1472 | |
| 1473 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1474 | int ConstantBusUses = 0; |
| 1475 | for (unsigned i = 0; i < 3; ++i) { |
| 1476 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1477 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1478 | if (++ConstantBusUses > ConstantBusLimit) |
| 1479 | return false; |
| 1480 | } |
| 1481 | } |
| 1482 | return true; |
| 1483 | |
| 1484 | llvm_unreachable("anonymous_24045 should have returned"); |
| 1485 | } |
| 1486 | case GICXXPred_MI_Predicate_anonymous_24053: { |
| 1487 | |
| 1488 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1489 | int ConstantBusUses = 0; |
| 1490 | for (unsigned i = 0; i < 3; ++i) { |
| 1491 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1492 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1493 | if (++ConstantBusUses > ConstantBusLimit) |
| 1494 | return false; |
| 1495 | } |
| 1496 | } |
| 1497 | return true; |
| 1498 | |
| 1499 | llvm_unreachable("anonymous_24053 should have returned"); |
| 1500 | } |
| 1501 | case GICXXPred_MI_Predicate_anonymous_24088: { |
| 1502 | |
| 1503 | const int ConstantBusLimit = Subtarget->getConstantBusLimit(AMDGPU::V_ADD3_U32_e64); |
| 1504 | int ConstantBusUses = 0; |
| 1505 | for (unsigned i = 0; i < 3; ++i) { |
| 1506 | const RegisterBank *RegBank = RBI.getRegBank(Operands[i]->getReg(), MRI, TRI); |
| 1507 | if (RegBank->getID() == AMDGPU::SGPRRegBankID) { |
| 1508 | if (++ConstantBusUses > ConstantBusLimit) |
| 1509 | return false; |
| 1510 | } |
| 1511 | } |
| 1512 | return true; |
| 1513 | |
| 1514 | llvm_unreachable("anonymous_24088 should have returned"); |
| 1515 | } |
| 1516 | case GICXXPred_MI_Predicate_anonymous_24193: { |
| 1517 | return true; |
| 1518 | } |
| 1519 | case GICXXPred_MI_Predicate_anonymous_24196: { |
| 1520 | return true; |
| 1521 | } |
| 1522 | case GICXXPred_MI_Predicate_anonymous_24198: { |
| 1523 | return true; |
| 1524 | } |
| 1525 | case GICXXPred_MI_Predicate_anonymous_24200: { |
| 1526 | return true; |
| 1527 | } |
| 1528 | case GICXXPred_MI_Predicate_anonymous_24202: { |
| 1529 | return true; |
| 1530 | } |
| 1531 | case GICXXPred_MI_Predicate_anonymous_24204: { |
| 1532 | return true; |
| 1533 | } |
| 1534 | case GICXXPred_MI_Predicate_anonymous_24206: { |
| 1535 | return true; |
| 1536 | } |
| 1537 | case GICXXPred_MI_Predicate_anonymous_25064: { |
| 1538 | |
| 1539 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1540 | |
| 1541 | } |
| 1542 | case GICXXPred_MI_Predicate_anonymous_25066: { |
| 1543 | |
| 1544 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1545 | |
| 1546 | } |
| 1547 | case GICXXPred_MI_Predicate_anonymous_25070: { |
| 1548 | |
| 1549 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1550 | |
| 1551 | } |
| 1552 | case GICXXPred_MI_Predicate_anonymous_25072: { |
| 1553 | |
| 1554 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1555 | |
| 1556 | } |
| 1557 | case GICXXPred_MI_Predicate_anonymous_25074: { |
| 1558 | |
| 1559 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1560 | |
| 1561 | } |
| 1562 | case GICXXPred_MI_Predicate_anonymous_25076: { |
| 1563 | |
| 1564 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1565 | |
| 1566 | } |
| 1567 | case GICXXPred_MI_Predicate_anonymous_25080: { |
| 1568 | |
| 1569 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1570 | |
| 1571 | } |
| 1572 | case GICXXPred_MI_Predicate_anonymous_25082: { |
| 1573 | |
| 1574 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1575 | |
| 1576 | } |
| 1577 | case GICXXPred_MI_Predicate_anonymous_25084: { |
| 1578 | |
| 1579 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1580 | |
| 1581 | } |
| 1582 | case GICXXPred_MI_Predicate_anonymous_25086: { |
| 1583 | |
| 1584 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1585 | |
| 1586 | } |
| 1587 | case GICXXPred_MI_Predicate_anonymous_25088: { |
| 1588 | |
| 1589 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1590 | |
| 1591 | } |
| 1592 | case GICXXPred_MI_Predicate_anonymous_25090: { |
| 1593 | |
| 1594 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1595 | |
| 1596 | } |
| 1597 | case GICXXPred_MI_Predicate_anonymous_25092: { |
| 1598 | |
| 1599 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1600 | |
| 1601 | } |
| 1602 | case GICXXPred_MI_Predicate_anonymous_25094: { |
| 1603 | |
| 1604 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1605 | |
| 1606 | } |
| 1607 | case GICXXPred_MI_Predicate_anonymous_25098: { |
| 1608 | |
| 1609 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1610 | |
| 1611 | } |
| 1612 | case GICXXPred_MI_Predicate_anonymous_25100: { |
| 1613 | |
| 1614 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1615 | |
| 1616 | } |
| 1617 | case GICXXPred_MI_Predicate_anonymous_25102: { |
| 1618 | |
| 1619 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1620 | |
| 1621 | } |
| 1622 | case GICXXPred_MI_Predicate_anonymous_25104: { |
| 1623 | |
| 1624 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1625 | |
| 1626 | } |
| 1627 | case GICXXPred_MI_Predicate_anonymous_25108: { |
| 1628 | |
| 1629 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1630 | |
| 1631 | } |
| 1632 | case GICXXPred_MI_Predicate_anonymous_25110: { |
| 1633 | |
| 1634 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1635 | |
| 1636 | } |
| 1637 | case GICXXPred_MI_Predicate_anonymous_25114: { |
| 1638 | |
| 1639 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1640 | |
| 1641 | } |
| 1642 | case GICXXPred_MI_Predicate_anonymous_25116: { |
| 1643 | |
| 1644 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1645 | |
| 1646 | } |
| 1647 | case GICXXPred_MI_Predicate_anonymous_25118: { |
| 1648 | |
| 1649 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1650 | |
| 1651 | } |
| 1652 | case GICXXPred_MI_Predicate_anonymous_25120: { |
| 1653 | |
| 1654 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1655 | |
| 1656 | } |
| 1657 | case GICXXPred_MI_Predicate_anonymous_25124: { |
| 1658 | |
| 1659 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1660 | |
| 1661 | } |
| 1662 | case GICXXPred_MI_Predicate_anonymous_25126: { |
| 1663 | |
| 1664 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1665 | |
| 1666 | } |
| 1667 | case GICXXPred_MI_Predicate_anonymous_25128: { |
| 1668 | |
| 1669 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1670 | |
| 1671 | } |
| 1672 | case GICXXPred_MI_Predicate_anonymous_25130: { |
| 1673 | |
| 1674 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1675 | |
| 1676 | } |
| 1677 | case GICXXPred_MI_Predicate_anonymous_25132: { |
| 1678 | |
| 1679 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1680 | |
| 1681 | } |
| 1682 | case GICXXPred_MI_Predicate_anonymous_25134: { |
| 1683 | |
| 1684 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1685 | |
| 1686 | } |
| 1687 | case GICXXPred_MI_Predicate_anonymous_25136: { |
| 1688 | |
| 1689 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1690 | |
| 1691 | } |
| 1692 | case GICXXPred_MI_Predicate_anonymous_25138: { |
| 1693 | |
| 1694 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1695 | |
| 1696 | } |
| 1697 | case GICXXPred_MI_Predicate_anonymous_25142: { |
| 1698 | |
| 1699 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1700 | |
| 1701 | } |
| 1702 | case GICXXPred_MI_Predicate_anonymous_25144: { |
| 1703 | |
| 1704 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1705 | |
| 1706 | } |
| 1707 | case GICXXPred_MI_Predicate_anonymous_25146: { |
| 1708 | |
| 1709 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1710 | |
| 1711 | } |
| 1712 | case GICXXPred_MI_Predicate_anonymous_25148: { |
| 1713 | |
| 1714 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1715 | |
| 1716 | } |
| 1717 | case GICXXPred_MI_Predicate_anonymous_25152: { |
| 1718 | |
| 1719 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1720 | |
| 1721 | } |
| 1722 | case GICXXPred_MI_Predicate_anonymous_25154: { |
| 1723 | |
| 1724 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1725 | |
| 1726 | } |
| 1727 | case GICXXPred_MI_Predicate_anonymous_25156: { |
| 1728 | |
| 1729 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1730 | |
| 1731 | } |
| 1732 | case GICXXPred_MI_Predicate_anonymous_25158: { |
| 1733 | |
| 1734 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1735 | |
| 1736 | } |
| 1737 | case GICXXPred_MI_Predicate_anonymous_25162: { |
| 1738 | |
| 1739 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1740 | |
| 1741 | } |
| 1742 | case GICXXPred_MI_Predicate_anonymous_25164: { |
| 1743 | |
| 1744 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1745 | |
| 1746 | } |
| 1747 | case GICXXPred_MI_Predicate_anonymous_25168: { |
| 1748 | |
| 1749 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1750 | |
| 1751 | } |
| 1752 | case GICXXPred_MI_Predicate_anonymous_25170: { |
| 1753 | |
| 1754 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1755 | |
| 1756 | } |
| 1757 | case GICXXPred_MI_Predicate_anonymous_25172: { |
| 1758 | |
| 1759 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1760 | |
| 1761 | } |
| 1762 | case GICXXPred_MI_Predicate_anonymous_25174: { |
| 1763 | |
| 1764 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1765 | |
| 1766 | } |
| 1767 | case GICXXPred_MI_Predicate_anonymous_25176: { |
| 1768 | |
| 1769 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1770 | |
| 1771 | } |
| 1772 | case GICXXPred_MI_Predicate_anonymous_25178: { |
| 1773 | |
| 1774 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1775 | |
| 1776 | } |
| 1777 | case GICXXPred_MI_Predicate_anonymous_25180: { |
| 1778 | |
| 1779 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1780 | |
| 1781 | } |
| 1782 | case GICXXPred_MI_Predicate_anonymous_25182: { |
| 1783 | |
| 1784 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1785 | |
| 1786 | } |
| 1787 | case GICXXPred_MI_Predicate_anonymous_25186: { |
| 1788 | |
| 1789 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1790 | |
| 1791 | } |
| 1792 | case GICXXPred_MI_Predicate_anonymous_25188: { |
| 1793 | |
| 1794 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1795 | |
| 1796 | } |
| 1797 | case GICXXPred_MI_Predicate_anonymous_25190: { |
| 1798 | |
| 1799 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1800 | |
| 1801 | } |
| 1802 | case GICXXPred_MI_Predicate_anonymous_25192: { |
| 1803 | |
| 1804 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1805 | |
| 1806 | } |
| 1807 | case GICXXPred_MI_Predicate_anonymous_25196: { |
| 1808 | |
| 1809 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1810 | |
| 1811 | } |
| 1812 | case GICXXPred_MI_Predicate_anonymous_25198: { |
| 1813 | |
| 1814 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1815 | |
| 1816 | } |
| 1817 | case GICXXPred_MI_Predicate_anonymous_25200: { |
| 1818 | |
| 1819 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1820 | |
| 1821 | } |
| 1822 | case GICXXPred_MI_Predicate_anonymous_25202: { |
| 1823 | |
| 1824 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1825 | |
| 1826 | } |
| 1827 | case GICXXPred_MI_Predicate_anonymous_25204: { |
| 1828 | |
| 1829 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1830 | |
| 1831 | } |
| 1832 | case GICXXPred_MI_Predicate_anonymous_25206: { |
| 1833 | |
| 1834 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1835 | |
| 1836 | } |
| 1837 | case GICXXPred_MI_Predicate_anonymous_25210: { |
| 1838 | |
| 1839 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1840 | |
| 1841 | } |
| 1842 | case GICXXPred_MI_Predicate_anonymous_25212: { |
| 1843 | |
| 1844 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1845 | |
| 1846 | } |
| 1847 | case GICXXPred_MI_Predicate_anonymous_25214: { |
| 1848 | |
| 1849 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1850 | |
| 1851 | } |
| 1852 | case GICXXPred_MI_Predicate_anonymous_25216: { |
| 1853 | |
| 1854 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1855 | |
| 1856 | } |
| 1857 | case GICXXPred_MI_Predicate_anonymous_25218: { |
| 1858 | |
| 1859 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1860 | |
| 1861 | } |
| 1862 | case GICXXPred_MI_Predicate_anonymous_25220: { |
| 1863 | |
| 1864 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1865 | |
| 1866 | } |
| 1867 | case GICXXPred_MI_Predicate_anonymous_25222: { |
| 1868 | |
| 1869 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1870 | |
| 1871 | } |
| 1872 | case GICXXPred_MI_Predicate_anonymous_25224: { |
| 1873 | |
| 1874 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1875 | |
| 1876 | } |
| 1877 | case GICXXPred_MI_Predicate_anonymous_25226: { |
| 1878 | |
| 1879 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1880 | |
| 1881 | } |
| 1882 | case GICXXPred_MI_Predicate_anonymous_25228: { |
| 1883 | |
| 1884 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1885 | |
| 1886 | } |
| 1887 | case GICXXPred_MI_Predicate_anonymous_25232: { |
| 1888 | |
| 1889 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1890 | |
| 1891 | } |
| 1892 | case GICXXPred_MI_Predicate_anonymous_25234: { |
| 1893 | |
| 1894 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1895 | |
| 1896 | } |
| 1897 | case GICXXPred_MI_Predicate_anonymous_25236: { |
| 1898 | |
| 1899 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1900 | |
| 1901 | } |
| 1902 | case GICXXPred_MI_Predicate_anonymous_25238: { |
| 1903 | |
| 1904 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1905 | |
| 1906 | } |
| 1907 | case GICXXPred_MI_Predicate_anonymous_25240: { |
| 1908 | |
| 1909 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1910 | |
| 1911 | } |
| 1912 | case GICXXPred_MI_Predicate_anonymous_25242: { |
| 1913 | |
| 1914 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1915 | |
| 1916 | } |
| 1917 | case GICXXPred_MI_Predicate_anonymous_25244: { |
| 1918 | |
| 1919 | return MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1920 | |
| 1921 | } |
| 1922 | case GICXXPred_MI_Predicate_anonymous_25246: { |
| 1923 | |
| 1924 | return !MF.getInfo<SIMachineFunctionInfo>()->mayNeedAGPRs(); |
| 1925 | |
| 1926 | } |
| 1927 | case GICXXPred_MI_Predicate_anonymous_35622: { |
| 1928 | return true; |
| 1929 | } |
| 1930 | case GICXXPred_MI_Predicate_anonymous_35929: { |
| 1931 | return true; |
| 1932 | } |
| 1933 | case GICXXPred_MI_Predicate_anonymous_35931: { |
| 1934 | return true; |
| 1935 | } |
| 1936 | case GICXXPred_MI_Predicate_anonymous_35965: { |
| 1937 | return true; |
| 1938 | } |
| 1939 | case GICXXPred_MI_Predicate_anonymous_36140: { |
| 1940 | return true; |
| 1941 | } |
| 1942 | case GICXXPred_MI_Predicate_anonymous_36143: { |
| 1943 | return true; |
| 1944 | } |
| 1945 | case GICXXPred_MI_Predicate_anonymous_36148: { |
| 1946 | return true; |
| 1947 | } |
| 1948 | case GICXXPred_MI_Predicate_anonymous_36152: { |
| 1949 | return true; |
| 1950 | } |
| 1951 | case GICXXPred_MI_Predicate_anonymous_36198: { |
| 1952 | return true; |
| 1953 | } |
| 1954 | case GICXXPred_MI_Predicate_anonymous_36200: { |
| 1955 | return true; |
| 1956 | } |
| 1957 | case GICXXPred_MI_Predicate_anonymous_36239: { |
| 1958 | |
| 1959 | const SITargetLowering *TLI = static_cast<const SITargetLowering *>( |
| 1960 | MF.getSubtarget().getTargetLowering()); |
| 1961 | |
| 1962 | return TLI->isCanonicalized(MI.getOperand(1).getReg(), MF) && |
| 1963 | TLI->isCanonicalized(MI.getOperand(2).getReg(), MF); |
| 1964 | |
| 1965 | llvm_unreachable("anonymous_36239 should have returned"); |
| 1966 | } |
| 1967 | case GICXXPred_MI_Predicate_anonymous_36262: { |
| 1968 | return true; |
| 1969 | } |
| 1970 | case GICXXPred_MI_Predicate_anonymous_36264: { |
| 1971 | return true; |
| 1972 | } |
| 1973 | case GICXXPred_MI_Predicate_anonymous_36272: { |
| 1974 | return true; |
| 1975 | } |
| 1976 | case GICXXPred_MI_Predicate_anonymous_36274: { |
| 1977 | return true; |
| 1978 | } |
| 1979 | case GICXXPred_MI_Predicate_anonymous_36291: { |
| 1980 | |
| 1981 | const SITargetLowering *TLI = static_cast<const SITargetLowering *>( |
| 1982 | MF.getSubtarget().getTargetLowering()); |
| 1983 | |
| 1984 | return TLI->isCanonicalized(MI.getOperand(1).getReg(), MF); |
| 1985 | |
| 1986 | llvm_unreachable("anonymous_36291 should have returned"); |
| 1987 | } |
| 1988 | case GICXXPred_MI_Predicate_anonymous_36293: { |
| 1989 | return true; |
| 1990 | } |
| 1991 | case GICXXPred_MI_Predicate_anonymous_36295: { |
| 1992 | return true; |
| 1993 | } |
| 1994 | case GICXXPred_MI_Predicate_anonymous_36297: { |
| 1995 | return true; |
| 1996 | } |
| 1997 | case GICXXPred_MI_Predicate_anonymous_36299: { |
| 1998 | return true; |
| 1999 | } |
| 2000 | case GICXXPred_MI_Predicate_csh_mask_16: { |
| 2001 | return isUnneededShiftMask(MI, 4); |
| 2002 | } |
| 2003 | case GICXXPred_MI_Predicate_csh_mask_32: { |
| 2004 | return isUnneededShiftMask(MI, 5); |
| 2005 | } |
| 2006 | case GICXXPred_MI_Predicate_csh_mask_64: { |
| 2007 | return isUnneededShiftMask(MI, 6); |
| 2008 | } |
| 2009 | case GICXXPred_MI_Predicate_fmaxnum_like_nnan: { |
| 2010 | |
| 2011 | return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI); |
| 2012 | |
| 2013 | } |
| 2014 | case GICXXPred_MI_Predicate_fminnum_like_nnan: { |
| 2015 | |
| 2016 | return isKnownNeverNaN(MI.getOperand(0).getReg(), MRI); |
| 2017 | |
| 2018 | } |
| 2019 | case GICXXPred_MI_Predicate_is_canonicalized: { |
| 2020 | |
| 2021 | const SITargetLowering *TLI = static_cast<const SITargetLowering *>( |
| 2022 | MF.getSubtarget().getTargetLowering()); |
| 2023 | const MachineOperand &Dst = MI.getOperand(0); |
| 2024 | assert(Dst.isDef()); |
| 2025 | return TLI->isCanonicalized(Dst.getReg(), MF); |
| 2026 | |
| 2027 | llvm_unreachable("is_canonicalized should have returned"); |
| 2028 | } |
| 2029 | case GICXXPred_MI_Predicate_load_align_less_than_4_local: { |
| 2030 | return (*MI.memoperands_begin())->getAlign() < 4; |
| 2031 | } |
| 2032 | case GICXXPred_MI_Predicate_load_align_less_than_4_local_m0: { |
| 2033 | return (*MI.memoperands_begin())->getAlign() < 4; |
| 2034 | } |
| 2035 | case GICXXPred_MI_Predicate_shl1_add: { |
| 2036 | return true; |
| 2037 | } |
| 2038 | case GICXXPred_MI_Predicate_shl2_add: { |
| 2039 | return true; |
| 2040 | } |
| 2041 | case GICXXPred_MI_Predicate_shl3_add: { |
| 2042 | return true; |
| 2043 | } |
| 2044 | case GICXXPred_MI_Predicate_shl4_add: { |
| 2045 | return true; |
| 2046 | } |
| 2047 | case GICXXPred_MI_Predicate_shl_0_to_4: { |
| 2048 | |
| 2049 | int64_t Imm = 0; |
| 2050 | if (!mi_match(MI.getOperand(2).getReg(), MRI, m_ICst(Imm)) && |
| 2051 | !mi_match(MI.getOperand(2).getReg(), MRI, m_Copy(m_ICst(Imm)))) |
| 2052 | return false; |
| 2053 | return (uint64_t)Imm <= 4; |
| 2054 | |
| 2055 | llvm_unreachable("shl_0_to_4 should have returned"); |
| 2056 | } |
| 2057 | case GICXXPred_MI_Predicate_smrd_extloadi8: { |
| 2058 | |
| 2059 | if (!MI.hasOneMemOperand()) |
| 2060 | return false; |
| 2061 | if (!isInstrUniform(MI)) |
| 2062 | return false; |
| 2063 | |
| 2064 | // FIXME: We should probably be caching this. |
| 2065 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2066 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2067 | |
| 2068 | if (hasVgprParts(AddrInfo)) |
| 2069 | return false; |
| 2070 | return true; |
| 2071 | |
| 2072 | llvm_unreachable("smrd_extloadi8 should have returned"); |
| 2073 | } |
| 2074 | case GICXXPred_MI_Predicate_smrd_extloadi16: { |
| 2075 | |
| 2076 | if (!MI.hasOneMemOperand()) |
| 2077 | return false; |
| 2078 | if (!isInstrUniform(MI)) |
| 2079 | return false; |
| 2080 | |
| 2081 | // FIXME: We should probably be caching this. |
| 2082 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2083 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2084 | |
| 2085 | if (hasVgprParts(AddrInfo)) |
| 2086 | return false; |
| 2087 | return true; |
| 2088 | |
| 2089 | llvm_unreachable("smrd_extloadi16 should have returned"); |
| 2090 | } |
| 2091 | case GICXXPred_MI_Predicate_smrd_load: { |
| 2092 | |
| 2093 | if (!MI.hasOneMemOperand()) |
| 2094 | return false; |
| 2095 | if (!isInstrUniform(MI)) |
| 2096 | return false; |
| 2097 | |
| 2098 | // FIXME: We should probably be caching this. |
| 2099 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2100 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2101 | |
| 2102 | if (hasVgprParts(AddrInfo)) |
| 2103 | return false; |
| 2104 | return true; |
| 2105 | |
| 2106 | llvm_unreachable("smrd_load should have returned"); |
| 2107 | } |
| 2108 | case GICXXPred_MI_Predicate_smrd_prefetch: { |
| 2109 | |
| 2110 | return isInstrUniform(MI); |
| 2111 | |
| 2112 | } |
| 2113 | case GICXXPred_MI_Predicate_smrd_sextloadi8: { |
| 2114 | |
| 2115 | if (!MI.hasOneMemOperand()) |
| 2116 | return false; |
| 2117 | if (!isInstrUniform(MI)) |
| 2118 | return false; |
| 2119 | |
| 2120 | // FIXME: We should probably be caching this. |
| 2121 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2122 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2123 | |
| 2124 | if (hasVgprParts(AddrInfo)) |
| 2125 | return false; |
| 2126 | return true; |
| 2127 | |
| 2128 | llvm_unreachable("smrd_sextloadi8 should have returned"); |
| 2129 | } |
| 2130 | case GICXXPred_MI_Predicate_smrd_sextloadi16: { |
| 2131 | |
| 2132 | if (!MI.hasOneMemOperand()) |
| 2133 | return false; |
| 2134 | if (!isInstrUniform(MI)) |
| 2135 | return false; |
| 2136 | |
| 2137 | // FIXME: We should probably be caching this. |
| 2138 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2139 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2140 | |
| 2141 | if (hasVgprParts(AddrInfo)) |
| 2142 | return false; |
| 2143 | return true; |
| 2144 | |
| 2145 | llvm_unreachable("smrd_sextloadi16 should have returned"); |
| 2146 | } |
| 2147 | case GICXXPred_MI_Predicate_smrd_zextloadi8: { |
| 2148 | |
| 2149 | if (!MI.hasOneMemOperand()) |
| 2150 | return false; |
| 2151 | if (!isInstrUniform(MI)) |
| 2152 | return false; |
| 2153 | |
| 2154 | // FIXME: We should probably be caching this. |
| 2155 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2156 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2157 | |
| 2158 | if (hasVgprParts(AddrInfo)) |
| 2159 | return false; |
| 2160 | return true; |
| 2161 | |
| 2162 | llvm_unreachable("smrd_zextloadi8 should have returned"); |
| 2163 | } |
| 2164 | case GICXXPred_MI_Predicate_smrd_zextloadi16: { |
| 2165 | |
| 2166 | if (!MI.hasOneMemOperand()) |
| 2167 | return false; |
| 2168 | if (!isInstrUniform(MI)) |
| 2169 | return false; |
| 2170 | |
| 2171 | // FIXME: We should probably be caching this. |
| 2172 | SmallVector<GEPInfo, 4> AddrInfo; |
| 2173 | getAddrModeInfo(MI, MRI, AddrInfo); |
| 2174 | |
| 2175 | if (hasVgprParts(AddrInfo)) |
| 2176 | return false; |
| 2177 | return true; |
| 2178 | |
| 2179 | llvm_unreachable("smrd_zextloadi16 should have returned"); |
| 2180 | } |
| 2181 | case GICXXPred_MI_Predicate_store_align_less_than_4_local: { |
| 2182 | return (*MI.memoperands_begin())->getAlign() < 4; |
| 2183 | } |
| 2184 | case GICXXPred_MI_Predicate_store_align_less_than_4_local_m0: { |
| 2185 | return (*MI.memoperands_begin())->getAlign() < 4; |
| 2186 | } |
| 2187 | } |
| 2188 | llvm_unreachable("Unknown predicate"); |
| 2189 | return false; |
| 2190 | } |
| 2191 | // PatFrag predicates. |
| 2192 | enum { |
| 2193 | GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask = GICXXPred_Invalid + 1, |
| 2194 | GICXXPred_I64_Predicate_NegSubInlineConst32, |
| 2195 | GICXXPred_I64_Predicate_NegSubInlineIntConst16, |
| 2196 | GICXXPred_I64_Predicate_SIMM16bit, |
| 2197 | GICXXPred_I64_Predicate_ShiftAmt32Imm, |
| 2198 | GICXXPred_I64_Predicate_i32imm_one, |
| 2199 | GICXXPred_I64_Predicate_i32imm_zero, |
| 2200 | GICXXPred_I64_Predicate_i64imm_32bit, |
| 2201 | }; |
| 2202 | bool AMDGPUInstructionSelector::testImmPredicate_I64(unsigned PredicateID, int64_t Imm) const { |
| 2203 | switch (PredicateID) { |
| 2204 | case GICXXPred_I64_Predicate_IMMZeroBasedBitfieldMask: { |
| 2205 | |
| 2206 | return isMask_32(Imm); |
| 2207 | |
| 2208 | } |
| 2209 | case GICXXPred_I64_Predicate_NegSubInlineConst32: { |
| 2210 | |
| 2211 | return Imm < -16 && Imm >= -64; |
| 2212 | |
| 2213 | } |
| 2214 | case GICXXPred_I64_Predicate_NegSubInlineIntConst16: { |
| 2215 | |
| 2216 | return Imm < -16 && Imm >= -64; |
| 2217 | |
| 2218 | } |
| 2219 | case GICXXPred_I64_Predicate_SIMM16bit: { |
| 2220 | return isInt<16>(Imm) || isUInt<16>(Imm); |
| 2221 | } |
| 2222 | case GICXXPred_I64_Predicate_ShiftAmt32Imm: { |
| 2223 | |
| 2224 | return Imm < 32; |
| 2225 | |
| 2226 | } |
| 2227 | case GICXXPred_I64_Predicate_i32imm_one: { |
| 2228 | |
| 2229 | return Imm == 1; |
| 2230 | |
| 2231 | } |
| 2232 | case GICXXPred_I64_Predicate_i32imm_zero: { |
| 2233 | |
| 2234 | return Imm == 0; |
| 2235 | |
| 2236 | } |
| 2237 | case GICXXPred_I64_Predicate_i64imm_32bit: { |
| 2238 | |
| 2239 | return (Imm & 0xffffffffULL) == static_cast<uint64_t>(Imm); |
| 2240 | |
| 2241 | } |
| 2242 | } |
| 2243 | llvm_unreachable("Unknown predicate"); |
| 2244 | return false; |
| 2245 | } |
| 2246 | // PatFrag predicates. |
| 2247 | enum { |
| 2248 | GICXXPred_APFloat_Predicate_InlineImmFP32 = GICXXPred_Invalid + 1, |
| 2249 | GICXXPred_APFloat_Predicate_InlineImmFP64, |
| 2250 | GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64, |
| 2251 | GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64, |
| 2252 | }; |
| 2253 | bool AMDGPUInstructionSelector::testImmPredicate_APFloat(unsigned PredicateID, const APFloat & Imm) const { |
| 2254 | switch (PredicateID) { |
| 2255 | case GICXXPred_APFloat_Predicate_InlineImmFP32: { |
| 2256 | |
| 2257 | return isInlineImmediate(Imm); |
| 2258 | |
| 2259 | } |
| 2260 | case GICXXPred_APFloat_Predicate_InlineImmFP64: { |
| 2261 | |
| 2262 | return isInlineImmediate(Imm); |
| 2263 | |
| 2264 | } |
| 2265 | case GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64: { |
| 2266 | |
| 2267 | if (!Imm.isNegative()) |
| 2268 | return false; |
| 2269 | int Exp = Imm.getExactLog2Abs(); |
| 2270 | // Prefer leaving the FP inline immediates as they are. |
| 2271 | // 0.5, 1.0, 2.0, 4.0 |
| 2272 | |
| 2273 | // For f64 ldexp is always better than materializing a 64-bit |
| 2274 | // constant. |
| 2275 | return Exp != INT_MIN && (Exp < -1 || Exp > 2); |
| 2276 | |
| 2277 | llvm_unreachable("fpimm_neg_pow2_prefer_ldexp_f64 should have returned"); |
| 2278 | } |
| 2279 | case GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64: { |
| 2280 | |
| 2281 | if (Imm.isNegative()) |
| 2282 | return false; |
| 2283 | |
| 2284 | int Exp = Imm.getExactLog2Abs(); |
| 2285 | // Prefer leaving the FP inline immediates as they are. |
| 2286 | // 0.5, 1.0, 2.0, 4.0 |
| 2287 | |
| 2288 | // For f64 ldexp is always better than materializing a 64-bit |
| 2289 | // constant. |
| 2290 | return Exp != INT_MIN && (Exp < -1 || Exp > 2); |
| 2291 | |
| 2292 | llvm_unreachable("fpimm_pos_pow2_prefer_ldexp_f64 should have returned"); |
| 2293 | } |
| 2294 | } |
| 2295 | llvm_unreachable("Unknown predicate"); |
| 2296 | return false; |
| 2297 | } |
| 2298 | // PatFrag predicates. |
| 2299 | enum { |
| 2300 | GICXXPred_APInt_Predicate_InlineImm64 = GICXXPred_Invalid + 1, |
| 2301 | }; |
| 2302 | bool AMDGPUInstructionSelector::testImmPredicate_APInt(unsigned PredicateID, const APInt & Imm) const { |
| 2303 | switch (PredicateID) { |
| 2304 | case GICXXPred_APInt_Predicate_InlineImm64: { |
| 2305 | |
| 2306 | return isInlineImmediate(Imm); |
| 2307 | |
| 2308 | } |
| 2309 | } |
| 2310 | llvm_unreachable("Unknown predicate"); |
| 2311 | return false; |
| 2312 | } |
| 2313 | bool AMDGPUInstructionSelector::testSimplePredicate(unsigned) const { |
| 2314 | llvm_unreachable("AMDGPUInstructionSelector does not support simple predicates!"); |
| 2315 | return false; |
| 2316 | } |
| 2317 | // Custom renderers. |
| 2318 | enum { |
| 2319 | GICR_Invalid, |
| 2320 | GICR_renderBitcastImm, |
| 2321 | GICR_renderExtractCPol, |
| 2322 | GICR_renderExtractCpolSetGLC, |
| 2323 | GICR_renderExtractSWZ, |
| 2324 | GICR_renderFPPow2ToExponent, |
| 2325 | GICR_renderFrameIndex, |
| 2326 | GICR_renderNegateImm, |
| 2327 | GICR_renderOpSelTImm, |
| 2328 | GICR_renderPopcntImm, |
| 2329 | GICR_renderTruncTImm, |
| 2330 | }; |
| 2331 | AMDGPUInstructionSelector::CustomRendererFn |
| 2332 | AMDGPUInstructionSelector::CustomRenderers[] = { |
| 2333 | nullptr, // GICR_Invalid |
| 2334 | &AMDGPUInstructionSelector::renderBitcastImm, |
| 2335 | &AMDGPUInstructionSelector::renderExtractCPol, |
| 2336 | &AMDGPUInstructionSelector::renderExtractCpolSetGLC, |
| 2337 | &AMDGPUInstructionSelector::renderExtractSWZ, |
| 2338 | &AMDGPUInstructionSelector::renderFPPow2ToExponent, |
| 2339 | &AMDGPUInstructionSelector::renderFrameIndex, |
| 2340 | &AMDGPUInstructionSelector::renderNegateImm, |
| 2341 | &AMDGPUInstructionSelector::renderOpSelTImm, |
| 2342 | &AMDGPUInstructionSelector::renderPopcntImm, |
| 2343 | &AMDGPUInstructionSelector::renderTruncTImm, |
| 2344 | }; |
| 2345 | |
| 2346 | bool AMDGPUInstructionSelector::selectImpl(MachineInstr &I, CodeGenCoverage &CoverageInfo) const { |
| 2347 | const PredicateBitset AvailableFeatures = getAvailableFeatures(); |
| 2348 | MachineIRBuilder B(I); |
| 2349 | State.MIs.clear(); |
| 2350 | State.MIs.push_back(&I); |
| 2351 | |
| 2352 | if (executeMatchTable(*this, State, ExecInfo, B, getMatchTable(), TII, MF->getRegInfo(), TRI, RBI, AvailableFeatures, &CoverageInfo)) { |
| 2353 | return true; |
| 2354 | } |
| 2355 | |
| 2356 | return false; |
| 2357 | } |
| 2358 | |
| 2359 | bool AMDGPUInstructionSelector::runCustomAction(unsigned, const MatcherState&, NewMIVector &) const { |
| 2360 | llvm_unreachable("AMDGPUInstructionSelector does not support custom C++ actions!"); |
| 2361 | } |
| 2362 | #if __BYTE_ORDER__ == __ORDER_LITTLE_ENDIAN__ |
| 2363 | #define GIMT_Encode2(Val) uint8_t(Val), uint8_t((uint16_t)Val >> 8) |
| 2364 | #define GIMT_Encode4(Val) uint8_t(Val), uint8_t((uint32_t)Val >> 8), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 24) |
| 2365 | #define GIMT_Encode8(Val) uint8_t(Val), uint8_t((uint64_t)Val >> 8), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 56) |
| 2366 | #else |
| 2367 | #define GIMT_Encode2(Val) uint8_t((uint16_t)Val >> 8), uint8_t(Val) |
| 2368 | #define GIMT_Encode4(Val) uint8_t((uint32_t)Val >> 24), uint8_t((uint32_t)Val >> 16), uint8_t((uint32_t)Val >> 8), uint8_t(Val) |
| 2369 | #define GIMT_Encode8(Val) uint8_t((uint64_t)Val >> 56), uint8_t((uint64_t)Val >> 48), uint8_t((uint64_t)Val >> 40), uint8_t((uint64_t)Val >> 32), uint8_t((uint64_t)Val >> 24), uint8_t((uint64_t)Val >> 16), uint8_t((uint64_t)Val >> 8), uint8_t(Val) |
| 2370 | #endif |
| 2371 | const uint8_t *AMDGPUInstructionSelector::getMatchTable() const { |
| 2372 | constexpr static uint8_t MatchTable0[] = { |
| 2373 | GIM_SwitchOpcode, /*MI*/0, /*[*/GIMT_Encode2(51), GIMT_Encode2(3656), /*)*//*default:*//*Label 168*/ GIMT_Encode4(585939), |
| 2374 | /*TargetOpcode::G_ADD*//*Label 0*/ GIMT_Encode4(14430), |
| 2375 | /*TargetOpcode::G_SUB*//*Label 1*/ GIMT_Encode4(18064), |
| 2376 | /*TargetOpcode::G_MUL*//*Label 2*/ GIMT_Encode4(18565), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2377 | /*TargetOpcode::G_AND*//*Label 3*/ GIMT_Encode4(18851), |
| 2378 | /*TargetOpcode::G_OR*//*Label 4*/ GIMT_Encode4(19807), |
| 2379 | /*TargetOpcode::G_XOR*//*Label 5*/ GIMT_Encode4(34275), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2380 | /*TargetOpcode::G_FRAME_INDEX*//*Label 6*/ GIMT_Encode4(38639), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2381 | /*TargetOpcode::G_BUILD_VECTOR*//*Label 7*/ GIMT_Encode4(38691), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2382 | /*TargetOpcode::G_BITCAST*//*Label 8*/ GIMT_Encode4(41726), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2383 | /*TargetOpcode::G_INTRINSIC_TRUNC*//*Label 9*/ GIMT_Encode4(50199), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2384 | /*TargetOpcode::G_INTRINSIC_ROUNDEVEN*//*Label 10*/ GIMT_Encode4(50527), |
| 2385 | /*TargetOpcode::G_READCYCLECOUNTER*//*Label 11*/ GIMT_Encode4(50855), |
| 2386 | /*TargetOpcode::G_READSTEADYCOUNTER*//*Label 12*/ GIMT_Encode4(50995), |
| 2387 | /*TargetOpcode::G_LOAD*//*Label 13*/ GIMT_Encode4(51053), |
| 2388 | /*TargetOpcode::G_SEXTLOAD*//*Label 14*/ GIMT_Encode4(126442), |
| 2389 | /*TargetOpcode::G_ZEXTLOAD*//*Label 15*/ GIMT_Encode4(130408), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2390 | /*TargetOpcode::G_STORE*//*Label 16*/ GIMT_Encode4(134250), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2391 | /*TargetOpcode::G_ATOMIC_CMPXCHG*//*Label 17*/ GIMT_Encode4(170156), |
| 2392 | /*TargetOpcode::G_ATOMICRMW_XCHG*//*Label 18*/ GIMT_Encode4(171282), |
| 2393 | /*TargetOpcode::G_ATOMICRMW_ADD*//*Label 19*/ GIMT_Encode4(173494), |
| 2394 | /*TargetOpcode::G_ATOMICRMW_SUB*//*Label 20*/ GIMT_Encode4(176006), |
| 2395 | /*TargetOpcode::G_ATOMICRMW_AND*//*Label 21*/ GIMT_Encode4(178518), GIMT_Encode4(0), |
| 2396 | /*TargetOpcode::G_ATOMICRMW_OR*//*Label 22*/ GIMT_Encode4(181030), |
| 2397 | /*TargetOpcode::G_ATOMICRMW_XOR*//*Label 23*/ GIMT_Encode4(183542), |
| 2398 | /*TargetOpcode::G_ATOMICRMW_MAX*//*Label 24*/ GIMT_Encode4(186054), |
| 2399 | /*TargetOpcode::G_ATOMICRMW_MIN*//*Label 25*/ GIMT_Encode4(188566), |
| 2400 | /*TargetOpcode::G_ATOMICRMW_UMAX*//*Label 26*/ GIMT_Encode4(191078), |
| 2401 | /*TargetOpcode::G_ATOMICRMW_UMIN*//*Label 27*/ GIMT_Encode4(193590), |
| 2402 | /*TargetOpcode::G_ATOMICRMW_FADD*//*Label 28*/ GIMT_Encode4(196102), GIMT_Encode4(0), |
| 2403 | /*TargetOpcode::G_ATOMICRMW_FMAX*//*Label 29*/ GIMT_Encode4(198961), |
| 2404 | /*TargetOpcode::G_ATOMICRMW_FMIN*//*Label 30*/ GIMT_Encode4(201607), |
| 2405 | /*TargetOpcode::G_ATOMICRMW_UINC_WRAP*//*Label 31*/ GIMT_Encode4(204253), |
| 2406 | /*TargetOpcode::G_ATOMICRMW_UDEC_WRAP*//*Label 32*/ GIMT_Encode4(206765), |
| 2407 | /*TargetOpcode::G_FENCE*//*Label 33*/ GIMT_Encode4(209277), |
| 2408 | /*TargetOpcode::G_PREFETCH*//*Label 34*/ GIMT_Encode4(209296), |
| 2409 | /*TargetOpcode::G_BRCOND*//*Label 35*/ GIMT_Encode4(209732), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2410 | /*TargetOpcode::G_INTRINSIC*//*Label 36*/ GIMT_Encode4(209760), |
| 2411 | /*TargetOpcode::G_INTRINSIC_W_SIDE_EFFECTS*//*Label 37*/ GIMT_Encode4(222900), |
| 2412 | /*TargetOpcode::G_INTRINSIC_CONVERGENT*//*Label 38*/ GIMT_Encode4(231242), |
| 2413 | /*TargetOpcode::G_INTRINSIC_CONVERGENT_W_SIDE_EFFECTS*//*Label 39*/ GIMT_Encode4(248434), |
| 2414 | /*TargetOpcode::G_ANYEXT*//*Label 40*/ GIMT_Encode4(249649), |
| 2415 | /*TargetOpcode::G_TRUNC*//*Label 41*/ GIMT_Encode4(249978), |
| 2416 | /*TargetOpcode::G_CONSTANT*//*Label 42*/ GIMT_Encode4(250103), |
| 2417 | /*TargetOpcode::G_FCONSTANT*//*Label 43*/ GIMT_Encode4(250210), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2418 | /*TargetOpcode::G_SEXT*//*Label 44*/ GIMT_Encode4(250297), GIMT_Encode4(0), |
| 2419 | /*TargetOpcode::G_ZEXT*//*Label 45*/ GIMT_Encode4(251088), |
| 2420 | /*TargetOpcode::G_SHL*//*Label 46*/ GIMT_Encode4(252676), |
| 2421 | /*TargetOpcode::G_LSHR*//*Label 47*/ GIMT_Encode4(253866), |
| 2422 | /*TargetOpcode::G_ASHR*//*Label 48*/ GIMT_Encode4(254818), GIMT_Encode4(0), |
| 2423 | /*TargetOpcode::G_FSHR*//*Label 49*/ GIMT_Encode4(255770), |
| 2424 | /*TargetOpcode::G_ROTR*//*Label 50*/ GIMT_Encode4(255815), GIMT_Encode4(0), |
| 2425 | /*TargetOpcode::G_ICMP*//*Label 51*/ GIMT_Encode4(255847), |
| 2426 | /*TargetOpcode::G_FCMP*//*Label 52*/ GIMT_Encode4(256869), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2427 | /*TargetOpcode::G_SELECT*//*Label 53*/ GIMT_Encode4(260164), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2428 | /*TargetOpcode::G_UMULH*//*Label 54*/ GIMT_Encode4(260368), |
| 2429 | /*TargetOpcode::G_SMULH*//*Label 55*/ GIMT_Encode4(260477), |
| 2430 | /*TargetOpcode::G_UADDSAT*//*Label 56*/ GIMT_Encode4(260586), |
| 2431 | /*TargetOpcode::G_SADDSAT*//*Label 57*/ GIMT_Encode4(260852), |
| 2432 | /*TargetOpcode::G_USUBSAT*//*Label 58*/ GIMT_Encode4(261054), |
| 2433 | /*TargetOpcode::G_SSUBSAT*//*Label 59*/ GIMT_Encode4(261320), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2434 | /*TargetOpcode::G_FADD*//*Label 60*/ GIMT_Encode4(261522), |
| 2435 | /*TargetOpcode::G_FSUB*//*Label 61*/ GIMT_Encode4(262880), |
| 2436 | /*TargetOpcode::G_FMUL*//*Label 62*/ GIMT_Encode4(263244), |
| 2437 | /*TargetOpcode::G_FMA*//*Label 63*/ GIMT_Encode4(264630), |
| 2438 | /*TargetOpcode::G_FMAD*//*Label 64*/ GIMT_Encode4(266271), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2439 | /*TargetOpcode::G_FPOW*//*Label 65*/ GIMT_Encode4(267217), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2440 | /*TargetOpcode::G_FEXP2*//*Label 66*/ GIMT_Encode4(267335), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2441 | /*TargetOpcode::G_FLOG2*//*Label 67*/ GIMT_Encode4(267558), GIMT_Encode4(0), |
| 2442 | /*TargetOpcode::G_FLDEXP*//*Label 68*/ GIMT_Encode4(267781), GIMT_Encode4(0), |
| 2443 | /*TargetOpcode::G_FNEG*//*Label 69*/ GIMT_Encode4(268074), |
| 2444 | /*TargetOpcode::G_FPEXT*//*Label 70*/ GIMT_Encode4(269943), |
| 2445 | /*TargetOpcode::G_FPTRUNC*//*Label 71*/ GIMT_Encode4(270243), |
| 2446 | /*TargetOpcode::G_FPTOSI*//*Label 72*/ GIMT_Encode4(270881), |
| 2447 | /*TargetOpcode::G_FPTOUI*//*Label 73*/ GIMT_Encode4(271445), |
| 2448 | /*TargetOpcode::G_SITOFP*//*Label 74*/ GIMT_Encode4(272009), |
| 2449 | /*TargetOpcode::G_UITOFP*//*Label 75*/ GIMT_Encode4(272556), |
| 2450 | /*TargetOpcode::G_FABS*//*Label 76*/ GIMT_Encode4(273103), |
| 2451 | /*TargetOpcode::G_FCOPYSIGN*//*Label 77*/ GIMT_Encode4(273907), |
| 2452 | /*TargetOpcode::G_IS_FPCLASS*//*Label 78*/ GIMT_Encode4(274464), |
| 2453 | /*TargetOpcode::G_FCANONICALIZE*//*Label 79*/ GIMT_Encode4(274733), |
| 2454 | /*TargetOpcode::G_FMINNUM*//*Label 80*/ GIMT_Encode4(275933), |
| 2455 | /*TargetOpcode::G_FMAXNUM*//*Label 81*/ GIMT_Encode4(312272), |
| 2456 | /*TargetOpcode::G_FMINNUM_IEEE*//*Label 82*/ GIMT_Encode4(348611), |
| 2457 | /*TargetOpcode::G_FMAXNUM_IEEE*//*Label 83*/ GIMT_Encode4(384950), |
| 2458 | /*TargetOpcode::G_FMINIMUM*//*Label 84*/ GIMT_Encode4(421289), |
| 2459 | /*TargetOpcode::G_FMAXIMUM*//*Label 85*/ GIMT_Encode4(422759), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2460 | /*TargetOpcode::G_GET_FPMODE*//*Label 86*/ GIMT_Encode4(424229), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2461 | /*TargetOpcode::G_PTR_ADD*//*Label 87*/ GIMT_Encode4(424353), GIMT_Encode4(0), |
| 2462 | /*TargetOpcode::G_SMIN*//*Label 88*/ GIMT_Encode4(424430), |
| 2463 | /*TargetOpcode::G_SMAX*//*Label 89*/ GIMT_Encode4(427534), |
| 2464 | /*TargetOpcode::G_UMIN*//*Label 90*/ GIMT_Encode4(430800), |
| 2465 | /*TargetOpcode::G_UMAX*//*Label 91*/ GIMT_Encode4(433904), |
| 2466 | /*TargetOpcode::G_ABS*//*Label 92*/ GIMT_Encode4(437008), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2467 | /*TargetOpcode::G_BR*//*Label 93*/ GIMT_Encode4(437145), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2468 | /*TargetOpcode::G_CTTZ_ZERO_UNDEF*//*Label 94*/ GIMT_Encode4(437179), GIMT_Encode4(0), |
| 2469 | /*TargetOpcode::G_CTLZ_ZERO_UNDEF*//*Label 95*/ GIMT_Encode4(437278), |
| 2470 | /*TargetOpcode::G_CTPOP*//*Label 96*/ GIMT_Encode4(437380), |
| 2471 | /*TargetOpcode::G_BSWAP*//*Label 97*/ GIMT_Encode4(437592), |
| 2472 | /*TargetOpcode::G_BITREVERSE*//*Label 98*/ GIMT_Encode4(438539), |
| 2473 | /*TargetOpcode::G_FCEIL*//*Label 99*/ GIMT_Encode4(438787), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2474 | /*TargetOpcode::G_FSQRT*//*Label 100*/ GIMT_Encode4(439115), |
| 2475 | /*TargetOpcode::G_FFLOOR*//*Label 101*/ GIMT_Encode4(439407), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2476 | /*TargetOpcode::G_STRICT_FADD*//*Label 102*/ GIMT_Encode4(439921), |
| 2477 | /*TargetOpcode::G_STRICT_FSUB*//*Label 103*/ GIMT_Encode4(440883), |
| 2478 | /*TargetOpcode::G_STRICT_FMUL*//*Label 104*/ GIMT_Encode4(441247), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2479 | /*TargetOpcode::G_STRICT_FMA*//*Label 105*/ GIMT_Encode4(442515), GIMT_Encode4(0), |
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GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2481 | /*AMDGPU::G_AMDGPU_ATOMIC_CMPXCHG*//*Label 107*/ GIMT_Encode4(443696), |
| 2482 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_ADD*//*Label 108*/ GIMT_Encode4(445976), |
| 2483 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_AND*//*Label 109*/ GIMT_Encode4(448360), |
| 2484 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_CMPSWAP*//*Label 110*/ GIMT_Encode4(450744), |
| 2485 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_COND_SUB_U32*//*Label 111*/ GIMT_Encode4(455038), |
| 2486 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_DEC*//*Label 112*/ GIMT_Encode4(455655), |
| 2487 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FADD*//*Label 113*/ GIMT_Encode4(458039), |
| 2488 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMAX*//*Label 114*/ GIMT_Encode4(462865), |
| 2489 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_FMIN*//*Label 115*/ GIMT_Encode4(466481), |
| 2490 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_INC*//*Label 116*/ GIMT_Encode4(470097), |
| 2491 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_OR*//*Label 117*/ GIMT_Encode4(472481), |
| 2492 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMAX*//*Label 118*/ GIMT_Encode4(474865), |
| 2493 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SMIN*//*Label 119*/ GIMT_Encode4(477249), |
| 2494 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SUB*//*Label 120*/ GIMT_Encode4(479633), |
| 2495 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_SWAP*//*Label 121*/ GIMT_Encode4(482017), |
| 2496 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMAX*//*Label 122*/ GIMT_Encode4(485561), |
| 2497 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_UMIN*//*Label 123*/ GIMT_Encode4(487945), |
| 2498 | /*AMDGPU::G_AMDGPU_BUFFER_ATOMIC_XOR*//*Label 124*/ GIMT_Encode4(490329), |
| 2499 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD*//*Label 125*/ GIMT_Encode4(492713), |
| 2500 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT*//*Label 126*/ GIMT_Encode4(508635), |
| 2501 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_D16*//*Label 127*/ GIMT_Encode4(513543), |
| 2502 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_FORMAT_TFE*//*Label 128*/ GIMT_Encode4(521288), |
| 2503 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE*//*Label 129*/ GIMT_Encode4(523808), |
| 2504 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SBYTE_TFE*//*Label 130*/ GIMT_Encode4(524414), |
| 2505 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT*//*Label 131*/ GIMT_Encode4(525020), |
| 2506 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_SSHORT_TFE*//*Label 132*/ GIMT_Encode4(525626), |
| 2507 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_TFE*//*Label 133*/ GIMT_Encode4(526232), |
| 2508 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE*//*Label 134*/ GIMT_Encode4(528752), |
| 2509 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_UBYTE_TFE*//*Label 135*/ GIMT_Encode4(529358), |
| 2510 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT*//*Label 136*/ GIMT_Encode4(529964), |
| 2511 | /*AMDGPU::G_AMDGPU_BUFFER_LOAD_USHORT_TFE*//*Label 137*/ GIMT_Encode4(530570), |
| 2512 | /*AMDGPU::G_AMDGPU_BUFFER_STORE*//*Label 138*/ GIMT_Encode4(531176), |
| 2513 | /*AMDGPU::G_AMDGPU_BUFFER_STORE_BYTE*//*Label 139*/ GIMT_Encode4(547042), |
| 2514 | /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT*//*Label 140*/ GIMT_Encode4(547644), |
| 2515 | /*AMDGPU::G_AMDGPU_BUFFER_STORE_FORMAT_D16*//*Label 141*/ GIMT_Encode4(553132), |
| 2516 | /*AMDGPU::G_AMDGPU_BUFFER_STORE_SHORT*//*Label 142*/ GIMT_Encode4(559397), |
| 2517 | /*AMDGPU::G_AMDGPU_CLAMP*//*Label 143*/ GIMT_Encode4(559999), |
| 2518 | /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE0*//*Label 144*/ GIMT_Encode4(560938), |
| 2519 | /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE1*//*Label 145*/ GIMT_Encode4(560983), |
| 2520 | /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE2*//*Label 146*/ GIMT_Encode4(561028), |
| 2521 | /*AMDGPU::G_AMDGPU_CVT_F32_UBYTE3*//*Label 147*/ GIMT_Encode4(561073), |
| 2522 | /*AMDGPU::G_AMDGPU_CVT_PK_I16_I32*//*Label 148*/ GIMT_Encode4(561118), |
| 2523 | /*AMDGPU::G_AMDGPU_FFBH_U32*//*Label 149*/ GIMT_Encode4(561148), |
| 2524 | /*AMDGPU::G_AMDGPU_FFBL_B32*//*Label 150*/ GIMT_Encode4(561250), |
| 2525 | /*AMDGPU::G_AMDGPU_FMAX_LEGACY*//*Label 151*/ GIMT_Encode4(561349), |
| 2526 | /*AMDGPU::G_AMDGPU_FMED3*//*Label 152*/ GIMT_Encode4(561422), |
| 2527 | /*AMDGPU::G_AMDGPU_FMIN_LEGACY*//*Label 153*/ GIMT_Encode4(561618), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2528 | /*AMDGPU::G_AMDGPU_RCP_IFLAG*//*Label 154*/ GIMT_Encode4(561691), |
| 2529 | /*AMDGPU::G_AMDGPU_SMED3*//*Label 155*/ GIMT_Encode4(561741), |
| 2530 | /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD*//*Label 156*/ GIMT_Encode4(561889), |
| 2531 | /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SBYTE*//*Label 157*/ GIMT_Encode4(564191), |
| 2532 | /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_SSHORT*//*Label 158*/ GIMT_Encode4(564329), |
| 2533 | /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_UBYTE*//*Label 159*/ GIMT_Encode4(564467), |
| 2534 | /*AMDGPU::G_AMDGPU_S_BUFFER_LOAD_USHORT*//*Label 160*/ GIMT_Encode4(564605), GIMT_Encode4(0), GIMT_Encode4(0), |
| 2535 | /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT*//*Label 161*/ GIMT_Encode4(564743), |
| 2536 | /*AMDGPU::G_AMDGPU_TBUFFER_LOAD_FORMAT_D16*//*Label 162*/ GIMT_Encode4(570227), |
| 2537 | /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT*//*Label 163*/ GIMT_Encode4(575656), |
| 2538 | /*AMDGPU::G_AMDGPU_TBUFFER_STORE_FORMAT_D16*//*Label 164*/ GIMT_Encode4(581124), |
| 2539 | /*AMDGPU::G_AMDGPU_UMED3*//*Label 165*/ GIMT_Encode4(585729), GIMT_Encode4(0), |
| 2540 | /*AMDGPU::G_FPTRUNC_ROUND_DOWNWARD*//*Label 166*/ GIMT_Encode4(585877), |
| 2541 | /*AMDGPU::G_FPTRUNC_ROUND_UPWARD*//*Label 167*/ GIMT_Encode4(585908), |
| 2542 | // Label 0: @14430 |
| 2543 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 174*/ GIMT_Encode4(18063), |
| 2544 | /*GILLT_s1*//*Label 169*/ GIMT_Encode4(14461), |
| 2545 | /*GILLT_s16*//*Label 170*/ GIMT_Encode4(14580), |
| 2546 | /*GILLT_s32*//*Label 171*/ GIMT_Encode4(14853), |
| 2547 | /*GILLT_s64*//*Label 172*/ GIMT_Encode4(17586), |
| 2548 | /*GILLT_v2s16*//*Label 173*/ GIMT_Encode4(17793), |
| 2549 | // Label 169: @14461 |
| 2550 | GIM_Try, /*On fail goto*//*Label 175*/ GIMT_Encode4(14579), |
| 2551 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 2552 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 2553 | GIM_Try, /*On fail goto*//*Label 176*/ GIMT_Encode4(14500), // Rule ID 7168 // |
| 2554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 2555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 2556 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2557 | // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] }) => (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0) |
| 2558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64), |
| 2559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2560 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 2561 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2562 | GIR_RootConstrainSelectedInstOperands, |
| 2563 | // GIR_Coverage, 7168, |
| 2564 | GIR_EraseRootFromParent_Done, |
| 2565 | // Label 176: @14500 |
| 2566 | GIM_Try, /*On fail goto*//*Label 177*/ GIMT_Encode4(14528), // Rule ID 7175 // |
| 2567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 2568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2569 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 2570 | // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] }) => (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0) |
| 2571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32), |
| 2572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2573 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 2574 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2575 | GIR_RootConstrainSelectedInstOperands, |
| 2576 | // GIR_Coverage, 7175, |
| 2577 | GIR_EraseRootFromParent_Done, |
| 2578 | // Label 177: @14528 |
| 2579 | GIM_Try, /*On fail goto*//*Label 178*/ GIMT_Encode4(14553), // Rule ID 7166 // |
| 2580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 2581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 2582 | // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 2583 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64), |
| 2584 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 2585 | GIR_RootConstrainSelectedInstOperands, |
| 2586 | // GIR_Coverage, 7166, |
| 2587 | GIR_Done, |
| 2588 | // Label 178: @14553 |
| 2589 | GIM_Try, /*On fail goto*//*Label 179*/ GIMT_Encode4(14578), // Rule ID 7173 // |
| 2590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 2591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2592 | // (add:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 2593 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 2594 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 2595 | GIR_RootConstrainSelectedInstOperands, |
| 2596 | // GIR_Coverage, 7173, |
| 2597 | GIR_Done, |
| 2598 | // Label 179: @14578 |
| 2599 | GIM_Reject, |
| 2600 | // Label 175: @14579 |
| 2601 | GIM_Reject, |
| 2602 | // Label 170: @14580 |
| 2603 | GIM_Try, /*On fail goto*//*Label 180*/ GIMT_Encode4(14852), |
| 2604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 2605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 2606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2607 | GIM_Try, /*On fail goto*//*Label 181*/ GIMT_Encode4(14634), // Rule ID 2166 // |
| 2608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 2609 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2610 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2611 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16), |
| 2612 | // MIs[1] Operand 1 |
| 2613 | // No operand predicates |
| 2614 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2615 | // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1) => (V_SUB_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1)) |
| 2616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64), |
| 2617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2618 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 2619 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 2620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2621 | GIR_RootConstrainSelectedInstOperands, |
| 2622 | // GIR_Coverage, 2166, |
| 2623 | GIR_EraseRootFromParent_Done, |
| 2624 | // Label 181: @14634 |
| 2625 | GIM_Try, /*On fail goto*//*Label 182*/ GIMT_Encode4(14682), // Rule ID 2269 // |
| 2626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 2627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2628 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2629 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16), |
| 2630 | // MIs[1] Operand 1 |
| 2631 | // No operand predicates |
| 2632 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2633 | // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1) => (V_SUB_NC_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1), 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 2634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64), |
| 2635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2637 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 2638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2639 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 2640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2642 | GIR_RootConstrainSelectedInstOperands, |
| 2643 | // GIR_Coverage, 2269, |
| 2644 | GIR_EraseRootFromParent_Done, |
| 2645 | // Label 182: @14682 |
| 2646 | GIM_Try, /*On fail goto*//*Label 183*/ GIMT_Encode4(14728), // Rule ID 2204 // |
| 2647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9), |
| 2648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 2651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 2652 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2653 | // (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2) => (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 2654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64), |
| 2655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2656 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 2658 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 2659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2660 | GIR_RootConstrainSelectedInstOperands, |
| 2661 | // GIR_Coverage, 2204, |
| 2662 | GIR_EraseRootFromParent_Done, |
| 2663 | // Label 183: @14728 |
| 2664 | GIM_Try, /*On fail goto*//*Label 184*/ GIMT_Encode4(14774), // Rule ID 8126 // |
| 2665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX6GFX7GFX8GFX9), |
| 2666 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2667 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2668 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 2669 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 2670 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2671 | // (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MAD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 2672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64), |
| 2673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2674 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2675 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 2676 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 2677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2678 | GIR_RootConstrainSelectedInstOperands, |
| 2679 | // GIR_Coverage, 8126, |
| 2680 | GIR_EraseRootFromParent_Done, |
| 2681 | // Label 184: @14774 |
| 2682 | GIM_Try, /*On fail goto*//*Label 185*/ GIMT_Encode4(14829), // Rule ID 940 // |
| 2683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 2684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 2685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 2686 | // (add:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1) |
| 2687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_e64), |
| 2688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 2690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 2691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 2692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 2693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2695 | GIR_RootConstrainSelectedInstOperands, |
| 2696 | // GIR_Coverage, 940, |
| 2697 | GIR_EraseRootFromParent_Done, |
| 2698 | // Label 185: @14829 |
| 2699 | GIM_Try, /*On fail goto*//*Label 186*/ GIMT_Encode4(14851), // Rule ID 832 // |
| 2700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9), |
| 2701 | // (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_ADD_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 2702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64), |
| 2703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2704 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 2705 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 2707 | GIR_RootConstrainSelectedInstOperands, |
| 2708 | // GIR_Coverage, 832, |
| 2709 | GIR_EraseRootFromParent_Done, |
| 2710 | // Label 186: @14851 |
| 2711 | GIM_Reject, |
| 2712 | // Label 180: @14852 |
| 2713 | GIM_Reject, |
| 2714 | // Label 171: @14853 |
| 2715 | GIM_Try, /*On fail goto*//*Label 187*/ GIMT_Encode4(17585), |
| 2716 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 2717 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 2718 | GIM_Try, /*On fail goto*//*Label 188*/ GIMT_Encode4(14957), // Rule ID 2221 // |
| 2719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2722 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2723 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2724 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2725 | GIM_CheckHasOneUse, /*MI*/1, |
| 2726 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 2727 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2728 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2729 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 2730 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 2731 | GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y |
| 2732 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2733 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2734 | // MIs[3] Operand 1 |
| 2735 | // No operand predicates |
| 2736 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 2737 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z |
| 2738 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24022), |
| 2739 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 2740 | // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_24023>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_24022>> => (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 2741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64), |
| 2742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2743 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2744 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2745 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 2746 | GIR_RootConstrainSelectedInstOperands, |
| 2747 | // GIR_Coverage, 2221, |
| 2748 | GIR_EraseRootFromParent_Done, |
| 2749 | // Label 188: @14957 |
| 2750 | GIM_Try, /*On fail goto*//*Label 189*/ GIMT_Encode4(15050), // Rule ID 8129 // |
| 2751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2753 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z |
| 2754 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2755 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2756 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2757 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2758 | GIM_CheckHasOneUse, /*MI*/1, |
| 2759 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 2760 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 2761 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 2762 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 2763 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 2764 | GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:1:y |
| 2765 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 2766 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 2767 | // MIs[3] Operand 1 |
| 2768 | // No operand predicates |
| 2769 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 2770 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24022), |
| 2771 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 2772 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:1:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_24023>>)<<P:1:Predicate_anonymous_24022>> => (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 2773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64), |
| 2774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 2775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2776 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 2777 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 2778 | GIR_RootConstrainSelectedInstOperands, |
| 2779 | // GIR_Coverage, 8129, |
| 2780 | GIR_EraseRootFromParent_Done, |
| 2781 | // Label 189: @15050 |
| 2782 | GIM_Try, /*On fail goto*//*Label 190*/ GIMT_Encode4(15115), // Rule ID 84 // |
| 2783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2788 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2789 | GIM_CheckHasOneUse, /*MI*/1, |
| 2790 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2791 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 2792 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl1_add), |
| 2794 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2795 | // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl1_add>> => (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32), |
| 2797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2798 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2799 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2800 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2801 | GIR_RootConstrainSelectedInstOperands, |
| 2802 | // GIR_Coverage, 84, |
| 2803 | GIR_EraseRootFromParent_Done, |
| 2804 | // Label 190: @15115 |
| 2805 | GIM_Try, /*On fail goto*//*Label 191*/ GIMT_Encode4(15180), // Rule ID 85 // |
| 2806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2809 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2810 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2811 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2812 | GIM_CheckHasOneUse, /*MI*/1, |
| 2813 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2814 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 2815 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2816 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl2_add), |
| 2817 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2818 | // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl2_add>> => (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32), |
| 2820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2822 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2823 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2824 | GIR_RootConstrainSelectedInstOperands, |
| 2825 | // GIR_Coverage, 85, |
| 2826 | GIR_EraseRootFromParent_Done, |
| 2827 | // Label 191: @15180 |
| 2828 | GIM_Try, /*On fail goto*//*Label 192*/ GIMT_Encode4(15245), // Rule ID 86 // |
| 2829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2834 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2835 | GIM_CheckHasOneUse, /*MI*/1, |
| 2836 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2837 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 2838 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2839 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl3_add), |
| 2840 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2841 | // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl3_add>> => (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32), |
| 2843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2845 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2846 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2847 | GIR_RootConstrainSelectedInstOperands, |
| 2848 | // GIR_Coverage, 86, |
| 2849 | GIR_EraseRootFromParent_Done, |
| 2850 | // Label 192: @15245 |
| 2851 | GIM_Try, /*On fail goto*//*Label 193*/ GIMT_Encode4(15310), // Rule ID 87 // |
| 2852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2854 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 2855 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2856 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2857 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2858 | GIM_CheckHasOneUse, /*MI*/1, |
| 2859 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2860 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4, |
| 2861 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2862 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl4_add), |
| 2863 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2864 | // (add:{ *:[i32] } (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_shl4_add>> => (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32), |
| 2866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2868 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 2869 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2870 | GIR_RootConstrainSelectedInstOperands, |
| 2871 | // GIR_Coverage, 87, |
| 2872 | GIR_EraseRootFromParent_Done, |
| 2873 | // Label 193: @15310 |
| 2874 | GIM_Try, /*On fail goto*//*Label 194*/ GIMT_Encode4(15375), // Rule ID 8046 // |
| 2875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2877 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2878 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2879 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2880 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2881 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2882 | GIM_CheckHasOneUse, /*MI*/1, |
| 2883 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2884 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 1, |
| 2885 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl1_add), |
| 2886 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2887 | // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 1:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl1_add>> => (S_LSHL1_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL1_ADD_U32), |
| 2889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2890 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2891 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2892 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2893 | GIR_RootConstrainSelectedInstOperands, |
| 2894 | // GIR_Coverage, 8046, |
| 2895 | GIR_EraseRootFromParent_Done, |
| 2896 | // Label 194: @15375 |
| 2897 | GIM_Try, /*On fail goto*//*Label 195*/ GIMT_Encode4(15440), // Rule ID 8047 // |
| 2898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2900 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2902 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2904 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2905 | GIM_CheckHasOneUse, /*MI*/1, |
| 2906 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2907 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 2, |
| 2908 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl2_add), |
| 2909 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2910 | // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 2:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl2_add>> => (S_LSHL2_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL2_ADD_U32), |
| 2912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2914 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2915 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2916 | GIR_RootConstrainSelectedInstOperands, |
| 2917 | // GIR_Coverage, 8047, |
| 2918 | GIR_EraseRootFromParent_Done, |
| 2919 | // Label 195: @15440 |
| 2920 | GIM_Try, /*On fail goto*//*Label 196*/ GIMT_Encode4(15505), // Rule ID 8048 // |
| 2921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2923 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2924 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2925 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2926 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2927 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2928 | GIM_CheckHasOneUse, /*MI*/1, |
| 2929 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2930 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 3, |
| 2931 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl3_add), |
| 2932 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2933 | // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 3:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl3_add>> => (S_LSHL3_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL3_ADD_U32), |
| 2935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2936 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2937 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2938 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2939 | GIR_RootConstrainSelectedInstOperands, |
| 2940 | // GIR_Coverage, 8048, |
| 2941 | GIR_EraseRootFromParent_Done, |
| 2942 | // Label 196: @15505 |
| 2943 | GIM_Try, /*On fail goto*//*Label 197*/ GIMT_Encode4(15570), // Rule ID 8049 // |
| 2944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 2945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 2949 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2950 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2951 | GIM_CheckHasOneUse, /*MI*/1, |
| 2952 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 2953 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 4, |
| 2954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl4_add), |
| 2955 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2956 | // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, 4:{ *:[i32] })<<P:Predicate_shl_oneuse>>)<<P:Predicate_shl4_add>> => (S_LSHL4_ADD_U32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 2957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL4_ADD_U32), |
| 2958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 2959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 2960 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 2961 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 2962 | GIR_RootConstrainSelectedInstOperands, |
| 2963 | // GIR_Coverage, 8049, |
| 2964 | GIR_EraseRootFromParent_Done, |
| 2965 | // Label 197: @15570 |
| 2966 | GIM_Try, /*On fail goto*//*Label 198*/ GIMT_Encode4(15735), // Rule ID 8139 // |
| 2967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus), |
| 2968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 2969 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:11:z |
| 2970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2971 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 2972 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 2973 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 2974 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 2975 | GIM_CheckHasOneUse, /*MI*/1, |
| 2976 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:11:x |
| 2977 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:11:y |
| 2978 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 2979 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 2980 | // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:11:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:11:x, i32:{ *:[i32] }:$src1:$pred:11:y)<<P:Predicate_anonymous_24054>>)<<P:11:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 2981 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 2982 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 2983 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 2984 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2985 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 2986 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 2987 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2988 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2 |
| 2989 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 2990 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 2991 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 2992 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 2993 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2994 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 2995 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 2996 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 2997 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64), |
| 2998 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 2999 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3000 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3002 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3003 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3004 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3007 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3008 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3009 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3010 | // GIR_Coverage, 8139, |
| 3011 | GIR_EraseRootFromParent_Done, |
| 3012 | // Label 198: @15735 |
| 3013 | GIM_Try, /*On fail goto*//*Label 199*/ GIMT_Encode4(15900), // Rule ID 8143 // |
| 3014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only), |
| 3015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3016 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:14:z |
| 3017 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3019 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3020 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3021 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3022 | GIM_CheckHasOneUse, /*MI*/1, |
| 3023 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x |
| 3024 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y |
| 3025 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3026 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3027 | // (add:{ *:[i32] } VGPR_32:{ *:[i32] }:$src2:$pred:14:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:14:x, i32:{ *:[i32] }:$src1:$pred:14:y)<<P:Predicate_anonymous_24054>>)<<P:14:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3028 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3029 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3030 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3031 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3032 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3033 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3034 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3035 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2 |
| 3036 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3037 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3038 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3039 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3040 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3041 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3042 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3043 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3044 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64), |
| 3045 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3046 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3047 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3048 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3049 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3050 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3054 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3055 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3056 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3057 | // GIR_Coverage, 8143, |
| 3058 | GIR_EraseRootFromParent_Done, |
| 3059 | // Label 199: @15900 |
| 3060 | GIM_Try, /*On fail goto*//*Label 200*/ GIMT_Encode4(15965), // Rule ID 2224 // |
| 3061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3063 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3064 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 3065 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3066 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3067 | GIM_CheckHasOneUse, /*MI*/1, |
| 3068 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x |
| 3069 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y |
| 3070 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:3:z |
| 3071 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24028), |
| 3072 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3073 | // (add:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_24026>>, i32:{ *:[i32] }:$src2:$pred:3:z)<<P:3:Predicate_anonymous_24028>> => (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64), |
| 3075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3078 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 3079 | GIR_RootConstrainSelectedInstOperands, |
| 3080 | // GIR_Coverage, 2224, |
| 3081 | GIR_EraseRootFromParent_Done, |
| 3082 | // Label 200: @15965 |
| 3083 | GIM_Try, /*On fail goto*//*Label 201*/ GIMT_Encode4(16130), // Rule ID 2239 // |
| 3084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus), |
| 3085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3086 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3087 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3088 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3089 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3090 | GIM_CheckHasOneUse, /*MI*/1, |
| 3091 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:11:x |
| 3092 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:11:y |
| 3093 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:11:z |
| 3094 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3095 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3096 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3097 | // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:11:x, i32:{ *:[i32] }:$src1:$pred:11:y)<<P:Predicate_anonymous_24054>>, VGPR_32:{ *:[i32] }:$src2:$pred:11:z)<<P:11:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3098 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3099 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3100 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3101 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3102 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3103 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3104 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3105 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 3106 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3107 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3108 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3109 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3110 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3111 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3112 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64), |
| 3115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3116 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3117 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3118 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3119 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3120 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3121 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3124 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3125 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3126 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3127 | // GIR_Coverage, 2239, |
| 3128 | GIR_EraseRootFromParent_Done, |
| 3129 | // Label 201: @16130 |
| 3130 | GIM_Try, /*On fail goto*//*Label 202*/ GIMT_Encode4(16295), // Rule ID 2244 // |
| 3131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only), |
| 3132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3133 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3134 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3135 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3136 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3137 | GIM_CheckHasOneUse, /*MI*/1, |
| 3138 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:14:x |
| 3139 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:14:y |
| 3140 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:14:z |
| 3141 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3143 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3144 | // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:14:x, i32:{ *:[i32] }:$src1:$pred:14:y)<<P:Predicate_anonymous_24054>>, VGPR_32:{ *:[i32] }:$src2:$pred:14:z)<<P:14:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3145 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3146 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3147 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3148 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3150 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3151 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3152 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 3153 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3154 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3155 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3156 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3157 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3158 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3159 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3160 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3161 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64), |
| 3162 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3164 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3165 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3166 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3167 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3168 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3171 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3172 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3173 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3174 | // GIR_Coverage, 2244, |
| 3175 | GIR_EraseRootFromParent_Done, |
| 3176 | // Label 202: @16295 |
| 3177 | GIM_Try, /*On fail goto*//*Label 203*/ GIMT_Encode4(16456), // Rule ID 2238 // |
| 3178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus), |
| 3179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3183 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3184 | GIM_CheckHasOneUse, /*MI*/1, |
| 3185 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x |
| 3186 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y |
| 3187 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:10:z |
| 3188 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3189 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3190 | // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_anonymous_24054>>, i32:{ *:[i32] }:$src2:$pred:10:z)<<P:10:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3191 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3192 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3193 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3194 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3196 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3197 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3198 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 3199 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3200 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3201 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3202 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3203 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 3204 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 3205 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3206 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3207 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64), |
| 3208 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3209 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3210 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3211 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3212 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3213 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3214 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3217 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3218 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3219 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3220 | // GIR_Coverage, 2238, |
| 3221 | GIR_EraseRootFromParent_Done, |
| 3222 | // Label 203: @16456 |
| 3223 | GIM_Try, /*On fail goto*//*Label 204*/ GIMT_Encode4(16617), // Rule ID 2243 // |
| 3224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only), |
| 3225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3228 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3229 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3230 | GIM_CheckHasOneUse, /*MI*/1, |
| 3231 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:13:x |
| 3232 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:13:y |
| 3233 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:13:z |
| 3234 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3235 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3236 | // (add:{ *:[i32] } (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:13:x, i32:{ *:[i32] }:$src1:$pred:13:y)<<P:Predicate_anonymous_24054>>, i32:{ *:[i32] }:$src2:$pred:13:z)<<P:13:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3237 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3238 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3239 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3240 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3242 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3243 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3244 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src2 |
| 3245 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3246 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3247 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3248 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3249 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 3250 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 3251 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3252 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3253 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64), |
| 3254 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3255 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3256 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3257 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3258 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3259 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3263 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3264 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3265 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3266 | // GIR_Coverage, 2243, |
| 3267 | GIR_EraseRootFromParent_Done, |
| 3268 | // Label 204: @16617 |
| 3269 | GIM_Try, /*On fail goto*//*Label 205*/ GIMT_Encode4(16682), // Rule ID 2220 // |
| 3270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3272 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3273 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3274 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3275 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3276 | GIM_CheckHasOneUse, /*MI*/1, |
| 3277 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 3278 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y |
| 3279 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:1:z |
| 3280 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24022), |
| 3281 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3282 | // (add:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_24023>>, i32:{ *:[i32] }:$src2:$pred:1:z)<<P:1:Predicate_anonymous_24022>> => (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64), |
| 3284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3285 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3286 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3287 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 3288 | GIR_RootConstrainSelectedInstOperands, |
| 3289 | // GIR_Coverage, 2220, |
| 3290 | GIR_EraseRootFromParent_Done, |
| 3291 | // Label 205: @16682 |
| 3292 | GIM_Try, /*On fail goto*//*Label 206*/ GIMT_Encode4(16747), // Rule ID 2230 // |
| 3293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3295 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3296 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 3297 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3298 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3299 | GIM_CheckHasOneUse, /*MI*/1, |
| 3300 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x |
| 3301 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y |
| 3302 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:8:z |
| 3303 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24041), |
| 3304 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3305 | // (add:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_24042>>, i32:{ *:[i32] }:$src2:$pred:8:z)<<P:8:Predicate_anonymous_24041>> => (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64), |
| 3307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3310 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 3311 | GIR_RootConstrainSelectedInstOperands, |
| 3312 | // GIR_Coverage, 2230, |
| 3313 | GIR_EraseRootFromParent_Done, |
| 3314 | // Label 206: @16747 |
| 3315 | GIM_Try, /*On fail goto*//*Label 207*/ GIMT_Encode4(16812), // Rule ID 8130 // |
| 3316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3318 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:3:z |
| 3319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 3321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3323 | GIM_CheckHasOneUse, /*MI*/1, |
| 3324 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:3:x |
| 3325 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:3:y |
| 3326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24028), |
| 3327 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3328 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:3:z, (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:3:x, i32:{ *:[i32] }:$src1:$pred:3:y)<<P:Predicate_anonymous_24026>>)<<P:3:Predicate_anonymous_24028>> => (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64), |
| 3330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3331 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3332 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3333 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 3334 | GIR_RootConstrainSelectedInstOperands, |
| 3335 | // GIR_Coverage, 8130, |
| 3336 | GIR_EraseRootFromParent_Done, |
| 3337 | // Label 207: @16812 |
| 3338 | GIM_Try, /*On fail goto*//*Label 208*/ GIMT_Encode4(16973), // Rule ID 8138 // |
| 3339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNotMADIntraFwdBug_isGFX9Plus), |
| 3340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3341 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:10:z |
| 3342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3343 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3345 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3346 | GIM_CheckHasOneUse, /*MI*/1, |
| 3347 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:10:x |
| 3348 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:10:y |
| 3349 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3350 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3351 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:10:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:10:x, i32:{ *:[i32] }:$src1:$pred:10:y)<<P:Predicate_anonymous_24054>>)<<P:10:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3352 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3353 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3354 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3355 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3356 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3357 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3358 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3359 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2 |
| 3360 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3361 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3362 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3363 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3364 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 3365 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 3366 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3367 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3368 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_e64), |
| 3369 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3370 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3371 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3372 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3373 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3374 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3378 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3379 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3380 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3381 | // GIR_Coverage, 8138, |
| 3382 | GIR_EraseRootFromParent_Done, |
| 3383 | // Label 208: @16973 |
| 3384 | GIM_Try, /*On fail goto*//*Label 209*/ GIMT_Encode4(17134), // Rule ID 8142 // |
| 3385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMADIntraFwdBug_isGFX11Only), |
| 3386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3387 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:13:z |
| 3388 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3389 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3390 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3391 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3392 | GIM_CheckHasOneUse, /*MI*/1, |
| 3393 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:13:x |
| 3394 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:13:y |
| 3395 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24053), |
| 3396 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3397 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:13:z, (mul:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:13:x, i32:{ *:[i32] }:$src1:$pred:13:y)<<P:Predicate_anonymous_24054>>)<<P:13:Predicate_anonymous_24053>> => (EXTRACT_SUBREG:{ *:[i32] } (V_MAD_U64_U32_gfx11_e64:{ *:[i64] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src2, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i1] }), sub0:{ *:[i32] }) |
| 3398 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 3399 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 3400 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 3401 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 3403 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 3404 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3405 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src2 |
| 3406 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 3407 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 3408 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 3409 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3410 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 3411 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 3412 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 3413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 3414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U64_U32_gfx11_e64), |
| 3415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 3416 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3417 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3418 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3419 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 3420 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 3421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 3422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 3423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 3424 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 3425 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3426 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3427 | // GIR_Coverage, 8142, |
| 3428 | GIR_EraseRootFromParent_Done, |
| 3429 | // Label 209: @17134 |
| 3430 | GIM_Try, /*On fail goto*//*Label 210*/ GIMT_Encode4(17199), // Rule ID 8128 // |
| 3431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3433 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:1:z |
| 3434 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3435 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3436 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3437 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3438 | GIM_CheckHasOneUse, /*MI*/1, |
| 3439 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:1:x |
| 3440 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:1:y |
| 3441 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24022), |
| 3442 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3443 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:1:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:1:x, i32:{ *:[i32] }:$src1:$pred:1:y)<<P:Predicate_anonymous_24023>>)<<P:1:Predicate_anonymous_24022>> => (V_LSHL_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U32_e64), |
| 3445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3446 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3447 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3448 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 3449 | GIR_RootConstrainSelectedInstOperands, |
| 3450 | // GIR_Coverage, 8128, |
| 3451 | GIR_EraseRootFromParent_Done, |
| 3452 | // Label 210: @17199 |
| 3453 | GIM_Try, /*On fail goto*//*Label 211*/ GIMT_Encode4(17264), // Rule ID 8135 // |
| 3454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 3455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3456 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:8:z |
| 3457 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3458 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 3459 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3460 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3461 | GIM_CheckHasOneUse, /*MI*/1, |
| 3462 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:8:x |
| 3463 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:8:y |
| 3464 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24041), |
| 3465 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3466 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:8:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:8:x, i32:{ *:[i32] }:$src1:$pred:8:y)<<P:Predicate_anonymous_24042>>)<<P:8:Predicate_anonymous_24041>> => (V_XAD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 3467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XAD_U32_e64), |
| 3468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3470 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3471 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 3472 | GIR_RootConstrainSelectedInstOperands, |
| 3473 | // GIR_Coverage, 8135, |
| 3474 | GIR_EraseRootFromParent_Done, |
| 3475 | // Label 211: @17264 |
| 3476 | GIM_Try, /*On fail goto*//*Label 212*/ GIMT_Encode4(17308), // Rule ID 7294 // |
| 3477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3480 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32), |
| 3481 | // MIs[1] Operand 1 |
| 3482 | // No operand predicates |
| 3483 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18497), |
| 3484 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3485 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_18497>> => (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i1 i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1)) |
| 3486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32), |
| 3487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 3488 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3489 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 3490 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 3491 | GIR_RootConstrainSelectedInstOperands, |
| 3492 | // GIR_Coverage, 7294, |
| 3493 | GIR_EraseRootFromParent_Done, |
| 3494 | // Label 212: @17308 |
| 3495 | GIM_Try, /*On fail goto*//*Label 213*/ GIMT_Encode4(17355), // Rule ID 7295 // |
| 3496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts), |
| 3497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3498 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3499 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3500 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32), |
| 3501 | // MIs[1] Operand 1 |
| 3502 | // No operand predicates |
| 3503 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23239), |
| 3504 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3505 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_23239>> => (V_SUB_U32_e64:{ *:[i32] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1)) |
| 3506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64), |
| 3507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3508 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3509 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 3510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3511 | GIR_RootConstrainSelectedInstOperands, |
| 3512 | // GIR_Coverage, 7295, |
| 3513 | GIR_EraseRootFromParent_Done, |
| 3514 | // Label 213: @17355 |
| 3515 | GIM_Try, /*On fail goto*//*Label 214*/ GIMT_Encode4(17410), // Rule ID 7296 // |
| 3516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasAddNoCarryInsts), |
| 3517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3518 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3519 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 3520 | GIM_CheckI64ImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineConst32), |
| 3521 | // MIs[1] Operand 1 |
| 3522 | // No operand predicates |
| 3523 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23239), |
| 3524 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3525 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>><<X:NegateImm>>:$src1)<<P:Predicate_anonymous_23239>> => (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VS_32:{ *:[i32] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i32] })<<P:Predicate_NegSubInlineConst32>>:$src1)) |
| 3526 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 3527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64), |
| 3528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3529 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3530 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3531 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 3532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3533 | GIR_RootConstrainSelectedInstOperands, |
| 3534 | // GIR_Coverage, 7296, |
| 3535 | GIR_EraseRootFromParent_Done, |
| 3536 | // Label 214: @17410 |
| 3537 | GIM_Try, /*On fail goto*//*Label 215*/ GIMT_Encode4(17444), // Rule ID 45 // |
| 3538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3539 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3540 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18497), |
| 3542 | // (add:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18497>> => (S_ADD_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 3543 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_I32), |
| 3544 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3545 | GIR_RootConstrainSelectedInstOperands, |
| 3546 | // GIR_Coverage, 45, |
| 3547 | GIR_Done, |
| 3548 | // Label 215: @17444 |
| 3549 | GIM_Try, /*On fail goto*//*Label 216*/ GIMT_Encode4(17474), // Rule ID 2132 // |
| 3550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts), |
| 3551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3552 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23239), |
| 3553 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23239>> => (V_ADD_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] }) |
| 3554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U32_e64), |
| 3555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3556 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3557 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3559 | GIR_RootConstrainSelectedInstOperands, |
| 3560 | // GIR_Coverage, 2132, |
| 3561 | GIR_EraseRootFromParent_Done, |
| 3562 | // Label 216: @17474 |
| 3563 | GIM_Try, /*On fail goto*//*Label 217*/ GIMT_Encode4(17512), // Rule ID 2134 // |
| 3564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9), |
| 3565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3566 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23239), |
| 3567 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23239>> => (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] }) |
| 3568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 3569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64), |
| 3570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3571 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3572 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3573 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3575 | GIR_RootConstrainSelectedInstOperands, |
| 3576 | // GIR_Coverage, 2134, |
| 3577 | GIR_EraseRootFromParent_Done, |
| 3578 | // Label 217: @17512 |
| 3579 | GIM_Try, /*On fail goto*//*Label 218*/ GIMT_Encode4(17548), // Rule ID 754 // |
| 3580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3581 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3582 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP), |
| 3583 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3584 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3585 | // (add:{ *:[i32] } (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 3586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64), |
| 3587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3588 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3589 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3590 | GIR_RootConstrainSelectedInstOperands, |
| 3591 | // GIR_Coverage, 754, |
| 3592 | GIR_EraseRootFromParent_Done, |
| 3593 | // Label 218: @17548 |
| 3594 | GIM_Try, /*On fail goto*//*Label 219*/ GIMT_Encode4(17584), // Rule ID 8061 // |
| 3595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CTPOP), |
| 3598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 3599 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3600 | // (add:{ *:[i32] } i32:{ *:[i32] }:$src1, (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_BCNT_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 3601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64), |
| 3602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3603 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3604 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 3605 | GIR_RootConstrainSelectedInstOperands, |
| 3606 | // GIR_Coverage, 8061, |
| 3607 | GIR_EraseRootFromParent_Done, |
| 3608 | // Label 219: @17584 |
| 3609 | GIM_Reject, |
| 3610 | // Label 187: @17585 |
| 3611 | GIM_Reject, |
| 3612 | // Label 172: @17586 |
| 3613 | GIM_Try, /*On fail goto*//*Label 220*/ GIMT_Encode4(17792), |
| 3614 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 3615 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 3616 | GIM_Try, /*On fail goto*//*Label 221*/ GIMT_Encode4(17666), // Rule ID 2232 // |
| 3617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 3618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3619 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3620 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3621 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3622 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3623 | GIM_CheckHasOneUse, /*MI*/1, |
| 3624 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x |
| 3625 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y |
| 3626 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4), |
| 3627 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:9:z |
| 3628 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24045), |
| 3629 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3630 | // (add:{ *:[i64] } (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_24046>>, i64:{ *:[i64] }:$src2:$pred:9:z)<<P:9:Predicate_anonymous_24045>> => (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2) |
| 3631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64), |
| 3632 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3633 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3634 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3635 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 3636 | GIR_RootConstrainSelectedInstOperands, |
| 3637 | // GIR_Coverage, 2232, |
| 3638 | GIR_EraseRootFromParent_Done, |
| 3639 | // Label 221: @17666 |
| 3640 | GIM_Try, /*On fail goto*//*Label 222*/ GIMT_Encode4(17735), // Rule ID 8136 // |
| 3641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 3642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3643 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:9:z |
| 3644 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3645 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 3646 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 3647 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 3648 | GIM_CheckHasOneUse, /*MI*/1, |
| 3649 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:9:x |
| 3650 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:9:y |
| 3651 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_shl_0_to_4), |
| 3652 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24045), |
| 3653 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3654 | // (add:{ *:[i64] } i64:{ *:[i64] }:$src2:$pred:9:z, (shl:{ *:[i64] } i64:{ *:[i64] }:$src0:$pred:9:x, i32:{ *:[i32] }:$src1:$pred:9:y)<<P:Predicate_shl_0_to_4>><<P:Predicate_anonymous_24046>>)<<P:9:Predicate_anonymous_24045>> => (V_LSHL_ADD_U64_e64:{ *:[i64] } VSrc_b64:{ *:[i64] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b64:{ *:[i64] }:$src2) |
| 3655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_ADD_U64_e64), |
| 3656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 3658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 3659 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 3660 | GIR_RootConstrainSelectedInstOperands, |
| 3661 | // GIR_Coverage, 8136, |
| 3662 | GIR_EraseRootFromParent_Done, |
| 3663 | // Label 222: @17735 |
| 3664 | GIM_Try, /*On fail goto*//*Label 223*/ GIMT_Encode4(17765), // Rule ID 1114 // |
| 3665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3666 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23239), |
| 3667 | // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_23239>> => (V_ADD_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 3668 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U64_PSEUDO), |
| 3669 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead), |
| 3670 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 3671 | GIR_RootConstrainSelectedInstOperands, |
| 3672 | // GIR_Coverage, 1114, |
| 3673 | GIR_Done, |
| 3674 | // Label 223: @17765 |
| 3675 | GIM_Try, /*On fail goto*//*Label 224*/ GIMT_Encode4(17791), // Rule ID 1116 // |
| 3676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3677 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18497), |
| 3678 | // (add:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18497>> => (S_ADD_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 3679 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_U64_PSEUDO), |
| 3680 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3681 | GIR_RootConstrainSelectedInstOperands, |
| 3682 | // GIR_Coverage, 1116, |
| 3683 | GIR_Done, |
| 3684 | // Label 224: @17791 |
| 3685 | GIM_Reject, |
| 3686 | // Label 220: @17792 |
| 3687 | GIM_Reject, |
| 3688 | // Label 173: @17793 |
| 3689 | GIM_Try, /*On fail goto*//*Label 225*/ GIMT_Encode4(18062), |
| 3690 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3691 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 3692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3693 | GIM_Try, /*On fail goto*//*Label 226*/ GIMT_Encode4(17904), // Rule ID 8113 // |
| 3694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 3695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3697 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 3698 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3700 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3701 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3702 | // (add:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))) => (V_PK_MAD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2) |
| 3703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAD_U16), |
| 3704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 3706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 3707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_modifiers |
| 3708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 3709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 3710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 3711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3716 | GIR_RootConstrainSelectedInstOperands, |
| 3717 | // GIR_Coverage, 8113, |
| 3718 | GIR_EraseRootFromParent_Done, |
| 3719 | // Label 226: @17904 |
| 3720 | GIM_Try, /*On fail goto*//*Label 227*/ GIMT_Encode4(18000), // Rule ID 954 // |
| 3721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 3722 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 3723 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3724 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 3725 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 3726 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3727 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3728 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3729 | // (add:{ *:[v2i16] } (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_PK_MAD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2i16:{ *:[v2i16] }:$src2) |
| 3730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAD_U16), |
| 3731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 3733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 3734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 3735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 3736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 3737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 3738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3743 | GIR_RootConstrainSelectedInstOperands, |
| 3744 | // GIR_Coverage, 954, |
| 3745 | GIR_EraseRootFromParent_Done, |
| 3746 | // Label 227: @18000 |
| 3747 | GIM_Try, /*On fail goto*//*Label 228*/ GIMT_Encode4(18061), // Rule ID 965 // |
| 3748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3750 | // (add:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 3751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_U16), |
| 3752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 3754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 3755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 3756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 3757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3762 | GIR_RootConstrainSelectedInstOperands, |
| 3763 | // GIR_Coverage, 965, |
| 3764 | GIR_EraseRootFromParent_Done, |
| 3765 | // Label 228: @18061 |
| 3766 | GIM_Reject, |
| 3767 | // Label 225: @18062 |
| 3768 | GIM_Reject, |
| 3769 | // Label 174: @18063 |
| 3770 | GIM_Reject, |
| 3771 | // Label 1: @18064 |
| 3772 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 234*/ GIMT_Encode4(18564), |
| 3773 | /*GILLT_s1*//*Label 229*/ GIMT_Encode4(18095), |
| 3774 | /*GILLT_s16*//*Label 230*/ GIMT_Encode4(18214), |
| 3775 | /*GILLT_s32*//*Label 231*/ GIMT_Encode4(18308), |
| 3776 | /*GILLT_s64*//*Label 232*/ GIMT_Encode4(18423), |
| 3777 | /*GILLT_v2s16*//*Label 233*/ GIMT_Encode4(18492), |
| 3778 | // Label 229: @18095 |
| 3779 | GIM_Try, /*On fail goto*//*Label 235*/ GIMT_Encode4(18213), |
| 3780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 3781 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 3782 | GIM_Try, /*On fail goto*//*Label 236*/ GIMT_Encode4(18134), // Rule ID 7169 // |
| 3783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 3784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3785 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 3786 | // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] }) => (S_NOT_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0) |
| 3787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64), |
| 3788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 3789 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3790 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 3791 | GIR_RootConstrainSelectedInstOperands, |
| 3792 | // GIR_Coverage, 7169, |
| 3793 | GIR_EraseRootFromParent_Done, |
| 3794 | // Label 236: @18134 |
| 3795 | GIM_Try, /*On fail goto*//*Label 237*/ GIMT_Encode4(18162), // Rule ID 7176 // |
| 3796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 3797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3798 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 3799 | // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, -1:{ *:[i1] }) => (S_NOT_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0) |
| 3800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32), |
| 3801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 3802 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3803 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 3804 | GIR_RootConstrainSelectedInstOperands, |
| 3805 | // GIR_Coverage, 7176, |
| 3806 | GIR_EraseRootFromParent_Done, |
| 3807 | // Label 237: @18162 |
| 3808 | GIM_Try, /*On fail goto*//*Label 238*/ GIMT_Encode4(18187), // Rule ID 7167 // |
| 3809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 3810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3811 | // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 3812 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64), |
| 3813 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3814 | GIR_RootConstrainSelectedInstOperands, |
| 3815 | // GIR_Coverage, 7167, |
| 3816 | GIR_Done, |
| 3817 | // Label 238: @18187 |
| 3818 | GIM_Try, /*On fail goto*//*Label 239*/ GIMT_Encode4(18212), // Rule ID 7174 // |
| 3819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 3820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3821 | // (sub:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 3822 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 3823 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3824 | GIR_RootConstrainSelectedInstOperands, |
| 3825 | // GIR_Coverage, 7174, |
| 3826 | GIR_Done, |
| 3827 | // Label 239: @18212 |
| 3828 | GIM_Reject, |
| 3829 | // Label 235: @18213 |
| 3830 | GIM_Reject, |
| 3831 | // Label 230: @18214 |
| 3832 | GIM_Try, /*On fail goto*//*Label 240*/ GIMT_Encode4(18307), |
| 3833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 3834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 3835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3836 | GIM_Try, /*On fail goto*//*Label 241*/ GIMT_Encode4(18284), // Rule ID 941 // |
| 3837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 3838 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 3839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 3840 | // (sub:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_NC_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1) |
| 3841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64), |
| 3842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 3844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 3845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 3846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 3847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3849 | GIR_RootConstrainSelectedInstOperands, |
| 3850 | // GIR_Coverage, 941, |
| 3851 | GIR_EraseRootFromParent_Done, |
| 3852 | // Label 241: @18284 |
| 3853 | GIM_Try, /*On fail goto*//*Label 242*/ GIMT_Encode4(18306), // Rule ID 833 // |
| 3854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9), |
| 3855 | // (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_SUB_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 3856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64), |
| 3857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3858 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3859 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3861 | GIR_RootConstrainSelectedInstOperands, |
| 3862 | // GIR_Coverage, 833, |
| 3863 | GIR_EraseRootFromParent_Done, |
| 3864 | // Label 242: @18306 |
| 3865 | GIM_Reject, |
| 3866 | // Label 240: @18307 |
| 3867 | GIM_Reject, |
| 3868 | // Label 231: @18308 |
| 3869 | GIM_Try, /*On fail goto*//*Label 243*/ GIMT_Encode4(18422), |
| 3870 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 3871 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 3872 | GIM_Try, /*On fail goto*//*Label 244*/ GIMT_Encode4(18353), // Rule ID 46 // |
| 3873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3875 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 3876 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18498), |
| 3877 | // (sub:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18498>> => (S_SUB_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 3878 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_I32), |
| 3879 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3880 | GIR_RootConstrainSelectedInstOperands, |
| 3881 | // GIR_Coverage, 46, |
| 3882 | GIR_Done, |
| 3883 | // Label 244: @18353 |
| 3884 | GIM_Try, /*On fail goto*//*Label 245*/ GIMT_Encode4(18383), // Rule ID 2133 // |
| 3885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts), |
| 3886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3887 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23241), |
| 3888 | // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23241>> => (V_SUB_U32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] }) |
| 3889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64), |
| 3890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3891 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3892 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3894 | GIR_RootConstrainSelectedInstOperands, |
| 3895 | // GIR_Coverage, 2133, |
| 3896 | GIR_EraseRootFromParent_Done, |
| 3897 | // Label 245: @18383 |
| 3898 | GIM_Try, /*On fail goto*//*Label 246*/ GIMT_Encode4(18421), // Rule ID 2135 // |
| 3899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7GFX8GFX9), |
| 3900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3901 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23241), |
| 3902 | // (sub:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23241>> => (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, 0:{ *:[i1] }) |
| 3903 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 3904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64), |
| 3905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3906 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 3907 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 3908 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 3909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3910 | GIR_RootConstrainSelectedInstOperands, |
| 3911 | // GIR_Coverage, 2135, |
| 3912 | GIR_EraseRootFromParent_Done, |
| 3913 | // Label 246: @18421 |
| 3914 | GIM_Reject, |
| 3915 | // Label 243: @18422 |
| 3916 | GIM_Reject, |
| 3917 | // Label 232: @18423 |
| 3918 | GIM_Try, /*On fail goto*//*Label 247*/ GIMT_Encode4(18491), |
| 3919 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 3920 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 3921 | GIM_Try, /*On fail goto*//*Label 248*/ GIMT_Encode4(18464), // Rule ID 1115 // |
| 3922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 3923 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23241), |
| 3924 | // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_23241>> => (V_SUB_U64_PSEUDO:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 3925 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U64_PSEUDO), |
| 3926 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::VCC), GIMT_Encode2(RegState::Dead), |
| 3927 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 3928 | GIR_RootConstrainSelectedInstOperands, |
| 3929 | // GIR_Coverage, 1115, |
| 3930 | GIR_Done, |
| 3931 | // Label 248: @18464 |
| 3932 | GIM_Try, /*On fail goto*//*Label 249*/ GIMT_Encode4(18490), // Rule ID 1117 // |
| 3933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 3934 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18498), |
| 3935 | // (sub:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18498>> => (S_SUB_U64_PSEUDO:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 3936 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_U64_PSEUDO), |
| 3937 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 3938 | GIR_RootConstrainSelectedInstOperands, |
| 3939 | // GIR_Coverage, 1117, |
| 3940 | GIR_Done, |
| 3941 | // Label 249: @18490 |
| 3942 | GIM_Reject, |
| 3943 | // Label 247: @18491 |
| 3944 | GIM_Reject, |
| 3945 | // Label 233: @18492 |
| 3946 | GIM_Try, /*On fail goto*//*Label 250*/ GIMT_Encode4(18563), // Rule ID 973 // |
| 3947 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 3948 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 3949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 3952 | // (sub:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_SUB_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 3953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_I16), |
| 3954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 3955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 3956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 3957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 3958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 3959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 3964 | GIR_RootConstrainSelectedInstOperands, |
| 3965 | // GIR_Coverage, 973, |
| 3966 | GIR_EraseRootFromParent_Done, |
| 3967 | // Label 250: @18563 |
| 3968 | GIM_Reject, |
| 3969 | // Label 234: @18564 |
| 3970 | GIM_Reject, |
| 3971 | // Label 2: @18565 |
| 3972 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 255*/ GIMT_Encode4(18850), |
| 3973 | /*GILLT_s16*//*Label 251*/ GIMT_Encode4(18592), |
| 3974 | /*GILLT_s32*//*Label 252*/ GIMT_Encode4(18647), |
| 3975 | /*GILLT_s64*//*Label 253*/ GIMT_Encode4(18748), |
| 3976 | /*GILLT_v2s16*//*Label 254*/ GIMT_Encode4(18778), |
| 3977 | // Label 251: @18592 |
| 3978 | GIM_Try, /*On fail goto*//*Label 256*/ GIMT_Encode4(18646), |
| 3979 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 3980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 3981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 3982 | GIM_Try, /*On fail goto*//*Label 257*/ GIMT_Encode4(18626), // Rule ID 807 // |
| 3983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 3984 | // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MUL_LO_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 3985 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64), |
| 3986 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 3987 | GIR_RootConstrainSelectedInstOperands, |
| 3988 | // GIR_Coverage, 807, |
| 3989 | GIR_Done, |
| 3990 | // Label 257: @18626 |
| 3991 | GIM_Try, /*On fail goto*//*Label 258*/ GIMT_Encode4(18645), // Rule ID 808 // |
| 3992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 3993 | // (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MUL_LO_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 3994 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_t16_e64), |
| 3995 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 3996 | GIR_RootConstrainSelectedInstOperands, |
| 3997 | // GIR_Coverage, 808, |
| 3998 | GIR_Done, |
| 3999 | // Label 258: @18645 |
| 4000 | GIM_Reject, |
| 4001 | // Label 256: @18646 |
| 4002 | GIM_Reject, |
| 4003 | // Label 252: @18647 |
| 4004 | GIM_Try, /*On fail goto*//*Label 259*/ GIMT_Encode4(18747), |
| 4005 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4006 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4007 | GIM_Try, /*On fail goto*//*Label 260*/ GIMT_Encode4(18678), // Rule ID 83 // |
| 4008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18505), |
| 4010 | // (mul:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18505>> => (S_MUL_I32:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4011 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_I32), |
| 4012 | GIR_RootConstrainSelectedInstOperands, |
| 4013 | // GIR_Coverage, 83, |
| 4014 | GIR_Done, |
| 4015 | // Label 260: @18678 |
| 4016 | GIM_Try, /*On fail goto*//*Label 261*/ GIMT_Encode4(18712), // Rule ID 861 // |
| 4017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4018 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23638), |
| 4019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 4020 | // (mul:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23638>> => (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64), |
| 4022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 4024 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 4025 | GIR_RootConstrainSelectedInstOperands, |
| 4026 | // GIR_Coverage, 861, |
| 4027 | GIR_EraseRootFromParent_Done, |
| 4028 | // Label 261: @18712 |
| 4029 | GIM_Try, /*On fail goto*//*Label 262*/ GIMT_Encode4(18746), // Rule ID 8101 // |
| 4030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4031 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23638), |
| 4032 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 4033 | // (mul:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))<<P:Predicate_anonymous_23638>> => (V_MUL_LO_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U32_e64), |
| 4035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 4037 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 4038 | GIR_RootConstrainSelectedInstOperands, |
| 4039 | // GIR_Coverage, 8101, |
| 4040 | GIR_EraseRootFromParent_Done, |
| 4041 | // Label 262: @18746 |
| 4042 | GIM_Reject, |
| 4043 | // Label 259: @18747 |
| 4044 | GIM_Reject, |
| 4045 | // Label 253: @18748 |
| 4046 | GIM_Try, /*On fail goto*//*Label 263*/ GIMT_Encode4(18777), // Rule ID 53 // |
| 4047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 4048 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 4049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4051 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18505), |
| 4052 | // (mul:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18505>> => (S_MUL_U64:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 4053 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_U64), |
| 4054 | GIR_RootConstrainSelectedInstOperands, |
| 4055 | // GIR_Coverage, 53, |
| 4056 | GIR_Done, |
| 4057 | // Label 263: @18777 |
| 4058 | GIM_Reject, |
| 4059 | // Label 254: @18778 |
| 4060 | GIM_Try, /*On fail goto*//*Label 264*/ GIMT_Encode4(18849), // Rule ID 966 // |
| 4061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 4062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 4065 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 4066 | // (mul:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MUL_LO_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 4067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_LO_U16), |
| 4068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 4070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 4071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 4072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 4073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 4078 | GIR_RootConstrainSelectedInstOperands, |
| 4079 | // GIR_Coverage, 966, |
| 4080 | GIR_EraseRootFromParent_Done, |
| 4081 | // Label 264: @18849 |
| 4082 | GIM_Reject, |
| 4083 | // Label 255: @18850 |
| 4084 | GIM_Reject, |
| 4085 | // Label 3: @18851 |
| 4086 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 272*/ GIMT_Encode4(19806), |
| 4087 | /*GILLT_s1*//*Label 265*/ GIMT_Encode4(18902), |
| 4088 | /*GILLT_s16*//*Label 266*/ GIMT_Encode4(18965), |
| 4089 | /*GILLT_s32*//*Label 267*/ GIMT_Encode4(19123), |
| 4090 | /*GILLT_s64*//*Label 268*/ GIMT_Encode4(19284), |
| 4091 | /*GILLT_v2s16*//*Label 269*/ GIMT_Encode4(19409), |
| 4092 | /*GILLT_v2s32*//*Label 270*/ GIMT_Encode4(19560), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4093 | /*GILLT_v4s16*//*Label 271*/ GIMT_Encode4(19683), |
| 4094 | // Label 265: @18902 |
| 4095 | GIM_Try, /*On fail goto*//*Label 273*/ GIMT_Encode4(18964), |
| 4096 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 4097 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 4098 | GIM_Try, /*On fail goto*//*Label 274*/ GIMT_Encode4(18938), // Rule ID 7163 // |
| 4099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 4100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4101 | // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_AND_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 4102 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64), |
| 4103 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4104 | GIR_RootConstrainSelectedInstOperands, |
| 4105 | // GIR_Coverage, 7163, |
| 4106 | GIR_Done, |
| 4107 | // Label 274: @18938 |
| 4108 | GIM_Try, /*On fail goto*//*Label 275*/ GIMT_Encode4(18963), // Rule ID 7170 // |
| 4109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 4110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4111 | // (and:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 4112 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 4113 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4114 | GIR_RootConstrainSelectedInstOperands, |
| 4115 | // GIR_Coverage, 7170, |
| 4116 | GIR_Done, |
| 4117 | // Label 275: @18963 |
| 4118 | GIM_Reject, |
| 4119 | // Label 273: @18964 |
| 4120 | GIM_Reject, |
| 4121 | // Label 266: @18965 |
| 4122 | GIM_Try, /*On fail goto*//*Label 276*/ GIMT_Encode4(19122), |
| 4123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 4124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 4125 | GIM_Try, /*On fail goto*//*Label 277*/ GIMT_Encode4(19027), // Rule ID 8115 // |
| 4126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4127 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4128 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4129 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 4130 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 4131 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4132 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4133 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4134 | // (and:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }), i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1) |
| 4135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4137 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4138 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4139 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4140 | GIR_RootConstrainSelectedInstOperands, |
| 4141 | // GIR_Coverage, 8115, |
| 4142 | GIR_EraseRootFromParent_Done, |
| 4143 | // Label 277: @19027 |
| 4144 | GIM_Try, /*On fail goto*//*Label 278*/ GIMT_Encode4(19078), // Rule ID 1657 // |
| 4145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4146 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4147 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4148 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 4149 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 4150 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4151 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4152 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4153 | // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1) |
| 4154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4156 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4158 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4159 | GIR_RootConstrainSelectedInstOperands, |
| 4160 | // GIR_Coverage, 1657, |
| 4161 | GIR_EraseRootFromParent_Done, |
| 4162 | // Label 278: @19078 |
| 4163 | GIM_Try, /*On fail goto*//*Label 279*/ GIMT_Encode4(19098), // Rule ID 2160 // |
| 4164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4165 | // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_AND_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1) |
| 4166 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 4167 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4168 | GIR_RootConstrainSelectedInstOperands, |
| 4169 | // GIR_Coverage, 2160, |
| 4170 | GIR_Done, |
| 4171 | // Label 279: @19098 |
| 4172 | GIM_Try, /*On fail goto*//*Label 280*/ GIMT_Encode4(19121), // Rule ID 829 // |
| 4173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 4174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4175 | // (and:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_AND_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 4176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B16_t16_e64), |
| 4177 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4178 | GIR_RootConstrainSelectedInstOperands, |
| 4179 | // GIR_Coverage, 829, |
| 4180 | GIR_Done, |
| 4181 | // Label 280: @19121 |
| 4182 | GIM_Reject, |
| 4183 | // Label 276: @19122 |
| 4184 | GIM_Reject, |
| 4185 | // Label 267: @19123 |
| 4186 | GIM_Try, /*On fail goto*//*Label 281*/ GIMT_Encode4(19283), |
| 4187 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4188 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4189 | GIM_Try, /*On fail goto*//*Label 282*/ GIMT_Encode4(19185), // Rule ID 8042 // |
| 4190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4191 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4192 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4193 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4194 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4195 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4196 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4197 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4198 | // (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }), i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4201 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4202 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4203 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4204 | GIR_RootConstrainSelectedInstOperands, |
| 4205 | // GIR_Coverage, 8042, |
| 4206 | GIR_EraseRootFromParent_Done, |
| 4207 | // Label 282: @19185 |
| 4208 | GIM_Try, /*On fail goto*//*Label 283*/ GIMT_Encode4(19236), // Rule ID 66 // |
| 4209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4211 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4213 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4214 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4215 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4216 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4217 | // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4220 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4221 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4222 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4223 | GIR_RootConstrainSelectedInstOperands, |
| 4224 | // GIR_Coverage, 66, |
| 4225 | GIR_EraseRootFromParent_Done, |
| 4226 | // Label 283: @19236 |
| 4227 | GIM_Try, /*On fail goto*//*Label 284*/ GIMT_Encode4(19262), // Rule ID 54 // |
| 4228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4229 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4230 | // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18506>> => (S_AND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4231 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 4232 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4233 | GIR_RootConstrainSelectedInstOperands, |
| 4234 | // GIR_Coverage, 54, |
| 4235 | GIR_Done, |
| 4236 | // Label 284: @19262 |
| 4237 | GIM_Try, /*On fail goto*//*Label 285*/ GIMT_Encode4(19282), // Rule ID 751 // |
| 4238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4239 | // (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_AND_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 4240 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 4241 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4242 | GIR_RootConstrainSelectedInstOperands, |
| 4243 | // GIR_Coverage, 751, |
| 4244 | GIR_Done, |
| 4245 | // Label 285: @19282 |
| 4246 | GIM_Reject, |
| 4247 | // Label 281: @19283 |
| 4248 | GIM_Reject, |
| 4249 | // Label 268: @19284 |
| 4250 | GIM_Try, /*On fail goto*//*Label 286*/ GIMT_Encode4(19408), |
| 4251 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 4252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 4253 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4255 | GIM_Try, /*On fail goto*//*Label 287*/ GIMT_Encode4(19346), // Rule ID 8043 // |
| 4256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 4259 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 4260 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4261 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4262 | // (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }), i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 4263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4265 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4266 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4267 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4268 | GIR_RootConstrainSelectedInstOperands, |
| 4269 | // GIR_Coverage, 8043, |
| 4270 | GIR_EraseRootFromParent_Done, |
| 4271 | // Label 287: @19346 |
| 4272 | GIM_Try, /*On fail goto*//*Label 288*/ GIMT_Encode4(19389), // Rule ID 67 // |
| 4273 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4274 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4275 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 4276 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 4277 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4278 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4279 | // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 4280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4282 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4283 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4284 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4285 | GIR_RootConstrainSelectedInstOperands, |
| 4286 | // GIR_Coverage, 67, |
| 4287 | GIR_EraseRootFromParent_Done, |
| 4288 | // Label 288: @19389 |
| 4289 | GIM_Try, /*On fail goto*//*Label 289*/ GIMT_Encode4(19407), // Rule ID 55 // |
| 4290 | // (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18506>> => (S_AND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 4291 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B64), |
| 4292 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4293 | GIR_RootConstrainSelectedInstOperands, |
| 4294 | // GIR_Coverage, 55, |
| 4295 | GIR_Done, |
| 4296 | // Label 289: @19407 |
| 4297 | GIM_Reject, |
| 4298 | // Label 286: @19408 |
| 4299 | GIM_Reject, |
| 4300 | // Label 269: @19409 |
| 4301 | GIM_Try, /*On fail goto*//*Label 290*/ GIMT_Encode4(19559), |
| 4302 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 4303 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4304 | GIM_Try, /*On fail goto*//*Label 291*/ GIMT_Encode4(19479), // Rule ID 8116 // |
| 4305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4307 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 4309 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4311 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4312 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4314 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4315 | // (and:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }), v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1) |
| 4316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4318 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4320 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4321 | GIR_RootConstrainSelectedInstOperands, |
| 4322 | // GIR_Coverage, 8116, |
| 4323 | GIR_EraseRootFromParent_Done, |
| 4324 | // Label 291: @19479 |
| 4325 | GIM_Try, /*On fail goto*//*Label 292*/ GIMT_Encode4(19538), // Rule ID 1658 // |
| 4326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4327 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4328 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4329 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 4330 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 4331 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4332 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4333 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4335 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4336 | // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1) |
| 4337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B32), |
| 4338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4339 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4341 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4342 | GIR_RootConstrainSelectedInstOperands, |
| 4343 | // GIR_Coverage, 1658, |
| 4344 | GIR_EraseRootFromParent_Done, |
| 4345 | // Label 292: @19538 |
| 4346 | GIM_Try, /*On fail goto*//*Label 293*/ GIMT_Encode4(19558), // Rule ID 2163 // |
| 4347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4348 | // (and:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1) => (V_AND_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1) |
| 4349 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 4350 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4351 | GIR_RootConstrainSelectedInstOperands, |
| 4352 | // GIR_Coverage, 2163, |
| 4353 | GIR_Done, |
| 4354 | // Label 293: @19558 |
| 4355 | GIM_Reject, |
| 4356 | // Label 290: @19559 |
| 4357 | GIM_Reject, |
| 4358 | // Label 270: @19560 |
| 4359 | GIM_Try, /*On fail goto*//*Label 294*/ GIMT_Encode4(19682), |
| 4360 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4361 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4362 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4364 | GIM_Try, /*On fail goto*//*Label 295*/ GIMT_Encode4(19630), // Rule ID 8118 // |
| 4365 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4366 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4367 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4368 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4369 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4370 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4371 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4372 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4373 | // (and:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }), v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1) |
| 4374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4376 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4377 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4378 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4379 | GIR_RootConstrainSelectedInstOperands, |
| 4380 | // GIR_Coverage, 8118, |
| 4381 | GIR_EraseRootFromParent_Done, |
| 4382 | // Label 295: @19630 |
| 4383 | GIM_Try, /*On fail goto*//*Label 296*/ GIMT_Encode4(19681), // Rule ID 1660 // |
| 4384 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4385 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4386 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 4387 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 4388 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4389 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4390 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4391 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4392 | // (and:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1) |
| 4393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4395 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4396 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4397 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4398 | GIR_RootConstrainSelectedInstOperands, |
| 4399 | // GIR_Coverage, 1660, |
| 4400 | GIR_EraseRootFromParent_Done, |
| 4401 | // Label 296: @19681 |
| 4402 | GIM_Reject, |
| 4403 | // Label 294: @19682 |
| 4404 | GIM_Reject, |
| 4405 | // Label 271: @19683 |
| 4406 | GIM_Try, /*On fail goto*//*Label 297*/ GIMT_Encode4(19805), |
| 4407 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4408 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4409 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18506), |
| 4410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4411 | GIM_Try, /*On fail goto*//*Label 298*/ GIMT_Encode4(19753), // Rule ID 8117 // |
| 4412 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4413 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4414 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4415 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4416 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4417 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4418 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4419 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4420 | // (and:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }), v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1) |
| 4421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4423 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4424 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4425 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4426 | GIR_RootConstrainSelectedInstOperands, |
| 4427 | // GIR_Coverage, 8117, |
| 4428 | GIR_EraseRootFromParent_Done, |
| 4429 | // Label 298: @19753 |
| 4430 | GIM_Try, /*On fail goto*//*Label 299*/ GIMT_Encode4(19804), // Rule ID 1659 // |
| 4431 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4432 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4433 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 4434 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 4435 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4436 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 4437 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 4438 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 4439 | // (and:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }))<<P:Predicate_anonymous_18506>> => (S_ANDN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1) |
| 4440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ANDN2_B64), |
| 4441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4442 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4443 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4444 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4445 | GIR_RootConstrainSelectedInstOperands, |
| 4446 | // GIR_Coverage, 1659, |
| 4447 | GIR_EraseRootFromParent_Done, |
| 4448 | // Label 299: @19804 |
| 4449 | GIM_Reject, |
| 4450 | // Label 297: @19805 |
| 4451 | GIM_Reject, |
| 4452 | // Label 272: @19806 |
| 4453 | GIM_Reject, |
| 4454 | // Label 4: @19807 |
| 4455 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(17), /*)*//*default:*//*Label 307*/ GIMT_Encode4(34274), |
| 4456 | /*GILLT_s1*//*Label 300*/ GIMT_Encode4(19858), |
| 4457 | /*GILLT_s16*//*Label 301*/ GIMT_Encode4(19921), |
| 4458 | /*GILLT_s32*//*Label 302*/ GIMT_Encode4(20079), |
| 4459 | /*GILLT_s64*//*Label 303*/ GIMT_Encode4(24688), |
| 4460 | /*GILLT_v2s16*//*Label 304*/ GIMT_Encode4(33877), |
| 4461 | /*GILLT_v2s32*//*Label 305*/ GIMT_Encode4(34028), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 4462 | /*GILLT_v4s16*//*Label 306*/ GIMT_Encode4(34151), |
| 4463 | // Label 300: @19858 |
| 4464 | GIM_Try, /*On fail goto*//*Label 308*/ GIMT_Encode4(19920), |
| 4465 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 4466 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 4467 | GIM_Try, /*On fail goto*//*Label 309*/ GIMT_Encode4(19894), // Rule ID 7164 // |
| 4468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 4469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 4470 | // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_OR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 4471 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64), |
| 4472 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4473 | GIR_RootConstrainSelectedInstOperands, |
| 4474 | // GIR_Coverage, 7164, |
| 4475 | GIR_Done, |
| 4476 | // Label 309: @19894 |
| 4477 | GIM_Try, /*On fail goto*//*Label 310*/ GIMT_Encode4(19919), // Rule ID 7171 // |
| 4478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 4479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4480 | // (or:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_OR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 4481 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 4482 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 4483 | GIR_RootConstrainSelectedInstOperands, |
| 4484 | // GIR_Coverage, 7171, |
| 4485 | GIR_Done, |
| 4486 | // Label 310: @19919 |
| 4487 | GIM_Reject, |
| 4488 | // Label 308: @19920 |
| 4489 | GIM_Reject, |
| 4490 | // Label 301: @19921 |
| 4491 | GIM_Try, /*On fail goto*//*Label 311*/ GIMT_Encode4(20078), |
| 4492 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 4493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 4494 | GIM_Try, /*On fail goto*//*Label 312*/ GIMT_Encode4(19983), // Rule ID 8119 // |
| 4495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4496 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4497 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4498 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 4499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 4500 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4501 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 4502 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4503 | // (or:{ *:[i16] } (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }), i16:{ *:[i16] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1) |
| 4504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 4505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4506 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 4507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4508 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4509 | GIR_RootConstrainSelectedInstOperands, |
| 4510 | // GIR_Coverage, 8119, |
| 4511 | GIR_EraseRootFromParent_Done, |
| 4512 | // Label 312: @19983 |
| 4513 | GIM_Try, /*On fail goto*//*Label 313*/ GIMT_Encode4(20034), // Rule ID 1661 // |
| 4514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 4515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 4518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 4519 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 4520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 4521 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 4522 | // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, (xor:{ *:[i16] } i16:{ *:[i16] }:$src1, -1:{ *:[i16] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[i16] }:{ *:[i1] } SSrc_b32:{ *:[i16] }:$src0, SSrc_b32:{ *:[i16] }:$src1) |
| 4523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 4524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 4525 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 4526 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 4527 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 4528 | GIR_RootConstrainSelectedInstOperands, |
| 4529 | // GIR_Coverage, 1661, |
| 4530 | GIR_EraseRootFromParent_Done, |
| 4531 | // Label 313: @20034 |
| 4532 | GIM_Try, /*On fail goto*//*Label 314*/ GIMT_Encode4(20054), // Rule ID 2161 // |
| 4533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4534 | // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_OR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1) |
| 4535 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 4536 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4537 | GIR_RootConstrainSelectedInstOperands, |
| 4538 | // GIR_Coverage, 2161, |
| 4539 | GIR_Done, |
| 4540 | // Label 314: @20054 |
| 4541 | GIM_Try, /*On fail goto*//*Label 315*/ GIMT_Encode4(20077), // Rule ID 830 // |
| 4542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 4543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4544 | // (or:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_OR_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 4545 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B16_t16_e64), |
| 4546 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 4547 | GIR_RootConstrainSelectedInstOperands, |
| 4548 | // GIR_Coverage, 830, |
| 4549 | GIR_Done, |
| 4550 | // Label 315: @20077 |
| 4551 | GIM_Reject, |
| 4552 | // Label 311: @20078 |
| 4553 | GIM_Reject, |
| 4554 | // Label 302: @20079 |
| 4555 | GIM_Try, /*On fail goto*//*Label 316*/ GIMT_Encode4(24687), |
| 4556 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 4557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 4558 | GIM_Try, /*On fail goto*//*Label 317*/ GIMT_Encode4(20228), // Rule ID 10797 // |
| 4559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4560 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4564 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4565 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4566 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4567 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4568 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 4569 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 4570 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 4571 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4572 | // MIs[3] x |
| 4573 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 4574 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4575 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4576 | // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4577 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4578 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4579 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4580 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4581 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4582 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 4583 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4584 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4585 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4586 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y |
| 4587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4588 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4589 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4590 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 4591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4597 | GIR_RootConstrainSelectedInstOperands, |
| 4598 | // GIR_Coverage, 10797, |
| 4599 | GIR_EraseRootFromParent_Done, |
| 4600 | // Label 317: @20228 |
| 4601 | GIM_Try, /*On fail goto*//*Label 318*/ GIMT_Encode4(20366), // Rule ID 10796 // |
| 4602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4603 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4606 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4607 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4608 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4609 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4610 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4611 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 4612 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 4613 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 4614 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 4615 | // MIs[3] x |
| 4616 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 4617 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4618 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4619 | // (or:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4620 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4621 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4622 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4623 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4624 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4625 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 4626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4627 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4628 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4629 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y |
| 4630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4631 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4632 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4633 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 4634 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4637 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4639 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4640 | GIR_RootConstrainSelectedInstOperands, |
| 4641 | // GIR_Coverage, 10796, |
| 4642 | GIR_EraseRootFromParent_Done, |
| 4643 | // Label 318: @20366 |
| 4644 | GIM_Try, /*On fail goto*//*Label 319*/ GIMT_Encode4(20504), // Rule ID 10795 // |
| 4645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4646 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4647 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4649 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4650 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4651 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4652 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4653 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4654 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 4655 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 4656 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 4657 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4658 | // MIs[3] x |
| 4659 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 4660 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4661 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4662 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4663 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4664 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4665 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4666 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4667 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4668 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 4669 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4670 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4671 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4672 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/2, // y |
| 4673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4676 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 4677 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4680 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4681 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4682 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4683 | GIR_RootConstrainSelectedInstOperands, |
| 4684 | // GIR_Coverage, 10795, |
| 4685 | GIR_EraseRootFromParent_Done, |
| 4686 | // Label 319: @20504 |
| 4687 | GIM_Try, /*On fail goto*//*Label 320*/ GIMT_Encode4(20642), // Rule ID 10794 // |
| 4688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4689 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4690 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4691 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4692 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4693 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4694 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4695 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4696 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4697 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 4698 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 4699 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 4700 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 4701 | // MIs[3] x |
| 4702 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 4703 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4704 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4705 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })), (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4706 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4707 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4708 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4709 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4710 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4711 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 4712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4713 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4714 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4715 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/3, /*OpIdx*/1, // y |
| 4716 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4717 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4718 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4719 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 4720 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4725 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4726 | GIR_RootConstrainSelectedInstOperands, |
| 4727 | // GIR_Coverage, 10794, |
| 4728 | GIR_EraseRootFromParent_Done, |
| 4729 | // Label 320: @20642 |
| 4730 | GIM_Try, /*On fail goto*//*Label 321*/ GIMT_Encode4(20780), // Rule ID 10791 // |
| 4731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4732 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4734 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4735 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4736 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4737 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4738 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4739 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4740 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 4741 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4742 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4743 | // MIs[3] x |
| 4744 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 4745 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 4746 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4747 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4748 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4750 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4751 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4752 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4753 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4754 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 4755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4756 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4757 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4758 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 4759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4760 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4761 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4762 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 4763 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4767 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4768 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4769 | GIR_RootConstrainSelectedInstOperands, |
| 4770 | // GIR_Coverage, 10791, |
| 4771 | GIR_EraseRootFromParent_Done, |
| 4772 | // Label 321: @20780 |
| 4773 | GIM_Try, /*On fail goto*//*Label 322*/ GIMT_Encode4(20918), // Rule ID 10793 // |
| 4774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4775 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4776 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4777 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4778 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4779 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4780 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4781 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4782 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4783 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 4784 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4785 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4786 | // MIs[3] x |
| 4787 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 4788 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 4789 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4790 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4791 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] }), i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4792 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4793 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4794 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4795 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4796 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4797 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 4798 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4799 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4800 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4801 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 4802 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4803 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4804 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4805 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 4806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4809 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4810 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4811 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4812 | GIR_RootConstrainSelectedInstOperands, |
| 4813 | // GIR_Coverage, 10793, |
| 4814 | GIR_EraseRootFromParent_Done, |
| 4815 | // Label 322: @20918 |
| 4816 | GIM_Try, /*On fail goto*//*Label 323*/ GIMT_Encode4(21056), // Rule ID 7082 // |
| 4817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4818 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4819 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4820 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4821 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4822 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4823 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4824 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4825 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4826 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 4827 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4828 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4829 | // MIs[3] x |
| 4830 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 4831 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 4832 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4833 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4834 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4835 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4836 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4837 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4838 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4839 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4840 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 4841 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4842 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4843 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4844 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 4845 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4846 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4847 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4848 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 4849 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4852 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4853 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4854 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4855 | GIR_RootConstrainSelectedInstOperands, |
| 4856 | // GIR_Coverage, 7082, |
| 4857 | GIR_EraseRootFromParent_Done, |
| 4858 | // Label 323: @21056 |
| 4859 | GIM_Try, /*On fail goto*//*Label 324*/ GIMT_Encode4(21194), // Rule ID 10792 // |
| 4860 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4861 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4862 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4863 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4864 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4865 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 4866 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4867 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4868 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4869 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 4870 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 4871 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 4872 | // MIs[3] x |
| 4873 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 4874 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 4875 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4876 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4877 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, (xor:{ *:[i32] } i32:{ *:[i32] }:$x, -1:{ *:[i32] })))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 4878 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4879 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4880 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4881 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4882 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4883 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 4884 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 4885 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4886 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4887 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 4888 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 4889 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4890 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4891 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 4892 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 4893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 4894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4895 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 4896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 4897 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 4898 | GIR_RootConstrainSelectedInstOperands, |
| 4899 | // GIR_Coverage, 10792, |
| 4900 | GIR_EraseRootFromParent_Done, |
| 4901 | // Label 324: @21194 |
| 4902 | GIM_Try, /*On fail goto*//*Label 325*/ GIMT_Encode4(21287), // Rule ID 2227 // |
| 4903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 4904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4905 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4906 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 4907 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4908 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4909 | GIM_CheckHasOneUse, /*MI*/1, |
| 4910 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 4911 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4912 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4913 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4914 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4915 | GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y |
| 4916 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 4917 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4918 | // MIs[3] Operand 1 |
| 4919 | // No operand predicates |
| 4920 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 4921 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z |
| 4922 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24033), |
| 4923 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4924 | // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_24023>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_24033>> => (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 4925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64), |
| 4926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 4928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 4929 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 4930 | GIR_RootConstrainSelectedInstOperands, |
| 4931 | // GIR_Coverage, 2227, |
| 4932 | GIR_EraseRootFromParent_Done, |
| 4933 | // Label 325: @21287 |
| 4934 | GIM_Try, /*On fail goto*//*Label 326*/ GIMT_Encode4(21380), // Rule ID 8132 // |
| 4935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 4936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4937 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z |
| 4938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 4939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 4940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4941 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4942 | GIM_CheckHasOneUse, /*MI*/1, |
| 4943 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 4944 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 4945 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 4946 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4947 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4948 | GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/1, // Name : pred:5:y |
| 4949 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 4950 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 4951 | // MIs[3] Operand 1 |
| 4952 | // No operand predicates |
| 4953 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 4954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24033), |
| 4955 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4956 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, (and:{ *:[i32] } i32:{ *:[i32] }:$src1:$pred:5:y, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_24023>>)<<P:5:Predicate_anonymous_24033>> => (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 4957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64), |
| 4958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 4959 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 4960 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 4961 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 4962 | GIR_RootConstrainSelectedInstOperands, |
| 4963 | // GIR_Coverage, 8132, |
| 4964 | GIR_EraseRootFromParent_Done, |
| 4965 | // Label 326: @21380 |
| 4966 | GIM_Try, /*On fail goto*//*Label 327*/ GIMT_Encode4(21553), // Rule ID 10842 // |
| 4967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 4968 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 4969 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 4970 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 4971 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 4972 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 4973 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 4974 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 4975 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 4976 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 4977 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 4978 | // MIs[3] x |
| 4979 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 4980 | // MIs[3] z |
| 4981 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 4982 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 4983 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 4984 | // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 4985 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 4986 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 4987 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 4988 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 4989 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 4990 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4991 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4992 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 4993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 4994 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4995 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 4996 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 4997 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 4998 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 4999 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5000 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5002 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5003 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5004 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 5005 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5006 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5007 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5008 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5009 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5010 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5013 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5014 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5015 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5016 | GIR_RootConstrainSelectedInstOperands, |
| 5017 | // GIR_Coverage, 10842, |
| 5018 | GIR_EraseRootFromParent_Done, |
| 5019 | // Label 327: @21553 |
| 5020 | GIM_Try, /*On fail goto*//*Label 328*/ GIMT_Encode4(21726), // Rule ID 10843 // |
| 5021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5022 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5023 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5024 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5025 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5026 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5027 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5028 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5029 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5030 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5031 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5032 | // MIs[3] z |
| 5033 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5034 | // MIs[3] x |
| 5035 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5036 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5037 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5038 | // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5039 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5040 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5041 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5042 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5043 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5044 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5045 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5046 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5047 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5048 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5049 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5050 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 5051 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5052 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5053 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5054 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5055 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5056 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5057 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5058 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 5059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5060 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5061 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5062 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5063 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5064 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5068 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5069 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5070 | GIR_RootConstrainSelectedInstOperands, |
| 5071 | // GIR_Coverage, 10843, |
| 5072 | GIR_EraseRootFromParent_Done, |
| 5073 | // Label 328: @21726 |
| 5074 | GIM_Try, /*On fail goto*//*Label 329*/ GIMT_Encode4(21899), // Rule ID 10844 // |
| 5075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5076 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5077 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5078 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5079 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5080 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5081 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5082 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5083 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5084 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5085 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5086 | // MIs[3] x |
| 5087 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5088 | // MIs[3] z |
| 5089 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5090 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5091 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5092 | // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5093 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5094 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5095 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5096 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5097 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5098 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5099 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5100 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5102 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5103 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5104 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 5105 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5106 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5107 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5108 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5109 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5110 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5111 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5112 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x |
| 5113 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5116 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5117 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5118 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5121 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5122 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5123 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5124 | GIR_RootConstrainSelectedInstOperands, |
| 5125 | // GIR_Coverage, 10844, |
| 5126 | GIR_EraseRootFromParent_Done, |
| 5127 | // Label 329: @21899 |
| 5128 | GIM_Try, /*On fail goto*//*Label 330*/ GIMT_Encode4(22072), // Rule ID 10845 // |
| 5129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5130 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5131 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5133 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5134 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 5135 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5136 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5137 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5138 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5139 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5140 | // MIs[3] z |
| 5141 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5142 | // MIs[3] x |
| 5143 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5144 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5145 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5146 | // (or:{ *:[i32] } (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5147 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5148 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5149 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5150 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5151 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5152 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5153 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5154 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5156 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5157 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5158 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 5159 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5160 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5161 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5162 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, // y |
| 5163 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5164 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5165 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5166 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x |
| 5167 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5168 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5169 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5170 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5171 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5172 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5175 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5177 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5178 | GIR_RootConstrainSelectedInstOperands, |
| 5179 | // GIR_Coverage, 10845, |
| 5180 | GIR_EraseRootFromParent_Done, |
| 5181 | // Label 330: @22072 |
| 5182 | GIM_Try, /*On fail goto*//*Label 331*/ GIMT_Encode4(22245), // Rule ID 10838 // |
| 5183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5184 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5185 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5186 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5187 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5188 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5189 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5190 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5191 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5192 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5193 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5194 | // MIs[3] x |
| 5195 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5196 | // MIs[3] z |
| 5197 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5198 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5199 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5200 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5201 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5202 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5203 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5204 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5205 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5206 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5207 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5208 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5209 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5210 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5211 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5212 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 5213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5214 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5215 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5216 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5217 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5218 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5219 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5220 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 5221 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5222 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5223 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5224 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5225 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5229 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5230 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5231 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5232 | GIR_RootConstrainSelectedInstOperands, |
| 5233 | // GIR_Coverage, 10838, |
| 5234 | GIR_EraseRootFromParent_Done, |
| 5235 | // Label 331: @22245 |
| 5236 | GIM_Try, /*On fail goto*//*Label 332*/ GIMT_Encode4(22418), // Rule ID 10839 // |
| 5237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5238 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5239 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5240 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5241 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5242 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5243 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5244 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5245 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5246 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5247 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5248 | // MIs[3] z |
| 5249 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5250 | // MIs[3] x |
| 5251 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5252 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5253 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5254 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5255 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5256 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5257 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5258 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5259 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5260 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5261 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5262 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5263 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5264 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5265 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5266 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 5267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5268 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5269 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5270 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5272 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5273 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5274 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // x |
| 5275 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5276 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5277 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5278 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5279 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5280 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5283 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5284 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5285 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5286 | GIR_RootConstrainSelectedInstOperands, |
| 5287 | // GIR_Coverage, 10839, |
| 5288 | GIR_EraseRootFromParent_Done, |
| 5289 | // Label 332: @22418 |
| 5290 | GIM_Try, /*On fail goto*//*Label 333*/ GIMT_Encode4(22591), // Rule ID 10840 // |
| 5291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5292 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5293 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5294 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5295 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5296 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5297 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5298 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5299 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5300 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5301 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5302 | // MIs[3] x |
| 5303 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5304 | // MIs[3] z |
| 5305 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5307 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5308 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5310 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5311 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5312 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5313 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5314 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5315 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5316 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5317 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5318 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5319 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5320 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 5321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5322 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5323 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5324 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5325 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5326 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5327 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5328 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x |
| 5329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5330 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5332 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5333 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5334 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5339 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5340 | GIR_RootConstrainSelectedInstOperands, |
| 5341 | // GIR_Coverage, 10840, |
| 5342 | GIR_EraseRootFromParent_Done, |
| 5343 | // Label 333: @22591 |
| 5344 | GIM_Try, /*On fail goto*//*Label 334*/ GIMT_Encode4(22764), // Rule ID 10841 // |
| 5345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5346 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5347 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5348 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5349 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5350 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 5351 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 5352 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5353 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5354 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 5355 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 5356 | // MIs[3] z |
| 5357 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 5358 | // MIs[3] x |
| 5359 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 5360 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5361 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5362 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)), (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5363 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5364 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5365 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5366 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5367 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5368 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5369 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5370 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5372 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5373 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5374 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 5375 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5376 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5377 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5378 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, // y |
| 5379 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5380 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5381 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5382 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // x |
| 5383 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5384 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5385 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5386 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5387 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5388 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5391 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5392 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5394 | GIR_RootConstrainSelectedInstOperands, |
| 5395 | // GIR_Coverage, 10841, |
| 5396 | GIR_EraseRootFromParent_Done, |
| 5397 | // Label 334: @22764 |
| 5398 | GIM_Try, /*On fail goto*//*Label 335*/ GIMT_Encode4(22937), // Rule ID 10832 // |
| 5399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5400 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5401 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5402 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5403 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5404 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5405 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5406 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5407 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5408 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5409 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5410 | // MIs[3] x |
| 5411 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5412 | // MIs[3] z |
| 5413 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5414 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5415 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5416 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5417 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5418 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5419 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5420 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5421 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5422 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5423 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5424 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5425 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5426 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5427 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5428 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 5429 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5430 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5431 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5432 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5433 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5434 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5435 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5436 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 5437 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5438 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5439 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5440 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5441 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5447 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5448 | GIR_RootConstrainSelectedInstOperands, |
| 5449 | // GIR_Coverage, 10832, |
| 5450 | GIR_EraseRootFromParent_Done, |
| 5451 | // Label 335: @22937 |
| 5452 | GIM_Try, /*On fail goto*//*Label 336*/ GIMT_Encode4(23110), // Rule ID 10833 // |
| 5453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5454 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5455 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5456 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5457 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5458 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5459 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5460 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5461 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5462 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5463 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5464 | // MIs[3] z |
| 5465 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5466 | // MIs[3] x |
| 5467 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5468 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5469 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5470 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5471 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5472 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5473 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5474 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5475 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5476 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5477 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5478 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5479 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5480 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5481 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5482 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 5483 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5484 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5485 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5486 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5487 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5488 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5489 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5490 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 5491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5492 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5493 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5494 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5495 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5496 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5500 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5501 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5502 | GIR_RootConstrainSelectedInstOperands, |
| 5503 | // GIR_Coverage, 10833, |
| 5504 | GIR_EraseRootFromParent_Done, |
| 5505 | // Label 336: @23110 |
| 5506 | GIM_Try, /*On fail goto*//*Label 337*/ GIMT_Encode4(23283), // Rule ID 10836 // |
| 5507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5508 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5511 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5512 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5514 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5515 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5516 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5517 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5518 | // MIs[3] x |
| 5519 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5520 | // MIs[3] z |
| 5521 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5522 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5523 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5524 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5526 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5527 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5528 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5529 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5530 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5531 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5532 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5533 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5534 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5535 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5536 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 5537 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5538 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5539 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5540 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5541 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5542 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5543 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5544 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 5545 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5546 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5547 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5548 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5549 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5550 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5553 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5556 | GIR_RootConstrainSelectedInstOperands, |
| 5557 | // GIR_Coverage, 10836, |
| 5558 | GIR_EraseRootFromParent_Done, |
| 5559 | // Label 337: @23283 |
| 5560 | GIM_Try, /*On fail goto*//*Label 338*/ GIMT_Encode4(23456), // Rule ID 10837 // |
| 5561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5562 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5563 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5564 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5565 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5566 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5567 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5568 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5569 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5570 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 5571 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5572 | // MIs[3] z |
| 5573 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5574 | // MIs[3] x |
| 5575 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5576 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5577 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5578 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$y))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5579 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5580 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5581 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5582 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5583 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5584 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5585 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5586 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5587 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5588 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5589 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5590 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 5591 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5592 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5593 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5594 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 5595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5596 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5597 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5598 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 5599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5602 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5603 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5604 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5607 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5608 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5609 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5610 | GIR_RootConstrainSelectedInstOperands, |
| 5611 | // GIR_Coverage, 10837, |
| 5612 | GIR_EraseRootFromParent_Done, |
| 5613 | // Label 338: @23456 |
| 5614 | GIM_Try, /*On fail goto*//*Label 339*/ GIMT_Encode4(23629), // Rule ID 7308 // |
| 5615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5616 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5617 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5618 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5619 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5620 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5621 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5622 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5623 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5624 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5625 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5626 | // MIs[3] x |
| 5627 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5628 | // MIs[3] z |
| 5629 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5630 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5631 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5632 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5633 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5634 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5635 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5636 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5637 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5638 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5639 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5640 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5642 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5643 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5644 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 5645 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5646 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5647 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5648 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5649 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5650 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5651 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5652 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 5653 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5654 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5655 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5656 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5657 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5658 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5661 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5664 | GIR_RootConstrainSelectedInstOperands, |
| 5665 | // GIR_Coverage, 7308, |
| 5666 | GIR_EraseRootFromParent_Done, |
| 5667 | // Label 339: @23629 |
| 5668 | GIM_Try, /*On fail goto*//*Label 340*/ GIMT_Encode4(23802), // Rule ID 10831 // |
| 5669 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5670 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5671 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5672 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5673 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5674 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5675 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5676 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5677 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5678 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5679 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5680 | // MIs[3] z |
| 5681 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5682 | // MIs[3] x |
| 5683 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5684 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5685 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5686 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5688 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5689 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5690 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5691 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5692 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5693 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5694 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5695 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5696 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5697 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5698 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, // z |
| 5699 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5700 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5701 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5702 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5704 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5705 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5706 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 5707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5710 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5711 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5712 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5715 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5716 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5717 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5718 | GIR_RootConstrainSelectedInstOperands, |
| 5719 | // GIR_Coverage, 10831, |
| 5720 | GIR_EraseRootFromParent_Done, |
| 5721 | // Label 340: @23802 |
| 5722 | GIM_Try, /*On fail goto*//*Label 341*/ GIMT_Encode4(23975), // Rule ID 10834 // |
| 5723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5724 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5725 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5726 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5727 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5728 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5729 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5730 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5731 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5732 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5733 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5734 | // MIs[3] x |
| 5735 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5736 | // MIs[3] z |
| 5737 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5738 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5739 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5740 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$x, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5741 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5742 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5743 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5744 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5745 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5746 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5747 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5748 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5750 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5751 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5752 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 5753 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5754 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5755 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5756 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5757 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5758 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5759 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5760 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 5761 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5762 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5763 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5764 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5765 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5769 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5771 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5772 | GIR_RootConstrainSelectedInstOperands, |
| 5773 | // GIR_Coverage, 10834, |
| 5774 | GIR_EraseRootFromParent_Done, |
| 5775 | // Label 341: @23975 |
| 5776 | GIM_Try, /*On fail goto*//*Label 342*/ GIMT_Encode4(24148), // Rule ID 10835 // |
| 5777 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5778 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5779 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5780 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5781 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5782 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 5783 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 5784 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 5785 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 5786 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 5787 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 5788 | // MIs[3] z |
| 5789 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 5790 | // MIs[3] x |
| 5791 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 5792 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 5793 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 5794 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x), (and:{ *:[i32] } i32:{ *:[i32] }:$y, (or:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$x)))<<P:Predicate_anonymous_23251>> => (V_BFI_B32_e64:{ *:[i32] } (V_XOR_B32_e64:{ *:[i16] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] })) |
| 5795 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 5796 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 5797 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 5798 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 5799 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 5800 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5801 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5802 | GIR_Copy, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5803 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 5804 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5805 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5806 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, // z |
| 5807 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 5808 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5809 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5810 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 5811 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 5812 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 5813 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5814 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 5815 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 5816 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 5817 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 5818 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 5819 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 5820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 5821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 5822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5823 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 5824 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 5825 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 5826 | GIR_RootConstrainSelectedInstOperands, |
| 5827 | // GIR_Coverage, 10835, |
| 5828 | GIR_EraseRootFromParent_Done, |
| 5829 | // Label 342: @24148 |
| 5830 | GIM_Try, /*On fail goto*//*Label 343*/ GIMT_Encode4(24199), // Rule ID 8044 // |
| 5831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 5832 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5833 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 5834 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5835 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5836 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 5837 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 5838 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5839 | // (or:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }), i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 5840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 5841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 5842 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 5843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5844 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 5845 | GIR_RootConstrainSelectedInstOperands, |
| 5846 | // GIR_Coverage, 8044, |
| 5847 | GIR_EraseRootFromParent_Done, |
| 5848 | // Label 343: @24199 |
| 5849 | GIM_Try, /*On fail goto*//*Label 344*/ GIMT_Encode4(24250), // Rule ID 68 // |
| 5850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 5851 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5852 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 5853 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5854 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5855 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 5856 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 5857 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5858 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, -1:{ *:[i32] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 5859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 5860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 5861 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 5862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 5863 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 5864 | GIR_RootConstrainSelectedInstOperands, |
| 5865 | // GIR_Coverage, 68, |
| 5866 | GIR_EraseRootFromParent_Done, |
| 5867 | // Label 344: @24250 |
| 5868 | GIM_Try, /*On fail goto*//*Label 345*/ GIMT_Encode4(24315), // Rule ID 2228 // |
| 5869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5871 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5872 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5873 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5874 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5875 | GIM_CheckHasOneUse, /*MI*/1, |
| 5876 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x |
| 5877 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y |
| 5878 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:6:z |
| 5879 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24035), |
| 5880 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5881 | // (or:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_24036>>, i32:{ *:[i32] }:$src2:$pred:6:z)<<P:6:Predicate_anonymous_24035>> => (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64), |
| 5883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5884 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 5885 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 5886 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 5887 | GIR_RootConstrainSelectedInstOperands, |
| 5888 | // GIR_Coverage, 2228, |
| 5889 | GIR_EraseRootFromParent_Done, |
| 5890 | // Label 345: @24315 |
| 5891 | GIM_Try, /*On fail goto*//*Label 346*/ GIMT_Encode4(24380), // Rule ID 2229 // |
| 5892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5894 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5895 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 5896 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5897 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5898 | GIM_CheckHasOneUse, /*MI*/1, |
| 5899 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x |
| 5900 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y |
| 5901 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:7:z |
| 5902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24038), |
| 5903 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5904 | // (or:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_24039>>, i32:{ *:[i32] }:$src2:$pred:7:z)<<P:7:Predicate_anonymous_24038>> => (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64), |
| 5906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5907 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 5908 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 5909 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 5910 | GIR_RootConstrainSelectedInstOperands, |
| 5911 | // GIR_Coverage, 2229, |
| 5912 | GIR_EraseRootFromParent_Done, |
| 5913 | // Label 346: @24380 |
| 5914 | GIM_Try, /*On fail goto*//*Label 347*/ GIMT_Encode4(24445), // Rule ID 2226 // |
| 5915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 5918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5919 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5920 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5921 | GIM_CheckHasOneUse, /*MI*/1, |
| 5922 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 5923 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y |
| 5924 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:5:z |
| 5925 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24033), |
| 5926 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5927 | // (or:{ *:[i32] } (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_24023>>, i32:{ *:[i32] }:$src2:$pred:5:z)<<P:5:Predicate_anonymous_24033>> => (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64), |
| 5929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5930 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 5931 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 5932 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 5933 | GIR_RootConstrainSelectedInstOperands, |
| 5934 | // GIR_Coverage, 2226, |
| 5935 | GIR_EraseRootFromParent_Done, |
| 5936 | // Label 347: @24445 |
| 5937 | GIM_Try, /*On fail goto*//*Label 348*/ GIMT_Encode4(24510), // Rule ID 8133 // |
| 5938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5940 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:6:z |
| 5941 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5942 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 5943 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5944 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5945 | GIM_CheckHasOneUse, /*MI*/1, |
| 5946 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:6:x |
| 5947 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:6:y |
| 5948 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24035), |
| 5949 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5950 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:6:z, (and:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:6:x, i32:{ *:[i32] }:$src1:$pred:6:y)<<P:Predicate_anonymous_24036>>)<<P:6:Predicate_anonymous_24035>> => (V_AND_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_OR_B32_e64), |
| 5952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 5954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 5955 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 5956 | GIR_RootConstrainSelectedInstOperands, |
| 5957 | // GIR_Coverage, 8133, |
| 5958 | GIR_EraseRootFromParent_Done, |
| 5959 | // Label 348: @24510 |
| 5960 | GIM_Try, /*On fail goto*//*Label 349*/ GIMT_Encode4(24575), // Rule ID 8134 // |
| 5961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5963 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:7:z |
| 5964 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5965 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 5966 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5967 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5968 | GIM_CheckHasOneUse, /*MI*/1, |
| 5969 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:7:x |
| 5970 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:7:y |
| 5971 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24038), |
| 5972 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5973 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:7:z, (or:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:7:x, i32:{ *:[i32] }:$src1:$pred:7:y)<<P:Predicate_anonymous_24039>>)<<P:7:Predicate_anonymous_24038>> => (V_OR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR3_B32_e64), |
| 5975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5976 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 5977 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 5978 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 5979 | GIR_RootConstrainSelectedInstOperands, |
| 5980 | // GIR_Coverage, 8134, |
| 5981 | GIR_EraseRootFromParent_Done, |
| 5982 | // Label 349: @24575 |
| 5983 | GIM_Try, /*On fail goto*//*Label 350*/ GIMT_Encode4(24640), // Rule ID 8131 // |
| 5984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 5985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 5986 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:5:z |
| 5987 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 5988 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 5989 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 5990 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 5991 | GIM_CheckHasOneUse, /*MI*/1, |
| 5992 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:5:x |
| 5993 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:5:y |
| 5994 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24033), |
| 5995 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 5996 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:5:z, (shl:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:5:x, i32:{ *:[i32] }:$src1:$pred:5:y)<<P:Predicate_anonymous_24023>>)<<P:5:Predicate_anonymous_24033>> => (V_LSHL_OR_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 5997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64), |
| 5998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 5999 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 6000 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 6001 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 6002 | GIR_RootConstrainSelectedInstOperands, |
| 6003 | // GIR_Coverage, 8131, |
| 6004 | GIR_EraseRootFromParent_Done, |
| 6005 | // Label 350: @24640 |
| 6006 | GIM_Try, /*On fail goto*//*Label 351*/ GIMT_Encode4(24666), // Rule ID 56 // |
| 6007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 6008 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 6009 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18507>> => (S_OR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 6010 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 6011 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 6012 | GIR_RootConstrainSelectedInstOperands, |
| 6013 | // GIR_Coverage, 56, |
| 6014 | GIR_Done, |
| 6015 | // Label 351: @24666 |
| 6016 | GIM_Try, /*On fail goto*//*Label 352*/ GIMT_Encode4(24686), // Rule ID 752 // |
| 6017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6018 | // (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_OR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 6019 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 6020 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 6021 | GIR_RootConstrainSelectedInstOperands, |
| 6022 | // GIR_Coverage, 752, |
| 6023 | GIR_Done, |
| 6024 | // Label 352: @24686 |
| 6025 | GIM_Reject, |
| 6026 | // Label 316: @24687 |
| 6027 | GIM_Reject, |
| 6028 | // Label 303: @24688 |
| 6029 | GIM_Try, /*On fail goto*//*Label 353*/ GIMT_Encode4(33876), |
| 6030 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 6031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 6032 | GIM_Try, /*On fail goto*//*Label 354*/ GIMT_Encode4(25014), // Rule ID 10805 // |
| 6033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6034 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6035 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6036 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6037 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6038 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6039 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6040 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6041 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6042 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 6043 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6044 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6045 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6046 | // MIs[3] x |
| 6047 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6048 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6049 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6050 | // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6051 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6052 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6053 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6054 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6055 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6056 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6057 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6058 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6059 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6060 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6061 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6062 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6063 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6064 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6065 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6066 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6067 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6068 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6069 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6070 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6071 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6072 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6073 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6074 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6075 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6076 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6077 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6078 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6079 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6080 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6081 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6082 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6083 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6084 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6085 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6086 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6087 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6088 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6089 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6090 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6091 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6092 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6093 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6094 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6095 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6096 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6097 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6098 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6099 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6103 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6104 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6105 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6106 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6107 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6108 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6109 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6110 | // GIR_Coverage, 10805, |
| 6111 | GIR_EraseRootFromParent_Done, |
| 6112 | // Label 354: @25014 |
| 6113 | GIM_Try, /*On fail goto*//*Label 355*/ GIMT_Encode4(25329), // Rule ID 10804 // |
| 6114 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6115 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6116 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6117 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6118 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6119 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6120 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6121 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6122 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6123 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 6124 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6125 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6126 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 6127 | // MIs[3] x |
| 6128 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6129 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6130 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6131 | // (or:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6133 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6134 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6135 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6136 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6137 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6138 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6139 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6140 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6141 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6142 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6143 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6144 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6145 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6146 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6147 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6148 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6149 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6150 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6151 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6152 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6153 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6154 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6155 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6156 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6157 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6158 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6159 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6160 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6161 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6162 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6163 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6164 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6165 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6166 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6167 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6168 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6169 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6170 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6171 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6172 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6173 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6174 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6175 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6176 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6177 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6178 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6179 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6180 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6184 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6185 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6186 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6187 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6188 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6189 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6190 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6191 | // GIR_Coverage, 10804, |
| 6192 | GIR_EraseRootFromParent_Done, |
| 6193 | // Label 355: @25329 |
| 6194 | GIM_Try, /*On fail goto*//*Label 356*/ GIMT_Encode4(25644), // Rule ID 10803 // |
| 6195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6196 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6197 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6198 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6199 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6200 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6201 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6202 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6203 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6204 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 6205 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6206 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6207 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6208 | // MIs[3] x |
| 6209 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6210 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6211 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6212 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6213 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6214 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6215 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6216 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6217 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6218 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6219 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6220 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6221 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6222 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6223 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6224 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6225 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6226 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6227 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6228 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6229 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6230 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6231 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6232 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6233 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6234 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6235 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6236 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6237 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6238 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6239 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6240 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6241 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6242 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6243 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6244 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6245 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6246 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6247 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6248 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6249 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6250 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6251 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6252 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6253 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6254 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6255 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6256 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6257 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6258 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6259 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6260 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6261 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6262 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6265 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6266 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6268 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6269 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6270 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6271 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6272 | // GIR_Coverage, 10803, |
| 6273 | GIR_EraseRootFromParent_Done, |
| 6274 | // Label 356: @25644 |
| 6275 | GIM_Try, /*On fail goto*//*Label 357*/ GIMT_Encode4(25959), // Rule ID 10802 // |
| 6276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6277 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6278 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6279 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6280 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6281 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 6282 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6283 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6284 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6285 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, uint8_t(-1), |
| 6286 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6287 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6288 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s64, |
| 6289 | // MIs[3] x |
| 6290 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6291 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6292 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6293 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })), (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6295 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6296 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6297 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6298 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6299 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6300 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6301 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6302 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6303 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6304 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6305 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6306 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6307 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6308 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6309 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6310 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6311 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6312 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6313 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6314 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6315 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6316 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6317 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6318 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6319 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6320 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6321 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6323 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6324 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6325 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6326 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6327 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6328 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6329 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6330 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/3, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6331 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6332 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6333 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6334 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6335 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6336 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6337 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6338 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6339 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6340 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6341 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6342 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6343 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6346 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6347 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6348 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6349 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6350 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6351 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6352 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6353 | // GIR_Coverage, 10802, |
| 6354 | GIR_EraseRootFromParent_Done, |
| 6355 | // Label 357: @25959 |
| 6356 | GIM_Try, /*On fail goto*//*Label 358*/ GIMT_Encode4(26274), // Rule ID 10799 // |
| 6357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6358 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6359 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6360 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6361 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6362 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6363 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6364 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6365 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6366 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 6367 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6368 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6369 | // MIs[3] x |
| 6370 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 6371 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 6372 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6373 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6374 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6375 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6376 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6377 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6378 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6379 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6380 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6381 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6382 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6383 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6384 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6385 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6386 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6387 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6388 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6389 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6390 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6391 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6392 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6393 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6394 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6395 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6396 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6397 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6398 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6399 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6400 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6401 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6402 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6403 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6404 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6405 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6406 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6407 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6408 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6409 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6410 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6411 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6412 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6413 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6414 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6415 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6416 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6417 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6418 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6421 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6422 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6423 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6427 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6428 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6429 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6430 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6431 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6432 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6433 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6434 | // GIR_Coverage, 10799, |
| 6435 | GIR_EraseRootFromParent_Done, |
| 6436 | // Label 358: @26274 |
| 6437 | GIM_Try, /*On fail goto*//*Label 359*/ GIMT_Encode4(26589), // Rule ID 10801 // |
| 6438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6439 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6440 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6441 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6442 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6443 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6444 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6446 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6447 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 6448 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6449 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6450 | // MIs[3] x |
| 6451 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 6452 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 6453 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6454 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6455 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] }), i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6456 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6457 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6458 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6459 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6460 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6461 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6462 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6463 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6464 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6465 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6466 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6467 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6468 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6469 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6470 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6471 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6472 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6473 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6474 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6475 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6476 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6477 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6478 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6479 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6480 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6481 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6482 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6483 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6484 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6485 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6486 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6487 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6488 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6489 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6490 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6491 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6492 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6493 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6494 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6495 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6496 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6497 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6498 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6499 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6500 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6501 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6502 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6503 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6504 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6508 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6509 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6511 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6512 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6513 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6514 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6515 | // GIR_Coverage, 10801, |
| 6516 | GIR_EraseRootFromParent_Done, |
| 6517 | // Label 359: @26589 |
| 6518 | GIM_Try, /*On fail goto*//*Label 360*/ GIMT_Encode4(26904), // Rule ID 7084 // |
| 6519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6520 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6521 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6523 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6524 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6525 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6526 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6527 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6528 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6529 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6530 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6531 | // MIs[3] x |
| 6532 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 6533 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 6534 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6535 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6536 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6537 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6538 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6539 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6540 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6541 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6542 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6543 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6544 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6545 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6546 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6547 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6548 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6549 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6550 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6551 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6552 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6553 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6554 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6555 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6556 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6557 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6558 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6559 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6560 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6561 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6562 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6563 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6564 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6565 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6566 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6567 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6568 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6569 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6570 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6571 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6572 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6573 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6574 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6575 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6576 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6577 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6578 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6579 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6580 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6581 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6582 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6583 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6584 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6585 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6586 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6589 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6590 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6592 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6593 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6594 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6595 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6596 | // GIR_Coverage, 7084, |
| 6597 | GIR_EraseRootFromParent_Done, |
| 6598 | // Label 360: @26904 |
| 6599 | GIM_Try, /*On fail goto*//*Label 361*/ GIMT_Encode4(27219), // Rule ID 10800 // |
| 6600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6601 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6605 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 6606 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 6607 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6608 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6609 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 6610 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_XOR), |
| 6611 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s64, |
| 6612 | // MIs[3] x |
| 6613 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 6614 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, uint8_t(-1), |
| 6615 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6616 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6617 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, (xor:{ *:[i64] } i64:{ *:[i64] }:$x, -1:{ *:[i64] })))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6618 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6619 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 6620 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6621 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6622 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 6623 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6624 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 6625 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 6626 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6627 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6628 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6629 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6630 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6631 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6632 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6633 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6634 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6635 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6636 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6637 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6638 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6639 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6640 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6641 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6642 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6643 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 6644 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 6645 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 6646 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 6647 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6648 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6649 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6650 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6651 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6652 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6653 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6654 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6655 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6656 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6657 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6658 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6659 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6660 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6661 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6662 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6663 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6664 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6665 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 6666 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 6667 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6671 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6672 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 6673 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6674 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6675 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6676 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6677 | // GIR_Coverage, 10800, |
| 6678 | GIR_EraseRootFromParent_Done, |
| 6679 | // Label 361: @27219 |
| 6680 | GIM_Try, /*On fail goto*//*Label 362*/ GIMT_Encode4(27627), // Rule ID 10857 // |
| 6681 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6682 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6683 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6684 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6685 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6686 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6687 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 6688 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6689 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6690 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6691 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6692 | // MIs[3] x |
| 6693 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6694 | // MIs[3] z |
| 6695 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 6696 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6697 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6698 | // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6699 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6700 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 6701 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6702 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6703 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 6704 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6705 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 6706 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 6707 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 6708 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 6709 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 6710 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 6711 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6712 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6713 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6714 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6715 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6716 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6717 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6718 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6719 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6720 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6721 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6722 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6723 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6724 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6725 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6726 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6727 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6728 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6729 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6730 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6731 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6732 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6733 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 6734 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 6735 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 6736 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6737 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6738 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 6739 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 6740 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 6741 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 6742 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6743 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6744 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6745 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6746 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6747 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6748 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6749 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6750 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6751 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6752 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6753 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6754 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6755 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6756 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6757 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6758 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6759 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6760 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6761 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6762 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6763 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6764 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 6765 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 6766 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6769 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6770 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 6771 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 6772 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6776 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6777 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 6778 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6779 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6780 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6781 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6782 | // GIR_Coverage, 10857, |
| 6783 | GIR_EraseRootFromParent_Done, |
| 6784 | // Label 362: @27627 |
| 6785 | GIM_Try, /*On fail goto*//*Label 363*/ GIMT_Encode4(28035), // Rule ID 10858 // |
| 6786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6787 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6788 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6789 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6790 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6791 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6792 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 6793 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6794 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6795 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6796 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6797 | // MIs[3] z |
| 6798 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 6799 | // MIs[3] x |
| 6800 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6801 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6802 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6803 | // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6804 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6805 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 6806 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6807 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6808 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 6809 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6810 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 6811 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 6812 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 6813 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 6814 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 6815 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 6816 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6817 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6818 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6819 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6820 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6821 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6822 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6823 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6824 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6825 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6826 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6827 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6828 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6829 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6830 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6831 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6832 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6833 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6834 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6835 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6836 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6837 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6838 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 6839 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 6840 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 6841 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6842 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6843 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 6844 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 6845 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 6846 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 6847 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6848 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6849 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6850 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6851 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6852 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6853 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6854 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6855 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6856 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6857 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6858 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6859 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6860 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6861 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6862 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6863 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6864 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6865 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6866 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6867 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6868 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6869 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 6870 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 6871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6873 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6874 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6875 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 6876 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 6877 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6881 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6882 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 6883 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6884 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6885 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6886 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6887 | // GIR_Coverage, 10858, |
| 6888 | GIR_EraseRootFromParent_Done, |
| 6889 | // Label 363: @28035 |
| 6890 | GIM_Try, /*On fail goto*//*Label 364*/ GIMT_Encode4(28443), // Rule ID 10859 // |
| 6891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6892 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6893 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6894 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 6895 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 6896 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 6897 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 6898 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 6899 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 6900 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 6901 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 6902 | // MIs[3] x |
| 6903 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 6904 | // MIs[3] z |
| 6905 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 6906 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 6907 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 6908 | // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 6909 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 6910 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 6911 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 6912 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 6913 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 6914 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 6915 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 6916 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 6917 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 6918 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 6919 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 6920 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 6921 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6922 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6923 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6924 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6925 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6926 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6927 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6928 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 6929 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6930 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6931 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6932 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6933 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 6934 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6935 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6936 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6937 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6938 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 6939 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6940 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6941 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6942 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6943 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 6944 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 6945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 6946 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6947 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6948 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 6949 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 6950 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 6951 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 6952 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6953 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6954 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6955 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6956 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6957 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6958 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6959 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 6960 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6961 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6962 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6963 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6964 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 6965 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6966 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6967 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 6968 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6969 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 6970 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6971 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6972 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 6973 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6974 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 6975 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 6976 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 6977 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 6978 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 6979 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 6980 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 6981 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 6982 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 6983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 6984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 6985 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 6986 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 6987 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 6988 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 6989 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6990 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6991 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 6992 | // GIR_Coverage, 10859, |
| 6993 | GIR_EraseRootFromParent_Done, |
| 6994 | // Label 364: @28443 |
| 6995 | GIM_Try, /*On fail goto*//*Label 365*/ GIMT_Encode4(28851), // Rule ID 10860 // |
| 6996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 6997 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 6998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 6999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7000 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7001 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 7002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 7003 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7004 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7005 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7006 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7007 | // MIs[3] z |
| 7008 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7009 | // MIs[3] x |
| 7010 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 7011 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7012 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7013 | // (or:{ *:[i64] } (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7015 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7016 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7017 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7018 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7019 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7020 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7021 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7022 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7023 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7024 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7025 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7026 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7027 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7028 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7029 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7030 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7031 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7032 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7033 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7034 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7035 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7036 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7037 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7038 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7039 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7040 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7041 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7042 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7043 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7044 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7045 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7046 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7047 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7048 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7049 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7050 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7051 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7052 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7053 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7054 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7055 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7056 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7057 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7058 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7059 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7060 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7061 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7062 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7063 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7064 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7065 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7066 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7067 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7068 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7069 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7070 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7071 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7072 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7073 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7074 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7075 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7076 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7077 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7078 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7079 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7080 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7081 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7084 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7085 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7086 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7091 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7092 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7093 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7094 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7095 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7096 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7097 | // GIR_Coverage, 10860, |
| 7098 | GIR_EraseRootFromParent_Done, |
| 7099 | // Label 365: @28851 |
| 7100 | GIM_Try, /*On fail goto*//*Label 366*/ GIMT_Encode4(29259), // Rule ID 10853 // |
| 7101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7102 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7103 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7106 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7107 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 7108 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7109 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7110 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7111 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7112 | // MIs[3] x |
| 7113 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7114 | // MIs[3] z |
| 7115 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 7116 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7117 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7118 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7119 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7120 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7121 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7122 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7123 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7124 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7125 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7126 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7127 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7128 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7129 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7130 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7131 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7132 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7133 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7134 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7135 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7136 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7137 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7138 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7139 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7140 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7141 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7142 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7143 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7144 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7145 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7146 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7147 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7148 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7149 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7150 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7151 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7152 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7153 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7154 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7155 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7156 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7157 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7158 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7159 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7160 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7161 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7162 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7163 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7164 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7165 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7166 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7167 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7168 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7169 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7170 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7171 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7172 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7173 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7174 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7175 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7176 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7177 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7178 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7179 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7180 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7181 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7182 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7183 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7184 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7185 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7186 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7187 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7188 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7189 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7190 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7191 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7192 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7195 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7196 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7197 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7198 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7199 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7200 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7201 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7202 | // GIR_Coverage, 10853, |
| 7203 | GIR_EraseRootFromParent_Done, |
| 7204 | // Label 366: @29259 |
| 7205 | GIM_Try, /*On fail goto*//*Label 367*/ GIMT_Encode4(29667), // Rule ID 10854 // |
| 7206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7207 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7208 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7209 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7210 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7211 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7212 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 7213 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7214 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7215 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7216 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7217 | // MIs[3] z |
| 7218 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 7219 | // MIs[3] x |
| 7220 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7221 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7222 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7223 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7224 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7225 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7226 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7227 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7228 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7229 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7230 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7231 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7232 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7233 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7234 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7235 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7236 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7237 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7238 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7239 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7240 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7241 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7242 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7243 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7244 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7245 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7246 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7247 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7248 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7249 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7250 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7251 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7252 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7253 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7254 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7255 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7256 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7257 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7258 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7259 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7260 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7261 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7262 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7263 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7264 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7265 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7266 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7267 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7268 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7269 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7270 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7271 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7272 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7273 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7274 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7275 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7276 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7277 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7278 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7279 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7280 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7281 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7282 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7283 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7284 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7285 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7286 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7287 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7288 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7289 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7290 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7292 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7293 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7294 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7295 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7296 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7297 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7300 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7301 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7302 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7303 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7304 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7305 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7306 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7307 | // GIR_Coverage, 10854, |
| 7308 | GIR_EraseRootFromParent_Done, |
| 7309 | // Label 367: @29667 |
| 7310 | GIM_Try, /*On fail goto*//*Label 368*/ GIMT_Encode4(30075), // Rule ID 10855 // |
| 7311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7312 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7313 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7314 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7315 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7316 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7317 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 7318 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7319 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7320 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7321 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7322 | // MIs[3] x |
| 7323 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 7324 | // MIs[3] z |
| 7325 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7327 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7328 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7329 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7330 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7331 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7332 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7333 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7334 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7335 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7336 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7337 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7338 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7339 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7340 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7341 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7342 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7343 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7344 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7345 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7346 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7347 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7348 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7349 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7350 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7351 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7352 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7353 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7354 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7355 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7356 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7357 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7358 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7359 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7360 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7361 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7362 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7363 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7364 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7366 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7367 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7368 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7369 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7370 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7371 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7372 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7373 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7374 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7375 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7376 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7377 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7378 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7379 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7380 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7381 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7382 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7383 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7384 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7385 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7386 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7387 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7388 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7389 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7390 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7391 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7392 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7393 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7394 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7395 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7396 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7397 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7398 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7399 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7400 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7401 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7402 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7405 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7406 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7407 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7408 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7409 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7410 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7411 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7412 | // GIR_Coverage, 10855, |
| 7413 | GIR_EraseRootFromParent_Done, |
| 7414 | // Label 368: @30075 |
| 7415 | GIM_Try, /*On fail goto*//*Label 369*/ GIMT_Encode4(30483), // Rule ID 10856 // |
| 7416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7417 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7418 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7419 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7420 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7421 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 7422 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_OR), |
| 7423 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7424 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7425 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 7426 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_AND), |
| 7427 | // MIs[3] z |
| 7428 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 7429 | // MIs[3] x |
| 7430 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 7431 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7432 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7433 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)), (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7434 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7435 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7436 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7437 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7438 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7439 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7440 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7441 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7442 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7443 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7444 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7445 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7446 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7447 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7448 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7449 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7450 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7451 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7452 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7453 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7454 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7455 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7456 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7457 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7458 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7459 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7460 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7461 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7462 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7463 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7464 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7465 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7466 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7467 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7468 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7469 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7470 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7471 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7472 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7473 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7474 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7475 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7476 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7477 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7478 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7479 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7480 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7481 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7482 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7483 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7484 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7485 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7486 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7487 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7488 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7489 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7490 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7491 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7492 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7493 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7494 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7495 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7496 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7497 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7498 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7499 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7500 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7501 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7502 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7503 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7504 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7505 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7506 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7507 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7511 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7512 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7513 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7514 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7515 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7516 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7517 | // GIR_Coverage, 10856, |
| 7518 | GIR_EraseRootFromParent_Done, |
| 7519 | // Label 369: @30483 |
| 7520 | GIM_Try, /*On fail goto*//*Label 370*/ GIMT_Encode4(30891), // Rule ID 10847 // |
| 7521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7522 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7523 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7524 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7525 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7526 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7527 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7528 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7530 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7531 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 7532 | // MIs[3] x |
| 7533 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 7534 | // MIs[3] z |
| 7535 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 7536 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7537 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7538 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7539 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7540 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7541 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7542 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7543 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7544 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7545 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7546 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7547 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7548 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7549 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7550 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7551 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7552 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7553 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7554 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7555 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7556 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7557 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7558 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7559 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7560 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7561 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7562 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7563 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7564 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7565 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7566 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7567 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7568 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7569 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7570 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7571 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7572 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7573 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7574 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7576 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7577 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7578 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7579 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7580 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7581 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7582 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7583 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7584 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7585 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7586 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7587 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7588 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7589 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7590 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7591 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7592 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7593 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7594 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7595 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7596 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7597 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7598 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7599 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7600 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7601 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7602 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7603 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7604 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7605 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7606 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7607 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7608 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7609 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7610 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7611 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7612 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7616 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7617 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7618 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7619 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7620 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7621 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7622 | // GIR_Coverage, 10847, |
| 7623 | GIR_EraseRootFromParent_Done, |
| 7624 | // Label 370: @30891 |
| 7625 | GIM_Try, /*On fail goto*//*Label 371*/ GIMT_Encode4(31299), // Rule ID 10848 // |
| 7626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7627 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7628 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7629 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7630 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7631 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7632 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7633 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7634 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7635 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7636 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 7637 | // MIs[3] z |
| 7638 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 7639 | // MIs[3] x |
| 7640 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 7641 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7642 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7643 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7644 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7645 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7646 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7647 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7648 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7649 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7650 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7651 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7652 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7653 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7654 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7655 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7656 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7657 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7658 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7659 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7660 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7661 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7662 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7663 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7664 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7665 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7666 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7667 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7668 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7669 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7670 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7671 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7672 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7673 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7674 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7675 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7676 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7677 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7678 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7679 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7680 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7681 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7682 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7683 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7684 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7685 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7687 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7688 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7689 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7690 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7691 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7692 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7693 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7694 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7695 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7696 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7697 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7698 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7699 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7700 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7701 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7702 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7703 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7704 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7705 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7706 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7707 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7708 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7709 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7710 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7712 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7713 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7714 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7715 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7716 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7721 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7722 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7723 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7724 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7725 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7726 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7727 | // GIR_Coverage, 10848, |
| 7728 | GIR_EraseRootFromParent_Done, |
| 7729 | // Label 371: @31299 |
| 7730 | GIM_Try, /*On fail goto*//*Label 372*/ GIMT_Encode4(31707), // Rule ID 10851 // |
| 7731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7732 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7734 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7735 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7736 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7737 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7738 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7739 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7740 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7741 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 7742 | // MIs[3] x |
| 7743 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 7744 | // MIs[3] z |
| 7745 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 7746 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7747 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7748 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7750 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7751 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7752 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7753 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7754 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7755 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7756 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7757 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7758 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7759 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7760 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7761 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7762 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7763 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7764 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7765 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7766 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7767 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7768 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7769 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7770 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7771 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7772 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7773 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7774 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7775 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7776 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7777 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7778 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7779 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7780 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7781 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7782 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7783 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7784 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7785 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7786 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7787 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7788 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7789 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7790 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7791 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7792 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7793 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7794 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7795 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7796 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7797 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7798 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7799 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7800 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7801 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7802 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7803 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7804 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7805 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7806 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7807 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7808 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7809 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7810 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7811 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7812 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7813 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7814 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7815 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7816 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7819 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7820 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7821 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7822 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7825 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7826 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7827 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7828 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7829 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7830 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7831 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7832 | // GIR_Coverage, 10851, |
| 7833 | GIR_EraseRootFromParent_Done, |
| 7834 | // Label 372: @31707 |
| 7835 | GIM_Try, /*On fail goto*//*Label 373*/ GIMT_Encode4(32115), // Rule ID 10852 // |
| 7836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7837 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7838 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7839 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7840 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7841 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7842 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7843 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7844 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7845 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 7846 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 7847 | // MIs[3] z |
| 7848 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 7849 | // MIs[3] x |
| 7850 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 7851 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7852 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7853 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$y))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7855 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7856 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7857 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7858 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7859 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7860 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7861 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7862 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7863 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7864 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7865 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7866 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7867 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7868 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7869 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7870 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7871 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7872 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7873 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7874 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7875 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7876 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7877 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7878 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7879 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7880 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7881 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7882 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7883 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7884 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7885 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7886 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7887 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7888 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7889 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7891 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7892 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7893 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7894 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 7895 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 7896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 7897 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7898 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7899 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7900 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7901 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7902 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7903 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7904 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 7905 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7906 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7907 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7908 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7909 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 7910 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7911 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7912 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7913 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7914 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 7915 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7916 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7917 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7918 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7919 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 7920 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 7921 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 7922 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7923 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7924 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 7925 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 7926 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 7927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 7928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 7929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 7930 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 7931 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 7932 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 7933 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 7934 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7935 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7936 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7937 | // GIR_Coverage, 10852, |
| 7938 | GIR_EraseRootFromParent_Done, |
| 7939 | // Label 373: @32115 |
| 7940 | GIM_Try, /*On fail goto*//*Label 374*/ GIMT_Encode4(32523), // Rule ID 7309 // |
| 7941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7942 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 7943 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 7944 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 7945 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 7946 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 7947 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 7948 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 7949 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 7950 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 7951 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 7952 | // MIs[3] x |
| 7953 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 7954 | // MIs[3] z |
| 7955 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 7956 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 7957 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 7958 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 7959 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 7960 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 7961 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 7962 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 7963 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 7964 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 7965 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 7966 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 7967 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 7968 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 7969 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 7970 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 7971 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7972 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7973 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7974 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7975 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7976 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7977 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7978 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 7979 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7980 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7981 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7982 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7983 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 7984 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7985 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7986 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 7987 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7988 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 7989 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 7990 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 7991 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 7992 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7993 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 7994 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 7995 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 7996 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 7997 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 7998 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 7999 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 8000 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 8001 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 8002 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8003 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8004 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8005 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8006 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8007 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8008 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8009 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 8010 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8011 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8012 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8013 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8014 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8015 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8016 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8017 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8018 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8019 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 8020 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8021 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8022 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8023 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8024 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 8025 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 8026 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8027 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8028 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8029 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8030 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 8031 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 8032 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 8034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8035 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8036 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 8037 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 8038 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 8039 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8040 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8041 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8042 | // GIR_Coverage, 7309, |
| 8043 | GIR_EraseRootFromParent_Done, |
| 8044 | // Label 374: @32523 |
| 8045 | GIM_Try, /*On fail goto*//*Label 375*/ GIMT_Encode4(32931), // Rule ID 10846 // |
| 8046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8047 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8050 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8051 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 8054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 8055 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8056 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 8057 | // MIs[3] z |
| 8058 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 8059 | // MIs[3] x |
| 8060 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 8061 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 8062 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8063 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 8064 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8065 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8066 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8067 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 8068 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 8069 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 8070 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 8071 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 8072 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 8073 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 8074 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 8075 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 8076 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8077 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8078 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8079 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8080 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8081 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8082 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8083 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 8084 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8085 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8086 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8087 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8088 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8089 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8090 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8091 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8092 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8093 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 8094 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8095 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8096 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8097 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8098 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 8099 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 8100 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 8101 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8102 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8103 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 8104 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 8105 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 8106 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 8107 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8108 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8109 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8110 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8111 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8112 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8113 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8114 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 8115 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8116 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8117 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8118 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8119 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8120 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8121 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8122 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8123 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8124 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 8125 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8126 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8127 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8128 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8129 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 8130 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 8131 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8134 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8135 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 8136 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 8137 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 8139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8141 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 8142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 8143 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 8144 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8145 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8146 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8147 | // GIR_Coverage, 10846, |
| 8148 | GIR_EraseRootFromParent_Done, |
| 8149 | // Label 375: @32931 |
| 8150 | GIM_Try, /*On fail goto*//*Label 376*/ GIMT_Encode4(33339), // Rule ID 10849 // |
| 8151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8152 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8153 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8155 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8156 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8157 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8158 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 8159 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 8160 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8161 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 8162 | // MIs[3] x |
| 8163 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 8164 | // MIs[3] z |
| 8165 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 8166 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 8167 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8168 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$x, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 8169 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8170 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8171 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8172 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 8173 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 8174 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 8175 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 8176 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 8177 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 8178 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 8179 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 8180 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 8181 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8182 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8183 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8184 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8185 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8186 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8187 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8188 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 8189 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8190 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8191 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8192 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8193 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8194 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8195 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8196 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8197 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8198 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 8199 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8200 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8201 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8202 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8203 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 8204 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 8205 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 8206 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8207 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8208 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 8209 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 8210 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 8211 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 8212 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8213 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8214 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8215 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8216 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8217 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8218 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8219 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 8220 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8221 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8222 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8223 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8224 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8225 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8226 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8227 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8228 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8229 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 8230 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8231 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8232 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8233 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8234 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 8235 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 8236 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8237 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8238 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8239 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8240 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 8241 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 8242 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 8244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8245 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8246 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 8247 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 8248 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 8249 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8250 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8251 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8252 | // GIR_Coverage, 10849, |
| 8253 | GIR_EraseRootFromParent_Done, |
| 8254 | // Label 376: @33339 |
| 8255 | GIM_Try, /*On fail goto*//*Label 377*/ GIMT_Encode4(33747), // Rule ID 10850 // |
| 8256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8257 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8258 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8259 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8260 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8261 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 8262 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 8263 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 8264 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 8265 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 8266 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_OR), |
| 8267 | // MIs[3] z |
| 8268 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 8269 | // MIs[3] x |
| 8270 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 8271 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23251), |
| 8272 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 8273 | // (or:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x), (and:{ *:[i64] } i64:{ *:[i64] }:$y, (or:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$x)))<<P:Predicate_anonymous_23251>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (V_XOR_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 8274 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8275 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8276 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 8277 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 8278 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 8279 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 8280 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s16, |
| 8281 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 8282 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s32, |
| 8283 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s32, |
| 8284 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s32, |
| 8285 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 8286 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8287 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8288 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8289 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8290 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8291 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8292 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8293 | GIR_CopySubReg, /*NewInsnID*/11, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 8294 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8295 | GIR_ConstrainOperandRC, /*InsnID*/11, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8296 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8297 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8298 | GIR_CopySubReg, /*NewInsnID*/10, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 8299 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8300 | GIR_ConstrainOperandRC, /*InsnID*/10, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8301 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8302 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8303 | GIR_CopySubReg, /*NewInsnID*/9, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 8304 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8305 | GIR_ConstrainOperandRC, /*InsnID*/9, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8306 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8307 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8308 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/8, |
| 8309 | GIR_AddSimpleTempRegister, /*InsnID*/8, /*TempRegID*/9, |
| 8310 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 8311 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8312 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8313 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 8314 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/10, |
| 8315 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/11, |
| 8316 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 8317 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8318 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8319 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8320 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8321 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8322 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8323 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8324 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 8325 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8326 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8327 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8328 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8329 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 8330 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8331 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8332 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8333 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8334 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 8335 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8336 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8337 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8338 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8339 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 8340 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 8341 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8344 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 8345 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 8346 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 8347 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 8349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 8350 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8351 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 8352 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/6, |
| 8353 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 8354 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 8355 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8356 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8357 | // GIR_Coverage, 10850, |
| 8358 | GIR_EraseRootFromParent_Done, |
| 8359 | // Label 377: @33747 |
| 8360 | GIM_Try, /*On fail goto*//*Label 378*/ GIMT_Encode4(33798), // Rule ID 8045 // |
| 8361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8362 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8363 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8364 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8365 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8366 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8367 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8368 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8369 | // (or:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }), i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 8370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8372 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 8373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8374 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8375 | GIR_RootConstrainSelectedInstOperands, |
| 8376 | // GIR_Coverage, 8045, |
| 8377 | GIR_EraseRootFromParent_Done, |
| 8378 | // Label 378: @33798 |
| 8379 | GIM_Try, /*On fail goto*//*Label 379*/ GIMT_Encode4(33849), // Rule ID 69 // |
| 8380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8381 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8382 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8383 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 8384 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 8385 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 8386 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8387 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8388 | // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, (xor:{ *:[i64] } i64:{ *:[i64] }:$src1, -1:{ *:[i64] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 8389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8391 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 8392 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8393 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8394 | GIR_RootConstrainSelectedInstOperands, |
| 8395 | // GIR_Coverage, 69, |
| 8396 | GIR_EraseRootFromParent_Done, |
| 8397 | // Label 379: @33849 |
| 8398 | GIM_Try, /*On fail goto*//*Label 380*/ GIMT_Encode4(33875), // Rule ID 57 // |
| 8399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8400 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8401 | // (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18507>> => (S_OR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 8402 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B64), |
| 8403 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 8404 | GIR_RootConstrainSelectedInstOperands, |
| 8405 | // GIR_Coverage, 57, |
| 8406 | GIR_Done, |
| 8407 | // Label 380: @33875 |
| 8408 | GIM_Reject, |
| 8409 | // Label 353: @33876 |
| 8410 | GIM_Reject, |
| 8411 | // Label 304: @33877 |
| 8412 | GIM_Try, /*On fail goto*//*Label 381*/ GIMT_Encode4(34027), |
| 8413 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 8414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 8415 | GIM_Try, /*On fail goto*//*Label 382*/ GIMT_Encode4(33947), // Rule ID 8120 // |
| 8416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8417 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8418 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8419 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 8420 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 8421 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8422 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8423 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8424 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8425 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8426 | // (or:{ *:[v2i16] } (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }), v2i16:{ *:[v2i16] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1) |
| 8427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 8428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8429 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 8430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8431 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8432 | GIR_RootConstrainSelectedInstOperands, |
| 8433 | // GIR_Coverage, 8120, |
| 8434 | GIR_EraseRootFromParent_Done, |
| 8435 | // Label 382: @33947 |
| 8436 | GIM_Try, /*On fail goto*//*Label 383*/ GIMT_Encode4(34006), // Rule ID 1662 // |
| 8437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8438 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8439 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8440 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 8441 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 8442 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8443 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8444 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8445 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8446 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8447 | // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, immAllOnesV:{ *:[v2i16] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B32:{ *:[v2i16] }:{ *:[i1] } SSrc_b32:{ *:[v2i16] }:$src0, SSrc_b32:{ *:[v2i16] }:$src1) |
| 8448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B32), |
| 8449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8450 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 8451 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8452 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8453 | GIR_RootConstrainSelectedInstOperands, |
| 8454 | // GIR_Coverage, 1662, |
| 8455 | GIR_EraseRootFromParent_Done, |
| 8456 | // Label 383: @34006 |
| 8457 | GIM_Try, /*On fail goto*//*Label 384*/ GIMT_Encode4(34026), // Rule ID 2164 // |
| 8458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8459 | // (or:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1) => (V_OR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1) |
| 8460 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 8461 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 8462 | GIR_RootConstrainSelectedInstOperands, |
| 8463 | // GIR_Coverage, 2164, |
| 8464 | GIR_Done, |
| 8465 | // Label 384: @34026 |
| 8466 | GIM_Reject, |
| 8467 | // Label 381: @34027 |
| 8468 | GIM_Reject, |
| 8469 | // Label 305: @34028 |
| 8470 | GIM_Try, /*On fail goto*//*Label 385*/ GIMT_Encode4(34150), |
| 8471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8473 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8475 | GIM_Try, /*On fail goto*//*Label 386*/ GIMT_Encode4(34098), // Rule ID 8122 // |
| 8476 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8477 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8478 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8479 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8481 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8482 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8483 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8484 | // (or:{ *:[v2i32] } (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }), v2i32:{ *:[v2i32] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1) |
| 8485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8487 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 8488 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8489 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8490 | GIR_RootConstrainSelectedInstOperands, |
| 8491 | // GIR_Coverage, 8122, |
| 8492 | GIR_EraseRootFromParent_Done, |
| 8493 | // Label 386: @34098 |
| 8494 | GIM_Try, /*On fail goto*//*Label 387*/ GIMT_Encode4(34149), // Rule ID 1664 // |
| 8495 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8496 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8497 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s32, |
| 8498 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s32, |
| 8499 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8500 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8501 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8502 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8503 | // (or:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src0, (xor:{ *:[v2i32] } v2i32:{ *:[v2i32] }:$src1, immAllOnesV:{ *:[v2i32] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[v2i32] }:{ *:[i1] } SSrc_b64:{ *:[v2i32] }:$src0, SSrc_b64:{ *:[v2i32] }:$src1) |
| 8504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8506 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 8507 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8508 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8509 | GIR_RootConstrainSelectedInstOperands, |
| 8510 | // GIR_Coverage, 1664, |
| 8511 | GIR_EraseRootFromParent_Done, |
| 8512 | // Label 387: @34149 |
| 8513 | GIM_Reject, |
| 8514 | // Label 385: @34150 |
| 8515 | GIM_Reject, |
| 8516 | // Label 306: @34151 |
| 8517 | GIM_Try, /*On fail goto*//*Label 388*/ GIMT_Encode4(34273), |
| 8518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8519 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18507), |
| 8521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8522 | GIM_Try, /*On fail goto*//*Label 389*/ GIMT_Encode4(34221), // Rule ID 8121 // |
| 8523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8524 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8525 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8526 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8527 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8528 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8529 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8530 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8531 | // (or:{ *:[v4i16] } (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }), v4i16:{ *:[v4i16] }:$src0)<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1) |
| 8532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8534 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 8535 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8536 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8537 | GIR_RootConstrainSelectedInstOperands, |
| 8538 | // GIR_Coverage, 8121, |
| 8539 | GIR_EraseRootFromParent_Done, |
| 8540 | // Label 389: @34221 |
| 8541 | GIM_Try, /*On fail goto*//*Label 390*/ GIMT_Encode4(34272), // Rule ID 1663 // |
| 8542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8543 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8544 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v4s16, |
| 8545 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v4s16, |
| 8546 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8547 | GIM_CheckOpcodeIsEither, /*MI*/2, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR_TRUNC), |
| 8548 | GIM_CheckIsBuildVectorAllOnes, /*MI*/2, |
| 8549 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8550 | // (or:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src0, (xor:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src1, immAllOnesV:{ *:[v4i16] }))<<P:Predicate_anonymous_18507>> => (S_ORN2_B64:{ *:[v4i16] }:{ *:[i1] } SSrc_b64:{ *:[v4i16] }:$src0, SSrc_b64:{ *:[v4i16] }:$src1) |
| 8551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ORN2_B64), |
| 8552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8553 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 8554 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 8555 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8556 | GIR_RootConstrainSelectedInstOperands, |
| 8557 | // GIR_Coverage, 1663, |
| 8558 | GIR_EraseRootFromParent_Done, |
| 8559 | // Label 390: @34272 |
| 8560 | GIM_Reject, |
| 8561 | // Label 388: @34273 |
| 8562 | GIM_Reject, |
| 8563 | // Label 307: @34274 |
| 8564 | GIM_Reject, |
| 8565 | // Label 5: @34275 |
| 8566 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(12), /*)*//*default:*//*Label 396*/ GIMT_Encode4(38638), |
| 8567 | /*GILLT_s1*//*Label 391*/ GIMT_Encode4(34306), |
| 8568 | /*GILLT_s16*//*Label 392*/ GIMT_Encode4(34369), |
| 8569 | /*GILLT_s32*//*Label 393*/ GIMT_Encode4(34421), |
| 8570 | /*GILLT_s64*//*Label 394*/ GIMT_Encode4(35978), |
| 8571 | /*GILLT_v2s16*//*Label 395*/ GIMT_Encode4(38611), |
| 8572 | // Label 391: @34306 |
| 8573 | GIM_Try, /*On fail goto*//*Label 397*/ GIMT_Encode4(34368), |
| 8574 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 8575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 8576 | GIM_Try, /*On fail goto*//*Label 398*/ GIMT_Encode4(34342), // Rule ID 7165 // |
| 8577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 8578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 8579 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 8580 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64), |
| 8581 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 8582 | GIR_RootConstrainSelectedInstOperands, |
| 8583 | // GIR_Coverage, 7165, |
| 8584 | GIR_Done, |
| 8585 | // Label 398: @34342 |
| 8586 | GIM_Try, /*On fail goto*//*Label 399*/ GIMT_Encode4(34367), // Rule ID 7172 // |
| 8587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 8588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8589 | // (xor:{ *:[i1] } i1:{ *:[i1] }:$src0, i1:{ *:[i1] }:$src1) => (S_XOR_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i1] }:$src0, ?:{ *:[i1] }:$src1) |
| 8590 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 8591 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 8592 | GIR_RootConstrainSelectedInstOperands, |
| 8593 | // GIR_Coverage, 7172, |
| 8594 | GIR_Done, |
| 8595 | // Label 399: @34367 |
| 8596 | GIM_Reject, |
| 8597 | // Label 397: @34368 |
| 8598 | GIM_Reject, |
| 8599 | // Label 392: @34369 |
| 8600 | GIM_Try, /*On fail goto*//*Label 400*/ GIMT_Encode4(34420), |
| 8601 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 8602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 8603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8604 | GIM_Try, /*On fail goto*//*Label 401*/ GIMT_Encode4(34400), // Rule ID 2162 // |
| 8605 | // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_XOR_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i16] }:$src0, VSrc_b32:{ *:[i16] }:$src1) |
| 8606 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 8607 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 8608 | GIR_RootConstrainSelectedInstOperands, |
| 8609 | // GIR_Coverage, 2162, |
| 8610 | GIR_Done, |
| 8611 | // Label 401: @34400 |
| 8612 | GIM_Try, /*On fail goto*//*Label 402*/ GIMT_Encode4(34419), // Rule ID 831 // |
| 8613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 8614 | // (xor:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_XOR_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 8615 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B16_t16_e64), |
| 8616 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 8617 | GIR_RootConstrainSelectedInstOperands, |
| 8618 | // GIR_Coverage, 831, |
| 8619 | GIR_Done, |
| 8620 | // Label 402: @34419 |
| 8621 | GIM_Reject, |
| 8622 | // Label 400: @34420 |
| 8623 | GIM_Reject, |
| 8624 | // Label 393: @34421 |
| 8625 | GIM_Try, /*On fail goto*//*Label 403*/ GIMT_Encode4(35977), |
| 8626 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 8627 | GIM_Try, /*On fail goto*//*Label 404*/ GIMT_Encode4(34487), // Rule ID 62 // |
| 8628 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8630 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8631 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8632 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8633 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8634 | GIM_CheckHasOneUse, /*MI*/1, |
| 8635 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 8637 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8638 | // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_18476>> => (S_NAND_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 8639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B32), |
| 8640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 8642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 8643 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8644 | GIR_RootConstrainSelectedInstOperands, |
| 8645 | // GIR_Coverage, 62, |
| 8646 | GIR_EraseRootFromParent_Done, |
| 8647 | // Label 404: @34487 |
| 8648 | GIM_Try, /*On fail goto*//*Label 405*/ GIMT_Encode4(34545), // Rule ID 64 // |
| 8649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8651 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8652 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 8653 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8654 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8655 | GIM_CheckHasOneUse, /*MI*/1, |
| 8656 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8657 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 8658 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8659 | // (xor:{ *:[i32] } (or:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_18476>> => (S_NOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 8660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B32), |
| 8661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 8663 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 8664 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8665 | GIR_RootConstrainSelectedInstOperands, |
| 8666 | // GIR_Coverage, 64, |
| 8667 | GIR_EraseRootFromParent_Done, |
| 8668 | // Label 405: @34545 |
| 8669 | GIM_Try, /*On fail goto*//*Label 406*/ GIMT_Encode4(34603), // Rule ID 60 // |
| 8670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 8672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8676 | GIM_CheckHasOneUse, /*MI*/1, |
| 8677 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 8678 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 8679 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 8680 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i32] })<<P:Predicate_anonymous_18476>> => (S_XNOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 8681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B32), |
| 8682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 8683 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 8684 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 8685 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 8686 | GIR_RootConstrainSelectedInstOperands, |
| 8687 | // GIR_Coverage, 60, |
| 8688 | GIR_EraseRootFromParent_Done, |
| 8689 | // Label 406: @34603 |
| 8690 | GIM_Try, /*On fail goto*//*Label 407*/ GIMT_Encode4(34725), // Rule ID 10811 // |
| 8691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8692 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8693 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8694 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8695 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8696 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8697 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8699 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8700 | // MIs[0] z |
| 8701 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 8702 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8703 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8704 | // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8705 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8706 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8707 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8708 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8709 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8710 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 8711 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8712 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8713 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8714 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 8715 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8716 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8717 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8718 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 8719 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8722 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8725 | GIR_RootConstrainSelectedInstOperands, |
| 8726 | // GIR_Coverage, 10811, |
| 8727 | GIR_EraseRootFromParent_Done, |
| 8728 | // Label 407: @34725 |
| 8729 | GIM_Try, /*On fail goto*//*Label 408*/ GIMT_Encode4(34847), // Rule ID 10812 // |
| 8730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8731 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8735 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8736 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8739 | // MIs[0] z |
| 8740 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 8741 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8742 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8743 | // (xor:{ *:[i32] } (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8745 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8746 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8747 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8748 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8749 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 8750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8751 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8752 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8753 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 8754 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8755 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8756 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8757 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 8758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8762 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8763 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8764 | GIR_RootConstrainSelectedInstOperands, |
| 8765 | // GIR_Coverage, 10812, |
| 8766 | GIR_EraseRootFromParent_Done, |
| 8767 | // Label 408: @34847 |
| 8768 | GIM_Try, /*On fail goto*//*Label 409*/ GIMT_Encode4(34969), // Rule ID 10809 // |
| 8769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8770 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8771 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8772 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8773 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8774 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8775 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8776 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8777 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8778 | // MIs[0] z |
| 8779 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 8780 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8781 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8782 | // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8783 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8784 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8785 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8786 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8787 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8788 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, // z |
| 8789 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8790 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8791 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8792 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 8793 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8794 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8795 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8796 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 8797 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8800 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8801 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8802 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8803 | GIR_RootConstrainSelectedInstOperands, |
| 8804 | // GIR_Coverage, 10809, |
| 8805 | GIR_EraseRootFromParent_Done, |
| 8806 | // Label 409: @34969 |
| 8807 | GIM_Try, /*On fail goto*//*Label 410*/ GIMT_Encode4(35091), // Rule ID 10810 // |
| 8808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8809 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 8810 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8812 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8813 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8814 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8815 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8816 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8817 | // MIs[0] z |
| 8818 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 8819 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8820 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8821 | // (xor:{ *:[i32] } (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)), i32:{ *:[i32] }:$z)<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8822 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8823 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8824 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8825 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8826 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8827 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, // z |
| 8828 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8829 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8830 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8831 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 8832 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8833 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8834 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8835 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 8836 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8839 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8840 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8841 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8842 | GIR_RootConstrainSelectedInstOperands, |
| 8843 | // GIR_Coverage, 10810, |
| 8844 | GIR_EraseRootFromParent_Done, |
| 8845 | // Label 410: @35091 |
| 8846 | GIM_Try, /*On fail goto*//*Label 411*/ GIMT_Encode4(35212), // Rule ID 10808 // |
| 8847 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8849 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8850 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8851 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8852 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8853 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8854 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8855 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8856 | // MIs[2] z |
| 8857 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 8858 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8859 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8860 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8861 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8862 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8863 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8864 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8865 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8866 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z |
| 8867 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8868 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8869 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8870 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 8871 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8873 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8874 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 8875 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8878 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8879 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8881 | GIR_RootConstrainSelectedInstOperands, |
| 8882 | // GIR_Coverage, 10808, |
| 8883 | GIR_EraseRootFromParent_Done, |
| 8884 | // Label 411: @35212 |
| 8885 | GIM_Try, /*On fail goto*//*Label 412*/ GIMT_Encode4(35333), // Rule ID 10807 // |
| 8886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8888 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8889 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8892 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 8893 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8894 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8895 | // MIs[2] z |
| 8896 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 8897 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8898 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8899 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z), i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8901 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8902 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8903 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8904 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8905 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z |
| 8906 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8907 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8908 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8909 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 8910 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8911 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8912 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8913 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 8914 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8917 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8919 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8920 | GIR_RootConstrainSelectedInstOperands, |
| 8921 | // GIR_Coverage, 10807, |
| 8922 | GIR_EraseRootFromParent_Done, |
| 8923 | // Label 412: @35333 |
| 8924 | GIM_Try, /*On fail goto*//*Label 413*/ GIMT_Encode4(35454), // Rule ID 10806 // |
| 8925 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8927 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8928 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8929 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8930 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8931 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8932 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8933 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 8934 | // MIs[2] z |
| 8935 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 8936 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8937 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8938 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$z, i32:{ *:[i32] }:$y)))<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8939 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8940 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8941 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8942 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8943 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8944 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z |
| 8945 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8946 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8947 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8948 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/2, // y |
| 8949 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8950 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8951 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8952 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 8953 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8956 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8959 | GIR_RootConstrainSelectedInstOperands, |
| 8960 | // GIR_Coverage, 10806, |
| 8961 | GIR_EraseRootFromParent_Done, |
| 8962 | // Label 413: @35454 |
| 8963 | GIM_Try, /*On fail goto*//*Label 414*/ GIMT_Encode4(35575), // Rule ID 7085 // |
| 8964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 8965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 8966 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 8967 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 8968 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 8969 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 8970 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 8971 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 8972 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 8973 | // MIs[2] z |
| 8974 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 8975 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 8976 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 8977 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$z, (and:{ *:[i32] } i32:{ *:[i32] }:$x, (xor:{ *:[i32] } i32:{ *:[i32] }:$y, i32:{ *:[i32] }:$z)))<<P:Predicate_anonymous_23253>> => (V_BFI_B32_e64:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$x, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$y, VGPR_32:{ *:[i32] }), (COPY_TO_REGCLASS:{ *:[i16] } VSrc_b32:{ *:[i32] }:$z, VGPR_32:{ *:[i32] })) |
| 8978 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 8979 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 8980 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 8981 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8982 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8983 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // z |
| 8984 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 8985 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8986 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8987 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/2, /*OpIdx*/1, // y |
| 8988 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 8989 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 8990 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 8991 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, // x |
| 8992 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 8993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 8994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 8995 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 8996 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 8997 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 8998 | GIR_RootConstrainSelectedInstOperands, |
| 8999 | // GIR_Coverage, 7085, |
| 9000 | GIR_EraseRootFromParent_Done, |
| 9001 | // Label 414: @35575 |
| 9002 | GIM_Try, /*On fail goto*//*Label 415*/ GIMT_Encode4(35607), // Rule ID 0 // |
| 9003 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 9005 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9006 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 9007 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_18476>> => (S_NOT_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0) |
| 9008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B32), |
| 9009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9010 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 9011 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 9012 | GIR_RootConstrainSelectedInstOperands, |
| 9013 | // GIR_Coverage, 0, |
| 9014 | GIR_EraseRootFromParent_Done, |
| 9015 | // Label 415: @35607 |
| 9016 | GIM_Try, /*On fail goto*//*Label 416*/ GIMT_Encode4(35636), // Rule ID 7177 // |
| 9017 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9019 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9020 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9021 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })<<P:Predicate_anonymous_23253>> => (V_NOT_B32_e32:{ *:[i32] } ?:{ *:[i32] }:$src0) |
| 9022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_NOT_B32_e32), |
| 9023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9024 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 9025 | GIR_RootConstrainSelectedInstOperands, |
| 9026 | // GIR_Coverage, 7177, |
| 9027 | GIR_EraseRootFromParent_Done, |
| 9028 | // Label 416: @35636 |
| 9029 | GIM_Try, /*On fail goto*//*Label 417*/ GIMT_Encode4(35704), // Rule ID 2248 // |
| 9030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 9031 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9037 | GIM_CheckHasOneUse, /*MI*/1, |
| 9038 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x |
| 9039 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y |
| 9040 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:16:z |
| 9041 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24088), |
| 9042 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9043 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_24042>>, i32:{ *:[i32] }:$src2:$pred:16:z)<<P:16:Predicate_anonymous_24088>> => (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 9044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64), |
| 9045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9047 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9048 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 9049 | GIR_RootConstrainSelectedInstOperands, |
| 9050 | // GIR_Coverage, 2248, |
| 9051 | GIR_EraseRootFromParent_Done, |
| 9052 | // Label 417: @35704 |
| 9053 | GIM_Try, /*On fail goto*//*Label 418*/ GIMT_Encode4(35772), // Rule ID 8146 // |
| 9054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 9055 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9057 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/1, /*StoreIdx*/2, // Name : pred:16:z |
| 9058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9061 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9062 | GIM_CheckHasOneUse, /*MI*/1, |
| 9063 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:16:x |
| 9064 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:16:y |
| 9065 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24088), |
| 9066 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9067 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:16:z, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:16:x, i32:{ *:[i32] }:$src1:$pred:16:y)<<P:Predicate_anonymous_24042>>)<<P:16:Predicate_anonymous_24088>> => (V_XOR3_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 9068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR3_B32_e64), |
| 9069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9071 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9072 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 9073 | GIR_RootConstrainSelectedInstOperands, |
| 9074 | // GIR_Coverage, 8146, |
| 9075 | GIR_EraseRootFromParent_Done, |
| 9076 | // Label 418: @35772 |
| 9077 | GIM_Try, /*On fail goto*//*Label 419*/ GIMT_Encode4(35801), // Rule ID 58 // |
| 9078 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 9080 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18508), |
| 9081 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18508>> => (S_XOR_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 9082 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 9083 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 9084 | GIR_RootConstrainSelectedInstOperands, |
| 9085 | // GIR_Coverage, 58, |
| 9086 | GIR_Done, |
| 9087 | // Label 419: @35801 |
| 9088 | GIM_Try, /*On fail goto*//*Label 420*/ GIMT_Encode4(35851), // Rule ID 8078 // |
| 9089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts), |
| 9090 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9092 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9093 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9094 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9095 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9096 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 9097 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9098 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] }), i32:{ *:[i32] }:$src1) => (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 9099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64), |
| 9100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9101 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9102 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 9103 | GIR_RootConstrainSelectedInstOperands, |
| 9104 | // GIR_Coverage, 8078, |
| 9105 | GIR_EraseRootFromParent_Done, |
| 9106 | // Label 420: @35851 |
| 9107 | GIM_Try, /*On fail goto*//*Label 421*/ GIMT_Encode4(35903), // Rule ID 834 // |
| 9108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts), |
| 9109 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9112 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9114 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9115 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9116 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9117 | // (xor:{ *:[i32] } (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), -1:{ *:[i32] }) => (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 9118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64), |
| 9119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9120 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9121 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9122 | GIR_RootConstrainSelectedInstOperands, |
| 9123 | // GIR_Coverage, 834, |
| 9124 | GIR_EraseRootFromParent_Done, |
| 9125 | // Label 421: @35903 |
| 9126 | GIM_Try, /*On fail goto*//*Label 422*/ GIMT_Encode4(35953), // Rule ID 8079 // |
| 9127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts), |
| 9128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9131 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9133 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 9134 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 9135 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9136 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src1, (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, -1:{ *:[i32] })) => (V_XNOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 9137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XNOR_B32_e64), |
| 9138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9139 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9140 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 9141 | GIR_RootConstrainSelectedInstOperands, |
| 9142 | // GIR_Coverage, 8079, |
| 9143 | GIR_EraseRootFromParent_Done, |
| 9144 | // Label 422: @35953 |
| 9145 | GIM_Try, /*On fail goto*//*Label 423*/ GIMT_Encode4(35976), // Rule ID 753 // |
| 9146 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 9147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9148 | // (xor:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_XOR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 9149 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 9150 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 9151 | GIR_RootConstrainSelectedInstOperands, |
| 9152 | // GIR_Coverage, 753, |
| 9153 | GIR_Done, |
| 9154 | // Label 423: @35976 |
| 9155 | GIM_Reject, |
| 9156 | // Label 403: @35977 |
| 9157 | GIM_Reject, |
| 9158 | // Label 394: @35978 |
| 9159 | GIM_Try, /*On fail goto*//*Label 424*/ GIMT_Encode4(38610), |
| 9160 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 9161 | GIM_Try, /*On fail goto*//*Label 425*/ GIMT_Encode4(36044), // Rule ID 63 // |
| 9162 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 9164 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9165 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9166 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9167 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9168 | GIM_CheckHasOneUse, /*MI*/1, |
| 9169 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9170 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 9171 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9172 | // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_and_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_18476>> => (S_NAND_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 9173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NAND_B64), |
| 9174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9177 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 9178 | GIR_RootConstrainSelectedInstOperands, |
| 9179 | // GIR_Coverage, 63, |
| 9180 | GIR_EraseRootFromParent_Done, |
| 9181 | // Label 425: @36044 |
| 9182 | GIM_Try, /*On fail goto*//*Label 426*/ GIMT_Encode4(36102), // Rule ID 65 // |
| 9183 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 9185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9186 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_OR), |
| 9187 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9188 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9189 | GIM_CheckHasOneUse, /*MI*/1, |
| 9190 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9191 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 9192 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9193 | // (xor:{ *:[i64] } (or:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_or_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_18476>> => (S_NOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 9194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOR_B64), |
| 9195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9196 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9197 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9198 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 9199 | GIR_RootConstrainSelectedInstOperands, |
| 9200 | // GIR_Coverage, 65, |
| 9201 | GIR_EraseRootFromParent_Done, |
| 9202 | // Label 426: @36102 |
| 9203 | GIM_Try, /*On fail goto*//*Label 427*/ GIMT_Encode4(36160), // Rule ID 61 // |
| 9204 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 9206 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9207 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9208 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9209 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9210 | GIM_CheckHasOneUse, /*MI*/1, |
| 9211 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9212 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 9213 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 9214 | // (xor:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_xor_oneuse>>, -1:{ *:[i64] })<<P:Predicate_anonymous_18476>> => (S_XNOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 9215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XNOR_B64), |
| 9216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9217 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 9218 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 9219 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 9220 | GIR_RootConstrainSelectedInstOperands, |
| 9221 | // GIR_Coverage, 61, |
| 9222 | GIR_EraseRootFromParent_Done, |
| 9223 | // Label 427: @36160 |
| 9224 | GIM_Try, /*On fail goto*//*Label 428*/ GIMT_Encode4(36459), // Rule ID 10818 // |
| 9225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9226 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9228 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9229 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9230 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9231 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9232 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9233 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9234 | // MIs[0] z |
| 9235 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9236 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9237 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9238 | // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9239 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9240 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9241 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9242 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9243 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9244 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9245 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9246 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9247 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9248 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9249 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9250 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9251 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9252 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9253 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9254 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9255 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9256 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9257 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9258 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9259 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9260 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9261 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9262 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9263 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9264 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9265 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9266 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9267 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9268 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9269 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9270 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9271 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9272 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9273 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9274 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9275 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9276 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9277 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9278 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9279 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9280 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9281 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9282 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9283 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9284 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9285 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9286 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9287 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9288 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9291 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9292 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9293 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9294 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9295 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9296 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9297 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9298 | // GIR_Coverage, 10818, |
| 9299 | GIR_EraseRootFromParent_Done, |
| 9300 | // Label 428: @36459 |
| 9301 | GIM_Try, /*On fail goto*//*Label 429*/ GIMT_Encode4(36758), // Rule ID 10819 // |
| 9302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9303 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9304 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9305 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9306 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9307 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9308 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9309 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9310 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9311 | // MIs[0] z |
| 9312 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9314 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9315 | // (xor:{ *:[i64] } (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9316 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9317 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9318 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9319 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9320 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9321 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9322 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9323 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9324 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9325 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9326 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9327 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9328 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9329 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9330 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9331 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9332 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9333 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9334 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9335 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9336 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9337 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9338 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9339 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9340 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9341 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9342 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9343 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9344 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9345 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9346 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9347 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9348 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9349 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9350 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9351 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9352 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9353 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9354 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9355 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9356 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9357 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9358 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9359 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9362 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9363 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9364 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9365 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9368 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9369 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9371 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9372 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9373 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9374 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9375 | // GIR_Coverage, 10819, |
| 9376 | GIR_EraseRootFromParent_Done, |
| 9377 | // Label 429: @36758 |
| 9378 | GIM_Try, /*On fail goto*//*Label 430*/ GIMT_Encode4(37057), // Rule ID 10816 // |
| 9379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9380 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9381 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9382 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9383 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9384 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9385 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9386 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9387 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9388 | // MIs[0] z |
| 9389 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 9390 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9391 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9392 | // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9393 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9394 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9395 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9396 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9397 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9398 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9399 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9400 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9401 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9402 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9403 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9404 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9405 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9406 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9407 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9408 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9409 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9410 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9411 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9412 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9413 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9414 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9415 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9416 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9417 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9418 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9419 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9420 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9421 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9422 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9423 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9424 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9425 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9426 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9427 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9428 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9429 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9430 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9431 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9432 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9433 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9434 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9435 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9436 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9437 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9438 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9439 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9440 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9441 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9442 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9446 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9447 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9448 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9449 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9450 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9451 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9452 | // GIR_Coverage, 10816, |
| 9453 | GIR_EraseRootFromParent_Done, |
| 9454 | // Label 430: @37057 |
| 9455 | GIM_Try, /*On fail goto*//*Label 431*/ GIMT_Encode4(37356), // Rule ID 10817 // |
| 9456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9457 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 9458 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9459 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9460 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9461 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9462 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9463 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9464 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9465 | // MIs[0] z |
| 9466 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/0, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 9467 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9468 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9469 | // (xor:{ *:[i64] } (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)), i64:{ *:[i64] }:$z)<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9470 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9471 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9472 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9473 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9474 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9475 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9476 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9477 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9478 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9479 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9480 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9481 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9482 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9483 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9484 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9485 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9486 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9487 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9488 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9489 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9490 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9491 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9492 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9493 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9494 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9495 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9496 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9497 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9499 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9500 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9501 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9502 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9503 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9504 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9505 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9506 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9507 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9508 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9509 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9510 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9511 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9512 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9513 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9514 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9515 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9516 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9517 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9518 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9522 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9523 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9524 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9525 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9526 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9527 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9528 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9529 | // GIR_Coverage, 10817, |
| 9530 | GIR_EraseRootFromParent_Done, |
| 9531 | // Label 431: @37356 |
| 9532 | GIM_Try, /*On fail goto*//*Label 432*/ GIMT_Encode4(37654), // Rule ID 10815 // |
| 9533 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9535 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9537 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9538 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9539 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9540 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9541 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9542 | // MIs[2] z |
| 9543 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 9544 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9545 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9546 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9547 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9548 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9549 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9550 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9551 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9552 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9553 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9554 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9555 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9556 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9557 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9558 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9559 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9560 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9561 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9562 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9563 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9564 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9565 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9566 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9567 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9568 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9569 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9570 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9571 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9572 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9573 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9574 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9576 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9577 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9578 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9579 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9580 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9581 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9582 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9583 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9584 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9585 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9586 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9587 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9588 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9589 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9590 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9593 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9594 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9595 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9599 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9600 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9601 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9602 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9603 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9604 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9605 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9606 | // GIR_Coverage, 10815, |
| 9607 | GIR_EraseRootFromParent_Done, |
| 9608 | // Label 432: @37654 |
| 9609 | GIM_Try, /*On fail goto*//*Label 433*/ GIMT_Encode4(37952), // Rule ID 10814 // |
| 9610 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9612 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9613 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9614 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9615 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9616 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9617 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9618 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9619 | // MIs[2] z |
| 9620 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 9621 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9622 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9623 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z), i64:{ *:[i64] }:$x))<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9624 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9625 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9626 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9627 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9628 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9629 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9630 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9631 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9632 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9633 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9634 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9635 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9636 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9637 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9638 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9639 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9640 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9641 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9642 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9643 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9644 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9645 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9646 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9647 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9648 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9649 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9650 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9651 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9652 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9653 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9654 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9655 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9656 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9657 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9658 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9659 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9660 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9661 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9662 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9663 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9664 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9665 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9666 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9667 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9668 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9669 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9670 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9671 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9672 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9673 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9675 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9676 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9677 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9679 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9680 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9681 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9682 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9683 | // GIR_Coverage, 10814, |
| 9684 | GIR_EraseRootFromParent_Done, |
| 9685 | // Label 433: @37952 |
| 9686 | GIM_Try, /*On fail goto*//*Label 434*/ GIMT_Encode4(38250), // Rule ID 10813 // |
| 9687 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9689 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9690 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9691 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9692 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9693 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9694 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9695 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s64, |
| 9696 | // MIs[2] z |
| 9697 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/1, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 9698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9699 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9700 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$z, i64:{ *:[i64] }:$y)))<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9702 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9703 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9704 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9705 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9706 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9707 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9708 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9709 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9710 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9711 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9712 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9713 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9714 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9715 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9716 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9717 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9718 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9719 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9720 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9721 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9722 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9723 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9724 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9725 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9726 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9727 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9728 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9730 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9731 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9732 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9733 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9734 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9735 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9736 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9737 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9738 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9739 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9740 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9741 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9742 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9743 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9744 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9747 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9748 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9749 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9750 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9753 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9754 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9755 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9756 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9757 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9758 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9759 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9760 | // GIR_Coverage, 10813, |
| 9761 | GIR_EraseRootFromParent_Done, |
| 9762 | // Label 434: @38250 |
| 9763 | GIM_Try, /*On fail goto*//*Label 435*/ GIMT_Encode4(38548), // Rule ID 7086 // |
| 9764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9766 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9767 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 9768 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 9769 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s64, |
| 9770 | GIM_RecordInsnIgnoreCopies, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 9771 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_XOR), |
| 9772 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 9773 | // MIs[2] z |
| 9774 | GIM_CheckIsSameOperandIgnoreCopies, /*MI*/2, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 9775 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23253), |
| 9776 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 9777 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$z, (and:{ *:[i64] } i64:{ *:[i64] }:$x, (xor:{ *:[i64] } i64:{ *:[i64] }:$y, i64:{ *:[i64] }:$z)))<<P:Predicate_anonymous_23253>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub0:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$x, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$y, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$z, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 9778 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 9779 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 9780 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 9781 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 9782 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 9783 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s32, |
| 9784 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 9785 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 9786 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9787 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9788 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // z |
| 9789 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9790 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9791 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9792 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9793 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // y |
| 9794 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9795 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9796 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9797 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9798 | GIR_CopySubReg, /*NewInsnID*/6, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // x |
| 9799 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9800 | GIR_ConstrainOperandRC, /*InsnID*/6, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9801 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9802 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9803 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 9804 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 9805 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/7, |
| 9806 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 9807 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9808 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9809 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // z |
| 9810 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9811 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9812 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9813 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9814 | GIR_CopySubReg, /*NewInsnID*/3, /*OldInsnID*/2, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // y |
| 9815 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9816 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9817 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 9818 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9819 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // x |
| 9820 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9821 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 9823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 9824 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 9825 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 9826 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/3, |
| 9827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 9828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 9829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 9830 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 9831 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 9832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/4, |
| 9833 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 9834 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 9835 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9836 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9837 | // GIR_Coverage, 7086, |
| 9838 | GIR_EraseRootFromParent_Done, |
| 9839 | // Label 435: @38548 |
| 9840 | GIM_Try, /*On fail goto*//*Label 436*/ GIMT_Encode4(38580), // Rule ID 1 // |
| 9841 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 9843 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, uint8_t(-1), |
| 9844 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18476), |
| 9845 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, -1:{ *:[i64] })<<P:Predicate_anonymous_18476>> => (S_NOT_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0) |
| 9846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOT_B64), |
| 9847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9848 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 9849 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 9850 | GIR_RootConstrainSelectedInstOperands, |
| 9851 | // GIR_Coverage, 1, |
| 9852 | GIR_EraseRootFromParent_Done, |
| 9853 | // Label 436: @38580 |
| 9854 | GIM_Try, /*On fail goto*//*Label 437*/ GIMT_Encode4(38609), // Rule ID 59 // |
| 9855 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 9856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 9857 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18508), |
| 9858 | // (xor:{ *:[i64] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1)<<P:Predicate_anonymous_18508>> => (S_XOR_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 9859 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B64), |
| 9860 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 9861 | GIR_RootConstrainSelectedInstOperands, |
| 9862 | // GIR_Coverage, 59, |
| 9863 | GIR_Done, |
| 9864 | // Label 437: @38609 |
| 9865 | GIM_Reject, |
| 9866 | // Label 424: @38610 |
| 9867 | GIM_Reject, |
| 9868 | // Label 395: @38611 |
| 9869 | GIM_Try, /*On fail goto*//*Label 438*/ GIMT_Encode4(38637), // Rule ID 2165 // |
| 9870 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 9871 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 9872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9873 | // (xor:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1) => (V_XOR_B32_e64:{ *:[v2i16] } VSrc_b32:{ *:[v2i16] }:$src0, VSrc_b32:{ *:[v2i16] }:$src1) |
| 9874 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 9875 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 9876 | GIR_RootConstrainSelectedInstOperands, |
| 9877 | // GIR_Coverage, 2165, |
| 9878 | GIR_Done, |
| 9879 | // Label 438: @38637 |
| 9880 | GIM_Reject, |
| 9881 | // Label 396: @38638 |
| 9882 | GIM_Reject, |
| 9883 | // Label 6: @38639 |
| 9884 | GIM_Try, /*On fail goto*//*Label 439*/ GIMT_Encode4(38690), |
| 9885 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 9886 | GIM_Try, /*On fail goto*//*Label 440*/ GIMT_Encode4(38668), // Rule ID 7067 // |
| 9887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9888 | // MIs[0] fi |
| 9889 | // No operand predicates |
| 9890 | // (frameindex:{ *:[i32] }):$fi => (V_MOV_B32_e32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi)) |
| 9891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 9892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9893 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi |
| 9894 | GIR_RootConstrainSelectedInstOperands, |
| 9895 | // GIR_Coverage, 7067, |
| 9896 | GIR_EraseRootFromParent_Done, |
| 9897 | // Label 440: @38668 |
| 9898 | GIM_Try, /*On fail goto*//*Label 441*/ GIMT_Encode4(38689), // Rule ID 7068 // |
| 9899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 9900 | // MIs[0] fi |
| 9901 | // No operand predicates |
| 9902 | // (frameindex:{ *:[i32] }):$fi => (S_MOV_B32:{ *:[i32] } (frameindex_to_targetframeindex:{ *:[i32] } ?:{ *:[i32] }:$fi)) |
| 9903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 9904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 9905 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderFrameIndex), // fi |
| 9906 | GIR_RootConstrainSelectedInstOperands, |
| 9907 | // GIR_Coverage, 7068, |
| 9908 | GIR_EraseRootFromParent_Done, |
| 9909 | // Label 441: @38689 |
| 9910 | GIM_Reject, |
| 9911 | // Label 439: @38690 |
| 9912 | GIM_Reject, |
| 9913 | // Label 7: @38691 |
| 9914 | GIM_Try, /*On fail goto*//*Label 442*/ GIMT_Encode4(41725), |
| 9915 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 9916 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 9917 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 9918 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 9919 | GIM_Try, /*On fail goto*//*Label 443*/ GIMT_Encode4(39186), |
| 9920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 9921 | GIM_Try, /*On fail goto*//*Label 444*/ GIMT_Encode4(38840), // Rule ID 2317 // |
| 9922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 9923 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9924 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP), |
| 9925 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 9926 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9927 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 9928 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 9929 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9930 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMA), |
| 9931 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 9932 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 9933 | GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32, |
| 9934 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 9935 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9936 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9937 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9938 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))) => (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 9939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16), |
| 9940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 9942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 9943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 9944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 9945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 9946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 9947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 9948 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 9949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9951 | GIR_RootConstrainSelectedInstOperands, |
| 9952 | // GIR_Coverage, 2317, |
| 9953 | GIR_EraseRootFromParent_Done, |
| 9954 | // Label 444: @38840 |
| 9955 | GIM_Try, /*On fail goto*//*Label 445*/ GIMT_Encode4(38963), // Rule ID 2308 // |
| 9956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 9957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(AMDGPU::G_AMDGPU_CLAMP), |
| 9959 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 9960 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9961 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 9962 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 9963 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 9964 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAD), |
| 9965 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 9966 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 9967 | GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32, |
| 9968 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 9969 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9970 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9971 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 9972 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (AMDGPUclamp:{ *:[f16] } (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))))) => (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 1:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 9973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16), |
| 9974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 9975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 9976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 9977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 9978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 9979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 9980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 9981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 9982 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 9983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 9985 | GIR_RootConstrainSelectedInstOperands, |
| 9986 | // GIR_Coverage, 2308, |
| 9987 | GIR_EraseRootFromParent_Done, |
| 9988 | // Label 445: @38963 |
| 9989 | GIM_Try, /*On fail goto*//*Label 446*/ GIMT_Encode4(39074), // Rule ID 2316 // |
| 9990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 9991 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 9992 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 9993 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 9994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 9995 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMA), |
| 9996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 9997 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 9998 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 9999 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10000 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10001 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10002 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10003 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))) => (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 10004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16), |
| 10005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 10007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 10008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 10009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 10010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 10011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 10012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10013 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 10014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10016 | GIR_RootConstrainSelectedInstOperands, |
| 10017 | // GIR_Coverage, 2316, |
| 10018 | GIR_EraseRootFromParent_Done, |
| 10019 | // Label 446: @39074 |
| 10020 | GIM_Try, /*On fail goto*//*Label 447*/ GIMT_Encode4(39185), // Rule ID 2307 // |
| 10021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 10022 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10023 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 10024 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10025 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10026 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAD), |
| 10027 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10028 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10029 | GIM_CheckType, /*MI*/2, /*Op*/3, /*Type*/GILLT_s32, |
| 10030 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10031 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10032 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10033 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10034 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)))) => (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 10035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16), |
| 10036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 10038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 10039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 10040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 10041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 10042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 10043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10044 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 10045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10047 | GIR_RootConstrainSelectedInstOperands, |
| 10048 | // GIR_Coverage, 2307, |
| 10049 | GIR_EraseRootFromParent_Done, |
| 10050 | // Label 447: @39185 |
| 10051 | GIM_Reject, |
| 10052 | // Label 443: @39186 |
| 10053 | GIM_Try, /*On fail goto*//*Label 448*/ GIMT_Encode4(39500), |
| 10054 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10056 | GIM_Try, /*On fail goto*//*Label 449*/ GIMT_Encode4(39349), // Rule ID 7271 // |
| 10057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10058 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10059 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10060 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10061 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10062 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10063 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10064 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10065 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10066 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10067 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10068 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10069 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10070 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10071 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10072 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s16, |
| 10073 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] |
| 10074 | GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10075 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32, |
| 10076 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6] |
| 10077 | GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10078 | GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32, |
| 10079 | GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32, |
| 10080 | GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10081 | GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16, |
| 10082 | GIM_CheckIsSafeToFold, /*NumInsns*/6, |
| 10083 | // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] })) |
| 10084 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10085 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10086 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10087 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498), |
| 10088 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // b |
| 10092 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a |
| 10093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10094 | GIR_RootConstrainSelectedInstOperands, |
| 10095 | // GIR_Coverage, 7271, |
| 10096 | GIR_EraseRootFromParent_Done, |
| 10097 | // Label 449: @39349 |
| 10098 | GIM_Try, /*On fail goto*//*Label 450*/ GIMT_Encode4(39499), // Rule ID 7277 // |
| 10099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10100 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10101 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10102 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10103 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10104 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10105 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10106 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10107 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10108 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10109 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10110 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10111 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10112 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/0, /*OpIdx*/2, // MIs[4] |
| 10113 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10114 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s16, |
| 10115 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] |
| 10116 | GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10117 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32, |
| 10118 | GIM_RecordInsn, /*DefineMI*/6, /*MI*/5, /*OpIdx*/1, // MIs[6] |
| 10119 | GIM_CheckOpcode, /*MI*/6, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10120 | GIM_CheckType, /*MI*/6, /*Op*/1, /*Type*/GILLT_s32, |
| 10121 | GIM_CheckType, /*MI*/6, /*Op*/2, /*Type*/GILLT_s32, |
| 10122 | GIM_CheckRegBankForClass, /*MI*/6, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10123 | GIM_CheckConstantInt8, /*MI*/6, /*Op*/2, 16, |
| 10124 | GIM_CheckIsSafeToFold, /*NumInsns*/6, |
| 10125 | // (build_vector:{ *:[v2bf16] } (bitconvert:{ *:[bf16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), (bitconvert:{ *:[bf16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] })) |
| 10126 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10127 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10128 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10129 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498), |
| 10130 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10133 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/6, /*OpIdx*/1, // b |
| 10134 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a |
| 10135 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10136 | GIR_RootConstrainSelectedInstOperands, |
| 10137 | // GIR_Coverage, 7277, |
| 10138 | GIR_EraseRootFromParent_Done, |
| 10139 | // Label 450: @39499 |
| 10140 | GIM_Reject, |
| 10141 | // Label 448: @39500 |
| 10142 | GIM_Try, /*On fail goto*//*Label 451*/ GIMT_Encode4(39611), // Rule ID 7259 // |
| 10143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10145 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10146 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10147 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10148 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10149 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10150 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10151 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10152 | GIM_CheckHasOneUse, /*MI*/2, |
| 10153 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10154 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10155 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 10156 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10157 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10158 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10159 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10160 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 10161 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 10162 | GIM_CheckHasOneUse, /*MI*/4, |
| 10163 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10164 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16, |
| 10165 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10166 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 10167 | // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_36198>> => (S_PACK_HH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i32] }:$src1) |
| 10168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HH_B32_B16), |
| 10169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10170 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 10171 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // src1 |
| 10172 | GIR_RootConstrainSelectedInstOperands, |
| 10173 | // GIR_Coverage, 7259, |
| 10174 | GIR_EraseRootFromParent_Done, |
| 10175 | // Label 451: @39611 |
| 10176 | GIM_Try, /*On fail goto*//*Label 452*/ GIMT_Encode4(39674), // Rule ID 7278 // |
| 10177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10179 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36239), |
| 10180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 10181 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 10182 | // (build_vector:{ *:[v2f16] } (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } VGPR_32:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_anonymous_36239>> => (V_PACK_B32_F16_e64:{ *:[v2f16] } ?:{ *:[i32] }:$src0_mods, VGPR_32:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, VGPR_32:{ *:[f16] }:$src1) |
| 10183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PACK_B32_F16_e64), |
| 10184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 10186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 10187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 10188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 10189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10191 | GIR_RootConstrainSelectedInstOperands, |
| 10192 | // GIR_Coverage, 7278, |
| 10193 | GIR_EraseRootFromParent_Done, |
| 10194 | // Label 452: @39674 |
| 10195 | GIM_Try, /*On fail goto*//*Label 453*/ GIMT_Encode4(39876), |
| 10196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10197 | GIM_Try, /*On fail goto*//*Label 454*/ GIMT_Encode4(39779), // Rule ID 2311 // |
| 10198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 10199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 10201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10202 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10203 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 10204 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10205 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10206 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10207 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10208 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10209 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))) => (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 10210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16), |
| 10211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 10213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 10214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 10215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 10216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10219 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 10220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10222 | GIR_RootConstrainSelectedInstOperands, |
| 10223 | // GIR_Coverage, 2311, |
| 10224 | GIR_EraseRootFromParent_Done, |
| 10225 | // Label 454: @39779 |
| 10226 | GIM_Try, /*On fail goto*//*Label 455*/ GIMT_Encode4(39875), // Rule ID 2320 // |
| 10227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 10228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10229 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 10230 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10231 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10232 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 10233 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10234 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10235 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10236 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10237 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 10238 | // (build_vector:{ *:[v2f16] } f16:{ *:[f16] }:$elt0, (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)))) => (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, VGPR_32:{ *:[f16] }:$elt0) |
| 10239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16), |
| 10240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 10242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 10243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 10244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 10245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10248 | GIR_RootToRootCopy, /*OpIdx*/1, // elt0 |
| 10249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 10251 | GIR_RootConstrainSelectedInstOperands, |
| 10252 | // GIR_Coverage, 2320, |
| 10253 | GIR_EraseRootFromParent_Done, |
| 10254 | // Label 455: @39875 |
| 10255 | GIM_Reject, |
| 10256 | // Label 453: @39876 |
| 10257 | GIM_Try, /*On fail goto*//*Label 456*/ GIMT_Encode4(40380), |
| 10258 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10260 | GIM_Try, /*On fail goto*//*Label 457*/ GIMT_Encode4(40015), // Rule ID 7265 // |
| 10261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10266 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10267 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10268 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10269 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10270 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10271 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 10272 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10273 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10274 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/3, /*OpIdx*/1, // MIs[4] |
| 10275 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10276 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 10277 | GIM_CheckType, /*MI*/4, /*Op*/2, /*Type*/GILLT_s32, |
| 10278 | GIM_CheckRegBankForClass, /*MI*/4, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10279 | GIM_CheckConstantInt8, /*MI*/4, /*Op*/2, 16, |
| 10280 | GIM_CheckIsSafeToFold, /*NumInsns*/4, |
| 10281 | // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$b, VGPR_32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 117834498:{ *:[i32] })) |
| 10282 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10283 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10284 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10285 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(117834498), |
| 10286 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10289 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/4, /*OpIdx*/1, // b |
| 10290 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a |
| 10291 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10292 | GIR_RootConstrainSelectedInstOperands, |
| 10293 | // GIR_Coverage, 7265, |
| 10294 | GIR_EraseRootFromParent_Done, |
| 10295 | // Label 457: @40015 |
| 10296 | GIM_Try, /*On fail goto*//*Label 458*/ GIMT_Encode4(40094), // Rule ID 7270 // |
| 10297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10299 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10301 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10302 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10303 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10304 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10305 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10306 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10307 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10308 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10309 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10310 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10311 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 10312 | // (build_vector:{ *:[v2f16] } (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_36200>> => (V_ALIGNBIT_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }) |
| 10313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 10314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10315 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10316 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a |
| 10317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10318 | GIR_RootConstrainSelectedInstOperands, |
| 10319 | // GIR_Coverage, 7270, |
| 10320 | GIR_EraseRootFromParent_Done, |
| 10321 | // Label 458: @40094 |
| 10322 | GIM_Try, /*On fail goto*//*Label 459*/ GIMT_Encode4(40173), // Rule ID 7276 // |
| 10323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10324 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10325 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10326 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10327 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10328 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10329 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10330 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10331 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10332 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10333 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10334 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10335 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10336 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10337 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 10338 | // (build_vector:{ *:[v2bf16] } (bitconvert:{ *:[bf16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }))), VGPR_32:{ *:[bf16] }:$b)<<P:Predicate_anonymous_36200>> => (V_ALIGNBIT_B32_e64:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }) |
| 10339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 10340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10341 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // a |
| 10343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10344 | GIR_RootConstrainSelectedInstOperands, |
| 10345 | // GIR_Coverage, 7276, |
| 10346 | GIR_EraseRootFromParent_Done, |
| 10347 | // Label 459: @40173 |
| 10348 | GIM_Try, /*On fail goto*//*Label 460*/ GIMT_Encode4(40276), // Rule ID 7269 // |
| 10349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10354 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10355 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10356 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10357 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10358 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10359 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10360 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10361 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10362 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10363 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 10364 | // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, (bitconvert:{ *:[f16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_36200>> => (V_BFI_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[i32] }:$b) |
| 10365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10368 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 10369 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 10371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10372 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10373 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // b |
| 10375 | GIR_RootConstrainSelectedInstOperands, |
| 10376 | // GIR_Coverage, 7269, |
| 10377 | GIR_EraseRootFromParent_Done, |
| 10378 | // Label 460: @40276 |
| 10379 | GIM_Try, /*On fail goto*//*Label 461*/ GIMT_Encode4(40379), // Rule ID 7275 // |
| 10380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10381 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10383 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 10384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 10385 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10386 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10387 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10388 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 10389 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10390 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 10391 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 10392 | GIM_CheckRegBankForClass, /*MI*/3, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10393 | GIM_CheckConstantInt8, /*MI*/3, /*Op*/2, 16, |
| 10394 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 10395 | // (build_vector:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$a, (bitconvert:{ *:[bf16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] }))))<<P:Predicate_anonymous_36200>> => (V_BFI_B32_e64:{ *:[v2bf16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[bf16] }:$a, VGPR_32:{ *:[i32] }:$b) |
| 10396 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10397 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10398 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10399 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 10400 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 10402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10403 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10404 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/3, /*OpIdx*/1, // b |
| 10406 | GIR_RootConstrainSelectedInstOperands, |
| 10407 | // GIR_Coverage, 7275, |
| 10408 | GIR_EraseRootFromParent_Done, |
| 10409 | // Label 461: @40379 |
| 10410 | GIM_Reject, |
| 10411 | // Label 456: @40380 |
| 10412 | GIM_Try, /*On fail goto*//*Label 462*/ GIMT_Encode4(40454), // Rule ID 7258 // |
| 10413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10415 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10416 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10417 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10418 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10419 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10420 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10421 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10422 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10423 | GIM_CheckHasOneUse, /*MI*/2, |
| 10424 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10425 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10426 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10427 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10428 | // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src1, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>))<<P:Predicate_anonymous_36198>> => (S_PACK_LH_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] }:$src1) |
| 10429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LH_B32_B16), |
| 10430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10431 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 10433 | GIR_RootConstrainSelectedInstOperands, |
| 10434 | // GIR_Coverage, 7258, |
| 10435 | GIR_EraseRootFromParent_Done, |
| 10436 | // Label 462: @40454 |
| 10437 | GIM_Try, /*On fail goto*//*Label 463*/ GIMT_Encode4(40529), // Rule ID 7264 // |
| 10438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10440 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10441 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10442 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10443 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10444 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10446 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10447 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10448 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10449 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10450 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10451 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10452 | // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] })), VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_36200>> => (V_ALIGNBIT_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i32] }:$a, 16:{ *:[i32] }) |
| 10453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 10454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10455 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10456 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // a |
| 10457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10458 | GIR_RootConstrainSelectedInstOperands, |
| 10459 | // GIR_Coverage, 7264, |
| 10460 | GIR_EraseRootFromParent_Done, |
| 10461 | // Label 463: @40529 |
| 10462 | GIM_Try, /*On fail goto*//*Label 464*/ GIMT_Encode4(40599), // Rule ID 7279 // |
| 10463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 10464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10465 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10466 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10467 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10468 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10469 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10470 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10471 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10472 | GIM_CheckHasOneUse, /*MI*/2, |
| 10473 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10474 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10475 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10476 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10477 | // (build_vector:{ *:[v2i16] } (trunc:{ *:[i16] } (srl:{ *:[i32] } SReg_32:{ *:[i32] }:$src0, 16:{ *:[i32] })<<P:Predicate_srl_oneuse>>), SReg_32:{ *:[i16] }:$src1) => (S_PACK_HL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0, SReg_32:{ *:[i16] }:$src1) |
| 10478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_HL_B32_B16), |
| 10479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10480 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 10481 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10482 | GIR_RootConstrainSelectedInstOperands, |
| 10483 | // GIR_Coverage, 7279, |
| 10484 | GIR_EraseRootFromParent_Done, |
| 10485 | // Label 464: @40599 |
| 10486 | GIM_Try, /*On fail goto*//*Label 465*/ GIMT_Encode4(40698), // Rule ID 7263 // |
| 10487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10489 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10490 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10491 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_TRUNC), |
| 10492 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 10493 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 10494 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 10495 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 10496 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 10497 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10498 | GIM_CheckConstantInt8, /*MI*/2, /*Op*/2, 16, |
| 10499 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10500 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 10501 | // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, (trunc:{ *:[i16] } (srl:{ *:[i32] } VGPR_32:{ *:[i32] }:$b, 16:{ *:[i32] })))<<P:Predicate_anonymous_36200>> => (V_BFI_B32_e64:{ *:[v2i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i32] }:$b) |
| 10502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10505 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 10506 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 10508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10509 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10510 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10511 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // b |
| 10512 | GIR_RootConstrainSelectedInstOperands, |
| 10513 | // GIR_Coverage, 7263, |
| 10514 | GIR_EraseRootFromParent_Done, |
| 10515 | // Label 465: @40698 |
| 10516 | GIM_Try, /*On fail goto*//*Label 466*/ GIMT_Encode4(40734), // Rule ID 7239 // |
| 10517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10518 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 10519 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10521 | // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i16] }) |
| 10522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 10523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10524 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10526 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 10527 | GIR_RootConstrainSelectedInstOperands, |
| 10528 | // GIR_Coverage, 7239, |
| 10529 | GIR_EraseRootFromParent_Done, |
| 10530 | // Label 466: @40734 |
| 10531 | GIM_Try, /*On fail goto*//*Label 467*/ GIMT_Encode4(40767), // Rule ID 7240 // |
| 10532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10533 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/1, 0, |
| 10534 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10535 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10536 | // (build_vector:{ *:[v2i16] } 0:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36200>> => (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i16] }, VGPR_32:{ *:[i16] }:$src1) |
| 10537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 10538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10540 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10541 | GIR_RootConstrainSelectedInstOperands, |
| 10542 | // GIR_Coverage, 7240, |
| 10543 | GIR_EraseRootFromParent_Done, |
| 10544 | // Label 467: @40767 |
| 10545 | GIM_Try, /*On fail goto*//*Label 468*/ GIMT_Encode4(40827), // Rule ID 7241 // |
| 10546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10547 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10548 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 10549 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10550 | // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_36198>> => (S_AND_B32:{ *:[v2i16] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), SReg_32:{ *:[i16] }:$src1) |
| 10551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 10552 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10553 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10554 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 10555 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 10557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10559 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 10560 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 10561 | GIR_RootConstrainSelectedInstOperands, |
| 10562 | // GIR_Coverage, 7241, |
| 10563 | GIR_EraseRootFromParent_Done, |
| 10564 | // Label 468: @40827 |
| 10565 | GIM_Try, /*On fail goto*//*Label 469*/ GIMT_Encode4(40884), // Rule ID 7242 // |
| 10566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10568 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 10569 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10570 | // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src1, 0:{ *:[i16] })<<P:Predicate_anonymous_36200>> => (V_AND_B32_e64:{ *:[v2i16] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), VGPR_32:{ *:[i16] }:$src1) |
| 10571 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 10572 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 10573 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10574 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 10575 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 10577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10578 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10579 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 10580 | GIR_RootConstrainSelectedInstOperands, |
| 10581 | // GIR_Coverage, 7242, |
| 10582 | GIR_EraseRootFromParent_Done, |
| 10583 | // Label 469: @40884 |
| 10584 | GIM_Try, /*On fail goto*//*Label 470*/ GIMT_Encode4(40926), // Rule ID 7247 // |
| 10585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10586 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10587 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10588 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10589 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10590 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10591 | // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_LSHL_B32:{ *:[v2i16] }:{ *:[i1] } SReg_32:{ *:[i16] }:$src1, 16:{ *:[i32] }) |
| 10592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 10593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10594 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10596 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 10597 | GIR_RootConstrainSelectedInstOperands, |
| 10598 | // GIR_Coverage, 7247, |
| 10599 | GIR_EraseRootFromParent_Done, |
| 10600 | // Label 470: @40926 |
| 10601 | GIM_Try, /*On fail goto*//*Label 471*/ GIMT_Encode4(40965), // Rule ID 7248 // |
| 10602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10605 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10606 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10607 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10608 | // (build_vector:{ *:[v2i16] } (undef:{ *:[i16] }), VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36200>> => (V_LSHLREV_B32_e64:{ *:[v2i16] } 16:{ *:[i32] }, VGPR_32:{ *:[i16] }:$src1) |
| 10609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 10610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10612 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10613 | GIR_RootConstrainSelectedInstOperands, |
| 10614 | // GIR_Coverage, 7248, |
| 10615 | GIR_EraseRootFromParent_Done, |
| 10616 | // Label 471: @40965 |
| 10617 | GIM_Try, /*On fail goto*//*Label 472*/ GIMT_Encode4(41007), // Rule ID 7251 // |
| 10618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10619 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10620 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10621 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10622 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10623 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10624 | // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_LSHL_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src1, 16:{ *:[i32] }) |
| 10625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 10626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10627 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10629 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 10630 | GIR_RootConstrainSelectedInstOperands, |
| 10631 | // GIR_Coverage, 7251, |
| 10632 | GIR_EraseRootFromParent_Done, |
| 10633 | // Label 472: @41007 |
| 10634 | GIM_Try, /*On fail goto*//*Label 473*/ GIMT_Encode4(41046), // Rule ID 7252 // |
| 10635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10638 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10639 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10640 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10641 | // (build_vector:{ *:[v2f16] } (undef:{ *:[f16] }), VGPR_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_36200>> => (V_LSHLREV_B32_e64:{ *:[v2f16] } 16:{ *:[i32] }, VGPR_32:{ *:[f16] }:$src1) |
| 10642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 10643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10645 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10646 | GIR_RootConstrainSelectedInstOperands, |
| 10647 | // GIR_Coverage, 7252, |
| 10648 | GIR_EraseRootFromParent_Done, |
| 10649 | // Label 473: @41046 |
| 10650 | GIM_Try, /*On fail goto*//*Label 474*/ GIMT_Encode4(41088), // Rule ID 7255 // |
| 10651 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10652 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10653 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10654 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10655 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10656 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10657 | // (build_vector:{ *:[v2bf16] } (undef:{ *:[bf16] }), SReg_32:{ *:[bf16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_LSHL_B32:{ *:[v2bf16] }:{ *:[i1] } SReg_32:{ *:[bf16] }:$src1, 16:{ *:[i32] }) |
| 10658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 10659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 10660 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10662 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 10663 | GIR_RootConstrainSelectedInstOperands, |
| 10664 | // GIR_Coverage, 7255, |
| 10665 | GIR_EraseRootFromParent_Done, |
| 10666 | // Label 474: @41088 |
| 10667 | GIM_Try, /*On fail goto*//*Label 475*/ GIMT_Encode4(41127), // Rule ID 7256 // |
| 10668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10669 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 10670 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10671 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10672 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10673 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10674 | // (build_vector:{ *:[v2bf16] } (undef:{ *:[bf16] }), VGPR_32:{ *:[bf16] }:$src1)<<P:Predicate_anonymous_36200>> => (V_LSHLREV_B32_e64:{ *:[v2bf16] } 16:{ *:[i32] }, VGPR_32:{ *:[bf16] }:$src1) |
| 10675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 10676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10678 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10679 | GIR_RootConstrainSelectedInstOperands, |
| 10680 | // GIR_Coverage, 7256, |
| 10681 | GIR_EraseRootFromParent_Done, |
| 10682 | // Label 475: @41127 |
| 10683 | GIM_Try, /*On fail goto*//*Label 476*/ GIMT_Encode4(41167), // Rule ID 7245 // |
| 10684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10688 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10689 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10690 | // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_36198>> => (COPY_TO_REGCLASS:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i32] }) |
| 10691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10693 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10694 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10695 | // GIR_Coverage, 7245, |
| 10696 | GIR_EraseRootFromParent_Done, |
| 10697 | // Label 476: @41167 |
| 10698 | GIM_Try, /*On fail goto*//*Label 477*/ GIMT_Encode4(41207), // Rule ID 7246 // |
| 10699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10700 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10701 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10702 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10703 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10704 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10705 | // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, (undef:{ *:[i16] }))<<P:Predicate_anonymous_36200>> => (COPY_TO_REGCLASS:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i32] }) |
| 10706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10708 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10709 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10710 | // GIR_Coverage, 7246, |
| 10711 | GIR_EraseRootFromParent_Done, |
| 10712 | // Label 477: @41207 |
| 10713 | GIM_Try, /*On fail goto*//*Label 478*/ GIMT_Encode4(41247), // Rule ID 7249 // |
| 10714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10718 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10719 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10720 | // (build_vector:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, (undef:{ *:[f16] }))<<P:Predicate_anonymous_36198>> => (COPY_TO_REGCLASS:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[i32] }) |
| 10721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10723 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10724 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10725 | // GIR_Coverage, 7249, |
| 10726 | GIR_EraseRootFromParent_Done, |
| 10727 | // Label 478: @41247 |
| 10728 | GIM_Try, /*On fail goto*//*Label 479*/ GIMT_Encode4(41287), // Rule ID 7250 // |
| 10729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10733 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10734 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10735 | // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$src0, (undef:{ *:[f16] }))<<P:Predicate_anonymous_36200>> => (COPY_TO_REGCLASS:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$src0, VGPR_32:{ *:[i32] }) |
| 10736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10738 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10739 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10740 | // GIR_Coverage, 7250, |
| 10741 | GIR_EraseRootFromParent_Done, |
| 10742 | // Label 479: @41287 |
| 10743 | GIM_Try, /*On fail goto*//*Label 480*/ GIMT_Encode4(41327), // Rule ID 7253 // |
| 10744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10745 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10746 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10747 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10748 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10749 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10750 | // (build_vector:{ *:[v2bf16] } SReg_32:{ *:[bf16] }:$src0, (undef:{ *:[bf16] }))<<P:Predicate_anonymous_36198>> => (COPY_TO_REGCLASS:{ *:[v2bf16] } SReg_32:{ *:[bf16] }:$src0, SReg_32:{ *:[i32] }) |
| 10751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10753 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10754 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10755 | // GIR_Coverage, 7253, |
| 10756 | GIR_EraseRootFromParent_Done, |
| 10757 | // Label 480: @41327 |
| 10758 | GIM_Try, /*On fail goto*//*Label 481*/ GIMT_Encode4(41445), |
| 10759 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10761 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10762 | GIM_Try, /*On fail goto*//*Label 482*/ GIMT_Encode4(41372), // Rule ID 7254 // |
| 10763 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 10764 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_IMPLICIT_DEF), |
| 10765 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 10766 | // (build_vector:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$src0, (undef:{ *:[bf16] }))<<P:Predicate_anonymous_36200>> => (COPY_TO_REGCLASS:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$src0, VGPR_32:{ *:[i32] }) |
| 10767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 10769 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10770 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10771 | // GIR_Coverage, 7254, |
| 10772 | GIR_EraseRootFromParent_Done, |
| 10773 | // Label 482: @41372 |
| 10774 | GIM_Try, /*On fail goto*//*Label 483*/ GIMT_Encode4(41444), // Rule ID 7257 // |
| 10775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10776 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10777 | // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$src0, VGPR_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36200>> => (V_LSHL_OR_B32_e64:{ *:[v2i16] } ?:{ *:[i16] }:$src1, 16:{ *:[i32] }, (V_AND_B32_e64:{ *:[i32] } (V_MOV_B32_e32:{ *:[i32] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src0)) |
| 10778 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 10779 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 10780 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 10781 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10782 | GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535), |
| 10783 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 10784 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 10785 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10786 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 10787 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src0 |
| 10788 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_OR_B32_e64), |
| 10790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10791 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 10792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 10793 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10794 | GIR_RootConstrainSelectedInstOperands, |
| 10795 | // GIR_Coverage, 7257, |
| 10796 | GIR_EraseRootFromParent_Done, |
| 10797 | // Label 483: @41444 |
| 10798 | GIM_Reject, |
| 10799 | // Label 481: @41445 |
| 10800 | GIM_Try, /*On fail goto*//*Label 484*/ GIMT_Encode4(41476), // Rule ID 7260 // |
| 10801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10803 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10804 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10805 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10806 | // (build_vector:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_PACK_LL_B32_B16:{ *:[v2i16] } SReg_32:{ *:[i16] }:$src0, SReg_32:{ *:[i16] }:$src1) |
| 10807 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16), |
| 10808 | GIR_RootConstrainSelectedInstOperands, |
| 10809 | // GIR_Coverage, 7260, |
| 10810 | GIR_Done, |
| 10811 | // Label 484: @41476 |
| 10812 | GIM_Try, /*On fail goto*//*Label 485*/ GIMT_Encode4(41538), // Rule ID 7261 // |
| 10813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10815 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10816 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10817 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10818 | // (build_vector:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$a, VGPR_32:{ *:[i16] }:$b)<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2i16] } VGPR_32:{ *:[i16] }:$b, VGPR_32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] })) |
| 10819 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10820 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10821 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10822 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480), |
| 10823 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10826 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10827 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10828 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10829 | GIR_RootConstrainSelectedInstOperands, |
| 10830 | // GIR_Coverage, 7261, |
| 10831 | GIR_EraseRootFromParent_Done, |
| 10832 | // Label 485: @41538 |
| 10833 | GIM_Try, /*On fail goto*//*Label 486*/ GIMT_Encode4(41569), // Rule ID 7266 // |
| 10834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10837 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10839 | // (build_vector:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_PACK_LL_B32_B16:{ *:[v2f16] } SReg_32:{ *:[f16] }:$src0, SReg_32:{ *:[f16] }:$src1) |
| 10840 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16), |
| 10841 | GIR_RootConstrainSelectedInstOperands, |
| 10842 | // GIR_Coverage, 7266, |
| 10843 | GIR_Done, |
| 10844 | // Label 486: @41569 |
| 10845 | GIM_Try, /*On fail goto*//*Label 487*/ GIMT_Encode4(41631), // Rule ID 7267 // |
| 10846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10849 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10851 | // (build_vector:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$a, VGPR_32:{ *:[f16] }:$b)<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2f16] } VGPR_32:{ *:[f16] }:$b, VGPR_32:{ *:[f16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] })) |
| 10852 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10853 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10854 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10855 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480), |
| 10856 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10859 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10860 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10861 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10862 | GIR_RootConstrainSelectedInstOperands, |
| 10863 | // GIR_Coverage, 7267, |
| 10864 | GIR_EraseRootFromParent_Done, |
| 10865 | // Label 487: @41631 |
| 10866 | GIM_Try, /*On fail goto*//*Label 488*/ GIMT_Encode4(41662), // Rule ID 7272 // |
| 10867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10869 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10870 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10871 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36198), |
| 10872 | // (build_vector:{ *:[v2bf16] } SReg_32:{ *:[bf16] }:$src0, SReg_32:{ *:[bf16] }:$src1)<<P:Predicate_anonymous_36198>> => (S_PACK_LL_B32_B16:{ *:[v2bf16] } SReg_32:{ *:[bf16] }:$src0, SReg_32:{ *:[bf16] }:$src1) |
| 10873 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_PACK_LL_B32_B16), |
| 10874 | GIR_RootConstrainSelectedInstOperands, |
| 10875 | // GIR_Coverage, 7272, |
| 10876 | GIR_Done, |
| 10877 | // Label 488: @41662 |
| 10878 | GIM_Try, /*On fail goto*//*Label 489*/ GIMT_Encode4(41724), // Rule ID 7273 // |
| 10879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 10880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10881 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10882 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10883 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36200), |
| 10884 | // (build_vector:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$a, VGPR_32:{ *:[bf16] }:$b)<<P:Predicate_anonymous_36200>> => (V_PERM_B32_e64:{ *:[v2bf16] } VGPR_32:{ *:[bf16] }:$b, VGPR_32:{ *:[bf16] }:$a, (S_MOV_B32:{ *:[i16] } 84148480:{ *:[i32] })) |
| 10885 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 10886 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 10887 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 10888 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(84148480), |
| 10889 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 10890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 10891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 10892 | GIR_RootToRootCopy, /*OpIdx*/2, // b |
| 10893 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 10894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 10895 | GIR_RootConstrainSelectedInstOperands, |
| 10896 | // GIR_Coverage, 7273, |
| 10897 | GIR_EraseRootFromParent_Done, |
| 10898 | // Label 489: @41724 |
| 10899 | GIM_Reject, |
| 10900 | // Label 442: @41725 |
| 10901 | GIM_Reject, |
| 10902 | // Label 8: @41726 |
| 10903 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(34), /*)*//*default:*//*Label 516*/ GIMT_Encode4(50198), |
| 10904 | /*GILLT_s16*//*Label 490*/ GIMT_Encode4(41841), |
| 10905 | /*GILLT_s32*//*Label 491*/ GIMT_Encode4(42163), |
| 10906 | /*GILLT_s64*//*Label 492*/ GIMT_Encode4(42512), |
| 10907 | /*GILLT_v2s16*//*Label 493*/ GIMT_Encode4(42861), |
| 10908 | /*GILLT_v2s32*//*Label 494*/ GIMT_Encode4(43384), |
| 10909 | /*GILLT_v2s64*//*Label 495*/ GIMT_Encode4(43762), |
| 10910 | /*GILLT_v3s32*//*Label 496*/ GIMT_Encode4(44169), |
| 10911 | /*GILLT_v3s64*//*Label 497*/ GIMT_Encode4(44223), |
| 10912 | /*GILLT_v4s16*//*Label 498*/ GIMT_Encode4(44398), |
| 10913 | /*GILLT_v4s32*//*Label 499*/ GIMT_Encode4(44921), |
| 10914 | /*GILLT_v4s64*//*Label 500*/ GIMT_Encode4(45328), |
| 10915 | /*GILLT_v5s32*//*Label 501*/ GIMT_Encode4(45677), |
| 10916 | /*GILLT_v6s32*//*Label 502*/ GIMT_Encode4(45791), |
| 10917 | /*GILLT_v7s32*//*Label 503*/ GIMT_Encode4(46024), |
| 10918 | /*GILLT_v8s16*//*Label 504*/ GIMT_Encode4(46138), |
| 10919 | /*GILLT_v8s32*//*Label 505*/ GIMT_Encode4(46951), |
| 10920 | /*GILLT_v8s64*//*Label 506*/ GIMT_Encode4(47358), |
| 10921 | /*GILLT_v9s32*//*Label 507*/ GIMT_Encode4(47649), |
| 10922 | /*GILLT_v10s32*//*Label 508*/ GIMT_Encode4(47763), |
| 10923 | /*GILLT_v11s32*//*Label 509*/ GIMT_Encode4(47877), |
| 10924 | /*GILLT_v12s32*//*Label 510*/ GIMT_Encode4(47991), |
| 10925 | /*GILLT_v16s16*//*Label 511*/ GIMT_Encode4(48105), |
| 10926 | /*GILLT_v16s32*//*Label 512*/ GIMT_Encode4(48802), |
| 10927 | /*GILLT_v16s64*//*Label 513*/ GIMT_Encode4(49209), |
| 10928 | /*GILLT_v32s16*//*Label 514*/ GIMT_Encode4(49384), |
| 10929 | /*GILLT_v32s32*//*Label 515*/ GIMT_Encode4(50023), |
| 10930 | // Label 490: @41841 |
| 10931 | GIM_Try, /*On fail goto*//*Label 517*/ GIMT_Encode4(42162), |
| 10932 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 10933 | GIM_Try, /*On fail goto*//*Label 518*/ GIMT_Encode4(41875), // Rule ID 6712 // |
| 10934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10935 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10936 | // (bitconvert:{ *:[i16] } VGPR_32:{ *:[f16] }:$src0) => VGPR_32:{ *:[i16] }:$src0 |
| 10937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10938 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10939 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10940 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10941 | // GIR_Coverage, 6712, |
| 10942 | GIR_EraseRootFromParent_Done, |
| 10943 | // Label 518: @41875 |
| 10944 | GIM_Try, /*On fail goto*//*Label 519*/ GIMT_Encode4(41901), // Rule ID 6713 // |
| 10945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10947 | // (bitconvert:{ *:[f16] } VGPR_32:{ *:[i16] }:$src0) => VGPR_32:{ *:[f16] }:$src0 |
| 10948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10949 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10950 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10951 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10952 | // GIR_Coverage, 6713, |
| 10953 | GIR_EraseRootFromParent_Done, |
| 10954 | // Label 519: @41901 |
| 10955 | GIM_Try, /*On fail goto*//*Label 520*/ GIMT_Encode4(41927), // Rule ID 6714 // |
| 10956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10957 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10958 | // (bitconvert:{ *:[f16] } VGPR_32:{ *:[bf16] }:$src0) => VGPR_32:{ *:[f16] }:$src0 |
| 10959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10960 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10961 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10962 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10963 | // GIR_Coverage, 6714, |
| 10964 | GIR_EraseRootFromParent_Done, |
| 10965 | // Label 520: @41927 |
| 10966 | GIM_Try, /*On fail goto*//*Label 521*/ GIMT_Encode4(41953), // Rule ID 6715 // |
| 10967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10968 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10969 | // (bitconvert:{ *:[bf16] } VGPR_32:{ *:[f16] }:$src0) => VGPR_32:{ *:[bf16] }:$src0 |
| 10970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10971 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10972 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10973 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 10974 | // GIR_Coverage, 6715, |
| 10975 | GIR_EraseRootFromParent_Done, |
| 10976 | // Label 521: @41953 |
| 10977 | GIM_Try, /*On fail goto*//*Label 522*/ GIMT_Encode4(41979), // Rule ID 6716 // |
| 10978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10979 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10980 | // (bitconvert:{ *:[i16] } SReg_32:{ *:[f16] }:$src0) => SReg_32:{ *:[i16] }:$src0 |
| 10981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10982 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10983 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10984 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10985 | // GIR_Coverage, 6716, |
| 10986 | GIR_EraseRootFromParent_Done, |
| 10987 | // Label 522: @41979 |
| 10988 | GIM_Try, /*On fail goto*//*Label 523*/ GIMT_Encode4(42005), // Rule ID 6717 // |
| 10989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10991 | // (bitconvert:{ *:[f16] } SReg_32:{ *:[i16] }:$src0) => SReg_32:{ *:[f16] }:$src0 |
| 10992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 10993 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 10994 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 10995 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 10996 | // GIR_Coverage, 6717, |
| 10997 | GIR_EraseRootFromParent_Done, |
| 10998 | // Label 523: @42005 |
| 10999 | GIM_Try, /*On fail goto*//*Label 524*/ GIMT_Encode4(42031), // Rule ID 6718 // |
| 11000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11001 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11002 | // (bitconvert:{ *:[f16] } SReg_32:{ *:[bf16] }:$src0) => SReg_32:{ *:[f16] }:$src0 |
| 11003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11004 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11005 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11006 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11007 | // GIR_Coverage, 6718, |
| 11008 | GIR_EraseRootFromParent_Done, |
| 11009 | // Label 524: @42031 |
| 11010 | GIM_Try, /*On fail goto*//*Label 525*/ GIMT_Encode4(42057), // Rule ID 6719 // |
| 11011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11012 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11013 | // (bitconvert:{ *:[bf16] } SReg_32:{ *:[f16] }:$src0) => SReg_32:{ *:[bf16] }:$src0 |
| 11014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11015 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11016 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11017 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11018 | // GIR_Coverage, 6719, |
| 11019 | GIR_EraseRootFromParent_Done, |
| 11020 | // Label 525: @42057 |
| 11021 | GIM_Try, /*On fail goto*//*Label 526*/ GIMT_Encode4(42083), // Rule ID 6720 // |
| 11022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11023 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11024 | // (bitconvert:{ *:[i16] } VGPR_32:{ *:[bf16] }:$src0) => VGPR_32:{ *:[i16] }:$src0 |
| 11025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11026 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11027 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11028 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11029 | // GIR_Coverage, 6720, |
| 11030 | GIR_EraseRootFromParent_Done, |
| 11031 | // Label 526: @42083 |
| 11032 | GIM_Try, /*On fail goto*//*Label 527*/ GIMT_Encode4(42109), // Rule ID 6721 // |
| 11033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11034 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11035 | // (bitconvert:{ *:[bf16] } VGPR_32:{ *:[i16] }:$src0) => VGPR_32:{ *:[bf16] }:$src0 |
| 11036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11037 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11038 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11039 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11040 | // GIR_Coverage, 6721, |
| 11041 | GIR_EraseRootFromParent_Done, |
| 11042 | // Label 527: @42109 |
| 11043 | GIM_Try, /*On fail goto*//*Label 528*/ GIMT_Encode4(42135), // Rule ID 6722 // |
| 11044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11045 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11046 | // (bitconvert:{ *:[i16] } SReg_32:{ *:[bf16] }:$src0) => SReg_32:{ *:[i16] }:$src0 |
| 11047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11048 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11049 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11050 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11051 | // GIR_Coverage, 6722, |
| 11052 | GIR_EraseRootFromParent_Done, |
| 11053 | // Label 528: @42135 |
| 11054 | GIM_Try, /*On fail goto*//*Label 529*/ GIMT_Encode4(42161), // Rule ID 6723 // |
| 11055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11057 | // (bitconvert:{ *:[bf16] } SReg_32:{ *:[i16] }:$src0) => SReg_32:{ *:[bf16] }:$src0 |
| 11058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11059 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11060 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11061 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11062 | // GIR_Coverage, 6723, |
| 11063 | GIR_EraseRootFromParent_Done, |
| 11064 | // Label 529: @42161 |
| 11065 | GIM_Reject, |
| 11066 | // Label 517: @42162 |
| 11067 | GIM_Reject, |
| 11068 | // Label 491: @42163 |
| 11069 | GIM_Try, /*On fail goto*//*Label 530*/ GIMT_Encode4(42192), // Rule ID 6724 // |
| 11070 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11072 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11073 | // (bitconvert:{ *:[i32] } VGPR_32:{ *:[f32] }:$src0) => VGPR_32:{ *:[i32] }:$src0 |
| 11074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11075 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11076 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11077 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11078 | // GIR_Coverage, 6724, |
| 11079 | GIR_EraseRootFromParent_Done, |
| 11080 | // Label 530: @42192 |
| 11081 | GIM_Try, /*On fail goto*//*Label 531*/ GIMT_Encode4(42221), // Rule ID 6725 // |
| 11082 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11084 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11085 | // (bitconvert:{ *:[f32] } VGPR_32:{ *:[i32] }:$src0) => VGPR_32:{ *:[f32] }:$src0 |
| 11086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11087 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11088 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11089 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11090 | // GIR_Coverage, 6725, |
| 11091 | GIR_EraseRootFromParent_Done, |
| 11092 | // Label 531: @42221 |
| 11093 | GIM_Try, /*On fail goto*//*Label 532*/ GIMT_Encode4(42250), // Rule ID 6726 // |
| 11094 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11096 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11097 | // (bitconvert:{ *:[i32] } SReg_32:{ *:[f32] }:$src0) => SReg_32:{ *:[i32] }:$src0 |
| 11098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11099 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11100 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11101 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11102 | // GIR_Coverage, 6726, |
| 11103 | GIR_EraseRootFromParent_Done, |
| 11104 | // Label 532: @42250 |
| 11105 | GIM_Try, /*On fail goto*//*Label 533*/ GIMT_Encode4(42279), // Rule ID 6727 // |
| 11106 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11108 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11109 | // (bitconvert:{ *:[f32] } SReg_32:{ *:[i32] }:$src0) => SReg_32:{ *:[f32] }:$src0 |
| 11110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11111 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11112 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11113 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11114 | // GIR_Coverage, 6727, |
| 11115 | GIR_EraseRootFromParent_Done, |
| 11116 | // Label 533: @42279 |
| 11117 | GIM_Try, /*On fail goto*//*Label 534*/ GIMT_Encode4(42308), // Rule ID 6729 // |
| 11118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11120 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11121 | // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2i16] }:$src0) => SReg_32:{ *:[i32] }:$src0 |
| 11122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11123 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11124 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11125 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11126 | // GIR_Coverage, 6729, |
| 11127 | GIR_EraseRootFromParent_Done, |
| 11128 | // Label 534: @42308 |
| 11129 | GIM_Try, /*On fail goto*//*Label 535*/ GIMT_Encode4(42337), // Rule ID 6731 // |
| 11130 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11133 | // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2f16] }:$src0) => SReg_32:{ *:[i32] }:$src0 |
| 11134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11135 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11136 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11137 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11138 | // GIR_Coverage, 6731, |
| 11139 | GIR_EraseRootFromParent_Done, |
| 11140 | // Label 535: @42337 |
| 11141 | GIM_Try, /*On fail goto*//*Label 536*/ GIMT_Encode4(42366), // Rule ID 6735 // |
| 11142 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11144 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11145 | // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2f16] }:$src0) => SReg_32:{ *:[f32] }:$src0 |
| 11146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11147 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11148 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11149 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11150 | // GIR_Coverage, 6735, |
| 11151 | GIR_EraseRootFromParent_Done, |
| 11152 | // Label 536: @42366 |
| 11153 | GIM_Try, /*On fail goto*//*Label 537*/ GIMT_Encode4(42395), // Rule ID 6737 // |
| 11154 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11157 | // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2i16] }:$src0) => SReg_32:{ *:[f32] }:$src0 |
| 11158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11159 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11160 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11161 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11162 | // GIR_Coverage, 6737, |
| 11163 | GIR_EraseRootFromParent_Done, |
| 11164 | // Label 537: @42395 |
| 11165 | GIM_Try, /*On fail goto*//*Label 538*/ GIMT_Encode4(42424), // Rule ID 6739 // |
| 11166 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11168 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11169 | // (bitconvert:{ *:[i32] } SReg_32:{ *:[v2bf16] }:$src0) => SReg_32:{ *:[i32] }:$src0 |
| 11170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11171 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11172 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11173 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11174 | // GIR_Coverage, 6739, |
| 11175 | GIR_EraseRootFromParent_Done, |
| 11176 | // Label 538: @42424 |
| 11177 | GIM_Try, /*On fail goto*//*Label 539*/ GIMT_Encode4(42453), // Rule ID 6741 // |
| 11178 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11180 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11181 | // (bitconvert:{ *:[i32] } VGPR_32:{ *:[v2bf16] }:$src0) => VGPR_32:{ *:[i32] }:$src0 |
| 11182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11183 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11184 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11185 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11186 | // GIR_Coverage, 6741, |
| 11187 | GIR_EraseRootFromParent_Done, |
| 11188 | // Label 539: @42453 |
| 11189 | GIM_Try, /*On fail goto*//*Label 540*/ GIMT_Encode4(42482), // Rule ID 6750 // |
| 11190 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11191 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11192 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11193 | // (bitconvert:{ *:[f32] } VGPR_32:{ *:[v2bf16] }:$src0) => VGPR_32:{ *:[f32] }:$src0 |
| 11194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11195 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11196 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11197 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11198 | // GIR_Coverage, 6750, |
| 11199 | GIR_EraseRootFromParent_Done, |
| 11200 | // Label 540: @42482 |
| 11201 | GIM_Try, /*On fail goto*//*Label 541*/ GIMT_Encode4(42511), // Rule ID 6752 // |
| 11202 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11205 | // (bitconvert:{ *:[f32] } SReg_32:{ *:[v2bf16] }:$src0) => SReg_32:{ *:[f32] }:$src0 |
| 11206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11207 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11208 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11209 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11210 | // GIR_Coverage, 6752, |
| 11211 | GIR_EraseRootFromParent_Done, |
| 11212 | // Label 541: @42511 |
| 11213 | GIM_Reject, |
| 11214 | // Label 492: @42512 |
| 11215 | GIM_Try, /*On fail goto*//*Label 542*/ GIMT_Encode4(42541), // Rule ID 6754 // |
| 11216 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11218 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11219 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11221 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11222 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11223 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11224 | // GIR_Coverage, 6754, |
| 11225 | GIR_EraseRootFromParent_Done, |
| 11226 | // Label 542: @42541 |
| 11227 | GIM_Try, /*On fail goto*//*Label 543*/ GIMT_Encode4(42570), // Rule ID 6755 // |
| 11228 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11230 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11231 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11233 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11234 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11235 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11236 | // GIR_Coverage, 6755, |
| 11237 | GIR_EraseRootFromParent_Done, |
| 11238 | // Label 543: @42570 |
| 11239 | GIM_Try, /*On fail goto*//*Label 544*/ GIMT_Encode4(42599), // Rule ID 6758 // |
| 11240 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11242 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11243 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11245 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11246 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11247 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11248 | // GIR_Coverage, 6758, |
| 11249 | GIR_EraseRootFromParent_Done, |
| 11250 | // Label 544: @42599 |
| 11251 | GIM_Try, /*On fail goto*//*Label 545*/ GIMT_Encode4(42628), // Rule ID 6760 // |
| 11252 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11255 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11257 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11258 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11259 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11260 | // GIR_Coverage, 6760, |
| 11261 | GIR_EraseRootFromParent_Done, |
| 11262 | // Label 545: @42628 |
| 11263 | GIM_Try, /*On fail goto*//*Label 546*/ GIMT_Encode4(42657), // Rule ID 6762 // |
| 11264 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11266 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11267 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11269 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11270 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11271 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11272 | // GIR_Coverage, 6762, |
| 11273 | GIR_EraseRootFromParent_Done, |
| 11274 | // Label 546: @42657 |
| 11275 | GIM_Try, /*On fail goto*//*Label 547*/ GIMT_Encode4(42686), // Rule ID 6764 // |
| 11276 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11278 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11279 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11281 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11282 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11283 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11284 | // GIR_Coverage, 6764, |
| 11285 | GIR_EraseRootFromParent_Done, |
| 11286 | // Label 547: @42686 |
| 11287 | GIM_Try, /*On fail goto*//*Label 548*/ GIMT_Encode4(42715), // Rule ID 6771 // |
| 11288 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11289 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11290 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11291 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11293 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11294 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11295 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11296 | // GIR_Coverage, 6771, |
| 11297 | GIR_EraseRootFromParent_Done, |
| 11298 | // Label 548: @42715 |
| 11299 | GIM_Try, /*On fail goto*//*Label 549*/ GIMT_Encode4(42744), // Rule ID 6779 // |
| 11300 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11302 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11303 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11305 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11306 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11307 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11308 | // GIR_Coverage, 6779, |
| 11309 | GIR_EraseRootFromParent_Done, |
| 11310 | // Label 549: @42744 |
| 11311 | GIM_Try, /*On fail goto*//*Label 550*/ GIMT_Encode4(42773), // Rule ID 6791 // |
| 11312 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11314 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11315 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11317 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11318 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11319 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11320 | // GIR_Coverage, 6791, |
| 11321 | GIR_EraseRootFromParent_Done, |
| 11322 | // Label 550: @42773 |
| 11323 | GIM_Try, /*On fail goto*//*Label 551*/ GIMT_Encode4(42802), // Rule ID 6792 // |
| 11324 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11326 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11327 | // (bitconvert:{ *:[f64] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[f64] }:$src0 |
| 11328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11329 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11330 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11331 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11332 | // GIR_Coverage, 6792, |
| 11333 | GIR_EraseRootFromParent_Done, |
| 11334 | // Label 551: @42802 |
| 11335 | GIM_Try, /*On fail goto*//*Label 552*/ GIMT_Encode4(42831), // Rule ID 6795 // |
| 11336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11338 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11339 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11341 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11342 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11343 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11344 | // GIR_Coverage, 6795, |
| 11345 | GIR_EraseRootFromParent_Done, |
| 11346 | // Label 552: @42831 |
| 11347 | GIM_Try, /*On fail goto*//*Label 553*/ GIMT_Encode4(42860), // Rule ID 6796 // |
| 11348 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11351 | // (bitconvert:{ *:[i64] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[i64] }:$src0 |
| 11352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11353 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11354 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11355 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11356 | // GIR_Coverage, 6796, |
| 11357 | GIR_EraseRootFromParent_Done, |
| 11358 | // Label 553: @42860 |
| 11359 | GIM_Reject, |
| 11360 | // Label 493: @42861 |
| 11361 | GIM_Try, /*On fail goto*//*Label 554*/ GIMT_Encode4(42890), // Rule ID 6728 // |
| 11362 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11364 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11365 | // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[i32] }:$src0) => SReg_32:{ *:[v2i16] }:$src0 |
| 11366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11367 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11368 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11369 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11370 | // GIR_Coverage, 6728, |
| 11371 | GIR_EraseRootFromParent_Done, |
| 11372 | // Label 554: @42890 |
| 11373 | GIM_Try, /*On fail goto*//*Label 555*/ GIMT_Encode4(42919), // Rule ID 6730 // |
| 11374 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11376 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11377 | // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[i32] }:$src0) => SReg_32:{ *:[v2f16] }:$src0 |
| 11378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11379 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11380 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11381 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11382 | // GIR_Coverage, 6730, |
| 11383 | GIR_EraseRootFromParent_Done, |
| 11384 | // Label 555: @42919 |
| 11385 | GIM_Try, /*On fail goto*//*Label 556*/ GIMT_Encode4(42948), // Rule ID 6732 // |
| 11386 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11387 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11388 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11389 | // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2f16] }:$src0) => SReg_32:{ *:[v2i16] }:$src0 |
| 11390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11391 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11392 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11393 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11394 | // GIR_Coverage, 6732, |
| 11395 | GIR_EraseRootFromParent_Done, |
| 11396 | // Label 556: @42948 |
| 11397 | GIM_Try, /*On fail goto*//*Label 557*/ GIMT_Encode4(42977), // Rule ID 6733 // |
| 11398 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11400 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11401 | // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2i16] }:$src0) => SReg_32:{ *:[v2f16] }:$src0 |
| 11402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11403 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11404 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11405 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11406 | // GIR_Coverage, 6733, |
| 11407 | GIR_EraseRootFromParent_Done, |
| 11408 | // Label 557: @42977 |
| 11409 | GIM_Try, /*On fail goto*//*Label 558*/ GIMT_Encode4(43006), // Rule ID 6734 // |
| 11410 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11412 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11413 | // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[f32] }:$src0) => SReg_32:{ *:[v2f16] }:$src0 |
| 11414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11415 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11416 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11417 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11418 | // GIR_Coverage, 6734, |
| 11419 | GIR_EraseRootFromParent_Done, |
| 11420 | // Label 558: @43006 |
| 11421 | GIM_Try, /*On fail goto*//*Label 559*/ GIMT_Encode4(43035), // Rule ID 6736 // |
| 11422 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11424 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11425 | // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[f32] }:$src0) => SReg_32:{ *:[v2i16] }:$src0 |
| 11426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11427 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11428 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11429 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11430 | // GIR_Coverage, 6736, |
| 11431 | GIR_EraseRootFromParent_Done, |
| 11432 | // Label 559: @43035 |
| 11433 | GIM_Try, /*On fail goto*//*Label 560*/ GIMT_Encode4(43064), // Rule ID 6738 // |
| 11434 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11436 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11437 | // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[i32] }:$src0) => SReg_32:{ *:[v2bf16] }:$src0 |
| 11438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11439 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11440 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11441 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11442 | // GIR_Coverage, 6738, |
| 11443 | GIR_EraseRootFromParent_Done, |
| 11444 | // Label 560: @43064 |
| 11445 | GIM_Try, /*On fail goto*//*Label 561*/ GIMT_Encode4(43093), // Rule ID 6740 // |
| 11446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11448 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11449 | // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$src0) => VGPR_32:{ *:[v2bf16] }:$src0 |
| 11450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11451 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11452 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11453 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11454 | // GIR_Coverage, 6740, |
| 11455 | GIR_EraseRootFromParent_Done, |
| 11456 | // Label 561: @43093 |
| 11457 | GIM_Try, /*On fail goto*//*Label 562*/ GIMT_Encode4(43122), // Rule ID 6742 // |
| 11458 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11460 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11461 | // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[v2i16] }:$src0) => SReg_32:{ *:[v2bf16] }:$src0 |
| 11462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11463 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11464 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11465 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11466 | // GIR_Coverage, 6742, |
| 11467 | GIR_EraseRootFromParent_Done, |
| 11468 | // Label 562: @43122 |
| 11469 | GIM_Try, /*On fail goto*//*Label 563*/ GIMT_Encode4(43151), // Rule ID 6743 // |
| 11470 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11472 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11473 | // (bitconvert:{ *:[v2i16] } SReg_32:{ *:[v2bf16] }:$src0) => SReg_32:{ *:[v2i16] }:$src0 |
| 11474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11475 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11476 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11477 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11478 | // GIR_Coverage, 6743, |
| 11479 | GIR_EraseRootFromParent_Done, |
| 11480 | // Label 563: @43151 |
| 11481 | GIM_Try, /*On fail goto*//*Label 564*/ GIMT_Encode4(43180), // Rule ID 6744 // |
| 11482 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11484 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11485 | // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[v2i16] }:$src0) => VGPR_32:{ *:[v2bf16] }:$src0 |
| 11486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11487 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11488 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11489 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11490 | // GIR_Coverage, 6744, |
| 11491 | GIR_EraseRootFromParent_Done, |
| 11492 | // Label 564: @43180 |
| 11493 | GIM_Try, /*On fail goto*//*Label 565*/ GIMT_Encode4(43209), // Rule ID 6745 // |
| 11494 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11496 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11497 | // (bitconvert:{ *:[v2i16] } VGPR_32:{ *:[v2bf16] }:$src0) => VGPR_32:{ *:[v2i16] }:$src0 |
| 11498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11499 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11500 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11501 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11502 | // GIR_Coverage, 6745, |
| 11503 | GIR_EraseRootFromParent_Done, |
| 11504 | // Label 565: @43209 |
| 11505 | GIM_Try, /*On fail goto*//*Label 566*/ GIMT_Encode4(43238), // Rule ID 6746 // |
| 11506 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11508 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11509 | // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[v2f16] }:$src0) => SReg_32:{ *:[v2bf16] }:$src0 |
| 11510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11511 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11512 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11513 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11514 | // GIR_Coverage, 6746, |
| 11515 | GIR_EraseRootFromParent_Done, |
| 11516 | // Label 566: @43238 |
| 11517 | GIM_Try, /*On fail goto*//*Label 567*/ GIMT_Encode4(43267), // Rule ID 6747 // |
| 11518 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11520 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11521 | // (bitconvert:{ *:[v2f16] } SReg_32:{ *:[v2bf16] }:$src0) => SReg_32:{ *:[v2f16] }:$src0 |
| 11522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11523 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11524 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11525 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11526 | // GIR_Coverage, 6747, |
| 11527 | GIR_EraseRootFromParent_Done, |
| 11528 | // Label 567: @43267 |
| 11529 | GIM_Try, /*On fail goto*//*Label 568*/ GIMT_Encode4(43296), // Rule ID 6748 // |
| 11530 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11532 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11533 | // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[v2f16] }:$src0) => VGPR_32:{ *:[v2bf16] }:$src0 |
| 11534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11535 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11536 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11537 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11538 | // GIR_Coverage, 6748, |
| 11539 | GIR_EraseRootFromParent_Done, |
| 11540 | // Label 568: @43296 |
| 11541 | GIM_Try, /*On fail goto*//*Label 569*/ GIMT_Encode4(43325), // Rule ID 6749 // |
| 11542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 11543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11544 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11545 | // (bitconvert:{ *:[v2f16] } VGPR_32:{ *:[v2bf16] }:$src0) => VGPR_32:{ *:[v2f16] }:$src0 |
| 11546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11547 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11548 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11549 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11550 | // GIR_Coverage, 6749, |
| 11551 | GIR_EraseRootFromParent_Done, |
| 11552 | // Label 569: @43325 |
| 11553 | GIM_Try, /*On fail goto*//*Label 570*/ GIMT_Encode4(43354), // Rule ID 6751 // |
| 11554 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11557 | // (bitconvert:{ *:[v2bf16] } VGPR_32:{ *:[f32] }:$src0) => VGPR_32:{ *:[v2bf16] }:$src0 |
| 11558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11559 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11560 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11561 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 11562 | // GIR_Coverage, 6751, |
| 11563 | GIR_EraseRootFromParent_Done, |
| 11564 | // Label 570: @43354 |
| 11565 | GIM_Try, /*On fail goto*//*Label 571*/ GIMT_Encode4(43383), // Rule ID 6753 // |
| 11566 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 11567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11568 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11569 | // (bitconvert:{ *:[v2bf16] } SReg_32:{ *:[f32] }:$src0) => SReg_32:{ *:[v2bf16] }:$src0 |
| 11570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11571 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11572 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11573 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 11574 | // GIR_Coverage, 6753, |
| 11575 | GIR_EraseRootFromParent_Done, |
| 11576 | // Label 571: @43383 |
| 11577 | GIM_Reject, |
| 11578 | // Label 494: @43384 |
| 11579 | GIM_Try, /*On fail goto*//*Label 572*/ GIMT_Encode4(43413), // Rule ID 6756 // |
| 11580 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11582 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11583 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11585 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11586 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11587 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11588 | // GIR_Coverage, 6756, |
| 11589 | GIR_EraseRootFromParent_Done, |
| 11590 | // Label 572: @43413 |
| 11591 | GIM_Try, /*On fail goto*//*Label 573*/ GIMT_Encode4(43442), // Rule ID 6757 // |
| 11592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 11593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11594 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11595 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11597 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11598 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11599 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11600 | // GIR_Coverage, 6757, |
| 11601 | GIR_EraseRootFromParent_Done, |
| 11602 | // Label 573: @43442 |
| 11603 | GIM_Try, /*On fail goto*//*Label 574*/ GIMT_Encode4(43471), // Rule ID 6759 // |
| 11604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11607 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11609 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11610 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11611 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11612 | // GIR_Coverage, 6759, |
| 11613 | GIR_EraseRootFromParent_Done, |
| 11614 | // Label 574: @43471 |
| 11615 | GIM_Try, /*On fail goto*//*Label 575*/ GIMT_Encode4(43500), // Rule ID 6761 // |
| 11616 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11619 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11621 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11622 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11623 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11624 | // GIR_Coverage, 6761, |
| 11625 | GIR_EraseRootFromParent_Done, |
| 11626 | // Label 575: @43500 |
| 11627 | GIM_Try, /*On fail goto*//*Label 576*/ GIMT_Encode4(43529), // Rule ID 6763 // |
| 11628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11630 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11631 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11633 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11634 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11635 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11636 | // GIR_Coverage, 6763, |
| 11637 | GIR_EraseRootFromParent_Done, |
| 11638 | // Label 576: @43529 |
| 11639 | GIM_Try, /*On fail goto*//*Label 577*/ GIMT_Encode4(43558), // Rule ID 6765 // |
| 11640 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 11641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11642 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11643 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11645 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11646 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11647 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11648 | // GIR_Coverage, 6765, |
| 11649 | GIR_EraseRootFromParent_Done, |
| 11650 | // Label 577: @43558 |
| 11651 | GIM_Try, /*On fail goto*//*Label 578*/ GIMT_Encode4(43587), // Rule ID 6769 // |
| 11652 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11654 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11655 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11657 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11658 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11659 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11660 | // GIR_Coverage, 6769, |
| 11661 | GIR_EraseRootFromParent_Done, |
| 11662 | // Label 578: @43587 |
| 11663 | GIM_Try, /*On fail goto*//*Label 579*/ GIMT_Encode4(43616), // Rule ID 6777 // |
| 11664 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11666 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11667 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11669 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11670 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11671 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11672 | // GIR_Coverage, 6777, |
| 11673 | GIR_EraseRootFromParent_Done, |
| 11674 | // Label 579: @43616 |
| 11675 | GIM_Try, /*On fail goto*//*Label 580*/ GIMT_Encode4(43645), // Rule ID 6780 // |
| 11676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11679 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11681 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11682 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11683 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11684 | // GIR_Coverage, 6780, |
| 11685 | GIR_EraseRootFromParent_Done, |
| 11686 | // Label 580: @43645 |
| 11687 | GIM_Try, /*On fail goto*//*Label 581*/ GIMT_Encode4(43674), // Rule ID 6782 // |
| 11688 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11690 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11691 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11693 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11694 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11695 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11696 | // GIR_Coverage, 6782, |
| 11697 | GIR_EraseRootFromParent_Done, |
| 11698 | // Label 581: @43674 |
| 11699 | GIM_Try, /*On fail goto*//*Label 582*/ GIMT_Encode4(43703), // Rule ID 6783 // |
| 11700 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11702 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11703 | // (bitconvert:{ *:[v2i32] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[v2i32] }:$src0 |
| 11704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11705 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11706 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11707 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11708 | // GIR_Coverage, 6783, |
| 11709 | GIR_EraseRootFromParent_Done, |
| 11710 | // Label 582: @43703 |
| 11711 | GIM_Try, /*On fail goto*//*Label 583*/ GIMT_Encode4(43732), // Rule ID 6785 // |
| 11712 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11715 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11717 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11718 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11719 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11720 | // GIR_Coverage, 6785, |
| 11721 | GIR_EraseRootFromParent_Done, |
| 11722 | // Label 583: @43732 |
| 11723 | GIM_Try, /*On fail goto*//*Label 584*/ GIMT_Encode4(43761), // Rule ID 6787 // |
| 11724 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 11725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11727 | // (bitconvert:{ *:[v2f32] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[v2f32] }:$src0 |
| 11728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11729 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11730 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11731 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 11732 | // GIR_Coverage, 6787, |
| 11733 | GIR_EraseRootFromParent_Done, |
| 11734 | // Label 584: @43761 |
| 11735 | GIM_Reject, |
| 11736 | // Label 495: @43762 |
| 11737 | GIM_Try, /*On fail goto*//*Label 585*/ GIMT_Encode4(43791), // Rule ID 6801 // |
| 11738 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11741 | // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$src0) => SReg_128:{ *:[v2i64] }:$src0 |
| 11742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11743 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11744 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11745 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11746 | // GIR_Coverage, 6801, |
| 11747 | GIR_EraseRootFromParent_Done, |
| 11748 | // Label 585: @43791 |
| 11749 | GIM_Try, /*On fail goto*//*Label 586*/ GIMT_Encode4(43820), // Rule ID 6803 // |
| 11750 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11753 | // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v2f64] }:$src0 |
| 11754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11755 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11756 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11757 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11758 | // GIR_Coverage, 6803, |
| 11759 | GIR_EraseRootFromParent_Done, |
| 11760 | // Label 586: @43820 |
| 11761 | GIM_Try, /*On fail goto*//*Label 587*/ GIMT_Encode4(43849), // Rule ID 6804 // |
| 11762 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11764 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11765 | // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v4i32] }:$src0) => VReg_128:{ *:[v2f64] }:$src0 |
| 11766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11767 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11768 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11769 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11770 | // GIR_Coverage, 6804, |
| 11771 | GIR_EraseRootFromParent_Done, |
| 11772 | // Label 587: @43849 |
| 11773 | GIM_Try, /*On fail goto*//*Label 588*/ GIMT_Encode4(43878), // Rule ID 6807 // |
| 11774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11777 | // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v2f64] }:$src0) => VReg_128:{ *:[v2i64] }:$src0 |
| 11778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11779 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11780 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11781 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11782 | // GIR_Coverage, 6807, |
| 11783 | GIR_EraseRootFromParent_Done, |
| 11784 | // Label 588: @43878 |
| 11785 | GIM_Try, /*On fail goto*//*Label 589*/ GIMT_Encode4(43907), // Rule ID 6808 // |
| 11786 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 11787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11788 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11789 | // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v2i64] }:$src0) => VReg_128:{ *:[v2f64] }:$src0 |
| 11790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11791 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11792 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11793 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11794 | // GIR_Coverage, 6808, |
| 11795 | GIR_EraseRootFromParent_Done, |
| 11796 | // Label 589: @43907 |
| 11797 | GIM_Try, /*On fail goto*//*Label 590*/ GIMT_Encode4(43936), // Rule ID 6810 // |
| 11798 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 11799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11800 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11801 | // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v2i64] }:$src0 |
| 11802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11803 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11804 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11805 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11806 | // GIR_Coverage, 6810, |
| 11807 | GIR_EraseRootFromParent_Done, |
| 11808 | // Label 590: @43936 |
| 11809 | GIM_Try, /*On fail goto*//*Label 591*/ GIMT_Encode4(43965), // Rule ID 6827 // |
| 11810 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11813 | // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8i16] }:$src0) => SReg_128:{ *:[v2i64] }:$src0 |
| 11814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11815 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11816 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11817 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11818 | // GIR_Coverage, 6827, |
| 11819 | GIR_EraseRootFromParent_Done, |
| 11820 | // Label 591: @43965 |
| 11821 | GIM_Try, /*On fail goto*//*Label 592*/ GIMT_Encode4(43994), // Rule ID 6828 // |
| 11822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11825 | // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8i16] }:$src0) => SReg_128:{ *:[v2f64] }:$src0 |
| 11826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11827 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11828 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11829 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11830 | // GIR_Coverage, 6828, |
| 11831 | GIR_EraseRootFromParent_Done, |
| 11832 | // Label 592: @43994 |
| 11833 | GIM_Try, /*On fail goto*//*Label 593*/ GIMT_Encode4(44023), // Rule ID 6829 // |
| 11834 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11837 | // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8f16] }:$src0) => SReg_128:{ *:[v2i64] }:$src0 |
| 11838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11839 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11840 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11841 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11842 | // GIR_Coverage, 6829, |
| 11843 | GIR_EraseRootFromParent_Done, |
| 11844 | // Label 593: @44023 |
| 11845 | GIM_Try, /*On fail goto*//*Label 594*/ GIMT_Encode4(44052), // Rule ID 6830 // |
| 11846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11849 | // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8f16] }:$src0) => SReg_128:{ *:[v2f64] }:$src0 |
| 11850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11851 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11852 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11853 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11854 | // GIR_Coverage, 6830, |
| 11855 | GIR_EraseRootFromParent_Done, |
| 11856 | // Label 594: @44052 |
| 11857 | GIM_Try, /*On fail goto*//*Label 595*/ GIMT_Encode4(44081), // Rule ID 6847 // |
| 11858 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11860 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11861 | // (bitconvert:{ *:[v2f64] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v2f64] }:$src0 |
| 11862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11863 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11864 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11865 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11866 | // GIR_Coverage, 6847, |
| 11867 | GIR_EraseRootFromParent_Done, |
| 11868 | // Label 595: @44081 |
| 11869 | GIM_Try, /*On fail goto*//*Label 596*/ GIMT_Encode4(44110), // Rule ID 6849 // |
| 11870 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11872 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11873 | // (bitconvert:{ *:[v2f64] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v2f64] }:$src0 |
| 11874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11875 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11876 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11877 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11878 | // GIR_Coverage, 6849, |
| 11879 | GIR_EraseRootFromParent_Done, |
| 11880 | // Label 596: @44110 |
| 11881 | GIM_Try, /*On fail goto*//*Label 597*/ GIMT_Encode4(44139), // Rule ID 6851 // |
| 11882 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11884 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11885 | // (bitconvert:{ *:[v2i64] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v2i64] }:$src0 |
| 11886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11887 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11888 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11889 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 11890 | // GIR_Coverage, 6851, |
| 11891 | GIR_EraseRootFromParent_Done, |
| 11892 | // Label 597: @44139 |
| 11893 | GIM_Try, /*On fail goto*//*Label 598*/ GIMT_Encode4(44168), // Rule ID 6853 // |
| 11894 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 11895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11896 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11897 | // (bitconvert:{ *:[v2i64] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v2i64] }:$src0 |
| 11898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11899 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11900 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11901 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 11902 | // GIR_Coverage, 6853, |
| 11903 | GIR_EraseRootFromParent_Done, |
| 11904 | // Label 598: @44168 |
| 11905 | GIM_Reject, |
| 11906 | // Label 496: @44169 |
| 11907 | GIM_Try, /*On fail goto*//*Label 599*/ GIMT_Encode4(44222), |
| 11908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s32, |
| 11909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID), |
| 11910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SGPR_96RegClassID), |
| 11911 | GIM_Try, /*On fail goto*//*Label 600*/ GIMT_Encode4(44203), // Rule ID 6799 // |
| 11912 | // (bitconvert:{ *:[v3i32] } SGPR_96:{ *:[v3f32] }:$src0) => SGPR_96:{ *:[v3i32] }:$src0 |
| 11913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11914 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11915 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11916 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID), |
| 11917 | // GIR_Coverage, 6799, |
| 11918 | GIR_EraseRootFromParent_Done, |
| 11919 | // Label 600: @44203 |
| 11920 | GIM_Try, /*On fail goto*//*Label 601*/ GIMT_Encode4(44221), // Rule ID 6800 // |
| 11921 | // (bitconvert:{ *:[v3f32] } SGPR_96:{ *:[v3i32] }:$src0) => SGPR_96:{ *:[v3f32] }:$src0 |
| 11922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11923 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11924 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11925 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SGPR_96RegClassID), |
| 11926 | // GIR_Coverage, 6800, |
| 11927 | GIR_EraseRootFromParent_Done, |
| 11928 | // Label 601: @44221 |
| 11929 | GIM_Reject, |
| 11930 | // Label 599: @44222 |
| 11931 | GIM_Reject, |
| 11932 | // Label 497: @44223 |
| 11933 | GIM_Try, /*On fail goto*//*Label 602*/ GIMT_Encode4(44252), // Rule ID 6863 // |
| 11934 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 11935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11936 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11937 | // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v3f64] }:$src0) => VReg_192:{ *:[v3i64] }:$src0 |
| 11938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11939 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11940 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11941 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11942 | // GIR_Coverage, 6863, |
| 11943 | GIR_EraseRootFromParent_Done, |
| 11944 | // Label 602: @44252 |
| 11945 | GIM_Try, /*On fail goto*//*Label 603*/ GIMT_Encode4(44281), // Rule ID 6864 // |
| 11946 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 11947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11948 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11949 | // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v3i64] }:$src0) => VReg_192:{ *:[v3f64] }:$src0 |
| 11950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11951 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11952 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11953 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11954 | // GIR_Coverage, 6864, |
| 11955 | GIR_EraseRootFromParent_Done, |
| 11956 | // Label 603: @44281 |
| 11957 | GIM_Try, /*On fail goto*//*Label 604*/ GIMT_Encode4(44310), // Rule ID 6865 // |
| 11958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 11959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11960 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11961 | // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6i32] }:$src0) => VReg_192:{ *:[v3i64] }:$src0 |
| 11962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11963 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11964 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11965 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11966 | // GIR_Coverage, 6865, |
| 11967 | GIR_EraseRootFromParent_Done, |
| 11968 | // Label 604: @44310 |
| 11969 | GIM_Try, /*On fail goto*//*Label 605*/ GIMT_Encode4(44339), // Rule ID 6866 // |
| 11970 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 11971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11972 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11973 | // (bitconvert:{ *:[v3i64] } VReg_192:{ *:[v6f32] }:$src0) => VReg_192:{ *:[v3i64] }:$src0 |
| 11974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11975 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11976 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11977 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11978 | // GIR_Coverage, 6866, |
| 11979 | GIR_EraseRootFromParent_Done, |
| 11980 | // Label 605: @44339 |
| 11981 | GIM_Try, /*On fail goto*//*Label 606*/ GIMT_Encode4(44368), // Rule ID 6867 // |
| 11982 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 11983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11984 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11985 | // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6i32] }:$src0) => VReg_192:{ *:[v3f64] }:$src0 |
| 11986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11987 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 11988 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 11989 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11990 | // GIR_Coverage, 6867, |
| 11991 | GIR_EraseRootFromParent_Done, |
| 11992 | // Label 606: @44368 |
| 11993 | GIM_Try, /*On fail goto*//*Label 607*/ GIMT_Encode4(44397), // Rule ID 6868 // |
| 11994 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 11995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11996 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 11997 | // (bitconvert:{ *:[v3f64] } VReg_192:{ *:[v6f32] }:$src0) => VReg_192:{ *:[v3f64] }:$src0 |
| 11998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 11999 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12000 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12001 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12002 | // GIR_Coverage, 6868, |
| 12003 | GIR_EraseRootFromParent_Done, |
| 12004 | // Label 607: @44397 |
| 12005 | GIM_Reject, |
| 12006 | // Label 498: @44398 |
| 12007 | GIM_Try, /*On fail goto*//*Label 608*/ GIMT_Encode4(44427), // Rule ID 6766 // |
| 12008 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12010 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12011 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12013 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12014 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12015 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12016 | // GIR_Coverage, 6766, |
| 12017 | GIR_EraseRootFromParent_Done, |
| 12018 | // Label 608: @44427 |
| 12019 | GIM_Try, /*On fail goto*//*Label 609*/ GIMT_Encode4(44456), // Rule ID 6767 // |
| 12020 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12022 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12023 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12025 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12026 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12027 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12028 | // GIR_Coverage, 6767, |
| 12029 | GIR_EraseRootFromParent_Done, |
| 12030 | // Label 609: @44456 |
| 12031 | GIM_Try, /*On fail goto*//*Label 610*/ GIMT_Encode4(44485), // Rule ID 6768 // |
| 12032 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12034 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12035 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12037 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12038 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12039 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12040 | // GIR_Coverage, 6768, |
| 12041 | GIR_EraseRootFromParent_Done, |
| 12042 | // Label 610: @44485 |
| 12043 | GIM_Try, /*On fail goto*//*Label 611*/ GIMT_Encode4(44514), // Rule ID 6770 // |
| 12044 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12046 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12047 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12049 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12050 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12051 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12052 | // GIR_Coverage, 6770, |
| 12053 | GIR_EraseRootFromParent_Done, |
| 12054 | // Label 611: @44514 |
| 12055 | GIM_Try, /*On fail goto*//*Label 612*/ GIMT_Encode4(44543), // Rule ID 6772 // |
| 12056 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12058 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12059 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v4i16] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12061 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12062 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12063 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12064 | // GIR_Coverage, 6772, |
| 12065 | GIR_EraseRootFromParent_Done, |
| 12066 | // Label 612: @44543 |
| 12067 | GIM_Try, /*On fail goto*//*Label 613*/ GIMT_Encode4(44572), // Rule ID 6773 // |
| 12068 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12070 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12071 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12073 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12074 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12075 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12076 | // GIR_Coverage, 6773, |
| 12077 | GIR_EraseRootFromParent_Done, |
| 12078 | // Label 613: @44572 |
| 12079 | GIM_Try, /*On fail goto*//*Label 614*/ GIMT_Encode4(44601), // Rule ID 6774 // |
| 12080 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12082 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12083 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v4f16] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12085 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12086 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12087 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12088 | // GIR_Coverage, 6774, |
| 12089 | GIR_EraseRootFromParent_Done, |
| 12090 | // Label 614: @44601 |
| 12091 | GIM_Try, /*On fail goto*//*Label 615*/ GIMT_Encode4(44630), // Rule ID 6775 // |
| 12092 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s16, |
| 12093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12095 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v4bf16] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12097 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12098 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12099 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12100 | // GIR_Coverage, 6775, |
| 12101 | GIR_EraseRootFromParent_Done, |
| 12102 | // Label 615: @44630 |
| 12103 | GIM_Try, /*On fail goto*//*Label 616*/ GIMT_Encode4(44659), // Rule ID 6776 // |
| 12104 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12107 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12109 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12110 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12111 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12112 | // GIR_Coverage, 6776, |
| 12113 | GIR_EraseRootFromParent_Done, |
| 12114 | // Label 616: @44659 |
| 12115 | GIM_Try, /*On fail goto*//*Label 617*/ GIMT_Encode4(44688), // Rule ID 6778 // |
| 12116 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12118 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12119 | // (bitconvert:{ *:[v4bf16] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[v4bf16] }:$src0 |
| 12120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12121 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12122 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12123 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12124 | // GIR_Coverage, 6778, |
| 12125 | GIR_EraseRootFromParent_Done, |
| 12126 | // Label 617: @44688 |
| 12127 | GIM_Try, /*On fail goto*//*Label 618*/ GIMT_Encode4(44717), // Rule ID 6781 // |
| 12128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12131 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12133 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12134 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12135 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12136 | // GIR_Coverage, 6781, |
| 12137 | GIR_EraseRootFromParent_Done, |
| 12138 | // Label 618: @44717 |
| 12139 | GIM_Try, /*On fail goto*//*Label 619*/ GIMT_Encode4(44746), // Rule ID 6784 // |
| 12140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12143 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2i32] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12145 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12146 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12147 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12148 | // GIR_Coverage, 6784, |
| 12149 | GIR_EraseRootFromParent_Done, |
| 12150 | // Label 619: @44746 |
| 12151 | GIM_Try, /*On fail goto*//*Label 620*/ GIMT_Encode4(44775), // Rule ID 6786 // |
| 12152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12155 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12157 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12158 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12159 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12160 | // GIR_Coverage, 6786, |
| 12161 | GIR_EraseRootFromParent_Done, |
| 12162 | // Label 620: @44775 |
| 12163 | GIM_Try, /*On fail goto*//*Label 621*/ GIMT_Encode4(44804), // Rule ID 6788 // |
| 12164 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 12165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12167 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[v2f32] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12169 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12170 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12171 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12172 | // GIR_Coverage, 6788, |
| 12173 | GIR_EraseRootFromParent_Done, |
| 12174 | // Label 621: @44804 |
| 12175 | GIM_Try, /*On fail goto*//*Label 622*/ GIMT_Encode4(44833), // Rule ID 6789 // |
| 12176 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12179 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12181 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12182 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12183 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12184 | // GIR_Coverage, 6789, |
| 12185 | GIR_EraseRootFromParent_Done, |
| 12186 | // Label 622: @44833 |
| 12187 | GIM_Try, /*On fail goto*//*Label 623*/ GIMT_Encode4(44862), // Rule ID 6790 // |
| 12188 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12191 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[f64] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12193 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12194 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12195 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12196 | // GIR_Coverage, 6790, |
| 12197 | GIR_EraseRootFromParent_Done, |
| 12198 | // Label 623: @44862 |
| 12199 | GIM_Try, /*On fail goto*//*Label 624*/ GIMT_Encode4(44891), // Rule ID 6793 // |
| 12200 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12202 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12203 | // (bitconvert:{ *:[v4i16] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[v4i16] }:$src0 |
| 12204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12205 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12206 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12207 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12208 | // GIR_Coverage, 6793, |
| 12209 | GIR_EraseRootFromParent_Done, |
| 12210 | // Label 624: @44891 |
| 12211 | GIM_Try, /*On fail goto*//*Label 625*/ GIMT_Encode4(44920), // Rule ID 6794 // |
| 12212 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 12213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12215 | // (bitconvert:{ *:[v4f16] } VReg_64:{ *:[i64] }:$src0) => VReg_64:{ *:[v4f16] }:$src0 |
| 12216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12217 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12218 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12219 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 12220 | // GIR_Coverage, 6794, |
| 12221 | GIR_EraseRootFromParent_Done, |
| 12222 | // Label 625: @44920 |
| 12223 | GIM_Reject, |
| 12224 | // Label 499: @44921 |
| 12225 | GIM_Try, /*On fail goto*//*Label 626*/ GIMT_Encode4(44950), // Rule ID 6797 // |
| 12226 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12227 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12228 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12229 | // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v4i32] }:$src0 |
| 12230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12231 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12232 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12233 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12234 | // GIR_Coverage, 6797, |
| 12235 | GIR_EraseRootFromParent_Done, |
| 12236 | // Label 626: @44950 |
| 12237 | GIM_Try, /*On fail goto*//*Label 627*/ GIMT_Encode4(44979), // Rule ID 6798 // |
| 12238 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12240 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12241 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v4i32] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12243 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12244 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12245 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12246 | // GIR_Coverage, 6798, |
| 12247 | GIR_EraseRootFromParent_Done, |
| 12248 | // Label 627: @44979 |
| 12249 | GIM_Try, /*On fail goto*//*Label 628*/ GIMT_Encode4(45008), // Rule ID 6802 // |
| 12250 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12252 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12253 | // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v2i64] }:$src0) => SReg_128:{ *:[v4i32] }:$src0 |
| 12254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12255 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12256 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12257 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12258 | // GIR_Coverage, 6802, |
| 12259 | GIR_EraseRootFromParent_Done, |
| 12260 | // Label 628: @45008 |
| 12261 | GIM_Try, /*On fail goto*//*Label 629*/ GIMT_Encode4(45037), // Rule ID 6805 // |
| 12262 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12264 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12265 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2f64] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12267 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12268 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12269 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12270 | // GIR_Coverage, 6805, |
| 12271 | GIR_EraseRootFromParent_Done, |
| 12272 | // Label 629: @45037 |
| 12273 | GIM_Try, /*On fail goto*//*Label 630*/ GIMT_Encode4(45066), // Rule ID 6806 // |
| 12274 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12276 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12277 | // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v2f64] }:$src0) => VReg_128:{ *:[v4i32] }:$src0 |
| 12278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12279 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12280 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12281 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12282 | // GIR_Coverage, 6806, |
| 12283 | GIR_EraseRootFromParent_Done, |
| 12284 | // Label 630: @45066 |
| 12285 | GIM_Try, /*On fail goto*//*Label 631*/ GIMT_Encode4(45095), // Rule ID 6809 // |
| 12286 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12288 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12289 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v2i64] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12291 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12292 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12293 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12294 | // GIR_Coverage, 6809, |
| 12295 | GIR_EraseRootFromParent_Done, |
| 12296 | // Label 631: @45095 |
| 12297 | GIM_Try, /*On fail goto*//*Label 632*/ GIMT_Encode4(45124), // Rule ID 6812 // |
| 12298 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12300 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12301 | // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8i16] }:$src0) => SReg_128:{ *:[v4i32] }:$src0 |
| 12302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12303 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12304 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12305 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12306 | // GIR_Coverage, 6812, |
| 12307 | GIR_EraseRootFromParent_Done, |
| 12308 | // Label 632: @45124 |
| 12309 | GIM_Try, /*On fail goto*//*Label 633*/ GIMT_Encode4(45153), // Rule ID 6815 // |
| 12310 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12312 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12313 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8f16] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12315 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12316 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12317 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12318 | // GIR_Coverage, 6815, |
| 12319 | GIR_EraseRootFromParent_Done, |
| 12320 | // Label 633: @45153 |
| 12321 | GIM_Try, /*On fail goto*//*Label 634*/ GIMT_Encode4(45182), // Rule ID 6816 // |
| 12322 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12323 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12324 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12325 | // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8f16] }:$src0) => VReg_128:{ *:[v4i32] }:$src0 |
| 12326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12327 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12328 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12329 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12330 | // GIR_Coverage, 6816, |
| 12331 | GIR_EraseRootFromParent_Done, |
| 12332 | // Label 634: @45182 |
| 12333 | GIM_Try, /*On fail goto*//*Label 635*/ GIMT_Encode4(45211), // Rule ID 6819 // |
| 12334 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12337 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8i16] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12339 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12340 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12341 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12342 | // GIR_Coverage, 6819, |
| 12343 | GIR_EraseRootFromParent_Done, |
| 12344 | // Label 635: @45211 |
| 12345 | GIM_Try, /*On fail goto*//*Label 636*/ GIMT_Encode4(45240), // Rule ID 6831 // |
| 12346 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12348 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12349 | // (bitconvert:{ *:[v4i32] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v4i32] }:$src0 |
| 12350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12351 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12352 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12353 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12354 | // GIR_Coverage, 6831, |
| 12355 | GIR_EraseRootFromParent_Done, |
| 12356 | // Label 636: @45240 |
| 12357 | GIM_Try, /*On fail goto*//*Label 637*/ GIMT_Encode4(45269), // Rule ID 6833 // |
| 12358 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12360 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12361 | // (bitconvert:{ *:[v4i32] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v4i32] }:$src0 |
| 12362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12363 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12364 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12365 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12366 | // GIR_Coverage, 6833, |
| 12367 | GIR_EraseRootFromParent_Done, |
| 12368 | // Label 637: @45269 |
| 12369 | GIM_Try, /*On fail goto*//*Label 638*/ GIMT_Encode4(45298), // Rule ID 6835 // |
| 12370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12373 | // (bitconvert:{ *:[v4f32] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v4f32] }:$src0 |
| 12374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12375 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12376 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12377 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12378 | // GIR_Coverage, 6835, |
| 12379 | GIR_EraseRootFromParent_Done, |
| 12380 | // Label 638: @45298 |
| 12381 | GIM_Try, /*On fail goto*//*Label 639*/ GIMT_Encode4(45327), // Rule ID 6837 // |
| 12382 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12384 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12385 | // (bitconvert:{ *:[v4f32] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v4f32] }:$src0 |
| 12386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12387 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12388 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12389 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12390 | // GIR_Coverage, 6837, |
| 12391 | GIR_EraseRootFromParent_Done, |
| 12392 | // Label 639: @45327 |
| 12393 | GIM_Reject, |
| 12394 | // Label 500: @45328 |
| 12395 | GIM_Try, /*On fail goto*//*Label 640*/ GIMT_Encode4(45357), // Rule ID 6881 // |
| 12396 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 12397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12398 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12399 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12401 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12402 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12403 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12404 | // GIR_Coverage, 6881, |
| 12405 | GIR_EraseRootFromParent_Done, |
| 12406 | // Label 640: @45357 |
| 12407 | GIM_Try, /*On fail goto*//*Label 641*/ GIMT_Encode4(45386), // Rule ID 6882 // |
| 12408 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 12409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12410 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12411 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12413 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12414 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12415 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12416 | // GIR_Coverage, 6882, |
| 12417 | GIR_EraseRootFromParent_Done, |
| 12418 | // Label 641: @45386 |
| 12419 | GIM_Try, /*On fail goto*//*Label 642*/ GIMT_Encode4(45415), // Rule ID 6883 // |
| 12420 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 12421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12422 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12423 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12425 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12426 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12427 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12428 | // GIR_Coverage, 6883, |
| 12429 | GIR_EraseRootFromParent_Done, |
| 12430 | // Label 642: @45415 |
| 12431 | GIM_Try, /*On fail goto*//*Label 643*/ GIMT_Encode4(45444), // Rule ID 6884 // |
| 12432 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 12433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12435 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12437 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12438 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12439 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12440 | // GIR_Coverage, 6884, |
| 12441 | GIR_EraseRootFromParent_Done, |
| 12442 | // Label 643: @45444 |
| 12443 | GIM_Try, /*On fail goto*//*Label 644*/ GIMT_Encode4(45473), // Rule ID 6885 // |
| 12444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 12445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12446 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12447 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12449 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12450 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12451 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12452 | // GIR_Coverage, 6885, |
| 12453 | GIR_EraseRootFromParent_Done, |
| 12454 | // Label 644: @45473 |
| 12455 | GIM_Try, /*On fail goto*//*Label 645*/ GIMT_Encode4(45502), // Rule ID 6886 // |
| 12456 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 12457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12458 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12459 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12461 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12462 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12463 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12464 | // GIR_Coverage, 6886, |
| 12465 | GIR_EraseRootFromParent_Done, |
| 12466 | // Label 645: @45502 |
| 12467 | GIM_Try, /*On fail goto*//*Label 646*/ GIMT_Encode4(45531), // Rule ID 6907 // |
| 12468 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12471 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12473 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12474 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12475 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12476 | // GIR_Coverage, 6907, |
| 12477 | GIR_EraseRootFromParent_Done, |
| 12478 | // Label 646: @45531 |
| 12479 | GIM_Try, /*On fail goto*//*Label 647*/ GIMT_Encode4(45560), // Rule ID 6908 // |
| 12480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12482 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12483 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12485 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12486 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12487 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12488 | // GIR_Coverage, 6908, |
| 12489 | GIR_EraseRootFromParent_Done, |
| 12490 | // Label 647: @45560 |
| 12491 | GIM_Try, /*On fail goto*//*Label 648*/ GIMT_Encode4(45589), // Rule ID 6909 // |
| 12492 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12494 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12495 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12497 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12498 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12499 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12500 | // GIR_Coverage, 6909, |
| 12501 | GIR_EraseRootFromParent_Done, |
| 12502 | // Label 648: @45589 |
| 12503 | GIM_Try, /*On fail goto*//*Label 649*/ GIMT_Encode4(45618), // Rule ID 6910 // |
| 12504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12506 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12507 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12509 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12510 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12511 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12512 | // GIR_Coverage, 6910, |
| 12513 | GIR_EraseRootFromParent_Done, |
| 12514 | // Label 649: @45618 |
| 12515 | GIM_Try, /*On fail goto*//*Label 650*/ GIMT_Encode4(45647), // Rule ID 6915 // |
| 12516 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12518 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12519 | // (bitconvert:{ *:[v4i64] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v4i64] }:$src0 |
| 12520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12521 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12522 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12523 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12524 | // GIR_Coverage, 6915, |
| 12525 | GIR_EraseRootFromParent_Done, |
| 12526 | // Label 650: @45647 |
| 12527 | GIM_Try, /*On fail goto*//*Label 651*/ GIMT_Encode4(45676), // Rule ID 6917 // |
| 12528 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 12529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12530 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12531 | // (bitconvert:{ *:[v4f64] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v4f64] }:$src0 |
| 12532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12533 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12534 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12535 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 12536 | // GIR_Coverage, 6917, |
| 12537 | GIR_EraseRootFromParent_Done, |
| 12538 | // Label 651: @45676 |
| 12539 | GIM_Reject, |
| 12540 | // Label 501: @45677 |
| 12541 | GIM_Try, /*On fail goto*//*Label 652*/ GIMT_Encode4(45790), |
| 12542 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v5s32, |
| 12543 | GIM_Try, /*On fail goto*//*Label 653*/ GIMT_Encode4(45711), // Rule ID 6855 // |
| 12544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12546 | // (bitconvert:{ *:[v5i32] } SReg_160:{ *:[v5f32] }:$src0) => SReg_160:{ *:[v5i32] }:$src0 |
| 12547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12548 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12549 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12550 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12551 | // GIR_Coverage, 6855, |
| 12552 | GIR_EraseRootFromParent_Done, |
| 12553 | // Label 653: @45711 |
| 12554 | GIM_Try, /*On fail goto*//*Label 654*/ GIMT_Encode4(45737), // Rule ID 6856 // |
| 12555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12557 | // (bitconvert:{ *:[v5f32] } SReg_160:{ *:[v5i32] }:$src0) => SReg_160:{ *:[v5f32] }:$src0 |
| 12558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12559 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12560 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12561 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_160RegClassID), |
| 12562 | // GIR_Coverage, 6856, |
| 12563 | GIR_EraseRootFromParent_Done, |
| 12564 | // Label 654: @45737 |
| 12565 | GIM_Try, /*On fail goto*//*Label 655*/ GIMT_Encode4(45763), // Rule ID 6857 // |
| 12566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12567 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12568 | // (bitconvert:{ *:[v5i32] } VReg_160:{ *:[v5f32] }:$src0) => VReg_160:{ *:[v5i32] }:$src0 |
| 12569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12570 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12571 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12572 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12573 | // GIR_Coverage, 6857, |
| 12574 | GIR_EraseRootFromParent_Done, |
| 12575 | // Label 655: @45763 |
| 12576 | GIM_Try, /*On fail goto*//*Label 656*/ GIMT_Encode4(45789), // Rule ID 6858 // |
| 12577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12578 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12579 | // (bitconvert:{ *:[v5f32] } VReg_160:{ *:[v5i32] }:$src0) => VReg_160:{ *:[v5f32] }:$src0 |
| 12580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12581 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12582 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12583 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_160RegClassID), |
| 12584 | // GIR_Coverage, 6858, |
| 12585 | GIR_EraseRootFromParent_Done, |
| 12586 | // Label 656: @45789 |
| 12587 | GIM_Reject, |
| 12588 | // Label 652: @45790 |
| 12589 | GIM_Reject, |
| 12590 | // Label 502: @45791 |
| 12591 | GIM_Try, /*On fail goto*//*Label 657*/ GIMT_Encode4(45820), // Rule ID 6859 // |
| 12592 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 12593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12594 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12595 | // (bitconvert:{ *:[v6i32] } SReg_192:{ *:[v6f32] }:$src0) => SReg_192:{ *:[v6i32] }:$src0 |
| 12596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12597 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12598 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12599 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12600 | // GIR_Coverage, 6859, |
| 12601 | GIR_EraseRootFromParent_Done, |
| 12602 | // Label 657: @45820 |
| 12603 | GIM_Try, /*On fail goto*//*Label 658*/ GIMT_Encode4(45849), // Rule ID 6860 // |
| 12604 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 12605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12606 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12607 | // (bitconvert:{ *:[v6f32] } SReg_192:{ *:[v6i32] }:$src0) => SReg_192:{ *:[v6f32] }:$src0 |
| 12608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12609 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12610 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12611 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_192RegClassID), |
| 12612 | // GIR_Coverage, 6860, |
| 12613 | GIR_EraseRootFromParent_Done, |
| 12614 | // Label 658: @45849 |
| 12615 | GIM_Try, /*On fail goto*//*Label 659*/ GIMT_Encode4(45878), // Rule ID 6861 // |
| 12616 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 12617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12619 | // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v6f32] }:$src0) => VReg_192:{ *:[v6i32] }:$src0 |
| 12620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12621 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12622 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12623 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12624 | // GIR_Coverage, 6861, |
| 12625 | GIR_EraseRootFromParent_Done, |
| 12626 | // Label 659: @45878 |
| 12627 | GIM_Try, /*On fail goto*//*Label 660*/ GIMT_Encode4(45907), // Rule ID 6862 // |
| 12628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v6s32, |
| 12629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12630 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12631 | // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v6i32] }:$src0) => VReg_192:{ *:[v6f32] }:$src0 |
| 12632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12633 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12634 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12635 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12636 | // GIR_Coverage, 6862, |
| 12637 | GIR_EraseRootFromParent_Done, |
| 12638 | // Label 660: @45907 |
| 12639 | GIM_Try, /*On fail goto*//*Label 661*/ GIMT_Encode4(45936), // Rule ID 6869 // |
| 12640 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 12641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12642 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12643 | // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3i64] }:$src0) => VReg_192:{ *:[v6i32] }:$src0 |
| 12644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12645 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12646 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12647 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12648 | // GIR_Coverage, 6869, |
| 12649 | GIR_EraseRootFromParent_Done, |
| 12650 | // Label 661: @45936 |
| 12651 | GIM_Try, /*On fail goto*//*Label 662*/ GIMT_Encode4(45965), // Rule ID 6870 // |
| 12652 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 12653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12654 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12655 | // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3i64] }:$src0) => VReg_192:{ *:[v6f32] }:$src0 |
| 12656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12657 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12658 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12659 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12660 | // GIR_Coverage, 6870, |
| 12661 | GIR_EraseRootFromParent_Done, |
| 12662 | // Label 662: @45965 |
| 12663 | GIM_Try, /*On fail goto*//*Label 663*/ GIMT_Encode4(45994), // Rule ID 6871 // |
| 12664 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 12665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12666 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12667 | // (bitconvert:{ *:[v6i32] } VReg_192:{ *:[v3f64] }:$src0) => VReg_192:{ *:[v6i32] }:$src0 |
| 12668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12669 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12670 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12671 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12672 | // GIR_Coverage, 6871, |
| 12673 | GIR_EraseRootFromParent_Done, |
| 12674 | // Label 663: @45994 |
| 12675 | GIM_Try, /*On fail goto*//*Label 664*/ GIMT_Encode4(46023), // Rule ID 6872 // |
| 12676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v3s64, |
| 12677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12678 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12679 | // (bitconvert:{ *:[v6f32] } VReg_192:{ *:[v3f64] }:$src0) => VReg_192:{ *:[v6f32] }:$src0 |
| 12680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12681 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12682 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12683 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_192RegClassID), |
| 12684 | // GIR_Coverage, 6872, |
| 12685 | GIR_EraseRootFromParent_Done, |
| 12686 | // Label 664: @46023 |
| 12687 | GIM_Reject, |
| 12688 | // Label 503: @46024 |
| 12689 | GIM_Try, /*On fail goto*//*Label 665*/ GIMT_Encode4(46137), |
| 12690 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v7s32, |
| 12691 | GIM_Try, /*On fail goto*//*Label 666*/ GIMT_Encode4(46058), // Rule ID 6873 // |
| 12692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12693 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12694 | // (bitconvert:{ *:[v7i32] } SReg_224:{ *:[v7f32] }:$src0) => SReg_224:{ *:[v7i32] }:$src0 |
| 12695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12696 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12697 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12698 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12699 | // GIR_Coverage, 6873, |
| 12700 | GIR_EraseRootFromParent_Done, |
| 12701 | // Label 666: @46058 |
| 12702 | GIM_Try, /*On fail goto*//*Label 667*/ GIMT_Encode4(46084), // Rule ID 6874 // |
| 12703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12705 | // (bitconvert:{ *:[v7f32] } SReg_224:{ *:[v7i32] }:$src0) => SReg_224:{ *:[v7f32] }:$src0 |
| 12706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12707 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12708 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12709 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_224RegClassID), |
| 12710 | // GIR_Coverage, 6874, |
| 12711 | GIR_EraseRootFromParent_Done, |
| 12712 | // Label 667: @46084 |
| 12713 | GIM_Try, /*On fail goto*//*Label 668*/ GIMT_Encode4(46110), // Rule ID 6875 // |
| 12714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12715 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12716 | // (bitconvert:{ *:[v7i32] } VReg_224:{ *:[v7f32] }:$src0) => VReg_224:{ *:[v7i32] }:$src0 |
| 12717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12718 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12719 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12720 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12721 | // GIR_Coverage, 6875, |
| 12722 | GIR_EraseRootFromParent_Done, |
| 12723 | // Label 668: @46110 |
| 12724 | GIM_Try, /*On fail goto*//*Label 669*/ GIMT_Encode4(46136), // Rule ID 6876 // |
| 12725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12726 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12727 | // (bitconvert:{ *:[v7f32] } VReg_224:{ *:[v7i32] }:$src0) => VReg_224:{ *:[v7f32] }:$src0 |
| 12728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12729 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12730 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12731 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_224RegClassID), |
| 12732 | // GIR_Coverage, 6876, |
| 12733 | GIR_EraseRootFromParent_Done, |
| 12734 | // Label 669: @46136 |
| 12735 | GIM_Reject, |
| 12736 | // Label 665: @46137 |
| 12737 | GIM_Reject, |
| 12738 | // Label 504: @46138 |
| 12739 | GIM_Try, /*On fail goto*//*Label 670*/ GIMT_Encode4(46167), // Rule ID 6811 // |
| 12740 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12742 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12743 | // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v4i32] }:$src0) => SReg_128:{ *:[v8i16] }:$src0 |
| 12744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12745 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12746 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12747 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12748 | // GIR_Coverage, 6811, |
| 12749 | GIR_EraseRootFromParent_Done, |
| 12750 | // Label 670: @46167 |
| 12751 | GIM_Try, /*On fail goto*//*Label 671*/ GIMT_Encode4(46196), // Rule ID 6813 // |
| 12752 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12754 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12755 | // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v8f16] }:$src0 |
| 12756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12757 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12758 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12759 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12760 | // GIR_Coverage, 6813, |
| 12761 | GIR_EraseRootFromParent_Done, |
| 12762 | // Label 671: @46196 |
| 12763 | GIM_Try, /*On fail goto*//*Label 672*/ GIMT_Encode4(46225), // Rule ID 6814 // |
| 12764 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12766 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12767 | // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v4i32] }:$src0) => VReg_128:{ *:[v8f16] }:$src0 |
| 12768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12769 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12770 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12771 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12772 | // GIR_Coverage, 6814, |
| 12773 | GIR_EraseRootFromParent_Done, |
| 12774 | // Label 672: @46225 |
| 12775 | GIM_Try, /*On fail goto*//*Label 673*/ GIMT_Encode4(46254), // Rule ID 6817 // |
| 12776 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12777 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12778 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12779 | // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v8f16] }:$src0) => VReg_128:{ *:[v8i16] }:$src0 |
| 12780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12781 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12782 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12783 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12784 | // GIR_Coverage, 6817, |
| 12785 | GIR_EraseRootFromParent_Done, |
| 12786 | // Label 673: @46254 |
| 12787 | GIM_Try, /*On fail goto*//*Label 674*/ GIMT_Encode4(46283), // Rule ID 6818 // |
| 12788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12790 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12791 | // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v8i16] }:$src0) => VReg_128:{ *:[v8f16] }:$src0 |
| 12792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12793 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12794 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12795 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12796 | // GIR_Coverage, 6818, |
| 12797 | GIR_EraseRootFromParent_Done, |
| 12798 | // Label 674: @46283 |
| 12799 | GIM_Try, /*On fail goto*//*Label 675*/ GIMT_Encode4(46312), // Rule ID 6820 // |
| 12800 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12802 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12803 | // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v8i16] }:$src0 |
| 12804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12805 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12806 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12807 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12808 | // GIR_Coverage, 6820, |
| 12809 | GIR_EraseRootFromParent_Done, |
| 12810 | // Label 675: @46312 |
| 12811 | GIM_Try, /*On fail goto*//*Label 676*/ GIMT_Encode4(46341), // Rule ID 6821 // |
| 12812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12814 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12815 | // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v8f16] }:$src0) => SReg_128:{ *:[v8i16] }:$src0 |
| 12816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12817 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12818 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12819 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12820 | // GIR_Coverage, 6821, |
| 12821 | GIR_EraseRootFromParent_Done, |
| 12822 | // Label 676: @46341 |
| 12823 | GIM_Try, /*On fail goto*//*Label 677*/ GIMT_Encode4(46370), // Rule ID 6822 // |
| 12824 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12826 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12827 | // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2i64] }:$src0) => SReg_128:{ *:[v8i16] }:$src0 |
| 12828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12829 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12830 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12831 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12832 | // GIR_Coverage, 6822, |
| 12833 | GIR_EraseRootFromParent_Done, |
| 12834 | // Label 677: @46370 |
| 12835 | GIM_Try, /*On fail goto*//*Label 678*/ GIMT_Encode4(46399), // Rule ID 6823 // |
| 12836 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12838 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12839 | // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v2f64] }:$src0) => SReg_128:{ *:[v8i16] }:$src0 |
| 12840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12841 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12842 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12843 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12844 | // GIR_Coverage, 6823, |
| 12845 | GIR_EraseRootFromParent_Done, |
| 12846 | // Label 678: @46399 |
| 12847 | GIM_Try, /*On fail goto*//*Label 679*/ GIMT_Encode4(46428), // Rule ID 6824 // |
| 12848 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12850 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12851 | // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2i64] }:$src0) => SReg_128:{ *:[v8f16] }:$src0 |
| 12852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12853 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12854 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12855 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12856 | // GIR_Coverage, 6824, |
| 12857 | GIR_EraseRootFromParent_Done, |
| 12858 | // Label 679: @46428 |
| 12859 | GIM_Try, /*On fail goto*//*Label 680*/ GIMT_Encode4(46457), // Rule ID 6825 // |
| 12860 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 12861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12862 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12863 | // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v2f64] }:$src0) => SReg_128:{ *:[v8f16] }:$src0 |
| 12864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12865 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12866 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12867 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12868 | // GIR_Coverage, 6825, |
| 12869 | GIR_EraseRootFromParent_Done, |
| 12870 | // Label 680: @46457 |
| 12871 | GIM_Try, /*On fail goto*//*Label 681*/ GIMT_Encode4(46486), // Rule ID 6826 // |
| 12872 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12875 | // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v8i16] }:$src0) => SReg_128:{ *:[v8f16] }:$src0 |
| 12876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12877 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12878 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12879 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12880 | // GIR_Coverage, 6826, |
| 12881 | GIR_EraseRootFromParent_Done, |
| 12882 | // Label 681: @46486 |
| 12883 | GIM_Try, /*On fail goto*//*Label 682*/ GIMT_Encode4(46515), // Rule ID 6832 // |
| 12884 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12887 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v4i32] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 12888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12889 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12890 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12891 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12892 | // GIR_Coverage, 6832, |
| 12893 | GIR_EraseRootFromParent_Done, |
| 12894 | // Label 682: @46515 |
| 12895 | GIM_Try, /*On fail goto*//*Label 683*/ GIMT_Encode4(46544), // Rule ID 6834 // |
| 12896 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12898 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12899 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v4i32] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 12900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12901 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12902 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12903 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12904 | // GIR_Coverage, 6834, |
| 12905 | GIR_EraseRootFromParent_Done, |
| 12906 | // Label 683: @46544 |
| 12907 | GIM_Try, /*On fail goto*//*Label 684*/ GIMT_Encode4(46573), // Rule ID 6836 // |
| 12908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12911 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v4f32] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 12912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12913 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12914 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12915 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12916 | // GIR_Coverage, 6836, |
| 12917 | GIR_EraseRootFromParent_Done, |
| 12918 | // Label 684: @46573 |
| 12919 | GIM_Try, /*On fail goto*//*Label 685*/ GIMT_Encode4(46602), // Rule ID 6838 // |
| 12920 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 12921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12923 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v4f32] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 12924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12925 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12926 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12927 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12928 | // GIR_Coverage, 6838, |
| 12929 | GIR_EraseRootFromParent_Done, |
| 12930 | // Label 685: @46602 |
| 12931 | GIM_Try, /*On fail goto*//*Label 686*/ GIMT_Encode4(46631), // Rule ID 6839 // |
| 12932 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12934 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12935 | // (bitconvert:{ *:[v8i16] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v8i16] }:$src0 |
| 12936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12937 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12938 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12939 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12940 | // GIR_Coverage, 6839, |
| 12941 | GIR_EraseRootFromParent_Done, |
| 12942 | // Label 686: @46631 |
| 12943 | GIM_Try, /*On fail goto*//*Label 687*/ GIMT_Encode4(46660), // Rule ID 6840 // |
| 12944 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12947 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v8i16] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 12948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12949 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12950 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12951 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12952 | // GIR_Coverage, 6840, |
| 12953 | GIR_EraseRootFromParent_Done, |
| 12954 | // Label 687: @46660 |
| 12955 | GIM_Try, /*On fail goto*//*Label 688*/ GIMT_Encode4(46689), // Rule ID 6841 // |
| 12956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12959 | // (bitconvert:{ *:[v8i16] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v8i16] }:$src0 |
| 12960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12961 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12962 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12963 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12964 | // GIR_Coverage, 6841, |
| 12965 | GIR_EraseRootFromParent_Done, |
| 12966 | // Label 688: @46689 |
| 12967 | GIM_Try, /*On fail goto*//*Label 689*/ GIMT_Encode4(46718), // Rule ID 6842 // |
| 12968 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12971 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v8i16] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 12972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12973 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12974 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12975 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 12976 | // GIR_Coverage, 6842, |
| 12977 | GIR_EraseRootFromParent_Done, |
| 12978 | // Label 689: @46718 |
| 12979 | GIM_Try, /*On fail goto*//*Label 690*/ GIMT_Encode4(46747), // Rule ID 6843 // |
| 12980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12983 | // (bitconvert:{ *:[v8f16] } SReg_128:{ *:[v8bf16] }:$src0) => SReg_128:{ *:[v8f16] }:$src0 |
| 12984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12985 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12986 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12987 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12988 | // GIR_Coverage, 6843, |
| 12989 | GIR_EraseRootFromParent_Done, |
| 12990 | // Label 690: @46747 |
| 12991 | GIM_Try, /*On fail goto*//*Label 691*/ GIMT_Encode4(46776), // Rule ID 6844 // |
| 12992 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 12993 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 12995 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v8f16] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 12996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 12997 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 12998 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 12999 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13000 | // GIR_Coverage, 6844, |
| 13001 | GIR_EraseRootFromParent_Done, |
| 13002 | // Label 691: @46776 |
| 13003 | GIM_Try, /*On fail goto*//*Label 692*/ GIMT_Encode4(46805), // Rule ID 6845 // |
| 13004 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13007 | // (bitconvert:{ *:[v8f16] } VReg_128:{ *:[v8bf16] }:$src0) => VReg_128:{ *:[v8f16] }:$src0 |
| 13008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13009 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13010 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13011 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13012 | // GIR_Coverage, 6845, |
| 13013 | GIR_EraseRootFromParent_Done, |
| 13014 | // Label 692: @46805 |
| 13015 | GIM_Try, /*On fail goto*//*Label 693*/ GIMT_Encode4(46834), // Rule ID 6846 // |
| 13016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s16, |
| 13017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13019 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v8f16] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 13020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13021 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13022 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13024 | // GIR_Coverage, 6846, |
| 13025 | GIR_EraseRootFromParent_Done, |
| 13026 | // Label 693: @46834 |
| 13027 | GIM_Try, /*On fail goto*//*Label 694*/ GIMT_Encode4(46863), // Rule ID 6848 // |
| 13028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13031 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v2f64] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 13032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13033 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13034 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13035 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13036 | // GIR_Coverage, 6848, |
| 13037 | GIR_EraseRootFromParent_Done, |
| 13038 | // Label 694: @46863 |
| 13039 | GIM_Try, /*On fail goto*//*Label 695*/ GIMT_Encode4(46892), // Rule ID 6850 // |
| 13040 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13042 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13043 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v2f64] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 13044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13045 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13046 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13047 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13048 | // GIR_Coverage, 6850, |
| 13049 | GIR_EraseRootFromParent_Done, |
| 13050 | // Label 695: @46892 |
| 13051 | GIM_Try, /*On fail goto*//*Label 696*/ GIMT_Encode4(46921), // Rule ID 6852 // |
| 13052 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13054 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13055 | // (bitconvert:{ *:[v8bf16] } SReg_128:{ *:[v2i64] }:$src0) => SReg_128:{ *:[v8bf16] }:$src0 |
| 13056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13057 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13058 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13059 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 13060 | // GIR_Coverage, 6852, |
| 13061 | GIR_EraseRootFromParent_Done, |
| 13062 | // Label 696: @46921 |
| 13063 | GIM_Try, /*On fail goto*//*Label 697*/ GIMT_Encode4(46950), // Rule ID 6854 // |
| 13064 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s64, |
| 13065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13066 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13067 | // (bitconvert:{ *:[v8bf16] } VReg_128:{ *:[v2i64] }:$src0) => VReg_128:{ *:[v8bf16] }:$src0 |
| 13068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13069 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13070 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13071 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 13072 | // GIR_Coverage, 6854, |
| 13073 | GIR_EraseRootFromParent_Done, |
| 13074 | // Label 697: @46950 |
| 13075 | GIM_Reject, |
| 13076 | // Label 505: @46951 |
| 13077 | GIM_Try, /*On fail goto*//*Label 698*/ GIMT_Encode4(46980), // Rule ID 6877 // |
| 13078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13080 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13081 | // (bitconvert:{ *:[v8i32] } SReg_256:{ *:[v8f32] }:$src0) => SReg_256:{ *:[v8i32] }:$src0 |
| 13082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13083 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13084 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13085 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13086 | // GIR_Coverage, 6877, |
| 13087 | GIR_EraseRootFromParent_Done, |
| 13088 | // Label 698: @46980 |
| 13089 | GIM_Try, /*On fail goto*//*Label 699*/ GIMT_Encode4(47009), // Rule ID 6878 // |
| 13090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13093 | // (bitconvert:{ *:[v8f32] } SReg_256:{ *:[v8i32] }:$src0) => SReg_256:{ *:[v8f32] }:$src0 |
| 13094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13095 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13096 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13097 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13098 | // GIR_Coverage, 6878, |
| 13099 | GIR_EraseRootFromParent_Done, |
| 13100 | // Label 699: @47009 |
| 13101 | GIM_Try, /*On fail goto*//*Label 700*/ GIMT_Encode4(47038), // Rule ID 6879 // |
| 13102 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13104 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13105 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13107 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13108 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13109 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13110 | // GIR_Coverage, 6879, |
| 13111 | GIR_EraseRootFromParent_Done, |
| 13112 | // Label 700: @47038 |
| 13113 | GIM_Try, /*On fail goto*//*Label 701*/ GIMT_Encode4(47067), // Rule ID 6880 // |
| 13114 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13116 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13117 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13119 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13120 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13121 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13122 | // GIR_Coverage, 6880, |
| 13123 | GIR_EraseRootFromParent_Done, |
| 13124 | // Label 701: @47067 |
| 13125 | GIM_Try, /*On fail goto*//*Label 702*/ GIMT_Encode4(47096), // Rule ID 6887 // |
| 13126 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13129 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13131 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13132 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13133 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13134 | // GIR_Coverage, 6887, |
| 13135 | GIR_EraseRootFromParent_Done, |
| 13136 | // Label 702: @47096 |
| 13137 | GIM_Try, /*On fail goto*//*Label 703*/ GIMT_Encode4(47125), // Rule ID 6888 // |
| 13138 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13140 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13141 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13143 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13144 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13145 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13146 | // GIR_Coverage, 6888, |
| 13147 | GIR_EraseRootFromParent_Done, |
| 13148 | // Label 703: @47125 |
| 13149 | GIM_Try, /*On fail goto*//*Label 704*/ GIMT_Encode4(47154), // Rule ID 6889 // |
| 13150 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13152 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13153 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13155 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13156 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13157 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13158 | // GIR_Coverage, 6889, |
| 13159 | GIR_EraseRootFromParent_Done, |
| 13160 | // Label 704: @47154 |
| 13161 | GIM_Try, /*On fail goto*//*Label 705*/ GIMT_Encode4(47183), // Rule ID 6890 // |
| 13162 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13164 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13165 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13167 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13168 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13169 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13170 | // GIR_Coverage, 6890, |
| 13171 | GIR_EraseRootFromParent_Done, |
| 13172 | // Label 705: @47183 |
| 13173 | GIM_Try, /*On fail goto*//*Label 706*/ GIMT_Encode4(47212), // Rule ID 6899 // |
| 13174 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13176 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13177 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13179 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13180 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13181 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13182 | // GIR_Coverage, 6899, |
| 13183 | GIR_EraseRootFromParent_Done, |
| 13184 | // Label 706: @47212 |
| 13185 | GIM_Try, /*On fail goto*//*Label 707*/ GIMT_Encode4(47241), // Rule ID 6900 // |
| 13186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13189 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13191 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13192 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13193 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13194 | // GIR_Coverage, 6900, |
| 13195 | GIR_EraseRootFromParent_Done, |
| 13196 | // Label 707: @47241 |
| 13197 | GIM_Try, /*On fail goto*//*Label 708*/ GIMT_Encode4(47270), // Rule ID 6901 // |
| 13198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13200 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13201 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13203 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13204 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13205 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13206 | // GIR_Coverage, 6901, |
| 13207 | GIR_EraseRootFromParent_Done, |
| 13208 | // Label 708: @47270 |
| 13209 | GIM_Try, /*On fail goto*//*Label 709*/ GIMT_Encode4(47299), // Rule ID 6902 // |
| 13210 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13212 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13213 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13215 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13216 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13217 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13218 | // GIR_Coverage, 6902, |
| 13219 | GIR_EraseRootFromParent_Done, |
| 13220 | // Label 709: @47299 |
| 13221 | GIM_Try, /*On fail goto*//*Label 710*/ GIMT_Encode4(47328), // Rule ID 6911 // |
| 13222 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13224 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13225 | // (bitconvert:{ *:[v8i32] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v8i32] }:$src0 |
| 13226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13227 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13228 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13229 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13230 | // GIR_Coverage, 6911, |
| 13231 | GIR_EraseRootFromParent_Done, |
| 13232 | // Label 710: @47328 |
| 13233 | GIM_Try, /*On fail goto*//*Label 711*/ GIMT_Encode4(47357), // Rule ID 6913 // |
| 13234 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13236 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13237 | // (bitconvert:{ *:[v8f32] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v8f32] }:$src0 |
| 13238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13239 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13240 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13241 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13242 | // GIR_Coverage, 6913, |
| 13243 | GIR_EraseRootFromParent_Done, |
| 13244 | // Label 711: @47357 |
| 13245 | GIM_Reject, |
| 13246 | // Label 506: @47358 |
| 13247 | GIM_Try, /*On fail goto*//*Label 712*/ GIMT_Encode4(47387), // Rule ID 6955 // |
| 13248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13250 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13251 | // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v8f64] }:$src0) => VReg_512:{ *:[v8i64] }:$src0 |
| 13252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13253 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13254 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13255 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13256 | // GIR_Coverage, 6955, |
| 13257 | GIR_EraseRootFromParent_Done, |
| 13258 | // Label 712: @47387 |
| 13259 | GIM_Try, /*On fail goto*//*Label 713*/ GIMT_Encode4(47416), // Rule ID 6956 // |
| 13260 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13263 | // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v8i64] }:$src0) => VReg_512:{ *:[v8f64] }:$src0 |
| 13264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13265 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13266 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13267 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13268 | // GIR_Coverage, 6956, |
| 13269 | GIR_EraseRootFromParent_Done, |
| 13270 | // Label 713: @47416 |
| 13271 | GIM_Try, /*On fail goto*//*Label 714*/ GIMT_Encode4(47445), // Rule ID 6957 // |
| 13272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13273 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13274 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13275 | // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v8i64] }:$src0 |
| 13276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13277 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13278 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13279 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13280 | // GIR_Coverage, 6957, |
| 13281 | GIR_EraseRootFromParent_Done, |
| 13282 | // Label 714: @47445 |
| 13283 | GIM_Try, /*On fail goto*//*Label 715*/ GIMT_Encode4(47474), // Rule ID 6958 // |
| 13284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13287 | // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v8f64] }:$src0 |
| 13288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13289 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13290 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13291 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13292 | // GIR_Coverage, 6958, |
| 13293 | GIR_EraseRootFromParent_Done, |
| 13294 | // Label 715: @47474 |
| 13295 | GIM_Try, /*On fail goto*//*Label 716*/ GIMT_Encode4(47503), // Rule ID 6961 // |
| 13296 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13299 | // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v8i64] }:$src0 |
| 13300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13301 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13302 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13303 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13304 | // GIR_Coverage, 6961, |
| 13305 | GIR_EraseRootFromParent_Done, |
| 13306 | // Label 716: @47503 |
| 13307 | GIM_Try, /*On fail goto*//*Label 717*/ GIMT_Encode4(47532), // Rule ID 6962 // |
| 13308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13310 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13311 | // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v8f64] }:$src0 |
| 13312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13313 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13314 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13315 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13316 | // GIR_Coverage, 6962, |
| 13317 | GIR_EraseRootFromParent_Done, |
| 13318 | // Label 717: @47532 |
| 13319 | GIM_Try, /*On fail goto*//*Label 718*/ GIMT_Encode4(47561), // Rule ID 6982 // |
| 13320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13323 | // (bitconvert:{ *:[v8f64] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v8f64] }:$src0 |
| 13324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13325 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13326 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13327 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13328 | // GIR_Coverage, 6982, |
| 13329 | GIR_EraseRootFromParent_Done, |
| 13330 | // Label 718: @47561 |
| 13331 | GIM_Try, /*On fail goto*//*Label 719*/ GIMT_Encode4(47590), // Rule ID 6984 // |
| 13332 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13334 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13335 | // (bitconvert:{ *:[v8f64] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v8f64] }:$src0 |
| 13336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13337 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13338 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13339 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13340 | // GIR_Coverage, 6984, |
| 13341 | GIR_EraseRootFromParent_Done, |
| 13342 | // Label 719: @47590 |
| 13343 | GIM_Try, /*On fail goto*//*Label 720*/ GIMT_Encode4(47619), // Rule ID 6986 // |
| 13344 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13347 | // (bitconvert:{ *:[v8i64] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v8i64] }:$src0 |
| 13348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13349 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13350 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13351 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13352 | // GIR_Coverage, 6986, |
| 13353 | GIR_EraseRootFromParent_Done, |
| 13354 | // Label 720: @47619 |
| 13355 | GIM_Try, /*On fail goto*//*Label 721*/ GIMT_Encode4(47648), // Rule ID 6988 // |
| 13356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13359 | // (bitconvert:{ *:[v8i64] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v8i64] }:$src0 |
| 13360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13361 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13362 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13363 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13364 | // GIR_Coverage, 6988, |
| 13365 | GIR_EraseRootFromParent_Done, |
| 13366 | // Label 721: @47648 |
| 13367 | GIM_Reject, |
| 13368 | // Label 507: @47649 |
| 13369 | GIM_Try, /*On fail goto*//*Label 722*/ GIMT_Encode4(47762), |
| 13370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v9s32, |
| 13371 | GIM_Try, /*On fail goto*//*Label 723*/ GIMT_Encode4(47683), // Rule ID 6927 // |
| 13372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13373 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13374 | // (bitconvert:{ *:[v9i32] } SReg_288:{ *:[v9f32] }:$src0) => SReg_288:{ *:[v9i32] }:$src0 |
| 13375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13376 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13377 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13378 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13379 | // GIR_Coverage, 6927, |
| 13380 | GIR_EraseRootFromParent_Done, |
| 13381 | // Label 723: @47683 |
| 13382 | GIM_Try, /*On fail goto*//*Label 724*/ GIMT_Encode4(47709), // Rule ID 6928 // |
| 13383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13384 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13385 | // (bitconvert:{ *:[v9f32] } SReg_288:{ *:[v9i32] }:$src0) => SReg_288:{ *:[v9f32] }:$src0 |
| 13386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13387 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13388 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13389 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_288RegClassID), |
| 13390 | // GIR_Coverage, 6928, |
| 13391 | GIR_EraseRootFromParent_Done, |
| 13392 | // Label 724: @47709 |
| 13393 | GIM_Try, /*On fail goto*//*Label 725*/ GIMT_Encode4(47735), // Rule ID 6929 // |
| 13394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13395 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13396 | // (bitconvert:{ *:[v9i32] } VReg_288:{ *:[v9f32] }:$src0) => VReg_288:{ *:[v9i32] }:$src0 |
| 13397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13398 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13399 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13400 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13401 | // GIR_Coverage, 6929, |
| 13402 | GIR_EraseRootFromParent_Done, |
| 13403 | // Label 725: @47735 |
| 13404 | GIM_Try, /*On fail goto*//*Label 726*/ GIMT_Encode4(47761), // Rule ID 6930 // |
| 13405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13406 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13407 | // (bitconvert:{ *:[v9f32] } VReg_288:{ *:[v9i32] }:$src0) => VReg_288:{ *:[v9f32] }:$src0 |
| 13408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13409 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13410 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13411 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_288RegClassID), |
| 13412 | // GIR_Coverage, 6930, |
| 13413 | GIR_EraseRootFromParent_Done, |
| 13414 | // Label 726: @47761 |
| 13415 | GIM_Reject, |
| 13416 | // Label 722: @47762 |
| 13417 | GIM_Reject, |
| 13418 | // Label 508: @47763 |
| 13419 | GIM_Try, /*On fail goto*//*Label 727*/ GIMT_Encode4(47876), |
| 13420 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v10s32, |
| 13421 | GIM_Try, /*On fail goto*//*Label 728*/ GIMT_Encode4(47797), // Rule ID 6931 // |
| 13422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13423 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13424 | // (bitconvert:{ *:[v10i32] } SReg_320:{ *:[v10f32] }:$src0) => SReg_320:{ *:[v10i32] }:$src0 |
| 13425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13426 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13427 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13428 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13429 | // GIR_Coverage, 6931, |
| 13430 | GIR_EraseRootFromParent_Done, |
| 13431 | // Label 728: @47797 |
| 13432 | GIM_Try, /*On fail goto*//*Label 729*/ GIMT_Encode4(47823), // Rule ID 6932 // |
| 13433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13435 | // (bitconvert:{ *:[v10f32] } SReg_320:{ *:[v10i32] }:$src0) => SReg_320:{ *:[v10f32] }:$src0 |
| 13436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13437 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13438 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13439 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_320RegClassID), |
| 13440 | // GIR_Coverage, 6932, |
| 13441 | GIR_EraseRootFromParent_Done, |
| 13442 | // Label 729: @47823 |
| 13443 | GIM_Try, /*On fail goto*//*Label 730*/ GIMT_Encode4(47849), // Rule ID 6933 // |
| 13444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13445 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13446 | // (bitconvert:{ *:[v10i32] } VReg_320:{ *:[v10f32] }:$src0) => VReg_320:{ *:[v10i32] }:$src0 |
| 13447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13448 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13449 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13450 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13451 | // GIR_Coverage, 6933, |
| 13452 | GIR_EraseRootFromParent_Done, |
| 13453 | // Label 730: @47849 |
| 13454 | GIM_Try, /*On fail goto*//*Label 731*/ GIMT_Encode4(47875), // Rule ID 6934 // |
| 13455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13456 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13457 | // (bitconvert:{ *:[v10f32] } VReg_320:{ *:[v10i32] }:$src0) => VReg_320:{ *:[v10f32] }:$src0 |
| 13458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13459 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13460 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13461 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_320RegClassID), |
| 13462 | // GIR_Coverage, 6934, |
| 13463 | GIR_EraseRootFromParent_Done, |
| 13464 | // Label 731: @47875 |
| 13465 | GIM_Reject, |
| 13466 | // Label 727: @47876 |
| 13467 | GIM_Reject, |
| 13468 | // Label 509: @47877 |
| 13469 | GIM_Try, /*On fail goto*//*Label 732*/ GIMT_Encode4(47990), |
| 13470 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v11s32, |
| 13471 | GIM_Try, /*On fail goto*//*Label 733*/ GIMT_Encode4(47911), // Rule ID 6935 // |
| 13472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13474 | // (bitconvert:{ *:[v11i32] } SReg_352:{ *:[v11f32] }:$src0) => SReg_352:{ *:[v11i32] }:$src0 |
| 13475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13476 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13477 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13478 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13479 | // GIR_Coverage, 6935, |
| 13480 | GIR_EraseRootFromParent_Done, |
| 13481 | // Label 733: @47911 |
| 13482 | GIM_Try, /*On fail goto*//*Label 734*/ GIMT_Encode4(47937), // Rule ID 6936 // |
| 13483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13484 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13485 | // (bitconvert:{ *:[v11f32] } SReg_352:{ *:[v11i32] }:$src0) => SReg_352:{ *:[v11f32] }:$src0 |
| 13486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13487 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13488 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13489 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_352RegClassID), |
| 13490 | // GIR_Coverage, 6936, |
| 13491 | GIR_EraseRootFromParent_Done, |
| 13492 | // Label 734: @47937 |
| 13493 | GIM_Try, /*On fail goto*//*Label 735*/ GIMT_Encode4(47963), // Rule ID 6937 // |
| 13494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13495 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13496 | // (bitconvert:{ *:[v11i32] } VReg_352:{ *:[v11f32] }:$src0) => VReg_352:{ *:[v11i32] }:$src0 |
| 13497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13498 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13499 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13500 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13501 | // GIR_Coverage, 6937, |
| 13502 | GIR_EraseRootFromParent_Done, |
| 13503 | // Label 735: @47963 |
| 13504 | GIM_Try, /*On fail goto*//*Label 736*/ GIMT_Encode4(47989), // Rule ID 6938 // |
| 13505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13506 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13507 | // (bitconvert:{ *:[v11f32] } VReg_352:{ *:[v11i32] }:$src0) => VReg_352:{ *:[v11f32] }:$src0 |
| 13508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13509 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13510 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13511 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_352RegClassID), |
| 13512 | // GIR_Coverage, 6938, |
| 13513 | GIR_EraseRootFromParent_Done, |
| 13514 | // Label 736: @47989 |
| 13515 | GIM_Reject, |
| 13516 | // Label 732: @47990 |
| 13517 | GIM_Reject, |
| 13518 | // Label 510: @47991 |
| 13519 | GIM_Try, /*On fail goto*//*Label 737*/ GIMT_Encode4(48104), |
| 13520 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v12s32, |
| 13521 | GIM_Try, /*On fail goto*//*Label 738*/ GIMT_Encode4(48025), // Rule ID 6939 // |
| 13522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13523 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13524 | // (bitconvert:{ *:[v12i32] } SReg_384:{ *:[v12f32] }:$src0) => SReg_384:{ *:[v12i32] }:$src0 |
| 13525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13526 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13527 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13528 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13529 | // GIR_Coverage, 6939, |
| 13530 | GIR_EraseRootFromParent_Done, |
| 13531 | // Label 738: @48025 |
| 13532 | GIM_Try, /*On fail goto*//*Label 739*/ GIMT_Encode4(48051), // Rule ID 6940 // |
| 13533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13534 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13535 | // (bitconvert:{ *:[v12f32] } SReg_384:{ *:[v12i32] }:$src0) => SReg_384:{ *:[v12f32] }:$src0 |
| 13536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13537 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13538 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13539 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_384RegClassID), |
| 13540 | // GIR_Coverage, 6940, |
| 13541 | GIR_EraseRootFromParent_Done, |
| 13542 | // Label 739: @48051 |
| 13543 | GIM_Try, /*On fail goto*//*Label 740*/ GIMT_Encode4(48077), // Rule ID 6941 // |
| 13544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13545 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13546 | // (bitconvert:{ *:[v12i32] } VReg_384:{ *:[v12f32] }:$src0) => VReg_384:{ *:[v12i32] }:$src0 |
| 13547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13548 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13549 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13550 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13551 | // GIR_Coverage, 6941, |
| 13552 | GIR_EraseRootFromParent_Done, |
| 13553 | // Label 740: @48077 |
| 13554 | GIM_Try, /*On fail goto*//*Label 741*/ GIMT_Encode4(48103), // Rule ID 6942 // |
| 13555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13556 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13557 | // (bitconvert:{ *:[v12f32] } VReg_384:{ *:[v12i32] }:$src0) => VReg_384:{ *:[v12f32] }:$src0 |
| 13558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13559 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13560 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13561 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_384RegClassID), |
| 13562 | // GIR_Coverage, 6942, |
| 13563 | GIR_EraseRootFromParent_Done, |
| 13564 | // Label 741: @48103 |
| 13565 | GIM_Reject, |
| 13566 | // Label 737: @48104 |
| 13567 | GIM_Reject, |
| 13568 | // Label 511: @48105 |
| 13569 | GIM_Try, /*On fail goto*//*Label 742*/ GIMT_Encode4(48134), // Rule ID 6891 // |
| 13570 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13572 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13573 | // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v16f16] }:$src0) => SReg_256:{ *:[v16i16] }:$src0 |
| 13574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13575 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13576 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13577 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13578 | // GIR_Coverage, 6891, |
| 13579 | GIR_EraseRootFromParent_Done, |
| 13580 | // Label 742: @48134 |
| 13581 | GIM_Try, /*On fail goto*//*Label 743*/ GIMT_Encode4(48163), // Rule ID 6892 // |
| 13582 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13584 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13585 | // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v16i16] }:$src0) => SReg_256:{ *:[v16f16] }:$src0 |
| 13586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13587 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13588 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13589 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13590 | // GIR_Coverage, 6892, |
| 13591 | GIR_EraseRootFromParent_Done, |
| 13592 | // Label 743: @48163 |
| 13593 | GIM_Try, /*On fail goto*//*Label 744*/ GIMT_Encode4(48192), // Rule ID 6893 // |
| 13594 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13596 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13597 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13599 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13600 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13601 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13602 | // GIR_Coverage, 6893, |
| 13603 | GIR_EraseRootFromParent_Done, |
| 13604 | // Label 744: @48192 |
| 13605 | GIM_Try, /*On fail goto*//*Label 745*/ GIMT_Encode4(48221), // Rule ID 6894 // |
| 13606 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13608 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13609 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13611 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13612 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13613 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13614 | // GIR_Coverage, 6894, |
| 13615 | GIR_EraseRootFromParent_Done, |
| 13616 | // Label 745: @48221 |
| 13617 | GIM_Try, /*On fail goto*//*Label 746*/ GIMT_Encode4(48250), // Rule ID 6895 // |
| 13618 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13620 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13621 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13623 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13624 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13625 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13626 | // GIR_Coverage, 6895, |
| 13627 | GIR_EraseRootFromParent_Done, |
| 13628 | // Label 746: @48250 |
| 13629 | GIM_Try, /*On fail goto*//*Label 747*/ GIMT_Encode4(48279), // Rule ID 6896 // |
| 13630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13632 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13633 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13635 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13636 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13637 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13638 | // GIR_Coverage, 6896, |
| 13639 | GIR_EraseRootFromParent_Done, |
| 13640 | // Label 747: @48279 |
| 13641 | GIM_Try, /*On fail goto*//*Label 748*/ GIMT_Encode4(48308), // Rule ID 6897 // |
| 13642 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13644 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13645 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13647 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13648 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13649 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13650 | // GIR_Coverage, 6897, |
| 13651 | GIR_EraseRootFromParent_Done, |
| 13652 | // Label 748: @48308 |
| 13653 | GIM_Try, /*On fail goto*//*Label 749*/ GIMT_Encode4(48337), // Rule ID 6898 // |
| 13654 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13656 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13657 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13659 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13660 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13661 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13662 | // GIR_Coverage, 6898, |
| 13663 | GIR_EraseRootFromParent_Done, |
| 13664 | // Label 749: @48337 |
| 13665 | GIM_Try, /*On fail goto*//*Label 750*/ GIMT_Encode4(48366), // Rule ID 6903 // |
| 13666 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13668 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13669 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13671 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13672 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13673 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13674 | // GIR_Coverage, 6903, |
| 13675 | GIR_EraseRootFromParent_Done, |
| 13676 | // Label 750: @48366 |
| 13677 | GIM_Try, /*On fail goto*//*Label 751*/ GIMT_Encode4(48395), // Rule ID 6904 // |
| 13678 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13681 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13683 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13684 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13685 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13686 | // GIR_Coverage, 6904, |
| 13687 | GIR_EraseRootFromParent_Done, |
| 13688 | // Label 751: @48395 |
| 13689 | GIM_Try, /*On fail goto*//*Label 752*/ GIMT_Encode4(48424), // Rule ID 6905 // |
| 13690 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13692 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13693 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13695 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13696 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13697 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13698 | // GIR_Coverage, 6905, |
| 13699 | GIR_EraseRootFromParent_Done, |
| 13700 | // Label 752: @48424 |
| 13701 | GIM_Try, /*On fail goto*//*Label 753*/ GIMT_Encode4(48453), // Rule ID 6906 // |
| 13702 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13705 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13707 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13708 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13709 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13710 | // GIR_Coverage, 6906, |
| 13711 | GIR_EraseRootFromParent_Done, |
| 13712 | // Label 753: @48453 |
| 13713 | GIM_Try, /*On fail goto*//*Label 754*/ GIMT_Encode4(48482), // Rule ID 6912 // |
| 13714 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13716 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13717 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v8i32] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13719 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13720 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13721 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13722 | // GIR_Coverage, 6912, |
| 13723 | GIR_EraseRootFromParent_Done, |
| 13724 | // Label 754: @48482 |
| 13725 | GIM_Try, /*On fail goto*//*Label 755*/ GIMT_Encode4(48511), // Rule ID 6914 // |
| 13726 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s32, |
| 13727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13728 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13729 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v8f32] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13731 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13732 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13733 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13734 | // GIR_Coverage, 6914, |
| 13735 | GIR_EraseRootFromParent_Done, |
| 13736 | // Label 755: @48511 |
| 13737 | GIM_Try, /*On fail goto*//*Label 756*/ GIMT_Encode4(48540), // Rule ID 6916 // |
| 13738 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13740 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13741 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v4i64] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13743 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13744 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13745 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13746 | // GIR_Coverage, 6916, |
| 13747 | GIR_EraseRootFromParent_Done, |
| 13748 | // Label 756: @48540 |
| 13749 | GIM_Try, /*On fail goto*//*Label 757*/ GIMT_Encode4(48569), // Rule ID 6918 // |
| 13750 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s64, |
| 13751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13752 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13753 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v4f64] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13755 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13756 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13757 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13758 | // GIR_Coverage, 6918, |
| 13759 | GIR_EraseRootFromParent_Done, |
| 13760 | // Label 757: @48569 |
| 13761 | GIM_Try, /*On fail goto*//*Label 758*/ GIMT_Encode4(48598), // Rule ID 6919 // |
| 13762 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13764 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13765 | // (bitconvert:{ *:[v16i16] } SReg_256:{ *:[v16bf16] }:$src0) => SReg_256:{ *:[v16i16] }:$src0 |
| 13766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13767 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13768 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13769 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13770 | // GIR_Coverage, 6919, |
| 13771 | GIR_EraseRootFromParent_Done, |
| 13772 | // Label 758: @48598 |
| 13773 | GIM_Try, /*On fail goto*//*Label 759*/ GIMT_Encode4(48627), // Rule ID 6920 // |
| 13774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13776 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13777 | // (bitconvert:{ *:[v16bf16] } SReg_256:{ *:[v16i16] }:$src0) => SReg_256:{ *:[v16bf16] }:$src0 |
| 13778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13779 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13780 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13781 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13782 | // GIR_Coverage, 6920, |
| 13783 | GIR_EraseRootFromParent_Done, |
| 13784 | // Label 759: @48627 |
| 13785 | GIM_Try, /*On fail goto*//*Label 760*/ GIMT_Encode4(48656), // Rule ID 6921 // |
| 13786 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13788 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13789 | // (bitconvert:{ *:[v16i16] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v16i16] }:$src0 |
| 13790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13791 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13792 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13793 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13794 | // GIR_Coverage, 6921, |
| 13795 | GIR_EraseRootFromParent_Done, |
| 13796 | // Label 760: @48656 |
| 13797 | GIM_Try, /*On fail goto*//*Label 761*/ GIMT_Encode4(48685), // Rule ID 6922 // |
| 13798 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13800 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13801 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v16i16] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13803 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13804 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13805 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13806 | // GIR_Coverage, 6922, |
| 13807 | GIR_EraseRootFromParent_Done, |
| 13808 | // Label 761: @48685 |
| 13809 | GIM_Try, /*On fail goto*//*Label 762*/ GIMT_Encode4(48714), // Rule ID 6923 // |
| 13810 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13812 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13813 | // (bitconvert:{ *:[v16f16] } SReg_256:{ *:[v16bf16] }:$src0) => SReg_256:{ *:[v16f16] }:$src0 |
| 13814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13815 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13816 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13817 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13818 | // GIR_Coverage, 6923, |
| 13819 | GIR_EraseRootFromParent_Done, |
| 13820 | // Label 762: @48714 |
| 13821 | GIM_Try, /*On fail goto*//*Label 763*/ GIMT_Encode4(48743), // Rule ID 6924 // |
| 13822 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13824 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13825 | // (bitconvert:{ *:[v16bf16] } SReg_256:{ *:[v16f16] }:$src0) => SReg_256:{ *:[v16bf16] }:$src0 |
| 13826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13827 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13828 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13829 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 13830 | // GIR_Coverage, 6924, |
| 13831 | GIR_EraseRootFromParent_Done, |
| 13832 | // Label 763: @48743 |
| 13833 | GIM_Try, /*On fail goto*//*Label 764*/ GIMT_Encode4(48772), // Rule ID 6925 // |
| 13834 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13837 | // (bitconvert:{ *:[v16f16] } VReg_256:{ *:[v16bf16] }:$src0) => VReg_256:{ *:[v16f16] }:$src0 |
| 13838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13839 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13840 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13841 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13842 | // GIR_Coverage, 6925, |
| 13843 | GIR_EraseRootFromParent_Done, |
| 13844 | // Label 764: @48772 |
| 13845 | GIM_Try, /*On fail goto*//*Label 765*/ GIMT_Encode4(48801), // Rule ID 6926 // |
| 13846 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s16, |
| 13847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13848 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13849 | // (bitconvert:{ *:[v16bf16] } VReg_256:{ *:[v16f16] }:$src0) => VReg_256:{ *:[v16bf16] }:$src0 |
| 13850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13851 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13852 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13853 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 13854 | // GIR_Coverage, 6926, |
| 13855 | GIR_EraseRootFromParent_Done, |
| 13856 | // Label 765: @48801 |
| 13857 | GIM_Reject, |
| 13858 | // Label 512: @48802 |
| 13859 | GIM_Try, /*On fail goto*//*Label 766*/ GIMT_Encode4(48831), // Rule ID 6947 // |
| 13860 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13862 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13863 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32f16] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 13864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13865 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13866 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13867 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13868 | // GIR_Coverage, 6947, |
| 13869 | GIR_EraseRootFromParent_Done, |
| 13870 | // Label 766: @48831 |
| 13871 | GIM_Try, /*On fail goto*//*Label 767*/ GIMT_Encode4(48860), // Rule ID 6948 // |
| 13872 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13875 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32f16] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13877 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13878 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13879 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13880 | // GIR_Coverage, 6948, |
| 13881 | GIR_EraseRootFromParent_Done, |
| 13882 | // Label 767: @48860 |
| 13883 | GIM_Try, /*On fail goto*//*Label 768*/ GIMT_Encode4(48889), // Rule ID 6951 // |
| 13884 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13886 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13887 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32i16] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 13888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13889 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13890 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13891 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13892 | // GIR_Coverage, 6951, |
| 13893 | GIR_EraseRootFromParent_Done, |
| 13894 | // Label 768: @48889 |
| 13895 | GIM_Try, /*On fail goto*//*Label 769*/ GIMT_Encode4(48918), // Rule ID 6952 // |
| 13896 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13898 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13899 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32i16] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13901 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13902 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13903 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13904 | // GIR_Coverage, 6952, |
| 13905 | GIR_EraseRootFromParent_Done, |
| 13906 | // Label 769: @48918 |
| 13907 | GIM_Try, /*On fail goto*//*Label 770*/ GIMT_Encode4(48947), // Rule ID 6953 // |
| 13908 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13910 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13911 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13913 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13914 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13915 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13916 | // GIR_Coverage, 6953, |
| 13917 | GIR_EraseRootFromParent_Done, |
| 13918 | // Label 770: @48947 |
| 13919 | GIM_Try, /*On fail goto*//*Label 771*/ GIMT_Encode4(48976), // Rule ID 6954 // |
| 13920 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 13921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13922 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13923 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 13924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13925 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13926 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13927 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13928 | // GIR_Coverage, 6954, |
| 13929 | GIR_EraseRootFromParent_Done, |
| 13930 | // Label 771: @48976 |
| 13931 | GIM_Try, /*On fail goto*//*Label 772*/ GIMT_Encode4(49005), // Rule ID 6959 // |
| 13932 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13933 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13934 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13935 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8i64] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13937 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13938 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13939 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13940 | // GIR_Coverage, 6959, |
| 13941 | GIR_EraseRootFromParent_Done, |
| 13942 | // Label 772: @49005 |
| 13943 | GIM_Try, /*On fail goto*//*Label 773*/ GIMT_Encode4(49034), // Rule ID 6960 // |
| 13944 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13946 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13947 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v8f64] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13949 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13950 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13951 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13952 | // GIR_Coverage, 6960, |
| 13953 | GIR_EraseRootFromParent_Done, |
| 13954 | // Label 773: @49034 |
| 13955 | GIM_Try, /*On fail goto*//*Label 774*/ GIMT_Encode4(49063), // Rule ID 6963 // |
| 13956 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13958 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13959 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8i64] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 13960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13961 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13962 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13963 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13964 | // GIR_Coverage, 6963, |
| 13965 | GIR_EraseRootFromParent_Done, |
| 13966 | // Label 774: @49063 |
| 13967 | GIM_Try, /*On fail goto*//*Label 775*/ GIMT_Encode4(49092), // Rule ID 6964 // |
| 13968 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 13969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13971 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v8f64] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 13972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13973 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13974 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13975 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13976 | // GIR_Coverage, 6964, |
| 13977 | GIR_EraseRootFromParent_Done, |
| 13978 | // Label 775: @49092 |
| 13979 | GIM_Try, /*On fail goto*//*Label 776*/ GIMT_Encode4(49121), // Rule ID 6974 // |
| 13980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13982 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13983 | // (bitconvert:{ *:[v16i32] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v16i32] }:$src0 |
| 13984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13985 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13986 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13987 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 13988 | // GIR_Coverage, 6974, |
| 13989 | GIR_EraseRootFromParent_Done, |
| 13990 | // Label 776: @49121 |
| 13991 | GIM_Try, /*On fail goto*//*Label 777*/ GIMT_Encode4(49150), // Rule ID 6976 // |
| 13992 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 13993 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13994 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 13995 | // (bitconvert:{ *:[v16i32] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v16i32] }:$src0 |
| 13996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 13997 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 13998 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 13999 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14000 | // GIR_Coverage, 6976, |
| 14001 | GIR_EraseRootFromParent_Done, |
| 14002 | // Label 777: @49150 |
| 14003 | GIM_Try, /*On fail goto*//*Label 778*/ GIMT_Encode4(49179), // Rule ID 6978 // |
| 14004 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14006 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14007 | // (bitconvert:{ *:[v16f32] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v16f32] }:$src0 |
| 14008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14009 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14010 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14011 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14012 | // GIR_Coverage, 6978, |
| 14013 | GIR_EraseRootFromParent_Done, |
| 14014 | // Label 778: @49179 |
| 14015 | GIM_Try, /*On fail goto*//*Label 779*/ GIMT_Encode4(49208), // Rule ID 6980 // |
| 14016 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14018 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14019 | // (bitconvert:{ *:[v16f32] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v16f32] }:$src0 |
| 14020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14021 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14022 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14024 | // GIR_Coverage, 6980, |
| 14025 | GIR_EraseRootFromParent_Done, |
| 14026 | // Label 779: @49208 |
| 14027 | GIM_Reject, |
| 14028 | // Label 513: @49209 |
| 14029 | GIM_Try, /*On fail goto*//*Label 780*/ GIMT_Encode4(49238), // Rule ID 6991 // |
| 14030 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14032 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14033 | // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v16f64] }:$src0) => VReg_1024:{ *:[v16i64] }:$src0 |
| 14034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14035 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14036 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14037 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14038 | // GIR_Coverage, 6991, |
| 14039 | GIR_EraseRootFromParent_Done, |
| 14040 | // Label 780: @49238 |
| 14041 | GIM_Try, /*On fail goto*//*Label 781*/ GIMT_Encode4(49267), // Rule ID 6992 // |
| 14042 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14044 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14045 | // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v16i64] }:$src0) => VReg_1024:{ *:[v16f64] }:$src0 |
| 14046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14047 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14048 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14049 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14050 | // GIR_Coverage, 6992, |
| 14051 | GIR_EraseRootFromParent_Done, |
| 14052 | // Label 781: @49267 |
| 14053 | GIM_Try, /*On fail goto*//*Label 782*/ GIMT_Encode4(49296), // Rule ID 6993 // |
| 14054 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14056 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14057 | // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32i32] }:$src0) => VReg_1024:{ *:[v16i64] }:$src0 |
| 14058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14059 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14060 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14061 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14062 | // GIR_Coverage, 6993, |
| 14063 | GIR_EraseRootFromParent_Done, |
| 14064 | // Label 782: @49296 |
| 14065 | GIM_Try, /*On fail goto*//*Label 783*/ GIMT_Encode4(49325), // Rule ID 6995 // |
| 14066 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14068 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14069 | // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32f32] }:$src0) => VReg_1024:{ *:[v16f64] }:$src0 |
| 14070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14071 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14072 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14073 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14074 | // GIR_Coverage, 6995, |
| 14075 | GIR_EraseRootFromParent_Done, |
| 14076 | // Label 783: @49325 |
| 14077 | GIM_Try, /*On fail goto*//*Label 784*/ GIMT_Encode4(49354), // Rule ID 6997 // |
| 14078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14080 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14081 | // (bitconvert:{ *:[v16i64] } VReg_1024:{ *:[v32f32] }:$src0) => VReg_1024:{ *:[v16i64] }:$src0 |
| 14082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14083 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14084 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14085 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14086 | // GIR_Coverage, 6997, |
| 14087 | GIR_EraseRootFromParent_Done, |
| 14088 | // Label 784: @49354 |
| 14089 | GIM_Try, /*On fail goto*//*Label 785*/ GIMT_Encode4(49383), // Rule ID 6999 // |
| 14090 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14092 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14093 | // (bitconvert:{ *:[v16f64] } VReg_1024:{ *:[v32i32] }:$src0) => VReg_1024:{ *:[v16f64] }:$src0 |
| 14094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14095 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14096 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14097 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14098 | // GIR_Coverage, 6999, |
| 14099 | GIR_EraseRootFromParent_Done, |
| 14100 | // Label 785: @49383 |
| 14101 | GIM_Reject, |
| 14102 | // Label 514: @49384 |
| 14103 | GIM_Try, /*On fail goto*//*Label 786*/ GIMT_Encode4(49413), // Rule ID 6943 // |
| 14104 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14106 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14107 | // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v32i16] }:$src0) => VReg_512:{ *:[v32f16] }:$src0 |
| 14108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14109 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14110 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14111 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14112 | // GIR_Coverage, 6943, |
| 14113 | GIR_EraseRootFromParent_Done, |
| 14114 | // Label 786: @49413 |
| 14115 | GIM_Try, /*On fail goto*//*Label 787*/ GIMT_Encode4(49442), // Rule ID 6944 // |
| 14116 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14118 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14119 | // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v32f16] }:$src0) => VReg_512:{ *:[v32i16] }:$src0 |
| 14120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14121 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14122 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14123 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14124 | // GIR_Coverage, 6944, |
| 14125 | GIR_EraseRootFromParent_Done, |
| 14126 | // Label 787: @49442 |
| 14127 | GIM_Try, /*On fail goto*//*Label 788*/ GIMT_Encode4(49471), // Rule ID 6945 // |
| 14128 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14130 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14131 | // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v32f16] }:$src0 |
| 14132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14133 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14134 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14135 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14136 | // GIR_Coverage, 6945, |
| 14137 | GIR_EraseRootFromParent_Done, |
| 14138 | // Label 788: @49471 |
| 14139 | GIM_Try, /*On fail goto*//*Label 789*/ GIMT_Encode4(49500), // Rule ID 6946 // |
| 14140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14142 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14143 | // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v32f16] }:$src0 |
| 14144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14145 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14146 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14147 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14148 | // GIR_Coverage, 6946, |
| 14149 | GIR_EraseRootFromParent_Done, |
| 14150 | // Label 789: @49500 |
| 14151 | GIM_Try, /*On fail goto*//*Label 790*/ GIMT_Encode4(49529), // Rule ID 6949 // |
| 14152 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14154 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14155 | // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v32i16] }:$src0 |
| 14156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14157 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14158 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14159 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14160 | // GIR_Coverage, 6949, |
| 14161 | GIR_EraseRootFromParent_Done, |
| 14162 | // Label 790: @49529 |
| 14163 | GIM_Try, /*On fail goto*//*Label 791*/ GIMT_Encode4(49558), // Rule ID 6950 // |
| 14164 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14166 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14167 | // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v32i16] }:$src0 |
| 14168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14169 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14170 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14171 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14172 | // GIR_Coverage, 6950, |
| 14173 | GIR_EraseRootFromParent_Done, |
| 14174 | // Label 791: @49558 |
| 14175 | GIM_Try, /*On fail goto*//*Label 792*/ GIMT_Encode4(49587), // Rule ID 6965 // |
| 14176 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14178 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14179 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v32i16] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14181 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14182 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14183 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14184 | // GIR_Coverage, 6965, |
| 14185 | GIR_EraseRootFromParent_Done, |
| 14186 | // Label 792: @49587 |
| 14187 | GIM_Try, /*On fail goto*//*Label 793*/ GIMT_Encode4(49616), // Rule ID 6966 // |
| 14188 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14191 | // (bitconvert:{ *:[v32i16] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v32i16] }:$src0 |
| 14192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14193 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14194 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14195 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14196 | // GIR_Coverage, 6966, |
| 14197 | GIR_EraseRootFromParent_Done, |
| 14198 | // Label 793: @49616 |
| 14199 | GIM_Try, /*On fail goto*//*Label 794*/ GIMT_Encode4(49645), // Rule ID 6967 // |
| 14200 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14202 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14203 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v32i16] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14205 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14206 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14207 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14208 | // GIR_Coverage, 6967, |
| 14209 | GIR_EraseRootFromParent_Done, |
| 14210 | // Label 794: @49645 |
| 14211 | GIM_Try, /*On fail goto*//*Label 795*/ GIMT_Encode4(49674), // Rule ID 6968 // |
| 14212 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14214 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14215 | // (bitconvert:{ *:[v32i16] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v32i16] }:$src0 |
| 14216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14217 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14218 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14219 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14220 | // GIR_Coverage, 6968, |
| 14221 | GIR_EraseRootFromParent_Done, |
| 14222 | // Label 795: @49674 |
| 14223 | GIM_Try, /*On fail goto*//*Label 796*/ GIMT_Encode4(49703), // Rule ID 6969 // |
| 14224 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14226 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14227 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v32f16] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14229 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14230 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14231 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14232 | // GIR_Coverage, 6969, |
| 14233 | GIR_EraseRootFromParent_Done, |
| 14234 | // Label 796: @49703 |
| 14235 | GIM_Try, /*On fail goto*//*Label 797*/ GIMT_Encode4(49732), // Rule ID 6970 // |
| 14236 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14239 | // (bitconvert:{ *:[v32f16] } VReg_512:{ *:[v32bf16] }:$src0) => VReg_512:{ *:[v32f16] }:$src0 |
| 14240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14241 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14242 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14243 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14244 | // GIR_Coverage, 6970, |
| 14245 | GIR_EraseRootFromParent_Done, |
| 14246 | // Label 797: @49732 |
| 14247 | GIM_Try, /*On fail goto*//*Label 798*/ GIMT_Encode4(49761), // Rule ID 6971 // |
| 14248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14250 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14251 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v32f16] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14253 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14254 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14255 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14256 | // GIR_Coverage, 6971, |
| 14257 | GIR_EraseRootFromParent_Done, |
| 14258 | // Label 798: @49761 |
| 14259 | GIM_Try, /*On fail goto*//*Label 799*/ GIMT_Encode4(49790), // Rule ID 6972 // |
| 14260 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s16, |
| 14261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14262 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14263 | // (bitconvert:{ *:[v32f16] } SReg_512:{ *:[v32bf16] }:$src0) => SReg_512:{ *:[v32f16] }:$src0 |
| 14264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14265 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14266 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14267 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14268 | // GIR_Coverage, 6972, |
| 14269 | GIR_EraseRootFromParent_Done, |
| 14270 | // Label 799: @49790 |
| 14271 | GIM_Try, /*On fail goto*//*Label 800*/ GIMT_Encode4(49819), // Rule ID 6973 // |
| 14272 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14273 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14274 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14275 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v16i32] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14277 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14278 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14279 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14280 | // GIR_Coverage, 6973, |
| 14281 | GIR_EraseRootFromParent_Done, |
| 14282 | // Label 800: @49819 |
| 14283 | GIM_Try, /*On fail goto*//*Label 801*/ GIMT_Encode4(49848), // Rule ID 6975 // |
| 14284 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14287 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v16i32] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14289 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14290 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14291 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14292 | // GIR_Coverage, 6975, |
| 14293 | GIR_EraseRootFromParent_Done, |
| 14294 | // Label 801: @49848 |
| 14295 | GIM_Try, /*On fail goto*//*Label 802*/ GIMT_Encode4(49877), // Rule ID 6977 // |
| 14296 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14298 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14299 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v16f32] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14301 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14302 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14303 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14304 | // GIR_Coverage, 6977, |
| 14305 | GIR_EraseRootFromParent_Done, |
| 14306 | // Label 802: @49877 |
| 14307 | GIM_Try, /*On fail goto*//*Label 803*/ GIMT_Encode4(49906), // Rule ID 6979 // |
| 14308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s32, |
| 14309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14310 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14311 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v16f32] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14313 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14314 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14315 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14316 | // GIR_Coverage, 6979, |
| 14317 | GIR_EraseRootFromParent_Done, |
| 14318 | // Label 803: @49906 |
| 14319 | GIM_Try, /*On fail goto*//*Label 804*/ GIMT_Encode4(49935), // Rule ID 6981 // |
| 14320 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 14321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14322 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14323 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v8f64] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14325 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14326 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14327 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14328 | // GIR_Coverage, 6981, |
| 14329 | GIR_EraseRootFromParent_Done, |
| 14330 | // Label 804: @49935 |
| 14331 | GIM_Try, /*On fail goto*//*Label 805*/ GIMT_Encode4(49964), // Rule ID 6983 // |
| 14332 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 14333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14334 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14335 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v8f64] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14337 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14338 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14339 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14340 | // GIR_Coverage, 6983, |
| 14341 | GIR_EraseRootFromParent_Done, |
| 14342 | // Label 805: @49964 |
| 14343 | GIM_Try, /*On fail goto*//*Label 806*/ GIMT_Encode4(49993), // Rule ID 6985 // |
| 14344 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 14345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14346 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14347 | // (bitconvert:{ *:[v32bf16] } VReg_512:{ *:[v8i64] }:$src0) => VReg_512:{ *:[v32bf16] }:$src0 |
| 14348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14349 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14350 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14351 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 14352 | // GIR_Coverage, 6985, |
| 14353 | GIR_EraseRootFromParent_Done, |
| 14354 | // Label 806: @49993 |
| 14355 | GIM_Try, /*On fail goto*//*Label 807*/ GIMT_Encode4(50022), // Rule ID 6987 // |
| 14356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v8s64, |
| 14357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14358 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14359 | // (bitconvert:{ *:[v32bf16] } SReg_512:{ *:[v8i64] }:$src0) => SReg_512:{ *:[v32bf16] }:$src0 |
| 14360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14361 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14362 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14363 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 14364 | // GIR_Coverage, 6987, |
| 14365 | GIR_EraseRootFromParent_Done, |
| 14366 | // Label 807: @50022 |
| 14367 | GIM_Reject, |
| 14368 | // Label 515: @50023 |
| 14369 | GIM_Try, /*On fail goto*//*Label 808*/ GIMT_Encode4(50052), // Rule ID 6989 // |
| 14370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14372 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14373 | // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v32f32] }:$src0) => VReg_1024:{ *:[v32i32] }:$src0 |
| 14374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14375 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14376 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14377 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14378 | // GIR_Coverage, 6989, |
| 14379 | GIR_EraseRootFromParent_Done, |
| 14380 | // Label 808: @50052 |
| 14381 | GIM_Try, /*On fail goto*//*Label 809*/ GIMT_Encode4(50081), // Rule ID 6990 // |
| 14382 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v32s32, |
| 14383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14384 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14385 | // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v32i32] }:$src0) => VReg_1024:{ *:[v32f32] }:$src0 |
| 14386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14387 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14388 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14389 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14390 | // GIR_Coverage, 6990, |
| 14391 | GIR_EraseRootFromParent_Done, |
| 14392 | // Label 809: @50081 |
| 14393 | GIM_Try, /*On fail goto*//*Label 810*/ GIMT_Encode4(50110), // Rule ID 6994 // |
| 14394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14396 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14397 | // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16i64] }:$src0) => VReg_1024:{ *:[v32i32] }:$src0 |
| 14398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14399 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14400 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14401 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14402 | // GIR_Coverage, 6994, |
| 14403 | GIR_EraseRootFromParent_Done, |
| 14404 | // Label 810: @50110 |
| 14405 | GIM_Try, /*On fail goto*//*Label 811*/ GIMT_Encode4(50139), // Rule ID 6996 // |
| 14406 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14408 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14409 | // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16f64] }:$src0) => VReg_1024:{ *:[v32f32] }:$src0 |
| 14410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14411 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14412 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14413 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14414 | // GIR_Coverage, 6996, |
| 14415 | GIR_EraseRootFromParent_Done, |
| 14416 | // Label 811: @50139 |
| 14417 | GIM_Try, /*On fail goto*//*Label 812*/ GIMT_Encode4(50168), // Rule ID 6998 // |
| 14418 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14420 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14421 | // (bitconvert:{ *:[v32i32] } VReg_1024:{ *:[v16f64] }:$src0) => VReg_1024:{ *:[v32i32] }:$src0 |
| 14422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14423 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14424 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14425 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14426 | // GIR_Coverage, 6998, |
| 14427 | GIR_EraseRootFromParent_Done, |
| 14428 | // Label 812: @50168 |
| 14429 | GIM_Try, /*On fail goto*//*Label 813*/ GIMT_Encode4(50197), // Rule ID 7000 // |
| 14430 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v16s64, |
| 14431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14432 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14433 | // (bitconvert:{ *:[v32f32] } VReg_1024:{ *:[v16i64] }:$src0) => VReg_1024:{ *:[v32f32] }:$src0 |
| 14434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 14435 | GIR_RootToRootCopy, /*OpIdx*/0, // dst |
| 14436 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 14437 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 14438 | // GIR_Coverage, 7000, |
| 14439 | GIR_EraseRootFromParent_Done, |
| 14440 | // Label 813: @50197 |
| 14441 | GIM_Reject, |
| 14442 | // Label 516: @50198 |
| 14443 | GIM_Reject, |
| 14444 | // Label 9: @50199 |
| 14445 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 817*/ GIMT_Encode4(50526), |
| 14446 | /*GILLT_s16*//*Label 814*/ GIMT_Encode4(50222), |
| 14447 | /*GILLT_s32*//*Label 815*/ GIMT_Encode4(50396), |
| 14448 | /*GILLT_s64*//*Label 816*/ GIMT_Encode4(50476), |
| 14449 | // Label 814: @50222 |
| 14450 | GIM_Try, /*On fail goto*//*Label 818*/ GIMT_Encode4(50395), |
| 14451 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 14452 | GIM_Try, /*On fail goto*//*Label 819*/ GIMT_Encode4(50257), // Rule ID 39 // |
| 14453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 14454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 14455 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18494), |
| 14456 | // (ftrunc:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_18494>> => (S_TRUNC_F16:{ *:[f16] } f16:{ *:[f16] }:$src0) |
| 14457 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F16), |
| 14458 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 14459 | GIR_RootConstrainSelectedInstOperands, |
| 14460 | // GIR_Coverage, 39, |
| 14461 | GIR_Done, |
| 14462 | // Label 819: @50257 |
| 14463 | GIM_Try, /*On fail goto*//*Label 820*/ GIMT_Encode4(50303), // Rule ID 709 // |
| 14464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 14465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14467 | // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_TRUNC_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_e64), |
| 14469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14474 | GIR_RootConstrainSelectedInstOperands, |
| 14475 | // GIR_Coverage, 709, |
| 14476 | GIR_EraseRootFromParent_Done, |
| 14477 | // Label 820: @50303 |
| 14478 | GIM_Try, /*On fail goto*//*Label 821*/ GIMT_Encode4(50349), // Rule ID 711 // |
| 14479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 14480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14482 | // (ftrunc:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_TRUNC_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_fake16_e64), |
| 14484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14489 | GIR_RootConstrainSelectedInstOperands, |
| 14490 | // GIR_Coverage, 711, |
| 14491 | GIR_EraseRootFromParent_Done, |
| 14492 | // Label 821: @50349 |
| 14493 | GIM_Try, /*On fail goto*//*Label 822*/ GIMT_Encode4(50394), // Rule ID 710 // |
| 14494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 14495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 14496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 14497 | // (ftrunc:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_TRUNC_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 14498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F16_t16_e64), |
| 14499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14505 | GIR_RootConstrainSelectedInstOperands, |
| 14506 | // GIR_Coverage, 710, |
| 14507 | GIR_EraseRootFromParent_Done, |
| 14508 | // Label 822: @50394 |
| 14509 | GIM_Reject, |
| 14510 | // Label 818: @50395 |
| 14511 | GIM_Reject, |
| 14512 | // Label 815: @50396 |
| 14513 | GIM_Try, /*On fail goto*//*Label 823*/ GIMT_Encode4(50475), |
| 14514 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14515 | GIM_Try, /*On fail goto*//*Label 824*/ GIMT_Encode4(50431), // Rule ID 34 // |
| 14516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 14517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 14518 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18494), |
| 14519 | // (ftrunc:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18494>> => (S_TRUNC_F32:{ *:[f32] } f32:{ *:[f32] }:$src0) |
| 14520 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_TRUNC_F32), |
| 14521 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 14522 | GIR_RootConstrainSelectedInstOperands, |
| 14523 | // GIR_Coverage, 34, |
| 14524 | GIR_Done, |
| 14525 | // Label 824: @50431 |
| 14526 | GIM_Try, /*On fail goto*//*Label 825*/ GIMT_Encode4(50474), // Rule ID 600 // |
| 14527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14529 | // (ftrunc:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_TRUNC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F32_e64), |
| 14531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14536 | GIR_RootConstrainSelectedInstOperands, |
| 14537 | // GIR_Coverage, 600, |
| 14538 | GIR_EraseRootFromParent_Done, |
| 14539 | // Label 825: @50474 |
| 14540 | GIM_Reject, |
| 14541 | // Label 823: @50475 |
| 14542 | GIM_Reject, |
| 14543 | // Label 816: @50476 |
| 14544 | GIM_Try, /*On fail goto*//*Label 826*/ GIMT_Encode4(50525), // Rule ID 644 // |
| 14545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus), |
| 14546 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 14548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14549 | // (ftrunc:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_TRUNC_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRUNC_F64_e64), |
| 14551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14556 | GIR_RootConstrainSelectedInstOperands, |
| 14557 | // GIR_Coverage, 644, |
| 14558 | GIR_EraseRootFromParent_Done, |
| 14559 | // Label 826: @50525 |
| 14560 | GIM_Reject, |
| 14561 | // Label 817: @50526 |
| 14562 | GIM_Reject, |
| 14563 | // Label 10: @50527 |
| 14564 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 830*/ GIMT_Encode4(50854), |
| 14565 | /*GILLT_s16*//*Label 827*/ GIMT_Encode4(50550), |
| 14566 | /*GILLT_s32*//*Label 828*/ GIMT_Encode4(50724), |
| 14567 | /*GILLT_s64*//*Label 829*/ GIMT_Encode4(50804), |
| 14568 | // Label 827: @50550 |
| 14569 | GIM_Try, /*On fail goto*//*Label 831*/ GIMT_Encode4(50723), |
| 14570 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 14571 | GIM_Try, /*On fail goto*//*Label 832*/ GIMT_Encode4(50585), // Rule ID 40 // |
| 14572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 14573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 14574 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18495), |
| 14575 | // (froundeven:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_18495>> => (S_RNDNE_F16:{ *:[f16] } f16:{ *:[f16] }:$src0) |
| 14576 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F16), |
| 14577 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 14578 | GIR_RootConstrainSelectedInstOperands, |
| 14579 | // GIR_Coverage, 40, |
| 14580 | GIR_Done, |
| 14581 | // Label 832: @50585 |
| 14582 | GIM_Try, /*On fail goto*//*Label 833*/ GIMT_Encode4(50631), // Rule ID 712 // |
| 14583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 14584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14586 | // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RNDNE_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_e64), |
| 14588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14593 | GIR_RootConstrainSelectedInstOperands, |
| 14594 | // GIR_Coverage, 712, |
| 14595 | GIR_EraseRootFromParent_Done, |
| 14596 | // Label 833: @50631 |
| 14597 | GIM_Try, /*On fail goto*//*Label 834*/ GIMT_Encode4(50677), // Rule ID 714 // |
| 14598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 14599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14601 | // (froundeven:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RNDNE_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_fake16_e64), |
| 14603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14608 | GIR_RootConstrainSelectedInstOperands, |
| 14609 | // GIR_Coverage, 714, |
| 14610 | GIR_EraseRootFromParent_Done, |
| 14611 | // Label 834: @50677 |
| 14612 | GIM_Try, /*On fail goto*//*Label 835*/ GIMT_Encode4(50722), // Rule ID 713 // |
| 14613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 14614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 14615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 14616 | // (froundeven:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_RNDNE_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 14617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F16_t16_e64), |
| 14618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14624 | GIR_RootConstrainSelectedInstOperands, |
| 14625 | // GIR_Coverage, 713, |
| 14626 | GIR_EraseRootFromParent_Done, |
| 14627 | // Label 835: @50722 |
| 14628 | GIM_Reject, |
| 14629 | // Label 831: @50723 |
| 14630 | GIM_Reject, |
| 14631 | // Label 828: @50724 |
| 14632 | GIM_Try, /*On fail goto*//*Label 836*/ GIMT_Encode4(50803), |
| 14633 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 14634 | GIM_Try, /*On fail goto*//*Label 837*/ GIMT_Encode4(50759), // Rule ID 35 // |
| 14635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 14636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 14637 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18495), |
| 14638 | // (froundeven:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18495>> => (S_RNDNE_F32:{ *:[f32] } f32:{ *:[f32] }:$src0) |
| 14639 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_RNDNE_F32), |
| 14640 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 14641 | GIR_RootConstrainSelectedInstOperands, |
| 14642 | // GIR_Coverage, 35, |
| 14643 | GIR_Done, |
| 14644 | // Label 837: @50759 |
| 14645 | GIM_Try, /*On fail goto*//*Label 838*/ GIMT_Encode4(50802), // Rule ID 602 // |
| 14646 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 14647 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14648 | // (froundeven:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RNDNE_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F32_e64), |
| 14650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14655 | GIR_RootConstrainSelectedInstOperands, |
| 14656 | // GIR_Coverage, 602, |
| 14657 | GIR_EraseRootFromParent_Done, |
| 14658 | // Label 838: @50802 |
| 14659 | GIM_Reject, |
| 14660 | // Label 836: @50803 |
| 14661 | GIM_Reject, |
| 14662 | // Label 829: @50804 |
| 14663 | GIM_Try, /*On fail goto*//*Label 839*/ GIMT_Encode4(50853), // Rule ID 646 // |
| 14664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus), |
| 14665 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 14666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 14667 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 14668 | // (froundeven:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RNDNE_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 14669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RNDNE_F64_e64), |
| 14670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 14672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 14673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 14674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 14675 | GIR_RootConstrainSelectedInstOperands, |
| 14676 | // GIR_Coverage, 646, |
| 14677 | GIR_EraseRootFromParent_Done, |
| 14678 | // Label 839: @50853 |
| 14679 | GIM_Reject, |
| 14680 | // Label 830: @50854 |
| 14681 | GIM_Reject, |
| 14682 | // Label 11: @50855 |
| 14683 | GIM_Try, /*On fail goto*//*Label 840*/ GIMT_Encode4(50994), |
| 14684 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14685 | GIM_Try, /*On fail goto*//*Label 841*/ GIMT_Encode4(50888), // Rule ID 1118 // |
| 14686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesHiLoRegisters), |
| 14687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 14688 | // (readcyclecounter:{ *:[i64] }) => (GET_SHADERCYCLESHILO:{ *:[i64] }:{ *:[i1] }) |
| 14689 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::GET_SHADERCYCLESHILO), |
| 14690 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 14691 | GIR_RootConstrainSelectedInstOperands, |
| 14692 | // GIR_Coverage, 1118, |
| 14693 | GIR_Done, |
| 14694 | // Label 841: @50888 |
| 14695 | GIM_Try, /*On fail goto*//*Label 842*/ GIMT_Encode4(50907), // Rule ID 3179 // |
| 14696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst), |
| 14697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14698 | // (readcyclecounter:{ *:[i64] }) => (S_MEMTIME:{ *:[i64] }) |
| 14699 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME), |
| 14700 | GIR_RootConstrainSelectedInstOperands, |
| 14701 | // GIR_Coverage, 3179, |
| 14702 | GIR_Done, |
| 14703 | // Label 842: @50907 |
| 14704 | GIM_Try, /*On fail goto*//*Label 843*/ GIMT_Encode4(50993), // Rule ID 3180 // |
| 14705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasShaderCyclesRegister), |
| 14706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 14707 | // (readcyclecounter:{ *:[i64] }) => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 38941:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 14708 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 14709 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 14710 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 14711 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14712 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 14713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 14714 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32), |
| 14715 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 14716 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(38941), |
| 14717 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 14718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 14719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 14720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 14721 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 14722 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 14723 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 14724 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 14725 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 14726 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 14727 | // GIR_Coverage, 3180, |
| 14728 | GIR_EraseRootFromParent_Done, |
| 14729 | // Label 843: @50993 |
| 14730 | GIM_Reject, |
| 14731 | // Label 840: @50994 |
| 14732 | GIM_Reject, |
| 14733 | // Label 12: @50995 |
| 14734 | GIM_Try, /*On fail goto*//*Label 844*/ GIMT_Encode4(51052), |
| 14735 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 14736 | GIM_Try, /*On fail goto*//*Label 845*/ GIMT_Encode4(51022), // Rule ID 3181 // |
| 14737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemRealTime), |
| 14738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14739 | // (readsteadycounter:{ *:[i64] }) => (S_MEMREALTIME:{ *:[i64] }) |
| 14740 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMREALTIME), |
| 14741 | GIR_RootConstrainSelectedInstOperands, |
| 14742 | // GIR_Coverage, 3181, |
| 14743 | GIR_Done, |
| 14744 | // Label 845: @51022 |
| 14745 | GIM_Try, /*On fail goto*//*Label 846*/ GIMT_Encode4(51051), // Rule ID 3182 // |
| 14746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 14747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 14748 | // (readsteadycounter:{ *:[i64] }) => (S_SENDMSG_RTN_B64:{ *:[i64] } 131:{ *:[i32] }) |
| 14749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B64), |
| 14750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14751 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(131), |
| 14752 | GIR_RootConstrainSelectedInstOperands, |
| 14753 | // GIR_Coverage, 3182, |
| 14754 | GIR_EraseRootFromParent_Done, |
| 14755 | // Label 846: @51051 |
| 14756 | GIM_Reject, |
| 14757 | // Label 844: @51052 |
| 14758 | GIM_Reject, |
| 14759 | // Label 13: @51053 |
| 14760 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(33), /*)*//*default:*//*Label 871*/ GIMT_Encode4(126441), |
| 14761 | /*GILLT_p0s64*//*Label 847*/ GIMT_Encode4(51196), |
| 14762 | /*GILLT_p1s64*//*Label 848*/ GIMT_Encode4(53190), |
| 14763 | /*GILLT_p2s32*//*Label 849*/ GIMT_Encode4(55184), |
| 14764 | /*GILLT_p3s32*//*Label 850*/ GIMT_Encode4(56886), |
| 14765 | /*GILLT_p4s64*//*Label 851*/ GIMT_Encode4(58588), |
| 14766 | /*GILLT_p5s32*//*Label 852*/ GIMT_Encode4(60582), |
| 14767 | /*GILLT_p6s32*//*Label 853*/ GIMT_Encode4(62284), |
| 14768 | /*GILLT_s1*//*Label 854*/ GIMT_Encode4(63986), |
| 14769 | /*GILLT_s16*//*Label 855*/ GIMT_Encode4(64619), |
| 14770 | /*GILLT_s32*//*Label 856*/ GIMT_Encode4(67854), |
| 14771 | /*GILLT_s64*//*Label 857*/ GIMT_Encode4(75882), |
| 14772 | /*GILLT_v2s16*//*Label 858*/ GIMT_Encode4(81272), |
| 14773 | /*GILLT_v2s32*//*Label 859*/ GIMT_Encode4(86376), |
| 14774 | /*GILLT_v2s64*//*Label 860*/ GIMT_Encode4(90625), |
| 14775 | /*GILLT_v3s32*//*Label 861*/ GIMT_Encode4(94612), GIMT_Encode4(0), |
| 14776 | /*GILLT_v4s16*//*Label 862*/ GIMT_Encode4(97990), |
| 14777 | /*GILLT_v4s32*//*Label 863*/ GIMT_Encode4(103970), |
| 14778 | /*GILLT_v4s64*//*Label 864*/ GIMT_Encode4(108219), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14779 | /*GILLT_v8s16*//*Label 865*/ GIMT_Encode4(109970), |
| 14780 | /*GILLT_v8s32*//*Label 866*/ GIMT_Encode4(115950), |
| 14781 | /*GILLT_v8s64*//*Label 867*/ GIMT_Encode4(117701), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 14782 | /*GILLT_v16s16*//*Label 868*/ GIMT_Encode4(119452), |
| 14783 | /*GILLT_v16s32*//*Label 869*/ GIMT_Encode4(122071), GIMT_Encode4(0), |
| 14784 | /*GILLT_v32s16*//*Label 870*/ GIMT_Encode4(123822), |
| 14785 | // Label 847: @51196 |
| 14786 | GIM_Try, /*On fail goto*//*Label 872*/ GIMT_Encode4(51263), // Rule ID 7995 // |
| 14787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 14788 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14792 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 14794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 14795 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 14797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 14801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14803 | GIR_RootConstrainSelectedInstOperands, |
| 14804 | // GIR_Coverage, 7995, |
| 14805 | GIR_EraseRootFromParent_Done, |
| 14806 | // Label 872: @51263 |
| 14807 | GIM_Try, /*On fail goto*//*Label 873*/ GIMT_Encode4(51326), // Rule ID 8000 // |
| 14808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 14809 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14812 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14813 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 14815 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 14817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 14821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14823 | GIR_RootConstrainSelectedInstOperands, |
| 14824 | // GIR_Coverage, 8000, |
| 14825 | GIR_EraseRootFromParent_Done, |
| 14826 | // Label 873: @51326 |
| 14827 | GIM_Try, /*On fail goto*//*Label 874*/ GIMT_Encode4(51389), // Rule ID 8006 // |
| 14828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 14829 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14830 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14832 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14833 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14834 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 14835 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 14837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 14841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14842 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14843 | GIR_RootConstrainSelectedInstOperands, |
| 14844 | // GIR_Coverage, 8006, |
| 14845 | GIR_EraseRootFromParent_Done, |
| 14846 | // Label 874: @51389 |
| 14847 | GIM_Try, /*On fail goto*//*Label 875*/ GIMT_Encode4(51451), // Rule ID 7991 // |
| 14848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 14849 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14850 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14852 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14853 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14854 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 14855 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 14856 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 14858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 14861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14862 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14863 | GIR_RootConstrainSelectedInstOperands, |
| 14864 | // GIR_Coverage, 7991, |
| 14865 | GIR_EraseRootFromParent_Done, |
| 14866 | // Label 875: @51451 |
| 14867 | GIM_Try, /*On fail goto*//*Label 876*/ GIMT_Encode4(51513), // Rule ID 7992 // |
| 14868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 14869 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14872 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14873 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14874 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 14875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 14876 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 14878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 14881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14883 | GIR_RootConstrainSelectedInstOperands, |
| 14884 | // GIR_Coverage, 7992, |
| 14885 | GIR_EraseRootFromParent_Done, |
| 14886 | // Label 876: @51513 |
| 14887 | GIM_Try, /*On fail goto*//*Label 877*/ GIMT_Encode4(51575), // Rule ID 7993 // |
| 14888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 14889 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14892 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14893 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14894 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 14895 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 14896 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 14897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 14898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14903 | GIR_RootConstrainSelectedInstOperands, |
| 14904 | // GIR_Coverage, 7993, |
| 14905 | GIR_EraseRootFromParent_Done, |
| 14906 | // Label 877: @51575 |
| 14907 | GIM_Try, /*On fail goto*//*Label 878*/ GIMT_Encode4(51640), // Rule ID 7994 // |
| 14908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 14909 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14910 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14913 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 14915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 14916 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 14917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 14918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14924 | GIR_RootConstrainSelectedInstOperands, |
| 14925 | // GIR_Coverage, 7994, |
| 14926 | GIR_EraseRootFromParent_Done, |
| 14927 | // Label 878: @51640 |
| 14928 | GIM_Try, /*On fail goto*//*Label 879*/ GIMT_Encode4(51698), // Rule ID 7997 // |
| 14929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 14930 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14931 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14933 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14934 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14935 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 14936 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 14937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 14938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 14941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14943 | GIR_RootConstrainSelectedInstOperands, |
| 14944 | // GIR_Coverage, 7997, |
| 14945 | GIR_EraseRootFromParent_Done, |
| 14946 | // Label 879: @51698 |
| 14947 | GIM_Try, /*On fail goto*//*Label 880*/ GIMT_Encode4(51756), // Rule ID 7998 // |
| 14948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 14949 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14950 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14953 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14954 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 14955 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 14956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 14957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14961 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14962 | GIR_RootConstrainSelectedInstOperands, |
| 14963 | // GIR_Coverage, 7998, |
| 14964 | GIR_EraseRootFromParent_Done, |
| 14965 | // Label 880: @51756 |
| 14966 | GIM_Try, /*On fail goto*//*Label 881*/ GIMT_Encode4(51817), // Rule ID 7999 // |
| 14967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 14968 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14969 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 14971 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 14973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 14974 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 14975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 14976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 14977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 14978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 14979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 14981 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 14982 | GIR_RootConstrainSelectedInstOperands, |
| 14983 | // GIR_Coverage, 7999, |
| 14984 | GIR_EraseRootFromParent_Done, |
| 14985 | // Label 881: @51817 |
| 14986 | GIM_Try, /*On fail goto*//*Label 882*/ GIMT_Encode4(51885), // Rule ID 7711 // |
| 14987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 14988 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 14989 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 14990 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 14991 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 14992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 14993 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 14994 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 14995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 14996 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 14997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 14998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 14999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15002 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15003 | GIR_RootConstrainSelectedInstOperands, |
| 15004 | // GIR_Coverage, 7711, |
| 15005 | GIR_EraseRootFromParent_Done, |
| 15006 | // Label 882: @51885 |
| 15007 | GIM_Try, /*On fail goto*//*Label 883*/ GIMT_Encode4(51948), // Rule ID 7635 // |
| 15008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 15009 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15010 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15011 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 15012 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15014 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15016 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 15018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15023 | GIR_RootConstrainSelectedInstOperands, |
| 15024 | // GIR_Coverage, 7635, |
| 15025 | GIR_EraseRootFromParent_Done, |
| 15026 | // Label 883: @51948 |
| 15027 | GIM_Try, /*On fail goto*//*Label 884*/ GIMT_Encode4(52003), // Rule ID 8002 // |
| 15028 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15029 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15031 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15032 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 15034 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15041 | GIR_RootConstrainSelectedInstOperands, |
| 15042 | // GIR_Coverage, 8002, |
| 15043 | GIR_EraseRootFromParent_Done, |
| 15044 | // Label 884: @52003 |
| 15045 | GIM_Try, /*On fail goto*//*Label 885*/ GIMT_Encode4(52061), // Rule ID 8003 // |
| 15046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 15047 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15048 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15051 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 15053 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 15055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15059 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15060 | GIR_RootConstrainSelectedInstOperands, |
| 15061 | // GIR_Coverage, 8003, |
| 15062 | GIR_EraseRootFromParent_Done, |
| 15063 | // Label 885: @52061 |
| 15064 | GIM_Try, /*On fail goto*//*Label 886*/ GIMT_Encode4(52119), // Rule ID 8004 // |
| 15065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 15066 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15067 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15069 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15070 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15072 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 15073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 15074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15079 | GIR_RootConstrainSelectedInstOperands, |
| 15080 | // GIR_Coverage, 8004, |
| 15081 | GIR_EraseRootFromParent_Done, |
| 15082 | // Label 886: @52119 |
| 15083 | GIM_Try, /*On fail goto*//*Label 887*/ GIMT_Encode4(52180), // Rule ID 8005 // |
| 15084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 15085 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15089 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15091 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 15093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15099 | GIR_RootConstrainSelectedInstOperands, |
| 15100 | // GIR_Coverage, 8005, |
| 15101 | GIR_EraseRootFromParent_Done, |
| 15102 | // Label 887: @52180 |
| 15103 | GIM_Try, /*On fail goto*//*Label 888*/ GIMT_Encode4(52244), // Rule ID 7712 // |
| 15104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 15105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15106 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15107 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15109 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15110 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 15111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15112 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 15114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15119 | GIR_RootConstrainSelectedInstOperands, |
| 15120 | // GIR_Coverage, 7712, |
| 15121 | GIR_EraseRootFromParent_Done, |
| 15122 | // Label 888: @52244 |
| 15123 | GIM_Try, /*On fail goto*//*Label 889*/ GIMT_Encode4(52303), // Rule ID 7636 // |
| 15124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 15125 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15126 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 15127 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15131 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 15133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15138 | GIR_RootConstrainSelectedInstOperands, |
| 15139 | // GIR_Coverage, 7636, |
| 15140 | GIR_EraseRootFromParent_Done, |
| 15141 | // Label 889: @52303 |
| 15142 | GIM_Try, /*On fail goto*//*Label 890*/ GIMT_Encode4(52357), // Rule ID 7996 // |
| 15143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15144 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15147 | // MIs[0] sbase |
| 15148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15149 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15150 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15151 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15152 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15155 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15159 | GIR_RootConstrainSelectedInstOperands, |
| 15160 | // GIR_Coverage, 7996, |
| 15161 | GIR_EraseRootFromParent_Done, |
| 15162 | // Label 890: @52357 |
| 15163 | GIM_Try, /*On fail goto*//*Label 891*/ GIMT_Encode4(52407), // Rule ID 8001 // |
| 15164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15165 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15166 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15168 | // MIs[0] sbase |
| 15169 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15170 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15171 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15172 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 15174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15175 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15178 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15179 | GIR_RootConstrainSelectedInstOperands, |
| 15180 | // GIR_Coverage, 8001, |
| 15181 | GIR_EraseRootFromParent_Done, |
| 15182 | // Label 891: @52407 |
| 15183 | GIM_Try, /*On fail goto*//*Label 892*/ GIMT_Encode4(52454), // Rule ID 8007 // |
| 15184 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15185 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15187 | // MIs[0] sbase |
| 15188 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15189 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15190 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15191 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15194 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15198 | GIR_RootConstrainSelectedInstOperands, |
| 15199 | // GIR_Coverage, 8007, |
| 15200 | GIR_EraseRootFromParent_Done, |
| 15201 | // Label 892: @52454 |
| 15202 | GIM_Try, /*On fail goto*//*Label 893*/ GIMT_Encode4(52514), // Rule ID 3972 // |
| 15203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 15204 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15205 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15207 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15208 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 15209 | // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 15211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 15214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15217 | GIR_RootConstrainSelectedInstOperands, |
| 15218 | // GIR_Coverage, 3972, |
| 15219 | GIR_EraseRootFromParent_Done, |
| 15220 | // Label 893: @52514 |
| 15221 | GIM_Try, /*On fail goto*//*Label 894*/ GIMT_Encode4(52569), // Rule ID 3971 // |
| 15222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 15223 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15224 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15226 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 15228 | // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 15229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 15230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 15232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15235 | GIR_RootConstrainSelectedInstOperands, |
| 15236 | // GIR_Coverage, 3971, |
| 15237 | GIR_EraseRootFromParent_Done, |
| 15238 | // Label 894: @52569 |
| 15239 | GIM_Try, /*On fail goto*//*Label 895*/ GIMT_Encode4(52624), // Rule ID 3970 // |
| 15240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 15241 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 15246 | // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 15247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 15248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15253 | GIR_RootConstrainSelectedInstOperands, |
| 15254 | // GIR_Coverage, 3970, |
| 15255 | GIR_EraseRootFromParent_Done, |
| 15256 | // Label 895: @52624 |
| 15257 | GIM_Try, /*On fail goto*//*Label 896*/ GIMT_Encode4(52694), // Rule ID 4194 // |
| 15258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 15259 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15260 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15262 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15263 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 15264 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 15266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 15268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 15270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 15271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15274 | GIR_RootConstrainSelectedInstOperands, |
| 15275 | // GIR_Coverage, 4194, |
| 15276 | GIR_EraseRootFromParent_Done, |
| 15277 | // Label 896: @52694 |
| 15278 | GIM_Try, /*On fail goto*//*Label 897*/ GIMT_Encode4(52761), // Rule ID 4196 // |
| 15279 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15280 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 15284 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 15286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 15288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 15290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 15291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15293 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15294 | GIR_RootConstrainSelectedInstOperands, |
| 15295 | // GIR_Coverage, 4196, |
| 15296 | GIR_EraseRootFromParent_Done, |
| 15297 | // Label 897: @52761 |
| 15298 | GIM_Try, /*On fail goto*//*Label 898*/ GIMT_Encode4(52825), // Rule ID 7571 // |
| 15299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 15300 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15301 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 15306 | // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 15307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 15308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 15311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 15312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15313 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15314 | GIR_RootConstrainSelectedInstOperands, |
| 15315 | // GIR_Coverage, 7571, |
| 15316 | GIR_EraseRootFromParent_Done, |
| 15317 | // Label 898: @52825 |
| 15318 | GIM_Try, /*On fail goto*//*Label 899*/ GIMT_Encode4(52890), // Rule ID 4193 // |
| 15319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 15320 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 15325 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 15327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15334 | GIR_RootConstrainSelectedInstOperands, |
| 15335 | // GIR_Coverage, 4193, |
| 15336 | GIR_EraseRootFromParent_Done, |
| 15337 | // Label 899: @52890 |
| 15338 | GIM_Try, /*On fail goto*//*Label 900*/ GIMT_Encode4(52952), // Rule ID 4195 // |
| 15339 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15340 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15342 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15343 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 15344 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 15346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15352 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15353 | GIR_RootConstrainSelectedInstOperands, |
| 15354 | // GIR_Coverage, 4195, |
| 15355 | GIR_EraseRootFromParent_Done, |
| 15356 | // Label 900: @52952 |
| 15357 | GIM_Try, /*On fail goto*//*Label 901*/ GIMT_Encode4(53012), // Rule ID 7573 // |
| 15358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 15359 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 15364 | // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 15365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 15366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 15369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 15370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15372 | GIR_RootConstrainSelectedInstOperands, |
| 15373 | // GIR_Coverage, 7573, |
| 15374 | GIR_EraseRootFromParent_Done, |
| 15375 | // Label 901: @53012 |
| 15376 | GIM_Try, /*On fail goto*//*Label 902*/ GIMT_Encode4(53074), // Rule ID 3513 // |
| 15377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 15378 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15379 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 15383 | // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 15385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 15387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 15388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15390 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15391 | GIR_RootConstrainSelectedInstOperands, |
| 15392 | // GIR_Coverage, 3513, |
| 15393 | GIR_EraseRootFromParent_Done, |
| 15394 | // Label 902: @53074 |
| 15395 | GIM_Try, /*On fail goto*//*Label 903*/ GIMT_Encode4(53131), // Rule ID 3512 // |
| 15396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 15397 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 15402 | // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 15403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 15404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15409 | GIR_RootConstrainSelectedInstOperands, |
| 15410 | // GIR_Coverage, 3512, |
| 15411 | GIR_EraseRootFromParent_Done, |
| 15412 | // Label 903: @53131 |
| 15413 | GIM_Try, /*On fail goto*//*Label 904*/ GIMT_Encode4(53189), // Rule ID 3262 // |
| 15414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 15415 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15416 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15418 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15419 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 15420 | // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 15421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 15422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15426 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15427 | GIR_RootConstrainSelectedInstOperands, |
| 15428 | // GIR_Coverage, 3262, |
| 15429 | GIR_EraseRootFromParent_Done, |
| 15430 | // Label 904: @53189 |
| 15431 | GIM_Reject, |
| 15432 | // Label 848: @53190 |
| 15433 | GIM_Try, /*On fail goto*//*Label 905*/ GIMT_Encode4(53257), // Rule ID 8012 // |
| 15434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 15435 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15436 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15439 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15440 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15441 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 15442 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 15444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15449 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15450 | GIR_RootConstrainSelectedInstOperands, |
| 15451 | // GIR_Coverage, 8012, |
| 15452 | GIR_EraseRootFromParent_Done, |
| 15453 | // Label 905: @53257 |
| 15454 | GIM_Try, /*On fail goto*//*Label 906*/ GIMT_Encode4(53320), // Rule ID 8017 // |
| 15455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 15456 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15457 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15460 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 15462 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 15464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15470 | GIR_RootConstrainSelectedInstOperands, |
| 15471 | // GIR_Coverage, 8017, |
| 15472 | GIR_EraseRootFromParent_Done, |
| 15473 | // Label 906: @53320 |
| 15474 | GIM_Try, /*On fail goto*//*Label 907*/ GIMT_Encode4(53383), // Rule ID 8023 // |
| 15475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 15476 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15480 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 15482 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 15484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15490 | GIR_RootConstrainSelectedInstOperands, |
| 15491 | // GIR_Coverage, 8023, |
| 15492 | GIR_EraseRootFromParent_Done, |
| 15493 | // Label 907: @53383 |
| 15494 | GIM_Try, /*On fail goto*//*Label 908*/ GIMT_Encode4(53445), // Rule ID 8008 // |
| 15495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15496 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15497 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15499 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15500 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15501 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 15503 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15509 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15510 | GIR_RootConstrainSelectedInstOperands, |
| 15511 | // GIR_Coverage, 8008, |
| 15512 | GIR_EraseRootFromParent_Done, |
| 15513 | // Label 908: @53445 |
| 15514 | GIM_Try, /*On fail goto*//*Label 909*/ GIMT_Encode4(53507), // Rule ID 8009 // |
| 15515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 15516 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15517 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15519 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15521 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 15523 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 15525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15530 | GIR_RootConstrainSelectedInstOperands, |
| 15531 | // GIR_Coverage, 8009, |
| 15532 | GIR_EraseRootFromParent_Done, |
| 15533 | // Label 909: @53507 |
| 15534 | GIM_Try, /*On fail goto*//*Label 910*/ GIMT_Encode4(53569), // Rule ID 8010 // |
| 15535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 15536 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15539 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15540 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15543 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 15544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 15545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15550 | GIR_RootConstrainSelectedInstOperands, |
| 15551 | // GIR_Coverage, 8010, |
| 15552 | GIR_EraseRootFromParent_Done, |
| 15553 | // Label 910: @53569 |
| 15554 | GIM_Try, /*On fail goto*//*Label 911*/ GIMT_Encode4(53634), // Rule ID 8011 // |
| 15555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 15556 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15560 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15561 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15563 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 15565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15571 | GIR_RootConstrainSelectedInstOperands, |
| 15572 | // GIR_Coverage, 8011, |
| 15573 | GIR_EraseRootFromParent_Done, |
| 15574 | // Label 911: @53634 |
| 15575 | GIM_Try, /*On fail goto*//*Label 912*/ GIMT_Encode4(53692), // Rule ID 8014 // |
| 15576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15577 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15581 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 15583 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 15585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15590 | GIR_RootConstrainSelectedInstOperands, |
| 15591 | // GIR_Coverage, 8014, |
| 15592 | GIR_EraseRootFromParent_Done, |
| 15593 | // Label 912: @53692 |
| 15594 | GIM_Try, /*On fail goto*//*Label 913*/ GIMT_Encode4(53750), // Rule ID 8015 // |
| 15595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 15596 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15600 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15601 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15602 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 15603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 15604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15609 | GIR_RootConstrainSelectedInstOperands, |
| 15610 | // GIR_Coverage, 8015, |
| 15611 | GIR_EraseRootFromParent_Done, |
| 15612 | // Label 913: @53750 |
| 15613 | GIM_Try, /*On fail goto*//*Label 914*/ GIMT_Encode4(53811), // Rule ID 8016 // |
| 15614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 15615 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15616 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15618 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15619 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15620 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15621 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 15623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15629 | GIR_RootConstrainSelectedInstOperands, |
| 15630 | // GIR_Coverage, 8016, |
| 15631 | GIR_EraseRootFromParent_Done, |
| 15632 | // Label 914: @53811 |
| 15633 | GIM_Try, /*On fail goto*//*Label 915*/ GIMT_Encode4(53879), // Rule ID 7715 // |
| 15634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 15635 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15636 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15637 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15640 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15641 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 15642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15643 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 15645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15650 | GIR_RootConstrainSelectedInstOperands, |
| 15651 | // GIR_Coverage, 7715, |
| 15652 | GIR_EraseRootFromParent_Done, |
| 15653 | // Label 915: @53879 |
| 15654 | GIM_Try, /*On fail goto*//*Label 916*/ GIMT_Encode4(53942), // Rule ID 7639 // |
| 15655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 15656 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15657 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15658 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 15659 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15661 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15662 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15663 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 15665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15670 | GIR_RootConstrainSelectedInstOperands, |
| 15671 | // GIR_Coverage, 7639, |
| 15672 | GIR_EraseRootFromParent_Done, |
| 15673 | // Label 916: @53942 |
| 15674 | GIM_Try, /*On fail goto*//*Label 917*/ GIMT_Encode4(53997), // Rule ID 8019 // |
| 15675 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15679 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15680 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 15681 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15688 | GIR_RootConstrainSelectedInstOperands, |
| 15689 | // GIR_Coverage, 8019, |
| 15690 | GIR_EraseRootFromParent_Done, |
| 15691 | // Label 917: @53997 |
| 15692 | GIM_Try, /*On fail goto*//*Label 918*/ GIMT_Encode4(54055), // Rule ID 8020 // |
| 15693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 15694 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15697 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 15700 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 15702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15707 | GIR_RootConstrainSelectedInstOperands, |
| 15708 | // GIR_Coverage, 8020, |
| 15709 | GIR_EraseRootFromParent_Done, |
| 15710 | // Label 918: @54055 |
| 15711 | GIM_Try, /*On fail goto*//*Label 919*/ GIMT_Encode4(54113), // Rule ID 8021 // |
| 15712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 15713 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15714 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15717 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15719 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 15720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 15721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15726 | GIR_RootConstrainSelectedInstOperands, |
| 15727 | // GIR_Coverage, 8021, |
| 15728 | GIR_EraseRootFromParent_Done, |
| 15729 | // Label 919: @54113 |
| 15730 | GIM_Try, /*On fail goto*//*Label 920*/ GIMT_Encode4(54174), // Rule ID 8022 // |
| 15731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 15732 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15733 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 15738 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 15740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 15742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15745 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15746 | GIR_RootConstrainSelectedInstOperands, |
| 15747 | // GIR_Coverage, 8022, |
| 15748 | GIR_EraseRootFromParent_Done, |
| 15749 | // Label 920: @54174 |
| 15750 | GIM_Try, /*On fail goto*//*Label 921*/ GIMT_Encode4(54238), // Rule ID 7716 // |
| 15751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 15752 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15753 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15754 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15756 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15757 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 15758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15759 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 15761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15765 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15766 | GIR_RootConstrainSelectedInstOperands, |
| 15767 | // GIR_Coverage, 7716, |
| 15768 | GIR_EraseRootFromParent_Done, |
| 15769 | // Label 921: @54238 |
| 15770 | GIM_Try, /*On fail goto*//*Label 922*/ GIMT_Encode4(54297), // Rule ID 7640 // |
| 15771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 15772 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15773 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 15774 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15776 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15777 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 15778 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 15779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 15780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15785 | GIR_RootConstrainSelectedInstOperands, |
| 15786 | // GIR_Coverage, 7640, |
| 15787 | GIR_EraseRootFromParent_Done, |
| 15788 | // Label 922: @54297 |
| 15789 | GIM_Try, /*On fail goto*//*Label 923*/ GIMT_Encode4(54351), // Rule ID 8013 // |
| 15790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15791 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15792 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15794 | // MIs[0] sbase |
| 15795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15797 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15798 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 15799 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15802 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15805 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15806 | GIR_RootConstrainSelectedInstOperands, |
| 15807 | // GIR_Coverage, 8013, |
| 15808 | GIR_EraseRootFromParent_Done, |
| 15809 | // Label 923: @54351 |
| 15810 | GIM_Try, /*On fail goto*//*Label 924*/ GIMT_Encode4(54401), // Rule ID 8018 // |
| 15811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 15812 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15813 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15815 | // MIs[0] sbase |
| 15816 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15817 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15818 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15819 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 15821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15822 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15825 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15826 | GIR_RootConstrainSelectedInstOperands, |
| 15827 | // GIR_Coverage, 8018, |
| 15828 | GIR_EraseRootFromParent_Done, |
| 15829 | // Label 924: @54401 |
| 15830 | GIM_Try, /*On fail goto*//*Label 925*/ GIMT_Encode4(54448), // Rule ID 8024 // |
| 15831 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15832 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15833 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 15834 | // MIs[0] sbase |
| 15835 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 15836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 15837 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 15838 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 15839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 15840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 15841 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 15842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15845 | GIR_RootConstrainSelectedInstOperands, |
| 15846 | // GIR_Coverage, 8024, |
| 15847 | GIR_EraseRootFromParent_Done, |
| 15848 | // Label 925: @54448 |
| 15849 | GIM_Try, /*On fail goto*//*Label 926*/ GIMT_Encode4(54508), // Rule ID 3978 // |
| 15850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 15851 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15852 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15853 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15854 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15855 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 15856 | // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 15857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 15858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 15861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15864 | GIR_RootConstrainSelectedInstOperands, |
| 15865 | // GIR_Coverage, 3978, |
| 15866 | GIR_EraseRootFromParent_Done, |
| 15867 | // Label 926: @54508 |
| 15868 | GIM_Try, /*On fail goto*//*Label 927*/ GIMT_Encode4(54563), // Rule ID 3977 // |
| 15869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 15870 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15871 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 15875 | // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 15876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 15877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 15879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15882 | GIR_RootConstrainSelectedInstOperands, |
| 15883 | // GIR_Coverage, 3977, |
| 15884 | GIR_EraseRootFromParent_Done, |
| 15885 | // Label 927: @54563 |
| 15886 | GIM_Try, /*On fail goto*//*Label 928*/ GIMT_Encode4(54618), // Rule ID 3976 // |
| 15887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 15888 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 15889 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15891 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 15893 | // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 15894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 15895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 15897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 15898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15899 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15900 | GIR_RootConstrainSelectedInstOperands, |
| 15901 | // GIR_Coverage, 3976, |
| 15902 | GIR_EraseRootFromParent_Done, |
| 15903 | // Label 928: @54618 |
| 15904 | GIM_Try, /*On fail goto*//*Label 929*/ GIMT_Encode4(54688), // Rule ID 4198 // |
| 15905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 15906 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15907 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15909 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15910 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 15911 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 15913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 15915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 15917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 15918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15921 | GIR_RootConstrainSelectedInstOperands, |
| 15922 | // GIR_Coverage, 4198, |
| 15923 | GIR_EraseRootFromParent_Done, |
| 15924 | // Label 929: @54688 |
| 15925 | GIM_Try, /*On fail goto*//*Label 930*/ GIMT_Encode4(54755), // Rule ID 4200 // |
| 15926 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15927 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15929 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 15931 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 15933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 15935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 15937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 15938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15940 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15941 | GIR_RootConstrainSelectedInstOperands, |
| 15942 | // GIR_Coverage, 4200, |
| 15943 | GIR_EraseRootFromParent_Done, |
| 15944 | // Label 930: @54755 |
| 15945 | GIM_Try, /*On fail goto*//*Label 931*/ GIMT_Encode4(54819), // Rule ID 7575 // |
| 15946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 15947 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 15948 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 15949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 15953 | // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 15954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 15955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 15956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 15957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 15958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 15959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15961 | GIR_RootConstrainSelectedInstOperands, |
| 15962 | // GIR_Coverage, 7575, |
| 15963 | GIR_EraseRootFromParent_Done, |
| 15964 | // Label 931: @54819 |
| 15965 | GIM_Try, /*On fail goto*//*Label 932*/ GIMT_Encode4(54884), // Rule ID 4197 // |
| 15966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 15967 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15968 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15970 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15971 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 15972 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 15974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 15981 | GIR_RootConstrainSelectedInstOperands, |
| 15982 | // GIR_Coverage, 4197, |
| 15983 | GIR_EraseRootFromParent_Done, |
| 15984 | // Label 932: @54884 |
| 15985 | GIM_Try, /*On fail goto*//*Label 933*/ GIMT_Encode4(54946), // Rule ID 4199 // |
| 15986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 15987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 15988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 15989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 15990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 15991 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 15992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 15993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 15994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 15995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 15996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 15997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 15999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16000 | GIR_RootConstrainSelectedInstOperands, |
| 16001 | // GIR_Coverage, 4199, |
| 16002 | GIR_EraseRootFromParent_Done, |
| 16003 | // Label 933: @54946 |
| 16004 | GIM_Try, /*On fail goto*//*Label 934*/ GIMT_Encode4(55006), // Rule ID 7577 // |
| 16005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 16006 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 16007 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 16009 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 16011 | // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 16012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 16013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 16015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 16016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 16017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16019 | GIR_RootConstrainSelectedInstOperands, |
| 16020 | // GIR_Coverage, 7577, |
| 16021 | GIR_EraseRootFromParent_Done, |
| 16022 | // Label 934: @55006 |
| 16023 | GIM_Try, /*On fail goto*//*Label 935*/ GIMT_Encode4(55068), // Rule ID 3517 // |
| 16024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 16025 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 16028 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16029 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 16030 | // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 16032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 16034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 16035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16037 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16038 | GIR_RootConstrainSelectedInstOperands, |
| 16039 | // GIR_Coverage, 3517, |
| 16040 | GIR_EraseRootFromParent_Done, |
| 16041 | // Label 935: @55068 |
| 16042 | GIM_Try, /*On fail goto*//*Label 936*/ GIMT_Encode4(55125), // Rule ID 3516 // |
| 16043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 16044 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16045 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 16047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 16049 | // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 16051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16055 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16056 | GIR_RootConstrainSelectedInstOperands, |
| 16057 | // GIR_Coverage, 3516, |
| 16058 | GIR_EraseRootFromParent_Done, |
| 16059 | // Label 936: @55125 |
| 16060 | GIM_Try, /*On fail goto*//*Label 937*/ GIMT_Encode4(55183), // Rule ID 3264 // |
| 16061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 16062 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16063 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 16065 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16066 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 16067 | // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 16069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16073 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16074 | GIR_RootConstrainSelectedInstOperands, |
| 16075 | // GIR_Coverage, 3264, |
| 16076 | GIR_EraseRootFromParent_Done, |
| 16077 | // Label 937: @55183 |
| 16078 | GIM_Reject, |
| 16079 | // Label 849: @55184 |
| 16080 | GIM_Try, /*On fail goto*//*Label 938*/ GIMT_Encode4(55251), // Rule ID 2564 // |
| 16081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 16082 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16083 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16085 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16086 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16087 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16088 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 16089 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16097 | GIR_RootConstrainSelectedInstOperands, |
| 16098 | // GIR_Coverage, 2564, |
| 16099 | GIR_EraseRootFromParent_Done, |
| 16100 | // Label 938: @55251 |
| 16101 | GIM_Try, /*On fail goto*//*Label 939*/ GIMT_Encode4(55314), // Rule ID 2570 // |
| 16102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 16103 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16106 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16107 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 16109 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16117 | GIR_RootConstrainSelectedInstOperands, |
| 16118 | // GIR_Coverage, 2570, |
| 16119 | GIR_EraseRootFromParent_Done, |
| 16120 | // Label 939: @55314 |
| 16121 | GIM_Try, /*On fail goto*//*Label 940*/ GIMT_Encode4(55376), // Rule ID 2560 // |
| 16122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 16123 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16127 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16128 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 16130 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16136 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16137 | GIR_RootConstrainSelectedInstOperands, |
| 16138 | // GIR_Coverage, 2560, |
| 16139 | GIR_EraseRootFromParent_Done, |
| 16140 | // Label 940: @55376 |
| 16141 | GIM_Try, /*On fail goto*//*Label 941*/ GIMT_Encode4(55438), // Rule ID 2561 // |
| 16142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 16143 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16147 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16148 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 16150 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 16152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16157 | GIR_RootConstrainSelectedInstOperands, |
| 16158 | // GIR_Coverage, 2561, |
| 16159 | GIR_EraseRootFromParent_Done, |
| 16160 | // Label 941: @55438 |
| 16161 | GIM_Try, /*On fail goto*//*Label 942*/ GIMT_Encode4(55500), // Rule ID 2562 // |
| 16162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 16163 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16167 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16169 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16170 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 16171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 16172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16177 | GIR_RootConstrainSelectedInstOperands, |
| 16178 | // GIR_Coverage, 2562, |
| 16179 | GIR_EraseRootFromParent_Done, |
| 16180 | // Label 942: @55500 |
| 16181 | GIM_Try, /*On fail goto*//*Label 943*/ GIMT_Encode4(55565), // Rule ID 2563 // |
| 16182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 16183 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16184 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16187 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16188 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16189 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16190 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16198 | GIR_RootConstrainSelectedInstOperands, |
| 16199 | // GIR_Coverage, 2563, |
| 16200 | GIR_EraseRootFromParent_Done, |
| 16201 | // Label 943: @55565 |
| 16202 | GIM_Try, /*On fail goto*//*Label 944*/ GIMT_Encode4(55620), // Rule ID 2566 // |
| 16203 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16204 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16206 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16207 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16208 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 16209 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16215 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16216 | GIR_RootConstrainSelectedInstOperands, |
| 16217 | // GIR_Coverage, 2566, |
| 16218 | GIR_EraseRootFromParent_Done, |
| 16219 | // Label 944: @55620 |
| 16220 | GIM_Try, /*On fail goto*//*Label 945*/ GIMT_Encode4(55678), // Rule ID 2567 // |
| 16221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 16222 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16225 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16226 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 16228 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 16230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16235 | GIR_RootConstrainSelectedInstOperands, |
| 16236 | // GIR_Coverage, 2567, |
| 16237 | GIR_EraseRootFromParent_Done, |
| 16238 | // Label 945: @55678 |
| 16239 | GIM_Try, /*On fail goto*//*Label 946*/ GIMT_Encode4(55736), // Rule ID 2568 // |
| 16240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 16241 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16245 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16247 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 16248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 16249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16254 | GIR_RootConstrainSelectedInstOperands, |
| 16255 | // GIR_Coverage, 2568, |
| 16256 | GIR_EraseRootFromParent_Done, |
| 16257 | // Label 946: @55736 |
| 16258 | GIM_Try, /*On fail goto*//*Label 947*/ GIMT_Encode4(55797), // Rule ID 2569 // |
| 16259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 16260 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16264 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16266 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16274 | GIR_RootConstrainSelectedInstOperands, |
| 16275 | // GIR_Coverage, 2569, |
| 16276 | GIR_EraseRootFromParent_Done, |
| 16277 | // Label 947: @55797 |
| 16278 | GIM_Try, /*On fail goto*//*Label 948*/ GIMT_Encode4(55851), // Rule ID 2565 // |
| 16279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 16280 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16283 | // MIs[0] sbase |
| 16284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 16285 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 16286 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16287 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16288 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16291 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 16292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16295 | GIR_RootConstrainSelectedInstOperands, |
| 16296 | // GIR_Coverage, 2565, |
| 16297 | GIR_EraseRootFromParent_Done, |
| 16298 | // Label 948: @55851 |
| 16299 | GIM_Try, /*On fail goto*//*Label 949*/ GIMT_Encode4(55898), // Rule ID 2571 // |
| 16300 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16301 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16303 | // MIs[0] sbase |
| 16304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 16305 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 16306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16307 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16310 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 16311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16313 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16314 | GIR_RootConstrainSelectedInstOperands, |
| 16315 | // GIR_Coverage, 2571, |
| 16316 | GIR_EraseRootFromParent_Done, |
| 16317 | // Label 949: @55898 |
| 16318 | GIM_Try, /*On fail goto*//*Label 950*/ GIMT_Encode4(55961), // Rule ID 6190 // |
| 16319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 16320 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 16325 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 16327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16334 | GIR_RootConstrainSelectedInstOperands, |
| 16335 | // GIR_Coverage, 6190, |
| 16336 | GIR_EraseRootFromParent_Done, |
| 16337 | // Label 950: @55961 |
| 16338 | GIM_Try, /*On fail goto*//*Label 951*/ GIMT_Encode4(56024), // Rule ID 6192 // |
| 16339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 16340 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16341 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 16345 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 16347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16354 | GIR_RootConstrainSelectedInstOperands, |
| 16355 | // GIR_Coverage, 6192, |
| 16356 | GIR_EraseRootFromParent_Done, |
| 16357 | // Label 951: @56024 |
| 16358 | GIM_Try, /*On fail goto*//*Label 952*/ GIMT_Encode4(56084), // Rule ID 3906 // |
| 16359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 16360 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16361 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 16365 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 16367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 16370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16373 | GIR_RootConstrainSelectedInstOperands, |
| 16374 | // GIR_Coverage, 3906, |
| 16375 | GIR_EraseRootFromParent_Done, |
| 16376 | // Label 952: @56084 |
| 16377 | GIM_Try, /*On fail goto*//*Label 953*/ GIMT_Encode4(56139), // Rule ID 3905 // |
| 16378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 16379 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16380 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16382 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 16384 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 16385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 16386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 16388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16390 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16391 | GIR_RootConstrainSelectedInstOperands, |
| 16392 | // GIR_Coverage, 3905, |
| 16393 | GIR_EraseRootFromParent_Done, |
| 16394 | // Label 953: @56139 |
| 16395 | GIM_Try, /*On fail goto*//*Label 954*/ GIMT_Encode4(56194), // Rule ID 3904 // |
| 16396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 16397 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 16402 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 16404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16409 | GIR_RootConstrainSelectedInstOperands, |
| 16410 | // GIR_Coverage, 3904, |
| 16411 | GIR_EraseRootFromParent_Done, |
| 16412 | // Label 954: @56194 |
| 16413 | GIM_Try, /*On fail goto*//*Label 955*/ GIMT_Encode4(56264), // Rule ID 4150 // |
| 16414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 16415 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16416 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16418 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16419 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 16420 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 16422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16429 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16430 | GIR_RootConstrainSelectedInstOperands, |
| 16431 | // GIR_Coverage, 4150, |
| 16432 | GIR_EraseRootFromParent_Done, |
| 16433 | // Label 955: @56264 |
| 16434 | GIM_Try, /*On fail goto*//*Label 956*/ GIMT_Encode4(56331), // Rule ID 4152 // |
| 16435 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16436 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 16440 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 16442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16449 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16450 | GIR_RootConstrainSelectedInstOperands, |
| 16451 | // GIR_Coverage, 4152, |
| 16452 | GIR_EraseRootFromParent_Done, |
| 16453 | // Label 956: @56331 |
| 16454 | GIM_Try, /*On fail goto*//*Label 957*/ GIMT_Encode4(56399), // Rule ID 6189 // |
| 16455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 16456 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16457 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16460 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 16461 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 16463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16471 | GIR_RootConstrainSelectedInstOperands, |
| 16472 | // GIR_Coverage, 6189, |
| 16473 | GIR_EraseRootFromParent_Done, |
| 16474 | // Label 957: @56399 |
| 16475 | GIM_Try, /*On fail goto*//*Label 958*/ GIMT_Encode4(56467), // Rule ID 6191 // |
| 16476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 16477 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16480 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 16482 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 16484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16491 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16492 | GIR_RootConstrainSelectedInstOperands, |
| 16493 | // GIR_Coverage, 6191, |
| 16494 | GIR_EraseRootFromParent_Done, |
| 16495 | // Label 958: @56467 |
| 16496 | GIM_Try, /*On fail goto*//*Label 959*/ GIMT_Encode4(56532), // Rule ID 4149 // |
| 16497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 16498 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16499 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 16503 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 16505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16511 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16512 | GIR_RootConstrainSelectedInstOperands, |
| 16513 | // GIR_Coverage, 4149, |
| 16514 | GIR_EraseRootFromParent_Done, |
| 16515 | // Label 959: @56532 |
| 16516 | GIM_Try, /*On fail goto*//*Label 960*/ GIMT_Encode4(56594), // Rule ID 4151 // |
| 16517 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16518 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 16522 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 16524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16531 | GIR_RootConstrainSelectedInstOperands, |
| 16532 | // GIR_Coverage, 4151, |
| 16533 | GIR_EraseRootFromParent_Done, |
| 16534 | // Label 960: @56594 |
| 16535 | GIM_Try, /*On fail goto*//*Label 961*/ GIMT_Encode4(56653), // Rule ID 7467 // |
| 16536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 16537 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16538 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 16539 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16541 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 16543 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 16544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 16545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 16547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16550 | GIR_RootConstrainSelectedInstOperands, |
| 16551 | // GIR_Coverage, 7467, |
| 16552 | GIR_EraseRootFromParent_Done, |
| 16553 | // Label 961: @56653 |
| 16554 | GIM_Try, /*On fail goto*//*Label 962*/ GIMT_Encode4(56708), // Rule ID 7468 // |
| 16555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 16556 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 16557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 16561 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 16562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 16563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 16565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16567 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16568 | GIR_RootConstrainSelectedInstOperands, |
| 16569 | // GIR_Coverage, 7468, |
| 16570 | GIR_EraseRootFromParent_Done, |
| 16571 | // Label 962: @56708 |
| 16572 | GIM_Try, /*On fail goto*//*Label 963*/ GIMT_Encode4(56770), // Rule ID 3469 // |
| 16573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 16574 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16575 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16577 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16578 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 16579 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 16581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 16583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 16584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16587 | GIR_RootConstrainSelectedInstOperands, |
| 16588 | // GIR_Coverage, 3469, |
| 16589 | GIR_EraseRootFromParent_Done, |
| 16590 | // Label 963: @56770 |
| 16591 | GIM_Try, /*On fail goto*//*Label 964*/ GIMT_Encode4(56827), // Rule ID 3468 // |
| 16592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 16593 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16594 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 16598 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 16600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16605 | GIR_RootConstrainSelectedInstOperands, |
| 16606 | // GIR_Coverage, 3468, |
| 16607 | GIR_EraseRootFromParent_Done, |
| 16608 | // Label 964: @56827 |
| 16609 | GIM_Try, /*On fail goto*//*Label 965*/ GIMT_Encode4(56885), // Rule ID 3239 // |
| 16610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 16611 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 16616 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 16618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16623 | GIR_RootConstrainSelectedInstOperands, |
| 16624 | // GIR_Coverage, 3239, |
| 16625 | GIR_EraseRootFromParent_Done, |
| 16626 | // Label 965: @56885 |
| 16627 | GIM_Reject, |
| 16628 | // Label 850: @56886 |
| 16629 | GIM_Try, /*On fail goto*//*Label 966*/ GIMT_Encode4(56953), // Rule ID 2576 // |
| 16630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 16631 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16635 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 16638 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16646 | GIR_RootConstrainSelectedInstOperands, |
| 16647 | // GIR_Coverage, 2576, |
| 16648 | GIR_EraseRootFromParent_Done, |
| 16649 | // Label 966: @56953 |
| 16650 | GIM_Try, /*On fail goto*//*Label 967*/ GIMT_Encode4(57016), // Rule ID 2582 // |
| 16651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 16652 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16653 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16655 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16656 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16657 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 16658 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16666 | GIR_RootConstrainSelectedInstOperands, |
| 16667 | // GIR_Coverage, 2582, |
| 16668 | GIR_EraseRootFromParent_Done, |
| 16669 | // Label 967: @57016 |
| 16670 | GIM_Try, /*On fail goto*//*Label 968*/ GIMT_Encode4(57078), // Rule ID 2572 // |
| 16671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 16672 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16673 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16675 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16676 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16677 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 16679 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16685 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16686 | GIR_RootConstrainSelectedInstOperands, |
| 16687 | // GIR_Coverage, 2572, |
| 16688 | GIR_EraseRootFromParent_Done, |
| 16689 | // Label 968: @57078 |
| 16690 | GIM_Try, /*On fail goto*//*Label 969*/ GIMT_Encode4(57140), // Rule ID 2573 // |
| 16691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 16692 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16696 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16697 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16698 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 16699 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 16701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16706 | GIR_RootConstrainSelectedInstOperands, |
| 16707 | // GIR_Coverage, 2573, |
| 16708 | GIR_EraseRootFromParent_Done, |
| 16709 | // Label 969: @57140 |
| 16710 | GIM_Try, /*On fail goto*//*Label 970*/ GIMT_Encode4(57202), // Rule ID 2574 // |
| 16711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 16712 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16713 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16716 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16717 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16719 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 16720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 16721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16726 | GIR_RootConstrainSelectedInstOperands, |
| 16727 | // GIR_Coverage, 2574, |
| 16728 | GIR_EraseRootFromParent_Done, |
| 16729 | // Label 970: @57202 |
| 16730 | GIM_Try, /*On fail goto*//*Label 971*/ GIMT_Encode4(57267), // Rule ID 2575 // |
| 16731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 16732 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16733 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16737 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16739 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16746 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16747 | GIR_RootConstrainSelectedInstOperands, |
| 16748 | // GIR_Coverage, 2575, |
| 16749 | GIR_EraseRootFromParent_Done, |
| 16750 | // Label 971: @57267 |
| 16751 | GIM_Try, /*On fail goto*//*Label 972*/ GIMT_Encode4(57322), // Rule ID 2578 // |
| 16752 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16753 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16755 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16756 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16757 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 16758 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16765 | GIR_RootConstrainSelectedInstOperands, |
| 16766 | // GIR_Coverage, 2578, |
| 16767 | GIR_EraseRootFromParent_Done, |
| 16768 | // Label 972: @57322 |
| 16769 | GIM_Try, /*On fail goto*//*Label 973*/ GIMT_Encode4(57380), // Rule ID 2579 // |
| 16770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 16771 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16772 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16775 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 16777 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 16779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16783 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16784 | GIR_RootConstrainSelectedInstOperands, |
| 16785 | // GIR_Coverage, 2579, |
| 16786 | GIR_EraseRootFromParent_Done, |
| 16787 | // Label 973: @57380 |
| 16788 | GIM_Try, /*On fail goto*//*Label 974*/ GIMT_Encode4(57438), // Rule ID 2580 // |
| 16789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 16790 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16791 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16794 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16795 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16796 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 16797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 16798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16803 | GIR_RootConstrainSelectedInstOperands, |
| 16804 | // GIR_Coverage, 2580, |
| 16805 | GIR_EraseRootFromParent_Done, |
| 16806 | // Label 974: @57438 |
| 16807 | GIM_Try, /*On fail goto*//*Label 975*/ GIMT_Encode4(57499), // Rule ID 2581 // |
| 16808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 16809 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16812 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16813 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 16815 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 16817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 16819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16823 | GIR_RootConstrainSelectedInstOperands, |
| 16824 | // GIR_Coverage, 2581, |
| 16825 | GIR_EraseRootFromParent_Done, |
| 16826 | // Label 975: @57499 |
| 16827 | GIM_Try, /*On fail goto*//*Label 976*/ GIMT_Encode4(57553), // Rule ID 2577 // |
| 16828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 16829 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16830 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16832 | // MIs[0] sbase |
| 16833 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 16834 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 16835 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16836 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 16837 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16840 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 16841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16843 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16844 | GIR_RootConstrainSelectedInstOperands, |
| 16845 | // GIR_Coverage, 2577, |
| 16846 | GIR_EraseRootFromParent_Done, |
| 16847 | // Label 976: @57553 |
| 16848 | GIM_Try, /*On fail goto*//*Label 977*/ GIMT_Encode4(57600), // Rule ID 2583 // |
| 16849 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 16850 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 16852 | // MIs[0] sbase |
| 16853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 16854 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 16855 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 16856 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 16857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 16858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 16859 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 16860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16862 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16863 | GIR_RootConstrainSelectedInstOperands, |
| 16864 | // GIR_Coverage, 2583, |
| 16865 | GIR_EraseRootFromParent_Done, |
| 16866 | // Label 977: @57600 |
| 16867 | GIM_Try, /*On fail goto*//*Label 978*/ GIMT_Encode4(57663), // Rule ID 6194 // |
| 16868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 16869 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16872 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16873 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 16874 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 16876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16883 | GIR_RootConstrainSelectedInstOperands, |
| 16884 | // GIR_Coverage, 6194, |
| 16885 | GIR_EraseRootFromParent_Done, |
| 16886 | // Label 978: @57663 |
| 16887 | GIM_Try, /*On fail goto*//*Label 979*/ GIMT_Encode4(57726), // Rule ID 6196 // |
| 16888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 16889 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16892 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 16894 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 16895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 16896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 16899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16903 | GIR_RootConstrainSelectedInstOperands, |
| 16904 | // GIR_Coverage, 6196, |
| 16905 | GIR_EraseRootFromParent_Done, |
| 16906 | // Label 979: @57726 |
| 16907 | GIM_Try, /*On fail goto*//*Label 980*/ GIMT_Encode4(57786), // Rule ID 3912 // |
| 16908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 16909 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16910 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 16914 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 16915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 16916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 16919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 16920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16922 | GIR_RootConstrainSelectedInstOperands, |
| 16923 | // GIR_Coverage, 3912, |
| 16924 | GIR_EraseRootFromParent_Done, |
| 16925 | // Label 980: @57786 |
| 16926 | GIM_Try, /*On fail goto*//*Label 981*/ GIMT_Encode4(57841), // Rule ID 3911 // |
| 16927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 16928 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 16933 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 16934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 16935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 16937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16939 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16940 | GIR_RootConstrainSelectedInstOperands, |
| 16941 | // GIR_Coverage, 3911, |
| 16942 | GIR_EraseRootFromParent_Done, |
| 16943 | // Label 981: @57841 |
| 16944 | GIM_Try, /*On fail goto*//*Label 982*/ GIMT_Encode4(57896), // Rule ID 3910 // |
| 16945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 16946 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 16947 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 16951 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 16952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 16953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 16954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 16955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 16956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16957 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16958 | GIR_RootConstrainSelectedInstOperands, |
| 16959 | // GIR_Coverage, 3910, |
| 16960 | GIR_EraseRootFromParent_Done, |
| 16961 | // Label 982: @57896 |
| 16962 | GIM_Try, /*On fail goto*//*Label 983*/ GIMT_Encode4(57966), // Rule ID 4154 // |
| 16963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 16964 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16965 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16968 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 16969 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 16971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16978 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16979 | GIR_RootConstrainSelectedInstOperands, |
| 16980 | // GIR_Coverage, 4154, |
| 16981 | GIR_EraseRootFromParent_Done, |
| 16982 | // Label 983: @57966 |
| 16983 | GIM_Try, /*On fail goto*//*Label 984*/ GIMT_Encode4(58033), // Rule ID 4156 // |
| 16984 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 16985 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 16986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 16987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 16988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 16989 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 16990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 16991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 16992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 16993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 16994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 16995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 16996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 16998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 16999 | GIR_RootConstrainSelectedInstOperands, |
| 17000 | // GIR_Coverage, 4156, |
| 17001 | GIR_EraseRootFromParent_Done, |
| 17002 | // Label 984: @58033 |
| 17003 | GIM_Try, /*On fail goto*//*Label 985*/ GIMT_Encode4(58101), // Rule ID 6193 // |
| 17004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 17005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 17006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 17010 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 17011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 17012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 17014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 17016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 17017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17020 | GIR_RootConstrainSelectedInstOperands, |
| 17021 | // GIR_Coverage, 6193, |
| 17022 | GIR_EraseRootFromParent_Done, |
| 17023 | // Label 985: @58101 |
| 17024 | GIM_Try, /*On fail goto*//*Label 986*/ GIMT_Encode4(58169), // Rule ID 6195 // |
| 17025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 17026 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 17027 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 17031 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 17032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 17033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 17035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 17037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 17038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17041 | GIR_RootConstrainSelectedInstOperands, |
| 17042 | // GIR_Coverage, 6195, |
| 17043 | GIR_EraseRootFromParent_Done, |
| 17044 | // Label 986: @58169 |
| 17045 | GIM_Try, /*On fail goto*//*Label 987*/ GIMT_Encode4(58234), // Rule ID 4153 // |
| 17046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 17047 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17048 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 17052 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 17054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17060 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17061 | GIR_RootConstrainSelectedInstOperands, |
| 17062 | // GIR_Coverage, 4153, |
| 17063 | GIR_EraseRootFromParent_Done, |
| 17064 | // Label 987: @58234 |
| 17065 | GIM_Try, /*On fail goto*//*Label 988*/ GIMT_Encode4(58296), // Rule ID 4155 // |
| 17066 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17067 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17069 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17070 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 17071 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 17073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17080 | GIR_RootConstrainSelectedInstOperands, |
| 17081 | // GIR_Coverage, 4155, |
| 17082 | GIR_EraseRootFromParent_Done, |
| 17083 | // Label 988: @58296 |
| 17084 | GIM_Try, /*On fail goto*//*Label 989*/ GIMT_Encode4(58355), // Rule ID 7469 // |
| 17085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 17086 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17087 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17088 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17092 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 17094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17099 | GIR_RootConstrainSelectedInstOperands, |
| 17100 | // GIR_Coverage, 7469, |
| 17101 | GIR_EraseRootFromParent_Done, |
| 17102 | // Label 989: @58355 |
| 17103 | GIM_Try, /*On fail goto*//*Label 990*/ GIMT_Encode4(58410), // Rule ID 7470 // |
| 17104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 17105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17110 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 17112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17117 | GIR_RootConstrainSelectedInstOperands, |
| 17118 | // GIR_Coverage, 7470, |
| 17119 | GIR_EraseRootFromParent_Done, |
| 17120 | // Label 990: @58410 |
| 17121 | GIM_Try, /*On fail goto*//*Label 991*/ GIMT_Encode4(58472), // Rule ID 3473 // |
| 17122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 17123 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 17128 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 17130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 17132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 17133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17136 | GIR_RootConstrainSelectedInstOperands, |
| 17137 | // GIR_Coverage, 3473, |
| 17138 | GIR_EraseRootFromParent_Done, |
| 17139 | // Label 991: @58472 |
| 17140 | GIM_Try, /*On fail goto*//*Label 992*/ GIMT_Encode4(58529), // Rule ID 3472 // |
| 17141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 17142 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17143 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17145 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17146 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 17147 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 17148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 17149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17153 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17154 | GIR_RootConstrainSelectedInstOperands, |
| 17155 | // GIR_Coverage, 3472, |
| 17156 | GIR_EraseRootFromParent_Done, |
| 17157 | // Label 992: @58529 |
| 17158 | GIM_Try, /*On fail goto*//*Label 993*/ GIMT_Encode4(58587), // Rule ID 3241 // |
| 17159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 17160 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17161 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 17163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 17165 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 17166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 17167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17172 | GIR_RootConstrainSelectedInstOperands, |
| 17173 | // GIR_Coverage, 3241, |
| 17174 | GIR_EraseRootFromParent_Done, |
| 17175 | // Label 993: @58587 |
| 17176 | GIM_Reject, |
| 17177 | // Label 851: @58588 |
| 17178 | GIM_Try, /*On fail goto*//*Label 994*/ GIMT_Encode4(58655), // Rule ID 8029 // |
| 17179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17180 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17181 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17183 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17184 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17185 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 17187 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 17189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17195 | GIR_RootConstrainSelectedInstOperands, |
| 17196 | // GIR_Coverage, 8029, |
| 17197 | GIR_EraseRootFromParent_Done, |
| 17198 | // Label 994: @58655 |
| 17199 | GIM_Try, /*On fail goto*//*Label 995*/ GIMT_Encode4(58718), // Rule ID 8034 // |
| 17200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17201 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17202 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17205 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 17207 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 17209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17215 | GIR_RootConstrainSelectedInstOperands, |
| 17216 | // GIR_Coverage, 8034, |
| 17217 | GIR_EraseRootFromParent_Done, |
| 17218 | // Label 995: @58718 |
| 17219 | GIM_Try, /*On fail goto*//*Label 996*/ GIMT_Encode4(58781), // Rule ID 8040 // |
| 17220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 17221 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17222 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 17227 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 17229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17235 | GIR_RootConstrainSelectedInstOperands, |
| 17236 | // GIR_Coverage, 8040, |
| 17237 | GIR_EraseRootFromParent_Done, |
| 17238 | // Label 996: @58781 |
| 17239 | GIM_Try, /*On fail goto*//*Label 997*/ GIMT_Encode4(58843), // Rule ID 8025 // |
| 17240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 17241 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17245 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17246 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 17248 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 17250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17255 | GIR_RootConstrainSelectedInstOperands, |
| 17256 | // GIR_Coverage, 8025, |
| 17257 | GIR_EraseRootFromParent_Done, |
| 17258 | // Label 997: @58843 |
| 17259 | GIM_Try, /*On fail goto*//*Label 998*/ GIMT_Encode4(58905), // Rule ID 8026 // |
| 17260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 17261 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17262 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17265 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17266 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 17268 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 17270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17275 | GIR_RootConstrainSelectedInstOperands, |
| 17276 | // GIR_Coverage, 8026, |
| 17277 | GIR_EraseRootFromParent_Done, |
| 17278 | // Label 998: @58905 |
| 17279 | GIM_Try, /*On fail goto*//*Label 999*/ GIMT_Encode4(58967), // Rule ID 8027 // |
| 17280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 17281 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17282 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17285 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17286 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17288 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 17289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 17290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17295 | GIR_RootConstrainSelectedInstOperands, |
| 17296 | // GIR_Coverage, 8027, |
| 17297 | GIR_EraseRootFromParent_Done, |
| 17298 | // Label 999: @58967 |
| 17299 | GIM_Try, /*On fail goto*//*Label 1000*/ GIMT_Encode4(59032), // Rule ID 8028 // |
| 17300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17301 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17305 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17308 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 17310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17316 | GIR_RootConstrainSelectedInstOperands, |
| 17317 | // GIR_Coverage, 8028, |
| 17318 | GIR_EraseRootFromParent_Done, |
| 17319 | // Label 1000: @59032 |
| 17320 | GIM_Try, /*On fail goto*//*Label 1001*/ GIMT_Encode4(59090), // Rule ID 8031 // |
| 17321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 17322 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17323 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17325 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 17328 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 17330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17335 | GIR_RootConstrainSelectedInstOperands, |
| 17336 | // GIR_Coverage, 8031, |
| 17337 | GIR_EraseRootFromParent_Done, |
| 17338 | // Label 1001: @59090 |
| 17339 | GIM_Try, /*On fail goto*//*Label 1002*/ GIMT_Encode4(59148), // Rule ID 8032 // |
| 17340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 17341 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17345 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17346 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17347 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 17348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 17349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17354 | GIR_RootConstrainSelectedInstOperands, |
| 17355 | // GIR_Coverage, 8032, |
| 17356 | GIR_EraseRootFromParent_Done, |
| 17357 | // Label 1002: @59148 |
| 17358 | GIM_Try, /*On fail goto*//*Label 1003*/ GIMT_Encode4(59209), // Rule ID 8033 // |
| 17359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17360 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17361 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17364 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17366 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 17368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17374 | GIR_RootConstrainSelectedInstOperands, |
| 17375 | // GIR_Coverage, 8033, |
| 17376 | GIR_EraseRootFromParent_Done, |
| 17377 | // Label 1003: @59209 |
| 17378 | GIM_Try, /*On fail goto*//*Label 1004*/ GIMT_Encode4(59277), // Rule ID 7719 // |
| 17379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 17380 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17381 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17382 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17386 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 17387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17388 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 17390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17395 | GIR_RootConstrainSelectedInstOperands, |
| 17396 | // GIR_Coverage, 7719, |
| 17397 | GIR_EraseRootFromParent_Done, |
| 17398 | // Label 1004: @59277 |
| 17399 | GIM_Try, /*On fail goto*//*Label 1005*/ GIMT_Encode4(59340), // Rule ID 7643 // |
| 17400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 17401 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17402 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17403 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 17404 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17406 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17408 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 17410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17415 | GIR_RootConstrainSelectedInstOperands, |
| 17416 | // GIR_Coverage, 7643, |
| 17417 | GIR_EraseRootFromParent_Done, |
| 17418 | // Label 1005: @59340 |
| 17419 | GIM_Try, /*On fail goto*//*Label 1006*/ GIMT_Encode4(59395), // Rule ID 8036 // |
| 17420 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17421 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17423 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17424 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 17426 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 17428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17433 | GIR_RootConstrainSelectedInstOperands, |
| 17434 | // GIR_Coverage, 8036, |
| 17435 | GIR_EraseRootFromParent_Done, |
| 17436 | // Label 1006: @59395 |
| 17437 | GIM_Try, /*On fail goto*//*Label 1007*/ GIMT_Encode4(59453), // Rule ID 8037 // |
| 17438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 17439 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17440 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17443 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 17445 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 17447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17452 | GIR_RootConstrainSelectedInstOperands, |
| 17453 | // GIR_Coverage, 8037, |
| 17454 | GIR_EraseRootFromParent_Done, |
| 17455 | // Label 1007: @59453 |
| 17456 | GIM_Try, /*On fail goto*//*Label 1008*/ GIMT_Encode4(59511), // Rule ID 8038 // |
| 17457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 17458 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17462 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17464 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 17465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 17466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17471 | GIR_RootConstrainSelectedInstOperands, |
| 17472 | // GIR_Coverage, 8038, |
| 17473 | GIR_EraseRootFromParent_Done, |
| 17474 | // Label 1008: @59511 |
| 17475 | GIM_Try, /*On fail goto*//*Label 1009*/ GIMT_Encode4(59572), // Rule ID 8039 // |
| 17476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 17477 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17480 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17481 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17483 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 17485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17490 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17491 | GIR_RootConstrainSelectedInstOperands, |
| 17492 | // GIR_Coverage, 8039, |
| 17493 | GIR_EraseRootFromParent_Done, |
| 17494 | // Label 1009: @59572 |
| 17495 | GIM_Try, /*On fail goto*//*Label 1010*/ GIMT_Encode4(59636), // Rule ID 7720 // |
| 17496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 17497 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17498 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17499 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17502 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 17503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17504 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 17506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17510 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17511 | GIR_RootConstrainSelectedInstOperands, |
| 17512 | // GIR_Coverage, 7720, |
| 17513 | GIR_EraseRootFromParent_Done, |
| 17514 | // Label 1010: @59636 |
| 17515 | GIM_Try, /*On fail goto*//*Label 1011*/ GIMT_Encode4(59695), // Rule ID 7644 // |
| 17516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 17517 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17518 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 17519 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 17523 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 17524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 17525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17530 | GIR_RootConstrainSelectedInstOperands, |
| 17531 | // GIR_Coverage, 7644, |
| 17532 | GIR_EraseRootFromParent_Done, |
| 17533 | // Label 1011: @59695 |
| 17534 | GIM_Try, /*On fail goto*//*Label 1012*/ GIMT_Encode4(59749), // Rule ID 8030 // |
| 17535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 17536 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17539 | // MIs[0] sbase |
| 17540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 17541 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 17542 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17543 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17544 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 17546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17547 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 17548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17550 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17551 | GIR_RootConstrainSelectedInstOperands, |
| 17552 | // GIR_Coverage, 8030, |
| 17553 | GIR_EraseRootFromParent_Done, |
| 17554 | // Label 1012: @59749 |
| 17555 | GIM_Try, /*On fail goto*//*Label 1013*/ GIMT_Encode4(59799), // Rule ID 8035 // |
| 17556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 17557 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17558 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17560 | // MIs[0] sbase |
| 17561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 17562 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 17563 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17564 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 17566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17567 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 17568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17571 | GIR_RootConstrainSelectedInstOperands, |
| 17572 | // GIR_Coverage, 8035, |
| 17573 | GIR_EraseRootFromParent_Done, |
| 17574 | // Label 1013: @59799 |
| 17575 | GIM_Try, /*On fail goto*//*Label 1014*/ GIMT_Encode4(59846), // Rule ID 8041 // |
| 17576 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17577 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 17579 | // MIs[0] sbase |
| 17580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 17581 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 17582 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17583 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 17585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17586 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 17587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17590 | GIR_RootConstrainSelectedInstOperands, |
| 17591 | // GIR_Coverage, 8041, |
| 17592 | GIR_EraseRootFromParent_Done, |
| 17593 | // Label 1014: @59846 |
| 17594 | GIM_Try, /*On fail goto*//*Label 1015*/ GIMT_Encode4(59906), // Rule ID 3984 // |
| 17595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 17596 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 17597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 17601 | // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 17603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 17606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17609 | GIR_RootConstrainSelectedInstOperands, |
| 17610 | // GIR_Coverage, 3984, |
| 17611 | GIR_EraseRootFromParent_Done, |
| 17612 | // Label 1015: @59906 |
| 17613 | GIM_Try, /*On fail goto*//*Label 1016*/ GIMT_Encode4(59961), // Rule ID 3983 // |
| 17614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 17615 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 17616 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17617 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17618 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17619 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 17620 | // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 17621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 17622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 17624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17627 | GIR_RootConstrainSelectedInstOperands, |
| 17628 | // GIR_Coverage, 3983, |
| 17629 | GIR_EraseRootFromParent_Done, |
| 17630 | // Label 1016: @59961 |
| 17631 | GIM_Try, /*On fail goto*//*Label 1017*/ GIMT_Encode4(60016), // Rule ID 3982 // |
| 17632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 17633 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 17634 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 17638 | // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 17639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 17640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17645 | GIR_RootConstrainSelectedInstOperands, |
| 17646 | // GIR_Coverage, 3982, |
| 17647 | GIR_EraseRootFromParent_Done, |
| 17648 | // Label 1017: @60016 |
| 17649 | GIM_Try, /*On fail goto*//*Label 1018*/ GIMT_Encode4(60086), // Rule ID 4202 // |
| 17650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 17651 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17652 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 17656 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 17658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 17660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 17662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 17663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17666 | GIR_RootConstrainSelectedInstOperands, |
| 17667 | // GIR_Coverage, 4202, |
| 17668 | GIR_EraseRootFromParent_Done, |
| 17669 | // Label 1018: @60086 |
| 17670 | GIM_Try, /*On fail goto*//*Label 1019*/ GIMT_Encode4(60153), // Rule ID 4204 // |
| 17671 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17672 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17674 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 17676 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 17678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 17680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 17682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 17683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17685 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17686 | GIR_RootConstrainSelectedInstOperands, |
| 17687 | // GIR_Coverage, 4204, |
| 17688 | GIR_EraseRootFromParent_Done, |
| 17689 | // Label 1019: @60153 |
| 17690 | GIM_Try, /*On fail goto*//*Label 1020*/ GIMT_Encode4(60217), // Rule ID 7579 // |
| 17691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 17692 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17693 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17694 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 17698 | // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 17699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 17700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 17703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 17704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17706 | GIR_RootConstrainSelectedInstOperands, |
| 17707 | // GIR_Coverage, 7579, |
| 17708 | GIR_EraseRootFromParent_Done, |
| 17709 | // Label 1020: @60217 |
| 17710 | GIM_Try, /*On fail goto*//*Label 1021*/ GIMT_Encode4(60282), // Rule ID 4201 // |
| 17711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 17712 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17713 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17716 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 17717 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 17719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17726 | GIR_RootConstrainSelectedInstOperands, |
| 17727 | // GIR_Coverage, 4201, |
| 17728 | GIR_EraseRootFromParent_Done, |
| 17729 | // Label 1021: @60282 |
| 17730 | GIM_Try, /*On fail goto*//*Label 1022*/ GIMT_Encode4(60344), // Rule ID 4203 // |
| 17731 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17734 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 17736 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 17737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 17738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 17739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 17740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17745 | GIR_RootConstrainSelectedInstOperands, |
| 17746 | // GIR_Coverage, 4203, |
| 17747 | GIR_EraseRootFromParent_Done, |
| 17748 | // Label 1022: @60344 |
| 17749 | GIM_Try, /*On fail goto*//*Label 1023*/ GIMT_Encode4(60404), // Rule ID 7581 // |
| 17750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 17751 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 17752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17755 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 17756 | // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 17757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 17758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 17760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 17761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 17762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17764 | GIR_RootConstrainSelectedInstOperands, |
| 17765 | // GIR_Coverage, 7581, |
| 17766 | GIR_EraseRootFromParent_Done, |
| 17767 | // Label 1023: @60404 |
| 17768 | GIM_Try, /*On fail goto*//*Label 1024*/ GIMT_Encode4(60466), // Rule ID 3521 // |
| 17769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 17770 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 17775 | // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 17777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 17779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 17780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17783 | GIR_RootConstrainSelectedInstOperands, |
| 17784 | // GIR_Coverage, 3521, |
| 17785 | GIR_EraseRootFromParent_Done, |
| 17786 | // Label 1024: @60466 |
| 17787 | GIM_Try, /*On fail goto*//*Label 1025*/ GIMT_Encode4(60523), // Rule ID 3520 // |
| 17788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 17789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 17794 | // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 17795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 17796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17801 | GIR_RootConstrainSelectedInstOperands, |
| 17802 | // GIR_Coverage, 3520, |
| 17803 | GIR_EraseRootFromParent_Done, |
| 17804 | // Label 1025: @60523 |
| 17805 | GIM_Try, /*On fail goto*//*Label 1026*/ GIMT_Encode4(60581), // Rule ID 3266 // |
| 17806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 17807 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 17808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 17810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 17812 | // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 17813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 17814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 17815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 17816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17819 | GIR_RootConstrainSelectedInstOperands, |
| 17820 | // GIR_Coverage, 3266, |
| 17821 | GIR_EraseRootFromParent_Done, |
| 17822 | // Label 1026: @60581 |
| 17823 | GIM_Reject, |
| 17824 | // Label 852: @60582 |
| 17825 | GIM_Try, /*On fail goto*//*Label 1027*/ GIMT_Encode4(60649), // Rule ID 2588 // |
| 17826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17827 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17832 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17833 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 17834 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 17836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17842 | GIR_RootConstrainSelectedInstOperands, |
| 17843 | // GIR_Coverage, 2588, |
| 17844 | GIR_EraseRootFromParent_Done, |
| 17845 | // Label 1027: @60649 |
| 17846 | GIM_Try, /*On fail goto*//*Label 1028*/ GIMT_Encode4(60712), // Rule ID 2594 // |
| 17847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 17848 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17849 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17851 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 17854 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 17856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 17860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17861 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17862 | GIR_RootConstrainSelectedInstOperands, |
| 17863 | // GIR_Coverage, 2594, |
| 17864 | GIR_EraseRootFromParent_Done, |
| 17865 | // Label 1028: @60712 |
| 17866 | GIM_Try, /*On fail goto*//*Label 1029*/ GIMT_Encode4(60774), // Rule ID 2584 // |
| 17867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 17868 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17869 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17872 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17873 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 17875 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 17877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17882 | GIR_RootConstrainSelectedInstOperands, |
| 17883 | // GIR_Coverage, 2584, |
| 17884 | GIR_EraseRootFromParent_Done, |
| 17885 | // Label 1029: @60774 |
| 17886 | GIM_Try, /*On fail goto*//*Label 1030*/ GIMT_Encode4(60836), // Rule ID 2585 // |
| 17887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 17888 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17889 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17891 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17892 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17893 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17894 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 17895 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 17897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17902 | GIR_RootConstrainSelectedInstOperands, |
| 17903 | // GIR_Coverage, 2585, |
| 17904 | GIR_EraseRootFromParent_Done, |
| 17905 | // Label 1030: @60836 |
| 17906 | GIM_Try, /*On fail goto*//*Label 1031*/ GIMT_Encode4(60898), // Rule ID 2586 // |
| 17907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 17908 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17909 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17912 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17913 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17915 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 17916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 17917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17922 | GIR_RootConstrainSelectedInstOperands, |
| 17923 | // GIR_Coverage, 2586, |
| 17924 | GIR_EraseRootFromParent_Done, |
| 17925 | // Label 1031: @60898 |
| 17926 | GIM_Try, /*On fail goto*//*Label 1032*/ GIMT_Encode4(60963), // Rule ID 2587 // |
| 17927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 17928 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17932 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 17934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17935 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 17936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 17937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17943 | GIR_RootConstrainSelectedInstOperands, |
| 17944 | // GIR_Coverage, 2587, |
| 17945 | GIR_EraseRootFromParent_Done, |
| 17946 | // Label 1032: @60963 |
| 17947 | GIM_Try, /*On fail goto*//*Label 1033*/ GIMT_Encode4(61018), // Rule ID 2590 // |
| 17948 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 17954 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 17956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17961 | GIR_RootConstrainSelectedInstOperands, |
| 17962 | // GIR_Coverage, 2590, |
| 17963 | GIR_EraseRootFromParent_Done, |
| 17964 | // Label 1033: @61018 |
| 17965 | GIM_Try, /*On fail goto*//*Label 1034*/ GIMT_Encode4(61076), // Rule ID 2591 // |
| 17966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 17967 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17968 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17970 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17971 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17972 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 17973 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 17974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 17975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 17978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17979 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17980 | GIR_RootConstrainSelectedInstOperands, |
| 17981 | // GIR_Coverage, 2591, |
| 17982 | GIR_EraseRootFromParent_Done, |
| 17983 | // Label 1034: @61076 |
| 17984 | GIM_Try, /*On fail goto*//*Label 1035*/ GIMT_Encode4(61134), // Rule ID 2592 // |
| 17985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 17986 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 17987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 17988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 17989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 17990 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 17991 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 17992 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 17993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 17994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 17995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 17996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 17997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 17998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 17999 | GIR_RootConstrainSelectedInstOperands, |
| 18000 | // GIR_Coverage, 2592, |
| 18001 | GIR_EraseRootFromParent_Done, |
| 18002 | // Label 1035: @61134 |
| 18003 | GIM_Try, /*On fail goto*//*Label 1036*/ GIMT_Encode4(61195), // Rule ID 2593 // |
| 18004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 18005 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 18011 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 18013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18019 | GIR_RootConstrainSelectedInstOperands, |
| 18020 | // GIR_Coverage, 2593, |
| 18021 | GIR_EraseRootFromParent_Done, |
| 18022 | // Label 1036: @61195 |
| 18023 | GIM_Try, /*On fail goto*//*Label 1037*/ GIMT_Encode4(61249), // Rule ID 2589 // |
| 18024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 18025 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18028 | // MIs[0] sbase |
| 18029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 18030 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 18031 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18032 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18033 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18036 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 18037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18039 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18040 | GIR_RootConstrainSelectedInstOperands, |
| 18041 | // GIR_Coverage, 2589, |
| 18042 | GIR_EraseRootFromParent_Done, |
| 18043 | // Label 1037: @61249 |
| 18044 | GIM_Try, /*On fail goto*//*Label 1038*/ GIMT_Encode4(61296), // Rule ID 2595 // |
| 18045 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18046 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18048 | // MIs[0] sbase |
| 18049 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 18050 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 18051 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18052 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18055 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 18056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18059 | GIR_RootConstrainSelectedInstOperands, |
| 18060 | // GIR_Coverage, 2595, |
| 18061 | GIR_EraseRootFromParent_Done, |
| 18062 | // Label 1038: @61296 |
| 18063 | GIM_Try, /*On fail goto*//*Label 1039*/ GIMT_Encode4(61359), // Rule ID 6198 // |
| 18064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 18065 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 18070 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 18072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18079 | GIR_RootConstrainSelectedInstOperands, |
| 18080 | // GIR_Coverage, 6198, |
| 18081 | GIR_EraseRootFromParent_Done, |
| 18082 | // Label 1039: @61359 |
| 18083 | GIM_Try, /*On fail goto*//*Label 1040*/ GIMT_Encode4(61422), // Rule ID 6200 // |
| 18084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 18085 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 18090 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 18092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18099 | GIR_RootConstrainSelectedInstOperands, |
| 18100 | // GIR_Coverage, 6200, |
| 18101 | GIR_EraseRootFromParent_Done, |
| 18102 | // Label 1040: @61422 |
| 18103 | GIM_Try, /*On fail goto*//*Label 1041*/ GIMT_Encode4(61482), // Rule ID 3918 // |
| 18104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 18105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 18110 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 18112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 18115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18117 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18118 | GIR_RootConstrainSelectedInstOperands, |
| 18119 | // GIR_Coverage, 3918, |
| 18120 | GIR_EraseRootFromParent_Done, |
| 18121 | // Label 1041: @61482 |
| 18122 | GIM_Try, /*On fail goto*//*Label 1042*/ GIMT_Encode4(61537), // Rule ID 3917 // |
| 18123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 18124 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18125 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18128 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 18129 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 18130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 18131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 18133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18136 | GIR_RootConstrainSelectedInstOperands, |
| 18137 | // GIR_Coverage, 3917, |
| 18138 | GIR_EraseRootFromParent_Done, |
| 18139 | // Label 1042: @61537 |
| 18140 | GIM_Try, /*On fail goto*//*Label 1043*/ GIMT_Encode4(61592), // Rule ID 3916 // |
| 18141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 18142 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18143 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18145 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18146 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 18147 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 18149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18153 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18154 | GIR_RootConstrainSelectedInstOperands, |
| 18155 | // GIR_Coverage, 3916, |
| 18156 | GIR_EraseRootFromParent_Done, |
| 18157 | // Label 1043: @61592 |
| 18158 | GIM_Try, /*On fail goto*//*Label 1044*/ GIMT_Encode4(61662), // Rule ID 4158 // |
| 18159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 18160 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18161 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 18165 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 18167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18174 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18175 | GIR_RootConstrainSelectedInstOperands, |
| 18176 | // GIR_Coverage, 4158, |
| 18177 | GIR_EraseRootFromParent_Done, |
| 18178 | // Label 1044: @61662 |
| 18179 | GIM_Try, /*On fail goto*//*Label 1045*/ GIMT_Encode4(61729), // Rule ID 4160 // |
| 18180 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18181 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18183 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 18185 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 18187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18195 | GIR_RootConstrainSelectedInstOperands, |
| 18196 | // GIR_Coverage, 4160, |
| 18197 | GIR_EraseRootFromParent_Done, |
| 18198 | // Label 1045: @61729 |
| 18199 | GIM_Try, /*On fail goto*//*Label 1046*/ GIMT_Encode4(61797), // Rule ID 6197 // |
| 18200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 18201 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18202 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 18206 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 18208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18215 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18216 | GIR_RootConstrainSelectedInstOperands, |
| 18217 | // GIR_Coverage, 6197, |
| 18218 | GIR_EraseRootFromParent_Done, |
| 18219 | // Label 1046: @61797 |
| 18220 | GIM_Try, /*On fail goto*//*Label 1047*/ GIMT_Encode4(61865), // Rule ID 6199 // |
| 18221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 18222 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18225 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 18227 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 18229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18236 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18237 | GIR_RootConstrainSelectedInstOperands, |
| 18238 | // GIR_Coverage, 6199, |
| 18239 | GIR_EraseRootFromParent_Done, |
| 18240 | // Label 1047: @61865 |
| 18241 | GIM_Try, /*On fail goto*//*Label 1048*/ GIMT_Encode4(61930), // Rule ID 4157 // |
| 18242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 18243 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18244 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18246 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 18248 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 18250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18257 | GIR_RootConstrainSelectedInstOperands, |
| 18258 | // GIR_Coverage, 4157, |
| 18259 | GIR_EraseRootFromParent_Done, |
| 18260 | // Label 1048: @61930 |
| 18261 | GIM_Try, /*On fail goto*//*Label 1049*/ GIMT_Encode4(61992), // Rule ID 4159 // |
| 18262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18263 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18265 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18266 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 18267 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 18269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18276 | GIR_RootConstrainSelectedInstOperands, |
| 18277 | // GIR_Coverage, 4159, |
| 18278 | GIR_EraseRootFromParent_Done, |
| 18279 | // Label 1049: @61992 |
| 18280 | GIM_Try, /*On fail goto*//*Label 1050*/ GIMT_Encode4(62051), // Rule ID 7471 // |
| 18281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 18282 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18283 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 18284 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 18288 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 18289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 18290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 18292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18295 | GIR_RootConstrainSelectedInstOperands, |
| 18296 | // GIR_Coverage, 7471, |
| 18297 | GIR_EraseRootFromParent_Done, |
| 18298 | // Label 1050: @62051 |
| 18299 | GIM_Try, /*On fail goto*//*Label 1051*/ GIMT_Encode4(62106), // Rule ID 7472 // |
| 18300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 18301 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 18302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 18306 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 18307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 18308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 18310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18313 | GIR_RootConstrainSelectedInstOperands, |
| 18314 | // GIR_Coverage, 7472, |
| 18315 | GIR_EraseRootFromParent_Done, |
| 18316 | // Label 1051: @62106 |
| 18317 | GIM_Try, /*On fail goto*//*Label 1052*/ GIMT_Encode4(62168), // Rule ID 3477 // |
| 18318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 18319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18320 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18322 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 18324 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 18326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 18328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 18329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18331 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18332 | GIR_RootConstrainSelectedInstOperands, |
| 18333 | // GIR_Coverage, 3477, |
| 18334 | GIR_EraseRootFromParent_Done, |
| 18335 | // Label 1052: @62168 |
| 18336 | GIM_Try, /*On fail goto*//*Label 1053*/ GIMT_Encode4(62225), // Rule ID 3476 // |
| 18337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 18338 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18339 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 18343 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 18345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18350 | GIR_RootConstrainSelectedInstOperands, |
| 18351 | // GIR_Coverage, 3476, |
| 18352 | GIR_EraseRootFromParent_Done, |
| 18353 | // Label 1053: @62225 |
| 18354 | GIM_Try, /*On fail goto*//*Label 1054*/ GIMT_Encode4(62283), // Rule ID 3243 // |
| 18355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 18356 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18357 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 18361 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 18363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18368 | GIR_RootConstrainSelectedInstOperands, |
| 18369 | // GIR_Coverage, 3243, |
| 18370 | GIR_EraseRootFromParent_Done, |
| 18371 | // Label 1054: @62283 |
| 18372 | GIM_Reject, |
| 18373 | // Label 853: @62284 |
| 18374 | GIM_Try, /*On fail goto*//*Label 1055*/ GIMT_Encode4(62351), // Rule ID 2600 // |
| 18375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 18376 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18377 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18380 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18381 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 18383 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 18385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18390 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18391 | GIR_RootConstrainSelectedInstOperands, |
| 18392 | // GIR_Coverage, 2600, |
| 18393 | GIR_EraseRootFromParent_Done, |
| 18394 | // Label 1055: @62351 |
| 18395 | GIM_Try, /*On fail goto*//*Label 1056*/ GIMT_Encode4(62414), // Rule ID 2606 // |
| 18396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 18397 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18401 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 18403 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 18405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18410 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18411 | GIR_RootConstrainSelectedInstOperands, |
| 18412 | // GIR_Coverage, 2606, |
| 18413 | GIR_EraseRootFromParent_Done, |
| 18414 | // Label 1056: @62414 |
| 18415 | GIM_Try, /*On fail goto*//*Label 1057*/ GIMT_Encode4(62476), // Rule ID 2596 // |
| 18416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 18417 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18418 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18421 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18422 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 18424 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18430 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18431 | GIR_RootConstrainSelectedInstOperands, |
| 18432 | // GIR_Coverage, 2596, |
| 18433 | GIR_EraseRootFromParent_Done, |
| 18434 | // Label 1057: @62476 |
| 18435 | GIM_Try, /*On fail goto*//*Label 1058*/ GIMT_Encode4(62538), // Rule ID 2597 // |
| 18436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 18437 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18438 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18440 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18441 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18442 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18443 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 18444 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 18446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18450 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18451 | GIR_RootConstrainSelectedInstOperands, |
| 18452 | // GIR_Coverage, 2597, |
| 18453 | GIR_EraseRootFromParent_Done, |
| 18454 | // Label 1058: @62538 |
| 18455 | GIM_Try, /*On fail goto*//*Label 1059*/ GIMT_Encode4(62600), // Rule ID 2598 // |
| 18456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 18457 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18458 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18460 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18461 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18462 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 18464 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 18465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 18466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18471 | GIR_RootConstrainSelectedInstOperands, |
| 18472 | // GIR_Coverage, 2598, |
| 18473 | GIR_EraseRootFromParent_Done, |
| 18474 | // Label 1059: @62600 |
| 18475 | GIM_Try, /*On fail goto*//*Label 1060*/ GIMT_Encode4(62665), // Rule ID 2599 // |
| 18476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 18477 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18480 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18481 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18482 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 18484 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 18486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18491 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18492 | GIR_RootConstrainSelectedInstOperands, |
| 18493 | // GIR_Coverage, 2599, |
| 18494 | GIR_EraseRootFromParent_Done, |
| 18495 | // Label 1060: @62665 |
| 18496 | GIM_Try, /*On fail goto*//*Label 1061*/ GIMT_Encode4(62720), // Rule ID 2602 // |
| 18497 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18498 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18500 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18501 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 18503 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18509 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18510 | GIR_RootConstrainSelectedInstOperands, |
| 18511 | // GIR_Coverage, 2602, |
| 18512 | GIR_EraseRootFromParent_Done, |
| 18513 | // Label 1061: @62720 |
| 18514 | GIM_Try, /*On fail goto*//*Label 1062*/ GIMT_Encode4(62778), // Rule ID 2603 // |
| 18515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 18516 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18517 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18519 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 18522 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 18524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18529 | GIR_RootConstrainSelectedInstOperands, |
| 18530 | // GIR_Coverage, 2603, |
| 18531 | GIR_EraseRootFromParent_Done, |
| 18532 | // Label 1062: @62778 |
| 18533 | GIM_Try, /*On fail goto*//*Label 1063*/ GIMT_Encode4(62836), // Rule ID 2604 // |
| 18534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 18535 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18536 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18539 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 18541 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 18542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 18543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18547 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18548 | GIR_RootConstrainSelectedInstOperands, |
| 18549 | // GIR_Coverage, 2604, |
| 18550 | GIR_EraseRootFromParent_Done, |
| 18551 | // Label 1063: @62836 |
| 18552 | GIM_Try, /*On fail goto*//*Label 1064*/ GIMT_Encode4(62897), // Rule ID 2605 // |
| 18553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 18554 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18555 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18557 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18558 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 18560 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 18562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18567 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18568 | GIR_RootConstrainSelectedInstOperands, |
| 18569 | // GIR_Coverage, 2605, |
| 18570 | GIR_EraseRootFromParent_Done, |
| 18571 | // Label 1064: @62897 |
| 18572 | GIM_Try, /*On fail goto*//*Label 1065*/ GIMT_Encode4(62951), // Rule ID 2601 // |
| 18573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 18574 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18575 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18577 | // MIs[0] sbase |
| 18578 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 18579 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 18580 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18581 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18582 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18585 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 18586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18588 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18589 | GIR_RootConstrainSelectedInstOperands, |
| 18590 | // GIR_Coverage, 2601, |
| 18591 | GIR_EraseRootFromParent_Done, |
| 18592 | // Label 1065: @62951 |
| 18593 | GIM_Try, /*On fail goto*//*Label 1066*/ GIMT_Encode4(62998), // Rule ID 2607 // |
| 18594 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18595 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 18597 | // MIs[0] sbase |
| 18598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 18599 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 18600 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18601 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 18602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 18603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18604 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 18605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18608 | GIR_RootConstrainSelectedInstOperands, |
| 18609 | // GIR_Coverage, 2607, |
| 18610 | GIR_EraseRootFromParent_Done, |
| 18611 | // Label 1066: @62998 |
| 18612 | GIM_Try, /*On fail goto*//*Label 1067*/ GIMT_Encode4(63061), // Rule ID 6202 // |
| 18613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 18614 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18615 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 18619 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 18621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18628 | GIR_RootConstrainSelectedInstOperands, |
| 18629 | // GIR_Coverage, 6202, |
| 18630 | GIR_EraseRootFromParent_Done, |
| 18631 | // Label 1067: @63061 |
| 18632 | GIM_Try, /*On fail goto*//*Label 1068*/ GIMT_Encode4(63124), // Rule ID 6204 // |
| 18633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 18634 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18635 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 18639 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 18641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18648 | GIR_RootConstrainSelectedInstOperands, |
| 18649 | // GIR_Coverage, 6204, |
| 18650 | GIR_EraseRootFromParent_Done, |
| 18651 | // Label 1068: @63124 |
| 18652 | GIM_Try, /*On fail goto*//*Label 1069*/ GIMT_Encode4(63184), // Rule ID 3924 // |
| 18653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 18654 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 18659 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 18661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 18664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18667 | GIR_RootConstrainSelectedInstOperands, |
| 18668 | // GIR_Coverage, 3924, |
| 18669 | GIR_EraseRootFromParent_Done, |
| 18670 | // Label 1069: @63184 |
| 18671 | GIM_Try, /*On fail goto*//*Label 1070*/ GIMT_Encode4(63239), // Rule ID 3923 // |
| 18672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 18673 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18676 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18677 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 18678 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 18679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 18680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 18682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18684 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18685 | GIR_RootConstrainSelectedInstOperands, |
| 18686 | // GIR_Coverage, 3923, |
| 18687 | GIR_EraseRootFromParent_Done, |
| 18688 | // Label 1070: @63239 |
| 18689 | GIM_Try, /*On fail goto*//*Label 1071*/ GIMT_Encode4(63294), // Rule ID 3922 // |
| 18690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 18691 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 18696 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 18698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18703 | GIR_RootConstrainSelectedInstOperands, |
| 18704 | // GIR_Coverage, 3922, |
| 18705 | GIR_EraseRootFromParent_Done, |
| 18706 | // Label 1071: @63294 |
| 18707 | GIM_Try, /*On fail goto*//*Label 1072*/ GIMT_Encode4(63364), // Rule ID 4162 // |
| 18708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 18709 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18712 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18713 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 18714 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 18716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18724 | GIR_RootConstrainSelectedInstOperands, |
| 18725 | // GIR_Coverage, 4162, |
| 18726 | GIR_EraseRootFromParent_Done, |
| 18727 | // Label 1072: @63364 |
| 18728 | GIM_Try, /*On fail goto*//*Label 1073*/ GIMT_Encode4(63431), // Rule ID 4164 // |
| 18729 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18730 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 18734 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 18736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18743 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18744 | GIR_RootConstrainSelectedInstOperands, |
| 18745 | // GIR_Coverage, 4164, |
| 18746 | GIR_EraseRootFromParent_Done, |
| 18747 | // Label 1073: @63431 |
| 18748 | GIM_Try, /*On fail goto*//*Label 1074*/ GIMT_Encode4(63499), // Rule ID 6201 // |
| 18749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 18750 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18751 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 18755 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 18757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18765 | GIR_RootConstrainSelectedInstOperands, |
| 18766 | // GIR_Coverage, 6201, |
| 18767 | GIR_EraseRootFromParent_Done, |
| 18768 | // Label 1074: @63499 |
| 18769 | GIM_Try, /*On fail goto*//*Label 1075*/ GIMT_Encode4(63567), // Rule ID 6203 // |
| 18770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 18771 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 18772 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 18776 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 18777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 18778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 18780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 18782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 18783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18785 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18786 | GIR_RootConstrainSelectedInstOperands, |
| 18787 | // GIR_Coverage, 6203, |
| 18788 | GIR_EraseRootFromParent_Done, |
| 18789 | // Label 1075: @63567 |
| 18790 | GIM_Try, /*On fail goto*//*Label 1076*/ GIMT_Encode4(63632), // Rule ID 4161 // |
| 18791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 18792 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18793 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 18797 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 18799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18805 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18806 | GIR_RootConstrainSelectedInstOperands, |
| 18807 | // GIR_Coverage, 4161, |
| 18808 | GIR_EraseRootFromParent_Done, |
| 18809 | // Label 1076: @63632 |
| 18810 | GIM_Try, /*On fail goto*//*Label 1077*/ GIMT_Encode4(63694), // Rule ID 4163 // |
| 18811 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18812 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18814 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18815 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 18816 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 18817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 18818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 18819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 18820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18825 | GIR_RootConstrainSelectedInstOperands, |
| 18826 | // GIR_Coverage, 4163, |
| 18827 | GIR_EraseRootFromParent_Done, |
| 18828 | // Label 1077: @63694 |
| 18829 | GIM_Try, /*On fail goto*//*Label 1078*/ GIMT_Encode4(63753), // Rule ID 7473 // |
| 18830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 18831 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18832 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 18833 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18835 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18836 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 18837 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 18838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 18839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 18841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18843 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18844 | GIR_RootConstrainSelectedInstOperands, |
| 18845 | // GIR_Coverage, 7473, |
| 18846 | GIR_EraseRootFromParent_Done, |
| 18847 | // Label 1078: @63753 |
| 18848 | GIM_Try, /*On fail goto*//*Label 1079*/ GIMT_Encode4(63808), // Rule ID 7474 // |
| 18849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 18850 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 18851 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 18855 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 18856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 18857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 18859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18861 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18862 | GIR_RootConstrainSelectedInstOperands, |
| 18863 | // GIR_Coverage, 7474, |
| 18864 | GIR_EraseRootFromParent_Done, |
| 18865 | // Label 1079: @63808 |
| 18866 | GIM_Try, /*On fail goto*//*Label 1080*/ GIMT_Encode4(63870), // Rule ID 3481 // |
| 18867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 18868 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18869 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 18873 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 18875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 18877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 18878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18880 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18881 | GIR_RootConstrainSelectedInstOperands, |
| 18882 | // GIR_Coverage, 3481, |
| 18883 | GIR_EraseRootFromParent_Done, |
| 18884 | // Label 1080: @63870 |
| 18885 | GIM_Try, /*On fail goto*//*Label 1081*/ GIMT_Encode4(63927), // Rule ID 3480 // |
| 18886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 18887 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18888 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 18892 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 18894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18898 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18899 | GIR_RootConstrainSelectedInstOperands, |
| 18900 | // GIR_Coverage, 3480, |
| 18901 | GIR_EraseRootFromParent_Done, |
| 18902 | // Label 1081: @63927 |
| 18903 | GIM_Try, /*On fail goto*//*Label 1082*/ GIMT_Encode4(63985), // Rule ID 3245 // |
| 18904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 18905 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 18906 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 18908 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18909 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 18910 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 18911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 18912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 18913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 18914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18917 | GIR_RootConstrainSelectedInstOperands, |
| 18918 | // GIR_Coverage, 3245, |
| 18919 | GIR_EraseRootFromParent_Done, |
| 18920 | // Label 1082: @63985 |
| 18921 | GIM_Reject, |
| 18922 | // Label 854: @63986 |
| 18923 | GIM_Try, /*On fail goto*//*Label 1083*/ GIMT_Encode4(64618), |
| 18924 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 18925 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 18926 | GIM_Try, /*On fail goto*//*Label 1084*/ GIMT_Encode4(64058), // Rule ID 2680 // |
| 18927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 18928 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 18930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18931 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 18933 | // (ld:{ *:[i1] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 18935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18940 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18941 | GIR_RootConstrainSelectedInstOperands, |
| 18942 | // GIR_Coverage, 2680, |
| 18943 | GIR_EraseRootFromParent_Done, |
| 18944 | // Label 1084: @64058 |
| 18945 | GIM_Try, /*On fail goto*//*Label 1085*/ GIMT_Encode4(64113), // Rule ID 2686 // |
| 18946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 18947 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 18949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 18951 | // (ld:{ *:[i1] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 18953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 18956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 18957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18959 | GIR_RootConstrainSelectedInstOperands, |
| 18960 | // GIR_Coverage, 2686, |
| 18961 | GIR_EraseRootFromParent_Done, |
| 18962 | // Label 1085: @64113 |
| 18963 | GIM_Try, /*On fail goto*//*Label 1086*/ GIMT_Encode4(64167), // Rule ID 2676 // |
| 18964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 18965 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 18967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18968 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 18970 | // (ld:{ *:[i1] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 18972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18977 | GIR_RootConstrainSelectedInstOperands, |
| 18978 | // GIR_Coverage, 2676, |
| 18979 | GIR_EraseRootFromParent_Done, |
| 18980 | // Label 1086: @64167 |
| 18981 | GIM_Try, /*On fail goto*//*Label 1087*/ GIMT_Encode4(64221), // Rule ID 2677 // |
| 18982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 18983 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 18984 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 18985 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 18986 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 18987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 18988 | // (ld:{ *:[i1] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 18989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 18990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 18991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 18992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 18993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 18994 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 18995 | GIR_RootConstrainSelectedInstOperands, |
| 18996 | // GIR_Coverage, 2677, |
| 18997 | GIR_EraseRootFromParent_Done, |
| 18998 | // Label 1087: @64221 |
| 18999 | GIM_Try, /*On fail goto*//*Label 1088*/ GIMT_Encode4(64275), // Rule ID 2678 // |
| 19000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 19001 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19003 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19004 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 19005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 19006 | // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 19007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 19008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19013 | GIR_RootConstrainSelectedInstOperands, |
| 19014 | // GIR_Coverage, 2678, |
| 19015 | GIR_EraseRootFromParent_Done, |
| 19016 | // Label 1088: @64275 |
| 19017 | GIM_Try, /*On fail goto*//*Label 1089*/ GIMT_Encode4(64332), // Rule ID 2679 // |
| 19018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 19019 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19022 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 19023 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 19024 | // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 19025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 19026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19032 | GIR_RootConstrainSelectedInstOperands, |
| 19033 | // GIR_Coverage, 2679, |
| 19034 | GIR_EraseRootFromParent_Done, |
| 19035 | // Label 1089: @64332 |
| 19036 | GIM_Try, /*On fail goto*//*Label 1090*/ GIMT_Encode4(64379), // Rule ID 2682 // |
| 19037 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19039 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19040 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 19041 | // (ld:{ *:[i1] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 19043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19048 | GIR_RootConstrainSelectedInstOperands, |
| 19049 | // GIR_Coverage, 2682, |
| 19050 | GIR_EraseRootFromParent_Done, |
| 19051 | // Label 1090: @64379 |
| 19052 | GIM_Try, /*On fail goto*//*Label 1091*/ GIMT_Encode4(64429), // Rule ID 2683 // |
| 19053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 19054 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19056 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 19058 | // (ld:{ *:[i1] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 19060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19065 | GIR_RootConstrainSelectedInstOperands, |
| 19066 | // GIR_Coverage, 2683, |
| 19067 | GIR_EraseRootFromParent_Done, |
| 19068 | // Label 1091: @64429 |
| 19069 | GIM_Try, /*On fail goto*//*Label 1092*/ GIMT_Encode4(64479), // Rule ID 2684 // |
| 19070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 19071 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19074 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 19075 | // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 19076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 19077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19081 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19082 | GIR_RootConstrainSelectedInstOperands, |
| 19083 | // GIR_Coverage, 2684, |
| 19084 | GIR_EraseRootFromParent_Done, |
| 19085 | // Label 1092: @64479 |
| 19086 | GIM_Try, /*On fail goto*//*Label 1093*/ GIMT_Encode4(64532), // Rule ID 2685 // |
| 19087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 19088 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 19092 | // (ld:{ *:[i1] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i1] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 19093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 19094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 19096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19099 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19100 | GIR_RootConstrainSelectedInstOperands, |
| 19101 | // GIR_Coverage, 2685, |
| 19102 | GIR_EraseRootFromParent_Done, |
| 19103 | // Label 1093: @64532 |
| 19104 | GIM_Try, /*On fail goto*//*Label 1094*/ GIMT_Encode4(64578), // Rule ID 2681 // |
| 19105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 19106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19108 | // MIs[0] sbase |
| 19109 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 19110 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 19111 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 19112 | // (ld:{ *:[i1] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i1] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 19113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 19114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19115 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 19116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19119 | GIR_RootConstrainSelectedInstOperands, |
| 19120 | // GIR_Coverage, 2681, |
| 19121 | GIR_EraseRootFromParent_Done, |
| 19122 | // Label 1094: @64578 |
| 19123 | GIM_Try, /*On fail goto*//*Label 1095*/ GIMT_Encode4(64617), // Rule ID 2687 // |
| 19124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 19126 | // MIs[0] sbase |
| 19127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 19128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 19129 | // (ld:{ *:[i1] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i1] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 19130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 19131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 19132 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 19133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19136 | GIR_RootConstrainSelectedInstOperands, |
| 19137 | // GIR_Coverage, 2687, |
| 19138 | GIR_EraseRootFromParent_Done, |
| 19139 | // Label 1095: @64617 |
| 19140 | GIM_Reject, |
| 19141 | // Label 1083: @64618 |
| 19142 | GIM_Reject, |
| 19143 | // Label 855: @64619 |
| 19144 | GIM_Try, /*On fail goto*//*Label 1096*/ GIMT_Encode4(64693), // Rule ID 6146 // |
| 19145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 19146 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19147 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19148 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19149 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19151 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19152 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 19153 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 19155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19161 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19162 | GIR_RootConstrainSelectedInstOperands, |
| 19163 | // GIR_Coverage, 6146, |
| 19164 | GIR_EraseRootFromParent_Done, |
| 19165 | // Label 1096: @64693 |
| 19166 | GIM_Try, /*On fail goto*//*Label 1097*/ GIMT_Encode4(64767), // Rule ID 6148 // |
| 19167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 19168 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19169 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19170 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19171 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19173 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19174 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 19175 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19176 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 19177 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19184 | GIR_RootConstrainSelectedInstOperands, |
| 19185 | // GIR_Coverage, 6148, |
| 19186 | GIR_EraseRootFromParent_Done, |
| 19187 | // Label 1097: @64767 |
| 19188 | GIM_Try, /*On fail goto*//*Label 1098*/ GIMT_Encode4(64830), // Rule ID 6166 // |
| 19189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 19190 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19191 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19193 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 19195 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 19197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19203 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19204 | GIR_RootConstrainSelectedInstOperands, |
| 19205 | // GIR_Coverage, 6166, |
| 19206 | GIR_EraseRootFromParent_Done, |
| 19207 | // Label 1098: @64830 |
| 19208 | GIM_Try, /*On fail goto*//*Label 1099*/ GIMT_Encode4(64893), // Rule ID 6168 // |
| 19209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 19210 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19211 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19213 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19214 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 19215 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 19217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19223 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19224 | GIR_RootConstrainSelectedInstOperands, |
| 19225 | // GIR_Coverage, 6168, |
| 19226 | GIR_EraseRootFromParent_Done, |
| 19227 | // Label 1099: @64893 |
| 19228 | GIM_Try, /*On fail goto*//*Label 1100*/ GIMT_Encode4(64964), // Rule ID 3858 // |
| 19229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 19230 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19231 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19232 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19233 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19236 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 19237 | // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS), |
| 19239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 19242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19245 | GIR_RootConstrainSelectedInstOperands, |
| 19246 | // GIR_Coverage, 3858, |
| 19247 | GIR_EraseRootFromParent_Done, |
| 19248 | // Label 1100: @64964 |
| 19249 | GIM_Try, /*On fail goto*//*Label 1101*/ GIMT_Encode4(65024), // Rule ID 3876 // |
| 19250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 19251 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19252 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19254 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19255 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 19256 | // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_USHORT_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS), |
| 19258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 19261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19263 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19264 | GIR_RootConstrainSelectedInstOperands, |
| 19265 | // GIR_Coverage, 3876, |
| 19266 | GIR_EraseRootFromParent_Done, |
| 19267 | // Label 1101: @65024 |
| 19268 | GIM_Try, /*On fail goto*//*Label 1102*/ GIMT_Encode4(65090), // Rule ID 3857 // |
| 19269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 19270 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19271 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19272 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19273 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19275 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 19277 | // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 19278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR), |
| 19279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19283 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19284 | GIR_RootConstrainSelectedInstOperands, |
| 19285 | // GIR_Coverage, 3857, |
| 19286 | GIR_EraseRootFromParent_Done, |
| 19287 | // Label 1102: @65090 |
| 19288 | GIM_Try, /*On fail goto*//*Label 1103*/ GIMT_Encode4(65145), // Rule ID 3875 // |
| 19289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 19290 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19291 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19293 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19294 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 19295 | // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 19296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR), |
| 19297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19302 | GIR_RootConstrainSelectedInstOperands, |
| 19303 | // GIR_Coverage, 3875, |
| 19304 | GIR_EraseRootFromParent_Done, |
| 19305 | // Label 1103: @65145 |
| 19306 | GIM_Try, /*On fail goto*//*Label 1104*/ GIMT_Encode4(65211), // Rule ID 3856 // |
| 19307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 19308 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19309 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19310 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19311 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 19315 | // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 19316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE), |
| 19317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19321 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19322 | GIR_RootConstrainSelectedInstOperands, |
| 19323 | // GIR_Coverage, 3856, |
| 19324 | GIR_EraseRootFromParent_Done, |
| 19325 | // Label 1104: @65211 |
| 19326 | GIM_Try, /*On fail goto*//*Label 1105*/ GIMT_Encode4(65266), // Rule ID 3874 // |
| 19327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 19328 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19329 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19331 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 19333 | // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_USHORT:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 19334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT), |
| 19335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19339 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19340 | GIR_RootConstrainSelectedInstOperands, |
| 19341 | // GIR_Coverage, 3874, |
| 19342 | GIR_EraseRootFromParent_Done, |
| 19343 | // Label 1105: @65266 |
| 19344 | GIM_Try, /*On fail goto*//*Label 1106*/ GIMT_Encode4(65343), // Rule ID 4098 // |
| 19345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 19346 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19347 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19348 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19350 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 19352 | // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 19354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19362 | GIR_RootConstrainSelectedInstOperands, |
| 19363 | // GIR_Coverage, 4098, |
| 19364 | GIR_EraseRootFromParent_Done, |
| 19365 | // Label 1106: @65343 |
| 19366 | GIM_Try, /*On fail goto*//*Label 1107*/ GIMT_Encode4(65417), // Rule ID 4100 // |
| 19367 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19368 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19369 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 19373 | // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64), |
| 19375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19382 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19383 | GIR_RootConstrainSelectedInstOperands, |
| 19384 | // GIR_Coverage, 4100, |
| 19385 | GIR_EraseRootFromParent_Done, |
| 19386 | // Label 1107: @65417 |
| 19387 | GIM_Try, /*On fail goto*//*Label 1108*/ GIMT_Encode4(65494), // Rule ID 4102 // |
| 19388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 19389 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19390 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19391 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 19395 | // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 19397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19404 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19405 | GIR_RootConstrainSelectedInstOperands, |
| 19406 | // GIR_Coverage, 4102, |
| 19407 | GIR_EraseRootFromParent_Done, |
| 19408 | // Label 1108: @65494 |
| 19409 | GIM_Try, /*On fail goto*//*Label 1109*/ GIMT_Encode4(65568), // Rule ID 4104 // |
| 19410 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19411 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19412 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19414 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 19416 | // (atomic_load:{ *:[i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64), |
| 19418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19426 | GIR_RootConstrainSelectedInstOperands, |
| 19427 | // GIR_Coverage, 4104, |
| 19428 | GIR_EraseRootFromParent_Done, |
| 19429 | // Label 1109: @65568 |
| 19430 | GIM_Try, /*On fail goto*//*Label 1110*/ GIMT_Encode4(65647), // Rule ID 6145 // |
| 19431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 19432 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19433 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19434 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19435 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19437 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19438 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 19439 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), |
| 19441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19449 | GIR_RootConstrainSelectedInstOperands, |
| 19450 | // GIR_Coverage, 6145, |
| 19451 | GIR_EraseRootFromParent_Done, |
| 19452 | // Label 1110: @65647 |
| 19453 | GIM_Try, /*On fail goto*//*Label 1111*/ GIMT_Encode4(65726), // Rule ID 6147 // |
| 19454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 19455 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19456 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19457 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19458 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19460 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 19462 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN), |
| 19464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19471 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19472 | GIR_RootConstrainSelectedInstOperands, |
| 19473 | // GIR_Coverage, 6147, |
| 19474 | GIR_EraseRootFromParent_Done, |
| 19475 | // Label 1111: @65726 |
| 19476 | GIM_Try, /*On fail goto*//*Label 1112*/ GIMT_Encode4(65794), // Rule ID 6165 // |
| 19477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 19478 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19479 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 19483 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_USHORT_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), |
| 19485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19493 | GIR_RootConstrainSelectedInstOperands, |
| 19494 | // GIR_Coverage, 6165, |
| 19495 | GIR_EraseRootFromParent_Done, |
| 19496 | // Label 1112: @65794 |
| 19497 | GIM_Try, /*On fail goto*//*Label 1113*/ GIMT_Encode4(65862), // Rule ID 6167 // |
| 19498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 19499 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 19500 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 19504 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 19505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN), |
| 19506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 19508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 19510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 19511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19514 | GIR_RootConstrainSelectedInstOperands, |
| 19515 | // GIR_Coverage, 6167, |
| 19516 | GIR_EraseRootFromParent_Done, |
| 19517 | // Label 1113: @65862 |
| 19518 | GIM_Try, /*On fail goto*//*Label 1114*/ GIMT_Encode4(65934), // Rule ID 4097 // |
| 19519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 19520 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19521 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19522 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19524 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19526 | // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 19528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19535 | GIR_RootConstrainSelectedInstOperands, |
| 19536 | // GIR_Coverage, 4097, |
| 19537 | GIR_EraseRootFromParent_Done, |
| 19538 | // Label 1114: @65934 |
| 19539 | GIM_Try, /*On fail goto*//*Label 1115*/ GIMT_Encode4(66003), // Rule ID 4099 // |
| 19540 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19541 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19542 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19546 | // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 19548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19555 | GIR_RootConstrainSelectedInstOperands, |
| 19556 | // GIR_Coverage, 4099, |
| 19557 | GIR_EraseRootFromParent_Done, |
| 19558 | // Label 1115: @66003 |
| 19559 | GIM_Try, /*On fail goto*//*Label 1116*/ GIMT_Encode4(66075), // Rule ID 4101 // |
| 19560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 19561 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19562 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19563 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19567 | // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 19569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19575 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19576 | GIR_RootConstrainSelectedInstOperands, |
| 19577 | // GIR_Coverage, 4101, |
| 19578 | GIR_EraseRootFromParent_Done, |
| 19579 | // Label 1116: @66075 |
| 19580 | GIM_Try, /*On fail goto*//*Label 1117*/ GIMT_Encode4(66144), // Rule ID 4103 // |
| 19581 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19583 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19587 | // (atomic_load:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 19588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 19589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19596 | GIR_RootConstrainSelectedInstOperands, |
| 19597 | // GIR_Coverage, 4103, |
| 19598 | GIR_EraseRootFromParent_Done, |
| 19599 | // Label 1117: @66144 |
| 19600 | GIM_Try, /*On fail goto*//*Label 1118*/ GIMT_Encode4(66219), // Rule ID 6115 // |
| 19601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19602 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19603 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19604 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19605 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19607 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19608 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19609 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 19611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19617 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19618 | GIR_RootConstrainSelectedInstOperands, |
| 19619 | // GIR_Coverage, 6115, |
| 19620 | GIR_EraseRootFromParent_Done, |
| 19621 | // Label 1118: @66219 |
| 19622 | GIM_Try, /*On fail goto*//*Label 1119*/ GIMT_Encode4(66294), // Rule ID 6116 // |
| 19623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19624 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19625 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19626 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19627 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19629 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19631 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 19633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19640 | GIR_RootConstrainSelectedInstOperands, |
| 19641 | // GIR_Coverage, 6116, |
| 19642 | GIR_EraseRootFromParent_Done, |
| 19643 | // Label 1119: @66294 |
| 19644 | GIM_Try, /*On fail goto*//*Label 1120*/ GIMT_Encode4(66370), // Rule ID 6121 // |
| 19645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19646 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19647 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19648 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19649 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19651 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19652 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19653 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 19655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19662 | GIR_RootConstrainSelectedInstOperands, |
| 19663 | // GIR_Coverage, 6121, |
| 19664 | GIR_EraseRootFromParent_Done, |
| 19665 | // Label 1120: @66370 |
| 19666 | GIM_Try, /*On fail goto*//*Label 1121*/ GIMT_Encode4(66446), // Rule ID 6122 // |
| 19667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19668 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19669 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19670 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19671 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19674 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19675 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 19677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19683 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19684 | GIR_RootConstrainSelectedInstOperands, |
| 19685 | // GIR_Coverage, 6122, |
| 19686 | GIR_EraseRootFromParent_Done, |
| 19687 | // Label 1121: @66446 |
| 19688 | GIM_Try, /*On fail goto*//*Label 1122*/ GIMT_Encode4(66511), // Rule ID 6125 // |
| 19689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19690 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19691 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19693 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19695 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 19697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19703 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19704 | GIR_RootConstrainSelectedInstOperands, |
| 19705 | // GIR_Coverage, 6125, |
| 19706 | GIR_EraseRootFromParent_Done, |
| 19707 | // Label 1122: @66511 |
| 19708 | GIM_Try, /*On fail goto*//*Label 1123*/ GIMT_Encode4(66576), // Rule ID 6126 // |
| 19709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 19710 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19711 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 19715 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 19716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 19717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 19718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 19719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 19720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19724 | GIR_RootConstrainSelectedInstOperands, |
| 19725 | // GIR_Coverage, 6126, |
| 19726 | GIR_EraseRootFromParent_Done, |
| 19727 | // Label 1123: @66576 |
| 19728 | GIM_Try, /*On fail goto*//*Label 1124*/ GIMT_Encode4(66638), // Rule ID 7475 // |
| 19729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 19730 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19731 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19732 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19734 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19736 | // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8_glue>><<P:Predicate_atomic_load_8_local_m0>> => (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 19738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19743 | GIR_RootConstrainSelectedInstOperands, |
| 19744 | // GIR_Coverage, 7475, |
| 19745 | GIR_EraseRootFromParent_Done, |
| 19746 | // Label 1124: @66638 |
| 19747 | GIM_Try, /*On fail goto*//*Label 1125*/ GIMT_Encode4(66700), // Rule ID 7476 // |
| 19748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 19749 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19750 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19751 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19755 | // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_local>> => (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 19757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19761 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19762 | GIR_RootConstrainSelectedInstOperands, |
| 19763 | // GIR_Coverage, 7476, |
| 19764 | GIR_EraseRootFromParent_Done, |
| 19765 | // Label 1125: @66700 |
| 19766 | GIM_Try, /*On fail goto*//*Label 1126*/ GIMT_Encode4(66762), // Rule ID 7479 // |
| 19767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 19768 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19769 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19770 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19774 | // (AMDGPUatomic_ld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16_glue>><<P:Predicate_atomic_load_16_local_m0>> => (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16), |
| 19776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19781 | GIR_RootConstrainSelectedInstOperands, |
| 19782 | // GIR_Coverage, 7479, |
| 19783 | GIR_EraseRootFromParent_Done, |
| 19784 | // Label 1126: @66762 |
| 19785 | GIM_Try, /*On fail goto*//*Label 1127*/ GIMT_Encode4(66824), // Rule ID 7480 // |
| 19786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 19787 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19788 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19789 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19793 | // (atomic_load:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_local>> => (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9), |
| 19795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19800 | GIR_RootConstrainSelectedInstOperands, |
| 19801 | // GIR_Coverage, 7480, |
| 19802 | GIR_EraseRootFromParent_Done, |
| 19803 | // Label 1127: @66824 |
| 19804 | GIM_Try, /*On fail goto*//*Label 1128*/ GIMT_Encode4(66890), // Rule ID 7443 // |
| 19805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 19806 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19807 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19808 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19809 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19813 | // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>> => (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 19815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19820 | GIR_RootConstrainSelectedInstOperands, |
| 19821 | // GIR_Coverage, 7443, |
| 19822 | GIR_EraseRootFromParent_Done, |
| 19823 | // Label 1128: @66890 |
| 19824 | GIM_Try, /*On fail goto*//*Label 1129*/ GIMT_Encode4(66956), // Rule ID 7444 // |
| 19825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 19826 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19827 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19828 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19829 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19831 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19833 | // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>> => (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 19835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19840 | GIR_RootConstrainSelectedInstOperands, |
| 19841 | // GIR_Coverage, 7444, |
| 19842 | GIR_EraseRootFromParent_Done, |
| 19843 | // Label 1129: @66956 |
| 19844 | GIM_Try, /*On fail goto*//*Label 1130*/ GIMT_Encode4(67015), // Rule ID 7455 // |
| 19845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 19846 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19847 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19848 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19852 | // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_U16:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16), |
| 19854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19859 | GIR_RootConstrainSelectedInstOperands, |
| 19860 | // GIR_Coverage, 7455, |
| 19861 | GIR_EraseRootFromParent_Done, |
| 19862 | // Label 1130: @67015 |
| 19863 | GIM_Try, /*On fail goto*//*Label 1131*/ GIMT_Encode4(67070), // Rule ID 7456 // |
| 19864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 19865 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 19866 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 19870 | // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_U16_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 19871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9), |
| 19872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 19874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19877 | GIR_RootConstrainSelectedInstOperands, |
| 19878 | // GIR_Coverage, 7456, |
| 19879 | GIR_EraseRootFromParent_Done, |
| 19880 | // Label 1131: @67070 |
| 19881 | GIM_Try, /*On fail goto*//*Label 1132*/ GIMT_Encode4(67139), // Rule ID 3425 // |
| 19882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19883 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19884 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19885 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19888 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 19889 | // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 19891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 19894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19897 | GIR_RootConstrainSelectedInstOperands, |
| 19898 | // GIR_Coverage, 3425, |
| 19899 | GIR_EraseRootFromParent_Done, |
| 19900 | // Label 1132: @67139 |
| 19901 | GIM_Try, /*On fail goto*//*Label 1133*/ GIMT_Encode4(67208), // Rule ID 3429 // |
| 19902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19903 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19904 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19905 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19907 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 19909 | // (atomic_load:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR), |
| 19911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 19914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19917 | GIR_RootConstrainSelectedInstOperands, |
| 19918 | // GIR_Coverage, 3429, |
| 19919 | GIR_EraseRootFromParent_Done, |
| 19920 | // Label 1133: @67208 |
| 19921 | GIM_Try, /*On fail goto*//*Label 1134*/ GIMT_Encode4(67281), // Rule ID 3437 // |
| 19922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19923 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 19924 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19925 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19926 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19929 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 19930 | // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 19932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 19935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19938 | GIR_RootConstrainSelectedInstOperands, |
| 19939 | // GIR_Coverage, 3437, |
| 19940 | GIR_EraseRootFromParent_Done, |
| 19941 | // Label 1134: @67281 |
| 19942 | GIM_Try, /*On fail goto*//*Label 1135*/ GIMT_Encode4(67343), // Rule ID 3449 // |
| 19943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19944 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19945 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 19946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 19949 | // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_USHORT_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 19950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR), |
| 19951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 19953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 19954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 19955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19956 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19957 | GIR_RootConstrainSelectedInstOperands, |
| 19958 | // GIR_Coverage, 3449, |
| 19959 | GIR_EraseRootFromParent_Done, |
| 19960 | // Label 1135: @67343 |
| 19961 | GIM_Try, /*On fail goto*//*Label 1136*/ GIMT_Encode4(67407), // Rule ID 3424 // |
| 19962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19963 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 19964 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19965 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19968 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 19969 | // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 19970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 19971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19975 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19976 | GIR_RootConstrainSelectedInstOperands, |
| 19977 | // GIR_Coverage, 3424, |
| 19978 | GIR_EraseRootFromParent_Done, |
| 19979 | // Label 1136: @67407 |
| 19980 | GIM_Try, /*On fail goto*//*Label 1137*/ GIMT_Encode4(67471), // Rule ID 3428 // |
| 19981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 19982 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 19983 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 19984 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 19985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 19986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 19987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 19988 | // (atomic_load:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 19989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT), |
| 19990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 19991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 19992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 19993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 19994 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 19995 | GIR_RootConstrainSelectedInstOperands, |
| 19996 | // GIR_Coverage, 3428, |
| 19997 | GIR_EraseRootFromParent_Done, |
| 19998 | // Label 1137: @67471 |
| 19999 | GIM_Try, /*On fail goto*//*Label 1138*/ GIMT_Encode4(67539), // Rule ID 3436 // |
| 20000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 20001 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20002 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20003 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20004 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20006 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 20008 | // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 20010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20014 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20015 | GIR_RootConstrainSelectedInstOperands, |
| 20016 | // GIR_Coverage, 3436, |
| 20017 | GIR_EraseRootFromParent_Done, |
| 20018 | // Label 1138: @67539 |
| 20019 | GIM_Try, /*On fail goto*//*Label 1139*/ GIMT_Encode4(67596), // Rule ID 3448 // |
| 20020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 20021 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20022 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20024 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 20026 | // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT), |
| 20028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20033 | GIR_RootConstrainSelectedInstOperands, |
| 20034 | // GIR_Coverage, 3448, |
| 20035 | GIR_EraseRootFromParent_Done, |
| 20036 | // Label 1139: @67596 |
| 20037 | GIM_Try, /*On fail goto*//*Label 1140*/ GIMT_Encode4(67661), // Rule ID 3211 // |
| 20038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 20039 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20040 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20041 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 20042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 20045 | // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 20047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20052 | GIR_RootConstrainSelectedInstOperands, |
| 20053 | // GIR_Coverage, 3211, |
| 20054 | GIR_EraseRootFromParent_Done, |
| 20055 | // Label 1140: @67661 |
| 20056 | GIM_Try, /*On fail goto*//*Label 1141*/ GIMT_Encode4(67726), // Rule ID 3213 // |
| 20057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 20058 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20059 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20060 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 20061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 20064 | // (atomic_load:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_flat>> => (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT), |
| 20066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20070 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20071 | GIR_RootConstrainSelectedInstOperands, |
| 20072 | // GIR_Coverage, 3213, |
| 20073 | GIR_EraseRootFromParent_Done, |
| 20074 | // Label 1141: @67726 |
| 20075 | GIM_Try, /*On fail goto*//*Label 1142*/ GIMT_Encode4(67795), // Rule ID 3217 // |
| 20076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 20077 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20078 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20079 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20080 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20082 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 20084 | // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 20086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20090 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20091 | GIR_RootConstrainSelectedInstOperands, |
| 20092 | // GIR_Coverage, 3217, |
| 20093 | GIR_EraseRootFromParent_Done, |
| 20094 | // Label 1142: @67795 |
| 20095 | GIM_Try, /*On fail goto*//*Label 1143*/ GIMT_Encode4(67853), // Rule ID 3222 // |
| 20096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 20097 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 20098 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20100 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 20102 | // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_USHORT:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 20103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT), |
| 20104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20108 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20109 | GIR_RootConstrainSelectedInstOperands, |
| 20110 | // GIR_Coverage, 3222, |
| 20111 | GIR_EraseRootFromParent_Done, |
| 20112 | // Label 1143: @67853 |
| 20113 | GIM_Reject, |
| 20114 | // Label 856: @67854 |
| 20115 | GIM_Try, /*On fail goto*//*Label 1144*/ GIMT_Encode4(67921), // Rule ID 2463 // |
| 20116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 20117 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20118 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20120 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20121 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20122 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20124 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20126 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20132 | GIR_RootConstrainSelectedInstOperands, |
| 20133 | // GIR_Coverage, 2463, |
| 20134 | GIR_EraseRootFromParent_Done, |
| 20135 | // Label 1144: @67921 |
| 20136 | GIM_Try, /*On fail goto*//*Label 1145*/ GIMT_Encode4(67988), // Rule ID 2516 // |
| 20137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 20138 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20139 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20143 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20145 | // (ld:{ *:[f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20153 | GIR_RootConstrainSelectedInstOperands, |
| 20154 | // GIR_Coverage, 2516, |
| 20155 | GIR_EraseRootFromParent_Done, |
| 20156 | // Label 1145: @67988 |
| 20157 | GIM_Try, /*On fail goto*//*Label 1146*/ GIMT_Encode4(68058), // Rule ID 2472 // |
| 20158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20159 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20160 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20161 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20164 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8), |
| 20165 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20166 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>> => (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM), |
| 20168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20173 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20174 | GIR_RootConstrainSelectedInstOperands, |
| 20175 | // GIR_Coverage, 2472, |
| 20176 | GIR_EraseRootFromParent_Done, |
| 20177 | // Label 1146: @68058 |
| 20178 | GIM_Try, /*On fail goto*//*Label 1147*/ GIMT_Encode4(68128), // Rule ID 2487 // |
| 20179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20180 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20181 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20182 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20184 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20185 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16), |
| 20186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20187 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>> => (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM), |
| 20189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20195 | GIR_RootConstrainSelectedInstOperands, |
| 20196 | // GIR_Coverage, 2487, |
| 20197 | GIR_EraseRootFromParent_Done, |
| 20198 | // Label 1147: @68128 |
| 20199 | GIM_Try, /*On fail goto*//*Label 1148*/ GIMT_Encode4(68191), // Rule ID 2510 // |
| 20200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 20201 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20202 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20205 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20207 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20215 | GIR_RootConstrainSelectedInstOperands, |
| 20216 | // GIR_Coverage, 2510, |
| 20217 | GIR_EraseRootFromParent_Done, |
| 20218 | // Label 1148: @68191 |
| 20219 | GIM_Try, /*On fail goto*//*Label 1149*/ GIMT_Encode4(68254), // Rule ID 2522 // |
| 20220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 20221 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20222 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 20227 | // (ld:{ *:[f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20235 | GIR_RootConstrainSelectedInstOperands, |
| 20236 | // GIR_Coverage, 2522, |
| 20237 | GIR_EraseRootFromParent_Done, |
| 20238 | // Label 1149: @68254 |
| 20239 | GIM_Try, /*On fail goto*//*Label 1150*/ GIMT_Encode4(68316), // Rule ID 2459 // |
| 20240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 20241 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20245 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20246 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20248 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20255 | GIR_RootConstrainSelectedInstOperands, |
| 20256 | // GIR_Coverage, 2459, |
| 20257 | GIR_EraseRootFromParent_Done, |
| 20258 | // Label 1150: @68316 |
| 20259 | GIM_Try, /*On fail goto*//*Label 1151*/ GIMT_Encode4(68378), // Rule ID 2460 // |
| 20260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 20261 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20262 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20265 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20266 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 20268 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 20270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20275 | GIR_RootConstrainSelectedInstOperands, |
| 20276 | // GIR_Coverage, 2460, |
| 20277 | GIR_EraseRootFromParent_Done, |
| 20278 | // Label 1151: @68378 |
| 20279 | GIM_Try, /*On fail goto*//*Label 1152*/ GIMT_Encode4(68440), // Rule ID 2461 // |
| 20280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 20281 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20282 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20285 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20286 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20288 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 20289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 20290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20295 | GIR_RootConstrainSelectedInstOperands, |
| 20296 | // GIR_Coverage, 2461, |
| 20297 | GIR_EraseRootFromParent_Done, |
| 20298 | // Label 1152: @68440 |
| 20299 | GIM_Try, /*On fail goto*//*Label 1153*/ GIMT_Encode4(68505), // Rule ID 2462 // |
| 20300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 20301 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20305 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20308 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20316 | GIR_RootConstrainSelectedInstOperands, |
| 20317 | // GIR_Coverage, 2462, |
| 20318 | GIR_EraseRootFromParent_Done, |
| 20319 | // Label 1153: @68505 |
| 20320 | GIM_Try, /*On fail goto*//*Label 1154*/ GIMT_Encode4(68567), // Rule ID 2512 // |
| 20321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 20322 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20323 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20325 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20327 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20329 | // (ld:{ *:[f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20335 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20336 | GIR_RootConstrainSelectedInstOperands, |
| 20337 | // GIR_Coverage, 2512, |
| 20338 | GIR_EraseRootFromParent_Done, |
| 20339 | // Label 1154: @68567 |
| 20340 | GIM_Try, /*On fail goto*//*Label 1155*/ GIMT_Encode4(68629), // Rule ID 2513 // |
| 20341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 20342 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20343 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20345 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20346 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20347 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20348 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 20349 | // (ld:{ *:[f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 20351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20356 | GIR_RootConstrainSelectedInstOperands, |
| 20357 | // GIR_Coverage, 2513, |
| 20358 | GIR_EraseRootFromParent_Done, |
| 20359 | // Label 1155: @68629 |
| 20360 | GIM_Try, /*On fail goto*//*Label 1156*/ GIMT_Encode4(68691), // Rule ID 2514 // |
| 20361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 20362 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20363 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20365 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20366 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20367 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20369 | // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 20370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 20371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20376 | GIR_RootConstrainSelectedInstOperands, |
| 20377 | // GIR_Coverage, 2514, |
| 20378 | GIR_EraseRootFromParent_Done, |
| 20379 | // Label 1156: @68691 |
| 20380 | GIM_Try, /*On fail goto*//*Label 1157*/ GIMT_Encode4(68756), // Rule ID 2515 // |
| 20381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 20382 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20386 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20387 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20388 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20389 | // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20397 | GIR_RootConstrainSelectedInstOperands, |
| 20398 | // GIR_Coverage, 2515, |
| 20399 | GIR_EraseRootFromParent_Done, |
| 20400 | // Label 1157: @68756 |
| 20401 | GIM_Try, /*On fail goto*//*Label 1158*/ GIMT_Encode4(68821), // Rule ID 2470 // |
| 20402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20403 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20404 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20405 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20408 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8), |
| 20409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20410 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>> => (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM), |
| 20412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20417 | GIR_RootConstrainSelectedInstOperands, |
| 20418 | // GIR_Coverage, 2470, |
| 20419 | GIR_EraseRootFromParent_Done, |
| 20420 | // Label 1158: @68821 |
| 20421 | GIM_Try, /*On fail goto*//*Label 1159*/ GIMT_Encode4(68889), // Rule ID 2471 // |
| 20422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20423 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20424 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20425 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20428 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8), |
| 20429 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20430 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>> => (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM), |
| 20432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20437 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20438 | GIR_RootConstrainSelectedInstOperands, |
| 20439 | // GIR_Coverage, 2471, |
| 20440 | GIR_EraseRootFromParent_Done, |
| 20441 | // Label 1159: @68889 |
| 20442 | GIM_Try, /*On fail goto*//*Label 1160*/ GIMT_Encode4(68954), // Rule ID 2485 // |
| 20443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20444 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20445 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20446 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20449 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16), |
| 20450 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20451 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>> => (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM), |
| 20453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20458 | GIR_RootConstrainSelectedInstOperands, |
| 20459 | // GIR_Coverage, 2485, |
| 20460 | GIR_EraseRootFromParent_Done, |
| 20461 | // Label 1160: @68954 |
| 20462 | GIM_Try, /*On fail goto*//*Label 1161*/ GIMT_Encode4(69022), // Rule ID 2486 // |
| 20463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20464 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20465 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20466 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20468 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20469 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16), |
| 20470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20471 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>> => (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM), |
| 20473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20478 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20479 | GIR_RootConstrainSelectedInstOperands, |
| 20480 | // GIR_Coverage, 2486, |
| 20481 | GIR_EraseRootFromParent_Done, |
| 20482 | // Label 1161: @69022 |
| 20483 | GIM_Try, /*On fail goto*//*Label 1162*/ GIMT_Encode4(69077), // Rule ID 2506 // |
| 20484 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20485 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20486 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20487 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20488 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20490 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20496 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20497 | GIR_RootConstrainSelectedInstOperands, |
| 20498 | // GIR_Coverage, 2506, |
| 20499 | GIR_EraseRootFromParent_Done, |
| 20500 | // Label 1162: @69077 |
| 20501 | GIM_Try, /*On fail goto*//*Label 1163*/ GIMT_Encode4(69135), // Rule ID 2507 // |
| 20502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 20503 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20504 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20506 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20507 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 20509 | // (ld:{ *:[i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 20511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20515 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20516 | GIR_RootConstrainSelectedInstOperands, |
| 20517 | // GIR_Coverage, 2507, |
| 20518 | GIR_EraseRootFromParent_Done, |
| 20519 | // Label 1163: @69135 |
| 20520 | GIM_Try, /*On fail goto*//*Label 1164*/ GIMT_Encode4(69193), // Rule ID 2508 // |
| 20521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 20522 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20523 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20525 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20526 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20527 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20528 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 20529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 20530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20535 | GIR_RootConstrainSelectedInstOperands, |
| 20536 | // GIR_Coverage, 2508, |
| 20537 | GIR_EraseRootFromParent_Done, |
| 20538 | // Label 1164: @69193 |
| 20539 | GIM_Try, /*On fail goto*//*Label 1165*/ GIMT_Encode4(69254), // Rule ID 2509 // |
| 20540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 20541 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20545 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20547 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20555 | GIR_RootConstrainSelectedInstOperands, |
| 20556 | // GIR_Coverage, 2509, |
| 20557 | GIR_EraseRootFromParent_Done, |
| 20558 | // Label 1165: @69254 |
| 20559 | GIM_Try, /*On fail goto*//*Label 1166*/ GIMT_Encode4(69309), // Rule ID 2518 // |
| 20560 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20563 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20564 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20565 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 20566 | // (ld:{ *:[f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20573 | GIR_RootConstrainSelectedInstOperands, |
| 20574 | // GIR_Coverage, 2518, |
| 20575 | GIR_EraseRootFromParent_Done, |
| 20576 | // Label 1166: @69309 |
| 20577 | GIM_Try, /*On fail goto*//*Label 1167*/ GIMT_Encode4(69367), // Rule ID 2519 // |
| 20578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 20579 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20580 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20582 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20583 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20584 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 20585 | // (ld:{ *:[f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 20587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 20590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20592 | GIR_RootConstrainSelectedInstOperands, |
| 20593 | // GIR_Coverage, 2519, |
| 20594 | GIR_EraseRootFromParent_Done, |
| 20595 | // Label 1167: @69367 |
| 20596 | GIM_Try, /*On fail goto*//*Label 1168*/ GIMT_Encode4(69425), // Rule ID 2520 // |
| 20597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 20598 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20599 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20602 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20603 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20604 | // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 20605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 20606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20611 | GIR_RootConstrainSelectedInstOperands, |
| 20612 | // GIR_Coverage, 2520, |
| 20613 | GIR_EraseRootFromParent_Done, |
| 20614 | // Label 1168: @69425 |
| 20615 | GIM_Try, /*On fail goto*//*Label 1169*/ GIMT_Encode4(69486), // Rule ID 2521 // |
| 20616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 20617 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20618 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20620 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20621 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 20623 | // (ld:{ *:[f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 20625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 20627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20630 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20631 | GIR_RootConstrainSelectedInstOperands, |
| 20632 | // GIR_Coverage, 2521, |
| 20633 | GIR_EraseRootFromParent_Done, |
| 20634 | // Label 1169: @69486 |
| 20635 | GIM_Try, /*On fail goto*//*Label 1170*/ GIMT_Encode4(69540), // Rule ID 2464 // |
| 20636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 20637 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20640 | // MIs[0] sbase |
| 20641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20642 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20643 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20644 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20645 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20648 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20651 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20652 | GIR_RootConstrainSelectedInstOperands, |
| 20653 | // GIR_Coverage, 2464, |
| 20654 | GIR_EraseRootFromParent_Done, |
| 20655 | // Label 1170: @69540 |
| 20656 | GIM_Try, /*On fail goto*//*Label 1171*/ GIMT_Encode4(69594), // Rule ID 2517 // |
| 20657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 20658 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20659 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20661 | // MIs[0] sbase |
| 20662 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20664 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20665 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 20666 | // (ld:{ *:[f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20669 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20672 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20673 | GIR_RootConstrainSelectedInstOperands, |
| 20674 | // GIR_Coverage, 2517, |
| 20675 | GIR_EraseRootFromParent_Done, |
| 20676 | // Label 1171: @69594 |
| 20677 | GIM_Try, /*On fail goto*//*Label 1172*/ GIMT_Encode4(69651), // Rule ID 2473 // |
| 20678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20679 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20680 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20683 | // MIs[0] sbase |
| 20684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20685 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20686 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi8), |
| 20687 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_smrd_extloadi8>> => (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM), |
| 20689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20690 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20693 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20694 | GIR_RootConstrainSelectedInstOperands, |
| 20695 | // GIR_Coverage, 2473, |
| 20696 | GIR_EraseRootFromParent_Done, |
| 20697 | // Label 1172: @69651 |
| 20698 | GIM_Try, /*On fail goto*//*Label 1173*/ GIMT_Encode4(69708), // Rule ID 2488 // |
| 20699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 20700 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20701 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20702 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20704 | // MIs[0] sbase |
| 20705 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20706 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20707 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_extloadi16), |
| 20708 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_smrd_extloadi16>> => (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM), |
| 20710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20711 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20714 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20715 | GIR_RootConstrainSelectedInstOperands, |
| 20716 | // GIR_Coverage, 2488, |
| 20717 | GIR_EraseRootFromParent_Done, |
| 20718 | // Label 1173: @69708 |
| 20719 | GIM_Try, /*On fail goto*//*Label 1174*/ GIMT_Encode4(69755), // Rule ID 2511 // |
| 20720 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20723 | // MIs[0] sbase |
| 20724 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20725 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20726 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20727 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20730 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20734 | GIR_RootConstrainSelectedInstOperands, |
| 20735 | // GIR_Coverage, 2511, |
| 20736 | GIR_EraseRootFromParent_Done, |
| 20737 | // Label 1174: @69755 |
| 20738 | GIM_Try, /*On fail goto*//*Label 1175*/ GIMT_Encode4(69802), // Rule ID 2523 // |
| 20739 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20740 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 20742 | // MIs[0] sbase |
| 20743 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 20744 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 20745 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 20746 | // (ld:{ *:[f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 20747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 20748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 20749 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 20750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20753 | GIR_RootConstrainSelectedInstOperands, |
| 20754 | // GIR_Coverage, 2523, |
| 20755 | GIR_EraseRootFromParent_Done, |
| 20756 | // Label 1175: @69802 |
| 20757 | GIM_Try, /*On fail goto*//*Label 1176*/ GIMT_Encode4(69876), // Rule ID 6134 // |
| 20758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 20759 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20760 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20761 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20762 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20764 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20766 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 20768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20774 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20775 | GIR_RootConstrainSelectedInstOperands, |
| 20776 | // GIR_Coverage, 6134, |
| 20777 | GIR_EraseRootFromParent_Done, |
| 20778 | // Label 1176: @69876 |
| 20779 | GIM_Try, /*On fail goto*//*Label 1177*/ GIMT_Encode4(69950), // Rule ID 6136 // |
| 20780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 20781 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20782 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20783 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20784 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20788 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 20790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20796 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20797 | GIR_RootConstrainSelectedInstOperands, |
| 20798 | // GIR_Coverage, 6136, |
| 20799 | GIR_EraseRootFromParent_Done, |
| 20800 | // Label 1177: @69950 |
| 20801 | GIM_Try, /*On fail goto*//*Label 1178*/ GIMT_Encode4(70024), // Rule ID 6158 // |
| 20802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 20803 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20804 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20805 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20806 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20810 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 20812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20819 | GIR_RootConstrainSelectedInstOperands, |
| 20820 | // GIR_Coverage, 6158, |
| 20821 | GIR_EraseRootFromParent_Done, |
| 20822 | // Label 1178: @70024 |
| 20823 | GIM_Try, /*On fail goto*//*Label 1179*/ GIMT_Encode4(70098), // Rule ID 6160 // |
| 20824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 20825 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20826 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20827 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20832 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 20834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20841 | GIR_RootConstrainSelectedInstOperands, |
| 20842 | // GIR_Coverage, 6160, |
| 20843 | GIR_EraseRootFromParent_Done, |
| 20844 | // Label 1179: @70098 |
| 20845 | GIM_Try, /*On fail goto*//*Label 1180*/ GIMT_Encode4(70161), // Rule ID 6170 // |
| 20846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 20847 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20848 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20852 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 20854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20860 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20861 | GIR_RootConstrainSelectedInstOperands, |
| 20862 | // GIR_Coverage, 6170, |
| 20863 | GIR_EraseRootFromParent_Done, |
| 20864 | // Label 1180: @70161 |
| 20865 | GIM_Try, /*On fail goto*//*Label 1181*/ GIMT_Encode4(70224), // Rule ID 6172 // |
| 20866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 20867 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20868 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20871 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20872 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 20874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20880 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20881 | GIR_RootConstrainSelectedInstOperands, |
| 20882 | // GIR_Coverage, 6172, |
| 20883 | GIR_EraseRootFromParent_Done, |
| 20884 | // Label 1181: @70224 |
| 20885 | GIM_Try, /*On fail goto*//*Label 1182*/ GIMT_Encode4(70287), // Rule ID 6174 // |
| 20886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 20887 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20888 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20892 | // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 20894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20900 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20901 | GIR_RootConstrainSelectedInstOperands, |
| 20902 | // GIR_Coverage, 6174, |
| 20903 | GIR_EraseRootFromParent_Done, |
| 20904 | // Label 1182: @70287 |
| 20905 | GIM_Try, /*On fail goto*//*Label 1183*/ GIMT_Encode4(70350), // Rule ID 6176 // |
| 20906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 20907 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20908 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 20912 | // (ld:{ *:[f32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 20913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 20914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 20915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 20916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 20917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20921 | GIR_RootConstrainSelectedInstOperands, |
| 20922 | // GIR_Coverage, 6176, |
| 20923 | GIR_EraseRootFromParent_Done, |
| 20924 | // Label 1183: @70350 |
| 20925 | GIM_Try, /*On fail goto*//*Label 1184*/ GIMT_Encode4(70421), // Rule ID 3203 // |
| 20926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 20927 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20928 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 20929 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20930 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 20934 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS), |
| 20936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 20939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20942 | GIR_RootConstrainSelectedInstOperands, |
| 20943 | // GIR_Coverage, 3203, |
| 20944 | GIR_EraseRootFromParent_Done, |
| 20945 | // Label 1184: @70421 |
| 20946 | GIM_Try, /*On fail goto*//*Label 1185*/ GIMT_Encode4(70492), // Rule ID 3867 // |
| 20947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 20948 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 20949 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 20950 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20951 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20953 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20954 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 20955 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS), |
| 20957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 20960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20963 | GIR_RootConstrainSelectedInstOperands, |
| 20964 | // GIR_Coverage, 3867, |
| 20965 | GIR_EraseRootFromParent_Done, |
| 20966 | // Label 1185: @70492 |
| 20967 | GIM_Try, /*On fail goto*//*Label 1186*/ GIMT_Encode4(70552), // Rule ID 3879 // |
| 20968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 20969 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20970 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20972 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 20974 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 20976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 20979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 20981 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 20982 | GIR_RootConstrainSelectedInstOperands, |
| 20983 | // GIR_Coverage, 3879, |
| 20984 | GIR_EraseRootFromParent_Done, |
| 20985 | // Label 1186: @70552 |
| 20986 | GIM_Try, /*On fail goto*//*Label 1187*/ GIMT_Encode4(70612), // Rule ID 3882 // |
| 20987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 20988 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 20989 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 20990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 20991 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 20992 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 20993 | // (ld:{ *:[f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 20994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 20995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 20996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 20997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 20998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 20999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21000 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21001 | GIR_RootConstrainSelectedInstOperands, |
| 21002 | // GIR_Coverage, 3882, |
| 21003 | GIR_EraseRootFromParent_Done, |
| 21004 | // Label 1187: @70612 |
| 21005 | GIM_Try, /*On fail goto*//*Label 1188*/ GIMT_Encode4(70678), // Rule ID 3202 // |
| 21006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21007 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21008 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21009 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21010 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21012 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21013 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 21014 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 21015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR), |
| 21016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 21018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21020 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21021 | GIR_RootConstrainSelectedInstOperands, |
| 21022 | // GIR_Coverage, 3202, |
| 21023 | GIR_EraseRootFromParent_Done, |
| 21024 | // Label 1188: @70678 |
| 21025 | GIM_Try, /*On fail goto*//*Label 1189*/ GIMT_Encode4(70744), // Rule ID 3866 // |
| 21026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21027 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21028 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21029 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21030 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 21034 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 21035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR), |
| 21036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 21038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21041 | GIR_RootConstrainSelectedInstOperands, |
| 21042 | // GIR_Coverage, 3866, |
| 21043 | GIR_EraseRootFromParent_Done, |
| 21044 | // Label 1189: @70744 |
| 21045 | GIM_Try, /*On fail goto*//*Label 1190*/ GIMT_Encode4(70799), // Rule ID 3878 // |
| 21046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21047 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21048 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 21052 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 21053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 21054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 21056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21059 | GIR_RootConstrainSelectedInstOperands, |
| 21060 | // GIR_Coverage, 3878, |
| 21061 | GIR_EraseRootFromParent_Done, |
| 21062 | // Label 1190: @70799 |
| 21063 | GIM_Try, /*On fail goto*//*Label 1191*/ GIMT_Encode4(70854), // Rule ID 3881 // |
| 21064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21065 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 21070 | // (ld:{ *:[f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 21071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 21072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 21074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21077 | GIR_RootConstrainSelectedInstOperands, |
| 21078 | // GIR_Coverage, 3881, |
| 21079 | GIR_EraseRootFromParent_Done, |
| 21080 | // Label 1191: @70854 |
| 21081 | GIM_Try, /*On fail goto*//*Label 1192*/ GIMT_Encode4(70920), // Rule ID 3201 // |
| 21082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21083 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21084 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21085 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 21090 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 21091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE), |
| 21092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 21094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21097 | GIR_RootConstrainSelectedInstOperands, |
| 21098 | // GIR_Coverage, 3201, |
| 21099 | GIR_EraseRootFromParent_Done, |
| 21100 | // Label 1192: @70920 |
| 21101 | GIM_Try, /*On fail goto*//*Label 1193*/ GIMT_Encode4(70986), // Rule ID 3865 // |
| 21102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21103 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21104 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 21110 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 21111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT), |
| 21112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 21114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21117 | GIR_RootConstrainSelectedInstOperands, |
| 21118 | // GIR_Coverage, 3865, |
| 21119 | GIR_EraseRootFromParent_Done, |
| 21120 | // Label 1193: @70986 |
| 21121 | GIM_Try, /*On fail goto*//*Label 1194*/ GIMT_Encode4(71041), // Rule ID 3877 // |
| 21122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21123 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 21128 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 21129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 21130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 21132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21134 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21135 | GIR_RootConstrainSelectedInstOperands, |
| 21136 | // GIR_Coverage, 3877, |
| 21137 | GIR_EraseRootFromParent_Done, |
| 21138 | // Label 1194: @71041 |
| 21139 | GIM_Try, /*On fail goto*//*Label 1195*/ GIMT_Encode4(71096), // Rule ID 3880 // |
| 21140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 21141 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21142 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 21146 | // (ld:{ *:[f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 21147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 21148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 21150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21153 | GIR_RootConstrainSelectedInstOperands, |
| 21154 | // GIR_Coverage, 3880, |
| 21155 | GIR_EraseRootFromParent_Done, |
| 21156 | // Label 1195: @71096 |
| 21157 | GIM_Try, /*On fail goto*//*Label 1196*/ GIMT_Encode4(71173), // Rule ID 4088 // |
| 21158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21159 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21160 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21161 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21165 | // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 21167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21174 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21175 | GIR_RootConstrainSelectedInstOperands, |
| 21176 | // GIR_Coverage, 4088, |
| 21177 | GIR_EraseRootFromParent_Done, |
| 21178 | // Label 1196: @71173 |
| 21179 | GIM_Try, /*On fail goto*//*Label 1197*/ GIMT_Encode4(71247), // Rule ID 4092 // |
| 21180 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21181 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21182 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21184 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21185 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21186 | // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64), |
| 21188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21196 | GIR_RootConstrainSelectedInstOperands, |
| 21197 | // GIR_Coverage, 4092, |
| 21198 | GIR_EraseRootFromParent_Done, |
| 21199 | // Label 1197: @71247 |
| 21200 | GIM_Try, /*On fail goto*//*Label 1198*/ GIMT_Encode4(71324), // Rule ID 4094 // |
| 21201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21202 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21203 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21204 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21206 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21208 | // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 21210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21217 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21218 | GIR_RootConstrainSelectedInstOperands, |
| 21219 | // GIR_Coverage, 4094, |
| 21220 | GIR_EraseRootFromParent_Done, |
| 21221 | // Label 1198: @71324 |
| 21222 | GIM_Try, /*On fail goto*//*Label 1199*/ GIMT_Encode4(71398), // Rule ID 4096 // |
| 21223 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21224 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21225 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21229 | // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64), |
| 21231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21239 | GIR_RootConstrainSelectedInstOperands, |
| 21240 | // GIR_Coverage, 4096, |
| 21241 | GIR_EraseRootFromParent_Done, |
| 21242 | // Label 1199: @71398 |
| 21243 | GIM_Try, /*On fail goto*//*Label 1200*/ GIMT_Encode4(71475), // Rule ID 6103 // |
| 21244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 21245 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 21246 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21247 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21249 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21251 | // (atomic_load:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 21252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 21253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21261 | GIR_RootConstrainSelectedInstOperands, |
| 21262 | // GIR_Coverage, 6103, |
| 21263 | GIR_EraseRootFromParent_Done, |
| 21264 | // Label 1200: @71475 |
| 21265 | GIM_Try, /*On fail goto*//*Label 1201*/ GIMT_Encode4(71556), // Rule ID 4106 // |
| 21266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21267 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21268 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21269 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21270 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21272 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21274 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 21276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21283 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21284 | GIR_RootConstrainSelectedInstOperands, |
| 21285 | // GIR_Coverage, 4106, |
| 21286 | GIR_EraseRootFromParent_Done, |
| 21287 | // Label 1201: @71556 |
| 21288 | GIM_Try, /*On fail goto*//*Label 1202*/ GIMT_Encode4(71634), // Rule ID 4108 // |
| 21289 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21290 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21291 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21292 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21294 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21296 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64), |
| 21298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21305 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21306 | GIR_RootConstrainSelectedInstOperands, |
| 21307 | // GIR_Coverage, 4108, |
| 21308 | GIR_EraseRootFromParent_Done, |
| 21309 | // Label 1202: @71634 |
| 21310 | GIM_Try, /*On fail goto*//*Label 1203*/ GIMT_Encode4(71715), // Rule ID 4118 // |
| 21311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21312 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21313 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21314 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21315 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21319 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 21321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21328 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21329 | GIR_RootConstrainSelectedInstOperands, |
| 21330 | // GIR_Coverage, 4118, |
| 21331 | GIR_EraseRootFromParent_Done, |
| 21332 | // Label 1203: @71715 |
| 21333 | GIM_Try, /*On fail goto*//*Label 1204*/ GIMT_Encode4(71793), // Rule ID 4120 // |
| 21334 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21335 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21336 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21337 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21339 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21341 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64), |
| 21343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21351 | GIR_RootConstrainSelectedInstOperands, |
| 21352 | // GIR_Coverage, 4120, |
| 21353 | GIR_EraseRootFromParent_Done, |
| 21354 | // Label 1204: @71793 |
| 21355 | GIM_Try, /*On fail goto*//*Label 1205*/ GIMT_Encode4(71873), // Rule ID 6106 // |
| 21356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 21357 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21358 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21359 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21364 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_constant>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 21365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 21366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21374 | GIR_RootConstrainSelectedInstOperands, |
| 21375 | // GIR_Coverage, 6106, |
| 21376 | GIR_EraseRootFromParent_Done, |
| 21377 | // Label 1205: @71873 |
| 21378 | GIM_Try, /*On fail goto*//*Label 1206*/ GIMT_Encode4(71953), // Rule ID 6109 // |
| 21379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 21380 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21381 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21382 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21387 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_constant>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 21388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 21389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21397 | GIR_RootConstrainSelectedInstOperands, |
| 21398 | // GIR_Coverage, 6109, |
| 21399 | GIR_EraseRootFromParent_Done, |
| 21400 | // Label 1206: @71953 |
| 21401 | GIM_Try, /*On fail goto*//*Label 1207*/ GIMT_Encode4(72032), // Rule ID 6133 // |
| 21402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 21403 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21404 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21405 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21406 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21408 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21410 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), |
| 21412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21420 | GIR_RootConstrainSelectedInstOperands, |
| 21421 | // GIR_Coverage, 6133, |
| 21422 | GIR_EraseRootFromParent_Done, |
| 21423 | // Label 1207: @72032 |
| 21424 | GIM_Try, /*On fail goto*//*Label 1208*/ GIMT_Encode4(72111), // Rule ID 6135 // |
| 21425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 21426 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21427 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21428 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21429 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21433 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN), |
| 21435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21443 | GIR_RootConstrainSelectedInstOperands, |
| 21444 | // GIR_Coverage, 6135, |
| 21445 | GIR_EraseRootFromParent_Done, |
| 21446 | // Label 1208: @72111 |
| 21447 | GIM_Try, /*On fail goto*//*Label 1209*/ GIMT_Encode4(72190), // Rule ID 6157 // |
| 21448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 21449 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21450 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21451 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21452 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21454 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21456 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), |
| 21458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21466 | GIR_RootConstrainSelectedInstOperands, |
| 21467 | // GIR_Coverage, 6157, |
| 21468 | GIR_EraseRootFromParent_Done, |
| 21469 | // Label 1209: @72190 |
| 21470 | GIM_Try, /*On fail goto*//*Label 1210*/ GIMT_Encode4(72269), // Rule ID 6159 // |
| 21471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 21472 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21473 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21474 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21475 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21477 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21479 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN), |
| 21481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21489 | GIR_RootConstrainSelectedInstOperands, |
| 21490 | // GIR_Coverage, 6159, |
| 21491 | GIR_EraseRootFromParent_Done, |
| 21492 | // Label 1210: @72269 |
| 21493 | GIM_Try, /*On fail goto*//*Label 1211*/ GIMT_Encode4(72339), // Rule ID 4130 // |
| 21494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21495 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21496 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21498 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21500 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 21502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21509 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21510 | GIR_RootConstrainSelectedInstOperands, |
| 21511 | // GIR_Coverage, 4130, |
| 21512 | GIR_EraseRootFromParent_Done, |
| 21513 | // Label 1211: @72339 |
| 21514 | GIM_Try, /*On fail goto*//*Label 1212*/ GIMT_Encode4(72406), // Rule ID 4132 // |
| 21515 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21516 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21518 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21519 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21520 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 21522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21530 | GIR_RootConstrainSelectedInstOperands, |
| 21531 | // GIR_Coverage, 4132, |
| 21532 | GIR_EraseRootFromParent_Done, |
| 21533 | // Label 1212: @72406 |
| 21534 | GIM_Try, /*On fail goto*//*Label 1213*/ GIMT_Encode4(72476), // Rule ID 4134 // |
| 21535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21536 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21539 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21541 | // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 21543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21550 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21551 | GIR_RootConstrainSelectedInstOperands, |
| 21552 | // GIR_Coverage, 4134, |
| 21553 | GIR_EraseRootFromParent_Done, |
| 21554 | // Label 1213: @72476 |
| 21555 | GIM_Try, /*On fail goto*//*Label 1214*/ GIMT_Encode4(72543), // Rule ID 4136 // |
| 21556 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 21561 | // (ld:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 21563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21571 | GIR_RootConstrainSelectedInstOperands, |
| 21572 | // GIR_Coverage, 4136, |
| 21573 | GIR_EraseRootFromParent_Done, |
| 21574 | // Label 1214: @72543 |
| 21575 | GIM_Try, /*On fail goto*//*Label 1215*/ GIMT_Encode4(72611), // Rule ID 6169 // |
| 21576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 21577 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21582 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 21584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21592 | GIR_RootConstrainSelectedInstOperands, |
| 21593 | // GIR_Coverage, 6169, |
| 21594 | GIR_EraseRootFromParent_Done, |
| 21595 | // Label 1215: @72611 |
| 21596 | GIM_Try, /*On fail goto*//*Label 1216*/ GIMT_Encode4(72679), // Rule ID 6171 // |
| 21597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 21598 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21599 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21601 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21603 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 21605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21612 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21613 | GIR_RootConstrainSelectedInstOperands, |
| 21614 | // GIR_Coverage, 6171, |
| 21615 | GIR_EraseRootFromParent_Done, |
| 21616 | // Label 1216: @72679 |
| 21617 | GIM_Try, /*On fail goto*//*Label 1217*/ GIMT_Encode4(72747), // Rule ID 6173 // |
| 21618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 21619 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21620 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21623 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21624 | // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 21626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21633 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21634 | GIR_RootConstrainSelectedInstOperands, |
| 21635 | // GIR_Coverage, 6173, |
| 21636 | GIR_EraseRootFromParent_Done, |
| 21637 | // Label 1217: @72747 |
| 21638 | GIM_Try, /*On fail goto*//*Label 1218*/ GIMT_Encode4(72815), // Rule ID 6175 // |
| 21639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 21640 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 21641 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21643 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21644 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 21645 | // (ld:{ *:[f32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 21646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 21647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 21649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 21651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 21652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21654 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21655 | GIR_RootConstrainSelectedInstOperands, |
| 21656 | // GIR_Coverage, 6175, |
| 21657 | GIR_EraseRootFromParent_Done, |
| 21658 | // Label 1218: @72815 |
| 21659 | GIM_Try, /*On fail goto*//*Label 1219*/ GIMT_Encode4(72887), // Rule ID 4087 // |
| 21660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21661 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21662 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21663 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21665 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21667 | // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 21669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21675 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21676 | GIR_RootConstrainSelectedInstOperands, |
| 21677 | // GIR_Coverage, 4087, |
| 21678 | GIR_EraseRootFromParent_Done, |
| 21679 | // Label 1219: @72887 |
| 21680 | GIM_Try, /*On fail goto*//*Label 1220*/ GIMT_Encode4(72956), // Rule ID 4091 // |
| 21681 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21682 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21683 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21687 | // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 21689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21696 | GIR_RootConstrainSelectedInstOperands, |
| 21697 | // GIR_Coverage, 4091, |
| 21698 | GIR_EraseRootFromParent_Done, |
| 21699 | // Label 1220: @72956 |
| 21700 | GIM_Try, /*On fail goto*//*Label 1221*/ GIMT_Encode4(73028), // Rule ID 4093 // |
| 21701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21702 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21703 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21704 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21706 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21707 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21708 | // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 21710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21717 | GIR_RootConstrainSelectedInstOperands, |
| 21718 | // GIR_Coverage, 4093, |
| 21719 | GIR_EraseRootFromParent_Done, |
| 21720 | // Label 1221: @73028 |
| 21721 | GIM_Try, /*On fail goto*//*Label 1222*/ GIMT_Encode4(73097), // Rule ID 4095 // |
| 21722 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21723 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21724 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21726 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21727 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21728 | // (atomic_load:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 21730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21737 | GIR_RootConstrainSelectedInstOperands, |
| 21738 | // GIR_Coverage, 4095, |
| 21739 | GIR_EraseRootFromParent_Done, |
| 21740 | // Label 1222: @73097 |
| 21741 | GIM_Try, /*On fail goto*//*Label 1223*/ GIMT_Encode4(73173), // Rule ID 4105 // |
| 21742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21743 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21744 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21745 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21746 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21750 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 21752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21759 | GIR_RootConstrainSelectedInstOperands, |
| 21760 | // GIR_Coverage, 4105, |
| 21761 | GIR_EraseRootFromParent_Done, |
| 21762 | // Label 1223: @73173 |
| 21763 | GIM_Try, /*On fail goto*//*Label 1224*/ GIMT_Encode4(73246), // Rule ID 4107 // |
| 21764 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21765 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21766 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21767 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21770 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21771 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 21773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21780 | GIR_RootConstrainSelectedInstOperands, |
| 21781 | // GIR_Coverage, 4107, |
| 21782 | GIR_EraseRootFromParent_Done, |
| 21783 | // Label 1224: @73246 |
| 21784 | GIM_Try, /*On fail goto*//*Label 1225*/ GIMT_Encode4(73322), // Rule ID 4117 // |
| 21785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21786 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21787 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21788 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21793 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 21795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21802 | GIR_RootConstrainSelectedInstOperands, |
| 21803 | // GIR_Coverage, 4117, |
| 21804 | GIR_EraseRootFromParent_Done, |
| 21805 | // Label 1225: @73322 |
| 21806 | GIM_Try, /*On fail goto*//*Label 1226*/ GIMT_Encode4(73395), // Rule ID 4119 // |
| 21807 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 21808 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21809 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21812 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21814 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 21816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21823 | GIR_RootConstrainSelectedInstOperands, |
| 21824 | // GIR_Coverage, 4119, |
| 21825 | GIR_EraseRootFromParent_Done, |
| 21826 | // Label 1226: @73395 |
| 21827 | GIM_Try, /*On fail goto*//*Label 1227*/ GIMT_Encode4(73460), // Rule ID 4129 // |
| 21828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21829 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21830 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21832 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21833 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21834 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 21836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21842 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21843 | GIR_RootConstrainSelectedInstOperands, |
| 21844 | // GIR_Coverage, 4129, |
| 21845 | GIR_EraseRootFromParent_Done, |
| 21846 | // Label 1227: @73460 |
| 21847 | GIM_Try, /*On fail goto*//*Label 1228*/ GIMT_Encode4(73522), // Rule ID 4131 // |
| 21848 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21849 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21851 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21852 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21853 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 21855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21861 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21862 | GIR_RootConstrainSelectedInstOperands, |
| 21863 | // GIR_Coverage, 4131, |
| 21864 | GIR_EraseRootFromParent_Done, |
| 21865 | // Label 1228: @73522 |
| 21866 | GIM_Try, /*On fail goto*//*Label 1229*/ GIMT_Encode4(73587), // Rule ID 4133 // |
| 21867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 21868 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21869 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21870 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21873 | // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 21875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21882 | GIR_RootConstrainSelectedInstOperands, |
| 21883 | // GIR_Coverage, 4133, |
| 21884 | GIR_EraseRootFromParent_Done, |
| 21885 | // Label 1229: @73587 |
| 21886 | GIM_Try, /*On fail goto*//*Label 1230*/ GIMT_Encode4(73649), // Rule ID 4135 // |
| 21887 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 21888 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 21889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 21892 | // (ld:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 21893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 21894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 21895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 21896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 21897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 21898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21900 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21901 | GIR_RootConstrainSelectedInstOperands, |
| 21902 | // GIR_Coverage, 4135, |
| 21903 | GIR_EraseRootFromParent_Done, |
| 21904 | // Label 1230: @73649 |
| 21905 | GIM_Try, /*On fail goto*//*Label 1231*/ GIMT_Encode4(73711), // Rule ID 7477 // |
| 21906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 21907 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21908 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 21909 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21912 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 21913 | // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8_glue>><<P:Predicate_atomic_load_8_local_m0>> => (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 21914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 21915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 21917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21919 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21920 | GIR_RootConstrainSelectedInstOperands, |
| 21921 | // GIR_Coverage, 7477, |
| 21922 | GIR_EraseRootFromParent_Done, |
| 21923 | // Label 1231: @73711 |
| 21924 | GIM_Try, /*On fail goto*//*Label 1232*/ GIMT_Encode4(73773), // Rule ID 7478 // |
| 21925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 21926 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 21927 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 21928 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 21932 | // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_local>> => (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 21933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 21934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 21936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21939 | GIR_RootConstrainSelectedInstOperands, |
| 21940 | // GIR_Coverage, 7478, |
| 21941 | GIR_EraseRootFromParent_Done, |
| 21942 | // Label 1232: @73773 |
| 21943 | GIM_Try, /*On fail goto*//*Label 1233*/ GIMT_Encode4(73835), // Rule ID 7481 // |
| 21944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 21945 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21946 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 21947 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 21951 | // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16_glue>><<P:Predicate_atomic_load_16_local_m0>> => (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 21952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16), |
| 21953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 21955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21957 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21958 | GIR_RootConstrainSelectedInstOperands, |
| 21959 | // GIR_Coverage, 7481, |
| 21960 | GIR_EraseRootFromParent_Done, |
| 21961 | // Label 1233: @73835 |
| 21962 | GIM_Try, /*On fail goto*//*Label 1234*/ GIMT_Encode4(73897), // Rule ID 7482 // |
| 21963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 21964 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 21965 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 21966 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 21970 | // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_local>> => (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 21971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9), |
| 21972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 21974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21977 | GIR_RootConstrainSelectedInstOperands, |
| 21978 | // GIR_Coverage, 7482, |
| 21979 | GIR_EraseRootFromParent_Done, |
| 21980 | // Label 1234: @73897 |
| 21981 | GIM_Try, /*On fail goto*//*Label 1235*/ GIMT_Encode4(73959), // Rule ID 7483 // |
| 21982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 21983 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 21984 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 21985 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 21986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 21987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 21988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 21989 | // (AMDGPUatomic_ld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32_glue>><<P:Predicate_atomic_load_32_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 21990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 21991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 21992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 21993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 21994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 21995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 21996 | GIR_RootConstrainSelectedInstOperands, |
| 21997 | // GIR_Coverage, 7483, |
| 21998 | GIR_EraseRootFromParent_Done, |
| 21999 | // Label 1235: @73959 |
| 22000 | GIM_Try, /*On fail goto*//*Label 1236*/ GIMT_Encode4(74021), // Rule ID 7484 // |
| 22001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 22002 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 22003 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22004 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22006 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22008 | // (atomic_load:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 22010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22014 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22015 | GIR_RootConstrainSelectedInstOperands, |
| 22016 | // GIR_Coverage, 7484, |
| 22017 | GIR_EraseRootFromParent_Done, |
| 22018 | // Label 1236: @74021 |
| 22019 | GIM_Try, /*On fail goto*//*Label 1237*/ GIMT_Encode4(74087), // Rule ID 7439 // |
| 22020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 22021 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22022 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22023 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22028 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi8_glue>><<P:Predicate_extloadi8_local_m0>> => (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 22030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22034 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22035 | GIR_RootConstrainSelectedInstOperands, |
| 22036 | // GIR_Coverage, 7439, |
| 22037 | GIR_EraseRootFromParent_Done, |
| 22038 | // Label 1237: @74087 |
| 22039 | GIM_Try, /*On fail goto*//*Label 1238*/ GIMT_Encode4(74153), // Rule ID 7440 // |
| 22040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 22041 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22042 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22043 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22048 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_local>> => (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 22050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22054 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22055 | GIR_RootConstrainSelectedInstOperands, |
| 22056 | // GIR_Coverage, 7440, |
| 22057 | GIR_EraseRootFromParent_Done, |
| 22058 | // Label 1238: @74153 |
| 22059 | GIM_Try, /*On fail goto*//*Label 1239*/ GIMT_Encode4(74219), // Rule ID 7451 // |
| 22060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 22061 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22062 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22063 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22068 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_extload_glue>><<P:Predicate_extloadi16_glue>><<P:Predicate_extloadi16_local_m0>> => (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16), |
| 22070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22074 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22075 | GIR_RootConstrainSelectedInstOperands, |
| 22076 | // GIR_Coverage, 7451, |
| 22077 | GIR_EraseRootFromParent_Done, |
| 22078 | // Label 1239: @74219 |
| 22079 | GIM_Try, /*On fail goto*//*Label 1240*/ GIMT_Encode4(74285), // Rule ID 7452 // |
| 22080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 22081 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22082 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22083 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22088 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_local>> => (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9), |
| 22090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22094 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22095 | GIR_RootConstrainSelectedInstOperands, |
| 22096 | // GIR_Coverage, 7452, |
| 22097 | GIR_EraseRootFromParent_Done, |
| 22098 | // Label 1240: @74285 |
| 22099 | GIM_Try, /*On fail goto*//*Label 1241*/ GIMT_Encode4(74344), // Rule ID 7457 // |
| 22100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 22101 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22102 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22103 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22107 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 22109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22113 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22114 | GIR_RootConstrainSelectedInstOperands, |
| 22115 | // GIR_Coverage, 7457, |
| 22116 | GIR_EraseRootFromParent_Done, |
| 22117 | // Label 1241: @74344 |
| 22118 | GIM_Try, /*On fail goto*//*Label 1242*/ GIMT_Encode4(74403), // Rule ID 7459 // |
| 22119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 22120 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22121 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22126 | // (AMDGPUld_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 22128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22132 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22133 | GIR_RootConstrainSelectedInstOperands, |
| 22134 | // GIR_Coverage, 7459, |
| 22135 | GIR_EraseRootFromParent_Done, |
| 22136 | // Label 1242: @74403 |
| 22137 | GIM_Try, /*On fail goto*//*Label 1243*/ GIMT_Encode4(74458), // Rule ID 7458 // |
| 22138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 22139 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22144 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 22146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22151 | GIR_RootConstrainSelectedInstOperands, |
| 22152 | // GIR_Coverage, 7458, |
| 22153 | GIR_EraseRootFromParent_Done, |
| 22154 | // Label 1243: @74458 |
| 22155 | GIM_Try, /*On fail goto*//*Label 1244*/ GIMT_Encode4(74513), // Rule ID 7460 // |
| 22156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 22157 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 22158 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22160 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 22162 | // (ld:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 22163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 22164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 22166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22169 | GIR_RootConstrainSelectedInstOperands, |
| 22170 | // GIR_Coverage, 7460, |
| 22171 | GIR_EraseRootFromParent_Done, |
| 22172 | // Label 1244: @74513 |
| 22173 | GIM_Try, /*On fail goto*//*Label 1245*/ GIMT_Encode4(74582), // Rule ID 3192 // |
| 22174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22175 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22176 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22177 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22181 | // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 22183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22188 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22189 | GIR_RootConstrainSelectedInstOperands, |
| 22190 | // GIR_Coverage, 3192, |
| 22191 | GIR_EraseRootFromParent_Done, |
| 22192 | // Label 1245: @74582 |
| 22193 | GIM_Try, /*On fail goto*//*Label 1246*/ GIMT_Encode4(74651), // Rule ID 3427 // |
| 22194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22195 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22196 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22197 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22201 | // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR), |
| 22203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22208 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22209 | GIR_RootConstrainSelectedInstOperands, |
| 22210 | // GIR_Coverage, 3427, |
| 22211 | GIR_EraseRootFromParent_Done, |
| 22212 | // Label 1246: @74651 |
| 22213 | GIM_Try, /*On fail goto*//*Label 1247*/ GIMT_Encode4(74720), // Rule ID 3555 // |
| 22214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22215 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 22216 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22217 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22221 | // (atomic_load:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 22223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22229 | GIR_RootConstrainSelectedInstOperands, |
| 22230 | // GIR_Coverage, 3555, |
| 22231 | GIR_EraseRootFromParent_Done, |
| 22232 | // Label 1247: @74720 |
| 22233 | GIM_Try, /*On fail goto*//*Label 1248*/ GIMT_Encode4(74793), // Rule ID 3431 // |
| 22234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22235 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22236 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22237 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22238 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22242 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 22244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22250 | GIR_RootConstrainSelectedInstOperands, |
| 22251 | // GIR_Coverage, 3431, |
| 22252 | GIR_EraseRootFromParent_Done, |
| 22253 | // Label 1248: @74793 |
| 22254 | GIM_Try, /*On fail goto*//*Label 1249*/ GIMT_Encode4(74866), // Rule ID 3443 // |
| 22255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22256 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22257 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22258 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22259 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22261 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22262 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22263 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR), |
| 22265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22270 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22271 | GIR_RootConstrainSelectedInstOperands, |
| 22272 | // GIR_Coverage, 3443, |
| 22273 | GIR_EraseRootFromParent_Done, |
| 22274 | // Label 1249: @74866 |
| 22275 | GIM_Try, /*On fail goto*//*Label 1250*/ GIMT_Encode4(74928), // Rule ID 3451 // |
| 22276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22277 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22278 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22280 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22281 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22282 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 22284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22290 | GIR_RootConstrainSelectedInstOperands, |
| 22291 | // GIR_Coverage, 3451, |
| 22292 | GIR_EraseRootFromParent_Done, |
| 22293 | // Label 1250: @74928 |
| 22294 | GIM_Try, /*On fail goto*//*Label 1251*/ GIMT_Encode4(74990), // Rule ID 3453 // |
| 22295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22296 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22297 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22299 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 22301 | // (ld:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 22303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 22305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 22306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22309 | GIR_RootConstrainSelectedInstOperands, |
| 22310 | // GIR_Coverage, 3453, |
| 22311 | GIR_EraseRootFromParent_Done, |
| 22312 | // Label 1251: @74990 |
| 22313 | GIM_Try, /*On fail goto*//*Label 1252*/ GIMT_Encode4(75054), // Rule ID 3191 // |
| 22314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22315 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22316 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22317 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22321 | // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 22323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22328 | GIR_RootConstrainSelectedInstOperands, |
| 22329 | // GIR_Coverage, 3191, |
| 22330 | GIR_EraseRootFromParent_Done, |
| 22331 | // Label 1252: @75054 |
| 22332 | GIM_Try, /*On fail goto*//*Label 1253*/ GIMT_Encode4(75118), // Rule ID 3426 // |
| 22333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22334 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22335 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22336 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22338 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22340 | // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_global>> => (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT), |
| 22342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22347 | GIR_RootConstrainSelectedInstOperands, |
| 22348 | // GIR_Coverage, 3426, |
| 22349 | GIR_EraseRootFromParent_Done, |
| 22350 | // Label 1253: @75118 |
| 22351 | GIM_Try, /*On fail goto*//*Label 1254*/ GIMT_Encode4(75182), // Rule ID 3554 // |
| 22352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22353 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 22354 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22355 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22357 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22358 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22359 | // (atomic_load:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 22361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22365 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22366 | GIR_RootConstrainSelectedInstOperands, |
| 22367 | // GIR_Coverage, 3554, |
| 22368 | GIR_EraseRootFromParent_Done, |
| 22369 | // Label 1254: @75182 |
| 22370 | GIM_Try, /*On fail goto*//*Label 1255*/ GIMT_Encode4(75250), // Rule ID 3430 // |
| 22371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22372 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22373 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22374 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22377 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22378 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22379 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 22381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22385 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22386 | GIR_RootConstrainSelectedInstOperands, |
| 22387 | // GIR_Coverage, 3430, |
| 22388 | GIR_EraseRootFromParent_Done, |
| 22389 | // Label 1255: @75250 |
| 22390 | GIM_Try, /*On fail goto*//*Label 1256*/ GIMT_Encode4(75318), // Rule ID 3442 // |
| 22391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22392 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22393 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22394 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22395 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22397 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22399 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_global>> => (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT), |
| 22401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22406 | GIR_RootConstrainSelectedInstOperands, |
| 22407 | // GIR_Coverage, 3442, |
| 22408 | GIR_EraseRootFromParent_Done, |
| 22409 | // Label 1256: @75318 |
| 22410 | GIM_Try, /*On fail goto*//*Label 1257*/ GIMT_Encode4(75375), // Rule ID 3450 // |
| 22411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22412 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22413 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22415 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22417 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 22419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22424 | GIR_RootConstrainSelectedInstOperands, |
| 22425 | // GIR_Coverage, 3450, |
| 22426 | GIR_EraseRootFromParent_Done, |
| 22427 | // Label 1257: @75375 |
| 22428 | GIM_Try, /*On fail goto*//*Label 1258*/ GIMT_Encode4(75432), // Rule ID 3452 // |
| 22429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 22430 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22431 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 22435 | // (ld:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 22437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22442 | GIR_RootConstrainSelectedInstOperands, |
| 22443 | // GIR_Coverage, 3452, |
| 22444 | GIR_EraseRootFromParent_Done, |
| 22445 | // Label 1258: @75432 |
| 22446 | GIM_Try, /*On fail goto*//*Label 1259*/ GIMT_Encode4(75497), // Rule ID 3210 // |
| 22447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22448 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22449 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22450 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22454 | // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_8>><<P:Predicate_atomic_load_8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 22456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22460 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22461 | GIR_RootConstrainSelectedInstOperands, |
| 22462 | // GIR_Coverage, 3210, |
| 22463 | GIR_EraseRootFromParent_Done, |
| 22464 | // Label 1259: @75497 |
| 22465 | GIM_Try, /*On fail goto*//*Label 1260*/ GIMT_Encode4(75562), // Rule ID 3212 // |
| 22466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22467 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22468 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22469 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22473 | // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_16>><<P:Predicate_atomic_load_16_flat>> => (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT), |
| 22475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22479 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22480 | GIR_RootConstrainSelectedInstOperands, |
| 22481 | // GIR_Coverage, 3212, |
| 22482 | GIR_EraseRootFromParent_Done, |
| 22483 | // Label 1260: @75562 |
| 22484 | GIM_Try, /*On fail goto*//*Label 1261*/ GIMT_Encode4(75627), // Rule ID 3225 // |
| 22485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22486 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 22487 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22488 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 22489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22492 | // (atomic_load:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_32>><<P:Predicate_atomic_load_32_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 22494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22499 | GIR_RootConstrainSelectedInstOperands, |
| 22500 | // GIR_Coverage, 3225, |
| 22501 | GIR_EraseRootFromParent_Done, |
| 22502 | // Label 1261: @75627 |
| 22503 | GIM_Try, /*On fail goto*//*Label 1262*/ GIMT_Encode4(75696), // Rule ID 3214 // |
| 22504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22505 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22506 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 22507 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22512 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi8>><<P:Predicate_extloadi8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 22514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22518 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22519 | GIR_RootConstrainSelectedInstOperands, |
| 22520 | // GIR_Coverage, 3214, |
| 22521 | GIR_EraseRootFromParent_Done, |
| 22522 | // Label 1262: @75696 |
| 22523 | GIM_Try, /*On fail goto*//*Label 1263*/ GIMT_Encode4(75765), // Rule ID 3220 // |
| 22524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22525 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22526 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 22527 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22532 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_extload>><<P:Predicate_extloadi16>><<P:Predicate_extloadi16_flat>> => (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT), |
| 22534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22538 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22539 | GIR_RootConstrainSelectedInstOperands, |
| 22540 | // GIR_Coverage, 3220, |
| 22541 | GIR_EraseRootFromParent_Done, |
| 22542 | // Label 1263: @75765 |
| 22543 | GIM_Try, /*On fail goto*//*Label 1264*/ GIMT_Encode4(75823), // Rule ID 3229 // |
| 22544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22545 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22546 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22548 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22550 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 22552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22557 | GIR_RootConstrainSelectedInstOperands, |
| 22558 | // GIR_Coverage, 3229, |
| 22559 | GIR_EraseRootFromParent_Done, |
| 22560 | // Label 1264: @75823 |
| 22561 | GIM_Try, /*On fail goto*//*Label 1265*/ GIMT_Encode4(75881), // Rule ID 3231 // |
| 22562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 22563 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 22564 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22565 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 22566 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 22568 | // (ld:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 22569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 22570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 22571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 22572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22574 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22575 | GIR_RootConstrainSelectedInstOperands, |
| 22576 | // GIR_Coverage, 3231, |
| 22577 | GIR_EraseRootFromParent_Done, |
| 22578 | // Label 1265: @75881 |
| 22579 | GIM_Reject, |
| 22580 | // Label 857: @75882 |
| 22581 | GIM_Try, /*On fail goto*//*Label 1266*/ GIMT_Encode4(75949), // Rule ID 2629 // |
| 22582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22583 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22584 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22587 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22588 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22590 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22598 | GIR_RootConstrainSelectedInstOperands, |
| 22599 | // GIR_Coverage, 2629, |
| 22600 | GIR_EraseRootFromParent_Done, |
| 22601 | // Label 1266: @75949 |
| 22602 | GIM_Try, /*On fail goto*//*Label 1267*/ GIMT_Encode4(76016), // Rule ID 2663 // |
| 22603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22604 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22605 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22607 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22608 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22609 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22611 | // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22618 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22619 | GIR_RootConstrainSelectedInstOperands, |
| 22620 | // GIR_Coverage, 2663, |
| 22621 | GIR_EraseRootFromParent_Done, |
| 22622 | // Label 1267: @76016 |
| 22623 | GIM_Try, /*On fail goto*//*Label 1268*/ GIMT_Encode4(76083), // Rule ID 7978 // |
| 22624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22625 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22626 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22628 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22629 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22630 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22632 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22640 | GIR_RootConstrainSelectedInstOperands, |
| 22641 | // GIR_Coverage, 7978, |
| 22642 | GIR_EraseRootFromParent_Done, |
| 22643 | // Label 1268: @76083 |
| 22644 | GIM_Try, /*On fail goto*//*Label 1269*/ GIMT_Encode4(76146), // Rule ID 2634 // |
| 22645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22646 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22647 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22649 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22650 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22652 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 22654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22659 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22660 | GIR_RootConstrainSelectedInstOperands, |
| 22661 | // GIR_Coverage, 2634, |
| 22662 | GIR_EraseRootFromParent_Done, |
| 22663 | // Label 1269: @76146 |
| 22664 | GIM_Try, /*On fail goto*//*Label 1270*/ GIMT_Encode4(76209), // Rule ID 2668 // |
| 22665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22666 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22667 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22669 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22670 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22671 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22672 | // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 22674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22679 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22680 | GIR_RootConstrainSelectedInstOperands, |
| 22681 | // GIR_Coverage, 2668, |
| 22682 | GIR_EraseRootFromParent_Done, |
| 22683 | // Label 1270: @76209 |
| 22684 | GIM_Try, /*On fail goto*//*Label 1271*/ GIMT_Encode4(76272), // Rule ID 7983 // |
| 22685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22686 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22687 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22689 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22690 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22692 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 22694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22699 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22700 | GIR_RootConstrainSelectedInstOperands, |
| 22701 | // GIR_Coverage, 7983, |
| 22702 | GIR_EraseRootFromParent_Done, |
| 22703 | // Label 1271: @76272 |
| 22704 | GIM_Try, /*On fail goto*//*Label 1272*/ GIMT_Encode4(76335), // Rule ID 2640 // |
| 22705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 22706 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22707 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22709 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22710 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22711 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22712 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22719 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22720 | GIR_RootConstrainSelectedInstOperands, |
| 22721 | // GIR_Coverage, 2640, |
| 22722 | GIR_EraseRootFromParent_Done, |
| 22723 | // Label 1272: @76335 |
| 22724 | GIM_Try, /*On fail goto*//*Label 1273*/ GIMT_Encode4(76398), // Rule ID 2674 // |
| 22725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 22726 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22727 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22729 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22730 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22732 | // (ld:{ *:[f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22740 | GIR_RootConstrainSelectedInstOperands, |
| 22741 | // GIR_Coverage, 2674, |
| 22742 | GIR_EraseRootFromParent_Done, |
| 22743 | // Label 1273: @76398 |
| 22744 | GIM_Try, /*On fail goto*//*Label 1274*/ GIMT_Encode4(76461), // Rule ID 7989 // |
| 22745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 22746 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22749 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22750 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 22752 | // (ld:{ *:[i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 22758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22760 | GIR_RootConstrainSelectedInstOperands, |
| 22761 | // GIR_Coverage, 7989, |
| 22762 | GIR_EraseRootFromParent_Done, |
| 22763 | // Label 1274: @76461 |
| 22764 | GIM_Try, /*On fail goto*//*Label 1275*/ GIMT_Encode4(76523), // Rule ID 2625 // |
| 22765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 22766 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22767 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22770 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22771 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 22773 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 22775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22780 | GIR_RootConstrainSelectedInstOperands, |
| 22781 | // GIR_Coverage, 2625, |
| 22782 | GIR_EraseRootFromParent_Done, |
| 22783 | // Label 1275: @76523 |
| 22784 | GIM_Try, /*On fail goto*//*Label 1276*/ GIMT_Encode4(76585), // Rule ID 2626 // |
| 22785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 22786 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22787 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22790 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22791 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 22793 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 22795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22800 | GIR_RootConstrainSelectedInstOperands, |
| 22801 | // GIR_Coverage, 2626, |
| 22802 | GIR_EraseRootFromParent_Done, |
| 22803 | // Label 1276: @76585 |
| 22804 | GIM_Try, /*On fail goto*//*Label 1277*/ GIMT_Encode4(76647), // Rule ID 2627 // |
| 22805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 22806 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22809 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22810 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22811 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22813 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 22814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 22815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22820 | GIR_RootConstrainSelectedInstOperands, |
| 22821 | // GIR_Coverage, 2627, |
| 22822 | GIR_EraseRootFromParent_Done, |
| 22823 | // Label 1277: @76647 |
| 22824 | GIM_Try, /*On fail goto*//*Label 1278*/ GIMT_Encode4(76712), // Rule ID 2628 // |
| 22825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22826 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22827 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22830 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22833 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 22834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22841 | GIR_RootConstrainSelectedInstOperands, |
| 22842 | // GIR_Coverage, 2628, |
| 22843 | GIR_EraseRootFromParent_Done, |
| 22844 | // Label 1278: @76712 |
| 22845 | GIM_Try, /*On fail goto*//*Label 1279*/ GIMT_Encode4(76774), // Rule ID 2659 // |
| 22846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 22847 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22848 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22851 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 22854 | // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 22856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22860 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22861 | GIR_RootConstrainSelectedInstOperands, |
| 22862 | // GIR_Coverage, 2659, |
| 22863 | GIR_EraseRootFromParent_Done, |
| 22864 | // Label 1279: @76774 |
| 22865 | GIM_Try, /*On fail goto*//*Label 1280*/ GIMT_Encode4(76836), // Rule ID 2660 // |
| 22866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 22867 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22868 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22871 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22872 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22873 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 22874 | // (ld:{ *:[f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 22876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22880 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22881 | GIR_RootConstrainSelectedInstOperands, |
| 22882 | // GIR_Coverage, 2660, |
| 22883 | GIR_EraseRootFromParent_Done, |
| 22884 | // Label 1280: @76836 |
| 22885 | GIM_Try, /*On fail goto*//*Label 1281*/ GIMT_Encode4(76898), // Rule ID 2661 // |
| 22886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 22887 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22888 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22891 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22892 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22894 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 22895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 22896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22900 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22901 | GIR_RootConstrainSelectedInstOperands, |
| 22902 | // GIR_Coverage, 2661, |
| 22903 | GIR_EraseRootFromParent_Done, |
| 22904 | // Label 1281: @76898 |
| 22905 | GIM_Try, /*On fail goto*//*Label 1282*/ GIMT_Encode4(76963), // Rule ID 2662 // |
| 22906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22907 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22908 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22911 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22912 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22914 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 22915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22922 | GIR_RootConstrainSelectedInstOperands, |
| 22923 | // GIR_Coverage, 2662, |
| 22924 | GIR_EraseRootFromParent_Done, |
| 22925 | // Label 1282: @76963 |
| 22926 | GIM_Try, /*On fail goto*//*Label 1283*/ GIMT_Encode4(77025), // Rule ID 7974 // |
| 22927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 22928 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22931 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22932 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 22935 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 22937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22942 | GIR_RootConstrainSelectedInstOperands, |
| 22943 | // GIR_Coverage, 7974, |
| 22944 | GIR_EraseRootFromParent_Done, |
| 22945 | // Label 1283: @77025 |
| 22946 | GIM_Try, /*On fail goto*//*Label 1284*/ GIMT_Encode4(77087), // Rule ID 7975 // |
| 22947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 22948 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22953 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22954 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 22955 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 22956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 22957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 22960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22961 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22962 | GIR_RootConstrainSelectedInstOperands, |
| 22963 | // GIR_Coverage, 7975, |
| 22964 | GIR_EraseRootFromParent_Done, |
| 22965 | // Label 1284: @77087 |
| 22966 | GIM_Try, /*On fail goto*//*Label 1285*/ GIMT_Encode4(77149), // Rule ID 7976 // |
| 22967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 22968 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22969 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22971 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22973 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22974 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22975 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 22976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 22977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 22980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 22981 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 22982 | GIR_RootConstrainSelectedInstOperands, |
| 22983 | // GIR_Coverage, 7976, |
| 22984 | GIR_EraseRootFromParent_Done, |
| 22985 | // Label 1285: @77149 |
| 22986 | GIM_Try, /*On fail goto*//*Label 1286*/ GIMT_Encode4(77214), // Rule ID 7977 // |
| 22987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 22988 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 22989 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 22990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 22991 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 22992 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 22993 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 22994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 22995 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 22996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 22997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 22998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 22999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23002 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23003 | GIR_RootConstrainSelectedInstOperands, |
| 23004 | // GIR_Coverage, 7977, |
| 23005 | GIR_EraseRootFromParent_Done, |
| 23006 | // Label 1286: @77214 |
| 23007 | GIM_Try, /*On fail goto*//*Label 1287*/ GIMT_Encode4(77272), // Rule ID 2631 // |
| 23008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23009 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23010 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23012 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23013 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23014 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23015 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23021 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23022 | GIR_RootConstrainSelectedInstOperands, |
| 23023 | // GIR_Coverage, 2631, |
| 23024 | GIR_EraseRootFromParent_Done, |
| 23025 | // Label 1287: @77272 |
| 23026 | GIM_Try, /*On fail goto*//*Label 1288*/ GIMT_Encode4(77330), // Rule ID 2632 // |
| 23027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 23028 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23029 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23031 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23032 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23034 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 23036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23041 | GIR_RootConstrainSelectedInstOperands, |
| 23042 | // GIR_Coverage, 2632, |
| 23043 | GIR_EraseRootFromParent_Done, |
| 23044 | // Label 1288: @77330 |
| 23045 | GIM_Try, /*On fail goto*//*Label 1289*/ GIMT_Encode4(77391), // Rule ID 2633 // |
| 23046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 23047 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23048 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23051 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23053 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 23055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23060 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23061 | GIR_RootConstrainSelectedInstOperands, |
| 23062 | // GIR_Coverage, 2633, |
| 23063 | GIR_EraseRootFromParent_Done, |
| 23064 | // Label 1289: @77391 |
| 23065 | GIM_Try, /*On fail goto*//*Label 1290*/ GIMT_Encode4(77449), // Rule ID 2665 // |
| 23066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23067 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23068 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23070 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23071 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23073 | // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23080 | GIR_RootConstrainSelectedInstOperands, |
| 23081 | // GIR_Coverage, 2665, |
| 23082 | GIR_EraseRootFromParent_Done, |
| 23083 | // Label 1290: @77449 |
| 23084 | GIM_Try, /*On fail goto*//*Label 1291*/ GIMT_Encode4(77507), // Rule ID 2666 // |
| 23085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 23086 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23087 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23090 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23092 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 23094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23099 | GIR_RootConstrainSelectedInstOperands, |
| 23100 | // GIR_Coverage, 2666, |
| 23101 | GIR_EraseRootFromParent_Done, |
| 23102 | // Label 1291: @77507 |
| 23103 | GIM_Try, /*On fail goto*//*Label 1292*/ GIMT_Encode4(77568), // Rule ID 2667 // |
| 23104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 23105 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23109 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23111 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 23113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23119 | GIR_RootConstrainSelectedInstOperands, |
| 23120 | // GIR_Coverage, 2667, |
| 23121 | GIR_EraseRootFromParent_Done, |
| 23122 | // Label 1292: @77568 |
| 23123 | GIM_Try, /*On fail goto*//*Label 1293*/ GIMT_Encode4(77626), // Rule ID 7980 // |
| 23124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23125 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23126 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23128 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23129 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23131 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23138 | GIR_RootConstrainSelectedInstOperands, |
| 23139 | // GIR_Coverage, 7980, |
| 23140 | GIR_EraseRootFromParent_Done, |
| 23141 | // Label 1293: @77626 |
| 23142 | GIM_Try, /*On fail goto*//*Label 1294*/ GIMT_Encode4(77684), // Rule ID 7981 // |
| 23143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 23144 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23148 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23150 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 23152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23157 | GIR_RootConstrainSelectedInstOperands, |
| 23158 | // GIR_Coverage, 7981, |
| 23159 | GIR_EraseRootFromParent_Done, |
| 23160 | // Label 1294: @77684 |
| 23161 | GIM_Try, /*On fail goto*//*Label 1295*/ GIMT_Encode4(77745), // Rule ID 7982 // |
| 23162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 23163 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23167 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23168 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23169 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 23171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23177 | GIR_RootConstrainSelectedInstOperands, |
| 23178 | // GIR_Coverage, 7982, |
| 23179 | GIR_EraseRootFromParent_Done, |
| 23180 | // Label 1295: @77745 |
| 23181 | GIM_Try, /*On fail goto*//*Label 1296*/ GIMT_Encode4(77813), // Rule ID 7683 // |
| 23182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 23183 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23184 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23185 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23186 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23188 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23189 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 23190 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23191 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 23193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23198 | GIR_RootConstrainSelectedInstOperands, |
| 23199 | // GIR_Coverage, 7683, |
| 23200 | GIR_EraseRootFromParent_Done, |
| 23201 | // Label 1296: @77813 |
| 23202 | GIM_Try, /*On fail goto*//*Label 1297*/ GIMT_Encode4(77881), // Rule ID 7687 // |
| 23203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 23204 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23205 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23206 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23207 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23209 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23210 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 23211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23212 | // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 23214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23218 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23219 | GIR_RootConstrainSelectedInstOperands, |
| 23220 | // GIR_Coverage, 7687, |
| 23221 | GIR_EraseRootFromParent_Done, |
| 23222 | // Label 1297: @77881 |
| 23223 | GIM_Try, /*On fail goto*//*Label 1298*/ GIMT_Encode4(77944), // Rule ID 7607 // |
| 23224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 23225 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23226 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23227 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 23228 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23230 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23231 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23232 | // (AMDGPUld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 23234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23239 | GIR_RootConstrainSelectedInstOperands, |
| 23240 | // GIR_Coverage, 7607, |
| 23241 | GIR_EraseRootFromParent_Done, |
| 23242 | // Label 1298: @77944 |
| 23243 | GIM_Try, /*On fail goto*//*Label 1299*/ GIMT_Encode4(78007), // Rule ID 7611 // |
| 23244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 23245 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23246 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23247 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 23248 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23250 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23251 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23252 | // (AMDGPUld_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 23254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23259 | GIR_RootConstrainSelectedInstOperands, |
| 23260 | // GIR_Coverage, 7611, |
| 23261 | GIR_EraseRootFromParent_Done, |
| 23262 | // Label 1299: @78007 |
| 23263 | GIM_Try, /*On fail goto*//*Label 1300*/ GIMT_Encode4(78062), // Rule ID 2636 // |
| 23264 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23268 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23270 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23276 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23277 | GIR_RootConstrainSelectedInstOperands, |
| 23278 | // GIR_Coverage, 2636, |
| 23279 | GIR_EraseRootFromParent_Done, |
| 23280 | // Label 1300: @78062 |
| 23281 | GIM_Try, /*On fail goto*//*Label 1301*/ GIMT_Encode4(78120), // Rule ID 2637 // |
| 23282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 23283 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23284 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23287 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 23289 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 23291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23296 | GIR_RootConstrainSelectedInstOperands, |
| 23297 | // GIR_Coverage, 2637, |
| 23298 | GIR_EraseRootFromParent_Done, |
| 23299 | // Label 1301: @78120 |
| 23300 | GIM_Try, /*On fail goto*//*Label 1302*/ GIMT_Encode4(78178), // Rule ID 2638 // |
| 23301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 23302 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23308 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 23310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23315 | GIR_RootConstrainSelectedInstOperands, |
| 23316 | // GIR_Coverage, 2638, |
| 23317 | GIR_EraseRootFromParent_Done, |
| 23318 | // Label 1302: @78178 |
| 23319 | GIM_Try, /*On fail goto*//*Label 1303*/ GIMT_Encode4(78239), // Rule ID 2639 // |
| 23320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 23321 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23322 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23323 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23324 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23325 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23327 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 23329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23335 | GIR_RootConstrainSelectedInstOperands, |
| 23336 | // GIR_Coverage, 2639, |
| 23337 | GIR_EraseRootFromParent_Done, |
| 23338 | // Label 1303: @78239 |
| 23339 | GIM_Try, /*On fail goto*//*Label 1304*/ GIMT_Encode4(78294), // Rule ID 2670 // |
| 23340 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23341 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23344 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23346 | // (ld:{ *:[f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23352 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23353 | GIR_RootConstrainSelectedInstOperands, |
| 23354 | // GIR_Coverage, 2670, |
| 23355 | GIR_EraseRootFromParent_Done, |
| 23356 | // Label 1304: @78294 |
| 23357 | GIM_Try, /*On fail goto*//*Label 1305*/ GIMT_Encode4(78352), // Rule ID 2671 // |
| 23358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 23359 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23363 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 23365 | // (ld:{ *:[f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 23367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23372 | GIR_RootConstrainSelectedInstOperands, |
| 23373 | // GIR_Coverage, 2671, |
| 23374 | GIR_EraseRootFromParent_Done, |
| 23375 | // Label 1305: @78352 |
| 23376 | GIM_Try, /*On fail goto*//*Label 1306*/ GIMT_Encode4(78410), // Rule ID 2672 // |
| 23377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 23378 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23379 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23382 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23384 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 23386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23390 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23391 | GIR_RootConstrainSelectedInstOperands, |
| 23392 | // GIR_Coverage, 2672, |
| 23393 | GIR_EraseRootFromParent_Done, |
| 23394 | // Label 1306: @78410 |
| 23395 | GIM_Try, /*On fail goto*//*Label 1307*/ GIMT_Encode4(78471), // Rule ID 2673 // |
| 23396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 23397 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23398 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23401 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23403 | // (ld:{ *:[f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 23405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23410 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23411 | GIR_RootConstrainSelectedInstOperands, |
| 23412 | // GIR_Coverage, 2673, |
| 23413 | GIR_EraseRootFromParent_Done, |
| 23414 | // Label 1307: @78471 |
| 23415 | GIM_Try, /*On fail goto*//*Label 1308*/ GIMT_Encode4(78526), // Rule ID 7985 // |
| 23416 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23419 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23420 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 23422 | // (ld:{ *:[i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23428 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23429 | GIR_RootConstrainSelectedInstOperands, |
| 23430 | // GIR_Coverage, 7985, |
| 23431 | GIR_EraseRootFromParent_Done, |
| 23432 | // Label 1308: @78526 |
| 23433 | GIM_Try, /*On fail goto*//*Label 1309*/ GIMT_Encode4(78584), // Rule ID 7986 // |
| 23434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 23435 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23436 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23439 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 23441 | // (ld:{ *:[i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 23443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23448 | GIR_RootConstrainSelectedInstOperands, |
| 23449 | // GIR_Coverage, 7986, |
| 23450 | GIR_EraseRootFromParent_Done, |
| 23451 | // Label 1309: @78584 |
| 23452 | GIM_Try, /*On fail goto*//*Label 1310*/ GIMT_Encode4(78642), // Rule ID 7987 // |
| 23453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 23454 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23455 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23458 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23460 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 23461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 23462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23467 | GIR_RootConstrainSelectedInstOperands, |
| 23468 | // GIR_Coverage, 7987, |
| 23469 | GIR_EraseRootFromParent_Done, |
| 23470 | // Label 1310: @78642 |
| 23471 | GIM_Try, /*On fail goto*//*Label 1311*/ GIMT_Encode4(78703), // Rule ID 7988 // |
| 23472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 23473 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23474 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23476 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23477 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 23479 | // (ld:{ *:[i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 23481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 23483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 23484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23487 | GIR_RootConstrainSelectedInstOperands, |
| 23488 | // GIR_Coverage, 7988, |
| 23489 | GIR_EraseRootFromParent_Done, |
| 23490 | // Label 1311: @78703 |
| 23491 | GIM_Try, /*On fail goto*//*Label 1312*/ GIMT_Encode4(78767), // Rule ID 7684 // |
| 23492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 23493 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23495 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23498 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 23499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23500 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 23502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23507 | GIR_RootConstrainSelectedInstOperands, |
| 23508 | // GIR_Coverage, 7684, |
| 23509 | GIR_EraseRootFromParent_Done, |
| 23510 | // Label 1312: @78767 |
| 23511 | GIM_Try, /*On fail goto*//*Label 1313*/ GIMT_Encode4(78831), // Rule ID 7688 // |
| 23512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 23513 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23514 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23515 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23518 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 23519 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23520 | // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 23522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23526 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23527 | GIR_RootConstrainSelectedInstOperands, |
| 23528 | // GIR_Coverage, 7688, |
| 23529 | GIR_EraseRootFromParent_Done, |
| 23530 | // Label 1313: @78831 |
| 23531 | GIM_Try, /*On fail goto*//*Label 1314*/ GIMT_Encode4(78890), // Rule ID 7608 // |
| 23532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 23533 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23534 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 23535 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23537 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23539 | // (ld:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 23541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23546 | GIR_RootConstrainSelectedInstOperands, |
| 23547 | // GIR_Coverage, 7608, |
| 23548 | GIR_EraseRootFromParent_Done, |
| 23549 | // Label 1314: @78890 |
| 23550 | GIM_Try, /*On fail goto*//*Label 1315*/ GIMT_Encode4(78949), // Rule ID 7612 // |
| 23551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 23552 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23553 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 23554 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23557 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 23558 | // (ld:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 23559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 23560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23564 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23565 | GIR_RootConstrainSelectedInstOperands, |
| 23566 | // GIR_Coverage, 7612, |
| 23567 | GIR_EraseRootFromParent_Done, |
| 23568 | // Label 1315: @78949 |
| 23569 | GIM_Try, /*On fail goto*//*Label 1316*/ GIMT_Encode4(79003), // Rule ID 2630 // |
| 23570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23571 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23572 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23574 | // MIs[0] sbase |
| 23575 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23576 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23577 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23578 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 23579 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23582 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23585 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23586 | GIR_RootConstrainSelectedInstOperands, |
| 23587 | // GIR_Coverage, 2630, |
| 23588 | GIR_EraseRootFromParent_Done, |
| 23589 | // Label 1316: @79003 |
| 23590 | GIM_Try, /*On fail goto*//*Label 1317*/ GIMT_Encode4(79057), // Rule ID 2664 // |
| 23591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23592 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23593 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23595 | // MIs[0] sbase |
| 23596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23597 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23598 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23599 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 23600 | // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23603 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23607 | GIR_RootConstrainSelectedInstOperands, |
| 23608 | // GIR_Coverage, 2664, |
| 23609 | GIR_EraseRootFromParent_Done, |
| 23610 | // Label 1317: @79057 |
| 23611 | GIM_Try, /*On fail goto*//*Label 1318*/ GIMT_Encode4(79111), // Rule ID 7979 // |
| 23612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23613 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23614 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23615 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23616 | // MIs[0] sbase |
| 23617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23618 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23619 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23620 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 23621 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23624 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23628 | GIR_RootConstrainSelectedInstOperands, |
| 23629 | // GIR_Coverage, 7979, |
| 23630 | GIR_EraseRootFromParent_Done, |
| 23631 | // Label 1318: @79111 |
| 23632 | GIM_Try, /*On fail goto*//*Label 1319*/ GIMT_Encode4(79161), // Rule ID 2635 // |
| 23633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23634 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23635 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23637 | // MIs[0] sbase |
| 23638 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23639 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23640 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23641 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23644 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23648 | GIR_RootConstrainSelectedInstOperands, |
| 23649 | // GIR_Coverage, 2635, |
| 23650 | GIR_EraseRootFromParent_Done, |
| 23651 | // Label 1319: @79161 |
| 23652 | GIM_Try, /*On fail goto*//*Label 1320*/ GIMT_Encode4(79211), // Rule ID 2669 // |
| 23653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23654 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23657 | // MIs[0] sbase |
| 23658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23659 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23660 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23661 | // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23664 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23667 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23668 | GIR_RootConstrainSelectedInstOperands, |
| 23669 | // GIR_Coverage, 2669, |
| 23670 | GIR_EraseRootFromParent_Done, |
| 23671 | // Label 1320: @79211 |
| 23672 | GIM_Try, /*On fail goto*//*Label 1321*/ GIMT_Encode4(79261), // Rule ID 7984 // |
| 23673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 23674 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23677 | // MIs[0] sbase |
| 23678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23679 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23680 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23681 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 23683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23684 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23688 | GIR_RootConstrainSelectedInstOperands, |
| 23689 | // GIR_Coverage, 7984, |
| 23690 | GIR_EraseRootFromParent_Done, |
| 23691 | // Label 1321: @79261 |
| 23692 | GIM_Try, /*On fail goto*//*Label 1322*/ GIMT_Encode4(79308), // Rule ID 2641 // |
| 23693 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23694 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23695 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23696 | // MIs[0] sbase |
| 23697 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23698 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23699 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23700 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23703 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23707 | GIR_RootConstrainSelectedInstOperands, |
| 23708 | // GIR_Coverage, 2641, |
| 23709 | GIR_EraseRootFromParent_Done, |
| 23710 | // Label 1322: @79308 |
| 23711 | GIM_Try, /*On fail goto*//*Label 1323*/ GIMT_Encode4(79355), // Rule ID 2675 // |
| 23712 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23713 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23715 | // MIs[0] sbase |
| 23716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23717 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23718 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23719 | // (ld:{ *:[f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23722 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23726 | GIR_RootConstrainSelectedInstOperands, |
| 23727 | // GIR_Coverage, 2675, |
| 23728 | GIR_EraseRootFromParent_Done, |
| 23729 | // Label 1323: @79355 |
| 23730 | GIM_Try, /*On fail goto*//*Label 1324*/ GIMT_Encode4(79402), // Rule ID 7990 // |
| 23731 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 23734 | // MIs[0] sbase |
| 23735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 23736 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 23737 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 23738 | // (ld:{ *:[i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 23739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 23740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 23741 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 23742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23745 | GIR_RootConstrainSelectedInstOperands, |
| 23746 | // GIR_Coverage, 7990, |
| 23747 | GIR_EraseRootFromParent_Done, |
| 23748 | // Label 1324: @79402 |
| 23749 | GIM_Try, /*On fail goto*//*Label 1325*/ GIMT_Encode4(79462), // Rule ID 3930 // |
| 23750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 23751 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23755 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 23756 | // (ld:{ *:[i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 23758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 23760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 23761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 23762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23764 | GIR_RootConstrainSelectedInstOperands, |
| 23765 | // GIR_Coverage, 3930, |
| 23766 | GIR_EraseRootFromParent_Done, |
| 23767 | // Label 1325: @79462 |
| 23768 | GIM_Try, /*On fail goto*//*Label 1326*/ GIMT_Encode4(79522), // Rule ID 3936 // |
| 23769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 23770 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 23775 | // (ld:{ *:[f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 23776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 23777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 23779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 23780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 23781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23783 | GIR_RootConstrainSelectedInstOperands, |
| 23784 | // GIR_Coverage, 3936, |
| 23785 | GIR_EraseRootFromParent_Done, |
| 23786 | // Label 1326: @79522 |
| 23787 | GIM_Try, /*On fail goto*//*Label 1327*/ GIMT_Encode4(79577), // Rule ID 3929 // |
| 23788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 23789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 23794 | // (ld:{ *:[i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 23795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 23796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 23798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23801 | GIR_RootConstrainSelectedInstOperands, |
| 23802 | // GIR_Coverage, 3929, |
| 23803 | GIR_EraseRootFromParent_Done, |
| 23804 | // Label 1327: @79577 |
| 23805 | GIM_Try, /*On fail goto*//*Label 1328*/ GIMT_Encode4(79632), // Rule ID 3935 // |
| 23806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 23807 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 23812 | // (ld:{ *:[f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 23813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 23814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 23816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23819 | GIR_RootConstrainSelectedInstOperands, |
| 23820 | // GIR_Coverage, 3935, |
| 23821 | GIR_EraseRootFromParent_Done, |
| 23822 | // Label 1328: @79632 |
| 23823 | GIM_Try, /*On fail goto*//*Label 1329*/ GIMT_Encode4(79687), // Rule ID 3928 // |
| 23824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 23825 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23826 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23828 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23829 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 23830 | // (ld:{ *:[i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 23831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 23832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 23834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23837 | GIR_RootConstrainSelectedInstOperands, |
| 23838 | // GIR_Coverage, 3928, |
| 23839 | GIR_EraseRootFromParent_Done, |
| 23840 | // Label 1329: @79687 |
| 23841 | GIM_Try, /*On fail goto*//*Label 1330*/ GIMT_Encode4(79742), // Rule ID 3934 // |
| 23842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 23843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 23844 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 23848 | // (ld:{ *:[f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 23849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 23850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 23852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 23853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23855 | GIR_RootConstrainSelectedInstOperands, |
| 23856 | // GIR_Coverage, 3934, |
| 23857 | GIR_EraseRootFromParent_Done, |
| 23858 | // Label 1330: @79742 |
| 23859 | GIM_Try, /*On fail goto*//*Label 1331*/ GIMT_Encode4(79819), // Rule ID 6111 // |
| 23860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 23861 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 23862 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 23863 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 23864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 23867 | // (atomic_load:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 23868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 23869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 23870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 23871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 23872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 23873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 23874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23877 | GIR_RootConstrainSelectedInstOperands, |
| 23878 | // GIR_Coverage, 6111, |
| 23879 | GIR_EraseRootFromParent_Done, |
| 23880 | // Label 1331: @79819 |
| 23881 | GIM_Try, /*On fail goto*//*Label 1332*/ GIMT_Encode4(79889), // Rule ID 4166 // |
| 23882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 23883 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 23884 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 23888 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 23889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 23890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 23891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 23892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 23893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 23894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 23895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23898 | GIR_RootConstrainSelectedInstOperands, |
| 23899 | // GIR_Coverage, 4166, |
| 23900 | GIR_EraseRootFromParent_Done, |
| 23901 | // Label 1332: @79889 |
| 23902 | GIM_Try, /*On fail goto*//*Label 1333*/ GIMT_Encode4(79956), // Rule ID 4168 // |
| 23903 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 23904 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 23908 | // (ld:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 23909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 23910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 23911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 23912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 23913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 23914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 23915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23918 | GIR_RootConstrainSelectedInstOperands, |
| 23919 | // GIR_Coverage, 4168, |
| 23920 | GIR_EraseRootFromParent_Done, |
| 23921 | // Label 1333: @79956 |
| 23922 | GIM_Try, /*On fail goto*//*Label 1334*/ GIMT_Encode4(80026), // Rule ID 4170 // |
| 23923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 23924 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 23925 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23927 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23928 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 23929 | // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 23930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 23931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 23932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 23933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 23934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 23935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 23936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23939 | GIR_RootConstrainSelectedInstOperands, |
| 23940 | // GIR_Coverage, 4170, |
| 23941 | GIR_EraseRootFromParent_Done, |
| 23942 | // Label 1334: @80026 |
| 23943 | GIM_Try, /*On fail goto*//*Label 1335*/ GIMT_Encode4(80093), // Rule ID 4172 // |
| 23944 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 23945 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 23949 | // (ld:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 23950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 23951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 23952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 23953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 23954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 23955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 23956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23959 | GIR_RootConstrainSelectedInstOperands, |
| 23960 | // GIR_Coverage, 4172, |
| 23961 | GIR_EraseRootFromParent_Done, |
| 23962 | // Label 1335: @80093 |
| 23963 | GIM_Try, /*On fail goto*//*Label 1336*/ GIMT_Encode4(80157), // Rule ID 7539 // |
| 23964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 23965 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23966 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23967 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 23971 | // (AMDGPUld_glue:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 23972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 23973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 23976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 23977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23978 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23979 | GIR_RootConstrainSelectedInstOperands, |
| 23980 | // GIR_Coverage, 7539, |
| 23981 | GIR_EraseRootFromParent_Done, |
| 23982 | // Label 1336: @80157 |
| 23983 | GIM_Try, /*On fail goto*//*Label 1337*/ GIMT_Encode4(80221), // Rule ID 7547 // |
| 23984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 23985 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 23986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 23987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 23988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 23989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 23990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 23991 | // (AMDGPUld_glue:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 23992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 23993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 23994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 23995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 23996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 23997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 23998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 23999 | GIR_RootConstrainSelectedInstOperands, |
| 24000 | // GIR_Coverage, 7547, |
| 24001 | GIR_EraseRootFromParent_Done, |
| 24002 | // Label 1337: @80221 |
| 24003 | GIM_Try, /*On fail goto*//*Label 1338*/ GIMT_Encode4(80286), // Rule ID 4165 // |
| 24004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 24005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 24010 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 24011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 24012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 24013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 24014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24019 | GIR_RootConstrainSelectedInstOperands, |
| 24020 | // GIR_Coverage, 4165, |
| 24021 | GIR_EraseRootFromParent_Done, |
| 24022 | // Label 1338: @80286 |
| 24023 | GIM_Try, /*On fail goto*//*Label 1339*/ GIMT_Encode4(80348), // Rule ID 4167 // |
| 24024 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24025 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 24029 | // (ld:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 24030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 24031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 24032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 24033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24037 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24038 | GIR_RootConstrainSelectedInstOperands, |
| 24039 | // GIR_Coverage, 4167, |
| 24040 | GIR_EraseRootFromParent_Done, |
| 24041 | // Label 1339: @80348 |
| 24042 | GIM_Try, /*On fail goto*//*Label 1340*/ GIMT_Encode4(80413), // Rule ID 4169 // |
| 24043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 24044 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24045 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 24049 | // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 24050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 24051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 24052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 24053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24058 | GIR_RootConstrainSelectedInstOperands, |
| 24059 | // GIR_Coverage, 4169, |
| 24060 | GIR_EraseRootFromParent_Done, |
| 24061 | // Label 1340: @80413 |
| 24062 | GIM_Try, /*On fail goto*//*Label 1341*/ GIMT_Encode4(80475), // Rule ID 4171 // |
| 24063 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 24068 | // (ld:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 24069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 24070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 24071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 24072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24077 | GIR_RootConstrainSelectedInstOperands, |
| 24078 | // GIR_Coverage, 4171, |
| 24079 | GIR_EraseRootFromParent_Done, |
| 24080 | // Label 1341: @80475 |
| 24081 | GIM_Try, /*On fail goto*//*Label 1342*/ GIMT_Encode4(80535), // Rule ID 7541 // |
| 24082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 24083 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 24084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 24088 | // (ld:{ *:[i64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 24089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 24090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 24092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 24093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 24094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24095 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24096 | GIR_RootConstrainSelectedInstOperands, |
| 24097 | // GIR_Coverage, 7541, |
| 24098 | GIR_EraseRootFromParent_Done, |
| 24099 | // Label 1342: @80535 |
| 24100 | GIM_Try, /*On fail goto*//*Label 1343*/ GIMT_Encode4(80595), // Rule ID 7549 // |
| 24101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 24102 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 24103 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 24107 | // (ld:{ *:[f64] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 24108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 24109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 24111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 24112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 24113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24114 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24115 | GIR_RootConstrainSelectedInstOperands, |
| 24116 | // GIR_Coverage, 7549, |
| 24117 | GIR_EraseRootFromParent_Done, |
| 24118 | // Label 1343: @80595 |
| 24119 | GIM_Try, /*On fail goto*//*Label 1344*/ GIMT_Encode4(80657), // Rule ID 7485 // |
| 24120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 24121 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 24122 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 24123 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24125 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 24127 | // (AMDGPUatomic_ld_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64_glue>><<P:Predicate_atomic_load_64_local_m0>> => (DS_READ_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 24128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 24129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 24131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24134 | GIR_RootConstrainSelectedInstOperands, |
| 24135 | // GIR_Coverage, 7485, |
| 24136 | GIR_EraseRootFromParent_Done, |
| 24137 | // Label 1344: @80657 |
| 24138 | GIM_Try, /*On fail goto*//*Label 1345*/ GIMT_Encode4(80719), // Rule ID 7486 // |
| 24139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 24140 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 24141 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 24142 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 24146 | // (atomic_load:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_local>> => (DS_READ_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 24147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 24148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 24150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24153 | GIR_RootConstrainSelectedInstOperands, |
| 24154 | // GIR_Coverage, 7486, |
| 24155 | GIR_EraseRootFromParent_Done, |
| 24156 | // Label 1345: @80719 |
| 24157 | GIM_Try, /*On fail goto*//*Label 1346*/ GIMT_Encode4(80788), // Rule ID 3557 // |
| 24158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24159 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 24160 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24161 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 24165 | // (atomic_load:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 24167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 24169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 24170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24173 | GIR_RootConstrainSelectedInstOperands, |
| 24174 | // GIR_Coverage, 3557, |
| 24175 | GIR_EraseRootFromParent_Done, |
| 24176 | // Label 1346: @80788 |
| 24177 | GIM_Try, /*On fail goto*//*Label 1347*/ GIMT_Encode4(80850), // Rule ID 3485 // |
| 24178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24179 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24180 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24182 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 24184 | // (ld:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 24186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 24188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 24189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24191 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24192 | GIR_RootConstrainSelectedInstOperands, |
| 24193 | // GIR_Coverage, 3485, |
| 24194 | GIR_EraseRootFromParent_Done, |
| 24195 | // Label 1347: @80850 |
| 24196 | GIM_Try, /*On fail goto*//*Label 1348*/ GIMT_Encode4(80912), // Rule ID 3489 // |
| 24197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24198 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24199 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24201 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 24203 | // (ld:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 24205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 24207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 24208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24210 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24211 | GIR_RootConstrainSelectedInstOperands, |
| 24212 | // GIR_Coverage, 3489, |
| 24213 | GIR_EraseRootFromParent_Done, |
| 24214 | // Label 1348: @80912 |
| 24215 | GIM_Try, /*On fail goto*//*Label 1349*/ GIMT_Encode4(80976), // Rule ID 3556 // |
| 24216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24217 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 24218 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24219 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24221 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24222 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 24223 | // (atomic_load:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 24225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24230 | GIR_RootConstrainSelectedInstOperands, |
| 24231 | // GIR_Coverage, 3556, |
| 24232 | GIR_EraseRootFromParent_Done, |
| 24233 | // Label 1349: @80976 |
| 24234 | GIM_Try, /*On fail goto*//*Label 1350*/ GIMT_Encode4(81033), // Rule ID 3484 // |
| 24235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24236 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24237 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24239 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24240 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 24241 | // (ld:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 24243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24248 | GIR_RootConstrainSelectedInstOperands, |
| 24249 | // GIR_Coverage, 3484, |
| 24250 | GIR_EraseRootFromParent_Done, |
| 24251 | // Label 1350: @81033 |
| 24252 | GIM_Try, /*On fail goto*//*Label 1351*/ GIMT_Encode4(81090), // Rule ID 3488 // |
| 24253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 24254 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24255 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24257 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 24259 | // (ld:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 24261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24266 | GIR_RootConstrainSelectedInstOperands, |
| 24267 | // GIR_Coverage, 3488, |
| 24268 | GIR_EraseRootFromParent_Done, |
| 24269 | // Label 1351: @81090 |
| 24270 | GIM_Try, /*On fail goto*//*Label 1352*/ GIMT_Encode4(81155), // Rule ID 3226 // |
| 24271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 24272 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 24273 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24274 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 24275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24276 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 24278 | // (atomic_load:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_load_64>><<P:Predicate_atomic_load_64_flat>> => (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 24280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24284 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24285 | GIR_RootConstrainSelectedInstOperands, |
| 24286 | // GIR_Coverage, 3226, |
| 24287 | GIR_EraseRootFromParent_Done, |
| 24288 | // Label 1352: @81155 |
| 24289 | GIM_Try, /*On fail goto*//*Label 1353*/ GIMT_Encode4(81213), // Rule ID 3248 // |
| 24290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 24291 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24292 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24294 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 24296 | // (ld:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 24298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24302 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24303 | GIR_RootConstrainSelectedInstOperands, |
| 24304 | // GIR_Coverage, 3248, |
| 24305 | GIR_EraseRootFromParent_Done, |
| 24306 | // Label 1353: @81213 |
| 24307 | GIM_Try, /*On fail goto*//*Label 1354*/ GIMT_Encode4(81271), // Rule ID 3250 // |
| 24308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 24309 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 24310 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 24312 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 24314 | // (ld:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 24315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 24316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 24317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 24318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24320 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24321 | GIR_RootConstrainSelectedInstOperands, |
| 24322 | // GIR_Coverage, 3250, |
| 24323 | GIR_EraseRootFromParent_Done, |
| 24324 | // Label 1354: @81271 |
| 24325 | GIM_Reject, |
| 24326 | // Label 858: @81272 |
| 24327 | GIM_Try, /*On fail goto*//*Label 1355*/ GIMT_Encode4(81339), // Rule ID 2528 // |
| 24328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24329 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24330 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24332 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24333 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24336 | // (ld:{ *:[v2i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24343 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24344 | GIR_RootConstrainSelectedInstOperands, |
| 24345 | // GIR_Coverage, 2528, |
| 24346 | GIR_EraseRootFromParent_Done, |
| 24347 | // Label 1355: @81339 |
| 24348 | GIM_Try, /*On fail goto*//*Label 1356*/ GIMT_Encode4(81406), // Rule ID 2540 // |
| 24349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24350 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24351 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24353 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24354 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24355 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24356 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24357 | // (ld:{ *:[v2f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24364 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24365 | GIR_RootConstrainSelectedInstOperands, |
| 24366 | // GIR_Coverage, 2540, |
| 24367 | GIR_EraseRootFromParent_Done, |
| 24368 | // Label 1356: @81406 |
| 24369 | GIM_Try, /*On fail goto*//*Label 1357*/ GIMT_Encode4(81473), // Rule ID 2552 // |
| 24370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24371 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24372 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24374 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24375 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24376 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24378 | // (ld:{ *:[v2bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24385 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24386 | GIR_RootConstrainSelectedInstOperands, |
| 24387 | // GIR_Coverage, 2552, |
| 24388 | GIR_EraseRootFromParent_Done, |
| 24389 | // Label 1357: @81473 |
| 24390 | GIM_Try, /*On fail goto*//*Label 1358*/ GIMT_Encode4(81536), // Rule ID 2534 // |
| 24391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24392 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24393 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24395 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24396 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24397 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24398 | // (ld:{ *:[v2i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24406 | GIR_RootConstrainSelectedInstOperands, |
| 24407 | // GIR_Coverage, 2534, |
| 24408 | GIR_EraseRootFromParent_Done, |
| 24409 | // Label 1358: @81536 |
| 24410 | GIM_Try, /*On fail goto*//*Label 1359*/ GIMT_Encode4(81599), // Rule ID 2546 // |
| 24411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24412 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24413 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24415 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24416 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24417 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24418 | // (ld:{ *:[v2f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24426 | GIR_RootConstrainSelectedInstOperands, |
| 24427 | // GIR_Coverage, 2546, |
| 24428 | GIR_EraseRootFromParent_Done, |
| 24429 | // Label 1359: @81599 |
| 24430 | GIM_Try, /*On fail goto*//*Label 1360*/ GIMT_Encode4(81662), // Rule ID 2558 // |
| 24431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24432 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24433 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24435 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24436 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 24438 | // (ld:{ *:[v2bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 24444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24445 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24446 | GIR_RootConstrainSelectedInstOperands, |
| 24447 | // GIR_Coverage, 2558, |
| 24448 | GIR_EraseRootFromParent_Done, |
| 24449 | // Label 1360: @81662 |
| 24450 | GIM_Try, /*On fail goto*//*Label 1361*/ GIMT_Encode4(81724), // Rule ID 2524 // |
| 24451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24452 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24453 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24455 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24456 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24457 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24459 | // (ld:{ *:[v2i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24466 | GIR_RootConstrainSelectedInstOperands, |
| 24467 | // GIR_Coverage, 2524, |
| 24468 | GIR_EraseRootFromParent_Done, |
| 24469 | // Label 1361: @81724 |
| 24470 | GIM_Try, /*On fail goto*//*Label 1362*/ GIMT_Encode4(81786), // Rule ID 2525 // |
| 24471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 24472 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24476 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24477 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24479 | // (ld:{ *:[v2i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24486 | GIR_RootConstrainSelectedInstOperands, |
| 24487 | // GIR_Coverage, 2525, |
| 24488 | GIR_EraseRootFromParent_Done, |
| 24489 | // Label 1362: @81786 |
| 24490 | GIM_Try, /*On fail goto*//*Label 1363*/ GIMT_Encode4(81848), // Rule ID 2526 // |
| 24491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 24492 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24493 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24495 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24496 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24497 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24499 | // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24505 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24506 | GIR_RootConstrainSelectedInstOperands, |
| 24507 | // GIR_Coverage, 2526, |
| 24508 | GIR_EraseRootFromParent_Done, |
| 24509 | // Label 1363: @81848 |
| 24510 | GIM_Try, /*On fail goto*//*Label 1364*/ GIMT_Encode4(81913), // Rule ID 2527 // |
| 24511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24512 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24513 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24516 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24517 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24519 | // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24526 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24527 | GIR_RootConstrainSelectedInstOperands, |
| 24528 | // GIR_Coverage, 2527, |
| 24529 | GIR_EraseRootFromParent_Done, |
| 24530 | // Label 1364: @81913 |
| 24531 | GIM_Try, /*On fail goto*//*Label 1365*/ GIMT_Encode4(81975), // Rule ID 2536 // |
| 24532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24533 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24534 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24536 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24537 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24538 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24540 | // (ld:{ *:[v2f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24547 | GIR_RootConstrainSelectedInstOperands, |
| 24548 | // GIR_Coverage, 2536, |
| 24549 | GIR_EraseRootFromParent_Done, |
| 24550 | // Label 1365: @81975 |
| 24551 | GIM_Try, /*On fail goto*//*Label 1366*/ GIMT_Encode4(82037), // Rule ID 2537 // |
| 24552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 24553 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24554 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24557 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24558 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24560 | // (ld:{ *:[v2f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24566 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24567 | GIR_RootConstrainSelectedInstOperands, |
| 24568 | // GIR_Coverage, 2537, |
| 24569 | GIR_EraseRootFromParent_Done, |
| 24570 | // Label 1366: @82037 |
| 24571 | GIM_Try, /*On fail goto*//*Label 1367*/ GIMT_Encode4(82099), // Rule ID 2538 // |
| 24572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 24573 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24574 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24576 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24577 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24578 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24580 | // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24587 | GIR_RootConstrainSelectedInstOperands, |
| 24588 | // GIR_Coverage, 2538, |
| 24589 | GIR_EraseRootFromParent_Done, |
| 24590 | // Label 1367: @82099 |
| 24591 | GIM_Try, /*On fail goto*//*Label 1368*/ GIMT_Encode4(82164), // Rule ID 2539 // |
| 24592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24593 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24594 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24597 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24598 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24600 | // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24608 | GIR_RootConstrainSelectedInstOperands, |
| 24609 | // GIR_Coverage, 2539, |
| 24610 | GIR_EraseRootFromParent_Done, |
| 24611 | // Label 1368: @82164 |
| 24612 | GIM_Try, /*On fail goto*//*Label 1369*/ GIMT_Encode4(82226), // Rule ID 2548 // |
| 24613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24614 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24615 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24618 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24619 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24620 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24621 | // (ld:{ *:[v2bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24628 | GIR_RootConstrainSelectedInstOperands, |
| 24629 | // GIR_Coverage, 2548, |
| 24630 | GIR_EraseRootFromParent_Done, |
| 24631 | // Label 1369: @82226 |
| 24632 | GIM_Try, /*On fail goto*//*Label 1370*/ GIMT_Encode4(82288), // Rule ID 2549 // |
| 24633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 24634 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24635 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24638 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24639 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24640 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24641 | // (ld:{ *:[v2bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24648 | GIR_RootConstrainSelectedInstOperands, |
| 24649 | // GIR_Coverage, 2549, |
| 24650 | GIR_EraseRootFromParent_Done, |
| 24651 | // Label 1370: @82288 |
| 24652 | GIM_Try, /*On fail goto*//*Label 1371*/ GIMT_Encode4(82350), // Rule ID 2550 // |
| 24653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 24654 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24658 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24659 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24661 | // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24667 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24668 | GIR_RootConstrainSelectedInstOperands, |
| 24669 | // GIR_Coverage, 2550, |
| 24670 | GIR_EraseRootFromParent_Done, |
| 24671 | // Label 1371: @82350 |
| 24672 | GIM_Try, /*On fail goto*//*Label 1372*/ GIMT_Encode4(82415), // Rule ID 2551 // |
| 24673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 24674 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24678 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24679 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24680 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24681 | // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24689 | GIR_RootConstrainSelectedInstOperands, |
| 24690 | // GIR_Coverage, 2551, |
| 24691 | GIR_EraseRootFromParent_Done, |
| 24692 | // Label 1372: @82415 |
| 24693 | GIM_Try, /*On fail goto*//*Label 1373*/ GIMT_Encode4(82470), // Rule ID 2530 // |
| 24694 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24697 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24700 | // (ld:{ *:[v2i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24707 | GIR_RootConstrainSelectedInstOperands, |
| 24708 | // GIR_Coverage, 2530, |
| 24709 | GIR_EraseRootFromParent_Done, |
| 24710 | // Label 1373: @82470 |
| 24711 | GIM_Try, /*On fail goto*//*Label 1374*/ GIMT_Encode4(82528), // Rule ID 2531 // |
| 24712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 24713 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24714 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24717 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24719 | // (ld:{ *:[v2i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24726 | GIR_RootConstrainSelectedInstOperands, |
| 24727 | // GIR_Coverage, 2531, |
| 24728 | GIR_EraseRootFromParent_Done, |
| 24729 | // Label 1374: @82528 |
| 24730 | GIM_Try, /*On fail goto*//*Label 1375*/ GIMT_Encode4(82586), // Rule ID 2532 // |
| 24731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 24732 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24733 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24735 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24738 | // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24745 | GIR_RootConstrainSelectedInstOperands, |
| 24746 | // GIR_Coverage, 2532, |
| 24747 | GIR_EraseRootFromParent_Done, |
| 24748 | // Label 1375: @82586 |
| 24749 | GIM_Try, /*On fail goto*//*Label 1376*/ GIMT_Encode4(82647), // Rule ID 2533 // |
| 24750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24751 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24755 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24756 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24757 | // (ld:{ *:[v2i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24765 | GIR_RootConstrainSelectedInstOperands, |
| 24766 | // GIR_Coverage, 2533, |
| 24767 | GIR_EraseRootFromParent_Done, |
| 24768 | // Label 1376: @82647 |
| 24769 | GIM_Try, /*On fail goto*//*Label 1377*/ GIMT_Encode4(82702), // Rule ID 2542 // |
| 24770 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24774 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24776 | // (ld:{ *:[v2f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24783 | GIR_RootConstrainSelectedInstOperands, |
| 24784 | // GIR_Coverage, 2542, |
| 24785 | GIR_EraseRootFromParent_Done, |
| 24786 | // Label 1377: @82702 |
| 24787 | GIM_Try, /*On fail goto*//*Label 1378*/ GIMT_Encode4(82760), // Rule ID 2543 // |
| 24788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 24789 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24792 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24795 | // (ld:{ *:[v2f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24802 | GIR_RootConstrainSelectedInstOperands, |
| 24803 | // GIR_Coverage, 2543, |
| 24804 | GIR_EraseRootFromParent_Done, |
| 24805 | // Label 1378: @82760 |
| 24806 | GIM_Try, /*On fail goto*//*Label 1379*/ GIMT_Encode4(82818), // Rule ID 2544 // |
| 24807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 24808 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24809 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24812 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24814 | // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24821 | GIR_RootConstrainSelectedInstOperands, |
| 24822 | // GIR_Coverage, 2544, |
| 24823 | GIR_EraseRootFromParent_Done, |
| 24824 | // Label 1379: @82818 |
| 24825 | GIM_Try, /*On fail goto*//*Label 1380*/ GIMT_Encode4(82879), // Rule ID 2545 // |
| 24826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24827 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24833 | // (ld:{ *:[v2f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24841 | GIR_RootConstrainSelectedInstOperands, |
| 24842 | // GIR_Coverage, 2545, |
| 24843 | GIR_EraseRootFromParent_Done, |
| 24844 | // Label 1380: @82879 |
| 24845 | GIM_Try, /*On fail goto*//*Label 1381*/ GIMT_Encode4(82934), // Rule ID 2554 // |
| 24846 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24847 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24849 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 24852 | // (ld:{ *:[v2bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24859 | GIR_RootConstrainSelectedInstOperands, |
| 24860 | // GIR_Coverage, 2554, |
| 24861 | GIR_EraseRootFromParent_Done, |
| 24862 | // Label 1381: @82934 |
| 24863 | GIM_Try, /*On fail goto*//*Label 1382*/ GIMT_Encode4(82992), // Rule ID 2555 // |
| 24864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 24865 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24866 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24869 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 24871 | // (ld:{ *:[v2bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM_ci:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 24872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM_ci), |
| 24873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 24876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24877 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24878 | GIR_RootConstrainSelectedInstOperands, |
| 24879 | // GIR_Coverage, 2555, |
| 24880 | GIR_EraseRootFromParent_Done, |
| 24881 | // Label 1382: @82992 |
| 24882 | GIM_Try, /*On fail goto*//*Label 1383*/ GIMT_Encode4(83050), // Rule ID 2556 // |
| 24883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 24884 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24885 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24890 | // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 24891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR), |
| 24892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24897 | GIR_RootConstrainSelectedInstOperands, |
| 24898 | // GIR_Coverage, 2556, |
| 24899 | GIR_EraseRootFromParent_Done, |
| 24900 | // Label 1383: @83050 |
| 24901 | GIM_Try, /*On fail goto*//*Label 1384*/ GIMT_Encode4(83111), // Rule ID 2557 // |
| 24902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 24903 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24904 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 24907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 24909 | // (ld:{ *:[v2bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_SGPR_IMM:{ *:[v2bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_SGPR_IMM), |
| 24911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 24913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 24914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24917 | GIR_RootConstrainSelectedInstOperands, |
| 24918 | // GIR_Coverage, 2557, |
| 24919 | GIR_EraseRootFromParent_Done, |
| 24920 | // Label 1384: @83111 |
| 24921 | GIM_Try, /*On fail goto*//*Label 1385*/ GIMT_Encode4(83165), // Rule ID 2529 // |
| 24922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24923 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24924 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24926 | // MIs[0] sbase |
| 24927 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24928 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 24929 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24930 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24931 | // (ld:{ *:[v2i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24934 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 24935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24938 | GIR_RootConstrainSelectedInstOperands, |
| 24939 | // GIR_Coverage, 2529, |
| 24940 | GIR_EraseRootFromParent_Done, |
| 24941 | // Label 1385: @83165 |
| 24942 | GIM_Try, /*On fail goto*//*Label 1386*/ GIMT_Encode4(83219), // Rule ID 2541 // |
| 24943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24944 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24945 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24947 | // MIs[0] sbase |
| 24948 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24949 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 24950 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24951 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24952 | // (ld:{ *:[v2f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24955 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 24956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24959 | GIR_RootConstrainSelectedInstOperands, |
| 24960 | // GIR_Coverage, 2541, |
| 24961 | GIR_EraseRootFromParent_Done, |
| 24962 | // Label 1386: @83219 |
| 24963 | GIM_Try, /*On fail goto*//*Label 1387*/ GIMT_Encode4(83273), // Rule ID 2553 // |
| 24964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 24965 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24966 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24968 | // MIs[0] sbase |
| 24969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24970 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 24971 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 24973 | // (ld:{ *:[v2bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24976 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 24977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24979 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24980 | GIR_RootConstrainSelectedInstOperands, |
| 24981 | // GIR_Coverage, 2553, |
| 24982 | GIR_EraseRootFromParent_Done, |
| 24983 | // Label 1387: @83273 |
| 24984 | GIM_Try, /*On fail goto*//*Label 1388*/ GIMT_Encode4(83320), // Rule ID 2535 // |
| 24985 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 24986 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 24987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 24988 | // MIs[0] sbase |
| 24989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 24990 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 24991 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 24992 | // (ld:{ *:[v2i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 24993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 24994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 24995 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 24996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 24998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 24999 | GIR_RootConstrainSelectedInstOperands, |
| 25000 | // GIR_Coverage, 2535, |
| 25001 | GIR_EraseRootFromParent_Done, |
| 25002 | // Label 1388: @83320 |
| 25003 | GIM_Try, /*On fail goto*//*Label 1389*/ GIMT_Encode4(83367), // Rule ID 2547 // |
| 25004 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25005 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 25007 | // MIs[0] sbase |
| 25008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25009 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 25010 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 25011 | // (ld:{ *:[v2f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 25012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 25013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 25014 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 25015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25018 | GIR_RootConstrainSelectedInstOperands, |
| 25019 | // GIR_Coverage, 2547, |
| 25020 | GIR_EraseRootFromParent_Done, |
| 25021 | // Label 1389: @83367 |
| 25022 | GIM_Try, /*On fail goto*//*Label 1390*/ GIMT_Encode4(83414), // Rule ID 2559 // |
| 25023 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 25026 | // MIs[0] sbase |
| 25027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 25028 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 25029 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 25030 | // (ld:{ *:[v2bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORD_IMM:{ *:[v2bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 25031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORD_IMM), |
| 25032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 25033 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 25034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25037 | GIR_RootConstrainSelectedInstOperands, |
| 25038 | // GIR_Coverage, 2559, |
| 25039 | GIR_EraseRootFromParent_Done, |
| 25040 | // Label 1390: @83414 |
| 25041 | GIM_Try, /*On fail goto*//*Label 1391*/ GIMT_Encode4(83477), // Rule ID 6178 // |
| 25042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25043 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25048 | // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25056 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25057 | GIR_RootConstrainSelectedInstOperands, |
| 25058 | // GIR_Coverage, 6178, |
| 25059 | GIR_EraseRootFromParent_Done, |
| 25060 | // Label 1391: @83477 |
| 25061 | GIM_Try, /*On fail goto*//*Label 1392*/ GIMT_Encode4(83540), // Rule ID 6180 // |
| 25062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25063 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25064 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25068 | // (ld:{ *:[v2i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25077 | GIR_RootConstrainSelectedInstOperands, |
| 25078 | // GIR_Coverage, 6180, |
| 25079 | GIR_EraseRootFromParent_Done, |
| 25080 | // Label 1392: @83540 |
| 25081 | GIM_Try, /*On fail goto*//*Label 1393*/ GIMT_Encode4(83603), // Rule ID 6182 // |
| 25082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25083 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25088 | // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25097 | GIR_RootConstrainSelectedInstOperands, |
| 25098 | // GIR_Coverage, 6182, |
| 25099 | GIR_EraseRootFromParent_Done, |
| 25100 | // Label 1393: @83603 |
| 25101 | GIM_Try, /*On fail goto*//*Label 1394*/ GIMT_Encode4(83666), // Rule ID 6184 // |
| 25102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25103 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25106 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25107 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25108 | // (ld:{ *:[v2f16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25117 | GIR_RootConstrainSelectedInstOperands, |
| 25118 | // GIR_Coverage, 6184, |
| 25119 | GIR_EraseRootFromParent_Done, |
| 25120 | // Label 1394: @83666 |
| 25121 | GIM_Try, /*On fail goto*//*Label 1395*/ GIMT_Encode4(83729), // Rule ID 6186 // |
| 25122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25123 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25128 | // (ld:{ *:[v2bf16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2bf16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25136 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25137 | GIR_RootConstrainSelectedInstOperands, |
| 25138 | // GIR_Coverage, 6186, |
| 25139 | GIR_EraseRootFromParent_Done, |
| 25140 | // Label 1395: @83729 |
| 25141 | GIM_Try, /*On fail goto*//*Label 1396*/ GIMT_Encode4(83792), // Rule ID 6188 // |
| 25142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25143 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 25148 | // (ld:{ *:[v2bf16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2bf16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25157 | GIR_RootConstrainSelectedInstOperands, |
| 25158 | // GIR_Coverage, 6188, |
| 25159 | GIR_EraseRootFromParent_Done, |
| 25160 | // Label 1396: @83792 |
| 25161 | GIM_Try, /*On fail goto*//*Label 1397*/ GIMT_Encode4(83852), // Rule ID 3888 // |
| 25162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 25163 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25167 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 25168 | // (ld:{ *:[v2i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 25170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 25173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25175 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25176 | GIR_RootConstrainSelectedInstOperands, |
| 25177 | // GIR_Coverage, 3888, |
| 25178 | GIR_EraseRootFromParent_Done, |
| 25179 | // Label 1397: @83852 |
| 25180 | GIM_Try, /*On fail goto*//*Label 1398*/ GIMT_Encode4(83912), // Rule ID 3894 // |
| 25181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 25182 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25183 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 25187 | // (ld:{ *:[v2f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 25189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 25192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25195 | GIR_RootConstrainSelectedInstOperands, |
| 25196 | // GIR_Coverage, 3894, |
| 25197 | GIR_EraseRootFromParent_Done, |
| 25198 | // Label 1398: @83912 |
| 25199 | GIM_Try, /*On fail goto*//*Label 1399*/ GIMT_Encode4(83972), // Rule ID 3900 // |
| 25200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 25201 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25202 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 25206 | // (ld:{ *:[v2bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SVS:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SVS), |
| 25208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 25211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25213 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25214 | GIR_RootConstrainSelectedInstOperands, |
| 25215 | // GIR_Coverage, 3900, |
| 25216 | GIR_EraseRootFromParent_Done, |
| 25217 | // Label 1399: @83972 |
| 25218 | GIM_Try, /*On fail goto*//*Label 1400*/ GIMT_Encode4(84027), // Rule ID 3887 // |
| 25219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25220 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25221 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25223 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 25225 | // (ld:{ *:[v2i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 25226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 25227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25231 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25232 | GIR_RootConstrainSelectedInstOperands, |
| 25233 | // GIR_Coverage, 3887, |
| 25234 | GIR_EraseRootFromParent_Done, |
| 25235 | // Label 1400: @84027 |
| 25236 | GIM_Try, /*On fail goto*//*Label 1401*/ GIMT_Encode4(84082), // Rule ID 3893 // |
| 25237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25238 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25239 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25241 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25242 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 25243 | // (ld:{ *:[v2f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 25244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 25245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25250 | GIR_RootConstrainSelectedInstOperands, |
| 25251 | // GIR_Coverage, 3893, |
| 25252 | GIR_EraseRootFromParent_Done, |
| 25253 | // Label 1401: @84082 |
| 25254 | GIM_Try, /*On fail goto*//*Label 1402*/ GIMT_Encode4(84137), // Rule ID 3899 // |
| 25255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25256 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25257 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25260 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 25261 | // (ld:{ *:[v2bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD_SADDR:{ *:[v2bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 25262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD_SADDR), |
| 25263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25267 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25268 | GIR_RootConstrainSelectedInstOperands, |
| 25269 | // GIR_Coverage, 3899, |
| 25270 | GIR_EraseRootFromParent_Done, |
| 25271 | // Label 1402: @84137 |
| 25272 | GIM_Try, /*On fail goto*//*Label 1403*/ GIMT_Encode4(84192), // Rule ID 3886 // |
| 25273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25274 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25275 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25277 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 25279 | // (ld:{ *:[v2i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 25281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25285 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25286 | GIR_RootConstrainSelectedInstOperands, |
| 25287 | // GIR_Coverage, 3886, |
| 25288 | GIR_EraseRootFromParent_Done, |
| 25289 | // Label 1403: @84192 |
| 25290 | GIM_Try, /*On fail goto*//*Label 1404*/ GIMT_Encode4(84247), // Rule ID 3892 // |
| 25291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25292 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25293 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25295 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 25297 | // (ld:{ *:[v2f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 25299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25304 | GIR_RootConstrainSelectedInstOperands, |
| 25305 | // GIR_Coverage, 3892, |
| 25306 | GIR_EraseRootFromParent_Done, |
| 25307 | // Label 1404: @84247 |
| 25308 | GIM_Try, /*On fail goto*//*Label 1405*/ GIMT_Encode4(84302), // Rule ID 3898 // |
| 25309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 25310 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25311 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 25315 | // (ld:{ *:[v2bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORD), |
| 25317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25321 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25322 | GIR_RootConstrainSelectedInstOperands, |
| 25323 | // GIR_Coverage, 3898, |
| 25324 | GIR_EraseRootFromParent_Done, |
| 25325 | // Label 1405: @84302 |
| 25326 | GIM_Try, /*On fail goto*//*Label 1406*/ GIMT_Encode4(84372), // Rule ID 4138 // |
| 25327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25328 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25329 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25331 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25333 | // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 25335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25342 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25343 | GIR_RootConstrainSelectedInstOperands, |
| 25344 | // GIR_Coverage, 4138, |
| 25345 | GIR_EraseRootFromParent_Done, |
| 25346 | // Label 1406: @84372 |
| 25347 | GIM_Try, /*On fail goto*//*Label 1407*/ GIMT_Encode4(84439), // Rule ID 4140 // |
| 25348 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25349 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25351 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25352 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25353 | // (ld:{ *:[v2i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 25355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25362 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25363 | GIR_RootConstrainSelectedInstOperands, |
| 25364 | // GIR_Coverage, 4140, |
| 25365 | GIR_EraseRootFromParent_Done, |
| 25366 | // Label 1407: @84439 |
| 25367 | GIM_Try, /*On fail goto*//*Label 1408*/ GIMT_Encode4(84509), // Rule ID 4142 // |
| 25368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25369 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25372 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25374 | // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 25376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25384 | GIR_RootConstrainSelectedInstOperands, |
| 25385 | // GIR_Coverage, 4142, |
| 25386 | GIR_EraseRootFromParent_Done, |
| 25387 | // Label 1408: @84509 |
| 25388 | GIM_Try, /*On fail goto*//*Label 1409*/ GIMT_Encode4(84576), // Rule ID 4144 // |
| 25389 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25390 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25392 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25394 | // (ld:{ *:[v2f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 25396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25403 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25404 | GIR_RootConstrainSelectedInstOperands, |
| 25405 | // GIR_Coverage, 4144, |
| 25406 | GIR_EraseRootFromParent_Done, |
| 25407 | // Label 1409: @84576 |
| 25408 | GIM_Try, /*On fail goto*//*Label 1410*/ GIMT_Encode4(84646), // Rule ID 4146 // |
| 25409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25410 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25411 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25413 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25415 | // (ld:{ *:[v2bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_ADDR64:{ *:[v2bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_ADDR64), |
| 25417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25424 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25425 | GIR_RootConstrainSelectedInstOperands, |
| 25426 | // GIR_Coverage, 4146, |
| 25427 | GIR_EraseRootFromParent_Done, |
| 25428 | // Label 1410: @84646 |
| 25429 | GIM_Try, /*On fail goto*//*Label 1411*/ GIMT_Encode4(84713), // Rule ID 4148 // |
| 25430 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25431 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 25435 | // (ld:{ *:[v2bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_ADDR64:{ *:[v2bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_ADDR64), |
| 25437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25445 | GIR_RootConstrainSelectedInstOperands, |
| 25446 | // GIR_Coverage, 4148, |
| 25447 | GIR_EraseRootFromParent_Done, |
| 25448 | // Label 1411: @84713 |
| 25449 | GIM_Try, /*On fail goto*//*Label 1412*/ GIMT_Encode4(84781), // Rule ID 6177 // |
| 25450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25451 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25452 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25454 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25456 | // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 25458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25466 | GIR_RootConstrainSelectedInstOperands, |
| 25467 | // GIR_Coverage, 6177, |
| 25468 | GIR_EraseRootFromParent_Done, |
| 25469 | // Label 1412: @84781 |
| 25470 | GIM_Try, /*On fail goto*//*Label 1413*/ GIMT_Encode4(84849), // Rule ID 6179 // |
| 25471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25472 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25477 | // (ld:{ *:[v2i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 25479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25487 | GIR_RootConstrainSelectedInstOperands, |
| 25488 | // GIR_Coverage, 6179, |
| 25489 | GIR_EraseRootFromParent_Done, |
| 25490 | // Label 1413: @84849 |
| 25491 | GIM_Try, /*On fail goto*//*Label 1414*/ GIMT_Encode4(84917), // Rule ID 6181 // |
| 25492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25493 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25494 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25498 | // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 25500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25508 | GIR_RootConstrainSelectedInstOperands, |
| 25509 | // GIR_Coverage, 6181, |
| 25510 | GIR_EraseRootFromParent_Done, |
| 25511 | // Label 1414: @84917 |
| 25512 | GIM_Try, /*On fail goto*//*Label 1415*/ GIMT_Encode4(84985), // Rule ID 6183 // |
| 25513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25514 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25515 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25519 | // (ld:{ *:[v2f16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 25521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25529 | GIR_RootConstrainSelectedInstOperands, |
| 25530 | // GIR_Coverage, 6183, |
| 25531 | GIR_EraseRootFromParent_Done, |
| 25532 | // Label 1415: @84985 |
| 25533 | GIM_Try, /*On fail goto*//*Label 1416*/ GIMT_Encode4(85053), // Rule ID 6185 // |
| 25534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 25535 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25536 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25540 | // (ld:{ *:[v2bf16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 25542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25550 | GIR_RootConstrainSelectedInstOperands, |
| 25551 | // GIR_Coverage, 6185, |
| 25552 | GIR_EraseRootFromParent_Done, |
| 25553 | // Label 1416: @85053 |
| 25554 | GIM_Try, /*On fail goto*//*Label 1417*/ GIMT_Encode4(85121), // Rule ID 6187 // |
| 25555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 25556 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 25557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25559 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 25561 | // (ld:{ *:[v2bf16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 25562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 25563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 25565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 25567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 25568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25571 | GIR_RootConstrainSelectedInstOperands, |
| 25572 | // GIR_Coverage, 6187, |
| 25573 | GIR_EraseRootFromParent_Done, |
| 25574 | // Label 1417: @85121 |
| 25575 | GIM_Try, /*On fail goto*//*Label 1418*/ GIMT_Encode4(85186), // Rule ID 4137 // |
| 25576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25577 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25582 | // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25590 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25591 | GIR_RootConstrainSelectedInstOperands, |
| 25592 | // GIR_Coverage, 4137, |
| 25593 | GIR_EraseRootFromParent_Done, |
| 25594 | // Label 1418: @85186 |
| 25595 | GIM_Try, /*On fail goto*//*Label 1419*/ GIMT_Encode4(85248), // Rule ID 4139 // |
| 25596 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25601 | // (ld:{ *:[v2i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25609 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25610 | GIR_RootConstrainSelectedInstOperands, |
| 25611 | // GIR_Coverage, 4139, |
| 25612 | GIR_EraseRootFromParent_Done, |
| 25613 | // Label 1419: @85248 |
| 25614 | GIM_Try, /*On fail goto*//*Label 1420*/ GIMT_Encode4(85313), // Rule ID 4141 // |
| 25615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25616 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25619 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25620 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25621 | // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25630 | GIR_RootConstrainSelectedInstOperands, |
| 25631 | // GIR_Coverage, 4141, |
| 25632 | GIR_EraseRootFromParent_Done, |
| 25633 | // Label 1420: @85313 |
| 25634 | GIM_Try, /*On fail goto*//*Label 1421*/ GIMT_Encode4(85375), // Rule ID 4143 // |
| 25635 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25636 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25638 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25639 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25640 | // (ld:{ *:[v2f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25648 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25649 | GIR_RootConstrainSelectedInstOperands, |
| 25650 | // GIR_Coverage, 4143, |
| 25651 | GIR_EraseRootFromParent_Done, |
| 25652 | // Label 1421: @85375 |
| 25653 | GIM_Try, /*On fail goto*//*Label 1422*/ GIMT_Encode4(85440), // Rule ID 4145 // |
| 25654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 25655 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25656 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25660 | // (ld:{ *:[v2bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 25662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25669 | GIR_RootConstrainSelectedInstOperands, |
| 25670 | // GIR_Coverage, 4145, |
| 25671 | GIR_EraseRootFromParent_Done, |
| 25672 | // Label 1422: @85440 |
| 25673 | GIM_Try, /*On fail goto*//*Label 1423*/ GIMT_Encode4(85502), // Rule ID 4147 // |
| 25674 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 25679 | // (ld:{ *:[v2bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 25680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 25681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 25682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 25683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25688 | GIR_RootConstrainSelectedInstOperands, |
| 25689 | // GIR_Coverage, 4147, |
| 25690 | GIR_EraseRootFromParent_Done, |
| 25691 | // Label 1423: @85502 |
| 25692 | GIM_Try, /*On fail goto*//*Label 1424*/ GIMT_Encode4(85561), // Rule ID 7461 // |
| 25693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 25694 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25695 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25696 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25698 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25700 | // (AMDGPUld_glue:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 25702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25707 | GIR_RootConstrainSelectedInstOperands, |
| 25708 | // GIR_Coverage, 7461, |
| 25709 | GIR_EraseRootFromParent_Done, |
| 25710 | // Label 1424: @85561 |
| 25711 | GIM_Try, /*On fail goto*//*Label 1425*/ GIMT_Encode4(85620), // Rule ID 7463 // |
| 25712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 25713 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25714 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25717 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25719 | // (AMDGPUld_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 25721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25726 | GIR_RootConstrainSelectedInstOperands, |
| 25727 | // GIR_Coverage, 7463, |
| 25728 | GIR_EraseRootFromParent_Done, |
| 25729 | // Label 1425: @85620 |
| 25730 | GIM_Try, /*On fail goto*//*Label 1426*/ GIMT_Encode4(85679), // Rule ID 7465 // |
| 25731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 25732 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25733 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25734 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25738 | // (AMDGPUld_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B32:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32), |
| 25740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25745 | GIR_RootConstrainSelectedInstOperands, |
| 25746 | // GIR_Coverage, 7465, |
| 25747 | GIR_EraseRootFromParent_Done, |
| 25748 | // Label 1426: @85679 |
| 25749 | GIM_Try, /*On fail goto*//*Label 1427*/ GIMT_Encode4(85734), // Rule ID 7462 // |
| 25750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 25751 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25755 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25756 | // (ld:{ *:[v2i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[v2i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 25758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25762 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25763 | GIR_RootConstrainSelectedInstOperands, |
| 25764 | // GIR_Coverage, 7462, |
| 25765 | GIR_EraseRootFromParent_Done, |
| 25766 | // Label 1427: @85734 |
| 25767 | GIM_Try, /*On fail goto*//*Label 1428*/ GIMT_Encode4(85789), // Rule ID 7464 // |
| 25768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 25769 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25774 | // (ld:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 25776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25781 | GIR_RootConstrainSelectedInstOperands, |
| 25782 | // GIR_Coverage, 7464, |
| 25783 | GIR_EraseRootFromParent_Done, |
| 25784 | // Label 1428: @85789 |
| 25785 | GIM_Try, /*On fail goto*//*Label 1429*/ GIMT_Encode4(85844), // Rule ID 7466 // |
| 25786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 25787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 25788 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25790 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 25792 | // (ld:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B32_gfx9:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 25793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B32_gfx9), |
| 25794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 25796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25798 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25799 | GIR_RootConstrainSelectedInstOperands, |
| 25800 | // GIR_Coverage, 7466, |
| 25801 | GIR_EraseRootFromParent_Done, |
| 25802 | // Label 1429: @85844 |
| 25803 | GIM_Try, /*On fail goto*//*Label 1430*/ GIMT_Encode4(85906), // Rule ID 3457 // |
| 25804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25805 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25806 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 25810 | // (ld:{ *:[v2i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 25812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 25815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25818 | GIR_RootConstrainSelectedInstOperands, |
| 25819 | // GIR_Coverage, 3457, |
| 25820 | GIR_EraseRootFromParent_Done, |
| 25821 | // Label 1430: @85906 |
| 25822 | GIM_Try, /*On fail goto*//*Label 1431*/ GIMT_Encode4(85968), // Rule ID 3461 // |
| 25823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25824 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25825 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 25829 | // (ld:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 25831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 25834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25837 | GIR_RootConstrainSelectedInstOperands, |
| 25838 | // GIR_Coverage, 3461, |
| 25839 | GIR_EraseRootFromParent_Done, |
| 25840 | // Label 1431: @85968 |
| 25841 | GIM_Try, /*On fail goto*//*Label 1432*/ GIMT_Encode4(86030), // Rule ID 3465 // |
| 25842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25844 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 25848 | // (ld:{ *:[v2bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD_SADDR:{ *:[v2bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD_SADDR), |
| 25850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 25852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 25853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25855 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25856 | GIR_RootConstrainSelectedInstOperands, |
| 25857 | // GIR_Coverage, 3465, |
| 25858 | GIR_EraseRootFromParent_Done, |
| 25859 | // Label 1432: @86030 |
| 25860 | GIM_Try, /*On fail goto*//*Label 1433*/ GIMT_Encode4(86087), // Rule ID 3456 // |
| 25861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25862 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25863 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 25867 | // (ld:{ *:[v2i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 25869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25873 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25874 | GIR_RootConstrainSelectedInstOperands, |
| 25875 | // GIR_Coverage, 3456, |
| 25876 | GIR_EraseRootFromParent_Done, |
| 25877 | // Label 1433: @86087 |
| 25878 | GIM_Try, /*On fail goto*//*Label 1434*/ GIMT_Encode4(86144), // Rule ID 3460 // |
| 25879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25880 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25881 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25883 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25884 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 25885 | // (ld:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 25887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25892 | GIR_RootConstrainSelectedInstOperands, |
| 25893 | // GIR_Coverage, 3460, |
| 25894 | GIR_EraseRootFromParent_Done, |
| 25895 | // Label 1434: @86144 |
| 25896 | GIM_Try, /*On fail goto*//*Label 1435*/ GIMT_Encode4(86201), // Rule ID 3464 // |
| 25897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 25898 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25899 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25901 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25902 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 25903 | // (ld:{ *:[v2bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORD), |
| 25905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25909 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25910 | GIR_RootConstrainSelectedInstOperands, |
| 25911 | // GIR_Coverage, 3464, |
| 25912 | GIR_EraseRootFromParent_Done, |
| 25913 | // Label 1435: @86201 |
| 25914 | GIM_Try, /*On fail goto*//*Label 1436*/ GIMT_Encode4(86259), // Rule ID 3233 // |
| 25915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 25916 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25917 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25919 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 25921 | // (ld:{ *:[v2i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[v2i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 25923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25927 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25928 | GIR_RootConstrainSelectedInstOperands, |
| 25929 | // GIR_Coverage, 3233, |
| 25930 | GIR_EraseRootFromParent_Done, |
| 25931 | // Label 1436: @86259 |
| 25932 | GIM_Try, /*On fail goto*//*Label 1437*/ GIMT_Encode4(86317), // Rule ID 3235 // |
| 25933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 25934 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25935 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 25939 | // (ld:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[v2f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 25941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25945 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25946 | GIR_RootConstrainSelectedInstOperands, |
| 25947 | // GIR_Coverage, 3235, |
| 25948 | GIR_EraseRootFromParent_Done, |
| 25949 | // Label 1437: @86317 |
| 25950 | GIM_Try, /*On fail goto*//*Label 1438*/ GIMT_Encode4(86375), // Rule ID 3237 // |
| 25951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 25952 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 25953 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 25955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 25957 | // (ld:{ *:[v2bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORD:{ *:[v2bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 25958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORD), |
| 25959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 25960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 25961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 25962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25964 | GIR_RootConstrainSelectedInstOperands, |
| 25965 | // GIR_Coverage, 3237, |
| 25966 | GIR_EraseRootFromParent_Done, |
| 25967 | // Label 1438: @86375 |
| 25968 | GIM_Reject, |
| 25969 | // Label 859: @86376 |
| 25970 | GIM_Try, /*On fail goto*//*Label 1439*/ GIMT_Encode4(86443), // Rule ID 2612 // |
| 25971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 25972 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25973 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 25975 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25976 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 25977 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 25978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 25979 | // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 25980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 25981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 25982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 25983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 25984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 25985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 25986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 25987 | GIR_RootConstrainSelectedInstOperands, |
| 25988 | // GIR_Coverage, 2612, |
| 25989 | GIR_EraseRootFromParent_Done, |
| 25990 | // Label 1439: @86443 |
| 25991 | GIM_Try, /*On fail goto*//*Label 1440*/ GIMT_Encode4(86510), // Rule ID 2646 // |
| 25992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 25993 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 25994 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 25995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 25996 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 25997 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 25998 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 25999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 26000 | // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26007 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26008 | GIR_RootConstrainSelectedInstOperands, |
| 26009 | // GIR_Coverage, 2646, |
| 26010 | GIR_EraseRootFromParent_Done, |
| 26011 | // Label 1440: @86510 |
| 26012 | GIM_Try, /*On fail goto*//*Label 1441*/ GIMT_Encode4(86573), // Rule ID 2617 // |
| 26013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26014 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26015 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26017 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26018 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 26020 | // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 26022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26027 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26028 | GIR_RootConstrainSelectedInstOperands, |
| 26029 | // GIR_Coverage, 2617, |
| 26030 | GIR_EraseRootFromParent_Done, |
| 26031 | // Label 1441: @86573 |
| 26032 | GIM_Try, /*On fail goto*//*Label 1442*/ GIMT_Encode4(86636), // Rule ID 2651 // |
| 26033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26034 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26035 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26038 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 26040 | // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 26042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26048 | GIR_RootConstrainSelectedInstOperands, |
| 26049 | // GIR_Coverage, 2651, |
| 26050 | GIR_EraseRootFromParent_Done, |
| 26051 | // Label 1442: @86636 |
| 26052 | GIM_Try, /*On fail goto*//*Label 1443*/ GIMT_Encode4(86699), // Rule ID 2623 // |
| 26053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 26054 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26055 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26057 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26058 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 26060 | // (ld:{ *:[v2i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26067 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26068 | GIR_RootConstrainSelectedInstOperands, |
| 26069 | // GIR_Coverage, 2623, |
| 26070 | GIR_EraseRootFromParent_Done, |
| 26071 | // Label 1443: @86699 |
| 26072 | GIM_Try, /*On fail goto*//*Label 1444*/ GIMT_Encode4(86762), // Rule ID 2657 // |
| 26073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 26074 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26075 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26077 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26078 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26079 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 26080 | // (ld:{ *:[v2f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26087 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26088 | GIR_RootConstrainSelectedInstOperands, |
| 26089 | // GIR_Coverage, 2657, |
| 26090 | GIR_EraseRootFromParent_Done, |
| 26091 | // Label 1444: @86762 |
| 26092 | GIM_Try, /*On fail goto*//*Label 1445*/ GIMT_Encode4(86824), // Rule ID 2608 // |
| 26093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26094 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26095 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26097 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26098 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26099 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26101 | // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26107 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26108 | GIR_RootConstrainSelectedInstOperands, |
| 26109 | // GIR_Coverage, 2608, |
| 26110 | GIR_EraseRootFromParent_Done, |
| 26111 | // Label 1445: @86824 |
| 26112 | GIM_Try, /*On fail goto*//*Label 1446*/ GIMT_Encode4(86886), // Rule ID 2609 // |
| 26113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 26114 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26115 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26117 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26118 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26119 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 26121 | // (ld:{ *:[v2i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 26123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26127 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26128 | GIR_RootConstrainSelectedInstOperands, |
| 26129 | // GIR_Coverage, 2609, |
| 26130 | GIR_EraseRootFromParent_Done, |
| 26131 | // Label 1446: @86886 |
| 26132 | GIM_Try, /*On fail goto*//*Label 1447*/ GIMT_Encode4(86948), // Rule ID 2610 // |
| 26133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 26134 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26135 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26138 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26139 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26140 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26141 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 26143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26148 | GIR_RootConstrainSelectedInstOperands, |
| 26149 | // GIR_Coverage, 2610, |
| 26150 | GIR_EraseRootFromParent_Done, |
| 26151 | // Label 1447: @86948 |
| 26152 | GIM_Try, /*On fail goto*//*Label 1448*/ GIMT_Encode4(87013), // Rule ID 2611 // |
| 26153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26154 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26155 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26157 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26158 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26159 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26160 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26161 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26169 | GIR_RootConstrainSelectedInstOperands, |
| 26170 | // GIR_Coverage, 2611, |
| 26171 | GIR_EraseRootFromParent_Done, |
| 26172 | // Label 1448: @87013 |
| 26173 | GIM_Try, /*On fail goto*//*Label 1449*/ GIMT_Encode4(87075), // Rule ID 2642 // |
| 26174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26175 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26179 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26180 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26181 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26182 | // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26188 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26189 | GIR_RootConstrainSelectedInstOperands, |
| 26190 | // GIR_Coverage, 2642, |
| 26191 | GIR_EraseRootFromParent_Done, |
| 26192 | // Label 1449: @87075 |
| 26193 | GIM_Try, /*On fail goto*//*Label 1450*/ GIMT_Encode4(87137), // Rule ID 2643 // |
| 26194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 26195 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26196 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26198 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26199 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26200 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 26202 | // (ld:{ *:[v2f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 26204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26208 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26209 | GIR_RootConstrainSelectedInstOperands, |
| 26210 | // GIR_Coverage, 2643, |
| 26211 | GIR_EraseRootFromParent_Done, |
| 26212 | // Label 1450: @87137 |
| 26213 | GIM_Try, /*On fail goto*//*Label 1451*/ GIMT_Encode4(87199), // Rule ID 2644 // |
| 26214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 26215 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26216 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26218 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26219 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26220 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26221 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26222 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 26224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26229 | GIR_RootConstrainSelectedInstOperands, |
| 26230 | // GIR_Coverage, 2644, |
| 26231 | GIR_EraseRootFromParent_Done, |
| 26232 | // Label 1451: @87199 |
| 26233 | GIM_Try, /*On fail goto*//*Label 1452*/ GIMT_Encode4(87264), // Rule ID 2645 // |
| 26234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26235 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26236 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26239 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26240 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26242 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26250 | GIR_RootConstrainSelectedInstOperands, |
| 26251 | // GIR_Coverage, 2645, |
| 26252 | GIR_EraseRootFromParent_Done, |
| 26253 | // Label 1452: @87264 |
| 26254 | GIM_Try, /*On fail goto*//*Label 1453*/ GIMT_Encode4(87322), // Rule ID 2614 // |
| 26255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26256 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26257 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26260 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26262 | // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 26264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26268 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26269 | GIR_RootConstrainSelectedInstOperands, |
| 26270 | // GIR_Coverage, 2614, |
| 26271 | GIR_EraseRootFromParent_Done, |
| 26272 | // Label 1453: @87322 |
| 26273 | GIM_Try, /*On fail goto*//*Label 1454*/ GIMT_Encode4(87380), // Rule ID 2615 // |
| 26274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 26275 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26278 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26279 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26281 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 26283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26287 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26288 | GIR_RootConstrainSelectedInstOperands, |
| 26289 | // GIR_Coverage, 2615, |
| 26290 | GIR_EraseRootFromParent_Done, |
| 26291 | // Label 1454: @87380 |
| 26292 | GIM_Try, /*On fail goto*//*Label 1455*/ GIMT_Encode4(87441), // Rule ID 2616 // |
| 26293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26294 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26295 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26297 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26298 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26300 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 26302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26308 | GIR_RootConstrainSelectedInstOperands, |
| 26309 | // GIR_Coverage, 2616, |
| 26310 | GIR_EraseRootFromParent_Done, |
| 26311 | // Label 1455: @87441 |
| 26312 | GIM_Try, /*On fail goto*//*Label 1456*/ GIMT_Encode4(87499), // Rule ID 2648 // |
| 26313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26314 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26315 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26318 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26320 | // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 26322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26327 | GIR_RootConstrainSelectedInstOperands, |
| 26328 | // GIR_Coverage, 2648, |
| 26329 | GIR_EraseRootFromParent_Done, |
| 26330 | // Label 1456: @87499 |
| 26331 | GIM_Try, /*On fail goto*//*Label 1457*/ GIMT_Encode4(87557), // Rule ID 2649 // |
| 26332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 26333 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26334 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26337 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26339 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 26341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26345 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26346 | GIR_RootConstrainSelectedInstOperands, |
| 26347 | // GIR_Coverage, 2649, |
| 26348 | GIR_EraseRootFromParent_Done, |
| 26349 | // Label 1457: @87557 |
| 26350 | GIM_Try, /*On fail goto*//*Label 1458*/ GIMT_Encode4(87618), // Rule ID 2650 // |
| 26351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 26352 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26353 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26355 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26356 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26357 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26358 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 26360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26365 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26366 | GIR_RootConstrainSelectedInstOperands, |
| 26367 | // GIR_Coverage, 2650, |
| 26368 | GIR_EraseRootFromParent_Done, |
| 26369 | // Label 1458: @87618 |
| 26370 | GIM_Try, /*On fail goto*//*Label 1459*/ GIMT_Encode4(87686), // Rule ID 7691 // |
| 26371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 26372 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26373 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26374 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26377 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26378 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 26379 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26380 | // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 26382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26387 | GIR_RootConstrainSelectedInstOperands, |
| 26388 | // GIR_Coverage, 7691, |
| 26389 | GIR_EraseRootFromParent_Done, |
| 26390 | // Label 1459: @87686 |
| 26391 | GIM_Try, /*On fail goto*//*Label 1460*/ GIMT_Encode4(87754), // Rule ID 7695 // |
| 26392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 26393 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26394 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26395 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26396 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26398 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26399 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 26400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26401 | // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 26403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26407 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26408 | GIR_RootConstrainSelectedInstOperands, |
| 26409 | // GIR_Coverage, 7695, |
| 26410 | GIR_EraseRootFromParent_Done, |
| 26411 | // Label 1460: @87754 |
| 26412 | GIM_Try, /*On fail goto*//*Label 1461*/ GIMT_Encode4(87817), // Rule ID 7615 // |
| 26413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 26414 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26415 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26416 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 26417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26419 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26421 | // (AMDGPUld_glue:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 26423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26427 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26428 | GIR_RootConstrainSelectedInstOperands, |
| 26429 | // GIR_Coverage, 7615, |
| 26430 | GIR_EraseRootFromParent_Done, |
| 26431 | // Label 1461: @87817 |
| 26432 | GIM_Try, /*On fail goto*//*Label 1462*/ GIMT_Encode4(87880), // Rule ID 7619 // |
| 26433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 26434 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26435 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26436 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 26437 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26441 | // (AMDGPUld_glue:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 26443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26448 | GIR_RootConstrainSelectedInstOperands, |
| 26449 | // GIR_Coverage, 7619, |
| 26450 | GIR_EraseRootFromParent_Done, |
| 26451 | // Label 1462: @87880 |
| 26452 | GIM_Try, /*On fail goto*//*Label 1463*/ GIMT_Encode4(87935), // Rule ID 2619 // |
| 26453 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26454 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26457 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26459 | // (ld:{ *:[v2i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26466 | GIR_RootConstrainSelectedInstOperands, |
| 26467 | // GIR_Coverage, 2619, |
| 26468 | GIR_EraseRootFromParent_Done, |
| 26469 | // Label 1463: @87935 |
| 26470 | GIM_Try, /*On fail goto*//*Label 1464*/ GIMT_Encode4(87993), // Rule ID 2620 // |
| 26471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 26472 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26476 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26477 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 26478 | // (ld:{ *:[v2i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 26480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26485 | GIR_RootConstrainSelectedInstOperands, |
| 26486 | // GIR_Coverage, 2620, |
| 26487 | GIR_EraseRootFromParent_Done, |
| 26488 | // Label 1464: @87993 |
| 26489 | GIM_Try, /*On fail goto*//*Label 1465*/ GIMT_Encode4(88051), // Rule ID 2621 // |
| 26490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 26491 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26494 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26495 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26497 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 26499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26503 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26504 | GIR_RootConstrainSelectedInstOperands, |
| 26505 | // GIR_Coverage, 2621, |
| 26506 | GIR_EraseRootFromParent_Done, |
| 26507 | // Label 1465: @88051 |
| 26508 | GIM_Try, /*On fail goto*//*Label 1466*/ GIMT_Encode4(88112), // Rule ID 2622 // |
| 26509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 26510 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26511 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26513 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26514 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26516 | // (ld:{ *:[v2i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26523 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26524 | GIR_RootConstrainSelectedInstOperands, |
| 26525 | // GIR_Coverage, 2622, |
| 26526 | GIR_EraseRootFromParent_Done, |
| 26527 | // Label 1466: @88112 |
| 26528 | GIM_Try, /*On fail goto*//*Label 1467*/ GIMT_Encode4(88167), // Rule ID 2653 // |
| 26529 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26530 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26533 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 26535 | // (ld:{ *:[v2f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26541 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26542 | GIR_RootConstrainSelectedInstOperands, |
| 26543 | // GIR_Coverage, 2653, |
| 26544 | GIR_EraseRootFromParent_Done, |
| 26545 | // Label 1467: @88167 |
| 26546 | GIM_Try, /*On fail goto*//*Label 1468*/ GIMT_Encode4(88225), // Rule ID 2654 // |
| 26547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 26548 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26549 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26551 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26552 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 26554 | // (ld:{ *:[v2f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 26556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26560 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26561 | GIR_RootConstrainSelectedInstOperands, |
| 26562 | // GIR_Coverage, 2654, |
| 26563 | GIR_EraseRootFromParent_Done, |
| 26564 | // Label 1468: @88225 |
| 26565 | GIM_Try, /*On fail goto*//*Label 1469*/ GIMT_Encode4(88283), // Rule ID 2655 // |
| 26566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 26567 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26568 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26570 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26571 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26572 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26573 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 26574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 26575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26579 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26580 | GIR_RootConstrainSelectedInstOperands, |
| 26581 | // GIR_Coverage, 2655, |
| 26582 | GIR_EraseRootFromParent_Done, |
| 26583 | // Label 1469: @88283 |
| 26584 | GIM_Try, /*On fail goto*//*Label 1470*/ GIMT_Encode4(88344), // Rule ID 2656 // |
| 26585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 26586 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26587 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26590 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26591 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 26592 | // (ld:{ *:[v2f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 26594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 26596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26599 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26600 | GIR_RootConstrainSelectedInstOperands, |
| 26601 | // GIR_Coverage, 2656, |
| 26602 | GIR_EraseRootFromParent_Done, |
| 26603 | // Label 1470: @88344 |
| 26604 | GIM_Try, /*On fail goto*//*Label 1471*/ GIMT_Encode4(88408), // Rule ID 7692 // |
| 26605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 26606 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26607 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26608 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26610 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26611 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 26612 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26613 | // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 26615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26620 | GIR_RootConstrainSelectedInstOperands, |
| 26621 | // GIR_Coverage, 7692, |
| 26622 | GIR_EraseRootFromParent_Done, |
| 26623 | // Label 1471: @88408 |
| 26624 | GIM_Try, /*On fail goto*//*Label 1472*/ GIMT_Encode4(88472), // Rule ID 7696 // |
| 26625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 26626 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26627 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26628 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26630 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26631 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 26632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26633 | // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 26635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26640 | GIR_RootConstrainSelectedInstOperands, |
| 26641 | // GIR_Coverage, 7696, |
| 26642 | GIR_EraseRootFromParent_Done, |
| 26643 | // Label 1472: @88472 |
| 26644 | GIM_Try, /*On fail goto*//*Label 1473*/ GIMT_Encode4(88531), // Rule ID 7616 // |
| 26645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 26646 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26647 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 26648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26650 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26652 | // (ld:{ *:[v2i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 26654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26659 | GIR_RootConstrainSelectedInstOperands, |
| 26660 | // GIR_Coverage, 7616, |
| 26661 | GIR_EraseRootFromParent_Done, |
| 26662 | // Label 1473: @88531 |
| 26663 | GIM_Try, /*On fail goto*//*Label 1474*/ GIMT_Encode4(88590), // Rule ID 7620 // |
| 26664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 26665 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 26666 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 26667 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26669 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26670 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 26671 | // (ld:{ *:[v2f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 26672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 26673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 26675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26677 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26678 | GIR_RootConstrainSelectedInstOperands, |
| 26679 | // GIR_Coverage, 7620, |
| 26680 | GIR_EraseRootFromParent_Done, |
| 26681 | // Label 1474: @88590 |
| 26682 | GIM_Try, /*On fail goto*//*Label 1475*/ GIMT_Encode4(88644), // Rule ID 2613 // |
| 26683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26684 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26685 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26687 | // MIs[0] sbase |
| 26688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26689 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26690 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26691 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26692 | // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26695 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26698 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26699 | GIR_RootConstrainSelectedInstOperands, |
| 26700 | // GIR_Coverage, 2613, |
| 26701 | GIR_EraseRootFromParent_Done, |
| 26702 | // Label 1475: @88644 |
| 26703 | GIM_Try, /*On fail goto*//*Label 1476*/ GIMT_Encode4(88698), // Rule ID 2647 // |
| 26704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26705 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26706 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26708 | // MIs[0] sbase |
| 26709 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26710 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26711 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26712 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 26713 | // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26716 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26719 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26720 | GIR_RootConstrainSelectedInstOperands, |
| 26721 | // GIR_Coverage, 2647, |
| 26722 | GIR_EraseRootFromParent_Done, |
| 26723 | // Label 1476: @88698 |
| 26724 | GIM_Try, /*On fail goto*//*Label 1477*/ GIMT_Encode4(88748), // Rule ID 2618 // |
| 26725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26726 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26727 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26729 | // MIs[0] sbase |
| 26730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26731 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26732 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26733 | // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 26735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26736 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26740 | GIR_RootConstrainSelectedInstOperands, |
| 26741 | // GIR_Coverage, 2618, |
| 26742 | GIR_EraseRootFromParent_Done, |
| 26743 | // Label 1477: @88748 |
| 26744 | GIM_Try, /*On fail goto*//*Label 1478*/ GIMT_Encode4(88798), // Rule ID 2652 // |
| 26745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 26746 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26749 | // MIs[0] sbase |
| 26750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26751 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26752 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26753 | // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 26755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26756 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26760 | GIR_RootConstrainSelectedInstOperands, |
| 26761 | // GIR_Coverage, 2652, |
| 26762 | GIR_EraseRootFromParent_Done, |
| 26763 | // Label 1478: @88798 |
| 26764 | GIM_Try, /*On fail goto*//*Label 1479*/ GIMT_Encode4(88845), // Rule ID 2624 // |
| 26765 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26766 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26768 | // MIs[0] sbase |
| 26769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26771 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26772 | // (ld:{ *:[v2i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26775 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26778 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26779 | GIR_RootConstrainSelectedInstOperands, |
| 26780 | // GIR_Coverage, 2624, |
| 26781 | GIR_EraseRootFromParent_Done, |
| 26782 | // Label 1479: @88845 |
| 26783 | GIM_Try, /*On fail goto*//*Label 1480*/ GIMT_Encode4(88892), // Rule ID 2658 // |
| 26784 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 26785 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 26787 | // MIs[0] sbase |
| 26788 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 26789 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 26790 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 26791 | // (ld:{ *:[v2f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v2f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 26792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 26793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 26794 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 26795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26798 | GIR_RootConstrainSelectedInstOperands, |
| 26799 | // GIR_Coverage, 2658, |
| 26800 | GIR_EraseRootFromParent_Done, |
| 26801 | // Label 1480: @88892 |
| 26802 | GIM_Try, /*On fail goto*//*Label 1481*/ GIMT_Encode4(88955), // Rule ID 6206 // |
| 26803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 26804 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26805 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26807 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 26809 | // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 26810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 26811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 26812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 26813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26818 | GIR_RootConstrainSelectedInstOperands, |
| 26819 | // GIR_Coverage, 6206, |
| 26820 | GIR_EraseRootFromParent_Done, |
| 26821 | // Label 1481: @88955 |
| 26822 | GIM_Try, /*On fail goto*//*Label 1482*/ GIMT_Encode4(89018), // Rule ID 6208 // |
| 26823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 26824 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26825 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 26829 | // (ld:{ *:[v2i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 26830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 26831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 26832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 26833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 26834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26838 | GIR_RootConstrainSelectedInstOperands, |
| 26839 | // GIR_Coverage, 6208, |
| 26840 | GIR_EraseRootFromParent_Done, |
| 26841 | // Label 1482: @89018 |
| 26842 | GIM_Try, /*On fail goto*//*Label 1483*/ GIMT_Encode4(89078), // Rule ID 3942 // |
| 26843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 26844 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26847 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26848 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 26849 | // (ld:{ *:[v2i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 26851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 26853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 26854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26857 | GIR_RootConstrainSelectedInstOperands, |
| 26858 | // GIR_Coverage, 3942, |
| 26859 | GIR_EraseRootFromParent_Done, |
| 26860 | // Label 1483: @89078 |
| 26861 | GIM_Try, /*On fail goto*//*Label 1484*/ GIMT_Encode4(89138), // Rule ID 3948 // |
| 26862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 26863 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26864 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26866 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 26868 | // (ld:{ *:[v2f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 26869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 26870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 26872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 26873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 26874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26875 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26876 | GIR_RootConstrainSelectedInstOperands, |
| 26877 | // GIR_Coverage, 3948, |
| 26878 | GIR_EraseRootFromParent_Done, |
| 26879 | // Label 1484: @89138 |
| 26880 | GIM_Try, /*On fail goto*//*Label 1485*/ GIMT_Encode4(89193), // Rule ID 3941 // |
| 26881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 26882 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26883 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 26887 | // (ld:{ *:[v2i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 26888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 26889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 26891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26893 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26894 | GIR_RootConstrainSelectedInstOperands, |
| 26895 | // GIR_Coverage, 3941, |
| 26896 | GIR_EraseRootFromParent_Done, |
| 26897 | // Label 1485: @89193 |
| 26898 | GIM_Try, /*On fail goto*//*Label 1486*/ GIMT_Encode4(89248), // Rule ID 3947 // |
| 26899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 26900 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26901 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26903 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 26905 | // (ld:{ *:[v2f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 26906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 26907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 26909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26912 | GIR_RootConstrainSelectedInstOperands, |
| 26913 | // GIR_Coverage, 3947, |
| 26914 | GIR_EraseRootFromParent_Done, |
| 26915 | // Label 1486: @89248 |
| 26916 | GIM_Try, /*On fail goto*//*Label 1487*/ GIMT_Encode4(89303), // Rule ID 3940 // |
| 26917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 26918 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26919 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 26923 | // (ld:{ *:[v2i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 26924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 26925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 26927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26930 | GIR_RootConstrainSelectedInstOperands, |
| 26931 | // GIR_Coverage, 3940, |
| 26932 | GIR_EraseRootFromParent_Done, |
| 26933 | // Label 1487: @89303 |
| 26934 | GIM_Try, /*On fail goto*//*Label 1488*/ GIMT_Encode4(89358), // Rule ID 3946 // |
| 26935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 26936 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 26937 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26939 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 26941 | // (ld:{ *:[v2f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 26942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 26943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 26944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 26945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 26946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26948 | GIR_RootConstrainSelectedInstOperands, |
| 26949 | // GIR_Coverage, 3946, |
| 26950 | GIR_EraseRootFromParent_Done, |
| 26951 | // Label 1488: @89358 |
| 26952 | GIM_Try, /*On fail goto*//*Label 1489*/ GIMT_Encode4(89428), // Rule ID 4174 // |
| 26953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 26954 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 26955 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26957 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26958 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 26959 | // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 26960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 26961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 26962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 26963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 26964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 26965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 26966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26969 | GIR_RootConstrainSelectedInstOperands, |
| 26970 | // GIR_Coverage, 4174, |
| 26971 | GIR_EraseRootFromParent_Done, |
| 26972 | // Label 1489: @89428 |
| 26973 | GIM_Try, /*On fail goto*//*Label 1490*/ GIMT_Encode4(89495), // Rule ID 4176 // |
| 26974 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 26975 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 26979 | // (ld:{ *:[v2i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 26980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 26981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 26982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 26983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 26984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 26985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 26986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 26988 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 26989 | GIR_RootConstrainSelectedInstOperands, |
| 26990 | // GIR_Coverage, 4176, |
| 26991 | GIR_EraseRootFromParent_Done, |
| 26992 | // Label 1490: @89495 |
| 26993 | GIM_Try, /*On fail goto*//*Label 1491*/ GIMT_Encode4(89565), // Rule ID 4178 // |
| 26994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 26995 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 26996 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 26997 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 26998 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 26999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 27000 | // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 27002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 27004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 27006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 27007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27009 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27010 | GIR_RootConstrainSelectedInstOperands, |
| 27011 | // GIR_Coverage, 4178, |
| 27012 | GIR_EraseRootFromParent_Done, |
| 27013 | // Label 1491: @89565 |
| 27014 | GIM_Try, /*On fail goto*//*Label 1492*/ GIMT_Encode4(89632), // Rule ID 4180 // |
| 27015 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27016 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27018 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 27020 | // (ld:{ *:[v2f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v2f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 27022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 27024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 27026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 27027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27030 | GIR_RootConstrainSelectedInstOperands, |
| 27031 | // GIR_Coverage, 4180, |
| 27032 | GIR_EraseRootFromParent_Done, |
| 27033 | // Label 1492: @89632 |
| 27034 | GIM_Try, /*On fail goto*//*Label 1493*/ GIMT_Encode4(89700), // Rule ID 6205 // |
| 27035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 27036 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 27037 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27039 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27040 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 27041 | // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 27042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 27043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 27045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 27047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 27048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27050 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27051 | GIR_RootConstrainSelectedInstOperands, |
| 27052 | // GIR_Coverage, 6205, |
| 27053 | GIR_EraseRootFromParent_Done, |
| 27054 | // Label 1493: @89700 |
| 27055 | GIM_Try, /*On fail goto*//*Label 1494*/ GIMT_Encode4(89768), // Rule ID 6207 // |
| 27056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 27057 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 27058 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27060 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27061 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 27062 | // (ld:{ *:[v2i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 27063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 27064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 27066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 27068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 27069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27072 | GIR_RootConstrainSelectedInstOperands, |
| 27073 | // GIR_Coverage, 6207, |
| 27074 | GIR_EraseRootFromParent_Done, |
| 27075 | // Label 1494: @89768 |
| 27076 | GIM_Try, /*On fail goto*//*Label 1495*/ GIMT_Encode4(89832), // Rule ID 7551 // |
| 27077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 27078 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27079 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27080 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27082 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 27084 | // (AMDGPUld_glue:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 27085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 27086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 27089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 27090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27091 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27092 | GIR_RootConstrainSelectedInstOperands, |
| 27093 | // GIR_Coverage, 7551, |
| 27094 | GIR_EraseRootFromParent_Done, |
| 27095 | // Label 1495: @89832 |
| 27096 | GIM_Try, /*On fail goto*//*Label 1496*/ GIMT_Encode4(89896), // Rule ID 7555 // |
| 27097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 27098 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27099 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27100 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27102 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27103 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 27104 | // (AMDGPUld_glue:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 27105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 27106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 27109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 27110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27111 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27112 | GIR_RootConstrainSelectedInstOperands, |
| 27113 | // GIR_Coverage, 7555, |
| 27114 | GIR_EraseRootFromParent_Done, |
| 27115 | // Label 1496: @89896 |
| 27116 | GIM_Try, /*On fail goto*//*Label 1497*/ GIMT_Encode4(89961), // Rule ID 4173 // |
| 27117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 27118 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27119 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27121 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27122 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 27123 | // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 27125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27132 | GIR_RootConstrainSelectedInstOperands, |
| 27133 | // GIR_Coverage, 4173, |
| 27134 | GIR_EraseRootFromParent_Done, |
| 27135 | // Label 1497: @89961 |
| 27136 | GIM_Try, /*On fail goto*//*Label 1498*/ GIMT_Encode4(90023), // Rule ID 4175 // |
| 27137 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27138 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27140 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 27142 | // (ld:{ *:[v2i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 27144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27151 | GIR_RootConstrainSelectedInstOperands, |
| 27152 | // GIR_Coverage, 4175, |
| 27153 | GIR_EraseRootFromParent_Done, |
| 27154 | // Label 1498: @90023 |
| 27155 | GIM_Try, /*On fail goto*//*Label 1499*/ GIMT_Encode4(90088), // Rule ID 4177 // |
| 27156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 27157 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27158 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27160 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 27162 | // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 27164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27170 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27171 | GIR_RootConstrainSelectedInstOperands, |
| 27172 | // GIR_Coverage, 4177, |
| 27173 | GIR_EraseRootFromParent_Done, |
| 27174 | // Label 1499: @90088 |
| 27175 | GIM_Try, /*On fail goto*//*Label 1500*/ GIMT_Encode4(90150), // Rule ID 4179 // |
| 27176 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27177 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 27181 | // (ld:{ *:[v2f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 27182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 27183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 27184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 27185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27189 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27190 | GIR_RootConstrainSelectedInstOperands, |
| 27191 | // GIR_Coverage, 4179, |
| 27192 | GIR_EraseRootFromParent_Done, |
| 27193 | // Label 1500: @90150 |
| 27194 | GIM_Try, /*On fail goto*//*Label 1501*/ GIMT_Encode4(90210), // Rule ID 7553 // |
| 27195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 27196 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27197 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 27201 | // (ld:{ *:[v2i32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[v2i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 27202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 27203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 27206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 27207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27208 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27209 | GIR_RootConstrainSelectedInstOperands, |
| 27210 | // GIR_Coverage, 7553, |
| 27211 | GIR_EraseRootFromParent_Done, |
| 27212 | // Label 1501: @90210 |
| 27213 | GIM_Try, /*On fail goto*//*Label 1502*/ GIMT_Encode4(90270), // Rule ID 7557 // |
| 27214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 27215 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27216 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27218 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27219 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 27220 | // (ld:{ *:[v2f32] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[v2f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 27221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 27222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 27225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 27226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27228 | GIR_RootConstrainSelectedInstOperands, |
| 27229 | // GIR_Coverage, 7557, |
| 27230 | GIR_EraseRootFromParent_Done, |
| 27231 | // Label 1502: @90270 |
| 27232 | GIM_Try, /*On fail goto*//*Label 1503*/ GIMT_Encode4(90332), // Rule ID 3493 // |
| 27233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 27234 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 27239 | // (ld:{ *:[v2i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 27241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 27243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 27244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27246 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27247 | GIR_RootConstrainSelectedInstOperands, |
| 27248 | // GIR_Coverage, 3493, |
| 27249 | GIR_EraseRootFromParent_Done, |
| 27250 | // Label 1503: @90332 |
| 27251 | GIM_Try, /*On fail goto*//*Label 1504*/ GIMT_Encode4(90394), // Rule ID 3497 // |
| 27252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 27253 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27254 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27256 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 27258 | // (ld:{ *:[v2f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v2f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 27260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 27262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 27263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27266 | GIR_RootConstrainSelectedInstOperands, |
| 27267 | // GIR_Coverage, 3497, |
| 27268 | GIR_EraseRootFromParent_Done, |
| 27269 | // Label 1504: @90394 |
| 27270 | GIM_Try, /*On fail goto*//*Label 1505*/ GIMT_Encode4(90451), // Rule ID 3492 // |
| 27271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 27272 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27273 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27275 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 27277 | // (ld:{ *:[v2i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 27278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 27279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 27281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27283 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27284 | GIR_RootConstrainSelectedInstOperands, |
| 27285 | // GIR_Coverage, 3492, |
| 27286 | GIR_EraseRootFromParent_Done, |
| 27287 | // Label 1505: @90451 |
| 27288 | GIM_Try, /*On fail goto*//*Label 1506*/ GIMT_Encode4(90508), // Rule ID 3496 // |
| 27289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 27290 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27291 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27293 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27294 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 27295 | // (ld:{ *:[v2f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 27296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 27297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 27299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27302 | GIR_RootConstrainSelectedInstOperands, |
| 27303 | // GIR_Coverage, 3496, |
| 27304 | GIR_EraseRootFromParent_Done, |
| 27305 | // Label 1506: @90508 |
| 27306 | GIM_Try, /*On fail goto*//*Label 1507*/ GIMT_Encode4(90566), // Rule ID 3252 // |
| 27307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 27308 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27309 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27311 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27312 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 27313 | // (ld:{ *:[v2i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 27314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 27315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 27317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27319 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27320 | GIR_RootConstrainSelectedInstOperands, |
| 27321 | // GIR_Coverage, 3252, |
| 27322 | GIR_EraseRootFromParent_Done, |
| 27323 | // Label 1507: @90566 |
| 27324 | GIM_Try, /*On fail goto*//*Label 1508*/ GIMT_Encode4(90624), // Rule ID 3254 // |
| 27325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 27326 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 27327 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 27329 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27330 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 27331 | // (ld:{ *:[v2f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[v2f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 27332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 27333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 27335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27338 | GIR_RootConstrainSelectedInstOperands, |
| 27339 | // GIR_Coverage, 3254, |
| 27340 | GIR_EraseRootFromParent_Done, |
| 27341 | // Label 1508: @90624 |
| 27342 | GIM_Reject, |
| 27343 | // Label 860: @90625 |
| 27344 | GIM_Try, /*On fail goto*//*Label 1509*/ GIMT_Encode4(90692), // Rule ID 2807 // |
| 27345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27346 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27347 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27349 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27350 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27351 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27352 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27353 | // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27360 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27361 | GIR_RootConstrainSelectedInstOperands, |
| 27362 | // GIR_Coverage, 2807, |
| 27363 | GIR_EraseRootFromParent_Done, |
| 27364 | // Label 1509: @90692 |
| 27365 | GIM_Try, /*On fail goto*//*Label 1510*/ GIMT_Encode4(90759), // Rule ID 2824 // |
| 27366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27367 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27368 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27370 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27371 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27372 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27374 | // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27381 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27382 | GIR_RootConstrainSelectedInstOperands, |
| 27383 | // GIR_Coverage, 2824, |
| 27384 | GIR_EraseRootFromParent_Done, |
| 27385 | // Label 1510: @90759 |
| 27386 | GIM_Try, /*On fail goto*//*Label 1511*/ GIMT_Encode4(90822), // Rule ID 2812 // |
| 27387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27388 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27389 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27391 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27392 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27394 | // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 27396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27402 | GIR_RootConstrainSelectedInstOperands, |
| 27403 | // GIR_Coverage, 2812, |
| 27404 | GIR_EraseRootFromParent_Done, |
| 27405 | // Label 1511: @90822 |
| 27406 | GIM_Try, /*On fail goto*//*Label 1512*/ GIMT_Encode4(90885), // Rule ID 2829 // |
| 27407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27408 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27409 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27411 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27412 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27414 | // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 27416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27422 | GIR_RootConstrainSelectedInstOperands, |
| 27423 | // GIR_Coverage, 2829, |
| 27424 | GIR_EraseRootFromParent_Done, |
| 27425 | // Label 1512: @90885 |
| 27426 | GIM_Try, /*On fail goto*//*Label 1513*/ GIMT_Encode4(90948), // Rule ID 2818 // |
| 27427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 27428 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27429 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27432 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27434 | // (ld:{ *:[v2i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27442 | GIR_RootConstrainSelectedInstOperands, |
| 27443 | // GIR_Coverage, 2818, |
| 27444 | GIR_EraseRootFromParent_Done, |
| 27445 | // Label 1513: @90948 |
| 27446 | GIM_Try, /*On fail goto*//*Label 1514*/ GIMT_Encode4(91011), // Rule ID 2835 // |
| 27447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 27448 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27449 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27451 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27452 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 27454 | // (ld:{ *:[v2f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 27460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27461 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27462 | GIR_RootConstrainSelectedInstOperands, |
| 27463 | // GIR_Coverage, 2835, |
| 27464 | GIR_EraseRootFromParent_Done, |
| 27465 | // Label 1514: @91011 |
| 27466 | GIM_Try, /*On fail goto*//*Label 1515*/ GIMT_Encode4(91073), // Rule ID 2803 // |
| 27467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 27468 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27469 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27472 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27473 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27475 | // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 27477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27482 | GIR_RootConstrainSelectedInstOperands, |
| 27483 | // GIR_Coverage, 2803, |
| 27484 | GIR_EraseRootFromParent_Done, |
| 27485 | // Label 1515: @91073 |
| 27486 | GIM_Try, /*On fail goto*//*Label 1516*/ GIMT_Encode4(91135), // Rule ID 2804 // |
| 27487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 27488 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27489 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27491 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27492 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27493 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 27495 | // (ld:{ *:[v2i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 27497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27502 | GIR_RootConstrainSelectedInstOperands, |
| 27503 | // GIR_Coverage, 2804, |
| 27504 | GIR_EraseRootFromParent_Done, |
| 27505 | // Label 1516: @91135 |
| 27506 | GIM_Try, /*On fail goto*//*Label 1517*/ GIMT_Encode4(91197), // Rule ID 2805 // |
| 27507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 27508 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27509 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27512 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27513 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27515 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 27517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27522 | GIR_RootConstrainSelectedInstOperands, |
| 27523 | // GIR_Coverage, 2805, |
| 27524 | GIR_EraseRootFromParent_Done, |
| 27525 | // Label 1517: @91197 |
| 27526 | GIM_Try, /*On fail goto*//*Label 1518*/ GIMT_Encode4(91262), // Rule ID 2806 // |
| 27527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27528 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27529 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27532 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27533 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27535 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27543 | GIR_RootConstrainSelectedInstOperands, |
| 27544 | // GIR_Coverage, 2806, |
| 27545 | GIR_EraseRootFromParent_Done, |
| 27546 | // Label 1518: @91262 |
| 27547 | GIM_Try, /*On fail goto*//*Label 1519*/ GIMT_Encode4(91324), // Rule ID 2820 // |
| 27548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 27549 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27550 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27552 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27553 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27554 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27555 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27556 | // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 27558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27562 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27563 | GIR_RootConstrainSelectedInstOperands, |
| 27564 | // GIR_Coverage, 2820, |
| 27565 | GIR_EraseRootFromParent_Done, |
| 27566 | // Label 1519: @91324 |
| 27567 | GIM_Try, /*On fail goto*//*Label 1520*/ GIMT_Encode4(91386), // Rule ID 2821 // |
| 27568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 27569 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27570 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27572 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27573 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27574 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 27576 | // (ld:{ *:[v2f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 27578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27582 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27583 | GIR_RootConstrainSelectedInstOperands, |
| 27584 | // GIR_Coverage, 2821, |
| 27585 | GIR_EraseRootFromParent_Done, |
| 27586 | // Label 1520: @91386 |
| 27587 | GIM_Try, /*On fail goto*//*Label 1521*/ GIMT_Encode4(91448), // Rule ID 2822 // |
| 27588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 27589 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27590 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27592 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27593 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27594 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27596 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 27598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27602 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27603 | GIR_RootConstrainSelectedInstOperands, |
| 27604 | // GIR_Coverage, 2822, |
| 27605 | GIR_EraseRootFromParent_Done, |
| 27606 | // Label 1521: @91448 |
| 27607 | GIM_Try, /*On fail goto*//*Label 1522*/ GIMT_Encode4(91513), // Rule ID 2823 // |
| 27608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27609 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27610 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27612 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27613 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27614 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 27615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27616 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27623 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27624 | GIR_RootConstrainSelectedInstOperands, |
| 27625 | // GIR_Coverage, 2823, |
| 27626 | GIR_EraseRootFromParent_Done, |
| 27627 | // Label 1522: @91513 |
| 27628 | GIM_Try, /*On fail goto*//*Label 1523*/ GIMT_Encode4(91571), // Rule ID 2809 // |
| 27629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 27630 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27631 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27633 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27634 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27636 | // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 27638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27642 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27643 | GIR_RootConstrainSelectedInstOperands, |
| 27644 | // GIR_Coverage, 2809, |
| 27645 | GIR_EraseRootFromParent_Done, |
| 27646 | // Label 1523: @91571 |
| 27647 | GIM_Try, /*On fail goto*//*Label 1524*/ GIMT_Encode4(91629), // Rule ID 2810 // |
| 27648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 27649 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27650 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27651 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27652 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27653 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27654 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27655 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 27657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27662 | GIR_RootConstrainSelectedInstOperands, |
| 27663 | // GIR_Coverage, 2810, |
| 27664 | GIR_EraseRootFromParent_Done, |
| 27665 | // Label 1524: @91629 |
| 27666 | GIM_Try, /*On fail goto*//*Label 1525*/ GIMT_Encode4(91690), // Rule ID 2811 // |
| 27667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27668 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27669 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27671 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27672 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27674 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 27676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27681 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27682 | GIR_RootConstrainSelectedInstOperands, |
| 27683 | // GIR_Coverage, 2811, |
| 27684 | GIR_EraseRootFromParent_Done, |
| 27685 | // Label 1525: @91690 |
| 27686 | GIM_Try, /*On fail goto*//*Label 1526*/ GIMT_Encode4(91748), // Rule ID 2826 // |
| 27687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 27688 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27689 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27692 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27693 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27694 | // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 27696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27700 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27701 | GIR_RootConstrainSelectedInstOperands, |
| 27702 | // GIR_Coverage, 2826, |
| 27703 | GIR_EraseRootFromParent_Done, |
| 27704 | // Label 1526: @91748 |
| 27705 | GIM_Try, /*On fail goto*//*Label 1527*/ GIMT_Encode4(91806), // Rule ID 2827 // |
| 27706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 27707 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27708 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27710 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27711 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27713 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 27715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27719 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27720 | GIR_RootConstrainSelectedInstOperands, |
| 27721 | // GIR_Coverage, 2827, |
| 27722 | GIR_EraseRootFromParent_Done, |
| 27723 | // Label 1527: @91806 |
| 27724 | GIM_Try, /*On fail goto*//*Label 1528*/ GIMT_Encode4(91867), // Rule ID 2828 // |
| 27725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 27726 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27727 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27729 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27730 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27732 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 27734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27740 | GIR_RootConstrainSelectedInstOperands, |
| 27741 | // GIR_Coverage, 2828, |
| 27742 | GIR_EraseRootFromParent_Done, |
| 27743 | // Label 1528: @91867 |
| 27744 | GIM_Try, /*On fail goto*//*Label 1529*/ GIMT_Encode4(91935), // Rule ID 7739 // |
| 27745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 27746 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27747 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27748 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27749 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 27751 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27752 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 27753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 27754 | // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 27755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 27756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27760 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27761 | GIR_RootConstrainSelectedInstOperands, |
| 27762 | // GIR_Coverage, 7739, |
| 27763 | GIR_EraseRootFromParent_Done, |
| 27764 | // Label 1529: @91935 |
| 27765 | GIM_Try, /*On fail goto*//*Label 1530*/ GIMT_Encode4(92003), // Rule ID 7743 // |
| 27766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 27767 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27768 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27769 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 27772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27773 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 27774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 27775 | // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 27776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 27777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27781 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27782 | GIR_RootConstrainSelectedInstOperands, |
| 27783 | // GIR_Coverage, 7743, |
| 27784 | GIR_EraseRootFromParent_Done, |
| 27785 | // Label 1530: @92003 |
| 27786 | GIM_Try, /*On fail goto*//*Label 1531*/ GIMT_Encode4(92066), // Rule ID 7663 // |
| 27787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 27788 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27790 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 27791 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 27793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 27795 | // (AMDGPUld_glue:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 27796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 27797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27802 | GIR_RootConstrainSelectedInstOperands, |
| 27803 | // GIR_Coverage, 7663, |
| 27804 | GIR_EraseRootFromParent_Done, |
| 27805 | // Label 1531: @92066 |
| 27806 | GIM_Try, /*On fail goto*//*Label 1532*/ GIMT_Encode4(92129), // Rule ID 7667 // |
| 27807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 27808 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27809 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27810 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 27811 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 27813 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 27815 | // (AMDGPUld_glue:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 27816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 27817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27821 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27822 | GIR_RootConstrainSelectedInstOperands, |
| 27823 | // GIR_Coverage, 7667, |
| 27824 | GIR_EraseRootFromParent_Done, |
| 27825 | // Label 1532: @92129 |
| 27826 | GIM_Try, /*On fail goto*//*Label 1533*/ GIMT_Encode4(92184), // Rule ID 2814 // |
| 27827 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27833 | // (ld:{ *:[v2i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 27835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27840 | GIR_RootConstrainSelectedInstOperands, |
| 27841 | // GIR_Coverage, 2814, |
| 27842 | GIR_EraseRootFromParent_Done, |
| 27843 | // Label 1533: @92184 |
| 27844 | GIM_Try, /*On fail goto*//*Label 1534*/ GIMT_Encode4(92242), // Rule ID 2815 // |
| 27845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 27846 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27847 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27849 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 27852 | // (ld:{ *:[v2i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 27854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27859 | GIR_RootConstrainSelectedInstOperands, |
| 27860 | // GIR_Coverage, 2815, |
| 27861 | GIR_EraseRootFromParent_Done, |
| 27862 | // Label 1534: @92242 |
| 27863 | GIM_Try, /*On fail goto*//*Label 1535*/ GIMT_Encode4(92300), // Rule ID 2816 // |
| 27864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 27865 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27866 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27869 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27871 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 27873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27877 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27878 | GIR_RootConstrainSelectedInstOperands, |
| 27879 | // GIR_Coverage, 2816, |
| 27880 | GIR_EraseRootFromParent_Done, |
| 27881 | // Label 1535: @92300 |
| 27882 | GIM_Try, /*On fail goto*//*Label 1536*/ GIMT_Encode4(92361), // Rule ID 2817 // |
| 27883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 27884 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27885 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27890 | // (ld:{ *:[v2i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27898 | GIR_RootConstrainSelectedInstOperands, |
| 27899 | // GIR_Coverage, 2817, |
| 27900 | GIR_EraseRootFromParent_Done, |
| 27901 | // Label 1536: @92361 |
| 27902 | GIM_Try, /*On fail goto*//*Label 1537*/ GIMT_Encode4(92416), // Rule ID 2831 // |
| 27903 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27904 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 27909 | // (ld:{ *:[v2f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 27911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27915 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27916 | GIR_RootConstrainSelectedInstOperands, |
| 27917 | // GIR_Coverage, 2831, |
| 27918 | GIR_EraseRootFromParent_Done, |
| 27919 | // Label 1537: @92416 |
| 27920 | GIM_Try, /*On fail goto*//*Label 1538*/ GIMT_Encode4(92474), // Rule ID 2832 // |
| 27921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 27922 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27923 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27926 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27927 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 27928 | // (ld:{ *:[v2f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 27929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 27930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27934 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27935 | GIR_RootConstrainSelectedInstOperands, |
| 27936 | // GIR_Coverage, 2832, |
| 27937 | GIR_EraseRootFromParent_Done, |
| 27938 | // Label 1538: @92474 |
| 27939 | GIM_Try, /*On fail goto*//*Label 1539*/ GIMT_Encode4(92532), // Rule ID 2833 // |
| 27940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 27941 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27944 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27945 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27947 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 27948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 27949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27954 | GIR_RootConstrainSelectedInstOperands, |
| 27955 | // GIR_Coverage, 2833, |
| 27956 | GIR_EraseRootFromParent_Done, |
| 27957 | // Label 1539: @92532 |
| 27958 | GIM_Try, /*On fail goto*//*Label 1540*/ GIMT_Encode4(92593), // Rule ID 2834 // |
| 27959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 27960 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 27961 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 27963 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27964 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 27965 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 27966 | // (ld:{ *:[v2f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v2f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 27967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 27968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 27969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 27970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 27971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27974 | GIR_RootConstrainSelectedInstOperands, |
| 27975 | // GIR_Coverage, 2834, |
| 27976 | GIR_EraseRootFromParent_Done, |
| 27977 | // Label 1540: @92593 |
| 27978 | GIM_Try, /*On fail goto*//*Label 1541*/ GIMT_Encode4(92657), // Rule ID 7740 // |
| 27979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 27980 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27981 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 27982 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 27983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 27984 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 27985 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 27986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 27987 | // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 27988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 27989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 27990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 27991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 27992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 27993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 27994 | GIR_RootConstrainSelectedInstOperands, |
| 27995 | // GIR_Coverage, 7740, |
| 27996 | GIR_EraseRootFromParent_Done, |
| 27997 | // Label 1541: @92657 |
| 27998 | GIM_Try, /*On fail goto*//*Label 1542*/ GIMT_Encode4(92721), // Rule ID 7744 // |
| 27999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 28000 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28001 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28002 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28005 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 28006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 28007 | // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 28008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 28009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28013 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28014 | GIR_RootConstrainSelectedInstOperands, |
| 28015 | // GIR_Coverage, 7744, |
| 28016 | GIR_EraseRootFromParent_Done, |
| 28017 | // Label 1542: @92721 |
| 28018 | GIM_Try, /*On fail goto*//*Label 1543*/ GIMT_Encode4(92780), // Rule ID 7664 // |
| 28019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 28020 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28021 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 28022 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28024 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 28026 | // (ld:{ *:[v2i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 28027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 28028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28033 | GIR_RootConstrainSelectedInstOperands, |
| 28034 | // GIR_Coverage, 7664, |
| 28035 | GIR_EraseRootFromParent_Done, |
| 28036 | // Label 1543: @92780 |
| 28037 | GIM_Try, /*On fail goto*//*Label 1544*/ GIMT_Encode4(92839), // Rule ID 7668 // |
| 28038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 28039 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28040 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 28041 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 28045 | // (ld:{ *:[v2f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 28046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 28047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28052 | GIR_RootConstrainSelectedInstOperands, |
| 28053 | // GIR_Coverage, 7668, |
| 28054 | GIR_EraseRootFromParent_Done, |
| 28055 | // Label 1544: @92839 |
| 28056 | GIM_Try, /*On fail goto*//*Label 1545*/ GIMT_Encode4(92893), // Rule ID 2808 // |
| 28057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28058 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28059 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28061 | // MIs[0] sbase |
| 28062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28063 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28064 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28065 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28066 | // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 28068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28069 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28073 | GIR_RootConstrainSelectedInstOperands, |
| 28074 | // GIR_Coverage, 2808, |
| 28075 | GIR_EraseRootFromParent_Done, |
| 28076 | // Label 1545: @92893 |
| 28077 | GIM_Try, /*On fail goto*//*Label 1546*/ GIMT_Encode4(92947), // Rule ID 2825 // |
| 28078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28079 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28080 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28082 | // MIs[0] sbase |
| 28083 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28084 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28085 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28086 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28087 | // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 28089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28090 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28094 | GIR_RootConstrainSelectedInstOperands, |
| 28095 | // GIR_Coverage, 2825, |
| 28096 | GIR_EraseRootFromParent_Done, |
| 28097 | // Label 1546: @92947 |
| 28098 | GIM_Try, /*On fail goto*//*Label 1547*/ GIMT_Encode4(92997), // Rule ID 2813 // |
| 28099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28100 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28101 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28103 | // MIs[0] sbase |
| 28104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28105 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28106 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28107 | // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 28109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28110 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28113 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28114 | GIR_RootConstrainSelectedInstOperands, |
| 28115 | // GIR_Coverage, 2813, |
| 28116 | GIR_EraseRootFromParent_Done, |
| 28117 | // Label 1547: @92997 |
| 28118 | GIM_Try, /*On fail goto*//*Label 1548*/ GIMT_Encode4(93047), // Rule ID 2830 // |
| 28119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28120 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28121 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28123 | // MIs[0] sbase |
| 28124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28125 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28126 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28127 | // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 28129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28130 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28134 | GIR_RootConstrainSelectedInstOperands, |
| 28135 | // GIR_Coverage, 2830, |
| 28136 | GIR_EraseRootFromParent_Done, |
| 28137 | // Label 1548: @93047 |
| 28138 | GIM_Try, /*On fail goto*//*Label 1549*/ GIMT_Encode4(93094), // Rule ID 2819 // |
| 28139 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28142 | // MIs[0] sbase |
| 28143 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28144 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28145 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28146 | // (ld:{ *:[v2i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 28148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28149 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28153 | GIR_RootConstrainSelectedInstOperands, |
| 28154 | // GIR_Coverage, 2819, |
| 28155 | GIR_EraseRootFromParent_Done, |
| 28156 | // Label 1549: @93094 |
| 28157 | GIM_Try, /*On fail goto*//*Label 1550*/ GIMT_Encode4(93141), // Rule ID 2836 // |
| 28158 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28159 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 28161 | // MIs[0] sbase |
| 28162 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 28163 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 28164 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28165 | // (ld:{ *:[v2f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v2f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 28167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28168 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 28169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28172 | GIR_RootConstrainSelectedInstOperands, |
| 28173 | // GIR_Coverage, 2836, |
| 28174 | GIR_EraseRootFromParent_Done, |
| 28175 | // Label 1550: @93141 |
| 28176 | GIM_Try, /*On fail goto*//*Label 1551*/ GIMT_Encode4(93201), // Rule ID 4005 // |
| 28177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 28178 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28179 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28181 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 28183 | // (ld:{ *:[v2i64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 28185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 28188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28190 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28191 | GIR_RootConstrainSelectedInstOperands, |
| 28192 | // GIR_Coverage, 4005, |
| 28193 | GIR_EraseRootFromParent_Done, |
| 28194 | // Label 1551: @93201 |
| 28195 | GIM_Try, /*On fail goto*//*Label 1552*/ GIMT_Encode4(93261), // Rule ID 4011 // |
| 28196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 28197 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28200 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 28202 | // (ld:{ *:[v2f64] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 28204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 28207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28210 | GIR_RootConstrainSelectedInstOperands, |
| 28211 | // GIR_Coverage, 4011, |
| 28212 | GIR_EraseRootFromParent_Done, |
| 28213 | // Label 1552: @93261 |
| 28214 | GIM_Try, /*On fail goto*//*Label 1553*/ GIMT_Encode4(93316), // Rule ID 4004 // |
| 28215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 28216 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28217 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28219 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 28221 | // (ld:{ *:[v2i64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 28222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 28223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 28225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28228 | GIR_RootConstrainSelectedInstOperands, |
| 28229 | // GIR_Coverage, 4004, |
| 28230 | GIR_EraseRootFromParent_Done, |
| 28231 | // Label 1553: @93316 |
| 28232 | GIM_Try, /*On fail goto*//*Label 1554*/ GIMT_Encode4(93371), // Rule ID 4010 // |
| 28233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 28234 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 28239 | // (ld:{ *:[v2f64] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 28240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 28241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 28243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28245 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28246 | GIR_RootConstrainSelectedInstOperands, |
| 28247 | // GIR_Coverage, 4010, |
| 28248 | GIR_EraseRootFromParent_Done, |
| 28249 | // Label 1554: @93371 |
| 28250 | GIM_Try, /*On fail goto*//*Label 1555*/ GIMT_Encode4(93426), // Rule ID 4003 // |
| 28251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 28252 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28253 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28255 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28256 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 28257 | // (ld:{ *:[v2i64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 28259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28263 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28264 | GIR_RootConstrainSelectedInstOperands, |
| 28265 | // GIR_Coverage, 4003, |
| 28266 | GIR_EraseRootFromParent_Done, |
| 28267 | // Label 1555: @93426 |
| 28268 | GIM_Try, /*On fail goto*//*Label 1556*/ GIMT_Encode4(93481), // Rule ID 4009 // |
| 28269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 28270 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 28271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28273 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 28275 | // (ld:{ *:[v2f64] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 28277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28281 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28282 | GIR_RootConstrainSelectedInstOperands, |
| 28283 | // GIR_Coverage, 4009, |
| 28284 | GIR_EraseRootFromParent_Done, |
| 28285 | // Label 1556: @93481 |
| 28286 | GIM_Try, /*On fail goto*//*Label 1557*/ GIMT_Encode4(93551), // Rule ID 4222 // |
| 28287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 28288 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28289 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 28293 | // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 28295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 28297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 28299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 28300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28302 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28303 | GIR_RootConstrainSelectedInstOperands, |
| 28304 | // GIR_Coverage, 4222, |
| 28305 | GIR_EraseRootFromParent_Done, |
| 28306 | // Label 1557: @93551 |
| 28307 | GIM_Try, /*On fail goto*//*Label 1558*/ GIMT_Encode4(93618), // Rule ID 4224 // |
| 28308 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28309 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28311 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28312 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 28313 | // (ld:{ *:[v2i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2i64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 28315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 28317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 28319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 28320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28323 | GIR_RootConstrainSelectedInstOperands, |
| 28324 | // GIR_Coverage, 4224, |
| 28325 | GIR_EraseRootFromParent_Done, |
| 28326 | // Label 1558: @93618 |
| 28327 | GIM_Try, /*On fail goto*//*Label 1559*/ GIMT_Encode4(93688), // Rule ID 4226 // |
| 28328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 28329 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28330 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28332 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28333 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 28334 | // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 28336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 28338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 28340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 28341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28343 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28344 | GIR_RootConstrainSelectedInstOperands, |
| 28345 | // GIR_Coverage, 4226, |
| 28346 | GIR_EraseRootFromParent_Done, |
| 28347 | // Label 1559: @93688 |
| 28348 | GIM_Try, /*On fail goto*//*Label 1560*/ GIMT_Encode4(93755), // Rule ID 4228 // |
| 28349 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28350 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 28354 | // (ld:{ *:[v2f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v2f64] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 28356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 28358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 28360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 28361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28363 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28364 | GIR_RootConstrainSelectedInstOperands, |
| 28365 | // GIR_Coverage, 4228, |
| 28366 | GIR_EraseRootFromParent_Done, |
| 28367 | // Label 1560: @93755 |
| 28368 | GIM_Try, /*On fail goto*//*Label 1561*/ GIMT_Encode4(93819), // Rule ID 7587 // |
| 28369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 28370 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28371 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28372 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28374 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28375 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 28376 | // (AMDGPUld_glue:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 28377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 28378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 28381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 28382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28384 | GIR_RootConstrainSelectedInstOperands, |
| 28385 | // GIR_Coverage, 7587, |
| 28386 | GIR_EraseRootFromParent_Done, |
| 28387 | // Label 1561: @93819 |
| 28388 | GIM_Try, /*On fail goto*//*Label 1562*/ GIMT_Encode4(93883), // Rule ID 7591 // |
| 28389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 28390 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28391 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28392 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28394 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28395 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 28396 | // (AMDGPUld_glue:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 28397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 28398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 28401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 28402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28403 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28404 | GIR_RootConstrainSelectedInstOperands, |
| 28405 | // GIR_Coverage, 7591, |
| 28406 | GIR_EraseRootFromParent_Done, |
| 28407 | // Label 1562: @93883 |
| 28408 | GIM_Try, /*On fail goto*//*Label 1563*/ GIMT_Encode4(93948), // Rule ID 4221 // |
| 28409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 28410 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28411 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28413 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 28415 | // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 28417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28424 | GIR_RootConstrainSelectedInstOperands, |
| 28425 | // GIR_Coverage, 4221, |
| 28426 | GIR_EraseRootFromParent_Done, |
| 28427 | // Label 1563: @93948 |
| 28428 | GIM_Try, /*On fail goto*//*Label 1564*/ GIMT_Encode4(94010), // Rule ID 4223 // |
| 28429 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 28434 | // (ld:{ *:[v2i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 28436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28443 | GIR_RootConstrainSelectedInstOperands, |
| 28444 | // GIR_Coverage, 4223, |
| 28445 | GIR_EraseRootFromParent_Done, |
| 28446 | // Label 1564: @94010 |
| 28447 | GIM_Try, /*On fail goto*//*Label 1565*/ GIMT_Encode4(94075), // Rule ID 4225 // |
| 28448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 28449 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28450 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 28454 | // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 28456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28462 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28463 | GIR_RootConstrainSelectedInstOperands, |
| 28464 | // GIR_Coverage, 4225, |
| 28465 | GIR_EraseRootFromParent_Done, |
| 28466 | // Label 1565: @94075 |
| 28467 | GIM_Try, /*On fail goto*//*Label 1566*/ GIMT_Encode4(94137), // Rule ID 4227 // |
| 28468 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28469 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 28473 | // (ld:{ *:[v2f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 28474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 28475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 28476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 28477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28482 | GIR_RootConstrainSelectedInstOperands, |
| 28483 | // GIR_Coverage, 4227, |
| 28484 | GIR_EraseRootFromParent_Done, |
| 28485 | // Label 1566: @94137 |
| 28486 | GIM_Try, /*On fail goto*//*Label 1567*/ GIMT_Encode4(94197), // Rule ID 7589 // |
| 28487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 28488 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28489 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28491 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28492 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 28493 | // (ld:{ *:[v2i64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v2i64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 28494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 28495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 28498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 28499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28501 | GIR_RootConstrainSelectedInstOperands, |
| 28502 | // GIR_Coverage, 7589, |
| 28503 | GIR_EraseRootFromParent_Done, |
| 28504 | // Label 1567: @94197 |
| 28505 | GIM_Try, /*On fail goto*//*Label 1568*/ GIMT_Encode4(94257), // Rule ID 7593 // |
| 28506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 28507 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 28508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 28512 | // (ld:{ *:[v2f64] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v2f64] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 28513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 28514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 28516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 28517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 28518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28519 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28520 | GIR_RootConstrainSelectedInstOperands, |
| 28521 | // GIR_Coverage, 7593, |
| 28522 | GIR_EraseRootFromParent_Done, |
| 28523 | // Label 1568: @94257 |
| 28524 | GIM_Try, /*On fail goto*//*Label 1569*/ GIMT_Encode4(94319), // Rule ID 3535 // |
| 28525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 28526 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28527 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28529 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 28531 | // (ld:{ *:[v2i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2i64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 28533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 28535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 28536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28538 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28539 | GIR_RootConstrainSelectedInstOperands, |
| 28540 | // GIR_Coverage, 3535, |
| 28541 | GIR_EraseRootFromParent_Done, |
| 28542 | // Label 1569: @94319 |
| 28543 | GIM_Try, /*On fail goto*//*Label 1570*/ GIMT_Encode4(94381), // Rule ID 3539 // |
| 28544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 28545 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28546 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28548 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 28550 | // (ld:{ *:[v2f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v2f64] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 28552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 28554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 28555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28557 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28558 | GIR_RootConstrainSelectedInstOperands, |
| 28559 | // GIR_Coverage, 3539, |
| 28560 | GIR_EraseRootFromParent_Done, |
| 28561 | // Label 1570: @94381 |
| 28562 | GIM_Try, /*On fail goto*//*Label 1571*/ GIMT_Encode4(94438), // Rule ID 3534 // |
| 28563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 28564 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28565 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28567 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28568 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 28569 | // (ld:{ *:[v2i64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 28571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28575 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28576 | GIR_RootConstrainSelectedInstOperands, |
| 28577 | // GIR_Coverage, 3534, |
| 28578 | GIR_EraseRootFromParent_Done, |
| 28579 | // Label 1571: @94438 |
| 28580 | GIM_Try, /*On fail goto*//*Label 1572*/ GIMT_Encode4(94495), // Rule ID 3538 // |
| 28581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 28582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28583 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 28587 | // (ld:{ *:[v2f64] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 28589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28593 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28594 | GIR_RootConstrainSelectedInstOperands, |
| 28595 | // GIR_Coverage, 3538, |
| 28596 | GIR_EraseRootFromParent_Done, |
| 28597 | // Label 1572: @94495 |
| 28598 | GIM_Try, /*On fail goto*//*Label 1573*/ GIMT_Encode4(94553), // Rule ID 3272 // |
| 28599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 28600 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28601 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28603 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 28605 | // (ld:{ *:[v2i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v2i64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 28607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28610 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28611 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28612 | GIR_RootConstrainSelectedInstOperands, |
| 28613 | // GIR_Coverage, 3272, |
| 28614 | GIR_EraseRootFromParent_Done, |
| 28615 | // Label 1573: @94553 |
| 28616 | GIM_Try, /*On fail goto*//*Label 1574*/ GIMT_Encode4(94611), // Rule ID 3274 // |
| 28617 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 28618 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 28619 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 28621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 28623 | // (ld:{ *:[v2f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v2f64] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 28624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 28625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 28626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 28627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28630 | GIR_RootConstrainSelectedInstOperands, |
| 28631 | // GIR_Coverage, 3274, |
| 28632 | GIR_EraseRootFromParent_Done, |
| 28633 | // Label 1574: @94611 |
| 28634 | GIM_Reject, |
| 28635 | // Label 861: @94612 |
| 28636 | GIM_Try, /*On fail goto*//*Label 1575*/ GIMT_Encode4(94679), // Rule ID 2742 // |
| 28637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28638 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28639 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28642 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28643 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28644 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28645 | // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28652 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28653 | GIR_RootConstrainSelectedInstOperands, |
| 28654 | // GIR_Coverage, 2742, |
| 28655 | GIR_EraseRootFromParent_Done, |
| 28656 | // Label 1575: @94679 |
| 28657 | GIM_Try, /*On fail goto*//*Label 1576*/ GIMT_Encode4(94746), // Rule ID 2757 // |
| 28658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28659 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28660 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28662 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28663 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28664 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28666 | // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28673 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28674 | GIR_RootConstrainSelectedInstOperands, |
| 28675 | // GIR_Coverage, 2757, |
| 28676 | GIR_EraseRootFromParent_Done, |
| 28677 | // Label 1576: @94746 |
| 28678 | GIM_Try, /*On fail goto*//*Label 1577*/ GIMT_Encode4(94809), // Rule ID 2747 // |
| 28679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28680 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28683 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28684 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28686 | // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec), |
| 28688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28693 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28694 | GIR_RootConstrainSelectedInstOperands, |
| 28695 | // GIR_Coverage, 2747, |
| 28696 | GIR_EraseRootFromParent_Done, |
| 28697 | // Label 1577: @94809 |
| 28698 | GIM_Try, /*On fail goto*//*Label 1578*/ GIMT_Encode4(94872), // Rule ID 2762 // |
| 28699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28700 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28701 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28704 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28706 | // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec), |
| 28708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28714 | GIR_RootConstrainSelectedInstOperands, |
| 28715 | // GIR_Coverage, 2762, |
| 28716 | GIR_EraseRootFromParent_Done, |
| 28717 | // Label 1578: @94872 |
| 28718 | GIM_Try, /*On fail goto*//*Label 1579*/ GIMT_Encode4(94935), // Rule ID 2752 // |
| 28719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 28720 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28723 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28724 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28725 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28726 | // (ld:{ *:[v3i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28734 | GIR_RootConstrainSelectedInstOperands, |
| 28735 | // GIR_Coverage, 2752, |
| 28736 | GIR_EraseRootFromParent_Done, |
| 28737 | // Label 1579: @94935 |
| 28738 | GIM_Try, /*On fail goto*//*Label 1580*/ GIMT_Encode4(94998), // Rule ID 2767 // |
| 28739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 28740 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28741 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28743 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28744 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28745 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 28746 | // (ld:{ *:[v3f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 28752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28753 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28754 | GIR_RootConstrainSelectedInstOperands, |
| 28755 | // GIR_Coverage, 2767, |
| 28756 | GIR_EraseRootFromParent_Done, |
| 28757 | // Label 1580: @94998 |
| 28758 | GIM_Try, /*On fail goto*//*Label 1581*/ GIMT_Encode4(95060), // Rule ID 2739 // |
| 28759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28760 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28761 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28764 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28765 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 28767 | // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 28769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28774 | GIR_RootConstrainSelectedInstOperands, |
| 28775 | // GIR_Coverage, 2739, |
| 28776 | GIR_EraseRootFromParent_Done, |
| 28777 | // Label 1581: @95060 |
| 28778 | GIM_Try, /*On fail goto*//*Label 1582*/ GIMT_Encode4(95122), // Rule ID 2740 // |
| 28779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 28780 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28783 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28784 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28785 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28787 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 28788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR), |
| 28789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28794 | GIR_RootConstrainSelectedInstOperands, |
| 28795 | // GIR_Coverage, 2740, |
| 28796 | GIR_EraseRootFromParent_Done, |
| 28797 | // Label 1582: @95122 |
| 28798 | GIM_Try, /*On fail goto*//*Label 1583*/ GIMT_Encode4(95187), // Rule ID 2741 // |
| 28799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28800 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28801 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28803 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28804 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28805 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28807 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28815 | GIR_RootConstrainSelectedInstOperands, |
| 28816 | // GIR_Coverage, 2741, |
| 28817 | GIR_EraseRootFromParent_Done, |
| 28818 | // Label 1583: @95187 |
| 28819 | GIM_Try, /*On fail goto*//*Label 1584*/ GIMT_Encode4(95249), // Rule ID 2754 // |
| 28820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28821 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28825 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28826 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 28828 | // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 28830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28834 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28835 | GIR_RootConstrainSelectedInstOperands, |
| 28836 | // GIR_Coverage, 2754, |
| 28837 | GIR_EraseRootFromParent_Done, |
| 28838 | // Label 1584: @95249 |
| 28839 | GIM_Try, /*On fail goto*//*Label 1585*/ GIMT_Encode4(95311), // Rule ID 2755 // |
| 28840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 28841 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28842 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28844 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28845 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28846 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28848 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 28849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR), |
| 28850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28855 | GIR_RootConstrainSelectedInstOperands, |
| 28856 | // GIR_Coverage, 2755, |
| 28857 | GIR_EraseRootFromParent_Done, |
| 28858 | // Label 1585: @95311 |
| 28859 | GIM_Try, /*On fail goto*//*Label 1586*/ GIMT_Encode4(95376), // Rule ID 2756 // |
| 28860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28861 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28862 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28864 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28865 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28866 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 28867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28868 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 28870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28875 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28876 | GIR_RootConstrainSelectedInstOperands, |
| 28877 | // GIR_Coverage, 2756, |
| 28878 | GIR_EraseRootFromParent_Done, |
| 28879 | // Label 1586: @95376 |
| 28880 | GIM_Try, /*On fail goto*//*Label 1587*/ GIMT_Encode4(95434), // Rule ID 2744 // |
| 28881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28882 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28883 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28886 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 28888 | // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec), |
| 28890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28895 | GIR_RootConstrainSelectedInstOperands, |
| 28896 | // GIR_Coverage, 2744, |
| 28897 | GIR_EraseRootFromParent_Done, |
| 28898 | // Label 1587: @95434 |
| 28899 | GIM_Try, /*On fail goto*//*Label 1588*/ GIMT_Encode4(95492), // Rule ID 2745 // |
| 28900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 28901 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28902 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28905 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28907 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 28908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_ec), |
| 28909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28913 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28914 | GIR_RootConstrainSelectedInstOperands, |
| 28915 | // GIR_Coverage, 2745, |
| 28916 | GIR_EraseRootFromParent_Done, |
| 28917 | // Label 1588: @95492 |
| 28918 | GIM_Try, /*On fail goto*//*Label 1589*/ GIMT_Encode4(95553), // Rule ID 2746 // |
| 28919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28920 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28921 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28923 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28924 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28926 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec), |
| 28928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28933 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28934 | GIR_RootConstrainSelectedInstOperands, |
| 28935 | // GIR_Coverage, 2746, |
| 28936 | GIR_EraseRootFromParent_Done, |
| 28937 | // Label 1589: @95553 |
| 28938 | GIM_Try, /*On fail goto*//*Label 1590*/ GIMT_Encode4(95611), // Rule ID 2759 // |
| 28939 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 28940 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28941 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28943 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28944 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28945 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 28946 | // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 28947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec), |
| 28948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 28951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28952 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28953 | GIR_RootConstrainSelectedInstOperands, |
| 28954 | // GIR_Coverage, 2759, |
| 28955 | GIR_EraseRootFromParent_Done, |
| 28956 | // Label 1590: @95611 |
| 28957 | GIM_Try, /*On fail goto*//*Label 1591*/ GIMT_Encode4(95669), // Rule ID 2760 // |
| 28958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 28959 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28960 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28963 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28964 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28965 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 28966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_ec), |
| 28967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28971 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28972 | GIR_RootConstrainSelectedInstOperands, |
| 28973 | // GIR_Coverage, 2760, |
| 28974 | GIR_EraseRootFromParent_Done, |
| 28975 | // Label 1591: @95669 |
| 28976 | GIM_Try, /*On fail goto*//*Label 1592*/ GIMT_Encode4(95730), // Rule ID 2761 // |
| 28977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 28978 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28979 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 28980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 28981 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 28982 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 28983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 28984 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM_ec:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 28985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM_ec), |
| 28986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 28987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 28988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 28989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 28991 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 28992 | GIR_RootConstrainSelectedInstOperands, |
| 28993 | // GIR_Coverage, 2761, |
| 28994 | GIR_EraseRootFromParent_Done, |
| 28995 | // Label 1592: @95730 |
| 28996 | GIM_Try, /*On fail goto*//*Label 1593*/ GIMT_Encode4(95789), // Rule ID 7723 // |
| 28997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 28998 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 28999 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29000 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29003 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29004 | // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96), |
| 29006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29011 | GIR_RootConstrainSelectedInstOperands, |
| 29012 | // GIR_Coverage, 7723, |
| 29013 | GIR_EraseRootFromParent_Done, |
| 29014 | // Label 1593: @95789 |
| 29015 | GIM_Try, /*On fail goto*//*Label 1594*/ GIMT_Encode4(95848), // Rule ID 7727 // |
| 29016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 29017 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29018 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29019 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29023 | // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96), |
| 29025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29030 | GIR_RootConstrainSelectedInstOperands, |
| 29031 | // GIR_Coverage, 7727, |
| 29032 | GIR_EraseRootFromParent_Done, |
| 29033 | // Label 1594: @95848 |
| 29034 | GIM_Try, /*On fail goto*//*Label 1595*/ GIMT_Encode4(95911), // Rule ID 7647 // |
| 29035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 29036 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29037 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29038 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 29039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29041 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29043 | // (AMDGPUld_glue:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B96:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96), |
| 29045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29049 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29050 | GIR_RootConstrainSelectedInstOperands, |
| 29051 | // GIR_Coverage, 7647, |
| 29052 | GIR_EraseRootFromParent_Done, |
| 29053 | // Label 1595: @95911 |
| 29054 | GIM_Try, /*On fail goto*//*Label 1596*/ GIMT_Encode4(95974), // Rule ID 7651 // |
| 29055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 29056 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29057 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29058 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 29059 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29061 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29062 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29063 | // (AMDGPUld_glue:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B96:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96), |
| 29065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29070 | GIR_RootConstrainSelectedInstOperands, |
| 29071 | // GIR_Coverage, 7651, |
| 29072 | GIR_EraseRootFromParent_Done, |
| 29073 | // Label 1596: @95974 |
| 29074 | GIM_Try, /*On fail goto*//*Label 1597*/ GIMT_Encode4(96029), // Rule ID 2749 // |
| 29075 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29076 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29078 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29079 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 29081 | // (ld:{ *:[v3i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29087 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29088 | GIR_RootConstrainSelectedInstOperands, |
| 29089 | // GIR_Coverage, 2749, |
| 29090 | GIR_EraseRootFromParent_Done, |
| 29091 | // Label 1597: @96029 |
| 29092 | GIM_Try, /*On fail goto*//*Label 1598*/ GIMT_Encode4(96087), // Rule ID 2750 // |
| 29093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 29094 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29095 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29097 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29098 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29099 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29100 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 29101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR), |
| 29102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29106 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29107 | GIR_RootConstrainSelectedInstOperands, |
| 29108 | // GIR_Coverage, 2750, |
| 29109 | GIR_EraseRootFromParent_Done, |
| 29110 | // Label 1598: @96087 |
| 29111 | GIM_Try, /*On fail goto*//*Label 1599*/ GIMT_Encode4(96148), // Rule ID 2751 // |
| 29112 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 29113 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29114 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29116 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29117 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29118 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29119 | // (ld:{ *:[v3i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 29121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29127 | GIR_RootConstrainSelectedInstOperands, |
| 29128 | // GIR_Coverage, 2751, |
| 29129 | GIR_EraseRootFromParent_Done, |
| 29130 | // Label 1599: @96148 |
| 29131 | GIM_Try, /*On fail goto*//*Label 1600*/ GIMT_Encode4(96203), // Rule ID 2764 // |
| 29132 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29133 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29135 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29136 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29137 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 29138 | // (ld:{ *:[v3f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29145 | GIR_RootConstrainSelectedInstOperands, |
| 29146 | // GIR_Coverage, 2764, |
| 29147 | GIR_EraseRootFromParent_Done, |
| 29148 | // Label 1600: @96203 |
| 29149 | GIM_Try, /*On fail goto*//*Label 1601*/ GIMT_Encode4(96261), // Rule ID 2765 // |
| 29150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 29151 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29152 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29155 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29156 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29157 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 29158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR), |
| 29159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29163 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29164 | GIR_RootConstrainSelectedInstOperands, |
| 29165 | // GIR_Coverage, 2765, |
| 29166 | GIR_EraseRootFromParent_Done, |
| 29167 | // Label 1601: @96261 |
| 29168 | GIM_Try, /*On fail goto*//*Label 1602*/ GIMT_Encode4(96322), // Rule ID 2766 // |
| 29169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 29170 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29171 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29173 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29174 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29176 | // (ld:{ *:[v3f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_SGPR_IMM), |
| 29178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29184 | GIR_RootConstrainSelectedInstOperands, |
| 29185 | // GIR_Coverage, 2766, |
| 29186 | GIR_EraseRootFromParent_Done, |
| 29187 | // Label 1602: @96322 |
| 29188 | GIM_Try, /*On fail goto*//*Label 1603*/ GIMT_Encode4(96377), // Rule ID 7724 // |
| 29189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 29190 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29191 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29193 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29195 | // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9), |
| 29197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29201 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29202 | GIR_RootConstrainSelectedInstOperands, |
| 29203 | // GIR_Coverage, 7724, |
| 29204 | GIR_EraseRootFromParent_Done, |
| 29205 | // Label 1603: @96377 |
| 29206 | GIM_Try, /*On fail goto*//*Label 1604*/ GIMT_Encode4(96432), // Rule ID 7728 // |
| 29207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 29208 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29209 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29211 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29212 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29213 | // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9), |
| 29215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29220 | GIR_RootConstrainSelectedInstOperands, |
| 29221 | // GIR_Coverage, 7728, |
| 29222 | GIR_EraseRootFromParent_Done, |
| 29223 | // Label 1604: @96432 |
| 29224 | GIM_Try, /*On fail goto*//*Label 1605*/ GIMT_Encode4(96491), // Rule ID 7648 // |
| 29225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 29226 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29227 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 29228 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29230 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29231 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29232 | // (ld:{ *:[v3i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B96_gfx9:{ *:[v3i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9), |
| 29234 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29239 | GIR_RootConstrainSelectedInstOperands, |
| 29240 | // GIR_Coverage, 7648, |
| 29241 | GIR_EraseRootFromParent_Done, |
| 29242 | // Label 1605: @96491 |
| 29243 | GIM_Try, /*On fail goto*//*Label 1606*/ GIMT_Encode4(96550), // Rule ID 7652 // |
| 29244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 29245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 29246 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 29247 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29249 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 29251 | // (ld:{ *:[v3f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B96_gfx9:{ *:[v3f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 29252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B96_gfx9), |
| 29253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 29255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29257 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29258 | GIR_RootConstrainSelectedInstOperands, |
| 29259 | // GIR_Coverage, 7652, |
| 29260 | GIR_EraseRootFromParent_Done, |
| 29261 | // Label 1606: @96550 |
| 29262 | GIM_Try, /*On fail goto*//*Label 1607*/ GIMT_Encode4(96604), // Rule ID 2743 // |
| 29263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 29264 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29267 | // MIs[0] sbase |
| 29268 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29269 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29270 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29271 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29272 | // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29275 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29279 | GIR_RootConstrainSelectedInstOperands, |
| 29280 | // GIR_Coverage, 2743, |
| 29281 | GIR_EraseRootFromParent_Done, |
| 29282 | // Label 1607: @96604 |
| 29283 | GIM_Try, /*On fail goto*//*Label 1608*/ GIMT_Encode4(96658), // Rule ID 2758 // |
| 29284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 29285 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29286 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29288 | // MIs[0] sbase |
| 29289 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29290 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29291 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29292 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29293 | // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29296 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29300 | GIR_RootConstrainSelectedInstOperands, |
| 29301 | // GIR_Coverage, 2758, |
| 29302 | GIR_EraseRootFromParent_Done, |
| 29303 | // Label 1608: @96658 |
| 29304 | GIM_Try, /*On fail goto*//*Label 1609*/ GIMT_Encode4(96708), // Rule ID 2748 // |
| 29305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 29306 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29307 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29309 | // MIs[0] sbase |
| 29310 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29311 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29312 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29313 | // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM_ec:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec), |
| 29315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29316 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29319 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29320 | GIR_RootConstrainSelectedInstOperands, |
| 29321 | // GIR_Coverage, 2748, |
| 29322 | GIR_EraseRootFromParent_Done, |
| 29323 | // Label 1609: @96708 |
| 29324 | GIM_Try, /*On fail goto*//*Label 1610*/ GIMT_Encode4(96758), // Rule ID 2763 // |
| 29325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 29326 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29327 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29329 | // MIs[0] sbase |
| 29330 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29331 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29332 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29333 | // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM_ec:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM_ec), |
| 29335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29336 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29339 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29340 | GIR_RootConstrainSelectedInstOperands, |
| 29341 | // GIR_Coverage, 2763, |
| 29342 | GIR_EraseRootFromParent_Done, |
| 29343 | // Label 1610: @96758 |
| 29344 | GIM_Try, /*On fail goto*//*Label 1611*/ GIMT_Encode4(96805), // Rule ID 2753 // |
| 29345 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29346 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29348 | // MIs[0] sbase |
| 29349 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29350 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29351 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29352 | // (ld:{ *:[v3i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29355 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29358 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29359 | GIR_RootConstrainSelectedInstOperands, |
| 29360 | // GIR_Coverage, 2753, |
| 29361 | GIR_EraseRootFromParent_Done, |
| 29362 | // Label 1611: @96805 |
| 29363 | GIM_Try, /*On fail goto*//*Label 1612*/ GIMT_Encode4(96852), // Rule ID 2768 // |
| 29364 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29365 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 29367 | // MIs[0] sbase |
| 29368 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 29369 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 29370 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29371 | // (ld:{ *:[v3f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX3_IMM:{ *:[v3f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX3_IMM), |
| 29373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29374 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 29375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29378 | GIR_RootConstrainSelectedInstOperands, |
| 29379 | // GIR_Coverage, 2768, |
| 29380 | GIR_EraseRootFromParent_Done, |
| 29381 | // Label 1612: @96852 |
| 29382 | GIM_Try, /*On fail goto*//*Label 1613*/ GIMT_Encode4(96915), // Rule ID 6210 // |
| 29383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 29384 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29385 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29387 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29388 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 29389 | // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 29390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), |
| 29391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29398 | GIR_RootConstrainSelectedInstOperands, |
| 29399 | // GIR_Coverage, 6210, |
| 29400 | GIR_EraseRootFromParent_Done, |
| 29401 | // Label 1613: @96915 |
| 29402 | GIM_Try, /*On fail goto*//*Label 1614*/ GIMT_Encode4(96978), // Rule ID 6212 // |
| 29403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 29404 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29405 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 29409 | // (ld:{ *:[v3i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 29410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET), |
| 29411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29418 | GIR_RootConstrainSelectedInstOperands, |
| 29419 | // GIR_Coverage, 6212, |
| 29420 | GIR_EraseRootFromParent_Done, |
| 29421 | // Label 1614: @96978 |
| 29422 | GIM_Try, /*On fail goto*//*Label 1615*/ GIMT_Encode4(97038), // Rule ID 3990 // |
| 29423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 29424 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29425 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 29429 | // (ld:{ *:[v3i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX3_SVS:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SVS), |
| 29431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 29433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 29434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29436 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29437 | GIR_RootConstrainSelectedInstOperands, |
| 29438 | // GIR_Coverage, 3990, |
| 29439 | GIR_EraseRootFromParent_Done, |
| 29440 | // Label 1615: @97038 |
| 29441 | GIM_Try, /*On fail goto*//*Label 1616*/ GIMT_Encode4(97093), // Rule ID 3989 // |
| 29442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 29443 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29444 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29446 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 29448 | // (ld:{ *:[v3i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 29449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3_SADDR), |
| 29450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 29452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29454 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29455 | GIR_RootConstrainSelectedInstOperands, |
| 29456 | // GIR_Coverage, 3989, |
| 29457 | GIR_EraseRootFromParent_Done, |
| 29458 | // Label 1616: @97093 |
| 29459 | GIM_Try, /*On fail goto*//*Label 1617*/ GIMT_Encode4(97148), // Rule ID 3988 // |
| 29460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 29461 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29464 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 29466 | // (ld:{ *:[v3i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 29467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX3), |
| 29468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 29470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29473 | GIR_RootConstrainSelectedInstOperands, |
| 29474 | // GIR_Coverage, 3988, |
| 29475 | GIR_EraseRootFromParent_Done, |
| 29476 | // Label 1617: @97148 |
| 29477 | GIM_Try, /*On fail goto*//*Label 1618*/ GIMT_Encode4(97218), // Rule ID 4206 // |
| 29478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 29479 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29480 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 29484 | // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64), |
| 29486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29493 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29494 | GIR_RootConstrainSelectedInstOperands, |
| 29495 | // GIR_Coverage, 4206, |
| 29496 | GIR_EraseRootFromParent_Done, |
| 29497 | // Label 1618: @97218 |
| 29498 | GIM_Try, /*On fail goto*//*Label 1619*/ GIMT_Encode4(97285), // Rule ID 4208 // |
| 29499 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29500 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 29504 | // (ld:{ *:[v3i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64), |
| 29506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29514 | GIR_RootConstrainSelectedInstOperands, |
| 29515 | // GIR_Coverage, 4208, |
| 29516 | GIR_EraseRootFromParent_Done, |
| 29517 | // Label 1619: @97285 |
| 29518 | GIM_Try, /*On fail goto*//*Label 1620*/ GIMT_Encode4(97355), // Rule ID 4210 // |
| 29519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 29520 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29521 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29523 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29524 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 29525 | // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_ADDR64), |
| 29527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29535 | GIR_RootConstrainSelectedInstOperands, |
| 29536 | // GIR_Coverage, 4210, |
| 29537 | GIR_EraseRootFromParent_Done, |
| 29538 | // Label 1620: @97355 |
| 29539 | GIM_Try, /*On fail goto*//*Label 1621*/ GIMT_Encode4(97422), // Rule ID 4212 // |
| 29540 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29541 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29543 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 29545 | // (ld:{ *:[v3f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64:{ *:[v3f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_ADDR64), |
| 29547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29555 | GIR_RootConstrainSelectedInstOperands, |
| 29556 | // GIR_Coverage, 4212, |
| 29557 | GIR_EraseRootFromParent_Done, |
| 29558 | // Label 1621: @97422 |
| 29559 | GIM_Try, /*On fail goto*//*Label 1622*/ GIMT_Encode4(97490), // Rule ID 6209 // |
| 29560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 29561 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29562 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29564 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29565 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 29566 | // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 29567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN), |
| 29568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29575 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29576 | GIR_RootConstrainSelectedInstOperands, |
| 29577 | // GIR_Coverage, 6209, |
| 29578 | GIR_EraseRootFromParent_Done, |
| 29579 | // Label 1622: @97490 |
| 29580 | GIM_Try, /*On fail goto*//*Label 1623*/ GIMT_Encode4(97558), // Rule ID 6211 // |
| 29581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 29582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 29583 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 29587 | // (ld:{ *:[v3i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 29588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN), |
| 29589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 29591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 29593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 29594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29597 | GIR_RootConstrainSelectedInstOperands, |
| 29598 | // GIR_Coverage, 6211, |
| 29599 | GIR_EraseRootFromParent_Done, |
| 29600 | // Label 1623: @97558 |
| 29601 | GIM_Try, /*On fail goto*//*Label 1624*/ GIMT_Encode4(97623), // Rule ID 4205 // |
| 29602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 29603 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29606 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29607 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 29608 | // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), |
| 29610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29617 | GIR_RootConstrainSelectedInstOperands, |
| 29618 | // GIR_Coverage, 4205, |
| 29619 | GIR_EraseRootFromParent_Done, |
| 29620 | // Label 1624: @97623 |
| 29621 | GIM_Try, /*On fail goto*//*Label 1625*/ GIMT_Encode4(97685), // Rule ID 4207 // |
| 29622 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29623 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29625 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29626 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 29627 | // (ld:{ *:[v3i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET), |
| 29629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29635 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29636 | GIR_RootConstrainSelectedInstOperands, |
| 29637 | // GIR_Coverage, 4207, |
| 29638 | GIR_EraseRootFromParent_Done, |
| 29639 | // Label 1625: @97685 |
| 29640 | GIM_Try, /*On fail goto*//*Label 1626*/ GIMT_Encode4(97750), // Rule ID 4209 // |
| 29641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 29642 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29643 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29644 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29645 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29646 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 29647 | // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), |
| 29649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29655 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29656 | GIR_RootConstrainSelectedInstOperands, |
| 29657 | // GIR_Coverage, 4209, |
| 29658 | GIR_EraseRootFromParent_Done, |
| 29659 | // Label 1626: @97750 |
| 29660 | GIM_Try, /*On fail goto*//*Label 1627*/ GIMT_Encode4(97812), // Rule ID 4211 // |
| 29661 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29662 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29664 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 29666 | // (ld:{ *:[v3f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 29667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET), |
| 29668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 29669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 29670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29675 | GIR_RootConstrainSelectedInstOperands, |
| 29676 | // GIR_Coverage, 4211, |
| 29677 | GIR_EraseRootFromParent_Done, |
| 29678 | // Label 1627: @97812 |
| 29679 | GIM_Try, /*On fail goto*//*Label 1628*/ GIMT_Encode4(97874), // Rule ID 3525 // |
| 29680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 29681 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 29686 | // (ld:{ *:[v3i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX3_SADDR:{ *:[v3i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3_SADDR), |
| 29688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 29690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 29691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29693 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29694 | GIR_RootConstrainSelectedInstOperands, |
| 29695 | // GIR_Coverage, 3525, |
| 29696 | GIR_EraseRootFromParent_Done, |
| 29697 | // Label 1628: @97874 |
| 29698 | GIM_Try, /*On fail goto*//*Label 1629*/ GIMT_Encode4(97931), // Rule ID 3524 // |
| 29699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 29700 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29701 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 29705 | // (ld:{ *:[v3i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 29706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX3), |
| 29707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 29709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29712 | GIR_RootConstrainSelectedInstOperands, |
| 29713 | // GIR_Coverage, 3524, |
| 29714 | GIR_EraseRootFromParent_Done, |
| 29715 | // Label 1629: @97931 |
| 29716 | GIM_Try, /*On fail goto*//*Label 1630*/ GIMT_Encode4(97989), // Rule ID 3224 // |
| 29717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 29718 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 29719 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 29721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 29723 | // (ld:{ *:[v3i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX3:{ *:[v3i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 29724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX3), |
| 29725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 29726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 29727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29729 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29730 | GIR_RootConstrainSelectedInstOperands, |
| 29731 | // GIR_Coverage, 3224, |
| 29732 | GIR_EraseRootFromParent_Done, |
| 29733 | // Label 1630: @97989 |
| 29734 | GIM_Reject, |
| 29735 | // Label 862: @97990 |
| 29736 | GIM_Try, /*On fail goto*//*Label 1631*/ GIMT_Encode4(98057), // Rule ID 2692 // |
| 29737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29738 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29739 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29741 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29742 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29743 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29745 | // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29753 | GIR_RootConstrainSelectedInstOperands, |
| 29754 | // GIR_Coverage, 2692, |
| 29755 | GIR_EraseRootFromParent_Done, |
| 29756 | // Label 1631: @98057 |
| 29757 | GIM_Try, /*On fail goto*//*Label 1632*/ GIMT_Encode4(98124), // Rule ID 2709 // |
| 29758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29759 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29760 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29762 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29763 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29764 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29766 | // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29774 | GIR_RootConstrainSelectedInstOperands, |
| 29775 | // GIR_Coverage, 2709, |
| 29776 | GIR_EraseRootFromParent_Done, |
| 29777 | // Label 1632: @98124 |
| 29778 | GIM_Try, /*On fail goto*//*Label 1633*/ GIMT_Encode4(98191), // Rule ID 2726 // |
| 29779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29780 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29783 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29784 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29785 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29787 | // (ld:{ *:[v4bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29795 | GIR_RootConstrainSelectedInstOperands, |
| 29796 | // GIR_Coverage, 2726, |
| 29797 | GIR_EraseRootFromParent_Done, |
| 29798 | // Label 1633: @98191 |
| 29799 | GIM_Try, /*On fail goto*//*Label 1634*/ GIMT_Encode4(98254), // Rule ID 2697 // |
| 29800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29801 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29802 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29804 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29805 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29807 | // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 29809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29815 | GIR_RootConstrainSelectedInstOperands, |
| 29816 | // GIR_Coverage, 2697, |
| 29817 | GIR_EraseRootFromParent_Done, |
| 29818 | // Label 1634: @98254 |
| 29819 | GIM_Try, /*On fail goto*//*Label 1635*/ GIMT_Encode4(98317), // Rule ID 2714 // |
| 29820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29821 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29825 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29826 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29827 | // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 29829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29834 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29835 | GIR_RootConstrainSelectedInstOperands, |
| 29836 | // GIR_Coverage, 2714, |
| 29837 | GIR_EraseRootFromParent_Done, |
| 29838 | // Label 1635: @98317 |
| 29839 | GIM_Try, /*On fail goto*//*Label 1636*/ GIMT_Encode4(98380), // Rule ID 2731 // |
| 29840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29841 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29842 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29844 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29845 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29847 | // (ld:{ *:[v4bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 29849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29855 | GIR_RootConstrainSelectedInstOperands, |
| 29856 | // GIR_Coverage, 2731, |
| 29857 | GIR_EraseRootFromParent_Done, |
| 29858 | // Label 1636: @98380 |
| 29859 | GIM_Try, /*On fail goto*//*Label 1637*/ GIMT_Encode4(98443), // Rule ID 2703 // |
| 29860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 29861 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29862 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29864 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29865 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29867 | // (ld:{ *:[v4i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29874 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29875 | GIR_RootConstrainSelectedInstOperands, |
| 29876 | // GIR_Coverage, 2703, |
| 29877 | GIR_EraseRootFromParent_Done, |
| 29878 | // Label 1637: @98443 |
| 29879 | GIM_Try, /*On fail goto*//*Label 1638*/ GIMT_Encode4(98506), // Rule ID 2720 // |
| 29880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 29881 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29882 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29884 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29885 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29887 | // (ld:{ *:[v4f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29895 | GIR_RootConstrainSelectedInstOperands, |
| 29896 | // GIR_Coverage, 2720, |
| 29897 | GIR_EraseRootFromParent_Done, |
| 29898 | // Label 1638: @98506 |
| 29899 | GIM_Try, /*On fail goto*//*Label 1639*/ GIMT_Encode4(98569), // Rule ID 2737 // |
| 29900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 29901 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29902 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29905 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 29907 | // (ld:{ *:[v4bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 29913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29915 | GIR_RootConstrainSelectedInstOperands, |
| 29916 | // GIR_Coverage, 2737, |
| 29917 | GIR_EraseRootFromParent_Done, |
| 29918 | // Label 1639: @98569 |
| 29919 | GIM_Try, /*On fail goto*//*Label 1640*/ GIMT_Encode4(98631), // Rule ID 2688 // |
| 29920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 29921 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29922 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29924 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29925 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29926 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29927 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 29928 | // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 29930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29934 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29935 | GIR_RootConstrainSelectedInstOperands, |
| 29936 | // GIR_Coverage, 2688, |
| 29937 | GIR_EraseRootFromParent_Done, |
| 29938 | // Label 1640: @98631 |
| 29939 | GIM_Try, /*On fail goto*//*Label 1641*/ GIMT_Encode4(98693), // Rule ID 2689 // |
| 29940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 29941 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29944 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29945 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29946 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 29948 | // (ld:{ *:[v4i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 29949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 29950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 29953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29954 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29955 | GIR_RootConstrainSelectedInstOperands, |
| 29956 | // GIR_Coverage, 2689, |
| 29957 | GIR_EraseRootFromParent_Done, |
| 29958 | // Label 1641: @98693 |
| 29959 | GIM_Try, /*On fail goto*//*Label 1642*/ GIMT_Encode4(98755), // Rule ID 2690 // |
| 29960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 29961 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29962 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29964 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29965 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29966 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29967 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29968 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 29969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 29970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29974 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29975 | GIR_RootConstrainSelectedInstOperands, |
| 29976 | // GIR_Coverage, 2690, |
| 29977 | GIR_EraseRootFromParent_Done, |
| 29978 | // Label 1642: @98755 |
| 29979 | GIM_Try, /*On fail goto*//*Label 1643*/ GIMT_Encode4(98820), // Rule ID 2691 // |
| 29980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 29981 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 29982 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 29983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 29984 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 29985 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 29986 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 29987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 29988 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 29989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 29990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 29991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 29992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 29993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 29995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 29996 | GIR_RootConstrainSelectedInstOperands, |
| 29997 | // GIR_Coverage, 2691, |
| 29998 | GIR_EraseRootFromParent_Done, |
| 29999 | // Label 1643: @98820 |
| 30000 | GIM_Try, /*On fail goto*//*Label 1644*/ GIMT_Encode4(98882), // Rule ID 2705 // |
| 30001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30002 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30003 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30006 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30007 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30009 | // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30016 | GIR_RootConstrainSelectedInstOperands, |
| 30017 | // GIR_Coverage, 2705, |
| 30018 | GIR_EraseRootFromParent_Done, |
| 30019 | // Label 1644: @98882 |
| 30020 | GIM_Try, /*On fail goto*//*Label 1645*/ GIMT_Encode4(98944), // Rule ID 2706 // |
| 30021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 30022 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30023 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30025 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30026 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30027 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 30029 | // (ld:{ *:[v4f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 30031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30036 | GIR_RootConstrainSelectedInstOperands, |
| 30037 | // GIR_Coverage, 2706, |
| 30038 | GIR_EraseRootFromParent_Done, |
| 30039 | // Label 1645: @98944 |
| 30040 | GIM_Try, /*On fail goto*//*Label 1646*/ GIMT_Encode4(99006), // Rule ID 2707 // |
| 30041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 30042 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30043 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30045 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30046 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30047 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30049 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 30051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30055 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30056 | GIR_RootConstrainSelectedInstOperands, |
| 30057 | // GIR_Coverage, 2707, |
| 30058 | GIR_EraseRootFromParent_Done, |
| 30059 | // Label 1646: @99006 |
| 30060 | GIM_Try, /*On fail goto*//*Label 1647*/ GIMT_Encode4(99071), // Rule ID 2708 // |
| 30061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 30062 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30063 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30065 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30066 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30067 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30068 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30069 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 30071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30077 | GIR_RootConstrainSelectedInstOperands, |
| 30078 | // GIR_Coverage, 2708, |
| 30079 | GIR_EraseRootFromParent_Done, |
| 30080 | // Label 1647: @99071 |
| 30081 | GIM_Try, /*On fail goto*//*Label 1648*/ GIMT_Encode4(99133), // Rule ID 2722 // |
| 30082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30083 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30084 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30086 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30087 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30088 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30090 | // (ld:{ *:[v4bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30097 | GIR_RootConstrainSelectedInstOperands, |
| 30098 | // GIR_Coverage, 2722, |
| 30099 | GIR_EraseRootFromParent_Done, |
| 30100 | // Label 1648: @99133 |
| 30101 | GIM_Try, /*On fail goto*//*Label 1649*/ GIMT_Encode4(99195), // Rule ID 2723 // |
| 30102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 30103 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30106 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30107 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30108 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 30110 | // (ld:{ *:[v4bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 30112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30117 | GIR_RootConstrainSelectedInstOperands, |
| 30118 | // GIR_Coverage, 2723, |
| 30119 | GIR_EraseRootFromParent_Done, |
| 30120 | // Label 1649: @99195 |
| 30121 | GIM_Try, /*On fail goto*//*Label 1650*/ GIMT_Encode4(99257), // Rule ID 2724 // |
| 30122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 30123 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30124 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30126 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30127 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30128 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30130 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 30132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30136 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30137 | GIR_RootConstrainSelectedInstOperands, |
| 30138 | // GIR_Coverage, 2724, |
| 30139 | GIR_EraseRootFromParent_Done, |
| 30140 | // Label 1650: @99257 |
| 30141 | GIM_Try, /*On fail goto*//*Label 1651*/ GIMT_Encode4(99322), // Rule ID 2725 // |
| 30142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 30143 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30147 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30148 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30150 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 30152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30158 | GIR_RootConstrainSelectedInstOperands, |
| 30159 | // GIR_Coverage, 2725, |
| 30160 | GIR_EraseRootFromParent_Done, |
| 30161 | // Label 1651: @99322 |
| 30162 | GIM_Try, /*On fail goto*//*Label 1652*/ GIMT_Encode4(99380), // Rule ID 2694 // |
| 30163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30164 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30165 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30167 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30169 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30170 | // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30177 | GIR_RootConstrainSelectedInstOperands, |
| 30178 | // GIR_Coverage, 2694, |
| 30179 | GIR_EraseRootFromParent_Done, |
| 30180 | // Label 1652: @99380 |
| 30181 | GIM_Try, /*On fail goto*//*Label 1653*/ GIMT_Encode4(99438), // Rule ID 2695 // |
| 30182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 30183 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30184 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30187 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30188 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30189 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 30191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30196 | GIR_RootConstrainSelectedInstOperands, |
| 30197 | // GIR_Coverage, 2695, |
| 30198 | GIR_EraseRootFromParent_Done, |
| 30199 | // Label 1653: @99438 |
| 30200 | GIM_Try, /*On fail goto*//*Label 1654*/ GIMT_Encode4(99499), // Rule ID 2696 // |
| 30201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 30202 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30205 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30206 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30208 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 30210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30215 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30216 | GIR_RootConstrainSelectedInstOperands, |
| 30217 | // GIR_Coverage, 2696, |
| 30218 | GIR_EraseRootFromParent_Done, |
| 30219 | // Label 1654: @99499 |
| 30220 | GIM_Try, /*On fail goto*//*Label 1655*/ GIMT_Encode4(99557), // Rule ID 2711 // |
| 30221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30222 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30225 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30226 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30228 | // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30235 | GIR_RootConstrainSelectedInstOperands, |
| 30236 | // GIR_Coverage, 2711, |
| 30237 | GIR_EraseRootFromParent_Done, |
| 30238 | // Label 1655: @99557 |
| 30239 | GIM_Try, /*On fail goto*//*Label 1656*/ GIMT_Encode4(99615), // Rule ID 2712 // |
| 30240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 30241 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30245 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30247 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 30249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30254 | GIR_RootConstrainSelectedInstOperands, |
| 30255 | // GIR_Coverage, 2712, |
| 30256 | GIR_EraseRootFromParent_Done, |
| 30257 | // Label 1656: @99615 |
| 30258 | GIM_Try, /*On fail goto*//*Label 1657*/ GIMT_Encode4(99676), // Rule ID 2713 // |
| 30259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 30260 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30264 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30266 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 30268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30274 | GIR_RootConstrainSelectedInstOperands, |
| 30275 | // GIR_Coverage, 2713, |
| 30276 | GIR_EraseRootFromParent_Done, |
| 30277 | // Label 1657: @99676 |
| 30278 | GIM_Try, /*On fail goto*//*Label 1658*/ GIMT_Encode4(99734), // Rule ID 2728 // |
| 30279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30280 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30284 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30285 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30286 | // (ld:{ *:[v4bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30288 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30292 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30293 | GIR_RootConstrainSelectedInstOperands, |
| 30294 | // GIR_Coverage, 2728, |
| 30295 | GIR_EraseRootFromParent_Done, |
| 30296 | // Label 1658: @99734 |
| 30297 | GIM_Try, /*On fail goto*//*Label 1659*/ GIMT_Encode4(99792), // Rule ID 2729 // |
| 30298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 30299 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30300 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30301 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30302 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30303 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30305 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_ec:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_ec), |
| 30307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30311 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30312 | GIR_RootConstrainSelectedInstOperands, |
| 30313 | // GIR_Coverage, 2729, |
| 30314 | GIR_EraseRootFromParent_Done, |
| 30315 | // Label 1659: @99792 |
| 30316 | GIM_Try, /*On fail goto*//*Label 1660*/ GIMT_Encode4(99853), // Rule ID 2730 // |
| 30317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 30318 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30319 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30322 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30324 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM_ec:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM_ec), |
| 30326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30331 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30332 | GIR_RootConstrainSelectedInstOperands, |
| 30333 | // GIR_Coverage, 2730, |
| 30334 | GIR_EraseRootFromParent_Done, |
| 30335 | // Label 1660: @99853 |
| 30336 | GIM_Try, /*On fail goto*//*Label 1661*/ GIMT_Encode4(99921), // Rule ID 7699 // |
| 30337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 30338 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30339 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30340 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30341 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30344 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 30345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30346 | // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30352 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30353 | GIR_RootConstrainSelectedInstOperands, |
| 30354 | // GIR_Coverage, 7699, |
| 30355 | GIR_EraseRootFromParent_Done, |
| 30356 | // Label 1661: @99921 |
| 30357 | GIM_Try, /*On fail goto*//*Label 1662*/ GIMT_Encode4(99989), // Rule ID 7703 // |
| 30358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 30359 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30360 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30361 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30362 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30365 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 30366 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30367 | // (AMDGPUld_glue:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30374 | GIR_RootConstrainSelectedInstOperands, |
| 30375 | // GIR_Coverage, 7703, |
| 30376 | GIR_EraseRootFromParent_Done, |
| 30377 | // Label 1662: @99989 |
| 30378 | GIM_Try, /*On fail goto*//*Label 1663*/ GIMT_Encode4(100057), // Rule ID 7707 // |
| 30379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 30380 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30381 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30382 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30386 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 30387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30388 | // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30395 | GIR_RootConstrainSelectedInstOperands, |
| 30396 | // GIR_Coverage, 7707, |
| 30397 | GIR_EraseRootFromParent_Done, |
| 30398 | // Label 1663: @100057 |
| 30399 | GIM_Try, /*On fail goto*//*Label 1664*/ GIMT_Encode4(100120), // Rule ID 7623 // |
| 30400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 30401 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30402 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30403 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30404 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30406 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30408 | // (AMDGPUld_glue:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30415 | GIR_RootConstrainSelectedInstOperands, |
| 30416 | // GIR_Coverage, 7623, |
| 30417 | GIR_EraseRootFromParent_Done, |
| 30418 | // Label 1664: @100120 |
| 30419 | GIM_Try, /*On fail goto*//*Label 1665*/ GIMT_Encode4(100183), // Rule ID 7627 // |
| 30420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 30421 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30422 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30423 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30424 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30426 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30427 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30428 | // (AMDGPUld_glue:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30435 | GIR_RootConstrainSelectedInstOperands, |
| 30436 | // GIR_Coverage, 7627, |
| 30437 | GIR_EraseRootFromParent_Done, |
| 30438 | // Label 1665: @100183 |
| 30439 | GIM_Try, /*On fail goto*//*Label 1666*/ GIMT_Encode4(100246), // Rule ID 7631 // |
| 30440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 30441 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30442 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30443 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30444 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30446 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30448 | // (AMDGPUld_glue:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align8_local_m0>> => (DS_READ_B64:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64), |
| 30450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30454 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30455 | GIR_RootConstrainSelectedInstOperands, |
| 30456 | // GIR_Coverage, 7631, |
| 30457 | GIR_EraseRootFromParent_Done, |
| 30458 | // Label 1666: @100246 |
| 30459 | GIM_Try, /*On fail goto*//*Label 1667*/ GIMT_Encode4(100301), // Rule ID 2699 // |
| 30460 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30461 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30463 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30464 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30466 | // (ld:{ *:[v4i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30473 | GIR_RootConstrainSelectedInstOperands, |
| 30474 | // GIR_Coverage, 2699, |
| 30475 | GIR_EraseRootFromParent_Done, |
| 30476 | // Label 1667: @100301 |
| 30477 | GIM_Try, /*On fail goto*//*Label 1668*/ GIMT_Encode4(100359), // Rule ID 2700 // |
| 30478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 30479 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30480 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30483 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 30485 | // (ld:{ *:[v4i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 30487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30491 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30492 | GIR_RootConstrainSelectedInstOperands, |
| 30493 | // GIR_Coverage, 2700, |
| 30494 | GIR_EraseRootFromParent_Done, |
| 30495 | // Label 1668: @100359 |
| 30496 | GIM_Try, /*On fail goto*//*Label 1669*/ GIMT_Encode4(100417), // Rule ID 2701 // |
| 30497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 30498 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30499 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30502 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30504 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 30506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30510 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30511 | GIR_RootConstrainSelectedInstOperands, |
| 30512 | // GIR_Coverage, 2701, |
| 30513 | GIR_EraseRootFromParent_Done, |
| 30514 | // Label 1669: @100417 |
| 30515 | GIM_Try, /*On fail goto*//*Label 1670*/ GIMT_Encode4(100478), // Rule ID 2702 // |
| 30516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 30517 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30518 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30521 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30523 | // (ld:{ *:[v4i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 30525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30531 | GIR_RootConstrainSelectedInstOperands, |
| 30532 | // GIR_Coverage, 2702, |
| 30533 | GIR_EraseRootFromParent_Done, |
| 30534 | // Label 1670: @100478 |
| 30535 | GIM_Try, /*On fail goto*//*Label 1671*/ GIMT_Encode4(100533), // Rule ID 2716 // |
| 30536 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30539 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30540 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30542 | // (ld:{ *:[v4f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30549 | GIR_RootConstrainSelectedInstOperands, |
| 30550 | // GIR_Coverage, 2716, |
| 30551 | GIR_EraseRootFromParent_Done, |
| 30552 | // Label 1671: @100533 |
| 30553 | GIM_Try, /*On fail goto*//*Label 1672*/ GIMT_Encode4(100591), // Rule ID 2717 // |
| 30554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 30555 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30556 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30558 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30559 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 30561 | // (ld:{ *:[v4f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 30563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30567 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30568 | GIR_RootConstrainSelectedInstOperands, |
| 30569 | // GIR_Coverage, 2717, |
| 30570 | GIR_EraseRootFromParent_Done, |
| 30571 | // Label 1672: @100591 |
| 30572 | GIM_Try, /*On fail goto*//*Label 1673*/ GIMT_Encode4(100649), // Rule ID 2718 // |
| 30573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 30574 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30575 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30577 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30578 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30580 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 30582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30587 | GIR_RootConstrainSelectedInstOperands, |
| 30588 | // GIR_Coverage, 2718, |
| 30589 | GIR_EraseRootFromParent_Done, |
| 30590 | // Label 1673: @100649 |
| 30591 | GIM_Try, /*On fail goto*//*Label 1674*/ GIMT_Encode4(100710), // Rule ID 2719 // |
| 30592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 30593 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30594 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30597 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30599 | // (ld:{ *:[v4f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 30601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30607 | GIR_RootConstrainSelectedInstOperands, |
| 30608 | // GIR_Coverage, 2719, |
| 30609 | GIR_EraseRootFromParent_Done, |
| 30610 | // Label 1674: @100710 |
| 30611 | GIM_Try, /*On fail goto*//*Label 1675*/ GIMT_Encode4(100765), // Rule ID 2733 // |
| 30612 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30613 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30616 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 30618 | // (ld:{ *:[v4bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30625 | GIR_RootConstrainSelectedInstOperands, |
| 30626 | // GIR_Coverage, 2733, |
| 30627 | GIR_EraseRootFromParent_Done, |
| 30628 | // Label 1675: @100765 |
| 30629 | GIM_Try, /*On fail goto*//*Label 1676*/ GIMT_Encode4(100823), // Rule ID 2734 // |
| 30630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 30631 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30635 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 30637 | // (ld:{ *:[v4bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ci:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ci), |
| 30639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30643 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30644 | GIR_RootConstrainSelectedInstOperands, |
| 30645 | // GIR_Coverage, 2734, |
| 30646 | GIR_EraseRootFromParent_Done, |
| 30647 | // Label 1676: @100823 |
| 30648 | GIM_Try, /*On fail goto*//*Label 1677*/ GIMT_Encode4(100881), // Rule ID 2735 // |
| 30649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 30650 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30651 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30654 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30656 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 30657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR), |
| 30658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30662 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30663 | GIR_RootConstrainSelectedInstOperands, |
| 30664 | // GIR_Coverage, 2735, |
| 30665 | GIR_EraseRootFromParent_Done, |
| 30666 | // Label 1677: @100881 |
| 30667 | GIM_Try, /*On fail goto*//*Label 1678*/ GIMT_Encode4(100942), // Rule ID 2736 // |
| 30668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 30669 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30670 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30672 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30673 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30674 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 30675 | // (ld:{ *:[v4bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_SGPR_IMM:{ *:[v4bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_SGPR_IMM), |
| 30677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 30679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 30680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30683 | GIR_RootConstrainSelectedInstOperands, |
| 30684 | // GIR_Coverage, 2736, |
| 30685 | GIR_EraseRootFromParent_Done, |
| 30686 | // Label 1678: @100942 |
| 30687 | GIM_Try, /*On fail goto*//*Label 1679*/ GIMT_Encode4(101006), // Rule ID 7700 // |
| 30688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 30689 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30690 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30691 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30693 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30694 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 30695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30696 | // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30703 | GIR_RootConstrainSelectedInstOperands, |
| 30704 | // GIR_Coverage, 7700, |
| 30705 | GIR_EraseRootFromParent_Done, |
| 30706 | // Label 1679: @101006 |
| 30707 | GIM_Try, /*On fail goto*//*Label 1680*/ GIMT_Encode4(101070), // Rule ID 7704 // |
| 30708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 30709 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30710 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30711 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30714 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 30715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30716 | // (ld:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30722 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30723 | GIR_RootConstrainSelectedInstOperands, |
| 30724 | // GIR_Coverage, 7704, |
| 30725 | GIR_EraseRootFromParent_Done, |
| 30726 | // Label 1680: @101070 |
| 30727 | GIM_Try, /*On fail goto*//*Label 1681*/ GIMT_Encode4(101134), // Rule ID 7708 // |
| 30728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 30729 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30730 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30731 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30734 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 30735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30736 | // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30743 | GIR_RootConstrainSelectedInstOperands, |
| 30744 | // GIR_Coverage, 7708, |
| 30745 | GIR_EraseRootFromParent_Done, |
| 30746 | // Label 1681: @101134 |
| 30747 | GIM_Try, /*On fail goto*//*Label 1682*/ GIMT_Encode4(101193), // Rule ID 7624 // |
| 30748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 30749 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30750 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30751 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30755 | // (ld:{ *:[v4f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30761 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30762 | GIR_RootConstrainSelectedInstOperands, |
| 30763 | // GIR_Coverage, 7624, |
| 30764 | GIR_EraseRootFromParent_Done, |
| 30765 | // Label 1682: @101193 |
| 30766 | GIM_Try, /*On fail goto*//*Label 1683*/ GIMT_Encode4(101252), // Rule ID 7628 // |
| 30767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 30768 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30769 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30774 | // (ld:{ *:[v4bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30781 | GIR_RootConstrainSelectedInstOperands, |
| 30782 | // GIR_Coverage, 7628, |
| 30783 | GIR_EraseRootFromParent_Done, |
| 30784 | // Label 1683: @101252 |
| 30785 | GIM_Try, /*On fail goto*//*Label 1684*/ GIMT_Encode4(101311), // Rule ID 7632 // |
| 30786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 30787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 30788 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 30789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 30793 | // (ld:{ *:[v4i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align8_local>> => (DS_READ_B64_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 30794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B64_gfx9), |
| 30795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 30797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 30798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30800 | GIR_RootConstrainSelectedInstOperands, |
| 30801 | // GIR_Coverage, 7632, |
| 30802 | GIR_EraseRootFromParent_Done, |
| 30803 | // Label 1684: @101311 |
| 30804 | GIM_Try, /*On fail goto*//*Label 1685*/ GIMT_Encode4(101365), // Rule ID 2693 // |
| 30805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30806 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30809 | // MIs[0] sbase |
| 30810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30811 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30812 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30813 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30814 | // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30817 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30821 | GIR_RootConstrainSelectedInstOperands, |
| 30822 | // GIR_Coverage, 2693, |
| 30823 | GIR_EraseRootFromParent_Done, |
| 30824 | // Label 1685: @101365 |
| 30825 | GIM_Try, /*On fail goto*//*Label 1686*/ GIMT_Encode4(101419), // Rule ID 2710 // |
| 30826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30827 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30830 | // MIs[0] sbase |
| 30831 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30832 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30833 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30834 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30835 | // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30838 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30842 | GIR_RootConstrainSelectedInstOperands, |
| 30843 | // GIR_Coverage, 2710, |
| 30844 | GIR_EraseRootFromParent_Done, |
| 30845 | // Label 1686: @101419 |
| 30846 | GIM_Try, /*On fail goto*//*Label 1687*/ GIMT_Encode4(101473), // Rule ID 2727 // |
| 30847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30848 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30849 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30851 | // MIs[0] sbase |
| 30852 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30853 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30854 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30855 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 30856 | // (ld:{ *:[v4bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30859 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30862 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30863 | GIR_RootConstrainSelectedInstOperands, |
| 30864 | // GIR_Coverage, 2727, |
| 30865 | GIR_EraseRootFromParent_Done, |
| 30866 | // Label 1687: @101473 |
| 30867 | GIM_Try, /*On fail goto*//*Label 1688*/ GIMT_Encode4(101523), // Rule ID 2698 // |
| 30868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30869 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30872 | // MIs[0] sbase |
| 30873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30875 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30876 | // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30879 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30883 | GIR_RootConstrainSelectedInstOperands, |
| 30884 | // GIR_Coverage, 2698, |
| 30885 | GIR_EraseRootFromParent_Done, |
| 30886 | // Label 1688: @101523 |
| 30887 | GIM_Try, /*On fail goto*//*Label 1689*/ GIMT_Encode4(101573), // Rule ID 2715 // |
| 30888 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30889 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30892 | // MIs[0] sbase |
| 30893 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30894 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30895 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30896 | // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30898 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30899 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30903 | GIR_RootConstrainSelectedInstOperands, |
| 30904 | // GIR_Coverage, 2715, |
| 30905 | GIR_EraseRootFromParent_Done, |
| 30906 | // Label 1689: @101573 |
| 30907 | GIM_Try, /*On fail goto*//*Label 1690*/ GIMT_Encode4(101623), // Rule ID 2732 // |
| 30908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 30909 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30910 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30912 | // MIs[0] sbase |
| 30913 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30914 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30915 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30916 | // (ld:{ *:[v4bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM_ec:{ *:[v4bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM_ec), |
| 30918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30919 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30923 | GIR_RootConstrainSelectedInstOperands, |
| 30924 | // GIR_Coverage, 2732, |
| 30925 | GIR_EraseRootFromParent_Done, |
| 30926 | // Label 1690: @101623 |
| 30927 | GIM_Try, /*On fail goto*//*Label 1691*/ GIMT_Encode4(101670), // Rule ID 2704 // |
| 30928 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30931 | // MIs[0] sbase |
| 30932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30933 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30934 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30935 | // (ld:{ *:[v4i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30938 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30942 | GIR_RootConstrainSelectedInstOperands, |
| 30943 | // GIR_Coverage, 2704, |
| 30944 | GIR_EraseRootFromParent_Done, |
| 30945 | // Label 1691: @101670 |
| 30946 | GIM_Try, /*On fail goto*//*Label 1692*/ GIMT_Encode4(101717), // Rule ID 2721 // |
| 30947 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30948 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30950 | // MIs[0] sbase |
| 30951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30952 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30953 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30954 | // (ld:{ *:[v4f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30957 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30961 | GIR_RootConstrainSelectedInstOperands, |
| 30962 | // GIR_Coverage, 2721, |
| 30963 | GIR_EraseRootFromParent_Done, |
| 30964 | // Label 1692: @101717 |
| 30965 | GIM_Try, /*On fail goto*//*Label 1693*/ GIMT_Encode4(101764), // Rule ID 2738 // |
| 30966 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 30967 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 30969 | // MIs[0] sbase |
| 30970 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 30971 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 30972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 30973 | // (ld:{ *:[v4bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX2_IMM:{ *:[v4bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 30974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX2_IMM), |
| 30975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 30976 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 30977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30979 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30980 | GIR_RootConstrainSelectedInstOperands, |
| 30981 | // GIR_Coverage, 2738, |
| 30982 | GIR_EraseRootFromParent_Done, |
| 30983 | // Label 1693: @101764 |
| 30984 | GIM_Try, /*On fail goto*//*Label 1694*/ GIMT_Encode4(101824), // Rule ID 3954 // |
| 30985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 30986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 30987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 30988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 30989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 30990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 30991 | // (ld:{ *:[v4f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 30992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 30993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 30994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 30995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 30996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 30997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 30998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 30999 | GIR_RootConstrainSelectedInstOperands, |
| 31000 | // GIR_Coverage, 3954, |
| 31001 | GIR_EraseRootFromParent_Done, |
| 31002 | // Label 1694: @101824 |
| 31003 | GIM_Try, /*On fail goto*//*Label 1695*/ GIMT_Encode4(101884), // Rule ID 3960 // |
| 31004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 31005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 31010 | // (ld:{ *:[v4bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 31012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 31015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31018 | GIR_RootConstrainSelectedInstOperands, |
| 31019 | // GIR_Coverage, 3960, |
| 31020 | GIR_EraseRootFromParent_Done, |
| 31021 | // Label 1695: @101884 |
| 31022 | GIM_Try, /*On fail goto*//*Label 1696*/ GIMT_Encode4(101944), // Rule ID 3966 // |
| 31023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 31024 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31025 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 31029 | // (ld:{ *:[v4i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SVS:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SVS), |
| 31031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 31034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31037 | GIR_RootConstrainSelectedInstOperands, |
| 31038 | // GIR_Coverage, 3966, |
| 31039 | GIR_EraseRootFromParent_Done, |
| 31040 | // Label 1696: @101944 |
| 31041 | GIM_Try, /*On fail goto*//*Label 1697*/ GIMT_Encode4(101999), // Rule ID 3953 // |
| 31042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31043 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 31048 | // (ld:{ *:[v4f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 31049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 31050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31054 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31055 | GIR_RootConstrainSelectedInstOperands, |
| 31056 | // GIR_Coverage, 3953, |
| 31057 | GIR_EraseRootFromParent_Done, |
| 31058 | // Label 1697: @101999 |
| 31059 | GIM_Try, /*On fail goto*//*Label 1698*/ GIMT_Encode4(102054), // Rule ID 3959 // |
| 31060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31061 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31062 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31064 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31065 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 31066 | // (ld:{ *:[v4bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 31067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 31068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31073 | GIR_RootConstrainSelectedInstOperands, |
| 31074 | // GIR_Coverage, 3959, |
| 31075 | GIR_EraseRootFromParent_Done, |
| 31076 | // Label 1698: @102054 |
| 31077 | GIM_Try, /*On fail goto*//*Label 1699*/ GIMT_Encode4(102109), // Rule ID 3965 // |
| 31078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31079 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31080 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31082 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 31084 | // (ld:{ *:[v4i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 31085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2_SADDR), |
| 31086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31090 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31091 | GIR_RootConstrainSelectedInstOperands, |
| 31092 | // GIR_Coverage, 3965, |
| 31093 | GIR_EraseRootFromParent_Done, |
| 31094 | // Label 1699: @102109 |
| 31095 | GIM_Try, /*On fail goto*//*Label 1700*/ GIMT_Encode4(102164), // Rule ID 3952 // |
| 31096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31097 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31098 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31099 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31100 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 31102 | // (ld:{ *:[v4f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 31104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31108 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31109 | GIR_RootConstrainSelectedInstOperands, |
| 31110 | // GIR_Coverage, 3952, |
| 31111 | GIR_EraseRootFromParent_Done, |
| 31112 | // Label 1700: @102164 |
| 31113 | GIM_Try, /*On fail goto*//*Label 1701*/ GIMT_Encode4(102219), // Rule ID 3958 // |
| 31114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31115 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31116 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 31120 | // (ld:{ *:[v4bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 31122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31127 | GIR_RootConstrainSelectedInstOperands, |
| 31128 | // GIR_Coverage, 3958, |
| 31129 | GIR_EraseRootFromParent_Done, |
| 31130 | // Label 1701: @102219 |
| 31131 | GIM_Try, /*On fail goto*//*Label 1702*/ GIMT_Encode4(102274), // Rule ID 3964 // |
| 31132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 31133 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 31134 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31136 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31137 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 31138 | // (ld:{ *:[v4i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX2), |
| 31140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31145 | GIR_RootConstrainSelectedInstOperands, |
| 31146 | // GIR_Coverage, 3964, |
| 31147 | GIR_EraseRootFromParent_Done, |
| 31148 | // Label 1702: @102274 |
| 31149 | GIM_Try, /*On fail goto*//*Label 1703*/ GIMT_Encode4(102344), // Rule ID 4182 // |
| 31150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31151 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31152 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31155 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31156 | // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 31158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31166 | GIR_RootConstrainSelectedInstOperands, |
| 31167 | // GIR_Coverage, 4182, |
| 31168 | GIR_EraseRootFromParent_Done, |
| 31169 | // Label 1703: @102344 |
| 31170 | GIM_Try, /*On fail goto*//*Label 1704*/ GIMT_Encode4(102411), // Rule ID 4184 // |
| 31171 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31172 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31176 | // (ld:{ *:[v4f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 31178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31185 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31186 | GIR_RootConstrainSelectedInstOperands, |
| 31187 | // GIR_Coverage, 4184, |
| 31188 | GIR_EraseRootFromParent_Done, |
| 31189 | // Label 1704: @102411 |
| 31190 | GIM_Try, /*On fail goto*//*Label 1705*/ GIMT_Encode4(102481), // Rule ID 4186 // |
| 31191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31192 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31193 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31197 | // (ld:{ *:[v4bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 31199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31207 | GIR_RootConstrainSelectedInstOperands, |
| 31208 | // GIR_Coverage, 4186, |
| 31209 | GIR_EraseRootFromParent_Done, |
| 31210 | // Label 1705: @102481 |
| 31211 | GIM_Try, /*On fail goto*//*Label 1706*/ GIMT_Encode4(102548), // Rule ID 4188 // |
| 31212 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31213 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31214 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31217 | // (ld:{ *:[v4bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 31219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31226 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31227 | GIR_RootConstrainSelectedInstOperands, |
| 31228 | // GIR_Coverage, 4188, |
| 31229 | GIR_EraseRootFromParent_Done, |
| 31230 | // Label 1706: @102548 |
| 31231 | GIM_Try, /*On fail goto*//*Label 1707*/ GIMT_Encode4(102618), // Rule ID 4190 // |
| 31232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31233 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31234 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31236 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31237 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31238 | // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_ADDR64), |
| 31240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31248 | GIR_RootConstrainSelectedInstOperands, |
| 31249 | // GIR_Coverage, 4190, |
| 31250 | GIR_EraseRootFromParent_Done, |
| 31251 | // Label 1707: @102618 |
| 31252 | GIM_Try, /*On fail goto*//*Label 1708*/ GIMT_Encode4(102685), // Rule ID 4192 // |
| 31253 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31254 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31256 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 31258 | // (ld:{ *:[v4i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64:{ *:[v4i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_ADDR64), |
| 31260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 31262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 31264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 31265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31267 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31268 | GIR_RootConstrainSelectedInstOperands, |
| 31269 | // GIR_Coverage, 4192, |
| 31270 | GIR_EraseRootFromParent_Done, |
| 31271 | // Label 1708: @102685 |
| 31272 | GIM_Try, /*On fail goto*//*Label 1709*/ GIMT_Encode4(102749), // Rule ID 7559 // |
| 31273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 31274 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31275 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31278 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31279 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31280 | // (AMDGPUld_glue:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 31282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31287 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31288 | GIR_RootConstrainSelectedInstOperands, |
| 31289 | // GIR_Coverage, 7559, |
| 31290 | GIR_EraseRootFromParent_Done, |
| 31291 | // Label 1709: @102749 |
| 31292 | GIM_Try, /*On fail goto*//*Label 1710*/ GIMT_Encode4(102813), // Rule ID 7563 // |
| 31293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 31294 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31295 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31296 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31300 | // (AMDGPUld_glue:{ *:[v4bf16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 31302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31308 | GIR_RootConstrainSelectedInstOperands, |
| 31309 | // GIR_Coverage, 7563, |
| 31310 | GIR_EraseRootFromParent_Done, |
| 31311 | // Label 1710: @102813 |
| 31312 | GIM_Try, /*On fail goto*//*Label 1711*/ GIMT_Encode4(102877), // Rule ID 7567 // |
| 31313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 31314 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31315 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31316 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31318 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31320 | // (AMDGPUld_glue:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B32:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32), |
| 31322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31328 | GIR_RootConstrainSelectedInstOperands, |
| 31329 | // GIR_Coverage, 7567, |
| 31330 | GIR_EraseRootFromParent_Done, |
| 31331 | // Label 1711: @102877 |
| 31332 | GIM_Try, /*On fail goto*//*Label 1712*/ GIMT_Encode4(102942), // Rule ID 4181 // |
| 31333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31334 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31335 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31337 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31339 | // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 31341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31348 | GIR_RootConstrainSelectedInstOperands, |
| 31349 | // GIR_Coverage, 4181, |
| 31350 | GIR_EraseRootFromParent_Done, |
| 31351 | // Label 1712: @102942 |
| 31352 | GIM_Try, /*On fail goto*//*Label 1713*/ GIMT_Encode4(103004), // Rule ID 4183 // |
| 31353 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31354 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31356 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31357 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31358 | // (ld:{ *:[v4f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 31360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31367 | GIR_RootConstrainSelectedInstOperands, |
| 31368 | // GIR_Coverage, 4183, |
| 31369 | GIR_EraseRootFromParent_Done, |
| 31370 | // Label 1713: @103004 |
| 31371 | GIM_Try, /*On fail goto*//*Label 1714*/ GIMT_Encode4(103069), // Rule ID 4185 // |
| 31372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31373 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31374 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31378 | // (ld:{ *:[v4bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 31380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31387 | GIR_RootConstrainSelectedInstOperands, |
| 31388 | // GIR_Coverage, 4185, |
| 31389 | GIR_EraseRootFromParent_Done, |
| 31390 | // Label 1714: @103069 |
| 31391 | GIM_Try, /*On fail goto*//*Label 1715*/ GIMT_Encode4(103131), // Rule ID 4187 // |
| 31392 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31393 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31395 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31397 | // (ld:{ *:[v4bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 31399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31406 | GIR_RootConstrainSelectedInstOperands, |
| 31407 | // GIR_Coverage, 4187, |
| 31408 | GIR_EraseRootFromParent_Done, |
| 31409 | // Label 1715: @103131 |
| 31410 | GIM_Try, /*On fail goto*//*Label 1716*/ GIMT_Encode4(103196), // Rule ID 4189 // |
| 31411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 31412 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31413 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31415 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31417 | // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 31419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31426 | GIR_RootConstrainSelectedInstOperands, |
| 31427 | // GIR_Coverage, 4189, |
| 31428 | GIR_EraseRootFromParent_Done, |
| 31429 | // Label 1716: @103196 |
| 31430 | GIM_Try, /*On fail goto*//*Label 1717*/ GIMT_Encode4(103258), // Rule ID 4191 // |
| 31431 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31432 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31434 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 31436 | // (ld:{ *:[v4i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 31437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 31438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 31439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 31440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31445 | GIR_RootConstrainSelectedInstOperands, |
| 31446 | // GIR_Coverage, 4191, |
| 31447 | GIR_EraseRootFromParent_Done, |
| 31448 | // Label 1717: @103258 |
| 31449 | GIM_Try, /*On fail goto*//*Label 1718*/ GIMT_Encode4(103318), // Rule ID 7561 // |
| 31450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 31451 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31452 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31454 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31456 | // (ld:{ *:[v4f16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[v4f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 31458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31463 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31464 | GIR_RootConstrainSelectedInstOperands, |
| 31465 | // GIR_Coverage, 7561, |
| 31466 | GIR_EraseRootFromParent_Done, |
| 31467 | // Label 1718: @103318 |
| 31468 | GIM_Try, /*On fail goto*//*Label 1719*/ GIMT_Encode4(103378), // Rule ID 7565 // |
| 31469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 31470 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31471 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31472 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31473 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31475 | // (ld:{ *:[v4bf16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[v4bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 31477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31483 | GIR_RootConstrainSelectedInstOperands, |
| 31484 | // GIR_Coverage, 7565, |
| 31485 | GIR_EraseRootFromParent_Done, |
| 31486 | // Label 1719: @103378 |
| 31487 | GIM_Try, /*On fail goto*//*Label 1720*/ GIMT_Encode4(103438), // Rule ID 7569 // |
| 31488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 31489 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 31490 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31492 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31493 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 31494 | // (ld:{ *:[v4i16] } (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B32_gfx9:{ *:[v4i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 31495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B32_gfx9), |
| 31496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 31498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 31499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 31500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31502 | GIR_RootConstrainSelectedInstOperands, |
| 31503 | // GIR_Coverage, 7569, |
| 31504 | GIR_EraseRootFromParent_Done, |
| 31505 | // Label 1720: @103438 |
| 31506 | GIM_Try, /*On fail goto*//*Label 1721*/ GIMT_Encode4(103500), // Rule ID 3501 // |
| 31507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31508 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31509 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 31513 | // (ld:{ *:[v4f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 31515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 31518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31520 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31521 | GIR_RootConstrainSelectedInstOperands, |
| 31522 | // GIR_Coverage, 3501, |
| 31523 | GIR_EraseRootFromParent_Done, |
| 31524 | // Label 1721: @103500 |
| 31525 | GIM_Try, /*On fail goto*//*Label 1722*/ GIMT_Encode4(103562), // Rule ID 3505 // |
| 31526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31527 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 31532 | // (ld:{ *:[v4bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 31534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 31537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31539 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31540 | GIR_RootConstrainSelectedInstOperands, |
| 31541 | // GIR_Coverage, 3505, |
| 31542 | GIR_EraseRootFromParent_Done, |
| 31543 | // Label 1722: @103562 |
| 31544 | GIM_Try, /*On fail goto*//*Label 1723*/ GIMT_Encode4(103624), // Rule ID 3509 // |
| 31545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31546 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31547 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 31551 | // (ld:{ *:[v4i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2_SADDR), |
| 31553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 31555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 31556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31558 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31559 | GIR_RootConstrainSelectedInstOperands, |
| 31560 | // GIR_Coverage, 3509, |
| 31561 | GIR_EraseRootFromParent_Done, |
| 31562 | // Label 1723: @103624 |
| 31563 | GIM_Try, /*On fail goto*//*Label 1724*/ GIMT_Encode4(103681), // Rule ID 3500 // |
| 31564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31565 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31566 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31568 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31569 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 31570 | // (ld:{ *:[v4f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 31572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31577 | GIR_RootConstrainSelectedInstOperands, |
| 31578 | // GIR_Coverage, 3500, |
| 31579 | GIR_EraseRootFromParent_Done, |
| 31580 | // Label 1724: @103681 |
| 31581 | GIM_Try, /*On fail goto*//*Label 1725*/ GIMT_Encode4(103738), // Rule ID 3504 // |
| 31582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31583 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31584 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 31588 | // (ld:{ *:[v4bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 31590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31594 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31595 | GIR_RootConstrainSelectedInstOperands, |
| 31596 | // GIR_Coverage, 3504, |
| 31597 | GIR_EraseRootFromParent_Done, |
| 31598 | // Label 1725: @103738 |
| 31599 | GIM_Try, /*On fail goto*//*Label 1726*/ GIMT_Encode4(103795), // Rule ID 3508 // |
| 31600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 31601 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31602 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31604 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 31606 | // (ld:{ *:[v4i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX2), |
| 31608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31612 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31613 | GIR_RootConstrainSelectedInstOperands, |
| 31614 | // GIR_Coverage, 3508, |
| 31615 | GIR_EraseRootFromParent_Done, |
| 31616 | // Label 1726: @103795 |
| 31617 | GIM_Try, /*On fail goto*//*Label 1727*/ GIMT_Encode4(103853), // Rule ID 3256 // |
| 31618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 31619 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31620 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31623 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 31624 | // (ld:{ *:[v4f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 31626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31630 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31631 | GIR_RootConstrainSelectedInstOperands, |
| 31632 | // GIR_Coverage, 3256, |
| 31633 | GIR_EraseRootFromParent_Done, |
| 31634 | // Label 1727: @103853 |
| 31635 | GIM_Try, /*On fail goto*//*Label 1728*/ GIMT_Encode4(103911), // Rule ID 3258 // |
| 31636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 31637 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31640 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31641 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 31642 | // (ld:{ *:[v4bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 31644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31648 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31649 | GIR_RootConstrainSelectedInstOperands, |
| 31650 | // GIR_Coverage, 3258, |
| 31651 | GIR_EraseRootFromParent_Done, |
| 31652 | // Label 1728: @103911 |
| 31653 | GIM_Try, /*On fail goto*//*Label 1729*/ GIMT_Encode4(103969), // Rule ID 3260 // |
| 31654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 31655 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 31656 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 31658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 31660 | // (ld:{ *:[v4i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX2:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 31661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX2), |
| 31662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 31663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 31664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31667 | GIR_RootConstrainSelectedInstOperands, |
| 31668 | // GIR_Coverage, 3260, |
| 31669 | GIR_EraseRootFromParent_Done, |
| 31670 | // Label 1729: @103969 |
| 31671 | GIM_Reject, |
| 31672 | // Label 863: @103970 |
| 31673 | GIM_Try, /*On fail goto*//*Label 1730*/ GIMT_Encode4(104037), // Rule ID 2773 // |
| 31674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31675 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31679 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31680 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31681 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31682 | // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31690 | GIR_RootConstrainSelectedInstOperands, |
| 31691 | // GIR_Coverage, 2773, |
| 31692 | GIR_EraseRootFromParent_Done, |
| 31693 | // Label 1730: @104037 |
| 31694 | GIM_Try, /*On fail goto*//*Label 1731*/ GIMT_Encode4(104104), // Rule ID 2790 // |
| 31695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31696 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31697 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31701 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31703 | // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31710 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31711 | GIR_RootConstrainSelectedInstOperands, |
| 31712 | // GIR_Coverage, 2790, |
| 31713 | GIR_EraseRootFromParent_Done, |
| 31714 | // Label 1731: @104104 |
| 31715 | GIM_Try, /*On fail goto*//*Label 1732*/ GIMT_Encode4(104167), // Rule ID 2778 // |
| 31716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31717 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31718 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31721 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31723 | // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 31725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31730 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31731 | GIR_RootConstrainSelectedInstOperands, |
| 31732 | // GIR_Coverage, 2778, |
| 31733 | GIR_EraseRootFromParent_Done, |
| 31734 | // Label 1732: @104167 |
| 31735 | GIM_Try, /*On fail goto*//*Label 1733*/ GIMT_Encode4(104230), // Rule ID 2795 // |
| 31736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31737 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31738 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31741 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31742 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31743 | // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 31745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31751 | GIR_RootConstrainSelectedInstOperands, |
| 31752 | // GIR_Coverage, 2795, |
| 31753 | GIR_EraseRootFromParent_Done, |
| 31754 | // Label 1733: @104230 |
| 31755 | GIM_Try, /*On fail goto*//*Label 1734*/ GIMT_Encode4(104293), // Rule ID 2784 // |
| 31756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 31757 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31758 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31760 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31761 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31762 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31763 | // (ld:{ *:[v4i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31770 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31771 | GIR_RootConstrainSelectedInstOperands, |
| 31772 | // GIR_Coverage, 2784, |
| 31773 | GIR_EraseRootFromParent_Done, |
| 31774 | // Label 1734: @104293 |
| 31775 | GIM_Try, /*On fail goto*//*Label 1735*/ GIMT_Encode4(104356), // Rule ID 2801 // |
| 31776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 31777 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31778 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31780 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31781 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 31783 | // (ld:{ *:[v4f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 31789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31790 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31791 | GIR_RootConstrainSelectedInstOperands, |
| 31792 | // GIR_Coverage, 2801, |
| 31793 | GIR_EraseRootFromParent_Done, |
| 31794 | // Label 1735: @104356 |
| 31795 | GIM_Try, /*On fail goto*//*Label 1736*/ GIMT_Encode4(104418), // Rule ID 2769 // |
| 31796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 31797 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31798 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31800 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31801 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31802 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31803 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 31804 | // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 31806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31810 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31811 | GIR_RootConstrainSelectedInstOperands, |
| 31812 | // GIR_Coverage, 2769, |
| 31813 | GIR_EraseRootFromParent_Done, |
| 31814 | // Label 1736: @104418 |
| 31815 | GIM_Try, /*On fail goto*//*Label 1737*/ GIMT_Encode4(104480), // Rule ID 2770 // |
| 31816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 31817 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31818 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31819 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31820 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31821 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31822 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 31824 | // (ld:{ *:[v4i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 31826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31831 | GIR_RootConstrainSelectedInstOperands, |
| 31832 | // GIR_Coverage, 2770, |
| 31833 | GIR_EraseRootFromParent_Done, |
| 31834 | // Label 1737: @104480 |
| 31835 | GIM_Try, /*On fail goto*//*Label 1738*/ GIMT_Encode4(104542), // Rule ID 2771 // |
| 31836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 31837 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31838 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31841 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31842 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 31844 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 31845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 31846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31850 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31851 | GIR_RootConstrainSelectedInstOperands, |
| 31852 | // GIR_Coverage, 2771, |
| 31853 | GIR_EraseRootFromParent_Done, |
| 31854 | // Label 1738: @104542 |
| 31855 | GIM_Try, /*On fail goto*//*Label 1739*/ GIMT_Encode4(104607), // Rule ID 2772 // |
| 31856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31857 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31858 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31860 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31861 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31862 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31863 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 31864 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 31865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31871 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31872 | GIR_RootConstrainSelectedInstOperands, |
| 31873 | // GIR_Coverage, 2772, |
| 31874 | GIR_EraseRootFromParent_Done, |
| 31875 | // Label 1739: @104607 |
| 31876 | GIM_Try, /*On fail goto*//*Label 1740*/ GIMT_Encode4(104669), // Rule ID 2786 // |
| 31877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 31878 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31879 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31882 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31883 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31884 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 31885 | // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 31887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31892 | GIR_RootConstrainSelectedInstOperands, |
| 31893 | // GIR_Coverage, 2786, |
| 31894 | GIR_EraseRootFromParent_Done, |
| 31895 | // Label 1740: @104669 |
| 31896 | GIM_Try, /*On fail goto*//*Label 1741*/ GIMT_Encode4(104731), // Rule ID 2787 // |
| 31897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 31898 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31899 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31901 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31903 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 31905 | // (ld:{ *:[v4f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 31907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31912 | GIR_RootConstrainSelectedInstOperands, |
| 31913 | // GIR_Coverage, 2787, |
| 31914 | GIR_EraseRootFromParent_Done, |
| 31915 | // Label 1741: @104731 |
| 31916 | GIM_Try, /*On fail goto*//*Label 1742*/ GIMT_Encode4(104793), // Rule ID 2788 // |
| 31917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 31918 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31919 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31922 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31923 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31924 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 31925 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 31926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 31927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31931 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31932 | GIR_RootConstrainSelectedInstOperands, |
| 31933 | // GIR_Coverage, 2788, |
| 31934 | GIR_EraseRootFromParent_Done, |
| 31935 | // Label 1742: @104793 |
| 31936 | GIM_Try, /*On fail goto*//*Label 1743*/ GIMT_Encode4(104858), // Rule ID 2789 // |
| 31937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31938 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31939 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31940 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31941 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31942 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31943 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 31944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 31945 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 31946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 31947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31952 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31953 | GIR_RootConstrainSelectedInstOperands, |
| 31954 | // GIR_Coverage, 2789, |
| 31955 | GIR_EraseRootFromParent_Done, |
| 31956 | // Label 1743: @104858 |
| 31957 | GIM_Try, /*On fail goto*//*Label 1744*/ GIMT_Encode4(104916), // Rule ID 2775 // |
| 31958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 31959 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31960 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31963 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31964 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 31965 | // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 31966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 31967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 31970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31971 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31972 | GIR_RootConstrainSelectedInstOperands, |
| 31973 | // GIR_Coverage, 2775, |
| 31974 | GIR_EraseRootFromParent_Done, |
| 31975 | // Label 1744: @104916 |
| 31976 | GIM_Try, /*On fail goto*//*Label 1745*/ GIMT_Encode4(104974), // Rule ID 2776 // |
| 31977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 31978 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31979 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 31981 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 31982 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 31983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 31984 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 31985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 31986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 31987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 31988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 31989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 31990 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 31991 | GIR_RootConstrainSelectedInstOperands, |
| 31992 | // GIR_Coverage, 2776, |
| 31993 | GIR_EraseRootFromParent_Done, |
| 31994 | // Label 1745: @104974 |
| 31995 | GIM_Try, /*On fail goto*//*Label 1746*/ GIMT_Encode4(105035), // Rule ID 2777 // |
| 31996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 31997 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 31998 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 31999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32000 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32001 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32003 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 32005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32011 | GIR_RootConstrainSelectedInstOperands, |
| 32012 | // GIR_Coverage, 2777, |
| 32013 | GIR_EraseRootFromParent_Done, |
| 32014 | // Label 1746: @105035 |
| 32015 | GIM_Try, /*On fail goto*//*Label 1747*/ GIMT_Encode4(105093), // Rule ID 2792 // |
| 32016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 32017 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32018 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32021 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 32023 | // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 32025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32030 | GIR_RootConstrainSelectedInstOperands, |
| 32031 | // GIR_Coverage, 2792, |
| 32032 | GIR_EraseRootFromParent_Done, |
| 32033 | // Label 1747: @105093 |
| 32034 | GIM_Try, /*On fail goto*//*Label 1748*/ GIMT_Encode4(105151), // Rule ID 2793 // |
| 32035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 32036 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32037 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32039 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32040 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32042 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 32043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 32044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32048 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32049 | GIR_RootConstrainSelectedInstOperands, |
| 32050 | // GIR_Coverage, 2793, |
| 32051 | GIR_EraseRootFromParent_Done, |
| 32052 | // Label 1748: @105151 |
| 32053 | GIM_Try, /*On fail goto*//*Label 1749*/ GIMT_Encode4(105212), // Rule ID 2794 // |
| 32054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 32055 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32056 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32058 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32059 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32061 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 32063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32068 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32069 | GIR_RootConstrainSelectedInstOperands, |
| 32070 | // GIR_Coverage, 2794, |
| 32071 | GIR_EraseRootFromParent_Done, |
| 32072 | // Label 1749: @105212 |
| 32073 | GIM_Try, /*On fail goto*//*Label 1750*/ GIMT_Encode4(105280), // Rule ID 7731 // |
| 32074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 32075 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32076 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32077 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32078 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32081 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 32082 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32083 | // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 32085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32089 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32090 | GIR_RootConstrainSelectedInstOperands, |
| 32091 | // GIR_Coverage, 7731, |
| 32092 | GIR_EraseRootFromParent_Done, |
| 32093 | // Label 1750: @105280 |
| 32094 | GIM_Try, /*On fail goto*//*Label 1751*/ GIMT_Encode4(105348), // Rule ID 7735 // |
| 32095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 32096 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32097 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32098 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32099 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32101 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32102 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 32103 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32104 | // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 32106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32110 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32111 | GIR_RootConstrainSelectedInstOperands, |
| 32112 | // GIR_Coverage, 7735, |
| 32113 | GIR_EraseRootFromParent_Done, |
| 32114 | // Label 1751: @105348 |
| 32115 | GIM_Try, /*On fail goto*//*Label 1752*/ GIMT_Encode4(105411), // Rule ID 7655 // |
| 32116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 32117 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32118 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32119 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 32120 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32121 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32124 | // (AMDGPUld_glue:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 32126 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32131 | GIR_RootConstrainSelectedInstOperands, |
| 32132 | // GIR_Coverage, 7655, |
| 32133 | GIR_EraseRootFromParent_Done, |
| 32134 | // Label 1752: @105411 |
| 32135 | GIM_Try, /*On fail goto*//*Label 1753*/ GIMT_Encode4(105474), // Rule ID 7659 // |
| 32136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 32137 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32138 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32139 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 32140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32144 | // (AMDGPUld_glue:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 32146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32151 | GIR_RootConstrainSelectedInstOperands, |
| 32152 | // GIR_Coverage, 7659, |
| 32153 | GIR_EraseRootFromParent_Done, |
| 32154 | // Label 1753: @105474 |
| 32155 | GIM_Try, /*On fail goto*//*Label 1754*/ GIMT_Encode4(105529), // Rule ID 2780 // |
| 32156 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32157 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32159 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32160 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 32162 | // (ld:{ *:[v4i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32169 | GIR_RootConstrainSelectedInstOperands, |
| 32170 | // GIR_Coverage, 2780, |
| 32171 | GIR_EraseRootFromParent_Done, |
| 32172 | // Label 1754: @105529 |
| 32173 | GIM_Try, /*On fail goto*//*Label 1755*/ GIMT_Encode4(105587), // Rule ID 2781 // |
| 32174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 32175 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32179 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 32181 | // (ld:{ *:[v4i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 32183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32187 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32188 | GIR_RootConstrainSelectedInstOperands, |
| 32189 | // GIR_Coverage, 2781, |
| 32190 | GIR_EraseRootFromParent_Done, |
| 32191 | // Label 1755: @105587 |
| 32192 | GIM_Try, /*On fail goto*//*Label 1756*/ GIMT_Encode4(105645), // Rule ID 2782 // |
| 32193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 32194 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32195 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32198 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32200 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 32201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 32202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32207 | GIR_RootConstrainSelectedInstOperands, |
| 32208 | // GIR_Coverage, 2782, |
| 32209 | GIR_EraseRootFromParent_Done, |
| 32210 | // Label 1756: @105645 |
| 32211 | GIM_Try, /*On fail goto*//*Label 1757*/ GIMT_Encode4(105706), // Rule ID 2783 // |
| 32212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 32213 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32214 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32216 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32217 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32219 | // (ld:{ *:[v4i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 32221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32226 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32227 | GIR_RootConstrainSelectedInstOperands, |
| 32228 | // GIR_Coverage, 2783, |
| 32229 | GIR_EraseRootFromParent_Done, |
| 32230 | // Label 1757: @105706 |
| 32231 | GIM_Try, /*On fail goto*//*Label 1758*/ GIMT_Encode4(105761), // Rule ID 2797 // |
| 32232 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32233 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32236 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32237 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 32238 | // (ld:{ *:[v4f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32245 | GIR_RootConstrainSelectedInstOperands, |
| 32246 | // GIR_Coverage, 2797, |
| 32247 | GIR_EraseRootFromParent_Done, |
| 32248 | // Label 1758: @105761 |
| 32249 | GIM_Try, /*On fail goto*//*Label 1759*/ GIMT_Encode4(105819), // Rule ID 2798 // |
| 32250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 32251 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32252 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32254 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32255 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32256 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 32257 | // (ld:{ *:[v4f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 32259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32263 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32264 | GIR_RootConstrainSelectedInstOperands, |
| 32265 | // GIR_Coverage, 2798, |
| 32266 | GIR_EraseRootFromParent_Done, |
| 32267 | // Label 1759: @105819 |
| 32268 | GIM_Try, /*On fail goto*//*Label 1760*/ GIMT_Encode4(105877), // Rule ID 2799 // |
| 32269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 32270 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32273 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32274 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32275 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32276 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 32277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 32278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32282 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32283 | GIR_RootConstrainSelectedInstOperands, |
| 32284 | // GIR_Coverage, 2799, |
| 32285 | GIR_EraseRootFromParent_Done, |
| 32286 | // Label 1760: @105877 |
| 32287 | GIM_Try, /*On fail goto*//*Label 1761*/ GIMT_Encode4(105938), // Rule ID 2800 // |
| 32288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 32289 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32290 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32292 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32293 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32294 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 32295 | // (ld:{ *:[v4f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 32297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 32299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32302 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32303 | GIR_RootConstrainSelectedInstOperands, |
| 32304 | // GIR_Coverage, 2800, |
| 32305 | GIR_EraseRootFromParent_Done, |
| 32306 | // Label 1761: @105938 |
| 32307 | GIM_Try, /*On fail goto*//*Label 1762*/ GIMT_Encode4(106002), // Rule ID 7732 // |
| 32308 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 32309 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32310 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32311 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32314 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 32315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32316 | // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 32318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32323 | GIR_RootConstrainSelectedInstOperands, |
| 32324 | // GIR_Coverage, 7732, |
| 32325 | GIR_EraseRootFromParent_Done, |
| 32326 | // Label 1762: @106002 |
| 32327 | GIM_Try, /*On fail goto*//*Label 1763*/ GIMT_Encode4(106066), // Rule ID 7736 // |
| 32328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 32329 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32330 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32331 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 32335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32336 | // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 32338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32342 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32343 | GIR_RootConstrainSelectedInstOperands, |
| 32344 | // GIR_Coverage, 7736, |
| 32345 | GIR_EraseRootFromParent_Done, |
| 32346 | // Label 1763: @106066 |
| 32347 | GIM_Try, /*On fail goto*//*Label 1764*/ GIMT_Encode4(106125), // Rule ID 7656 // |
| 32348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 32349 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32350 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 32351 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32353 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32355 | // (ld:{ *:[v4i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 32357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32362 | GIR_RootConstrainSelectedInstOperands, |
| 32363 | // GIR_Coverage, 7656, |
| 32364 | GIR_EraseRootFromParent_Done, |
| 32365 | // Label 1764: @106125 |
| 32366 | GIM_Try, /*On fail goto*//*Label 1765*/ GIMT_Encode4(106184), // Rule ID 7660 // |
| 32367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 32368 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32369 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 32370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32372 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 32374 | // (ld:{ *:[v4f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 32375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 32376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32381 | GIR_RootConstrainSelectedInstOperands, |
| 32382 | // GIR_Coverage, 7660, |
| 32383 | GIR_EraseRootFromParent_Done, |
| 32384 | // Label 1765: @106184 |
| 32385 | GIM_Try, /*On fail goto*//*Label 1766*/ GIMT_Encode4(106238), // Rule ID 2774 // |
| 32386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 32387 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32388 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32390 | // MIs[0] sbase |
| 32391 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32392 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32393 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32394 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 32395 | // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32398 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32402 | GIR_RootConstrainSelectedInstOperands, |
| 32403 | // GIR_Coverage, 2774, |
| 32404 | GIR_EraseRootFromParent_Done, |
| 32405 | // Label 1766: @106238 |
| 32406 | GIM_Try, /*On fail goto*//*Label 1767*/ GIMT_Encode4(106292), // Rule ID 2791 // |
| 32407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 32408 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32409 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32411 | // MIs[0] sbase |
| 32412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32413 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32414 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32415 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 32416 | // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32419 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32422 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32423 | GIR_RootConstrainSelectedInstOperands, |
| 32424 | // GIR_Coverage, 2791, |
| 32425 | GIR_EraseRootFromParent_Done, |
| 32426 | // Label 1767: @106292 |
| 32427 | GIM_Try, /*On fail goto*//*Label 1768*/ GIMT_Encode4(106342), // Rule ID 2779 // |
| 32428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 32429 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32432 | // MIs[0] sbase |
| 32433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32434 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32435 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32436 | // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 32438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32439 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32443 | GIR_RootConstrainSelectedInstOperands, |
| 32444 | // GIR_Coverage, 2779, |
| 32445 | GIR_EraseRootFromParent_Done, |
| 32446 | // Label 1768: @106342 |
| 32447 | GIM_Try, /*On fail goto*//*Label 1769*/ GIMT_Encode4(106392), // Rule ID 2796 // |
| 32448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 32449 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32450 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32452 | // MIs[0] sbase |
| 32453 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32454 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32455 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32456 | // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 32458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32459 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32462 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32463 | GIR_RootConstrainSelectedInstOperands, |
| 32464 | // GIR_Coverage, 2796, |
| 32465 | GIR_EraseRootFromParent_Done, |
| 32466 | // Label 1769: @106392 |
| 32467 | GIM_Try, /*On fail goto*//*Label 1770*/ GIMT_Encode4(106439), // Rule ID 2785 // |
| 32468 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32469 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32471 | // MIs[0] sbase |
| 32472 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32473 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32474 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32475 | // (ld:{ *:[v4i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32478 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32482 | GIR_RootConstrainSelectedInstOperands, |
| 32483 | // GIR_Coverage, 2785, |
| 32484 | GIR_EraseRootFromParent_Done, |
| 32485 | // Label 1770: @106439 |
| 32486 | GIM_Try, /*On fail goto*//*Label 1771*/ GIMT_Encode4(106486), // Rule ID 2802 // |
| 32487 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32488 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 32490 | // MIs[0] sbase |
| 32491 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 32492 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 32493 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 32494 | // (ld:{ *:[v4f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v4f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 32495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 32496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 32497 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 32498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32501 | GIR_RootConstrainSelectedInstOperands, |
| 32502 | // GIR_Coverage, 2802, |
| 32503 | GIR_EraseRootFromParent_Done, |
| 32504 | // Label 1771: @106486 |
| 32505 | GIM_Try, /*On fail goto*//*Label 1772*/ GIMT_Encode4(106549), // Rule ID 6214 // |
| 32506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 32507 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 32512 | // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 32513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 32514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32520 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32521 | GIR_RootConstrainSelectedInstOperands, |
| 32522 | // GIR_Coverage, 6214, |
| 32523 | GIR_EraseRootFromParent_Done, |
| 32524 | // Label 1772: @106549 |
| 32525 | GIM_Try, /*On fail goto*//*Label 1773*/ GIMT_Encode4(106612), // Rule ID 6216 // |
| 32526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 32527 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 32532 | // (ld:{ *:[v4i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 32533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 32534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32541 | GIR_RootConstrainSelectedInstOperands, |
| 32542 | // GIR_Coverage, 6216, |
| 32543 | GIR_EraseRootFromParent_Done, |
| 32544 | // Label 1773: @106612 |
| 32545 | GIM_Try, /*On fail goto*//*Label 1774*/ GIMT_Encode4(106672), // Rule ID 3993 // |
| 32546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 32547 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32550 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 32552 | // (ld:{ *:[v4i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 32554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 32556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 32557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32559 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32560 | GIR_RootConstrainSelectedInstOperands, |
| 32561 | // GIR_Coverage, 3993, |
| 32562 | GIR_EraseRootFromParent_Done, |
| 32563 | // Label 1774: @106672 |
| 32564 | GIM_Try, /*On fail goto*//*Label 1775*/ GIMT_Encode4(106732), // Rule ID 3999 // |
| 32565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 32566 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32567 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32569 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32570 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 32571 | // (ld:{ *:[v4f32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 32573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 32575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 32576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32578 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32579 | GIR_RootConstrainSelectedInstOperands, |
| 32580 | // GIR_Coverage, 3999, |
| 32581 | GIR_EraseRootFromParent_Done, |
| 32582 | // Label 1775: @106732 |
| 32583 | GIM_Try, /*On fail goto*//*Label 1776*/ GIMT_Encode4(106787), // Rule ID 3992 // |
| 32584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 32585 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32586 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32588 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 32590 | // (ld:{ *:[v4i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 32591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 32592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 32594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32597 | GIR_RootConstrainSelectedInstOperands, |
| 32598 | // GIR_Coverage, 3992, |
| 32599 | GIR_EraseRootFromParent_Done, |
| 32600 | // Label 1776: @106787 |
| 32601 | GIM_Try, /*On fail goto*//*Label 1777*/ GIMT_Encode4(106842), // Rule ID 3998 // |
| 32602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 32603 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32606 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32607 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 32608 | // (ld:{ *:[v4f32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 32609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 32610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 32612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32614 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32615 | GIR_RootConstrainSelectedInstOperands, |
| 32616 | // GIR_Coverage, 3998, |
| 32617 | GIR_EraseRootFromParent_Done, |
| 32618 | // Label 1777: @106842 |
| 32619 | GIM_Try, /*On fail goto*//*Label 1778*/ GIMT_Encode4(106897), // Rule ID 3991 // |
| 32620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 32621 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32622 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32624 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 32626 | // (ld:{ *:[v4i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 32627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 32628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 32630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32632 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32633 | GIR_RootConstrainSelectedInstOperands, |
| 32634 | // GIR_Coverage, 3991, |
| 32635 | GIR_EraseRootFromParent_Done, |
| 32636 | // Label 1778: @106897 |
| 32637 | GIM_Try, /*On fail goto*//*Label 1779*/ GIMT_Encode4(106952), // Rule ID 3997 // |
| 32638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 32639 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32640 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32642 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32643 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 32644 | // (ld:{ *:[v4f32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 32645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 32646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 32648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32650 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32651 | GIR_RootConstrainSelectedInstOperands, |
| 32652 | // GIR_Coverage, 3997, |
| 32653 | GIR_EraseRootFromParent_Done, |
| 32654 | // Label 1779: @106952 |
| 32655 | GIM_Try, /*On fail goto*//*Label 1780*/ GIMT_Encode4(107022), // Rule ID 4214 // |
| 32656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 32657 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32658 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32660 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 32662 | // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 32664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32671 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32672 | GIR_RootConstrainSelectedInstOperands, |
| 32673 | // GIR_Coverage, 4214, |
| 32674 | GIR_EraseRootFromParent_Done, |
| 32675 | // Label 1780: @107022 |
| 32676 | GIM_Try, /*On fail goto*//*Label 1781*/ GIMT_Encode4(107089), // Rule ID 4216 // |
| 32677 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32678 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32680 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32681 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 32682 | // (ld:{ *:[v4i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 32684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32692 | GIR_RootConstrainSelectedInstOperands, |
| 32693 | // GIR_Coverage, 4216, |
| 32694 | GIR_EraseRootFromParent_Done, |
| 32695 | // Label 1781: @107089 |
| 32696 | GIM_Try, /*On fail goto*//*Label 1782*/ GIMT_Encode4(107159), // Rule ID 4218 // |
| 32697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 32698 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32699 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32701 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 32703 | // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 32705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32713 | GIR_RootConstrainSelectedInstOperands, |
| 32714 | // GIR_Coverage, 4218, |
| 32715 | GIR_EraseRootFromParent_Done, |
| 32716 | // Label 1782: @107159 |
| 32717 | GIM_Try, /*On fail goto*//*Label 1783*/ GIMT_Encode4(107226), // Rule ID 4220 // |
| 32718 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32719 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 32723 | // (ld:{ *:[v4f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v4f32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 32725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32732 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32733 | GIR_RootConstrainSelectedInstOperands, |
| 32734 | // GIR_Coverage, 4220, |
| 32735 | GIR_EraseRootFromParent_Done, |
| 32736 | // Label 1783: @107226 |
| 32737 | GIM_Try, /*On fail goto*//*Label 1784*/ GIMT_Encode4(107294), // Rule ID 6213 // |
| 32738 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 32739 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32740 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32742 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 32744 | // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 32745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 32746 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32753 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32754 | GIR_RootConstrainSelectedInstOperands, |
| 32755 | // GIR_Coverage, 6213, |
| 32756 | GIR_EraseRootFromParent_Done, |
| 32757 | // Label 1784: @107294 |
| 32758 | GIM_Try, /*On fail goto*//*Label 1785*/ GIMT_Encode4(107362), // Rule ID 6215 // |
| 32759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 32760 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 32761 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 32765 | // (ld:{ *:[v4i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 32766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 32767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 32769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 32771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 32772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32774 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32775 | GIR_RootConstrainSelectedInstOperands, |
| 32776 | // GIR_Coverage, 6215, |
| 32777 | GIR_EraseRootFromParent_Done, |
| 32778 | // Label 1785: @107362 |
| 32779 | GIM_Try, /*On fail goto*//*Label 1786*/ GIMT_Encode4(107426), // Rule ID 7543 // |
| 32780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 32781 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32782 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32783 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 32787 | // (AMDGPUld_glue:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 32788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 32789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 32792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 32793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32795 | GIR_RootConstrainSelectedInstOperands, |
| 32796 | // GIR_Coverage, 7543, |
| 32797 | GIR_EraseRootFromParent_Done, |
| 32798 | // Label 1786: @107426 |
| 32799 | GIM_Try, /*On fail goto*//*Label 1787*/ GIMT_Encode4(107490), // Rule ID 7583 // |
| 32800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 32801 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 32802 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32803 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 32807 | // (AMDGPUld_glue:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 32808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 32809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 32812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 32813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32815 | GIR_RootConstrainSelectedInstOperands, |
| 32816 | // GIR_Coverage, 7583, |
| 32817 | GIR_EraseRootFromParent_Done, |
| 32818 | // Label 1787: @107490 |
| 32819 | GIM_Try, /*On fail goto*//*Label 1788*/ GIMT_Encode4(107555), // Rule ID 4213 // |
| 32820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 32821 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32825 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 32826 | // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 32828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32834 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32835 | GIR_RootConstrainSelectedInstOperands, |
| 32836 | // GIR_Coverage, 4213, |
| 32837 | GIR_EraseRootFromParent_Done, |
| 32838 | // Label 1788: @107555 |
| 32839 | GIM_Try, /*On fail goto*//*Label 1789*/ GIMT_Encode4(107617), // Rule ID 4215 // |
| 32840 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32841 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32843 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 32845 | // (ld:{ *:[v4i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 32847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32854 | GIR_RootConstrainSelectedInstOperands, |
| 32855 | // GIR_Coverage, 4215, |
| 32856 | GIR_EraseRootFromParent_Done, |
| 32857 | // Label 1789: @107617 |
| 32858 | GIM_Try, /*On fail goto*//*Label 1790*/ GIMT_Encode4(107682), // Rule ID 4217 // |
| 32859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 32860 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32861 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 32865 | // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 32867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32873 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32874 | GIR_RootConstrainSelectedInstOperands, |
| 32875 | // GIR_Coverage, 4217, |
| 32876 | GIR_EraseRootFromParent_Done, |
| 32877 | // Label 1790: @107682 |
| 32878 | GIM_Try, /*On fail goto*//*Label 1791*/ GIMT_Encode4(107744), // Rule ID 4219 // |
| 32879 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32880 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32882 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 32884 | // (ld:{ *:[v4f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 32885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 32886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 32887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 32888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 32889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32892 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32893 | GIR_RootConstrainSelectedInstOperands, |
| 32894 | // GIR_Coverage, 4219, |
| 32895 | GIR_EraseRootFromParent_Done, |
| 32896 | // Label 1791: @107744 |
| 32897 | GIM_Try, /*On fail goto*//*Label 1792*/ GIMT_Encode4(107804), // Rule ID 7545 // |
| 32898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 32899 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32900 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32902 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32903 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 32904 | // (ld:{ *:[v4i32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v4i32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 32905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 32906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 32909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 32910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32912 | GIR_RootConstrainSelectedInstOperands, |
| 32913 | // GIR_Coverage, 7545, |
| 32914 | GIR_EraseRootFromParent_Done, |
| 32915 | // Label 1792: @107804 |
| 32916 | GIM_Try, /*On fail goto*//*Label 1793*/ GIMT_Encode4(107864), // Rule ID 7585 // |
| 32917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 32918 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 32919 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 32923 | // (ld:{ *:[v4f32] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v4f32] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 32924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 32925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 32927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 32928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 32929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32930 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32931 | GIR_RootConstrainSelectedInstOperands, |
| 32932 | // GIR_Coverage, 7585, |
| 32933 | GIR_EraseRootFromParent_Done, |
| 32934 | // Label 1793: @107864 |
| 32935 | GIM_Try, /*On fail goto*//*Label 1794*/ GIMT_Encode4(107926), // Rule ID 3527 // |
| 32936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 32937 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32938 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32941 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 32942 | // (ld:{ *:[v4i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 32944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 32946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 32947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32950 | GIR_RootConstrainSelectedInstOperands, |
| 32951 | // GIR_Coverage, 3527, |
| 32952 | GIR_EraseRootFromParent_Done, |
| 32953 | // Label 1794: @107926 |
| 32954 | GIM_Try, /*On fail goto*//*Label 1795*/ GIMT_Encode4(107988), // Rule ID 3531 // |
| 32955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 32956 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32957 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32959 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 32961 | // (ld:{ *:[v4f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v4f32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 32962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 32963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 32965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 32966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 32967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32969 | GIR_RootConstrainSelectedInstOperands, |
| 32970 | // GIR_Coverage, 3531, |
| 32971 | GIR_EraseRootFromParent_Done, |
| 32972 | // Label 1795: @107988 |
| 32973 | GIM_Try, /*On fail goto*//*Label 1796*/ GIMT_Encode4(108045), // Rule ID 3526 // |
| 32974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 32975 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 32980 | // (ld:{ *:[v4i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 32981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 32982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 32983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 32984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 32985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 32986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 32987 | GIR_RootConstrainSelectedInstOperands, |
| 32988 | // GIR_Coverage, 3526, |
| 32989 | GIR_EraseRootFromParent_Done, |
| 32990 | // Label 1796: @108045 |
| 32991 | GIM_Try, /*On fail goto*//*Label 1797*/ GIMT_Encode4(108102), // Rule ID 3530 // |
| 32992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 32993 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 32994 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 32995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 32996 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 32997 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 32998 | // (ld:{ *:[v4f32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 32999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 33000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 33001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 33002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33004 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33005 | GIR_RootConstrainSelectedInstOperands, |
| 33006 | // GIR_Coverage, 3530, |
| 33007 | GIR_EraseRootFromParent_Done, |
| 33008 | // Label 1797: @108102 |
| 33009 | GIM_Try, /*On fail goto*//*Label 1798*/ GIMT_Encode4(108160), // Rule ID 3268 // |
| 33010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 33011 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 33012 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 33014 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 33016 | // (ld:{ *:[v4i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v4i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 33017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 33018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 33019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 33020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33023 | GIR_RootConstrainSelectedInstOperands, |
| 33024 | // GIR_Coverage, 3268, |
| 33025 | GIR_EraseRootFromParent_Done, |
| 33026 | // Label 1798: @108160 |
| 33027 | GIM_Try, /*On fail goto*//*Label 1799*/ GIMT_Encode4(108218), // Rule ID 3270 // |
| 33028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 33029 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 33030 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 33032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 33034 | // (ld:{ *:[v4f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v4f32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 33035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 33036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 33037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 33038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33041 | GIR_RootConstrainSelectedInstOperands, |
| 33042 | // GIR_Coverage, 3270, |
| 33043 | GIR_EraseRootFromParent_Done, |
| 33044 | // Label 1799: @108218 |
| 33045 | GIM_Reject, |
| 33046 | // Label 864: @108219 |
| 33047 | GIM_Try, /*On fail goto*//*Label 1800*/ GIMT_Encode4(109969), |
| 33048 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33049 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33050 | GIM_Try, /*On fail goto*//*Label 1801*/ GIMT_Encode4(108291), // Rule ID 2926 // |
| 33051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33052 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33055 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33057 | // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33065 | GIR_RootConstrainSelectedInstOperands, |
| 33066 | // GIR_Coverage, 2926, |
| 33067 | GIR_EraseRootFromParent_Done, |
| 33068 | // Label 1801: @108291 |
| 33069 | GIM_Try, /*On fail goto*//*Label 1802*/ GIMT_Encode4(108350), // Rule ID 2943 // |
| 33070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33071 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33074 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33075 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33076 | // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33084 | GIR_RootConstrainSelectedInstOperands, |
| 33085 | // GIR_Coverage, 2943, |
| 33086 | GIR_EraseRootFromParent_Done, |
| 33087 | // Label 1802: @108350 |
| 33088 | GIM_Try, /*On fail goto*//*Label 1803*/ GIMT_Encode4(108405), // Rule ID 2931 // |
| 33089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33090 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33092 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33093 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33094 | // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 33096 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33102 | GIR_RootConstrainSelectedInstOperands, |
| 33103 | // GIR_Coverage, 2931, |
| 33104 | GIR_EraseRootFromParent_Done, |
| 33105 | // Label 1803: @108405 |
| 33106 | GIM_Try, /*On fail goto*//*Label 1804*/ GIMT_Encode4(108460), // Rule ID 2948 // |
| 33107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33108 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33112 | // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 33114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33119 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33120 | GIR_RootConstrainSelectedInstOperands, |
| 33121 | // GIR_Coverage, 2948, |
| 33122 | GIR_EraseRootFromParent_Done, |
| 33123 | // Label 1804: @108460 |
| 33124 | GIM_Try, /*On fail goto*//*Label 1805*/ GIMT_Encode4(108515), // Rule ID 2937 // |
| 33125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33126 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33128 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33130 | // (ld:{ *:[v4i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33138 | GIR_RootConstrainSelectedInstOperands, |
| 33139 | // GIR_Coverage, 2937, |
| 33140 | GIR_EraseRootFromParent_Done, |
| 33141 | // Label 1805: @108515 |
| 33142 | GIM_Try, /*On fail goto*//*Label 1806*/ GIMT_Encode4(108570), // Rule ID 2954 // |
| 33143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33144 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33148 | // (ld:{ *:[v4f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33155 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33156 | GIR_RootConstrainSelectedInstOperands, |
| 33157 | // GIR_Coverage, 2954, |
| 33158 | GIR_EraseRootFromParent_Done, |
| 33159 | // Label 1806: @108570 |
| 33160 | GIM_Try, /*On fail goto*//*Label 1807*/ GIMT_Encode4(108624), // Rule ID 2922 // |
| 33161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33162 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33164 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33165 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33166 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33167 | // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33173 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33174 | GIR_RootConstrainSelectedInstOperands, |
| 33175 | // GIR_Coverage, 2922, |
| 33176 | GIR_EraseRootFromParent_Done, |
| 33177 | // Label 1807: @108624 |
| 33178 | GIM_Try, /*On fail goto*//*Label 1808*/ GIMT_Encode4(108678), // Rule ID 2923 // |
| 33179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 33180 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33182 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33183 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33185 | // (ld:{ *:[v4i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 33187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33191 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33192 | GIR_RootConstrainSelectedInstOperands, |
| 33193 | // GIR_Coverage, 2923, |
| 33194 | GIR_EraseRootFromParent_Done, |
| 33195 | // Label 1808: @108678 |
| 33196 | GIM_Try, /*On fail goto*//*Label 1809*/ GIMT_Encode4(108732), // Rule ID 2924 // |
| 33197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33200 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33201 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33203 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 33205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33210 | GIR_RootConstrainSelectedInstOperands, |
| 33211 | // GIR_Coverage, 2924, |
| 33212 | GIR_EraseRootFromParent_Done, |
| 33213 | // Label 1809: @108732 |
| 33214 | GIM_Try, /*On fail goto*//*Label 1810*/ GIMT_Encode4(108789), // Rule ID 2925 // |
| 33215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33216 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33218 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33219 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33221 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33229 | GIR_RootConstrainSelectedInstOperands, |
| 33230 | // GIR_Coverage, 2925, |
| 33231 | GIR_EraseRootFromParent_Done, |
| 33232 | // Label 1810: @108789 |
| 33233 | GIM_Try, /*On fail goto*//*Label 1811*/ GIMT_Encode4(108843), // Rule ID 2939 // |
| 33234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33235 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33238 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33239 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33240 | // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33246 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33247 | GIR_RootConstrainSelectedInstOperands, |
| 33248 | // GIR_Coverage, 2939, |
| 33249 | GIR_EraseRootFromParent_Done, |
| 33250 | // Label 1811: @108843 |
| 33251 | GIM_Try, /*On fail goto*//*Label 1812*/ GIMT_Encode4(108897), // Rule ID 2940 // |
| 33252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 33253 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33255 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33256 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33258 | // (ld:{ *:[v4f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 33260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33264 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33265 | GIR_RootConstrainSelectedInstOperands, |
| 33266 | // GIR_Coverage, 2940, |
| 33267 | GIR_EraseRootFromParent_Done, |
| 33268 | // Label 1812: @108897 |
| 33269 | GIM_Try, /*On fail goto*//*Label 1813*/ GIMT_Encode4(108951), // Rule ID 2941 // |
| 33270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33273 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33274 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33275 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33276 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 33278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33282 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33283 | GIR_RootConstrainSelectedInstOperands, |
| 33284 | // GIR_Coverage, 2941, |
| 33285 | GIR_EraseRootFromParent_Done, |
| 33286 | // Label 1813: @108951 |
| 33287 | GIM_Try, /*On fail goto*//*Label 1814*/ GIMT_Encode4(109008), // Rule ID 2942 // |
| 33288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33289 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33292 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33293 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33294 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33302 | GIR_RootConstrainSelectedInstOperands, |
| 33303 | // GIR_Coverage, 2942, |
| 33304 | GIR_EraseRootFromParent_Done, |
| 33305 | // Label 1814: @109008 |
| 33306 | GIM_Try, /*On fail goto*//*Label 1815*/ GIMT_Encode4(109058), // Rule ID 2928 // |
| 33307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33308 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33310 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33311 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33312 | // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 33314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33318 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33319 | GIR_RootConstrainSelectedInstOperands, |
| 33320 | // GIR_Coverage, 2928, |
| 33321 | GIR_EraseRootFromParent_Done, |
| 33322 | // Label 1815: @109058 |
| 33323 | GIM_Try, /*On fail goto*//*Label 1816*/ GIMT_Encode4(109108), // Rule ID 2929 // |
| 33324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33327 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33329 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 33331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33335 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33336 | GIR_RootConstrainSelectedInstOperands, |
| 33337 | // GIR_Coverage, 2929, |
| 33338 | GIR_EraseRootFromParent_Done, |
| 33339 | // Label 1816: @109108 |
| 33340 | GIM_Try, /*On fail goto*//*Label 1817*/ GIMT_Encode4(109161), // Rule ID 2930 // |
| 33341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33346 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 33348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33354 | GIR_RootConstrainSelectedInstOperands, |
| 33355 | // GIR_Coverage, 2930, |
| 33356 | GIR_EraseRootFromParent_Done, |
| 33357 | // Label 1817: @109161 |
| 33358 | GIM_Try, /*On fail goto*//*Label 1818*/ GIMT_Encode4(109211), // Rule ID 2945 // |
| 33359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33364 | // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 33366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33371 | GIR_RootConstrainSelectedInstOperands, |
| 33372 | // GIR_Coverage, 2945, |
| 33373 | GIR_EraseRootFromParent_Done, |
| 33374 | // Label 1818: @109211 |
| 33375 | GIM_Try, /*On fail goto*//*Label 1819*/ GIMT_Encode4(109261), // Rule ID 2946 // |
| 33376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33377 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33381 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 33383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33387 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33388 | GIR_RootConstrainSelectedInstOperands, |
| 33389 | // GIR_Coverage, 2946, |
| 33390 | GIR_EraseRootFromParent_Done, |
| 33391 | // Label 1819: @109261 |
| 33392 | GIM_Try, /*On fail goto*//*Label 1820*/ GIMT_Encode4(109314), // Rule ID 2947 // |
| 33393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33394 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33396 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33397 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33398 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 33400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33406 | GIR_RootConstrainSelectedInstOperands, |
| 33407 | // GIR_Coverage, 2947, |
| 33408 | GIR_EraseRootFromParent_Done, |
| 33409 | // Label 1820: @109314 |
| 33410 | GIM_Try, /*On fail goto*//*Label 1821*/ GIMT_Encode4(109361), // Rule ID 2933 // |
| 33411 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33413 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33415 | // (ld:{ *:[v4i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33422 | GIR_RootConstrainSelectedInstOperands, |
| 33423 | // GIR_Coverage, 2933, |
| 33424 | GIR_EraseRootFromParent_Done, |
| 33425 | // Label 1821: @109361 |
| 33426 | GIM_Try, /*On fail goto*//*Label 1822*/ GIMT_Encode4(109411), // Rule ID 2934 // |
| 33427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 33428 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33430 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33432 | // (ld:{ *:[v4i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 33434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33438 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33439 | GIR_RootConstrainSelectedInstOperands, |
| 33440 | // GIR_Coverage, 2934, |
| 33441 | GIR_EraseRootFromParent_Done, |
| 33442 | // Label 1822: @109411 |
| 33443 | GIM_Try, /*On fail goto*//*Label 1823*/ GIMT_Encode4(109461), // Rule ID 2935 // |
| 33444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 33445 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33447 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33449 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 33451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33455 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33456 | GIR_RootConstrainSelectedInstOperands, |
| 33457 | // GIR_Coverage, 2935, |
| 33458 | GIR_EraseRootFromParent_Done, |
| 33459 | // Label 1823: @109461 |
| 33460 | GIM_Try, /*On fail goto*//*Label 1824*/ GIMT_Encode4(109514), // Rule ID 2936 // |
| 33461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33464 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33466 | // (ld:{ *:[v4i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33474 | GIR_RootConstrainSelectedInstOperands, |
| 33475 | // GIR_Coverage, 2936, |
| 33476 | GIR_EraseRootFromParent_Done, |
| 33477 | // Label 1824: @109514 |
| 33478 | GIM_Try, /*On fail goto*//*Label 1825*/ GIMT_Encode4(109561), // Rule ID 2950 // |
| 33479 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33483 | // (ld:{ *:[v4f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33490 | GIR_RootConstrainSelectedInstOperands, |
| 33491 | // GIR_Coverage, 2950, |
| 33492 | GIR_EraseRootFromParent_Done, |
| 33493 | // Label 1825: @109561 |
| 33494 | GIM_Try, /*On fail goto*//*Label 1826*/ GIMT_Encode4(109611), // Rule ID 2951 // |
| 33495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 33496 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33498 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33500 | // (ld:{ *:[v4f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 33502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33507 | GIR_RootConstrainSelectedInstOperands, |
| 33508 | // GIR_Coverage, 2951, |
| 33509 | GIR_EraseRootFromParent_Done, |
| 33510 | // Label 1826: @109611 |
| 33511 | GIM_Try, /*On fail goto*//*Label 1827*/ GIMT_Encode4(109661), // Rule ID 2952 // |
| 33512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 33513 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33517 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 33519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33523 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33524 | GIR_RootConstrainSelectedInstOperands, |
| 33525 | // GIR_Coverage, 2952, |
| 33526 | GIR_EraseRootFromParent_Done, |
| 33527 | // Label 1827: @109661 |
| 33528 | GIM_Try, /*On fail goto*//*Label 1828*/ GIMT_Encode4(109714), // Rule ID 2953 // |
| 33529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33530 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33534 | // (ld:{ *:[v4f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v4f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 33536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33541 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33542 | GIR_RootConstrainSelectedInstOperands, |
| 33543 | // GIR_Coverage, 2953, |
| 33544 | GIR_EraseRootFromParent_Done, |
| 33545 | // Label 1828: @109714 |
| 33546 | GIM_Try, /*On fail goto*//*Label 1829*/ GIMT_Encode4(109760), // Rule ID 2927 // |
| 33547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33550 | // MIs[0] sbase |
| 33551 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33552 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33553 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33554 | // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33557 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33560 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33561 | GIR_RootConstrainSelectedInstOperands, |
| 33562 | // GIR_Coverage, 2927, |
| 33563 | GIR_EraseRootFromParent_Done, |
| 33564 | // Label 1829: @109760 |
| 33565 | GIM_Try, /*On fail goto*//*Label 1830*/ GIMT_Encode4(109806), // Rule ID 2944 // |
| 33566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33567 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33568 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33569 | // MIs[0] sbase |
| 33570 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33571 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33572 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33573 | // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33576 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33579 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33580 | GIR_RootConstrainSelectedInstOperands, |
| 33581 | // GIR_Coverage, 2944, |
| 33582 | GIR_EraseRootFromParent_Done, |
| 33583 | // Label 1830: @109806 |
| 33584 | GIM_Try, /*On fail goto*//*Label 1831*/ GIMT_Encode4(109848), // Rule ID 2932 // |
| 33585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33586 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33588 | // MIs[0] sbase |
| 33589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33590 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33591 | // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 33593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33594 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33598 | GIR_RootConstrainSelectedInstOperands, |
| 33599 | // GIR_Coverage, 2932, |
| 33600 | GIR_EraseRootFromParent_Done, |
| 33601 | // Label 1831: @109848 |
| 33602 | GIM_Try, /*On fail goto*//*Label 1832*/ GIMT_Encode4(109890), // Rule ID 2949 // |
| 33603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33606 | // MIs[0] sbase |
| 33607 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33608 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33609 | // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 33611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33612 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33615 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33616 | GIR_RootConstrainSelectedInstOperands, |
| 33617 | // GIR_Coverage, 2949, |
| 33618 | GIR_EraseRootFromParent_Done, |
| 33619 | // Label 1832: @109890 |
| 33620 | GIM_Try, /*On fail goto*//*Label 1833*/ GIMT_Encode4(109929), // Rule ID 2938 // |
| 33621 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33623 | // MIs[0] sbase |
| 33624 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33625 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33626 | // (ld:{ *:[v4i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33629 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33632 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33633 | GIR_RootConstrainSelectedInstOperands, |
| 33634 | // GIR_Coverage, 2938, |
| 33635 | GIR_EraseRootFromParent_Done, |
| 33636 | // Label 1833: @109929 |
| 33637 | GIM_Try, /*On fail goto*//*Label 1834*/ GIMT_Encode4(109968), // Rule ID 2955 // |
| 33638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 33640 | // MIs[0] sbase |
| 33641 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 33642 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 33643 | // (ld:{ *:[v4f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v4f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 33645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33646 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 33647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33650 | GIR_RootConstrainSelectedInstOperands, |
| 33651 | // GIR_Coverage, 2955, |
| 33652 | GIR_EraseRootFromParent_Done, |
| 33653 | // Label 1834: @109968 |
| 33654 | GIM_Reject, |
| 33655 | // Label 1800: @109969 |
| 33656 | GIM_Reject, |
| 33657 | // Label 865: @109970 |
| 33658 | GIM_Try, /*On fail goto*//*Label 1835*/ GIMT_Encode4(110037), // Rule ID 2841 // |
| 33659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33660 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33661 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33663 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33664 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33665 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33667 | // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33675 | GIR_RootConstrainSelectedInstOperands, |
| 33676 | // GIR_Coverage, 2841, |
| 33677 | GIR_EraseRootFromParent_Done, |
| 33678 | // Label 1835: @110037 |
| 33679 | GIM_Try, /*On fail goto*//*Label 1836*/ GIMT_Encode4(110104), // Rule ID 2858 // |
| 33680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33681 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33685 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33686 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33688 | // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33696 | GIR_RootConstrainSelectedInstOperands, |
| 33697 | // GIR_Coverage, 2858, |
| 33698 | GIR_EraseRootFromParent_Done, |
| 33699 | // Label 1836: @110104 |
| 33700 | GIM_Try, /*On fail goto*//*Label 1837*/ GIMT_Encode4(110171), // Rule ID 2875 // |
| 33701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33702 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33703 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33705 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33706 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33707 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33709 | // (ld:{ *:[v8bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33717 | GIR_RootConstrainSelectedInstOperands, |
| 33718 | // GIR_Coverage, 2875, |
| 33719 | GIR_EraseRootFromParent_Done, |
| 33720 | // Label 1837: @110171 |
| 33721 | GIM_Try, /*On fail goto*//*Label 1838*/ GIMT_Encode4(110234), // Rule ID 2846 // |
| 33722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33723 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33724 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33726 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33727 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33728 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33729 | // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 33731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33737 | GIR_RootConstrainSelectedInstOperands, |
| 33738 | // GIR_Coverage, 2846, |
| 33739 | GIR_EraseRootFromParent_Done, |
| 33740 | // Label 1838: @110234 |
| 33741 | GIM_Try, /*On fail goto*//*Label 1839*/ GIMT_Encode4(110297), // Rule ID 2863 // |
| 33742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33743 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33744 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33746 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33747 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33749 | // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 33751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33756 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33757 | GIR_RootConstrainSelectedInstOperands, |
| 33758 | // GIR_Coverage, 2863, |
| 33759 | GIR_EraseRootFromParent_Done, |
| 33760 | // Label 1839: @110297 |
| 33761 | GIM_Try, /*On fail goto*//*Label 1840*/ GIMT_Encode4(110360), // Rule ID 2880 // |
| 33762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33763 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33764 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33767 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33769 | // (ld:{ *:[v8bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 33771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33776 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33777 | GIR_RootConstrainSelectedInstOperands, |
| 33778 | // GIR_Coverage, 2880, |
| 33779 | GIR_EraseRootFromParent_Done, |
| 33780 | // Label 1840: @110360 |
| 33781 | GIM_Try, /*On fail goto*//*Label 1841*/ GIMT_Encode4(110423), // Rule ID 2852 // |
| 33782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33783 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33784 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33787 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33789 | // (ld:{ *:[v8i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33796 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33797 | GIR_RootConstrainSelectedInstOperands, |
| 33798 | // GIR_Coverage, 2852, |
| 33799 | GIR_EraseRootFromParent_Done, |
| 33800 | // Label 1841: @110423 |
| 33801 | GIM_Try, /*On fail goto*//*Label 1842*/ GIMT_Encode4(110486), // Rule ID 2869 // |
| 33802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33803 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33804 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33805 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33806 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33807 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33809 | // (ld:{ *:[v8f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33817 | GIR_RootConstrainSelectedInstOperands, |
| 33818 | // GIR_Coverage, 2869, |
| 33819 | GIR_EraseRootFromParent_Done, |
| 33820 | // Label 1842: @110486 |
| 33821 | GIM_Try, /*On fail goto*//*Label 1843*/ GIMT_Encode4(110549), // Rule ID 2886 // |
| 33822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 33823 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33824 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33827 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 33829 | // (ld:{ *:[v8bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 33835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33837 | GIR_RootConstrainSelectedInstOperands, |
| 33838 | // GIR_Coverage, 2886, |
| 33839 | GIR_EraseRootFromParent_Done, |
| 33840 | // Label 1843: @110549 |
| 33841 | GIM_Try, /*On fail goto*//*Label 1844*/ GIMT_Encode4(110611), // Rule ID 2837 // |
| 33842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33843 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33844 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33847 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33848 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33849 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33850 | // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 33852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33857 | GIR_RootConstrainSelectedInstOperands, |
| 33858 | // GIR_Coverage, 2837, |
| 33859 | GIR_EraseRootFromParent_Done, |
| 33860 | // Label 1844: @110611 |
| 33861 | GIM_Try, /*On fail goto*//*Label 1845*/ GIMT_Encode4(110673), // Rule ID 2838 // |
| 33862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 33863 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33864 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33866 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33867 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33868 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33870 | // (ld:{ *:[v8i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 33872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33877 | GIR_RootConstrainSelectedInstOperands, |
| 33878 | // GIR_Coverage, 2838, |
| 33879 | GIR_EraseRootFromParent_Done, |
| 33880 | // Label 1845: @110673 |
| 33881 | GIM_Try, /*On fail goto*//*Label 1846*/ GIMT_Encode4(110735), // Rule ID 2839 // |
| 33882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33883 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33884 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33887 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33890 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 33892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33897 | GIR_RootConstrainSelectedInstOperands, |
| 33898 | // GIR_Coverage, 2839, |
| 33899 | GIR_EraseRootFromParent_Done, |
| 33900 | // Label 1846: @110735 |
| 33901 | GIM_Try, /*On fail goto*//*Label 1847*/ GIMT_Encode4(110800), // Rule ID 2840 // |
| 33902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33903 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33904 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33908 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33909 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33910 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33918 | GIR_RootConstrainSelectedInstOperands, |
| 33919 | // GIR_Coverage, 2840, |
| 33920 | GIR_EraseRootFromParent_Done, |
| 33921 | // Label 1847: @110800 |
| 33922 | GIM_Try, /*On fail goto*//*Label 1848*/ GIMT_Encode4(110862), // Rule ID 2854 // |
| 33923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 33924 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33925 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33927 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33928 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33929 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 33931 | // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 33933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33938 | GIR_RootConstrainSelectedInstOperands, |
| 33939 | // GIR_Coverage, 2854, |
| 33940 | GIR_EraseRootFromParent_Done, |
| 33941 | // Label 1848: @110862 |
| 33942 | GIM_Try, /*On fail goto*//*Label 1849*/ GIMT_Encode4(110924), // Rule ID 2855 // |
| 33943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 33944 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33945 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33948 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33949 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 33951 | // (ld:{ *:[v8f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 33952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 33953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 33956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33957 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33958 | GIR_RootConstrainSelectedInstOperands, |
| 33959 | // GIR_Coverage, 2855, |
| 33960 | GIR_EraseRootFromParent_Done, |
| 33961 | // Label 1849: @110924 |
| 33962 | GIM_Try, /*On fail goto*//*Label 1850*/ GIMT_Encode4(110986), // Rule ID 2856 // |
| 33963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 33964 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33965 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33967 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33968 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33969 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33971 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 33972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 33973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33977 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33978 | GIR_RootConstrainSelectedInstOperands, |
| 33979 | // GIR_Coverage, 2856, |
| 33980 | GIR_EraseRootFromParent_Done, |
| 33981 | // Label 1850: @110986 |
| 33982 | GIM_Try, /*On fail goto*//*Label 1851*/ GIMT_Encode4(111051), // Rule ID 2857 // |
| 33983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 33984 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 33985 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 33986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 33987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 33988 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 33989 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 33990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 33991 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 33992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 33993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 33994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 33995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 33996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 33998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 33999 | GIR_RootConstrainSelectedInstOperands, |
| 34000 | // GIR_Coverage, 2857, |
| 34001 | GIR_EraseRootFromParent_Done, |
| 34002 | // Label 1851: @111051 |
| 34003 | GIM_Try, /*On fail goto*//*Label 1852*/ GIMT_Encode4(111113), // Rule ID 2871 // |
| 34004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34005 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34008 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34010 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34012 | // (ld:{ *:[v8bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34019 | GIR_RootConstrainSelectedInstOperands, |
| 34020 | // GIR_Coverage, 2871, |
| 34021 | GIR_EraseRootFromParent_Done, |
| 34022 | // Label 1852: @111113 |
| 34023 | GIM_Try, /*On fail goto*//*Label 1853*/ GIMT_Encode4(111175), // Rule ID 2872 // |
| 34024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 34025 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34028 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34029 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34030 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34031 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 34032 | // (ld:{ *:[v8bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 34034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34038 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34039 | GIR_RootConstrainSelectedInstOperands, |
| 34040 | // GIR_Coverage, 2872, |
| 34041 | GIR_EraseRootFromParent_Done, |
| 34042 | // Label 1853: @111175 |
| 34043 | GIM_Try, /*On fail goto*//*Label 1854*/ GIMT_Encode4(111237), // Rule ID 2873 // |
| 34044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 34045 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34046 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34048 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34049 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34050 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34052 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 34054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34059 | GIR_RootConstrainSelectedInstOperands, |
| 34060 | // GIR_Coverage, 2873, |
| 34061 | GIR_EraseRootFromParent_Done, |
| 34062 | // Label 1854: @111237 |
| 34063 | GIM_Try, /*On fail goto*//*Label 1855*/ GIMT_Encode4(111302), // Rule ID 2874 // |
| 34064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 34065 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34069 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34070 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34072 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 34074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34080 | GIR_RootConstrainSelectedInstOperands, |
| 34081 | // GIR_Coverage, 2874, |
| 34082 | GIR_EraseRootFromParent_Done, |
| 34083 | // Label 1855: @111302 |
| 34084 | GIM_Try, /*On fail goto*//*Label 1856*/ GIMT_Encode4(111360), // Rule ID 2843 // |
| 34085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34086 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34087 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34090 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34092 | // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34099 | GIR_RootConstrainSelectedInstOperands, |
| 34100 | // GIR_Coverage, 2843, |
| 34101 | GIR_EraseRootFromParent_Done, |
| 34102 | // Label 1856: @111360 |
| 34103 | GIM_Try, /*On fail goto*//*Label 1857*/ GIMT_Encode4(111418), // Rule ID 2844 // |
| 34104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 34105 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34106 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34109 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34111 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 34113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34117 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34118 | GIR_RootConstrainSelectedInstOperands, |
| 34119 | // GIR_Coverage, 2844, |
| 34120 | GIR_EraseRootFromParent_Done, |
| 34121 | // Label 1857: @111418 |
| 34122 | GIM_Try, /*On fail goto*//*Label 1858*/ GIMT_Encode4(111479), // Rule ID 2845 // |
| 34123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 34124 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34125 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34128 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34130 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 34132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34138 | GIR_RootConstrainSelectedInstOperands, |
| 34139 | // GIR_Coverage, 2845, |
| 34140 | GIR_EraseRootFromParent_Done, |
| 34141 | // Label 1858: @111479 |
| 34142 | GIM_Try, /*On fail goto*//*Label 1859*/ GIMT_Encode4(111537), // Rule ID 2860 // |
| 34143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34144 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34148 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34150 | // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34157 | GIR_RootConstrainSelectedInstOperands, |
| 34158 | // GIR_Coverage, 2860, |
| 34159 | GIR_EraseRootFromParent_Done, |
| 34160 | // Label 1859: @111537 |
| 34161 | GIM_Try, /*On fail goto*//*Label 1860*/ GIMT_Encode4(111595), // Rule ID 2861 // |
| 34162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 34163 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34164 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34167 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34168 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34169 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 34171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34175 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34176 | GIR_RootConstrainSelectedInstOperands, |
| 34177 | // GIR_Coverage, 2861, |
| 34178 | GIR_EraseRootFromParent_Done, |
| 34179 | // Label 1860: @111595 |
| 34180 | GIM_Try, /*On fail goto*//*Label 1861*/ GIMT_Encode4(111656), // Rule ID 2862 // |
| 34181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 34182 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34183 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34186 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34188 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 34190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34196 | GIR_RootConstrainSelectedInstOperands, |
| 34197 | // GIR_Coverage, 2862, |
| 34198 | GIR_EraseRootFromParent_Done, |
| 34199 | // Label 1861: @111656 |
| 34200 | GIM_Try, /*On fail goto*//*Label 1862*/ GIMT_Encode4(111714), // Rule ID 2877 // |
| 34201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34202 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34205 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34206 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34208 | // (ld:{ *:[v8bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34215 | GIR_RootConstrainSelectedInstOperands, |
| 34216 | // GIR_Coverage, 2877, |
| 34217 | GIR_EraseRootFromParent_Done, |
| 34218 | // Label 1862: @111714 |
| 34219 | GIM_Try, /*On fail goto*//*Label 1863*/ GIMT_Encode4(111772), // Rule ID 2878 // |
| 34220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 34221 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34222 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34227 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_ec:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_ec), |
| 34229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34233 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34234 | GIR_RootConstrainSelectedInstOperands, |
| 34235 | // GIR_Coverage, 2878, |
| 34236 | GIR_EraseRootFromParent_Done, |
| 34237 | // Label 1863: @111772 |
| 34238 | GIM_Try, /*On fail goto*//*Label 1864*/ GIMT_Encode4(111833), // Rule ID 2879 // |
| 34239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 34240 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34241 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34243 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34244 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34246 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM_ec:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM_ec), |
| 34248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34254 | GIR_RootConstrainSelectedInstOperands, |
| 34255 | // GIR_Coverage, 2879, |
| 34256 | GIR_EraseRootFromParent_Done, |
| 34257 | // Label 1864: @111833 |
| 34258 | GIM_Try, /*On fail goto*//*Label 1865*/ GIMT_Encode4(111901), // Rule ID 7747 // |
| 34259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 34260 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34261 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34263 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34265 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34266 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 34267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34268 | // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34275 | GIR_RootConstrainSelectedInstOperands, |
| 34276 | // GIR_Coverage, 7747, |
| 34277 | GIR_EraseRootFromParent_Done, |
| 34278 | // Label 1865: @111901 |
| 34279 | GIM_Try, /*On fail goto*//*Label 1866*/ GIMT_Encode4(111969), // Rule ID 7751 // |
| 34280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 34281 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34282 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34283 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34284 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34287 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 34288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34289 | // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34296 | GIR_RootConstrainSelectedInstOperands, |
| 34297 | // GIR_Coverage, 7751, |
| 34298 | GIR_EraseRootFromParent_Done, |
| 34299 | // Label 1866: @111969 |
| 34300 | GIM_Try, /*On fail goto*//*Label 1867*/ GIMT_Encode4(112037), // Rule ID 7755 // |
| 34301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 34302 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34303 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34304 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34305 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34308 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local_m0), |
| 34309 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34310 | // (AMDGPUld_glue:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align_less_than_4_local_m0>> => (DS_READ_B128:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34316 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34317 | GIR_RootConstrainSelectedInstOperands, |
| 34318 | // GIR_Coverage, 7755, |
| 34319 | GIR_EraseRootFromParent_Done, |
| 34320 | // Label 1867: @112037 |
| 34321 | GIM_Try, /*On fail goto*//*Label 1868*/ GIMT_Encode4(112100), // Rule ID 7671 // |
| 34322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 34323 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34324 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34325 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34326 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34328 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34329 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34330 | // (AMDGPUld_glue:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34336 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34337 | GIR_RootConstrainSelectedInstOperands, |
| 34338 | // GIR_Coverage, 7671, |
| 34339 | GIR_EraseRootFromParent_Done, |
| 34340 | // Label 1868: @112100 |
| 34341 | GIM_Try, /*On fail goto*//*Label 1869*/ GIMT_Encode4(112163), // Rule ID 7675 // |
| 34342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 34343 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34344 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34345 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34346 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34348 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34350 | // (AMDGPUld_glue:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34356 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34357 | GIR_RootConstrainSelectedInstOperands, |
| 34358 | // GIR_Coverage, 7675, |
| 34359 | GIR_EraseRootFromParent_Done, |
| 34360 | // Label 1869: @112163 |
| 34361 | GIM_Try, /*On fail goto*//*Label 1870*/ GIMT_Encode4(112226), // Rule ID 7679 // |
| 34362 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 34363 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34364 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34365 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34366 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34368 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34370 | // (AMDGPUld_glue:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>><<P:Predicate_load_align16_local_m0>> => (DS_READ_B128:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128), |
| 34372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34376 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34377 | GIR_RootConstrainSelectedInstOperands, |
| 34378 | // GIR_Coverage, 7679, |
| 34379 | GIR_EraseRootFromParent_Done, |
| 34380 | // Label 1870: @112226 |
| 34381 | GIM_Try, /*On fail goto*//*Label 1871*/ GIMT_Encode4(112281), // Rule ID 2848 // |
| 34382 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34385 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34386 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34388 | // (ld:{ *:[v8i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34395 | GIR_RootConstrainSelectedInstOperands, |
| 34396 | // GIR_Coverage, 2848, |
| 34397 | GIR_EraseRootFromParent_Done, |
| 34398 | // Label 1871: @112281 |
| 34399 | GIM_Try, /*On fail goto*//*Label 1872*/ GIMT_Encode4(112339), // Rule ID 2849 // |
| 34400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 34401 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34402 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34404 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34405 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 34407 | // (ld:{ *:[v8i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 34409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34414 | GIR_RootConstrainSelectedInstOperands, |
| 34415 | // GIR_Coverage, 2849, |
| 34416 | GIR_EraseRootFromParent_Done, |
| 34417 | // Label 1872: @112339 |
| 34418 | GIM_Try, /*On fail goto*//*Label 1873*/ GIMT_Encode4(112397), // Rule ID 2850 // |
| 34419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 34420 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34421 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34423 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34424 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34426 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 34428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34433 | GIR_RootConstrainSelectedInstOperands, |
| 34434 | // GIR_Coverage, 2850, |
| 34435 | GIR_EraseRootFromParent_Done, |
| 34436 | // Label 1873: @112397 |
| 34437 | GIM_Try, /*On fail goto*//*Label 1874*/ GIMT_Encode4(112458), // Rule ID 2851 // |
| 34438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 34439 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34440 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34443 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34445 | // (ld:{ *:[v8i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 34447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34453 | GIR_RootConstrainSelectedInstOperands, |
| 34454 | // GIR_Coverage, 2851, |
| 34455 | GIR_EraseRootFromParent_Done, |
| 34456 | // Label 1874: @112458 |
| 34457 | GIM_Try, /*On fail goto*//*Label 1875*/ GIMT_Encode4(112513), // Rule ID 2865 // |
| 34458 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34462 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34464 | // (ld:{ *:[v8f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34471 | GIR_RootConstrainSelectedInstOperands, |
| 34472 | // GIR_Coverage, 2865, |
| 34473 | GIR_EraseRootFromParent_Done, |
| 34474 | // Label 1875: @112513 |
| 34475 | GIM_Try, /*On fail goto*//*Label 1876*/ GIMT_Encode4(112571), // Rule ID 2866 // |
| 34476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 34477 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34479 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34480 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34481 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 34483 | // (ld:{ *:[v8f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 34485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34490 | GIR_RootConstrainSelectedInstOperands, |
| 34491 | // GIR_Coverage, 2866, |
| 34492 | GIR_EraseRootFromParent_Done, |
| 34493 | // Label 1876: @112571 |
| 34494 | GIM_Try, /*On fail goto*//*Label 1877*/ GIMT_Encode4(112629), // Rule ID 2867 // |
| 34495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 34496 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34497 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34499 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34500 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34501 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34502 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 34504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34508 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34509 | GIR_RootConstrainSelectedInstOperands, |
| 34510 | // GIR_Coverage, 2867, |
| 34511 | GIR_EraseRootFromParent_Done, |
| 34512 | // Label 1877: @112629 |
| 34513 | GIM_Try, /*On fail goto*//*Label 1878*/ GIMT_Encode4(112690), // Rule ID 2868 // |
| 34514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 34515 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34516 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34517 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34518 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34519 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34520 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34521 | // (ld:{ *:[v8f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 34523 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34529 | GIR_RootConstrainSelectedInstOperands, |
| 34530 | // GIR_Coverage, 2868, |
| 34531 | GIR_EraseRootFromParent_Done, |
| 34532 | // Label 1878: @112690 |
| 34533 | GIM_Try, /*On fail goto*//*Label 1879*/ GIMT_Encode4(112745), // Rule ID 2882 // |
| 34534 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34535 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34537 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34538 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 34540 | // (ld:{ *:[v8bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34547 | GIR_RootConstrainSelectedInstOperands, |
| 34548 | // GIR_Coverage, 2882, |
| 34549 | GIR_EraseRootFromParent_Done, |
| 34550 | // Label 1879: @112745 |
| 34551 | GIM_Try, /*On fail goto*//*Label 1880*/ GIMT_Encode4(112803), // Rule ID 2883 // |
| 34552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 34553 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34554 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34557 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34558 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 34559 | // (ld:{ *:[v8bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ci:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ci), |
| 34561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34565 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34566 | GIR_RootConstrainSelectedInstOperands, |
| 34567 | // GIR_Coverage, 2883, |
| 34568 | GIR_EraseRootFromParent_Done, |
| 34569 | // Label 1880: @112803 |
| 34570 | GIM_Try, /*On fail goto*//*Label 1881*/ GIMT_Encode4(112861), // Rule ID 2884 // |
| 34571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 34572 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34573 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34575 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34576 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34577 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34578 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 34579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR), |
| 34580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34584 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34585 | GIR_RootConstrainSelectedInstOperands, |
| 34586 | // GIR_Coverage, 2884, |
| 34587 | GIR_EraseRootFromParent_Done, |
| 34588 | // Label 1881: @112861 |
| 34589 | GIM_Try, /*On fail goto*//*Label 1882*/ GIMT_Encode4(112922), // Rule ID 2885 // |
| 34590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 34591 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34592 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34595 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 34597 | // (ld:{ *:[v8bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_SGPR_IMM:{ *:[v8bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_SGPR_IMM), |
| 34599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 34601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 34602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34605 | GIR_RootConstrainSelectedInstOperands, |
| 34606 | // GIR_Coverage, 2885, |
| 34607 | GIR_EraseRootFromParent_Done, |
| 34608 | // Label 1882: @112922 |
| 34609 | GIM_Try, /*On fail goto*//*Label 1883*/ GIMT_Encode4(112986), // Rule ID 7748 // |
| 34610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 34611 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34612 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34613 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34616 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 34617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34618 | // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34625 | GIR_RootConstrainSelectedInstOperands, |
| 34626 | // GIR_Coverage, 7748, |
| 34627 | GIR_EraseRootFromParent_Done, |
| 34628 | // Label 1883: @112986 |
| 34629 | GIM_Try, /*On fail goto*//*Label 1884*/ GIMT_Encode4(113050), // Rule ID 7752 // |
| 34630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 34631 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34632 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34633 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 34637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34638 | // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34645 | GIR_RootConstrainSelectedInstOperands, |
| 34646 | // GIR_Coverage, 7752, |
| 34647 | GIR_EraseRootFromParent_Done, |
| 34648 | // Label 1884: @113050 |
| 34649 | GIM_Try, /*On fail goto*//*Label 1885*/ GIMT_Encode4(113114), // Rule ID 7756 // |
| 34650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 34651 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34652 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34653 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34655 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34656 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_load_align_less_than_4_local), |
| 34657 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34658 | // (ld:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align_less_than_4_local>> => (DS_READ_B128_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34665 | GIR_RootConstrainSelectedInstOperands, |
| 34666 | // GIR_Coverage, 7756, |
| 34667 | GIR_EraseRootFromParent_Done, |
| 34668 | // Label 1885: @113114 |
| 34669 | GIM_Try, /*On fail goto*//*Label 1886*/ GIMT_Encode4(113173), // Rule ID 7672 // |
| 34670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 34671 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34672 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34673 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34674 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34675 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34676 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34677 | // (ld:{ *:[v8i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34683 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34684 | GIR_RootConstrainSelectedInstOperands, |
| 34685 | // GIR_Coverage, 7672, |
| 34686 | GIR_EraseRootFromParent_Done, |
| 34687 | // Label 1886: @113173 |
| 34688 | GIM_Try, /*On fail goto*//*Label 1887*/ GIMT_Encode4(113232), // Rule ID 7676 // |
| 34689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 34690 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34691 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34696 | // (ld:{ *:[v8f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34703 | GIR_RootConstrainSelectedInstOperands, |
| 34704 | // GIR_Coverage, 7676, |
| 34705 | GIR_EraseRootFromParent_Done, |
| 34706 | // Label 1887: @113232 |
| 34707 | GIM_Try, /*On fail goto*//*Label 1888*/ GIMT_Encode4(113291), // Rule ID 7680 // |
| 34708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 34709 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 34710 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 34711 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 34715 | // (ld:{ *:[v8bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_local>><<P:Predicate_load_align16_local>> => (DS_READ_B128_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 34716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_B128_gfx9), |
| 34717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 34719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34721 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34722 | GIR_RootConstrainSelectedInstOperands, |
| 34723 | // GIR_Coverage, 7680, |
| 34724 | GIR_EraseRootFromParent_Done, |
| 34725 | // Label 1888: @113291 |
| 34726 | GIM_Try, /*On fail goto*//*Label 1889*/ GIMT_Encode4(113345), // Rule ID 2842 // |
| 34727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34728 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34729 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34731 | // MIs[0] sbase |
| 34732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34733 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34734 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34735 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34736 | // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34739 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34743 | GIR_RootConstrainSelectedInstOperands, |
| 34744 | // GIR_Coverage, 2842, |
| 34745 | GIR_EraseRootFromParent_Done, |
| 34746 | // Label 1889: @113345 |
| 34747 | GIM_Try, /*On fail goto*//*Label 1890*/ GIMT_Encode4(113399), // Rule ID 2859 // |
| 34748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34749 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34750 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34752 | // MIs[0] sbase |
| 34753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34754 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34755 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34756 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34757 | // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34760 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34764 | GIR_RootConstrainSelectedInstOperands, |
| 34765 | // GIR_Coverage, 2859, |
| 34766 | GIR_EraseRootFromParent_Done, |
| 34767 | // Label 1890: @113399 |
| 34768 | GIM_Try, /*On fail goto*//*Label 1891*/ GIMT_Encode4(113453), // Rule ID 2876 // |
| 34769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34770 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34773 | // MIs[0] sbase |
| 34774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34775 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34776 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34777 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 34778 | // (ld:{ *:[v8bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34781 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34785 | GIR_RootConstrainSelectedInstOperands, |
| 34786 | // GIR_Coverage, 2876, |
| 34787 | GIR_EraseRootFromParent_Done, |
| 34788 | // Label 1891: @113453 |
| 34789 | GIM_Try, /*On fail goto*//*Label 1892*/ GIMT_Encode4(113503), // Rule ID 2847 // |
| 34790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34791 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34792 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34794 | // MIs[0] sbase |
| 34795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34797 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34798 | // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34801 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34804 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34805 | GIR_RootConstrainSelectedInstOperands, |
| 34806 | // GIR_Coverage, 2847, |
| 34807 | GIR_EraseRootFromParent_Done, |
| 34808 | // Label 1892: @113503 |
| 34809 | GIM_Try, /*On fail goto*//*Label 1893*/ GIMT_Encode4(113553), // Rule ID 2864 // |
| 34810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34811 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34812 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34814 | // MIs[0] sbase |
| 34815 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34816 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34817 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34818 | // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34821 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34825 | GIR_RootConstrainSelectedInstOperands, |
| 34826 | // GIR_Coverage, 2864, |
| 34827 | GIR_EraseRootFromParent_Done, |
| 34828 | // Label 1893: @113553 |
| 34829 | GIM_Try, /*On fail goto*//*Label 1894*/ GIMT_Encode4(113603), // Rule ID 2881 // |
| 34830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 34831 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34832 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34833 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34834 | // MIs[0] sbase |
| 34835 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34836 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34837 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34838 | // (ld:{ *:[v8bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM_ec:{ *:[v8bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM_ec), |
| 34840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34841 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34845 | GIR_RootConstrainSelectedInstOperands, |
| 34846 | // GIR_Coverage, 2881, |
| 34847 | GIR_EraseRootFromParent_Done, |
| 34848 | // Label 1894: @113603 |
| 34849 | GIM_Try, /*On fail goto*//*Label 1895*/ GIMT_Encode4(113650), // Rule ID 2853 // |
| 34850 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34851 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34853 | // MIs[0] sbase |
| 34854 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34855 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34856 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34857 | // (ld:{ *:[v8i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34860 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34864 | GIR_RootConstrainSelectedInstOperands, |
| 34865 | // GIR_Coverage, 2853, |
| 34866 | GIR_EraseRootFromParent_Done, |
| 34867 | // Label 1895: @113650 |
| 34868 | GIM_Try, /*On fail goto*//*Label 1896*/ GIMT_Encode4(113697), // Rule ID 2870 // |
| 34869 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34872 | // MIs[0] sbase |
| 34873 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34874 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34875 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34876 | // (ld:{ *:[v8f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34879 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34883 | GIR_RootConstrainSelectedInstOperands, |
| 34884 | // GIR_Coverage, 2870, |
| 34885 | GIR_EraseRootFromParent_Done, |
| 34886 | // Label 1896: @113697 |
| 34887 | GIM_Try, /*On fail goto*//*Label 1897*/ GIMT_Encode4(113744), // Rule ID 2887 // |
| 34888 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 34889 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 34891 | // MIs[0] sbase |
| 34892 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 34893 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 34894 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 34895 | // (ld:{ *:[v8bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX4_IMM:{ *:[v8bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 34896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX4_IMM), |
| 34897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 34898 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 34899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34902 | GIR_RootConstrainSelectedInstOperands, |
| 34903 | // GIR_Coverage, 2887, |
| 34904 | GIR_EraseRootFromParent_Done, |
| 34905 | // Label 1897: @113744 |
| 34906 | GIM_Try, /*On fail goto*//*Label 1898*/ GIMT_Encode4(113804), // Rule ID 4017 // |
| 34907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 34908 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 34909 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34911 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34912 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 34913 | // (ld:{ *:[v8i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 34915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 34917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 34918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 34919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34921 | GIR_RootConstrainSelectedInstOperands, |
| 34922 | // GIR_Coverage, 4017, |
| 34923 | GIR_EraseRootFromParent_Done, |
| 34924 | // Label 1898: @113804 |
| 34925 | GIM_Try, /*On fail goto*//*Label 1899*/ GIMT_Encode4(113864), // Rule ID 4023 // |
| 34926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 34927 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 34928 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 34932 | // (ld:{ *:[v8f16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 34934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 34936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 34937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 34938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34939 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34940 | GIR_RootConstrainSelectedInstOperands, |
| 34941 | // GIR_Coverage, 4023, |
| 34942 | GIR_EraseRootFromParent_Done, |
| 34943 | // Label 1899: @113864 |
| 34944 | GIM_Try, /*On fail goto*//*Label 1900*/ GIMT_Encode4(113924), // Rule ID 4029 // |
| 34945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 34946 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 34947 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 34951 | // (ld:{ *:[v8bf16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SVS:{ *:[v8bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 34952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SVS), |
| 34953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 34955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 34956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 34957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34959 | GIR_RootConstrainSelectedInstOperands, |
| 34960 | // GIR_Coverage, 4029, |
| 34961 | GIR_EraseRootFromParent_Done, |
| 34962 | // Label 1900: @113924 |
| 34963 | GIM_Try, /*On fail goto*//*Label 1901*/ GIMT_Encode4(113979), // Rule ID 4016 // |
| 34964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 34965 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 34966 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 34970 | // (ld:{ *:[v8i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 34971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 34972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 34974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34977 | GIR_RootConstrainSelectedInstOperands, |
| 34978 | // GIR_Coverage, 4016, |
| 34979 | GIR_EraseRootFromParent_Done, |
| 34980 | // Label 1901: @113979 |
| 34981 | GIM_Try, /*On fail goto*//*Label 1902*/ GIMT_Encode4(114034), // Rule ID 4022 // |
| 34982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 34983 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 34984 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 34985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 34986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 34987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 34988 | // (ld:{ *:[v8f16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 34989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 34990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 34991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 34992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 34993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 34994 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 34995 | GIR_RootConstrainSelectedInstOperands, |
| 34996 | // GIR_Coverage, 4022, |
| 34997 | GIR_EraseRootFromParent_Done, |
| 34998 | // Label 1902: @114034 |
| 34999 | GIM_Try, /*On fail goto*//*Label 1903*/ GIMT_Encode4(114089), // Rule ID 4028 // |
| 35000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 35001 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 35002 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 35006 | // (ld:{ *:[v8bf16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4_SADDR:{ *:[v8bf16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 35007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4_SADDR), |
| 35008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 35010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35013 | GIR_RootConstrainSelectedInstOperands, |
| 35014 | // GIR_Coverage, 4028, |
| 35015 | GIR_EraseRootFromParent_Done, |
| 35016 | // Label 1903: @114089 |
| 35017 | GIM_Try, /*On fail goto*//*Label 1904*/ GIMT_Encode4(114144), // Rule ID 4015 // |
| 35018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 35019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 35020 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35023 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 35024 | // (ld:{ *:[v8i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 35026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35030 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35031 | GIR_RootConstrainSelectedInstOperands, |
| 35032 | // GIR_Coverage, 4015, |
| 35033 | GIR_EraseRootFromParent_Done, |
| 35034 | // Label 1904: @114144 |
| 35035 | GIM_Try, /*On fail goto*//*Label 1905*/ GIMT_Encode4(114199), // Rule ID 4021 // |
| 35036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 35037 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 35038 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35040 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 35042 | // (ld:{ *:[v8f16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 35044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35048 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35049 | GIR_RootConstrainSelectedInstOperands, |
| 35050 | // GIR_Coverage, 4021, |
| 35051 | GIR_EraseRootFromParent_Done, |
| 35052 | // Label 1905: @114199 |
| 35053 | GIM_Try, /*On fail goto*//*Label 1906*/ GIMT_Encode4(114254), // Rule ID 4027 // |
| 35054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 35055 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 35056 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35058 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 35060 | // (ld:{ *:[v8bf16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_private>> => (SCRATCH_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_DWORDX4), |
| 35062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35066 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35067 | GIR_RootConstrainSelectedInstOperands, |
| 35068 | // GIR_Coverage, 4027, |
| 35069 | GIR_EraseRootFromParent_Done, |
| 35070 | // Label 1906: @114254 |
| 35071 | GIM_Try, /*On fail goto*//*Label 1907*/ GIMT_Encode4(114324), // Rule ID 4230 // |
| 35072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35073 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35074 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35076 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35077 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35078 | // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 35080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35087 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35088 | GIR_RootConstrainSelectedInstOperands, |
| 35089 | // GIR_Coverage, 4230, |
| 35090 | GIR_EraseRootFromParent_Done, |
| 35091 | // Label 1907: @114324 |
| 35092 | GIM_Try, /*On fail goto*//*Label 1908*/ GIMT_Encode4(114391), // Rule ID 4232 // |
| 35093 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35094 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35096 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35097 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35098 | // (ld:{ *:[v8i16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8i16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 35100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35107 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35108 | GIR_RootConstrainSelectedInstOperands, |
| 35109 | // GIR_Coverage, 4232, |
| 35110 | GIR_EraseRootFromParent_Done, |
| 35111 | // Label 1908: @114391 |
| 35112 | GIM_Try, /*On fail goto*//*Label 1909*/ GIMT_Encode4(114461), // Rule ID 4234 // |
| 35113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35114 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35115 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35117 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35118 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35119 | // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 35121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35128 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35129 | GIR_RootConstrainSelectedInstOperands, |
| 35130 | // GIR_Coverage, 4234, |
| 35131 | GIR_EraseRootFromParent_Done, |
| 35132 | // Label 1909: @114461 |
| 35133 | GIM_Try, /*On fail goto*//*Label 1910*/ GIMT_Encode4(114528), // Rule ID 4236 // |
| 35134 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35135 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35139 | // (ld:{ *:[v8f16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8f16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 35141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35148 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35149 | GIR_RootConstrainSelectedInstOperands, |
| 35150 | // GIR_Coverage, 4236, |
| 35151 | GIR_EraseRootFromParent_Done, |
| 35152 | // Label 1910: @114528 |
| 35153 | GIM_Try, /*On fail goto*//*Label 1911*/ GIMT_Encode4(114598), // Rule ID 4238 // |
| 35154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35155 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35156 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35157 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35158 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35160 | // (ld:{ *:[v8bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_ADDR64:{ *:[v8bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_ADDR64), |
| 35162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35170 | GIR_RootConstrainSelectedInstOperands, |
| 35171 | // GIR_Coverage, 4238, |
| 35172 | GIR_EraseRootFromParent_Done, |
| 35173 | // Label 1911: @114598 |
| 35174 | GIM_Try, /*On fail goto*//*Label 1912*/ GIMT_Encode4(114665), // Rule ID 4240 // |
| 35175 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35176 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 35180 | // (ld:{ *:[v8bf16] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64:{ *:[v8bf16] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_ADDR64), |
| 35182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 35184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 35186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 35187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35189 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35190 | GIR_RootConstrainSelectedInstOperands, |
| 35191 | // GIR_Coverage, 4240, |
| 35192 | GIR_EraseRootFromParent_Done, |
| 35193 | // Label 1912: @114665 |
| 35194 | GIM_Try, /*On fail goto*//*Label 1913*/ GIMT_Encode4(114729), // Rule ID 7595 // |
| 35195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 35196 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 35197 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35200 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35202 | // (AMDGPUld_glue:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 35204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35210 | GIR_RootConstrainSelectedInstOperands, |
| 35211 | // GIR_Coverage, 7595, |
| 35212 | GIR_EraseRootFromParent_Done, |
| 35213 | // Label 1913: @114729 |
| 35214 | GIM_Try, /*On fail goto*//*Label 1914*/ GIMT_Encode4(114793), // Rule ID 7599 // |
| 35215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 35216 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 35217 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35218 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35220 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35221 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35222 | // (AMDGPUld_glue:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 35224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35230 | GIR_RootConstrainSelectedInstOperands, |
| 35231 | // GIR_Coverage, 7599, |
| 35232 | GIR_EraseRootFromParent_Done, |
| 35233 | // Label 1914: @114793 |
| 35234 | GIM_Try, /*On fail goto*//*Label 1915*/ GIMT_Encode4(114857), // Rule ID 7603 // |
| 35235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 35236 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 35237 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35238 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35242 | // (AMDGPUld_glue:{ *:[v8bf16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload_glue>><<P:Predicate_load_glue>><<P:Predicate_load_local_m0>> => (DS_READ2_B64:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64), |
| 35244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35250 | GIR_RootConstrainSelectedInstOperands, |
| 35251 | // GIR_Coverage, 7603, |
| 35252 | GIR_EraseRootFromParent_Done, |
| 35253 | // Label 1915: @114857 |
| 35254 | GIM_Try, /*On fail goto*//*Label 1916*/ GIMT_Encode4(114922), // Rule ID 4229 // |
| 35255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35256 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35257 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35260 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35261 | // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 35263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35269 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35270 | GIR_RootConstrainSelectedInstOperands, |
| 35271 | // GIR_Coverage, 4229, |
| 35272 | GIR_EraseRootFromParent_Done, |
| 35273 | // Label 1916: @114922 |
| 35274 | GIM_Try, /*On fail goto*//*Label 1917*/ GIMT_Encode4(114984), // Rule ID 4231 // |
| 35275 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35278 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35279 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35280 | // (ld:{ *:[v8i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 35282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35289 | GIR_RootConstrainSelectedInstOperands, |
| 35290 | // GIR_Coverage, 4231, |
| 35291 | GIR_EraseRootFromParent_Done, |
| 35292 | // Label 1917: @114984 |
| 35293 | GIM_Try, /*On fail goto*//*Label 1918*/ GIMT_Encode4(115049), // Rule ID 4233 // |
| 35294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35295 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35296 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35300 | // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 35302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35309 | GIR_RootConstrainSelectedInstOperands, |
| 35310 | // GIR_Coverage, 4233, |
| 35311 | GIR_EraseRootFromParent_Done, |
| 35312 | // Label 1918: @115049 |
| 35313 | GIM_Try, /*On fail goto*//*Label 1919*/ GIMT_Encode4(115111), // Rule ID 4235 // |
| 35314 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35315 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35319 | // (ld:{ *:[v8f16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 35321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35328 | GIR_RootConstrainSelectedInstOperands, |
| 35329 | // GIR_Coverage, 4235, |
| 35330 | GIR_EraseRootFromParent_Done, |
| 35331 | // Label 1919: @115111 |
| 35332 | GIM_Try, /*On fail goto*//*Label 1920*/ GIMT_Encode4(115176), // Rule ID 4237 // |
| 35333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 35334 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35335 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35337 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35339 | // (ld:{ *:[v8bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 35341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35348 | GIR_RootConstrainSelectedInstOperands, |
| 35349 | // GIR_Coverage, 4237, |
| 35350 | GIR_EraseRootFromParent_Done, |
| 35351 | // Label 1920: @115176 |
| 35352 | GIM_Try, /*On fail goto*//*Label 1921*/ GIMT_Encode4(115238), // Rule ID 4239 // |
| 35353 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35354 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35356 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35357 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 35358 | // (ld:{ *:[v8bf16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 35359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 35360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 35361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 35362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35367 | GIR_RootConstrainSelectedInstOperands, |
| 35368 | // GIR_Coverage, 4239, |
| 35369 | GIR_EraseRootFromParent_Done, |
| 35370 | // Label 1921: @115238 |
| 35371 | GIM_Try, /*On fail goto*//*Label 1922*/ GIMT_Encode4(115298), // Rule ID 7597 // |
| 35372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 35373 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35374 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35378 | // (ld:{ *:[v8i16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v8i16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 35380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35385 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35386 | GIR_RootConstrainSelectedInstOperands, |
| 35387 | // GIR_Coverage, 7597, |
| 35388 | GIR_EraseRootFromParent_Done, |
| 35389 | // Label 1922: @115298 |
| 35390 | GIM_Try, /*On fail goto*//*Label 1923*/ GIMT_Encode4(115358), // Rule ID 7601 // |
| 35391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 35392 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35393 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35395 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35397 | // (ld:{ *:[v8f16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v8f16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 35399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35404 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35405 | GIR_RootConstrainSelectedInstOperands, |
| 35406 | // GIR_Coverage, 7601, |
| 35407 | GIR_EraseRootFromParent_Done, |
| 35408 | // Label 1923: @115358 |
| 35409 | GIM_Try, /*On fail goto*//*Label 1924*/ GIMT_Encode4(115418), // Rule ID 7605 // |
| 35410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 35411 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 35412 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35414 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 35416 | // (ld:{ *:[v8bf16] } (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedload>><<P:Predicate_load_local>> => (DS_READ2_B64_gfx9:{ *:[v8bf16] } ?:{ *:[i32] }:$ptr, ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 35417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ2_B64_gfx9), |
| 35418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 35420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 35421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 35422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35424 | GIR_RootConstrainSelectedInstOperands, |
| 35425 | // GIR_Coverage, 7605, |
| 35426 | GIR_EraseRootFromParent_Done, |
| 35427 | // Label 1924: @115418 |
| 35428 | GIM_Try, /*On fail goto*//*Label 1925*/ GIMT_Encode4(115480), // Rule ID 3543 // |
| 35429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35430 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35431 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35433 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 35435 | // (ld:{ *:[v8i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 35437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 35439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 35440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35443 | GIR_RootConstrainSelectedInstOperands, |
| 35444 | // GIR_Coverage, 3543, |
| 35445 | GIR_EraseRootFromParent_Done, |
| 35446 | // Label 1925: @115480 |
| 35447 | GIM_Try, /*On fail goto*//*Label 1926*/ GIMT_Encode4(115542), // Rule ID 3547 // |
| 35448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35449 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35450 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 35454 | // (ld:{ *:[v8f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 35456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 35458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 35459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35461 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35462 | GIR_RootConstrainSelectedInstOperands, |
| 35463 | // GIR_Coverage, 3547, |
| 35464 | GIR_EraseRootFromParent_Done, |
| 35465 | // Label 1926: @115542 |
| 35466 | GIM_Try, /*On fail goto*//*Label 1927*/ GIMT_Encode4(115604), // Rule ID 3551 // |
| 35467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35468 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35469 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 35473 | // (ld:{ *:[v8bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4_SADDR:{ *:[v8bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4_SADDR), |
| 35475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 35477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 35478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35480 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35481 | GIR_RootConstrainSelectedInstOperands, |
| 35482 | // GIR_Coverage, 3551, |
| 35483 | GIR_EraseRootFromParent_Done, |
| 35484 | // Label 1927: @115604 |
| 35485 | GIM_Try, /*On fail goto*//*Label 1928*/ GIMT_Encode4(115661), // Rule ID 3542 // |
| 35486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35487 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35488 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 35492 | // (ld:{ *:[v8i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 35494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35499 | GIR_RootConstrainSelectedInstOperands, |
| 35500 | // GIR_Coverage, 3542, |
| 35501 | GIR_EraseRootFromParent_Done, |
| 35502 | // Label 1928: @115661 |
| 35503 | GIM_Try, /*On fail goto*//*Label 1929*/ GIMT_Encode4(115718), // Rule ID 3546 // |
| 35504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35505 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35506 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35508 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 35510 | // (ld:{ *:[v8f16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 35512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35517 | GIR_RootConstrainSelectedInstOperands, |
| 35518 | // GIR_Coverage, 3546, |
| 35519 | GIR_EraseRootFromParent_Done, |
| 35520 | // Label 1929: @115718 |
| 35521 | GIM_Try, /*On fail goto*//*Label 1930*/ GIMT_Encode4(115775), // Rule ID 3550 // |
| 35522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 35523 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35524 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35526 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35527 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 35528 | // (ld:{ *:[v8bf16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_global>> => (GLOBAL_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_DWORDX4), |
| 35530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35535 | GIR_RootConstrainSelectedInstOperands, |
| 35536 | // GIR_Coverage, 3550, |
| 35537 | GIR_EraseRootFromParent_Done, |
| 35538 | // Label 1930: @115775 |
| 35539 | GIM_Try, /*On fail goto*//*Label 1931*/ GIMT_Encode4(115833), // Rule ID 3276 // |
| 35540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 35541 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 35546 | // (ld:{ *:[v8i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 35548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35552 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35553 | GIR_RootConstrainSelectedInstOperands, |
| 35554 | // GIR_Coverage, 3276, |
| 35555 | GIR_EraseRootFromParent_Done, |
| 35556 | // Label 1931: @115833 |
| 35557 | GIM_Try, /*On fail goto*//*Label 1932*/ GIMT_Encode4(115891), // Rule ID 3278 // |
| 35558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 35559 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35560 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 35564 | // (ld:{ *:[v8f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 35566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35571 | GIR_RootConstrainSelectedInstOperands, |
| 35572 | // GIR_Coverage, 3278, |
| 35573 | GIR_EraseRootFromParent_Done, |
| 35574 | // Label 1932: @115891 |
| 35575 | GIM_Try, /*On fail goto*//*Label 1933*/ GIMT_Encode4(115949), // Rule ID 3280 // |
| 35576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 35577 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 35578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 35580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 35582 | // (ld:{ *:[v8bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load_flat>> => (FLAT_LOAD_DWORDX4:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 35583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_DWORDX4), |
| 35584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 35585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 35586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35588 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35589 | GIR_RootConstrainSelectedInstOperands, |
| 35590 | // GIR_Coverage, 3280, |
| 35591 | GIR_EraseRootFromParent_Done, |
| 35592 | // Label 1933: @115949 |
| 35593 | GIM_Reject, |
| 35594 | // Label 866: @115950 |
| 35595 | GIM_Try, /*On fail goto*//*Label 1934*/ GIMT_Encode4(117700), |
| 35596 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 35597 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 35598 | GIM_Try, /*On fail goto*//*Label 1935*/ GIMT_Encode4(116022), // Rule ID 2892 // |
| 35599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35600 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35602 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35603 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35605 | // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35612 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35613 | GIR_RootConstrainSelectedInstOperands, |
| 35614 | // GIR_Coverage, 2892, |
| 35615 | GIR_EraseRootFromParent_Done, |
| 35616 | // Label 1935: @116022 |
| 35617 | GIM_Try, /*On fail goto*//*Label 1936*/ GIMT_Encode4(116081), // Rule ID 2909 // |
| 35618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35619 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35622 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35623 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35624 | // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35631 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35632 | GIR_RootConstrainSelectedInstOperands, |
| 35633 | // GIR_Coverage, 2909, |
| 35634 | GIR_EraseRootFromParent_Done, |
| 35635 | // Label 1936: @116081 |
| 35636 | GIM_Try, /*On fail goto*//*Label 1937*/ GIMT_Encode4(116136), // Rule ID 2897 // |
| 35637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35640 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35641 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35642 | // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 35644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35650 | GIR_RootConstrainSelectedInstOperands, |
| 35651 | // GIR_Coverage, 2897, |
| 35652 | GIR_EraseRootFromParent_Done, |
| 35653 | // Label 1937: @116136 |
| 35654 | GIM_Try, /*On fail goto*//*Label 1938*/ GIMT_Encode4(116191), // Rule ID 2914 // |
| 35655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35656 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35660 | // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 35662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35667 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35668 | GIR_RootConstrainSelectedInstOperands, |
| 35669 | // GIR_Coverage, 2914, |
| 35670 | GIR_EraseRootFromParent_Done, |
| 35671 | // Label 1938: @116191 |
| 35672 | GIM_Try, /*On fail goto*//*Label 1939*/ GIMT_Encode4(116246), // Rule ID 2903 // |
| 35673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 35674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35676 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35677 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35678 | // (ld:{ *:[v8i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35685 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35686 | GIR_RootConstrainSelectedInstOperands, |
| 35687 | // GIR_Coverage, 2903, |
| 35688 | GIR_EraseRootFromParent_Done, |
| 35689 | // Label 1939: @116246 |
| 35690 | GIM_Try, /*On fail goto*//*Label 1940*/ GIMT_Encode4(116301), // Rule ID 2920 // |
| 35691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 35692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 35696 | // (ld:{ *:[v8f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 35702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35703 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35704 | GIR_RootConstrainSelectedInstOperands, |
| 35705 | // GIR_Coverage, 2920, |
| 35706 | GIR_EraseRootFromParent_Done, |
| 35707 | // Label 1940: @116301 |
| 35708 | GIM_Try, /*On fail goto*//*Label 1941*/ GIMT_Encode4(116355), // Rule ID 2888 // |
| 35709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 35710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35712 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35713 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 35715 | // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 35717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35721 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35722 | GIR_RootConstrainSelectedInstOperands, |
| 35723 | // GIR_Coverage, 2888, |
| 35724 | GIR_EraseRootFromParent_Done, |
| 35725 | // Label 1941: @116355 |
| 35726 | GIM_Try, /*On fail goto*//*Label 1942*/ GIMT_Encode4(116409), // Rule ID 2889 // |
| 35727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 35728 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35731 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35732 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 35733 | // (ld:{ *:[v8i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 35735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35740 | GIR_RootConstrainSelectedInstOperands, |
| 35741 | // GIR_Coverage, 2889, |
| 35742 | GIR_EraseRootFromParent_Done, |
| 35743 | // Label 1942: @116409 |
| 35744 | GIM_Try, /*On fail goto*//*Label 1943*/ GIMT_Encode4(116463), // Rule ID 2890 // |
| 35745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 35746 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35749 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35750 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35751 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 35752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 35753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35758 | GIR_RootConstrainSelectedInstOperands, |
| 35759 | // GIR_Coverage, 2890, |
| 35760 | GIR_EraseRootFromParent_Done, |
| 35761 | // Label 1943: @116463 |
| 35762 | GIM_Try, /*On fail goto*//*Label 1944*/ GIMT_Encode4(116520), // Rule ID 2891 // |
| 35763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35764 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35767 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35769 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 35770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35776 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35777 | GIR_RootConstrainSelectedInstOperands, |
| 35778 | // GIR_Coverage, 2891, |
| 35779 | GIR_EraseRootFromParent_Done, |
| 35780 | // Label 1944: @116520 |
| 35781 | GIM_Try, /*On fail goto*//*Label 1945*/ GIMT_Encode4(116574), // Rule ID 2905 // |
| 35782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 35783 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35786 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 35788 | // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 35790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35795 | GIR_RootConstrainSelectedInstOperands, |
| 35796 | // GIR_Coverage, 2905, |
| 35797 | GIR_EraseRootFromParent_Done, |
| 35798 | // Label 1945: @116574 |
| 35799 | GIM_Try, /*On fail goto*//*Label 1946*/ GIMT_Encode4(116628), // Rule ID 2906 // |
| 35800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 35801 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35803 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35804 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35805 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 35806 | // (ld:{ *:[v8f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 35808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35812 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35813 | GIR_RootConstrainSelectedInstOperands, |
| 35814 | // GIR_Coverage, 2906, |
| 35815 | GIR_EraseRootFromParent_Done, |
| 35816 | // Label 1946: @116628 |
| 35817 | GIM_Try, /*On fail goto*//*Label 1947*/ GIMT_Encode4(116682), // Rule ID 2907 // |
| 35818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 35819 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35821 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35822 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35824 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 35825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 35826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35831 | GIR_RootConstrainSelectedInstOperands, |
| 35832 | // GIR_Coverage, 2907, |
| 35833 | GIR_EraseRootFromParent_Done, |
| 35834 | // Label 1947: @116682 |
| 35835 | GIM_Try, /*On fail goto*//*Label 1948*/ GIMT_Encode4(116739), // Rule ID 2908 // |
| 35836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35837 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35839 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35840 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 35841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35842 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 35843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 35844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35849 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35850 | GIR_RootConstrainSelectedInstOperands, |
| 35851 | // GIR_Coverage, 2908, |
| 35852 | GIR_EraseRootFromParent_Done, |
| 35853 | // Label 1948: @116739 |
| 35854 | GIM_Try, /*On fail goto*//*Label 1949*/ GIMT_Encode4(116789), // Rule ID 2894 // |
| 35855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 35856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 35860 | // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 35862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35866 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35867 | GIR_RootConstrainSelectedInstOperands, |
| 35868 | // GIR_Coverage, 2894, |
| 35869 | GIR_EraseRootFromParent_Done, |
| 35870 | // Label 1949: @116789 |
| 35871 | GIM_Try, /*On fail goto*//*Label 1950*/ GIMT_Encode4(116839), // Rule ID 2895 // |
| 35872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 35873 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35875 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35876 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35877 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 35878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 35879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35883 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35884 | GIR_RootConstrainSelectedInstOperands, |
| 35885 | // GIR_Coverage, 2895, |
| 35886 | GIR_EraseRootFromParent_Done, |
| 35887 | // Label 1950: @116839 |
| 35888 | GIM_Try, /*On fail goto*//*Label 1951*/ GIMT_Encode4(116892), // Rule ID 2896 // |
| 35889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35890 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35892 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35894 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 35895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 35896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35902 | GIR_RootConstrainSelectedInstOperands, |
| 35903 | // GIR_Coverage, 2896, |
| 35904 | GIR_EraseRootFromParent_Done, |
| 35905 | // Label 1951: @116892 |
| 35906 | GIM_Try, /*On fail goto*//*Label 1952*/ GIMT_Encode4(116942), // Rule ID 2911 // |
| 35907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 35908 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 35912 | // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 35914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35918 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35919 | GIR_RootConstrainSelectedInstOperands, |
| 35920 | // GIR_Coverage, 2911, |
| 35921 | GIR_EraseRootFromParent_Done, |
| 35922 | // Label 1952: @116942 |
| 35923 | GIM_Try, /*On fail goto*//*Label 1953*/ GIMT_Encode4(116992), // Rule ID 2912 // |
| 35924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 35925 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35927 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35928 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35929 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 35930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 35931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35935 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35936 | GIR_RootConstrainSelectedInstOperands, |
| 35937 | // GIR_Coverage, 2912, |
| 35938 | GIR_EraseRootFromParent_Done, |
| 35939 | // Label 1953: @116992 |
| 35940 | GIM_Try, /*On fail goto*//*Label 1954*/ GIMT_Encode4(117045), // Rule ID 2913 // |
| 35941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 35942 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35944 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35945 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35946 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 35947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 35948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 35951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35954 | GIR_RootConstrainSelectedInstOperands, |
| 35955 | // GIR_Coverage, 2913, |
| 35956 | GIR_EraseRootFromParent_Done, |
| 35957 | // Label 1954: @117045 |
| 35958 | GIM_Try, /*On fail goto*//*Label 1955*/ GIMT_Encode4(117092), // Rule ID 2899 // |
| 35959 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35961 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 35963 | // (ld:{ *:[v8i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 35965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35969 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35970 | GIR_RootConstrainSelectedInstOperands, |
| 35971 | // GIR_Coverage, 2899, |
| 35972 | GIR_EraseRootFromParent_Done, |
| 35973 | // Label 1955: @117092 |
| 35974 | GIM_Try, /*On fail goto*//*Label 1956*/ GIMT_Encode4(117142), // Rule ID 2900 // |
| 35975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 35976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 35980 | // (ld:{ *:[v8i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 35981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 35982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 35983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 35984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 35985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 35986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 35987 | GIR_RootConstrainSelectedInstOperands, |
| 35988 | // GIR_Coverage, 2900, |
| 35989 | GIR_EraseRootFromParent_Done, |
| 35990 | // Label 1956: @117142 |
| 35991 | GIM_Try, /*On fail goto*//*Label 1957*/ GIMT_Encode4(117192), // Rule ID 2901 // |
| 35992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 35993 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 35994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 35995 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 35996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 35997 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 35998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 35999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36003 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36004 | GIR_RootConstrainSelectedInstOperands, |
| 36005 | // GIR_Coverage, 2901, |
| 36006 | GIR_EraseRootFromParent_Done, |
| 36007 | // Label 1957: @117192 |
| 36008 | GIM_Try, /*On fail goto*//*Label 1958*/ GIMT_Encode4(117245), // Rule ID 2902 // |
| 36009 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36010 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36012 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36013 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36014 | // (ld:{ *:[v8i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36021 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36022 | GIR_RootConstrainSelectedInstOperands, |
| 36023 | // GIR_Coverage, 2902, |
| 36024 | GIR_EraseRootFromParent_Done, |
| 36025 | // Label 1958: @117245 |
| 36026 | GIM_Try, /*On fail goto*//*Label 1959*/ GIMT_Encode4(117292), // Rule ID 2916 // |
| 36027 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36028 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36029 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36031 | // (ld:{ *:[v8f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36037 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36038 | GIR_RootConstrainSelectedInstOperands, |
| 36039 | // GIR_Coverage, 2916, |
| 36040 | GIR_EraseRootFromParent_Done, |
| 36041 | // Label 1959: @117292 |
| 36042 | GIM_Try, /*On fail goto*//*Label 1960*/ GIMT_Encode4(117342), // Rule ID 2917 // |
| 36043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 36044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 36048 | // (ld:{ *:[v8f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 36050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36054 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36055 | GIR_RootConstrainSelectedInstOperands, |
| 36056 | // GIR_Coverage, 2917, |
| 36057 | GIR_EraseRootFromParent_Done, |
| 36058 | // Label 1960: @117342 |
| 36059 | GIM_Try, /*On fail goto*//*Label 1961*/ GIMT_Encode4(117392), // Rule ID 2918 // |
| 36060 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 36061 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36062 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36063 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36065 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 36067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36072 | GIR_RootConstrainSelectedInstOperands, |
| 36073 | // GIR_Coverage, 2918, |
| 36074 | GIR_EraseRootFromParent_Done, |
| 36075 | // Label 1961: @117392 |
| 36076 | GIM_Try, /*On fail goto*//*Label 1962*/ GIMT_Encode4(117445), // Rule ID 2919 // |
| 36077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36078 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36082 | // (ld:{ *:[v8f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36089 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36090 | GIR_RootConstrainSelectedInstOperands, |
| 36091 | // GIR_Coverage, 2919, |
| 36092 | GIR_EraseRootFromParent_Done, |
| 36093 | // Label 1962: @117445 |
| 36094 | GIM_Try, /*On fail goto*//*Label 1963*/ GIMT_Encode4(117491), // Rule ID 2893 // |
| 36095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36096 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36098 | // MIs[0] sbase |
| 36099 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36100 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36101 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36102 | // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36105 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36108 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36109 | GIR_RootConstrainSelectedInstOperands, |
| 36110 | // GIR_Coverage, 2893, |
| 36111 | GIR_EraseRootFromParent_Done, |
| 36112 | // Label 1963: @117491 |
| 36113 | GIM_Try, /*On fail goto*//*Label 1964*/ GIMT_Encode4(117537), // Rule ID 2910 // |
| 36114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36115 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36117 | // MIs[0] sbase |
| 36118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36119 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36120 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36121 | // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36124 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36127 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36128 | GIR_RootConstrainSelectedInstOperands, |
| 36129 | // GIR_Coverage, 2910, |
| 36130 | GIR_EraseRootFromParent_Done, |
| 36131 | // Label 1964: @117537 |
| 36132 | GIM_Try, /*On fail goto*//*Label 1965*/ GIMT_Encode4(117579), // Rule ID 2898 // |
| 36133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36134 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36136 | // MIs[0] sbase |
| 36137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36138 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36139 | // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 36141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36142 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36145 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36146 | GIR_RootConstrainSelectedInstOperands, |
| 36147 | // GIR_Coverage, 2898, |
| 36148 | GIR_EraseRootFromParent_Done, |
| 36149 | // Label 1965: @117579 |
| 36150 | GIM_Try, /*On fail goto*//*Label 1966*/ GIMT_Encode4(117621), // Rule ID 2915 // |
| 36151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36152 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36154 | // MIs[0] sbase |
| 36155 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36156 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36157 | // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 36159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36160 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36163 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36164 | GIR_RootConstrainSelectedInstOperands, |
| 36165 | // GIR_Coverage, 2915, |
| 36166 | GIR_EraseRootFromParent_Done, |
| 36167 | // Label 1966: @117621 |
| 36168 | GIM_Try, /*On fail goto*//*Label 1967*/ GIMT_Encode4(117660), // Rule ID 2904 // |
| 36169 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36171 | // MIs[0] sbase |
| 36172 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36173 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36174 | // (ld:{ *:[v8i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36177 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36181 | GIR_RootConstrainSelectedInstOperands, |
| 36182 | // GIR_Coverage, 2904, |
| 36183 | GIR_EraseRootFromParent_Done, |
| 36184 | // Label 1967: @117660 |
| 36185 | GIM_Try, /*On fail goto*//*Label 1968*/ GIMT_Encode4(117699), // Rule ID 2921 // |
| 36186 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36188 | // MIs[0] sbase |
| 36189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36190 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36191 | // (ld:{ *:[v8f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v8f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36193 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36194 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36198 | GIR_RootConstrainSelectedInstOperands, |
| 36199 | // GIR_Coverage, 2921, |
| 36200 | GIR_EraseRootFromParent_Done, |
| 36201 | // Label 1968: @117699 |
| 36202 | GIM_Reject, |
| 36203 | // Label 1934: @117700 |
| 36204 | GIM_Reject, |
| 36205 | // Label 867: @117701 |
| 36206 | GIM_Try, /*On fail goto*//*Label 1969*/ GIMT_Encode4(119451), |
| 36207 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 36208 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 36209 | GIM_Try, /*On fail goto*//*Label 1970*/ GIMT_Encode4(117773), // Rule ID 3045 // |
| 36210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36211 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36213 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36214 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36216 | // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36223 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36224 | GIR_RootConstrainSelectedInstOperands, |
| 36225 | // GIR_Coverage, 3045, |
| 36226 | GIR_EraseRootFromParent_Done, |
| 36227 | // Label 1970: @117773 |
| 36228 | GIM_Try, /*On fail goto*//*Label 1971*/ GIMT_Encode4(117832), // Rule ID 3062 // |
| 36229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36230 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36232 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36233 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36235 | // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36242 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36243 | GIR_RootConstrainSelectedInstOperands, |
| 36244 | // GIR_Coverage, 3062, |
| 36245 | GIR_EraseRootFromParent_Done, |
| 36246 | // Label 1971: @117832 |
| 36247 | GIM_Try, /*On fail goto*//*Label 1972*/ GIMT_Encode4(117887), // Rule ID 3050 // |
| 36248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36249 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36251 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36253 | // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 36255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36261 | GIR_RootConstrainSelectedInstOperands, |
| 36262 | // GIR_Coverage, 3050, |
| 36263 | GIR_EraseRootFromParent_Done, |
| 36264 | // Label 1972: @117887 |
| 36265 | GIM_Try, /*On fail goto*//*Label 1973*/ GIMT_Encode4(117942), // Rule ID 3067 // |
| 36266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36267 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36269 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36271 | // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 36273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36279 | GIR_RootConstrainSelectedInstOperands, |
| 36280 | // GIR_Coverage, 3067, |
| 36281 | GIR_EraseRootFromParent_Done, |
| 36282 | // Label 1973: @117942 |
| 36283 | GIM_Try, /*On fail goto*//*Label 1974*/ GIMT_Encode4(117997), // Rule ID 3056 // |
| 36284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36285 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36289 | // (ld:{ *:[v8i64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36296 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36297 | GIR_RootConstrainSelectedInstOperands, |
| 36298 | // GIR_Coverage, 3056, |
| 36299 | GIR_EraseRootFromParent_Done, |
| 36300 | // Label 1974: @117997 |
| 36301 | GIM_Try, /*On fail goto*//*Label 1975*/ GIMT_Encode4(118052), // Rule ID 3073 // |
| 36302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36305 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36307 | // (ld:{ *:[v8f64] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36315 | GIR_RootConstrainSelectedInstOperands, |
| 36316 | // GIR_Coverage, 3073, |
| 36317 | GIR_EraseRootFromParent_Done, |
| 36318 | // Label 1975: @118052 |
| 36319 | GIM_Try, /*On fail goto*//*Label 1976*/ GIMT_Encode4(118106), // Rule ID 3041 // |
| 36320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36324 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36325 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36326 | // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36333 | GIR_RootConstrainSelectedInstOperands, |
| 36334 | // GIR_Coverage, 3041, |
| 36335 | GIR_EraseRootFromParent_Done, |
| 36336 | // Label 1976: @118106 |
| 36337 | GIM_Try, /*On fail goto*//*Label 1977*/ GIMT_Encode4(118160), // Rule ID 3042 // |
| 36338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 36339 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36342 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36343 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 36344 | // (ld:{ *:[v8i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 36346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36351 | GIR_RootConstrainSelectedInstOperands, |
| 36352 | // GIR_Coverage, 3042, |
| 36353 | GIR_EraseRootFromParent_Done, |
| 36354 | // Label 1977: @118160 |
| 36355 | GIM_Try, /*On fail goto*//*Label 1978*/ GIMT_Encode4(118214), // Rule ID 3043 // |
| 36356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 36357 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36360 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36362 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 36364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36369 | GIR_RootConstrainSelectedInstOperands, |
| 36370 | // GIR_Coverage, 3043, |
| 36371 | GIR_EraseRootFromParent_Done, |
| 36372 | // Label 1978: @118214 |
| 36373 | GIM_Try, /*On fail goto*//*Label 1979*/ GIMT_Encode4(118271), // Rule ID 3044 // |
| 36374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36377 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36378 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36379 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36380 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36387 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36388 | GIR_RootConstrainSelectedInstOperands, |
| 36389 | // GIR_Coverage, 3044, |
| 36390 | GIR_EraseRootFromParent_Done, |
| 36391 | // Label 1979: @118271 |
| 36392 | GIM_Try, /*On fail goto*//*Label 1980*/ GIMT_Encode4(118325), // Rule ID 3058 // |
| 36393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36394 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36396 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36397 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36399 | // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36406 | GIR_RootConstrainSelectedInstOperands, |
| 36407 | // GIR_Coverage, 3058, |
| 36408 | GIR_EraseRootFromParent_Done, |
| 36409 | // Label 1980: @118325 |
| 36410 | GIM_Try, /*On fail goto*//*Label 1981*/ GIMT_Encode4(118379), // Rule ID 3059 // |
| 36411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 36412 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36414 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36415 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 36417 | // (ld:{ *:[v8f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 36419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36424 | GIR_RootConstrainSelectedInstOperands, |
| 36425 | // GIR_Coverage, 3059, |
| 36426 | GIR_EraseRootFromParent_Done, |
| 36427 | // Label 1981: @118379 |
| 36428 | GIM_Try, /*On fail goto*//*Label 1982*/ GIMT_Encode4(118433), // Rule ID 3060 // |
| 36429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 36430 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36433 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36435 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 36437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36442 | GIR_RootConstrainSelectedInstOperands, |
| 36443 | // GIR_Coverage, 3060, |
| 36444 | GIR_EraseRootFromParent_Done, |
| 36445 | // Label 1982: @118433 |
| 36446 | GIM_Try, /*On fail goto*//*Label 1983*/ GIMT_Encode4(118490), // Rule ID 3061 // |
| 36447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36448 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36450 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36451 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36453 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36460 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36461 | GIR_RootConstrainSelectedInstOperands, |
| 36462 | // GIR_Coverage, 3061, |
| 36463 | GIR_EraseRootFromParent_Done, |
| 36464 | // Label 1983: @118490 |
| 36465 | GIM_Try, /*On fail goto*//*Label 1984*/ GIMT_Encode4(118540), // Rule ID 3047 // |
| 36466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36467 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36469 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36471 | // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 36473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36477 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36478 | GIR_RootConstrainSelectedInstOperands, |
| 36479 | // GIR_Coverage, 3047, |
| 36480 | GIR_EraseRootFromParent_Done, |
| 36481 | // Label 1984: @118540 |
| 36482 | GIM_Try, /*On fail goto*//*Label 1985*/ GIMT_Encode4(118590), // Rule ID 3048 // |
| 36483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 36484 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36488 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 36490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36494 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36495 | GIR_RootConstrainSelectedInstOperands, |
| 36496 | // GIR_Coverage, 3048, |
| 36497 | GIR_EraseRootFromParent_Done, |
| 36498 | // Label 1985: @118590 |
| 36499 | GIM_Try, /*On fail goto*//*Label 1986*/ GIMT_Encode4(118643), // Rule ID 3049 // |
| 36500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36501 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36503 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36504 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36505 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 36507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36513 | GIR_RootConstrainSelectedInstOperands, |
| 36514 | // GIR_Coverage, 3049, |
| 36515 | GIR_EraseRootFromParent_Done, |
| 36516 | // Label 1986: @118643 |
| 36517 | GIM_Try, /*On fail goto*//*Label 1987*/ GIMT_Encode4(118693), // Rule ID 3064 // |
| 36518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36519 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36521 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36523 | // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 36525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36530 | GIR_RootConstrainSelectedInstOperands, |
| 36531 | // GIR_Coverage, 3064, |
| 36532 | GIR_EraseRootFromParent_Done, |
| 36533 | // Label 1987: @118693 |
| 36534 | GIM_Try, /*On fail goto*//*Label 1988*/ GIMT_Encode4(118743), // Rule ID 3065 // |
| 36535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 36536 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36537 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36540 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 36542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36547 | GIR_RootConstrainSelectedInstOperands, |
| 36548 | // GIR_Coverage, 3065, |
| 36549 | GIR_EraseRootFromParent_Done, |
| 36550 | // Label 1988: @118743 |
| 36551 | GIM_Try, /*On fail goto*//*Label 1989*/ GIMT_Encode4(118796), // Rule ID 3066 // |
| 36552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36553 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36554 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36555 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36556 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36557 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 36559 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36564 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36565 | GIR_RootConstrainSelectedInstOperands, |
| 36566 | // GIR_Coverage, 3066, |
| 36567 | GIR_EraseRootFromParent_Done, |
| 36568 | // Label 1989: @118796 |
| 36569 | GIM_Try, /*On fail goto*//*Label 1990*/ GIMT_Encode4(118843), // Rule ID 3052 // |
| 36570 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36572 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36573 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36574 | // (ld:{ *:[v8i64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36580 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36581 | GIR_RootConstrainSelectedInstOperands, |
| 36582 | // GIR_Coverage, 3052, |
| 36583 | GIR_EraseRootFromParent_Done, |
| 36584 | // Label 1990: @118843 |
| 36585 | GIM_Try, /*On fail goto*//*Label 1991*/ GIMT_Encode4(118893), // Rule ID 3053 // |
| 36586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 36587 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36590 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 36591 | // (ld:{ *:[v8i64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 36593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36598 | GIR_RootConstrainSelectedInstOperands, |
| 36599 | // GIR_Coverage, 3053, |
| 36600 | GIR_EraseRootFromParent_Done, |
| 36601 | // Label 1991: @118893 |
| 36602 | GIM_Try, /*On fail goto*//*Label 1992*/ GIMT_Encode4(118943), // Rule ID 3054 // |
| 36603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 36604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36606 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36607 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36608 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 36610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36614 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36615 | GIR_RootConstrainSelectedInstOperands, |
| 36616 | // GIR_Coverage, 3054, |
| 36617 | GIR_EraseRootFromParent_Done, |
| 36618 | // Label 1992: @118943 |
| 36619 | GIM_Try, /*On fail goto*//*Label 1993*/ GIMT_Encode4(118996), // Rule ID 3055 // |
| 36620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36621 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36623 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36624 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36625 | // (ld:{ *:[v8i64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8i64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36632 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36633 | GIR_RootConstrainSelectedInstOperands, |
| 36634 | // GIR_Coverage, 3055, |
| 36635 | GIR_EraseRootFromParent_Done, |
| 36636 | // Label 1993: @118996 |
| 36637 | GIM_Try, /*On fail goto*//*Label 1994*/ GIMT_Encode4(119043), // Rule ID 3069 // |
| 36638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36640 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36641 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36642 | // (ld:{ *:[v8f64] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36648 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36649 | GIR_RootConstrainSelectedInstOperands, |
| 36650 | // GIR_Coverage, 3069, |
| 36651 | GIR_EraseRootFromParent_Done, |
| 36652 | // Label 1994: @119043 |
| 36653 | GIM_Try, /*On fail goto*//*Label 1995*/ GIMT_Encode4(119093), // Rule ID 3070 // |
| 36654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 36655 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 36659 | // (ld:{ *:[v8f64] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 36661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36666 | GIR_RootConstrainSelectedInstOperands, |
| 36667 | // GIR_Coverage, 3070, |
| 36668 | GIR_EraseRootFromParent_Done, |
| 36669 | // Label 1995: @119093 |
| 36670 | GIM_Try, /*On fail goto*//*Label 1996*/ GIMT_Encode4(119143), // Rule ID 3071 // |
| 36671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 36672 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36674 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36676 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 36677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 36678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36683 | GIR_RootConstrainSelectedInstOperands, |
| 36684 | // GIR_Coverage, 3071, |
| 36685 | GIR_EraseRootFromParent_Done, |
| 36686 | // Label 1996: @119143 |
| 36687 | GIM_Try, /*On fail goto*//*Label 1997*/ GIMT_Encode4(119196), // Rule ID 3072 // |
| 36688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36689 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 36693 | // (ld:{ *:[v8f64] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v8f64] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 36695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36700 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36701 | GIR_RootConstrainSelectedInstOperands, |
| 36702 | // GIR_Coverage, 3072, |
| 36703 | GIR_EraseRootFromParent_Done, |
| 36704 | // Label 1997: @119196 |
| 36705 | GIM_Try, /*On fail goto*//*Label 1998*/ GIMT_Encode4(119242), // Rule ID 3046 // |
| 36706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36707 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36709 | // MIs[0] sbase |
| 36710 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36711 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36712 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36713 | // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36716 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36719 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36720 | GIR_RootConstrainSelectedInstOperands, |
| 36721 | // GIR_Coverage, 3046, |
| 36722 | GIR_EraseRootFromParent_Done, |
| 36723 | // Label 1998: @119242 |
| 36724 | GIM_Try, /*On fail goto*//*Label 1999*/ GIMT_Encode4(119288), // Rule ID 3063 // |
| 36725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36726 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36728 | // MIs[0] sbase |
| 36729 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36730 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36731 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36732 | // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36735 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36738 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36739 | GIR_RootConstrainSelectedInstOperands, |
| 36740 | // GIR_Coverage, 3063, |
| 36741 | GIR_EraseRootFromParent_Done, |
| 36742 | // Label 1999: @119288 |
| 36743 | GIM_Try, /*On fail goto*//*Label 2000*/ GIMT_Encode4(119330), // Rule ID 3051 // |
| 36744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36745 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36747 | // MIs[0] sbase |
| 36748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36749 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36750 | // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 36752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36753 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36756 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36757 | GIR_RootConstrainSelectedInstOperands, |
| 36758 | // GIR_Coverage, 3051, |
| 36759 | GIR_EraseRootFromParent_Done, |
| 36760 | // Label 2000: @119330 |
| 36761 | GIM_Try, /*On fail goto*//*Label 2001*/ GIMT_Encode4(119372), // Rule ID 3068 // |
| 36762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36763 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36765 | // MIs[0] sbase |
| 36766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36767 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36768 | // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 36770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36771 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36774 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36775 | GIR_RootConstrainSelectedInstOperands, |
| 36776 | // GIR_Coverage, 3068, |
| 36777 | GIR_EraseRootFromParent_Done, |
| 36778 | // Label 2001: @119372 |
| 36779 | GIM_Try, /*On fail goto*//*Label 2002*/ GIMT_Encode4(119411), // Rule ID 3057 // |
| 36780 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36782 | // MIs[0] sbase |
| 36783 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36784 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36785 | // (ld:{ *:[v8i64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8i64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36788 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36791 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36792 | GIR_RootConstrainSelectedInstOperands, |
| 36793 | // GIR_Coverage, 3057, |
| 36794 | GIR_EraseRootFromParent_Done, |
| 36795 | // Label 2002: @119411 |
| 36796 | GIM_Try, /*On fail goto*//*Label 2003*/ GIMT_Encode4(119450), // Rule ID 3074 // |
| 36797 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 36799 | // MIs[0] sbase |
| 36800 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 36801 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 36802 | // (ld:{ *:[v8f64] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v8f64] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 36803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 36804 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36805 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 36806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36809 | GIR_RootConstrainSelectedInstOperands, |
| 36810 | // GIR_Coverage, 3074, |
| 36811 | GIR_EraseRootFromParent_Done, |
| 36812 | // Label 2003: @119450 |
| 36813 | GIM_Reject, |
| 36814 | // Label 1969: @119451 |
| 36815 | GIM_Reject, |
| 36816 | // Label 868: @119452 |
| 36817 | GIM_Try, /*On fail goto*//*Label 2004*/ GIMT_Encode4(122070), |
| 36818 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 36819 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 36820 | GIM_Try, /*On fail goto*//*Label 2005*/ GIMT_Encode4(119524), // Rule ID 2960 // |
| 36821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36825 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36826 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36827 | // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36834 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36835 | GIR_RootConstrainSelectedInstOperands, |
| 36836 | // GIR_Coverage, 2960, |
| 36837 | GIR_EraseRootFromParent_Done, |
| 36838 | // Label 2005: @119524 |
| 36839 | GIM_Try, /*On fail goto*//*Label 2006*/ GIMT_Encode4(119583), // Rule ID 2977 // |
| 36840 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36841 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36843 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36844 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36845 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36846 | // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36854 | GIR_RootConstrainSelectedInstOperands, |
| 36855 | // GIR_Coverage, 2977, |
| 36856 | GIR_EraseRootFromParent_Done, |
| 36857 | // Label 2006: @119583 |
| 36858 | GIM_Try, /*On fail goto*//*Label 2007*/ GIMT_Encode4(119642), // Rule ID 2994 // |
| 36859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36860 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36862 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36863 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36865 | // (ld:{ *:[v16bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36873 | GIR_RootConstrainSelectedInstOperands, |
| 36874 | // GIR_Coverage, 2994, |
| 36875 | GIR_EraseRootFromParent_Done, |
| 36876 | // Label 2007: @119642 |
| 36877 | GIM_Try, /*On fail goto*//*Label 2008*/ GIMT_Encode4(119697), // Rule ID 2965 // |
| 36878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36879 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36883 | // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 36885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36891 | GIR_RootConstrainSelectedInstOperands, |
| 36892 | // GIR_Coverage, 2965, |
| 36893 | GIR_EraseRootFromParent_Done, |
| 36894 | // Label 2008: @119697 |
| 36895 | GIM_Try, /*On fail goto*//*Label 2009*/ GIMT_Encode4(119752), // Rule ID 2982 // |
| 36896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36897 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36899 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36901 | // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 36903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36908 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36909 | GIR_RootConstrainSelectedInstOperands, |
| 36910 | // GIR_Coverage, 2982, |
| 36911 | GIR_EraseRootFromParent_Done, |
| 36912 | // Label 2009: @119752 |
| 36913 | GIM_Try, /*On fail goto*//*Label 2010*/ GIMT_Encode4(119807), // Rule ID 2999 // |
| 36914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 36915 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36917 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36919 | // (ld:{ *:[v16bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 36921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36927 | GIR_RootConstrainSelectedInstOperands, |
| 36928 | // GIR_Coverage, 2999, |
| 36929 | GIR_EraseRootFromParent_Done, |
| 36930 | // Label 2010: @119807 |
| 36931 | GIM_Try, /*On fail goto*//*Label 2011*/ GIMT_Encode4(119862), // Rule ID 2971 // |
| 36932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36933 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36935 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36937 | // (ld:{ *:[v16i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36944 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36945 | GIR_RootConstrainSelectedInstOperands, |
| 36946 | // GIR_Coverage, 2971, |
| 36947 | GIR_EraseRootFromParent_Done, |
| 36948 | // Label 2011: @119862 |
| 36949 | GIM_Try, /*On fail goto*//*Label 2012*/ GIMT_Encode4(119917), // Rule ID 2988 // |
| 36950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36951 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36953 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36954 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36955 | // (ld:{ *:[v16f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36963 | GIR_RootConstrainSelectedInstOperands, |
| 36964 | // GIR_Coverage, 2988, |
| 36965 | GIR_EraseRootFromParent_Done, |
| 36966 | // Label 2012: @119917 |
| 36967 | GIM_Try, /*On fail goto*//*Label 2013*/ GIMT_Encode4(119972), // Rule ID 3005 // |
| 36968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 36969 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36971 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36972 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 36973 | // (ld:{ *:[v16bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 36975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 36978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 36979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36981 | GIR_RootConstrainSelectedInstOperands, |
| 36982 | // GIR_Coverage, 3005, |
| 36983 | GIR_EraseRootFromParent_Done, |
| 36984 | // Label 2013: @119972 |
| 36985 | GIM_Try, /*On fail goto*//*Label 2014*/ GIMT_Encode4(120026), // Rule ID 2956 // |
| 36986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 36987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 36988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 36989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 36990 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 36991 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 36992 | // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 36993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 36994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 36995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 36996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 36997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 36998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 36999 | GIR_RootConstrainSelectedInstOperands, |
| 37000 | // GIR_Coverage, 2956, |
| 37001 | GIR_EraseRootFromParent_Done, |
| 37002 | // Label 2014: @120026 |
| 37003 | GIM_Try, /*On fail goto*//*Label 2015*/ GIMT_Encode4(120080), // Rule ID 2957 // |
| 37004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 37005 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37008 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37010 | // (ld:{ *:[v16i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37017 | GIR_RootConstrainSelectedInstOperands, |
| 37018 | // GIR_Coverage, 2957, |
| 37019 | GIR_EraseRootFromParent_Done, |
| 37020 | // Label 2015: @120080 |
| 37021 | GIM_Try, /*On fail goto*//*Label 2016*/ GIMT_Encode4(120134), // Rule ID 2958 // |
| 37022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37023 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37025 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37026 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37028 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37034 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37035 | GIR_RootConstrainSelectedInstOperands, |
| 37036 | // GIR_Coverage, 2958, |
| 37037 | GIR_EraseRootFromParent_Done, |
| 37038 | // Label 2016: @120134 |
| 37039 | GIM_Try, /*On fail goto*//*Label 2017*/ GIMT_Encode4(120191), // Rule ID 2959 // |
| 37040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37041 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37044 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37046 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37053 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37054 | GIR_RootConstrainSelectedInstOperands, |
| 37055 | // GIR_Coverage, 2959, |
| 37056 | GIR_EraseRootFromParent_Done, |
| 37057 | // Label 2017: @120191 |
| 37058 | GIM_Try, /*On fail goto*//*Label 2018*/ GIMT_Encode4(120245), // Rule ID 2973 // |
| 37059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37063 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37065 | // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37072 | GIR_RootConstrainSelectedInstOperands, |
| 37073 | // GIR_Coverage, 2973, |
| 37074 | GIR_EraseRootFromParent_Done, |
| 37075 | // Label 2018: @120245 |
| 37076 | GIM_Try, /*On fail goto*//*Label 2019*/ GIMT_Encode4(120299), // Rule ID 2974 // |
| 37077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 37078 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37081 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37082 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37083 | // (ld:{ *:[v16f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37089 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37090 | GIR_RootConstrainSelectedInstOperands, |
| 37091 | // GIR_Coverage, 2974, |
| 37092 | GIR_EraseRootFromParent_Done, |
| 37093 | // Label 2019: @120299 |
| 37094 | GIM_Try, /*On fail goto*//*Label 2020*/ GIMT_Encode4(120353), // Rule ID 2975 // |
| 37095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37096 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37098 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37099 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37101 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37107 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37108 | GIR_RootConstrainSelectedInstOperands, |
| 37109 | // GIR_Coverage, 2975, |
| 37110 | GIR_EraseRootFromParent_Done, |
| 37111 | // Label 2020: @120353 |
| 37112 | GIM_Try, /*On fail goto*//*Label 2021*/ GIMT_Encode4(120410), // Rule ID 2976 // |
| 37113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37114 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37116 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37117 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37118 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37119 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37127 | GIR_RootConstrainSelectedInstOperands, |
| 37128 | // GIR_Coverage, 2976, |
| 37129 | GIR_EraseRootFromParent_Done, |
| 37130 | // Label 2021: @120410 |
| 37131 | GIM_Try, /*On fail goto*//*Label 2022*/ GIMT_Encode4(120464), // Rule ID 2990 // |
| 37132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37133 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37135 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37136 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37137 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37138 | // (ld:{ *:[v16bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37145 | GIR_RootConstrainSelectedInstOperands, |
| 37146 | // GIR_Coverage, 2990, |
| 37147 | GIR_EraseRootFromParent_Done, |
| 37148 | // Label 2022: @120464 |
| 37149 | GIM_Try, /*On fail goto*//*Label 2023*/ GIMT_Encode4(120518), // Rule ID 2991 // |
| 37150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 37151 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37153 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37154 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37155 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37156 | // (ld:{ *:[v16bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37162 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37163 | GIR_RootConstrainSelectedInstOperands, |
| 37164 | // GIR_Coverage, 2991, |
| 37165 | GIR_EraseRootFromParent_Done, |
| 37166 | // Label 2023: @120518 |
| 37167 | GIM_Try, /*On fail goto*//*Label 2024*/ GIMT_Encode4(120572), // Rule ID 2992 // |
| 37168 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37169 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37171 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37172 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37174 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37181 | GIR_RootConstrainSelectedInstOperands, |
| 37182 | // GIR_Coverage, 2992, |
| 37183 | GIR_EraseRootFromParent_Done, |
| 37184 | // Label 2024: @120572 |
| 37185 | GIM_Try, /*On fail goto*//*Label 2025*/ GIMT_Encode4(120629), // Rule ID 2993 // |
| 37186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37187 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37190 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37191 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37192 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37199 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37200 | GIR_RootConstrainSelectedInstOperands, |
| 37201 | // GIR_Coverage, 2993, |
| 37202 | GIR_EraseRootFromParent_Done, |
| 37203 | // Label 2025: @120629 |
| 37204 | GIM_Try, /*On fail goto*//*Label 2026*/ GIMT_Encode4(120679), // Rule ID 2962 // |
| 37205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37206 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37208 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37210 | // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37217 | GIR_RootConstrainSelectedInstOperands, |
| 37218 | // GIR_Coverage, 2962, |
| 37219 | GIR_EraseRootFromParent_Done, |
| 37220 | // Label 2026: @120679 |
| 37221 | GIM_Try, /*On fail goto*//*Label 2027*/ GIMT_Encode4(120729), // Rule ID 2963 // |
| 37222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37225 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37227 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 37229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37233 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37234 | GIR_RootConstrainSelectedInstOperands, |
| 37235 | // GIR_Coverage, 2963, |
| 37236 | GIR_EraseRootFromParent_Done, |
| 37237 | // Label 2027: @120729 |
| 37238 | GIM_Try, /*On fail goto*//*Label 2028*/ GIMT_Encode4(120782), // Rule ID 2964 // |
| 37239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37240 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37242 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37244 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 37246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37251 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37252 | GIR_RootConstrainSelectedInstOperands, |
| 37253 | // GIR_Coverage, 2964, |
| 37254 | GIR_EraseRootFromParent_Done, |
| 37255 | // Label 2028: @120782 |
| 37256 | GIM_Try, /*On fail goto*//*Label 2029*/ GIMT_Encode4(120832), // Rule ID 2979 // |
| 37257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37258 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37260 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37262 | // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37268 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37269 | GIR_RootConstrainSelectedInstOperands, |
| 37270 | // GIR_Coverage, 2979, |
| 37271 | GIR_EraseRootFromParent_Done, |
| 37272 | // Label 2029: @120832 |
| 37273 | GIM_Try, /*On fail goto*//*Label 2030*/ GIMT_Encode4(120882), // Rule ID 2980 // |
| 37274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37275 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37277 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37279 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 37281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37285 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37286 | GIR_RootConstrainSelectedInstOperands, |
| 37287 | // GIR_Coverage, 2980, |
| 37288 | GIR_EraseRootFromParent_Done, |
| 37289 | // Label 2030: @120882 |
| 37290 | GIM_Try, /*On fail goto*//*Label 2031*/ GIMT_Encode4(120935), // Rule ID 2981 // |
| 37291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37292 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37294 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37296 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 37298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37304 | GIR_RootConstrainSelectedInstOperands, |
| 37305 | // GIR_Coverage, 2981, |
| 37306 | GIR_EraseRootFromParent_Done, |
| 37307 | // Label 2031: @120935 |
| 37308 | GIM_Try, /*On fail goto*//*Label 2032*/ GIMT_Encode4(120985), // Rule ID 2996 // |
| 37309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37310 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37312 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37314 | // (ld:{ *:[v16bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37320 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37321 | GIR_RootConstrainSelectedInstOperands, |
| 37322 | // GIR_Coverage, 2996, |
| 37323 | GIR_EraseRootFromParent_Done, |
| 37324 | // Label 2032: @120985 |
| 37325 | GIM_Try, /*On fail goto*//*Label 2033*/ GIMT_Encode4(121035), // Rule ID 2997 // |
| 37326 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37327 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37329 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37330 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37331 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_ec:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_ec), |
| 37333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37338 | GIR_RootConstrainSelectedInstOperands, |
| 37339 | // GIR_Coverage, 2997, |
| 37340 | GIR_EraseRootFromParent_Done, |
| 37341 | // Label 2033: @121035 |
| 37342 | GIM_Try, /*On fail goto*//*Label 2034*/ GIMT_Encode4(121088), // Rule ID 2998 // |
| 37343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37344 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37345 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37346 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37347 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37348 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM_ec:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM_ec), |
| 37350 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37356 | GIR_RootConstrainSelectedInstOperands, |
| 37357 | // GIR_Coverage, 2998, |
| 37358 | GIR_EraseRootFromParent_Done, |
| 37359 | // Label 2034: @121088 |
| 37360 | GIM_Try, /*On fail goto*//*Label 2035*/ GIMT_Encode4(121135), // Rule ID 2967 // |
| 37361 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37365 | // (ld:{ *:[v16i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37372 | GIR_RootConstrainSelectedInstOperands, |
| 37373 | // GIR_Coverage, 2967, |
| 37374 | GIR_EraseRootFromParent_Done, |
| 37375 | // Label 2035: @121135 |
| 37376 | GIM_Try, /*On fail goto*//*Label 2036*/ GIMT_Encode4(121185), // Rule ID 2968 // |
| 37377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 37378 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37380 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37381 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37382 | // (ld:{ *:[v16i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37388 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37389 | GIR_RootConstrainSelectedInstOperands, |
| 37390 | // GIR_Coverage, 2968, |
| 37391 | GIR_EraseRootFromParent_Done, |
| 37392 | // Label 2036: @121185 |
| 37393 | GIM_Try, /*On fail goto*//*Label 2037*/ GIMT_Encode4(121235), // Rule ID 2969 // |
| 37394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 37395 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37397 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37399 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37405 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37406 | GIR_RootConstrainSelectedInstOperands, |
| 37407 | // GIR_Coverage, 2969, |
| 37408 | GIR_EraseRootFromParent_Done, |
| 37409 | // Label 2037: @121235 |
| 37410 | GIM_Try, /*On fail goto*//*Label 2038*/ GIMT_Encode4(121288), // Rule ID 2970 // |
| 37411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 37412 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37414 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37416 | // (ld:{ *:[v16i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37424 | GIR_RootConstrainSelectedInstOperands, |
| 37425 | // GIR_Coverage, 2970, |
| 37426 | GIR_EraseRootFromParent_Done, |
| 37427 | // Label 2038: @121288 |
| 37428 | GIM_Try, /*On fail goto*//*Label 2039*/ GIMT_Encode4(121335), // Rule ID 2984 // |
| 37429 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37433 | // (ld:{ *:[v16f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37440 | GIR_RootConstrainSelectedInstOperands, |
| 37441 | // GIR_Coverage, 2984, |
| 37442 | GIR_EraseRootFromParent_Done, |
| 37443 | // Label 2039: @121335 |
| 37444 | GIM_Try, /*On fail goto*//*Label 2040*/ GIMT_Encode4(121385), // Rule ID 2985 // |
| 37445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 37446 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37450 | // (ld:{ *:[v16f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37456 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37457 | GIR_RootConstrainSelectedInstOperands, |
| 37458 | // GIR_Coverage, 2985, |
| 37459 | GIR_EraseRootFromParent_Done, |
| 37460 | // Label 2040: @121385 |
| 37461 | GIM_Try, /*On fail goto*//*Label 2041*/ GIMT_Encode4(121435), // Rule ID 2986 // |
| 37462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 37463 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37465 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37467 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37474 | GIR_RootConstrainSelectedInstOperands, |
| 37475 | // GIR_Coverage, 2986, |
| 37476 | GIR_EraseRootFromParent_Done, |
| 37477 | // Label 2041: @121435 |
| 37478 | GIM_Try, /*On fail goto*//*Label 2042*/ GIMT_Encode4(121488), // Rule ID 2987 // |
| 37479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 37480 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37484 | // (ld:{ *:[v16f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37491 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37492 | GIR_RootConstrainSelectedInstOperands, |
| 37493 | // GIR_Coverage, 2987, |
| 37494 | GIR_EraseRootFromParent_Done, |
| 37495 | // Label 2042: @121488 |
| 37496 | GIM_Try, /*On fail goto*//*Label 2043*/ GIMT_Encode4(121535), // Rule ID 3001 // |
| 37497 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37499 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37500 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37501 | // (ld:{ *:[v16bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37508 | GIR_RootConstrainSelectedInstOperands, |
| 37509 | // GIR_Coverage, 3001, |
| 37510 | GIR_EraseRootFromParent_Done, |
| 37511 | // Label 2043: @121535 |
| 37512 | GIM_Try, /*On fail goto*//*Label 2044*/ GIMT_Encode4(121585), // Rule ID 3002 // |
| 37513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 37514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37516 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37517 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37518 | // (ld:{ *:[v16bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ci:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ci), |
| 37520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37524 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37525 | GIR_RootConstrainSelectedInstOperands, |
| 37526 | // GIR_Coverage, 3002, |
| 37527 | GIR_EraseRootFromParent_Done, |
| 37528 | // Label 2044: @121585 |
| 37529 | GIM_Try, /*On fail goto*//*Label 2045*/ GIMT_Encode4(121635), // Rule ID 3003 // |
| 37530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 37531 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37532 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37533 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37535 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR), |
| 37537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37541 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37542 | GIR_RootConstrainSelectedInstOperands, |
| 37543 | // GIR_Coverage, 3003, |
| 37544 | GIR_EraseRootFromParent_Done, |
| 37545 | // Label 2045: @121635 |
| 37546 | GIM_Try, /*On fail goto*//*Label 2046*/ GIMT_Encode4(121688), // Rule ID 3004 // |
| 37547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 37548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37550 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37552 | // (ld:{ *:[v16bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_SGPR_IMM:{ *:[v16bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_SGPR_IMM), |
| 37554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37559 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37560 | GIR_RootConstrainSelectedInstOperands, |
| 37561 | // GIR_Coverage, 3004, |
| 37562 | GIR_EraseRootFromParent_Done, |
| 37563 | // Label 2046: @121688 |
| 37564 | GIM_Try, /*On fail goto*//*Label 2047*/ GIMT_Encode4(121734), // Rule ID 2961 // |
| 37565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37566 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37567 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37568 | // MIs[0] sbase |
| 37569 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37570 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37571 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37572 | // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37575 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37578 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37579 | GIR_RootConstrainSelectedInstOperands, |
| 37580 | // GIR_Coverage, 2961, |
| 37581 | GIR_EraseRootFromParent_Done, |
| 37582 | // Label 2047: @121734 |
| 37583 | GIM_Try, /*On fail goto*//*Label 2048*/ GIMT_Encode4(121780), // Rule ID 2978 // |
| 37584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37585 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37587 | // MIs[0] sbase |
| 37588 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37589 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37590 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37591 | // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37594 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37598 | GIR_RootConstrainSelectedInstOperands, |
| 37599 | // GIR_Coverage, 2978, |
| 37600 | GIR_EraseRootFromParent_Done, |
| 37601 | // Label 2048: @121780 |
| 37602 | GIM_Try, /*On fail goto*//*Label 2049*/ GIMT_Encode4(121826), // Rule ID 2995 // |
| 37603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37606 | // MIs[0] sbase |
| 37607 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37608 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37609 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37610 | // (ld:{ *:[v16bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37613 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37617 | GIR_RootConstrainSelectedInstOperands, |
| 37618 | // GIR_Coverage, 2995, |
| 37619 | GIR_EraseRootFromParent_Done, |
| 37620 | // Label 2049: @121826 |
| 37621 | GIM_Try, /*On fail goto*//*Label 2050*/ GIMT_Encode4(121868), // Rule ID 2966 // |
| 37622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37623 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37624 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37625 | // MIs[0] sbase |
| 37626 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37627 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37628 | // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37631 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37634 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37635 | GIR_RootConstrainSelectedInstOperands, |
| 37636 | // GIR_Coverage, 2966, |
| 37637 | GIR_EraseRootFromParent_Done, |
| 37638 | // Label 2050: @121868 |
| 37639 | GIM_Try, /*On fail goto*//*Label 2051*/ GIMT_Encode4(121910), // Rule ID 2983 // |
| 37640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37641 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37643 | // MIs[0] sbase |
| 37644 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37645 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37646 | // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37649 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37652 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37653 | GIR_RootConstrainSelectedInstOperands, |
| 37654 | // GIR_Coverage, 2983, |
| 37655 | GIR_EraseRootFromParent_Done, |
| 37656 | // Label 2051: @121910 |
| 37657 | GIM_Try, /*On fail goto*//*Label 2052*/ GIMT_Encode4(121952), // Rule ID 3000 // |
| 37658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37659 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37661 | // MIs[0] sbase |
| 37662 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37663 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37664 | // (ld:{ *:[v16bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM_ec:{ *:[v16bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM_ec), |
| 37666 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37667 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37670 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37671 | GIR_RootConstrainSelectedInstOperands, |
| 37672 | // GIR_Coverage, 3000, |
| 37673 | GIR_EraseRootFromParent_Done, |
| 37674 | // Label 2052: @121952 |
| 37675 | GIM_Try, /*On fail goto*//*Label 2053*/ GIMT_Encode4(121991), // Rule ID 2972 // |
| 37676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37678 | // MIs[0] sbase |
| 37679 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37680 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37681 | // (ld:{ *:[v16i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37684 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37688 | GIR_RootConstrainSelectedInstOperands, |
| 37689 | // GIR_Coverage, 2972, |
| 37690 | GIR_EraseRootFromParent_Done, |
| 37691 | // Label 2053: @121991 |
| 37692 | GIM_Try, /*On fail goto*//*Label 2054*/ GIMT_Encode4(122030), // Rule ID 2989 // |
| 37693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37695 | // MIs[0] sbase |
| 37696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37697 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37698 | // (ld:{ *:[v16f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37701 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37704 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37705 | GIR_RootConstrainSelectedInstOperands, |
| 37706 | // GIR_Coverage, 2989, |
| 37707 | GIR_EraseRootFromParent_Done, |
| 37708 | // Label 2054: @122030 |
| 37709 | GIM_Try, /*On fail goto*//*Label 2055*/ GIMT_Encode4(122069), // Rule ID 3006 // |
| 37710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 37712 | // MIs[0] sbase |
| 37713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 37714 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 37715 | // (ld:{ *:[v16bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX8_IMM:{ *:[v16bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX8_IMM), |
| 37717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37718 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 37719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37721 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37722 | GIR_RootConstrainSelectedInstOperands, |
| 37723 | // GIR_Coverage, 3006, |
| 37724 | GIR_EraseRootFromParent_Done, |
| 37725 | // Label 2055: @122069 |
| 37726 | GIM_Reject, |
| 37727 | // Label 2004: @122070 |
| 37728 | GIM_Reject, |
| 37729 | // Label 869: @122071 |
| 37730 | GIM_Try, /*On fail goto*//*Label 2056*/ GIMT_Encode4(123821), |
| 37731 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 37732 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 37733 | GIM_Try, /*On fail goto*//*Label 2057*/ GIMT_Encode4(122143), // Rule ID 3011 // |
| 37734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37735 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37737 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37738 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37739 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37740 | // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37747 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37748 | GIR_RootConstrainSelectedInstOperands, |
| 37749 | // GIR_Coverage, 3011, |
| 37750 | GIR_EraseRootFromParent_Done, |
| 37751 | // Label 2057: @122143 |
| 37752 | GIM_Try, /*On fail goto*//*Label 2058*/ GIMT_Encode4(122202), // Rule ID 3028 // |
| 37753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37754 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37756 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37757 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37759 | // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37766 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37767 | GIR_RootConstrainSelectedInstOperands, |
| 37768 | // GIR_Coverage, 3028, |
| 37769 | GIR_EraseRootFromParent_Done, |
| 37770 | // Label 2058: @122202 |
| 37771 | GIM_Try, /*On fail goto*//*Label 2059*/ GIMT_Encode4(122257), // Rule ID 3016 // |
| 37772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37773 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37775 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37777 | // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 37779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37785 | GIR_RootConstrainSelectedInstOperands, |
| 37786 | // GIR_Coverage, 3016, |
| 37787 | GIR_EraseRootFromParent_Done, |
| 37788 | // Label 2059: @122257 |
| 37789 | GIM_Try, /*On fail goto*//*Label 2060*/ GIMT_Encode4(122312), // Rule ID 3033 // |
| 37790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37791 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37795 | // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 37797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37803 | GIR_RootConstrainSelectedInstOperands, |
| 37804 | // GIR_Coverage, 3033, |
| 37805 | GIR_EraseRootFromParent_Done, |
| 37806 | // Label 2060: @122312 |
| 37807 | GIM_Try, /*On fail goto*//*Label 2061*/ GIMT_Encode4(122367), // Rule ID 3022 // |
| 37808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 37809 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37813 | // (ld:{ *:[v16i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37821 | GIR_RootConstrainSelectedInstOperands, |
| 37822 | // GIR_Coverage, 3022, |
| 37823 | GIR_EraseRootFromParent_Done, |
| 37824 | // Label 2061: @122367 |
| 37825 | GIM_Try, /*On fail goto*//*Label 2062*/ GIMT_Encode4(122422), // Rule ID 3039 // |
| 37826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 37827 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 37831 | // (ld:{ *:[v16f32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 37837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37838 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37839 | GIR_RootConstrainSelectedInstOperands, |
| 37840 | // GIR_Coverage, 3039, |
| 37841 | GIR_EraseRootFromParent_Done, |
| 37842 | // Label 2062: @122422 |
| 37843 | GIM_Try, /*On fail goto*//*Label 2063*/ GIMT_Encode4(122476), // Rule ID 3007 // |
| 37844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37847 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37848 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37849 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37850 | // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 37852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37857 | GIR_RootConstrainSelectedInstOperands, |
| 37858 | // GIR_Coverage, 3007, |
| 37859 | GIR_EraseRootFromParent_Done, |
| 37860 | // Label 2063: @122476 |
| 37861 | GIM_Try, /*On fail goto*//*Label 2064*/ GIMT_Encode4(122530), // Rule ID 3008 // |
| 37862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 37863 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37866 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37868 | // (ld:{ *:[v16i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 37870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37874 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37875 | GIR_RootConstrainSelectedInstOperands, |
| 37876 | // GIR_Coverage, 3008, |
| 37877 | GIR_EraseRootFromParent_Done, |
| 37878 | // Label 2064: @122530 |
| 37879 | GIM_Try, /*On fail goto*//*Label 2065*/ GIMT_Encode4(122584), // Rule ID 3009 // |
| 37880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37881 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37883 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37884 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37885 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37886 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 37888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37892 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37893 | GIR_RootConstrainSelectedInstOperands, |
| 37894 | // GIR_Coverage, 3009, |
| 37895 | GIR_EraseRootFromParent_Done, |
| 37896 | // Label 2065: @122584 |
| 37897 | GIM_Try, /*On fail goto*//*Label 2066*/ GIMT_Encode4(122641), // Rule ID 3010 // |
| 37898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37899 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37901 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37903 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37904 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37912 | GIR_RootConstrainSelectedInstOperands, |
| 37913 | // GIR_Coverage, 3010, |
| 37914 | GIR_EraseRootFromParent_Done, |
| 37915 | // Label 2066: @122641 |
| 37916 | GIM_Try, /*On fail goto*//*Label 2067*/ GIMT_Encode4(122695), // Rule ID 3024 // |
| 37917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37918 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37920 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37921 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37923 | // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 37925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37930 | GIR_RootConstrainSelectedInstOperands, |
| 37931 | // GIR_Coverage, 3024, |
| 37932 | GIR_EraseRootFromParent_Done, |
| 37933 | // Label 2067: @122695 |
| 37934 | GIM_Try, /*On fail goto*//*Label 2068*/ GIMT_Encode4(122749), // Rule ID 3025 // |
| 37935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 37936 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37939 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 37941 | // (ld:{ *:[v16f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 37943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 37946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37948 | GIR_RootConstrainSelectedInstOperands, |
| 37949 | // GIR_Coverage, 3025, |
| 37950 | GIR_EraseRootFromParent_Done, |
| 37951 | // Label 2068: @122749 |
| 37952 | GIM_Try, /*On fail goto*//*Label 2069*/ GIMT_Encode4(122803), // Rule ID 3026 // |
| 37953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 37954 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37956 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37957 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37958 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37959 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 37960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 37961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37965 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37966 | GIR_RootConstrainSelectedInstOperands, |
| 37967 | // GIR_Coverage, 3026, |
| 37968 | GIR_EraseRootFromParent_Done, |
| 37969 | // Label 2069: @122803 |
| 37970 | GIM_Try, /*On fail goto*//*Label 2070*/ GIMT_Encode4(122860), // Rule ID 3027 // |
| 37971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 37972 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37974 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37975 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 37976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 37977 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 37978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 37979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 37982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 37984 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 37985 | GIR_RootConstrainSelectedInstOperands, |
| 37986 | // GIR_Coverage, 3027, |
| 37987 | GIR_EraseRootFromParent_Done, |
| 37988 | // Label 2070: @122860 |
| 37989 | GIM_Try, /*On fail goto*//*Label 2071*/ GIMT_Encode4(122910), // Rule ID 3013 // |
| 37990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 37991 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 37992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 37993 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 37994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 37995 | // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 37996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 37997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 37998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 37999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38001 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38002 | GIR_RootConstrainSelectedInstOperands, |
| 38003 | // GIR_Coverage, 3013, |
| 38004 | GIR_EraseRootFromParent_Done, |
| 38005 | // Label 2071: @122910 |
| 38006 | GIM_Try, /*On fail goto*//*Label 2072*/ GIMT_Encode4(122960), // Rule ID 3014 // |
| 38007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38008 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38010 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38012 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 38014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38019 | GIR_RootConstrainSelectedInstOperands, |
| 38020 | // GIR_Coverage, 3014, |
| 38021 | GIR_EraseRootFromParent_Done, |
| 38022 | // Label 2072: @122960 |
| 38023 | GIM_Try, /*On fail goto*//*Label 2073*/ GIMT_Encode4(123013), // Rule ID 3015 // |
| 38024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38025 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38026 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38029 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38037 | GIR_RootConstrainSelectedInstOperands, |
| 38038 | // GIR_Coverage, 3015, |
| 38039 | GIR_EraseRootFromParent_Done, |
| 38040 | // Label 2073: @123013 |
| 38041 | GIM_Try, /*On fail goto*//*Label 2074*/ GIMT_Encode4(123063), // Rule ID 3030 // |
| 38042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38043 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38045 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38046 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38047 | // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38053 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38054 | GIR_RootConstrainSelectedInstOperands, |
| 38055 | // GIR_Coverage, 3030, |
| 38056 | GIR_EraseRootFromParent_Done, |
| 38057 | // Label 2074: @123063 |
| 38058 | GIM_Try, /*On fail goto*//*Label 2075*/ GIMT_Encode4(123113), // Rule ID 3031 // |
| 38059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38064 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 38066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38070 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38071 | GIR_RootConstrainSelectedInstOperands, |
| 38072 | // GIR_Coverage, 3031, |
| 38073 | GIR_EraseRootFromParent_Done, |
| 38074 | // Label 2075: @123113 |
| 38075 | GIM_Try, /*On fail goto*//*Label 2076*/ GIMT_Encode4(123166), // Rule ID 3032 // |
| 38076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38077 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38079 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38081 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38088 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38089 | GIR_RootConstrainSelectedInstOperands, |
| 38090 | // GIR_Coverage, 3032, |
| 38091 | GIR_EraseRootFromParent_Done, |
| 38092 | // Label 2076: @123166 |
| 38093 | GIM_Try, /*On fail goto*//*Label 2077*/ GIMT_Encode4(123213), // Rule ID 3018 // |
| 38094 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38096 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38097 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38098 | // (ld:{ *:[v16i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38104 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38105 | GIR_RootConstrainSelectedInstOperands, |
| 38106 | // GIR_Coverage, 3018, |
| 38107 | GIR_EraseRootFromParent_Done, |
| 38108 | // Label 2077: @123213 |
| 38109 | GIM_Try, /*On fail goto*//*Label 2078*/ GIMT_Encode4(123263), // Rule ID 3019 // |
| 38110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 38111 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38113 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38115 | // (ld:{ *:[v16i32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38121 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38122 | GIR_RootConstrainSelectedInstOperands, |
| 38123 | // GIR_Coverage, 3019, |
| 38124 | GIR_EraseRootFromParent_Done, |
| 38125 | // Label 2078: @123263 |
| 38126 | GIM_Try, /*On fail goto*//*Label 2079*/ GIMT_Encode4(123313), // Rule ID 3020 // |
| 38127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 38128 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38130 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38131 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38132 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38139 | GIR_RootConstrainSelectedInstOperands, |
| 38140 | // GIR_Coverage, 3020, |
| 38141 | GIR_EraseRootFromParent_Done, |
| 38142 | // Label 2079: @123313 |
| 38143 | GIM_Try, /*On fail goto*//*Label 2080*/ GIMT_Encode4(123366), // Rule ID 3021 // |
| 38144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38149 | // (ld:{ *:[v16i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38157 | GIR_RootConstrainSelectedInstOperands, |
| 38158 | // GIR_Coverage, 3021, |
| 38159 | GIR_EraseRootFromParent_Done, |
| 38160 | // Label 2080: @123366 |
| 38161 | GIM_Try, /*On fail goto*//*Label 2081*/ GIMT_Encode4(123413), // Rule ID 3035 // |
| 38162 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38164 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38165 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38166 | // (ld:{ *:[v16f32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38173 | GIR_RootConstrainSelectedInstOperands, |
| 38174 | // GIR_Coverage, 3035, |
| 38175 | GIR_EraseRootFromParent_Done, |
| 38176 | // Label 2081: @123413 |
| 38177 | GIM_Try, /*On fail goto*//*Label 2082*/ GIMT_Encode4(123463), // Rule ID 3036 // |
| 38178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 38179 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38181 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38183 | // (ld:{ *:[v16f32] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38189 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38190 | GIR_RootConstrainSelectedInstOperands, |
| 38191 | // GIR_Coverage, 3036, |
| 38192 | GIR_EraseRootFromParent_Done, |
| 38193 | // Label 2082: @123463 |
| 38194 | GIM_Try, /*On fail goto*//*Label 2083*/ GIMT_Encode4(123513), // Rule ID 3037 // |
| 38195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 38196 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38198 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38200 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38207 | GIR_RootConstrainSelectedInstOperands, |
| 38208 | // GIR_Coverage, 3037, |
| 38209 | GIR_EraseRootFromParent_Done, |
| 38210 | // Label 2083: @123513 |
| 38211 | GIM_Try, /*On fail goto*//*Label 2084*/ GIMT_Encode4(123566), // Rule ID 3038 // |
| 38212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38213 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38214 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38217 | // (ld:{ *:[v16f32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38224 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38225 | GIR_RootConstrainSelectedInstOperands, |
| 38226 | // GIR_Coverage, 3038, |
| 38227 | GIR_EraseRootFromParent_Done, |
| 38228 | // Label 2084: @123566 |
| 38229 | GIM_Try, /*On fail goto*//*Label 2085*/ GIMT_Encode4(123612), // Rule ID 3012 // |
| 38230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38231 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38233 | // MIs[0] sbase |
| 38234 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38235 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38236 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38237 | // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38240 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38243 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38244 | GIR_RootConstrainSelectedInstOperands, |
| 38245 | // GIR_Coverage, 3012, |
| 38246 | GIR_EraseRootFromParent_Done, |
| 38247 | // Label 2085: @123612 |
| 38248 | GIM_Try, /*On fail goto*//*Label 2086*/ GIMT_Encode4(123658), // Rule ID 3029 // |
| 38249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38250 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38252 | // MIs[0] sbase |
| 38253 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38254 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38255 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38256 | // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38259 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38262 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38263 | GIR_RootConstrainSelectedInstOperands, |
| 38264 | // GIR_Coverage, 3029, |
| 38265 | GIR_EraseRootFromParent_Done, |
| 38266 | // Label 2086: @123658 |
| 38267 | GIM_Try, /*On fail goto*//*Label 2087*/ GIMT_Encode4(123700), // Rule ID 3017 // |
| 38268 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38269 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38271 | // MIs[0] sbase |
| 38272 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38274 | // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38277 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38281 | GIR_RootConstrainSelectedInstOperands, |
| 38282 | // GIR_Coverage, 3017, |
| 38283 | GIR_EraseRootFromParent_Done, |
| 38284 | // Label 2087: @123700 |
| 38285 | GIM_Try, /*On fail goto*//*Label 2088*/ GIMT_Encode4(123742), // Rule ID 3034 // |
| 38286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38287 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38289 | // MIs[0] sbase |
| 38290 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38291 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38292 | // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38295 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38298 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38299 | GIR_RootConstrainSelectedInstOperands, |
| 38300 | // GIR_Coverage, 3034, |
| 38301 | GIR_EraseRootFromParent_Done, |
| 38302 | // Label 2088: @123742 |
| 38303 | GIM_Try, /*On fail goto*//*Label 2089*/ GIMT_Encode4(123781), // Rule ID 3023 // |
| 38304 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38306 | // MIs[0] sbase |
| 38307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38308 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38309 | // (ld:{ *:[v16i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38312 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38316 | GIR_RootConstrainSelectedInstOperands, |
| 38317 | // GIR_Coverage, 3023, |
| 38318 | GIR_EraseRootFromParent_Done, |
| 38319 | // Label 2089: @123781 |
| 38320 | GIM_Try, /*On fail goto*//*Label 2090*/ GIMT_Encode4(123820), // Rule ID 3040 // |
| 38321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38322 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38323 | // MIs[0] sbase |
| 38324 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 38325 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 38326 | // (ld:{ *:[v16f32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v16f32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38329 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 38330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38333 | GIR_RootConstrainSelectedInstOperands, |
| 38334 | // GIR_Coverage, 3040, |
| 38335 | GIR_EraseRootFromParent_Done, |
| 38336 | // Label 2090: @123820 |
| 38337 | GIM_Reject, |
| 38338 | // Label 2056: @123821 |
| 38339 | GIM_Reject, |
| 38340 | // Label 870: @123822 |
| 38341 | GIM_Try, /*On fail goto*//*Label 2091*/ GIMT_Encode4(126440), |
| 38342 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 38343 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_load), |
| 38344 | GIM_Try, /*On fail goto*//*Label 2092*/ GIMT_Encode4(123894), // Rule ID 3079 // |
| 38345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38346 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38348 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38349 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38351 | // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38358 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38359 | GIR_RootConstrainSelectedInstOperands, |
| 38360 | // GIR_Coverage, 3079, |
| 38361 | GIR_EraseRootFromParent_Done, |
| 38362 | // Label 2092: @123894 |
| 38363 | GIM_Try, /*On fail goto*//*Label 2093*/ GIMT_Encode4(123953), // Rule ID 3096 // |
| 38364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38365 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38367 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38368 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38370 | // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38378 | GIR_RootConstrainSelectedInstOperands, |
| 38379 | // GIR_Coverage, 3096, |
| 38380 | GIR_EraseRootFromParent_Done, |
| 38381 | // Label 2093: @123953 |
| 38382 | GIM_Try, /*On fail goto*//*Label 2094*/ GIMT_Encode4(124012), // Rule ID 3113 // |
| 38383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38384 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38387 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38388 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38389 | // (ld:{ *:[v32bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38397 | GIR_RootConstrainSelectedInstOperands, |
| 38398 | // GIR_Coverage, 3113, |
| 38399 | GIR_EraseRootFromParent_Done, |
| 38400 | // Label 2094: @124012 |
| 38401 | GIM_Try, /*On fail goto*//*Label 2095*/ GIMT_Encode4(124067), // Rule ID 3084 // |
| 38402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38403 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38407 | // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38415 | GIR_RootConstrainSelectedInstOperands, |
| 38416 | // GIR_Coverage, 3084, |
| 38417 | GIR_EraseRootFromParent_Done, |
| 38418 | // Label 2095: @124067 |
| 38419 | GIM_Try, /*On fail goto*//*Label 2096*/ GIMT_Encode4(124122), // Rule ID 3101 // |
| 38420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38421 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38423 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38424 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38425 | // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38433 | GIR_RootConstrainSelectedInstOperands, |
| 38434 | // GIR_Coverage, 3101, |
| 38435 | GIR_EraseRootFromParent_Done, |
| 38436 | // Label 2096: @124122 |
| 38437 | GIM_Try, /*On fail goto*//*Label 2097*/ GIMT_Encode4(124177), // Rule ID 3118 // |
| 38438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38439 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38441 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38442 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38443 | // (ld:{ *:[v32bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38450 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38451 | GIR_RootConstrainSelectedInstOperands, |
| 38452 | // GIR_Coverage, 3118, |
| 38453 | GIR_EraseRootFromParent_Done, |
| 38454 | // Label 2097: @124177 |
| 38455 | GIM_Try, /*On fail goto*//*Label 2098*/ GIMT_Encode4(124232), // Rule ID 3090 // |
| 38456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38457 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38459 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38460 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38461 | // (ld:{ *:[v32i16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38469 | GIR_RootConstrainSelectedInstOperands, |
| 38470 | // GIR_Coverage, 3090, |
| 38471 | GIR_EraseRootFromParent_Done, |
| 38472 | // Label 2098: @124232 |
| 38473 | GIM_Try, /*On fail goto*//*Label 2099*/ GIMT_Encode4(124287), // Rule ID 3107 // |
| 38474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38475 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38477 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38479 | // (ld:{ *:[v32f16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38487 | GIR_RootConstrainSelectedInstOperands, |
| 38488 | // GIR_Coverage, 3107, |
| 38489 | GIR_EraseRootFromParent_Done, |
| 38490 | // Label 2099: @124287 |
| 38491 | GIM_Try, /*On fail goto*//*Label 2100*/ GIMT_Encode4(124342), // Rule ID 3124 // |
| 38492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38493 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38495 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 38497 | // (ld:{ *:[v32bf16] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 38503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38505 | GIR_RootConstrainSelectedInstOperands, |
| 38506 | // GIR_Coverage, 3124, |
| 38507 | GIR_EraseRootFromParent_Done, |
| 38508 | // Label 2100: @124342 |
| 38509 | GIM_Try, /*On fail goto*//*Label 2101*/ GIMT_Encode4(124396), // Rule ID 3075 // |
| 38510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38511 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38513 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38514 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38516 | // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38523 | GIR_RootConstrainSelectedInstOperands, |
| 38524 | // GIR_Coverage, 3075, |
| 38525 | GIR_EraseRootFromParent_Done, |
| 38526 | // Label 2101: @124396 |
| 38527 | GIM_Try, /*On fail goto*//*Label 2102*/ GIMT_Encode4(124450), // Rule ID 3076 // |
| 38528 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 38529 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38532 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38534 | // (ld:{ *:[v32i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38541 | GIR_RootConstrainSelectedInstOperands, |
| 38542 | // GIR_Coverage, 3076, |
| 38543 | GIR_EraseRootFromParent_Done, |
| 38544 | // Label 2102: @124450 |
| 38545 | GIM_Try, /*On fail goto*//*Label 2103*/ GIMT_Encode4(124504), // Rule ID 3077 // |
| 38546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38547 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38550 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38552 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38558 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38559 | GIR_RootConstrainSelectedInstOperands, |
| 38560 | // GIR_Coverage, 3077, |
| 38561 | GIR_EraseRootFromParent_Done, |
| 38562 | // Label 2103: @124504 |
| 38563 | GIM_Try, /*On fail goto*//*Label 2104*/ GIMT_Encode4(124561), // Rule ID 3078 // |
| 38564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38565 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38567 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38568 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38569 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38570 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38577 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38578 | GIR_RootConstrainSelectedInstOperands, |
| 38579 | // GIR_Coverage, 3078, |
| 38580 | GIR_EraseRootFromParent_Done, |
| 38581 | // Label 2104: @124561 |
| 38582 | GIM_Try, /*On fail goto*//*Label 2105*/ GIMT_Encode4(124615), // Rule ID 3092 // |
| 38583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38584 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38587 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38588 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38589 | // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38596 | GIR_RootConstrainSelectedInstOperands, |
| 38597 | // GIR_Coverage, 3092, |
| 38598 | GIR_EraseRootFromParent_Done, |
| 38599 | // Label 2105: @124615 |
| 38600 | GIM_Try, /*On fail goto*//*Label 2106*/ GIMT_Encode4(124669), // Rule ID 3093 // |
| 38601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 38602 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38604 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38605 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38607 | // (ld:{ *:[v32f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38613 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38614 | GIR_RootConstrainSelectedInstOperands, |
| 38615 | // GIR_Coverage, 3093, |
| 38616 | GIR_EraseRootFromParent_Done, |
| 38617 | // Label 2106: @124669 |
| 38618 | GIM_Try, /*On fail goto*//*Label 2107*/ GIMT_Encode4(124723), // Rule ID 3094 // |
| 38619 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38620 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38623 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38624 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38625 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38631 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38632 | GIR_RootConstrainSelectedInstOperands, |
| 38633 | // GIR_Coverage, 3094, |
| 38634 | GIR_EraseRootFromParent_Done, |
| 38635 | // Label 2107: @124723 |
| 38636 | GIM_Try, /*On fail goto*//*Label 2108*/ GIMT_Encode4(124780), // Rule ID 3095 // |
| 38637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38640 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38641 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38643 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38650 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38651 | GIR_RootConstrainSelectedInstOperands, |
| 38652 | // GIR_Coverage, 3095, |
| 38653 | GIR_EraseRootFromParent_Done, |
| 38654 | // Label 2108: @124780 |
| 38655 | GIM_Try, /*On fail goto*//*Label 2109*/ GIMT_Encode4(124834), // Rule ID 3109 // |
| 38656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38657 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38659 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38660 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38662 | // (ld:{ *:[v32bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38669 | GIR_RootConstrainSelectedInstOperands, |
| 38670 | // GIR_Coverage, 3109, |
| 38671 | GIR_EraseRootFromParent_Done, |
| 38672 | // Label 2109: @124834 |
| 38673 | GIM_Try, /*On fail goto*//*Label 2110*/ GIMT_Encode4(124888), // Rule ID 3110 // |
| 38674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX7Only), |
| 38675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38678 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38680 | // (ld:{ *:[v32bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38686 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38687 | GIR_RootConstrainSelectedInstOperands, |
| 38688 | // GIR_Coverage, 3110, |
| 38689 | GIR_EraseRootFromParent_Done, |
| 38690 | // Label 2110: @124888 |
| 38691 | GIM_Try, /*On fail goto*//*Label 2111*/ GIMT_Encode4(124942), // Rule ID 3111 // |
| 38692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38693 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38696 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38698 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38704 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38705 | GIR_RootConstrainSelectedInstOperands, |
| 38706 | // GIR_Coverage, 3111, |
| 38707 | GIR_EraseRootFromParent_Done, |
| 38708 | // Label 2111: @124942 |
| 38709 | GIM_Try, /*On fail goto*//*Label 2112*/ GIMT_Encode4(124999), // Rule ID 3112 // |
| 38710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38711 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38714 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 38715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38716 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38724 | GIR_RootConstrainSelectedInstOperands, |
| 38725 | // GIR_Coverage, 3112, |
| 38726 | GIR_EraseRootFromParent_Done, |
| 38727 | // Label 2112: @124999 |
| 38728 | GIM_Try, /*On fail goto*//*Label 2113*/ GIMT_Encode4(125049), // Rule ID 3081 // |
| 38729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38730 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38734 | // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38741 | GIR_RootConstrainSelectedInstOperands, |
| 38742 | // GIR_Coverage, 3081, |
| 38743 | GIR_EraseRootFromParent_Done, |
| 38744 | // Label 2113: @125049 |
| 38745 | GIM_Try, /*On fail goto*//*Label 2114*/ GIMT_Encode4(125099), // Rule ID 3082 // |
| 38746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38749 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38750 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38751 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 38753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38758 | GIR_RootConstrainSelectedInstOperands, |
| 38759 | // GIR_Coverage, 3082, |
| 38760 | GIR_EraseRootFromParent_Done, |
| 38761 | // Label 2114: @125099 |
| 38762 | GIM_Try, /*On fail goto*//*Label 2115*/ GIMT_Encode4(125152), // Rule ID 3083 // |
| 38763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38764 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38766 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38767 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38768 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38776 | GIR_RootConstrainSelectedInstOperands, |
| 38777 | // GIR_Coverage, 3083, |
| 38778 | GIR_EraseRootFromParent_Done, |
| 38779 | // Label 2115: @125152 |
| 38780 | GIM_Try, /*On fail goto*//*Label 2116*/ GIMT_Encode4(125202), // Rule ID 3098 // |
| 38781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38782 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38784 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38785 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38786 | // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38792 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38793 | GIR_RootConstrainSelectedInstOperands, |
| 38794 | // GIR_Coverage, 3098, |
| 38795 | GIR_EraseRootFromParent_Done, |
| 38796 | // Label 2116: @125202 |
| 38797 | GIM_Try, /*On fail goto*//*Label 2117*/ GIMT_Encode4(125252), // Rule ID 3099 // |
| 38798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38799 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38801 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38803 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 38805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38809 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38810 | GIR_RootConstrainSelectedInstOperands, |
| 38811 | // GIR_Coverage, 3099, |
| 38812 | GIR_EraseRootFromParent_Done, |
| 38813 | // Label 2117: @125252 |
| 38814 | GIM_Try, /*On fail goto*//*Label 2118*/ GIMT_Encode4(125305), // Rule ID 3100 // |
| 38815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38816 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38818 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38819 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38820 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38827 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38828 | GIR_RootConstrainSelectedInstOperands, |
| 38829 | // GIR_Coverage, 3100, |
| 38830 | GIR_EraseRootFromParent_Done, |
| 38831 | // Label 2118: @125305 |
| 38832 | GIM_Try, /*On fail goto*//*Label 2119*/ GIMT_Encode4(125355), // Rule ID 3115 // |
| 38833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 38834 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38836 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38838 | // (ld:{ *:[v32bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 38840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38845 | GIR_RootConstrainSelectedInstOperands, |
| 38846 | // GIR_Coverage, 3115, |
| 38847 | GIR_EraseRootFromParent_Done, |
| 38848 | // Label 2119: @125355 |
| 38849 | GIM_Try, /*On fail goto*//*Label 2120*/ GIMT_Encode4(125405), // Rule ID 3116 // |
| 38850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isNotGFX9Plus), |
| 38851 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38855 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_ec:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_ec), |
| 38857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38861 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38862 | GIR_RootConstrainSelectedInstOperands, |
| 38863 | // GIR_Coverage, 3116, |
| 38864 | GIR_EraseRootFromParent_Done, |
| 38865 | // Label 2120: @125405 |
| 38866 | GIM_Try, /*On fail goto*//*Label 2121*/ GIMT_Encode4(125458), // Rule ID 3117 // |
| 38867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled_isGFX9Plus), |
| 38868 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38869 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38871 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38872 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM_ec:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM_ec), |
| 38874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38880 | GIR_RootConstrainSelectedInstOperands, |
| 38881 | // GIR_Coverage, 3117, |
| 38882 | GIR_EraseRootFromParent_Done, |
| 38883 | // Label 2121: @125458 |
| 38884 | GIM_Try, /*On fail goto*//*Label 2122*/ GIMT_Encode4(125505), // Rule ID 3086 // |
| 38885 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38888 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38889 | // (ld:{ *:[v32i16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38895 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38896 | GIR_RootConstrainSelectedInstOperands, |
| 38897 | // GIR_Coverage, 3086, |
| 38898 | GIR_EraseRootFromParent_Done, |
| 38899 | // Label 2122: @125505 |
| 38900 | GIM_Try, /*On fail goto*//*Label 2123*/ GIMT_Encode4(125555), // Rule ID 3087 // |
| 38901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 38902 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38906 | // (ld:{ *:[v32i16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38912 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38913 | GIR_RootConstrainSelectedInstOperands, |
| 38914 | // GIR_Coverage, 3087, |
| 38915 | GIR_EraseRootFromParent_Done, |
| 38916 | // Label 2123: @125555 |
| 38917 | GIM_Try, /*On fail goto*//*Label 2124*/ GIMT_Encode4(125605), // Rule ID 3088 // |
| 38918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 38919 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38923 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38930 | GIR_RootConstrainSelectedInstOperands, |
| 38931 | // GIR_Coverage, 3088, |
| 38932 | GIR_EraseRootFromParent_Done, |
| 38933 | // Label 2124: @125605 |
| 38934 | GIM_Try, /*On fail goto*//*Label 2125*/ GIMT_Encode4(125658), // Rule ID 3089 // |
| 38935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 38936 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38940 | // (ld:{ *:[v32i16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32i16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 38941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 38942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38948 | GIR_RootConstrainSelectedInstOperands, |
| 38949 | // GIR_Coverage, 3089, |
| 38950 | GIR_EraseRootFromParent_Done, |
| 38951 | // Label 2125: @125658 |
| 38952 | GIM_Try, /*On fail goto*//*Label 2126*/ GIMT_Encode4(125705), // Rule ID 3103 // |
| 38953 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 38957 | // (ld:{ *:[v32f16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 38959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38964 | GIR_RootConstrainSelectedInstOperands, |
| 38965 | // GIR_Coverage, 3103, |
| 38966 | GIR_EraseRootFromParent_Done, |
| 38967 | // Label 2126: @125705 |
| 38968 | GIM_Try, /*On fail goto*//*Label 2127*/ GIMT_Encode4(125755), // Rule ID 3104 // |
| 38969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 38970 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38972 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 38974 | // (ld:{ *:[v32f16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 38975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 38976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 38979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38981 | GIR_RootConstrainSelectedInstOperands, |
| 38982 | // GIR_Coverage, 3104, |
| 38983 | GIR_EraseRootFromParent_Done, |
| 38984 | // Label 2127: @125755 |
| 38985 | GIM_Try, /*On fail goto*//*Label 2128*/ GIMT_Encode4(125805), // Rule ID 3105 // |
| 38986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 38987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 38988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 38989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 38990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 38991 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 38992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 38993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 38994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 38995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 38996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 38997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 38998 | GIR_RootConstrainSelectedInstOperands, |
| 38999 | // GIR_Coverage, 3105, |
| 39000 | GIR_EraseRootFromParent_Done, |
| 39001 | // Label 2128: @125805 |
| 39002 | GIM_Try, /*On fail goto*//*Label 2129*/ GIMT_Encode4(125858), // Rule ID 3106 // |
| 39003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 39004 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39006 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 39008 | // (ld:{ *:[v32f16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32f16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 39010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39016 | GIR_RootConstrainSelectedInstOperands, |
| 39017 | // GIR_Coverage, 3106, |
| 39018 | GIR_EraseRootFromParent_Done, |
| 39019 | // Label 2129: @125858 |
| 39020 | GIM_Try, /*On fail goto*//*Label 2130*/ GIMT_Encode4(125905), // Rule ID 3120 // |
| 39021 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39023 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39024 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 39025 | // (ld:{ *:[v32bf16] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39032 | GIR_RootConstrainSelectedInstOperands, |
| 39033 | // GIR_Coverage, 3120, |
| 39034 | GIR_EraseRootFromParent_Done, |
| 39035 | // Label 2130: @125905 |
| 39036 | GIM_Try, /*On fail goto*//*Label 2131*/ GIMT_Encode4(125955), // Rule ID 3121 // |
| 39037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 39038 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39040 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm32), |
| 39042 | // (ld:{ *:[v32bf16] } (SMRDImm32:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ci:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ci), |
| 39044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39048 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39049 | GIR_RootConstrainSelectedInstOperands, |
| 39050 | // GIR_Coverage, 3121, |
| 39051 | GIR_EraseRootFromParent_Done, |
| 39052 | // Label 2131: @125955 |
| 39053 | GIM_Try, /*On fail goto*//*Label 2132*/ GIMT_Encode4(126005), // Rule ID 3122 // |
| 39054 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 39055 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39057 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39058 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 39059 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }) |
| 39060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR), |
| 39061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39066 | GIR_RootConstrainSelectedInstOperands, |
| 39067 | // GIR_Coverage, 3122, |
| 39068 | GIR_EraseRootFromParent_Done, |
| 39069 | // Label 2132: @126005 |
| 39070 | GIM_Try, /*On fail goto*//*Label 2133*/ GIMT_Encode4(126058), // Rule ID 3123 // |
| 39071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 39072 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39074 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39075 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 39076 | // (ld:{ *:[v32bf16] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_SGPR_IMM:{ *:[v32bf16] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_SGPR_IMM), |
| 39078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39084 | GIR_RootConstrainSelectedInstOperands, |
| 39085 | // GIR_Coverage, 3123, |
| 39086 | GIR_EraseRootFromParent_Done, |
| 39087 | // Label 2133: @126058 |
| 39088 | GIM_Try, /*On fail goto*//*Label 2134*/ GIMT_Encode4(126104), // Rule ID 3080 // |
| 39089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39090 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39092 | // MIs[0] sbase |
| 39093 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39094 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39095 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 39096 | // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39099 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39102 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39103 | GIR_RootConstrainSelectedInstOperands, |
| 39104 | // GIR_Coverage, 3080, |
| 39105 | GIR_EraseRootFromParent_Done, |
| 39106 | // Label 2134: @126104 |
| 39107 | GIM_Try, /*On fail goto*//*Label 2135*/ GIMT_Encode4(126150), // Rule ID 3097 // |
| 39108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39109 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39111 | // MIs[0] sbase |
| 39112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39113 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39114 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 39115 | // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39118 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39121 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39122 | GIR_RootConstrainSelectedInstOperands, |
| 39123 | // GIR_Coverage, 3097, |
| 39124 | GIR_EraseRootFromParent_Done, |
| 39125 | // Label 2135: @126150 |
| 39126 | GIM_Try, /*On fail goto*//*Label 2136*/ GIMT_Encode4(126196), // Rule ID 3114 // |
| 39127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39128 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39130 | // MIs[0] sbase |
| 39131 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39132 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39133 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_aligned_smrd_load), |
| 39134 | // (ld:{ *:[v32bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>><<P:Predicate_aligned_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39137 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39140 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39141 | GIR_RootConstrainSelectedInstOperands, |
| 39142 | // GIR_Coverage, 3114, |
| 39143 | GIR_EraseRootFromParent_Done, |
| 39144 | // Label 2136: @126196 |
| 39145 | GIM_Try, /*On fail goto*//*Label 2137*/ GIMT_Encode4(126238), // Rule ID 3085 // |
| 39146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39147 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39149 | // MIs[0] sbase |
| 39150 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39151 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39152 | // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 39154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39155 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39159 | GIR_RootConstrainSelectedInstOperands, |
| 39160 | // GIR_Coverage, 3085, |
| 39161 | GIR_EraseRootFromParent_Done, |
| 39162 | // Label 2137: @126238 |
| 39163 | GIM_Try, /*On fail goto*//*Label 2138*/ GIMT_Encode4(126280), // Rule ID 3102 // |
| 39164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39165 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39167 | // MIs[0] sbase |
| 39168 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39169 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39170 | // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 39172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39173 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39177 | GIR_RootConstrainSelectedInstOperands, |
| 39178 | // GIR_Coverage, 3102, |
| 39179 | GIR_EraseRootFromParent_Done, |
| 39180 | // Label 2138: @126280 |
| 39181 | GIM_Try, /*On fail goto*//*Label 2139*/ GIMT_Encode4(126322), // Rule ID 3119 // |
| 39182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasXNACKEnabled), |
| 39183 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39185 | // MIs[0] sbase |
| 39186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39187 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39188 | // (ld:{ *:[v32bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM_ec:{ *:[v32bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM_ec), |
| 39190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39191 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39195 | GIR_RootConstrainSelectedInstOperands, |
| 39196 | // GIR_Coverage, 3119, |
| 39197 | GIR_EraseRootFromParent_Done, |
| 39198 | // Label 2139: @126322 |
| 39199 | GIM_Try, /*On fail goto*//*Label 2140*/ GIMT_Encode4(126361), // Rule ID 3091 // |
| 39200 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39202 | // MIs[0] sbase |
| 39203 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39204 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39205 | // (ld:{ *:[v32i16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32i16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39208 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39211 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39212 | GIR_RootConstrainSelectedInstOperands, |
| 39213 | // GIR_Coverage, 3091, |
| 39214 | GIR_EraseRootFromParent_Done, |
| 39215 | // Label 2140: @126361 |
| 39216 | GIM_Try, /*On fail goto*//*Label 2141*/ GIMT_Encode4(126400), // Rule ID 3108 // |
| 39217 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39219 | // MIs[0] sbase |
| 39220 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39221 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39222 | // (ld:{ *:[v32f16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32f16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39225 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39229 | GIR_RootConstrainSelectedInstOperands, |
| 39230 | // GIR_Coverage, 3108, |
| 39231 | GIR_EraseRootFromParent_Done, |
| 39232 | // Label 2141: @126400 |
| 39233 | GIM_Try, /*On fail goto*//*Label 2142*/ GIMT_Encode4(126439), // Rule ID 3125 // |
| 39234 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 39236 | // MIs[0] sbase |
| 39237 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39238 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39239 | // (ld:{ *:[v32bf16] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_load>><<P:Predicate_smrd_load>> => (S_LOAD_DWORDX16_IMM:{ *:[v32bf16] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_DWORDX16_IMM), |
| 39241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39242 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39245 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39246 | GIR_RootConstrainSelectedInstOperands, |
| 39247 | // GIR_Coverage, 3125, |
| 39248 | GIR_EraseRootFromParent_Done, |
| 39249 | // Label 2142: @126439 |
| 39250 | GIM_Reject, |
| 39251 | // Label 2091: @126440 |
| 39252 | GIM_Reject, |
| 39253 | // Label 871: @126441 |
| 39254 | GIM_Reject, |
| 39255 | // Label 14: @126442 |
| 39256 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 2145*/ GIMT_Encode4(130407), |
| 39257 | /*GILLT_s16*//*Label 2143*/ GIMT_Encode4(126461), |
| 39258 | /*GILLT_s32*//*Label 2144*/ GIMT_Encode4(127452), |
| 39259 | // Label 2143: @126461 |
| 39260 | GIM_Try, /*On fail goto*//*Label 2146*/ GIMT_Encode4(127451), |
| 39261 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39262 | GIM_Try, /*On fail goto*//*Label 2147*/ GIMT_Encode4(126536), // Rule ID 6142 // |
| 39263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 39264 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39266 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39269 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 39271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39278 | GIR_RootConstrainSelectedInstOperands, |
| 39279 | // GIR_Coverage, 6142, |
| 39280 | GIR_EraseRootFromParent_Done, |
| 39281 | // Label 2147: @126536 |
| 39282 | GIM_Try, /*On fail goto*//*Label 2148*/ GIMT_Encode4(126599), // Rule ID 6144 // |
| 39283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 39284 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39285 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39289 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 39291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39298 | GIR_RootConstrainSelectedInstOperands, |
| 39299 | // GIR_Coverage, 6144, |
| 39300 | GIR_EraseRootFromParent_Done, |
| 39301 | // Label 2148: @126599 |
| 39302 | GIM_Try, /*On fail goto*//*Label 2149*/ GIMT_Encode4(126659), // Rule ID 3864 // |
| 39303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 39304 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39305 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39307 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39308 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 39309 | // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS), |
| 39311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 39314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39316 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39317 | GIR_RootConstrainSelectedInstOperands, |
| 39318 | // GIR_Coverage, 3864, |
| 39319 | GIR_EraseRootFromParent_Done, |
| 39320 | // Label 2149: @126659 |
| 39321 | GIM_Try, /*On fail goto*//*Label 2150*/ GIMT_Encode4(126714), // Rule ID 3863 // |
| 39322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39323 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39324 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39326 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 39328 | // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 39329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR), |
| 39330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 39332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39335 | GIR_RootConstrainSelectedInstOperands, |
| 39336 | // GIR_Coverage, 3863, |
| 39337 | GIR_EraseRootFromParent_Done, |
| 39338 | // Label 2150: @126714 |
| 39339 | GIM_Try, /*On fail goto*//*Label 2151*/ GIMT_Encode4(126769), // Rule ID 3862 // |
| 39340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39341 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 39346 | // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 39347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE), |
| 39348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39352 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39353 | GIR_RootConstrainSelectedInstOperands, |
| 39354 | // GIR_Coverage, 3862, |
| 39355 | GIR_EraseRootFromParent_Done, |
| 39356 | // Label 2151: @126769 |
| 39357 | GIM_Try, /*On fail goto*//*Label 2152*/ GIMT_Encode4(126837), // Rule ID 6141 // |
| 39358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 39359 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39362 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 39364 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), |
| 39366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 39368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 39370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 39371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39374 | GIR_RootConstrainSelectedInstOperands, |
| 39375 | // GIR_Coverage, 6141, |
| 39376 | GIR_EraseRootFromParent_Done, |
| 39377 | // Label 2152: @126837 |
| 39378 | GIM_Try, /*On fail goto*//*Label 2153*/ GIMT_Encode4(126905), // Rule ID 6143 // |
| 39379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 39380 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39381 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 39385 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN), |
| 39387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 39389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 39391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 39392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39395 | GIR_RootConstrainSelectedInstOperands, |
| 39396 | // GIR_Coverage, 6143, |
| 39397 | GIR_EraseRootFromParent_Done, |
| 39398 | // Label 2153: @126905 |
| 39399 | GIM_Try, /*On fail goto*//*Label 2154*/ GIMT_Encode4(126969), // Rule ID 6113 // |
| 39400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 39401 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39402 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39404 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39405 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 39406 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 39407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 39408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39415 | GIR_RootConstrainSelectedInstOperands, |
| 39416 | // GIR_Coverage, 6113, |
| 39417 | GIR_EraseRootFromParent_Done, |
| 39418 | // Label 2154: @126969 |
| 39419 | GIM_Try, /*On fail goto*//*Label 2155*/ GIMT_Encode4(127033), // Rule ID 6114 // |
| 39420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 39421 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39422 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39423 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39424 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 39426 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 39427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 39428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39435 | GIR_RootConstrainSelectedInstOperands, |
| 39436 | // GIR_Coverage, 6114, |
| 39437 | GIR_EraseRootFromParent_Done, |
| 39438 | // Label 2155: @127033 |
| 39439 | GIM_Try, /*On fail goto*//*Label 2156*/ GIMT_Encode4(127098), // Rule ID 6119 // |
| 39440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 39441 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39442 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 39446 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 39447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 39448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39454 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39455 | GIR_RootConstrainSelectedInstOperands, |
| 39456 | // GIR_Coverage, 6119, |
| 39457 | GIR_EraseRootFromParent_Done, |
| 39458 | // Label 2156: @127098 |
| 39459 | GIM_Try, /*On fail goto*//*Label 2157*/ GIMT_Encode4(127163), // Rule ID 6120 // |
| 39460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 39461 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39464 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 39466 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 39467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 39468 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39474 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39475 | GIR_RootConstrainSelectedInstOperands, |
| 39476 | // GIR_Coverage, 6120, |
| 39477 | GIR_EraseRootFromParent_Done, |
| 39478 | // Label 2157: @127163 |
| 39479 | GIM_Try, /*On fail goto*//*Label 2158*/ GIMT_Encode4(127218), // Rule ID 7437 // |
| 39480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 39481 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 39482 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39484 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 39486 | // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>> => (DS_READ_I8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 39487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8), |
| 39488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 39490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39493 | GIR_RootConstrainSelectedInstOperands, |
| 39494 | // GIR_Coverage, 7437, |
| 39495 | GIR_EraseRootFromParent_Done, |
| 39496 | // Label 2158: @127218 |
| 39497 | GIM_Try, /*On fail goto*//*Label 2159*/ GIMT_Encode4(127273), // Rule ID 7438 // |
| 39498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 39499 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 39500 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 39504 | // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>> => (DS_READ_I8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 39505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9), |
| 39506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 39508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39510 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39511 | GIR_RootConstrainSelectedInstOperands, |
| 39512 | // GIR_Coverage, 7438, |
| 39513 | GIR_EraseRootFromParent_Done, |
| 39514 | // Label 2159: @127273 |
| 39515 | GIM_Try, /*On fail goto*//*Label 2160*/ GIMT_Encode4(127335), // Rule ID 3441 // |
| 39516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 39517 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39518 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 39522 | // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR), |
| 39524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 39526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 39527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39530 | GIR_RootConstrainSelectedInstOperands, |
| 39531 | // GIR_Coverage, 3441, |
| 39532 | GIR_EraseRootFromParent_Done, |
| 39533 | // Label 2160: @127335 |
| 39534 | GIM_Try, /*On fail goto*//*Label 2161*/ GIMT_Encode4(127392), // Rule ID 3440 // |
| 39535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 39536 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39537 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39539 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 39541 | // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (GLOBAL_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 39542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE), |
| 39543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39547 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39548 | GIR_RootConstrainSelectedInstOperands, |
| 39549 | // GIR_Coverage, 3440, |
| 39550 | GIR_EraseRootFromParent_Done, |
| 39551 | // Label 2161: @127392 |
| 39552 | GIM_Try, /*On fail goto*//*Label 2162*/ GIMT_Encode4(127450), // Rule ID 3219 // |
| 39553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 39554 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39555 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39557 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39558 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 39559 | // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>> => (FLAT_LOAD_SBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 39560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE), |
| 39561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39565 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39566 | GIR_RootConstrainSelectedInstOperands, |
| 39567 | // GIR_Coverage, 3219, |
| 39568 | GIR_EraseRootFromParent_Done, |
| 39569 | // Label 2162: @127450 |
| 39570 | GIM_Reject, |
| 39571 | // Label 2146: @127451 |
| 39572 | GIM_Reject, |
| 39573 | // Label 2144: @127452 |
| 39574 | GIM_Try, /*On fail goto*//*Label 2163*/ GIMT_Encode4(127518), // Rule ID 2483 // |
| 39575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39576 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39577 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39579 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39580 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8), |
| 39581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 39582 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>> => (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM), |
| 39584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39590 | GIR_RootConstrainSelectedInstOperands, |
| 39591 | // GIR_Coverage, 2483, |
| 39592 | GIR_EraseRootFromParent_Done, |
| 39593 | // Label 2163: @127518 |
| 39594 | GIM_Try, /*On fail goto*//*Label 2164*/ GIMT_Encode4(127584), // Rule ID 2495 // |
| 39595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39596 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39600 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16), |
| 39601 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 39602 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>> => (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM), |
| 39604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39609 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39610 | GIR_RootConstrainSelectedInstOperands, |
| 39611 | // GIR_Coverage, 2495, |
| 39612 | GIR_EraseRootFromParent_Done, |
| 39613 | // Label 2164: @127584 |
| 39614 | GIM_Try, /*On fail goto*//*Label 2165*/ GIMT_Encode4(127645), // Rule ID 2481 // |
| 39615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39616 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39619 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39620 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8), |
| 39621 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 39622 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>> => (S_LOAD_I8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM), |
| 39624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39629 | GIR_RootConstrainSelectedInstOperands, |
| 39630 | // GIR_Coverage, 2481, |
| 39631 | GIR_EraseRootFromParent_Done, |
| 39632 | // Label 2165: @127645 |
| 39633 | GIM_Try, /*On fail goto*//*Label 2166*/ GIMT_Encode4(127709), // Rule ID 2482 // |
| 39634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39635 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39636 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39638 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39639 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8), |
| 39640 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 39641 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>> => (S_LOAD_I8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_SGPR_IMM), |
| 39643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39648 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39649 | GIR_RootConstrainSelectedInstOperands, |
| 39650 | // GIR_Coverage, 2482, |
| 39651 | GIR_EraseRootFromParent_Done, |
| 39652 | // Label 2166: @127709 |
| 39653 | GIM_Try, /*On fail goto*//*Label 2167*/ GIMT_Encode4(127770), // Rule ID 2493 // |
| 39654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39655 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39656 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39659 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16), |
| 39660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 39661 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>> => (S_LOAD_I16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM), |
| 39663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39667 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39668 | GIR_RootConstrainSelectedInstOperands, |
| 39669 | // GIR_Coverage, 2493, |
| 39670 | GIR_EraseRootFromParent_Done, |
| 39671 | // Label 2167: @127770 |
| 39672 | GIM_Try, /*On fail goto*//*Label 2168*/ GIMT_Encode4(127834), // Rule ID 2494 // |
| 39673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39674 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39675 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39678 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16), |
| 39679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 39680 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>> => (S_LOAD_I16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_SGPR_IMM), |
| 39682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 39684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39688 | GIR_RootConstrainSelectedInstOperands, |
| 39689 | // GIR_Coverage, 2494, |
| 39690 | GIR_EraseRootFromParent_Done, |
| 39691 | // Label 2168: @127834 |
| 39692 | GIM_Try, /*On fail goto*//*Label 2169*/ GIMT_Encode4(127887), // Rule ID 2484 // |
| 39693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39694 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39696 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39697 | // MIs[0] sbase |
| 39698 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39699 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi8), |
| 39701 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_smrd_sextloadi8>> => (S_LOAD_I8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I8_IMM), |
| 39703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39704 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39707 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39708 | GIR_RootConstrainSelectedInstOperands, |
| 39709 | // GIR_Coverage, 2484, |
| 39710 | GIR_EraseRootFromParent_Done, |
| 39711 | // Label 2169: @127887 |
| 39712 | GIM_Try, /*On fail goto*//*Label 2170*/ GIMT_Encode4(127940), // Rule ID 2496 // |
| 39713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 39714 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 39717 | // MIs[0] sbase |
| 39718 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 39719 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 39720 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_sextloadi16), |
| 39721 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_smrd_sextloadi16>> => (S_LOAD_I16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 39722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_I16_IMM), |
| 39723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 39724 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 39725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39727 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39728 | GIR_RootConstrainSelectedInstOperands, |
| 39729 | // GIR_Coverage, 2496, |
| 39730 | GIR_EraseRootFromParent_Done, |
| 39731 | // Label 2170: @127940 |
| 39732 | GIM_Try, /*On fail goto*//*Label 2171*/ GIMT_Encode4(128010), // Rule ID 6128 // |
| 39733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 39734 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39735 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39736 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39738 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39739 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39740 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 39742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39749 | GIR_RootConstrainSelectedInstOperands, |
| 39750 | // GIR_Coverage, 6128, |
| 39751 | GIR_EraseRootFromParent_Done, |
| 39752 | // Label 2171: @128010 |
| 39753 | GIM_Try, /*On fail goto*//*Label 2172*/ GIMT_Encode4(128080), // Rule ID 6132 // |
| 39754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 39755 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39756 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39757 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39759 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39761 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 39763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39768 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39769 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39770 | GIR_RootConstrainSelectedInstOperands, |
| 39771 | // GIR_Coverage, 6132, |
| 39772 | GIR_EraseRootFromParent_Done, |
| 39773 | // Label 2172: @128080 |
| 39774 | GIM_Try, /*On fail goto*//*Label 2173*/ GIMT_Encode4(128150), // Rule ID 6154 // |
| 39775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 39776 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39777 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39778 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39780 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39781 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39782 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), |
| 39784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39790 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39791 | GIR_RootConstrainSelectedInstOperands, |
| 39792 | // GIR_Coverage, 6154, |
| 39793 | GIR_EraseRootFromParent_Done, |
| 39794 | // Label 2173: @128150 |
| 39795 | GIM_Try, /*On fail goto*//*Label 2174*/ GIMT_Encode4(128220), // Rule ID 6156 // |
| 39796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 39797 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39798 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39799 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39801 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 39803 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 39804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET), |
| 39805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 39808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39811 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39812 | GIR_RootConstrainSelectedInstOperands, |
| 39813 | // GIR_Coverage, 6156, |
| 39814 | GIR_EraseRootFromParent_Done, |
| 39815 | // Label 2174: @128220 |
| 39816 | GIM_Try, /*On fail goto*//*Label 2175*/ GIMT_Encode4(128287), // Rule ID 3855 // |
| 39817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 39818 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39819 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39820 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39822 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 39824 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SVS), |
| 39826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 39829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39832 | GIR_RootConstrainSelectedInstOperands, |
| 39833 | // GIR_Coverage, 3855, |
| 39834 | GIR_EraseRootFromParent_Done, |
| 39835 | // Label 2175: @128287 |
| 39836 | GIM_Try, /*On fail goto*//*Label 2176*/ GIMT_Encode4(128354), // Rule ID 3873 // |
| 39837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 39838 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39839 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39840 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39841 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39842 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 39844 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (SCRATCH_LOAD_SSHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 39845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SVS), |
| 39846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 39849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 39850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39852 | GIR_RootConstrainSelectedInstOperands, |
| 39853 | // GIR_Coverage, 3873, |
| 39854 | GIR_EraseRootFromParent_Done, |
| 39855 | // Label 2176: @128354 |
| 39856 | GIM_Try, /*On fail goto*//*Label 2177*/ GIMT_Encode4(128416), // Rule ID 3854 // |
| 39857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39858 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39859 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39860 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39862 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39863 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 39864 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 39865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE_SADDR), |
| 39866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 39868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39870 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39871 | GIR_RootConstrainSelectedInstOperands, |
| 39872 | // GIR_Coverage, 3854, |
| 39873 | GIR_EraseRootFromParent_Done, |
| 39874 | // Label 2177: @128416 |
| 39875 | GIM_Try, /*On fail goto*//*Label 2178*/ GIMT_Encode4(128478), // Rule ID 3872 // |
| 39876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39877 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39878 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39879 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 39883 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (SCRATCH_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 39884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT_SADDR), |
| 39885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 39887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39889 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39890 | GIR_RootConstrainSelectedInstOperands, |
| 39891 | // GIR_Coverage, 3872, |
| 39892 | GIR_EraseRootFromParent_Done, |
| 39893 | // Label 2178: @128478 |
| 39894 | GIM_Try, /*On fail goto*//*Label 2179*/ GIMT_Encode4(128540), // Rule ID 3853 // |
| 39895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39896 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39897 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39898 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39900 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39901 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 39902 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (SCRATCH_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 39903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SBYTE), |
| 39904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39908 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39909 | GIR_RootConstrainSelectedInstOperands, |
| 39910 | // GIR_Coverage, 3853, |
| 39911 | GIR_EraseRootFromParent_Done, |
| 39912 | // Label 2179: @128540 |
| 39913 | GIM_Try, /*On fail goto*//*Label 2180*/ GIMT_Encode4(128602), // Rule ID 3871 // |
| 39914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 39915 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39916 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 39917 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39919 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 39921 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (SCRATCH_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 39922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_SSHORT), |
| 39923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 39924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 39925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 39926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39927 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39928 | GIR_RootConstrainSelectedInstOperands, |
| 39929 | // GIR_Coverage, 3871, |
| 39930 | GIR_EraseRootFromParent_Done, |
| 39931 | // Label 2180: @128602 |
| 39932 | GIM_Try, /*On fail goto*//*Label 2181*/ GIMT_Encode4(128679), // Rule ID 4114 // |
| 39933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 39934 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39935 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39936 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 39940 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 39941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), |
| 39942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 39944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 39946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 39947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39950 | GIR_RootConstrainSelectedInstOperands, |
| 39951 | // GIR_Coverage, 4114, |
| 39952 | GIR_EraseRootFromParent_Done, |
| 39953 | // Label 2181: @128679 |
| 39954 | GIM_Try, /*On fail goto*//*Label 2182*/ GIMT_Encode4(128753), // Rule ID 4116 // |
| 39955 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 39956 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39957 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39959 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 39961 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 39962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_ADDR64), |
| 39963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 39965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 39967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 39968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39971 | GIR_RootConstrainSelectedInstOperands, |
| 39972 | // GIR_Coverage, 4116, |
| 39973 | GIR_EraseRootFromParent_Done, |
| 39974 | // Label 2182: @128753 |
| 39975 | GIM_Try, /*On fail goto*//*Label 2183*/ GIMT_Encode4(128830), // Rule ID 4126 // |
| 39976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 39977 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39978 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 39979 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 39980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 39981 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 39982 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 39983 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 39984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), |
| 39985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 39986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 39987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 39988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 39989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 39990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 39992 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 39993 | GIR_RootConstrainSelectedInstOperands, |
| 39994 | // GIR_Coverage, 4126, |
| 39995 | GIR_EraseRootFromParent_Done, |
| 39996 | // Label 2183: @128830 |
| 39997 | GIM_Try, /*On fail goto*//*Label 2184*/ GIMT_Encode4(128904), // Rule ID 4128 // |
| 39998 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 39999 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40000 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40003 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 40004 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (BUFFER_LOAD_SSHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 40005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_ADDR64), |
| 40006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40013 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40014 | GIR_RootConstrainSelectedInstOperands, |
| 40015 | // GIR_Coverage, 4128, |
| 40016 | GIR_EraseRootFromParent_Done, |
| 40017 | // Label 2184: @128904 |
| 40018 | GIM_Try, /*On fail goto*//*Label 2185*/ GIMT_Encode4(128980), // Rule ID 6105 // |
| 40019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 40020 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40021 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40022 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40024 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 40026 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_constant>> => (BUFFER_LOAD_SBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_ADDR64), |
| 40028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40036 | GIR_RootConstrainSelectedInstOperands, |
| 40037 | // GIR_Coverage, 6105, |
| 40038 | GIR_EraseRootFromParent_Done, |
| 40039 | // Label 2185: @128980 |
| 40040 | GIM_Try, /*On fail goto*//*Label 2186*/ GIMT_Encode4(129056), // Rule ID 6108 // |
| 40041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 40042 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40043 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40044 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 40048 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_constant>> => (BUFFER_LOAD_SSHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_ADDR64), |
| 40050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40058 | GIR_RootConstrainSelectedInstOperands, |
| 40059 | // GIR_Coverage, 6108, |
| 40060 | GIR_EraseRootFromParent_Done, |
| 40061 | // Label 2186: @129056 |
| 40062 | GIM_Try, /*On fail goto*//*Label 2187*/ GIMT_Encode4(129131), // Rule ID 6127 // |
| 40063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40064 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40065 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40070 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), |
| 40072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40080 | GIR_RootConstrainSelectedInstOperands, |
| 40081 | // GIR_Coverage, 6127, |
| 40082 | GIR_EraseRootFromParent_Done, |
| 40083 | // Label 2187: @129131 |
| 40084 | GIM_Try, /*On fail goto*//*Label 2188*/ GIMT_Encode4(129206), // Rule ID 6131 // |
| 40085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 40086 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40087 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40088 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40092 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_private>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN), |
| 40094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40102 | GIR_RootConstrainSelectedInstOperands, |
| 40103 | // GIR_Coverage, 6131, |
| 40104 | GIR_EraseRootFromParent_Done, |
| 40105 | // Label 2188: @129206 |
| 40106 | GIM_Try, /*On fail goto*//*Label 2189*/ GIMT_Encode4(129281), // Rule ID 6153 // |
| 40107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40108 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40109 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40110 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40114 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN), |
| 40116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40123 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40124 | GIR_RootConstrainSelectedInstOperands, |
| 40125 | // GIR_Coverage, 6153, |
| 40126 | GIR_EraseRootFromParent_Done, |
| 40127 | // Label 2189: @129281 |
| 40128 | GIM_Try, /*On fail goto*//*Label 2190*/ GIMT_Encode4(129356), // Rule ID 6155 // |
| 40129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 40130 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40131 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40132 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40134 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40136 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_private>> => (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN), |
| 40138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40145 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40146 | GIR_RootConstrainSelectedInstOperands, |
| 40147 | // GIR_Coverage, 6155, |
| 40148 | GIR_EraseRootFromParent_Done, |
| 40149 | // Label 2190: @129356 |
| 40150 | GIM_Try, /*On fail goto*//*Label 2191*/ GIMT_Encode4(129428), // Rule ID 4113 // |
| 40151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 40152 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40153 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40154 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40156 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40158 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 40159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 40160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40166 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40167 | GIR_RootConstrainSelectedInstOperands, |
| 40168 | // GIR_Coverage, 4113, |
| 40169 | GIR_EraseRootFromParent_Done, |
| 40170 | // Label 2191: @129428 |
| 40171 | GIM_Try, /*On fail goto*//*Label 2192*/ GIMT_Encode4(129497), // Rule ID 4115 // |
| 40172 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40173 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40174 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40176 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40177 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40178 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 40179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 40180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40186 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40187 | GIR_RootConstrainSelectedInstOperands, |
| 40188 | // GIR_Coverage, 4115, |
| 40189 | GIR_EraseRootFromParent_Done, |
| 40190 | // Label 2192: @129497 |
| 40191 | GIM_Try, /*On fail goto*//*Label 2193*/ GIMT_Encode4(129569), // Rule ID 4125 // |
| 40192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 40193 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40194 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40195 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40199 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 40200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), |
| 40201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40207 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40208 | GIR_RootConstrainSelectedInstOperands, |
| 40209 | // GIR_Coverage, 4125, |
| 40210 | GIR_EraseRootFromParent_Done, |
| 40211 | // Label 2193: @129569 |
| 40212 | GIM_Try, /*On fail goto*//*Label 2194*/ GIMT_Encode4(129638), // Rule ID 4127 // |
| 40213 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40214 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40215 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40219 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 40220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET), |
| 40221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40228 | GIR_RootConstrainSelectedInstOperands, |
| 40229 | // GIR_Coverage, 4127, |
| 40230 | GIR_EraseRootFromParent_Done, |
| 40231 | // Label 2194: @129638 |
| 40232 | GIM_Try, /*On fail goto*//*Label 2195*/ GIMT_Encode4(129700), // Rule ID 7435 // |
| 40233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 40234 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40235 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40236 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40239 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40240 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi8_glue>><<P:Predicate_sextloadi8_local_m0>> => (DS_READ_I8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8), |
| 40242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40246 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40247 | GIR_RootConstrainSelectedInstOperands, |
| 40248 | // GIR_Coverage, 7435, |
| 40249 | GIR_EraseRootFromParent_Done, |
| 40250 | // Label 2195: @129700 |
| 40251 | GIM_Try, /*On fail goto*//*Label 2196*/ GIMT_Encode4(129762), // Rule ID 7436 // |
| 40252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 40253 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40254 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40255 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40257 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40259 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_local>> => (DS_READ_I8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I8_gfx9), |
| 40261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40266 | GIR_RootConstrainSelectedInstOperands, |
| 40267 | // GIR_Coverage, 7436, |
| 40268 | GIR_EraseRootFromParent_Done, |
| 40269 | // Label 2196: @129762 |
| 40270 | GIM_Try, /*On fail goto*//*Label 2197*/ GIMT_Encode4(129824), // Rule ID 7447 // |
| 40271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 40272 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40273 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40274 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40276 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40278 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>> => (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16), |
| 40280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40284 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40285 | GIR_RootConstrainSelectedInstOperands, |
| 40286 | // GIR_Coverage, 7447, |
| 40287 | GIR_EraseRootFromParent_Done, |
| 40288 | // Label 2197: @129824 |
| 40289 | GIM_Try, /*On fail goto*//*Label 2198*/ GIMT_Encode4(129886), // Rule ID 7448 // |
| 40290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 40291 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40292 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40293 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40295 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40297 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>> => (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9), |
| 40299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40304 | GIR_RootConstrainSelectedInstOperands, |
| 40305 | // GIR_Coverage, 7448, |
| 40306 | GIR_EraseRootFromParent_Done, |
| 40307 | // Label 2198: @129886 |
| 40308 | GIM_Try, /*On fail goto*//*Label 2199*/ GIMT_Encode4(129948), // Rule ID 7449 // |
| 40309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 40310 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40311 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40312 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40314 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40316 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_sextload_glue>><<P:Predicate_sextloadi16_glue>><<P:Predicate_sextloadi16_local_m0>> => (DS_READ_I16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16), |
| 40318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40323 | GIR_RootConstrainSelectedInstOperands, |
| 40324 | // GIR_Coverage, 7449, |
| 40325 | GIR_EraseRootFromParent_Done, |
| 40326 | // Label 2199: @129948 |
| 40327 | GIM_Try, /*On fail goto*//*Label 2200*/ GIMT_Encode4(130010), // Rule ID 7450 // |
| 40328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 40329 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40330 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40331 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40335 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_local>> => (DS_READ_I16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_I16_gfx9), |
| 40337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40341 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40342 | GIR_RootConstrainSelectedInstOperands, |
| 40343 | // GIR_Coverage, 7450, |
| 40344 | GIR_EraseRootFromParent_Done, |
| 40345 | // Label 2200: @130010 |
| 40346 | GIM_Try, /*On fail goto*//*Label 2201*/ GIMT_Encode4(130079), // Rule ID 3435 // |
| 40347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40348 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40349 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40350 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40351 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40352 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 40354 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (GLOBAL_LOAD_SBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE_SADDR), |
| 40356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 40358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 40359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40362 | GIR_RootConstrainSelectedInstOperands, |
| 40363 | // GIR_Coverage, 3435, |
| 40364 | GIR_EraseRootFromParent_Done, |
| 40365 | // Label 2201: @130079 |
| 40366 | GIM_Try, /*On fail goto*//*Label 2202*/ GIMT_Encode4(130148), // Rule ID 3447 // |
| 40367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40368 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40369 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40371 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40372 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 40374 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (GLOBAL_LOAD_SSHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT_SADDR), |
| 40376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 40378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 40379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40381 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40382 | GIR_RootConstrainSelectedInstOperands, |
| 40383 | // GIR_Coverage, 3447, |
| 40384 | GIR_EraseRootFromParent_Done, |
| 40385 | // Label 2202: @130148 |
| 40386 | GIM_Try, /*On fail goto*//*Label 2203*/ GIMT_Encode4(130212), // Rule ID 3434 // |
| 40387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40388 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40389 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40390 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40392 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 40394 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_global>> => (GLOBAL_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SBYTE), |
| 40396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40401 | GIR_RootConstrainSelectedInstOperands, |
| 40402 | // GIR_Coverage, 3434, |
| 40403 | GIR_EraseRootFromParent_Done, |
| 40404 | // Label 2203: @130212 |
| 40405 | GIM_Try, /*On fail goto*//*Label 2204*/ GIMT_Encode4(130276), // Rule ID 3446 // |
| 40406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40407 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40408 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40409 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40411 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40412 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 40413 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_global>> => (GLOBAL_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_SSHORT), |
| 40415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40420 | GIR_RootConstrainSelectedInstOperands, |
| 40421 | // GIR_Coverage, 3446, |
| 40422 | GIR_EraseRootFromParent_Done, |
| 40423 | // Label 2204: @130276 |
| 40424 | GIM_Try, /*On fail goto*//*Label 2205*/ GIMT_Encode4(130341), // Rule ID 3216 // |
| 40425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 40426 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40427 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40428 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40430 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 40432 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi8>><<P:Predicate_sextloadi8_flat>> => (FLAT_LOAD_SBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SBYTE), |
| 40434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40438 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40439 | GIR_RootConstrainSelectedInstOperands, |
| 40440 | // GIR_Coverage, 3216, |
| 40441 | GIR_EraseRootFromParent_Done, |
| 40442 | // Label 2205: @130341 |
| 40443 | GIM_Try, /*On fail goto*//*Label 2206*/ GIMT_Encode4(130406), // Rule ID 3223 // |
| 40444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 40445 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40446 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40447 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40449 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40450 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 40451 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_sextload>><<P:Predicate_sextloadi16>><<P:Predicate_sextloadi16_flat>> => (FLAT_LOAD_SSHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_SSHORT), |
| 40453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40458 | GIR_RootConstrainSelectedInstOperands, |
| 40459 | // GIR_Coverage, 3223, |
| 40460 | GIR_EraseRootFromParent_Done, |
| 40461 | // Label 2206: @130406 |
| 40462 | GIM_Reject, |
| 40463 | // Label 2145: @130407 |
| 40464 | GIM_Reject, |
| 40465 | // Label 15: @130408 |
| 40466 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 2209*/ GIMT_Encode4(134249), |
| 40467 | /*GILLT_s16*//*Label 2207*/ GIMT_Encode4(130427), |
| 40468 | /*GILLT_s32*//*Label 2208*/ GIMT_Encode4(131418), |
| 40469 | // Label 2207: @130427 |
| 40470 | GIM_Try, /*On fail goto*//*Label 2210*/ GIMT_Encode4(131417), |
| 40471 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40472 | GIM_Try, /*On fail goto*//*Label 2211*/ GIMT_Encode4(130502), // Rule ID 6150 // |
| 40473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40474 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40475 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40477 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 40479 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 40481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40488 | GIR_RootConstrainSelectedInstOperands, |
| 40489 | // GIR_Coverage, 6150, |
| 40490 | GIR_EraseRootFromParent_Done, |
| 40491 | // Label 2211: @130502 |
| 40492 | GIM_Try, /*On fail goto*//*Label 2212*/ GIMT_Encode4(130565), // Rule ID 6152 // |
| 40493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 40494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40495 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 40499 | // (ld:{ *:[i16] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 40501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40508 | GIR_RootConstrainSelectedInstOperands, |
| 40509 | // GIR_Coverage, 6152, |
| 40510 | GIR_EraseRootFromParent_Done, |
| 40511 | // Label 2212: @130565 |
| 40512 | GIM_Try, /*On fail goto*//*Label 2213*/ GIMT_Encode4(130625), // Rule ID 3861 // |
| 40513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 40514 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40515 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 40519 | // (ld:{ *:[i16] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE_SVS:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS), |
| 40521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 40524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40526 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40527 | GIR_RootConstrainSelectedInstOperands, |
| 40528 | // GIR_Coverage, 3861, |
| 40529 | GIR_EraseRootFromParent_Done, |
| 40530 | // Label 2213: @130625 |
| 40531 | GIM_Try, /*On fail goto*//*Label 2214*/ GIMT_Encode4(130680), // Rule ID 3860 // |
| 40532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 40533 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40534 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40536 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40537 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 40538 | // (ld:{ *:[i16] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 40539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR), |
| 40540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 40542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40544 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40545 | GIR_RootConstrainSelectedInstOperands, |
| 40546 | // GIR_Coverage, 3860, |
| 40547 | GIR_EraseRootFromParent_Done, |
| 40548 | // Label 2214: @130680 |
| 40549 | GIM_Try, /*On fail goto*//*Label 2215*/ GIMT_Encode4(130735), // Rule ID 3859 // |
| 40550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 40551 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40552 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40554 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40555 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 40556 | // (ld:{ *:[i16] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE), |
| 40558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40562 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40563 | GIR_RootConstrainSelectedInstOperands, |
| 40564 | // GIR_Coverage, 3859, |
| 40565 | GIR_EraseRootFromParent_Done, |
| 40566 | // Label 2215: @130735 |
| 40567 | GIM_Try, /*On fail goto*//*Label 2216*/ GIMT_Encode4(130803), // Rule ID 6149 // |
| 40568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40569 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40570 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40572 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40573 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40574 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), |
| 40576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40583 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40584 | GIR_RootConstrainSelectedInstOperands, |
| 40585 | // GIR_Coverage, 6149, |
| 40586 | GIR_EraseRootFromParent_Done, |
| 40587 | // Label 2216: @130803 |
| 40588 | GIM_Try, /*On fail goto*//*Label 2217*/ GIMT_Encode4(130871), // Rule ID 6151 // |
| 40589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 40590 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40591 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40593 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40594 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 40595 | // (ld:{ *:[i16] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i16] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN), |
| 40597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 40599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 40601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 40602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40605 | GIR_RootConstrainSelectedInstOperands, |
| 40606 | // GIR_Coverage, 6151, |
| 40607 | GIR_EraseRootFromParent_Done, |
| 40608 | // Label 2217: @130871 |
| 40609 | GIM_Try, /*On fail goto*//*Label 2218*/ GIMT_Encode4(130935), // Rule ID 6117 // |
| 40610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 40611 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40616 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 40618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40625 | GIR_RootConstrainSelectedInstOperands, |
| 40626 | // GIR_Coverage, 6117, |
| 40627 | GIR_EraseRootFromParent_Done, |
| 40628 | // Label 2218: @130935 |
| 40629 | GIM_Try, /*On fail goto*//*Label 2219*/ GIMT_Encode4(130999), // Rule ID 6118 // |
| 40630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 40631 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40632 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40636 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 40638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40645 | GIR_RootConstrainSelectedInstOperands, |
| 40646 | // GIR_Coverage, 6118, |
| 40647 | GIR_EraseRootFromParent_Done, |
| 40648 | // Label 2219: @130999 |
| 40649 | GIM_Try, /*On fail goto*//*Label 2220*/ GIMT_Encode4(131064), // Rule ID 6123 // |
| 40650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 40651 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40652 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40656 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 40658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40665 | GIR_RootConstrainSelectedInstOperands, |
| 40666 | // GIR_Coverage, 6123, |
| 40667 | GIR_EraseRootFromParent_Done, |
| 40668 | // Label 2220: @131064 |
| 40669 | GIM_Try, /*On fail goto*//*Label 2221*/ GIMT_Encode4(131129), // Rule ID 6124 // |
| 40670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 40671 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40672 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40674 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 40676 | // (ld:{ *:[i16] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i16] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 40677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 40678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40684 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40685 | GIR_RootConstrainSelectedInstOperands, |
| 40686 | // GIR_Coverage, 6124, |
| 40687 | GIR_EraseRootFromParent_Done, |
| 40688 | // Label 2221: @131129 |
| 40689 | GIM_Try, /*On fail goto*//*Label 2222*/ GIMT_Encode4(131184), // Rule ID 7445 // |
| 40690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 40691 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40692 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40696 | // (AMDGPUld_glue:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>> => (DS_READ_U8:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 40698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40703 | GIR_RootConstrainSelectedInstOperands, |
| 40704 | // GIR_Coverage, 7445, |
| 40705 | GIR_EraseRootFromParent_Done, |
| 40706 | // Label 2222: @131184 |
| 40707 | GIM_Try, /*On fail goto*//*Label 2223*/ GIMT_Encode4(131239), // Rule ID 7446 // |
| 40708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 40709 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 40710 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40712 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40713 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 40714 | // (ld:{ *:[i16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>> => (DS_READ_U8_gfx9:{ *:[i16] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 40715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 40716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 40718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40720 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40721 | GIR_RootConstrainSelectedInstOperands, |
| 40722 | // GIR_Coverage, 7446, |
| 40723 | GIR_EraseRootFromParent_Done, |
| 40724 | // Label 2223: @131239 |
| 40725 | GIM_Try, /*On fail goto*//*Label 2224*/ GIMT_Encode4(131301), // Rule ID 3439 // |
| 40726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40727 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40728 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 40732 | // (ld:{ *:[i16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 40734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 40736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 40737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40740 | GIR_RootConstrainSelectedInstOperands, |
| 40741 | // GIR_Coverage, 3439, |
| 40742 | GIR_EraseRootFromParent_Done, |
| 40743 | // Label 2224: @131301 |
| 40744 | GIM_Try, /*On fail goto*//*Label 2225*/ GIMT_Encode4(131358), // Rule ID 3438 // |
| 40745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 40746 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40749 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40750 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 40751 | // (ld:{ *:[i16] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 40753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40758 | GIR_RootConstrainSelectedInstOperands, |
| 40759 | // GIR_Coverage, 3438, |
| 40760 | GIR_EraseRootFromParent_Done, |
| 40761 | // Label 2225: @131358 |
| 40762 | GIM_Try, /*On fail goto*//*Label 2226*/ GIMT_Encode4(131416), // Rule ID 3218 // |
| 40763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 40764 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 40765 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40767 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 40769 | // (ld:{ *:[i16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 40770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 40771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 40772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 40773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40776 | GIR_RootConstrainSelectedInstOperands, |
| 40777 | // GIR_Coverage, 3218, |
| 40778 | GIR_EraseRootFromParent_Done, |
| 40779 | // Label 2226: @131416 |
| 40780 | GIM_Reject, |
| 40781 | // Label 2210: @131417 |
| 40782 | GIM_Reject, |
| 40783 | // Label 2208: @131418 |
| 40784 | GIM_Try, /*On fail goto*//*Label 2227*/ GIMT_Encode4(131484), // Rule ID 2479 // |
| 40785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40786 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40787 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40790 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8), |
| 40791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 40792 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>> => (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM), |
| 40794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40800 | GIR_RootConstrainSelectedInstOperands, |
| 40801 | // GIR_Coverage, 2479, |
| 40802 | GIR_EraseRootFromParent_Done, |
| 40803 | // Label 2227: @131484 |
| 40804 | GIM_Try, /*On fail goto*//*Label 2228*/ GIMT_Encode4(131550), // Rule ID 2491 // |
| 40805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40806 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40809 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40810 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16), |
| 40811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr_imm), |
| 40812 | // (ld:{ *:[i32] } (SMRDSgprImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>> => (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM), |
| 40814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40820 | GIR_RootConstrainSelectedInstOperands, |
| 40821 | // GIR_Coverage, 2491, |
| 40822 | GIR_EraseRootFromParent_Done, |
| 40823 | // Label 2228: @131550 |
| 40824 | GIM_Try, /*On fail goto*//*Label 2229*/ GIMT_Encode4(131611), // Rule ID 2477 // |
| 40825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40826 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40827 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40830 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8), |
| 40831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 40832 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>> => (S_LOAD_U8_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM), |
| 40834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40838 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40839 | GIR_RootConstrainSelectedInstOperands, |
| 40840 | // GIR_Coverage, 2477, |
| 40841 | GIR_EraseRootFromParent_Done, |
| 40842 | // Label 2229: @131611 |
| 40843 | GIM_Try, /*On fail goto*//*Label 2230*/ GIMT_Encode4(131675), // Rule ID 2478 // |
| 40844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40845 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40846 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40848 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40849 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8), |
| 40850 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 40851 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>> => (S_LOAD_U8_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 40852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_SGPR_IMM), |
| 40853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40859 | GIR_RootConstrainSelectedInstOperands, |
| 40860 | // GIR_Coverage, 2478, |
| 40861 | GIR_EraseRootFromParent_Done, |
| 40862 | // Label 2230: @131675 |
| 40863 | GIM_Try, /*On fail goto*//*Label 2231*/ GIMT_Encode4(131736), // Rule ID 2489 // |
| 40864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40865 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40866 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40869 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16), |
| 40870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 40871 | // (ld:{ *:[i32] } (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>> => (S_LOAD_U16_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 40872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM), |
| 40873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 40876 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40877 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40878 | GIR_RootConstrainSelectedInstOperands, |
| 40879 | // GIR_Coverage, 2489, |
| 40880 | GIR_EraseRootFromParent_Done, |
| 40881 | // Label 2231: @131736 |
| 40882 | GIM_Try, /*On fail goto*//*Label 2232*/ GIMT_Encode4(131800), // Rule ID 2490 // |
| 40883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40884 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40885 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40887 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16), |
| 40889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_sgpr), |
| 40890 | // (ld:{ *:[i32] } (SMRDSgpr:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$soffset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>> => (S_LOAD_U16_SGPR_IMM:{ *:[i32] } ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$soffset, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 40891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_SGPR_IMM), |
| 40892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 40894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40898 | GIR_RootConstrainSelectedInstOperands, |
| 40899 | // GIR_Coverage, 2490, |
| 40900 | GIR_EraseRootFromParent_Done, |
| 40901 | // Label 2232: @131800 |
| 40902 | GIM_Try, /*On fail goto*//*Label 2233*/ GIMT_Encode4(131853), // Rule ID 2480 // |
| 40903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40904 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40905 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40907 | // MIs[0] sbase |
| 40908 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40909 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 40910 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi8), |
| 40911 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_smrd_zextloadi8>> => (S_LOAD_U8_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 40912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U8_IMM), |
| 40913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40914 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 40915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40918 | GIR_RootConstrainSelectedInstOperands, |
| 40919 | // GIR_Coverage, 2480, |
| 40920 | GIR_EraseRootFromParent_Done, |
| 40921 | // Label 2233: @131853 |
| 40922 | GIM_Try, /*On fail goto*//*Label 2234*/ GIMT_Encode4(131906), // Rule ID 2492 // |
| 40923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 40924 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40925 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 40927 | // MIs[0] sbase |
| 40928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/64, |
| 40929 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 40930 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_zextloadi16), |
| 40931 | // (ld:{ *:[i32] } SReg_64:{ *:[i64] }:$sbase)<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_smrd_zextloadi16>> => (S_LOAD_U16_IMM:{ *:[i32] } i64:{ *:[i64] }:$sbase, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 40932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LOAD_U16_IMM), |
| 40933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 40934 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 40935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40938 | GIR_RootConstrainSelectedInstOperands, |
| 40939 | // GIR_Coverage, 2492, |
| 40940 | GIR_EraseRootFromParent_Done, |
| 40941 | // Label 2234: @131906 |
| 40942 | GIM_Try, /*On fail goto*//*Label 2235*/ GIMT_Encode4(131976), // Rule ID 6138 // |
| 40943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40944 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40945 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40946 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40948 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40949 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 40950 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 40952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40959 | GIR_RootConstrainSelectedInstOperands, |
| 40960 | // GIR_Coverage, 6138, |
| 40961 | GIR_EraseRootFromParent_Done, |
| 40962 | // Label 2235: @131976 |
| 40963 | GIM_Try, /*On fail goto*//*Label 2236*/ GIMT_Encode4(132046), // Rule ID 6140 // |
| 40964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 40965 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 40966 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40967 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 40971 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 40973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40979 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 40980 | GIR_RootConstrainSelectedInstOperands, |
| 40981 | // GIR_Coverage, 6140, |
| 40982 | GIR_EraseRootFromParent_Done, |
| 40983 | // Label 2236: @132046 |
| 40984 | GIM_Try, /*On fail goto*//*Label 2237*/ GIMT_Encode4(132116), // Rule ID 6162 // |
| 40985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 40986 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 40987 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 40988 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 40989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 40990 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 40991 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 40992 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 40993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 40994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 40995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 40996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 40997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 40998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 40999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41000 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41001 | GIR_RootConstrainSelectedInstOperands, |
| 41002 | // GIR_Coverage, 6162, |
| 41003 | GIR_EraseRootFromParent_Done, |
| 41004 | // Label 2237: @132116 |
| 41005 | GIM_Try, /*On fail goto*//*Label 2238*/ GIMT_Encode4(132186), // Rule ID 6164 // |
| 41006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 41007 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41008 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41009 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41011 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 41013 | // (ld:{ *:[i32] } (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 41014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 41015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41021 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41022 | GIR_RootConstrainSelectedInstOperands, |
| 41023 | // GIR_Coverage, 6164, |
| 41024 | GIR_EraseRootFromParent_Done, |
| 41025 | // Label 2238: @132186 |
| 41026 | GIM_Try, /*On fail goto*//*Label 2239*/ GIMT_Encode4(132253), // Rule ID 3852 // |
| 41027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 41028 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41029 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41030 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 41034 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 41035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SVS), |
| 41036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 41039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41041 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41042 | GIR_RootConstrainSelectedInstOperands, |
| 41043 | // GIR_Coverage, 3852, |
| 41044 | GIR_EraseRootFromParent_Done, |
| 41045 | // Label 2239: @132253 |
| 41046 | GIM_Try, /*On fail goto*//*Label 2240*/ GIMT_Encode4(132320), // Rule ID 3870 // |
| 41047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 41048 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41049 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41050 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 41054 | // (ld:{ *:[i32] } (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (SCRATCH_LOAD_USHORT_SVS:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 41055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SVS), |
| 41056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 41059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41061 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41062 | GIR_RootConstrainSelectedInstOperands, |
| 41063 | // GIR_Coverage, 3870, |
| 41064 | GIR_EraseRootFromParent_Done, |
| 41065 | // Label 2240: @132320 |
| 41066 | GIM_Try, /*On fail goto*//*Label 2241*/ GIMT_Encode4(132382), // Rule ID 3851 // |
| 41067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41068 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41069 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41070 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 41074 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 41075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE_SADDR), |
| 41076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41081 | GIR_RootConstrainSelectedInstOperands, |
| 41082 | // GIR_Coverage, 3851, |
| 41083 | GIR_EraseRootFromParent_Done, |
| 41084 | // Label 2241: @132382 |
| 41085 | GIM_Try, /*On fail goto*//*Label 2242*/ GIMT_Encode4(132444), // Rule ID 3869 // |
| 41086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41087 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41088 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41089 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 41093 | // (ld:{ *:[i32] } (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (SCRATCH_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 41094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT_SADDR), |
| 41095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41099 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41100 | GIR_RootConstrainSelectedInstOperands, |
| 41101 | // GIR_Coverage, 3869, |
| 41102 | GIR_EraseRootFromParent_Done, |
| 41103 | // Label 2242: @132444 |
| 41104 | GIM_Try, /*On fail goto*//*Label 2243*/ GIMT_Encode4(132506), // Rule ID 3850 // |
| 41105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41106 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41107 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41108 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 41112 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (SCRATCH_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_UBYTE), |
| 41114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41119 | GIR_RootConstrainSelectedInstOperands, |
| 41120 | // GIR_Coverage, 3850, |
| 41121 | GIR_EraseRootFromParent_Done, |
| 41122 | // Label 2243: @132506 |
| 41123 | GIM_Try, /*On fail goto*//*Label 2244*/ GIMT_Encode4(132568), // Rule ID 3868 // |
| 41124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41125 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41126 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41127 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 41131 | // (ld:{ *:[i32] } (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (SCRATCH_LOAD_USHORT:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_LOAD_USHORT), |
| 41133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41138 | GIR_RootConstrainSelectedInstOperands, |
| 41139 | // GIR_Coverage, 3868, |
| 41140 | GIR_EraseRootFromParent_Done, |
| 41141 | // Label 2244: @132568 |
| 41142 | GIM_Try, /*On fail goto*//*Label 2245*/ GIMT_Encode4(132645), // Rule ID 4110 // |
| 41143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41144 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41145 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41146 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41150 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 41152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41159 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41160 | GIR_RootConstrainSelectedInstOperands, |
| 41161 | // GIR_Coverage, 4110, |
| 41162 | GIR_EraseRootFromParent_Done, |
| 41163 | // Label 2245: @132645 |
| 41164 | GIM_Try, /*On fail goto*//*Label 2246*/ GIMT_Encode4(132719), // Rule ID 4112 // |
| 41165 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41166 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41167 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41169 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41170 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41171 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_ADDR64), |
| 41173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41181 | GIR_RootConstrainSelectedInstOperands, |
| 41182 | // GIR_Coverage, 4112, |
| 41183 | GIR_EraseRootFromParent_Done, |
| 41184 | // Label 2246: @132719 |
| 41185 | GIM_Try, /*On fail goto*//*Label 2247*/ GIMT_Encode4(132796), // Rule ID 4122 // |
| 41186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41187 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41188 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41189 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41191 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41193 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 41195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41202 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41203 | GIR_RootConstrainSelectedInstOperands, |
| 41204 | // GIR_Coverage, 4122, |
| 41205 | GIR_EraseRootFromParent_Done, |
| 41206 | // Label 2247: @132796 |
| 41207 | GIM_Try, /*On fail goto*//*Label 2248*/ GIMT_Encode4(132870), // Rule ID 4124 // |
| 41208 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41209 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41210 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41212 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41213 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41214 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_ADDR64:{ *:[i32] } i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_ADDR64), |
| 41216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41223 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41224 | GIR_RootConstrainSelectedInstOperands, |
| 41225 | // GIR_Coverage, 4124, |
| 41226 | GIR_EraseRootFromParent_Done, |
| 41227 | // Label 2248: @132870 |
| 41228 | GIM_Try, /*On fail goto*//*Label 2249*/ GIMT_Encode4(132946), // Rule ID 6107 // |
| 41229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 41230 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41231 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41232 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41234 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41235 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41236 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_constant>> => (BUFFER_LOAD_UBYTE_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 41237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_ADDR64), |
| 41238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41245 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41246 | GIR_RootConstrainSelectedInstOperands, |
| 41247 | // GIR_Coverage, 6107, |
| 41248 | GIR_EraseRootFromParent_Done, |
| 41249 | // Label 2249: @132946 |
| 41250 | GIM_Try, /*On fail goto*//*Label 2250*/ GIMT_Encode4(133022), // Rule ID 6110 // |
| 41251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 41252 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41253 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41254 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41256 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41258 | // (ld:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_constant>> => (BUFFER_LOAD_USHORT_ADDR64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 41259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_ADDR64), |
| 41260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41267 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41268 | GIR_RootConstrainSelectedInstOperands, |
| 41269 | // GIR_Coverage, 6110, |
| 41270 | GIR_EraseRootFromParent_Done, |
| 41271 | // Label 2250: @133022 |
| 41272 | GIM_Try, /*On fail goto*//*Label 2251*/ GIMT_Encode4(133097), // Rule ID 6137 // |
| 41273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 41274 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41275 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41276 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41278 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41279 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 41280 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 41281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), |
| 41282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41290 | GIR_RootConstrainSelectedInstOperands, |
| 41291 | // GIR_Coverage, 6137, |
| 41292 | GIR_EraseRootFromParent_Done, |
| 41293 | // Label 2251: @133097 |
| 41294 | GIM_Try, /*On fail goto*//*Label 2252*/ GIMT_Encode4(133172), // Rule ID 6139 // |
| 41295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 41296 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41297 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41298 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 41302 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_private>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 41303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN), |
| 41304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41311 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41312 | GIR_RootConstrainSelectedInstOperands, |
| 41313 | // GIR_Coverage, 6139, |
| 41314 | GIR_EraseRootFromParent_Done, |
| 41315 | // Label 2252: @133172 |
| 41316 | GIM_Try, /*On fail goto*//*Label 2253*/ GIMT_Encode4(133247), // Rule ID 6161 // |
| 41317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 41318 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41320 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41322 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 41324 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 41325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), |
| 41326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41334 | GIR_RootConstrainSelectedInstOperands, |
| 41335 | // GIR_Coverage, 6161, |
| 41336 | GIR_EraseRootFromParent_Done, |
| 41337 | // Label 2253: @133247 |
| 41338 | GIM_Try, /*On fail goto*//*Label 2254*/ GIMT_Encode4(133322), // Rule ID 6163 // |
| 41339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 41340 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41341 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 41346 | // (ld:{ *:[i32] } (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_private>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 41347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN), |
| 41348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41356 | GIR_RootConstrainSelectedInstOperands, |
| 41357 | // GIR_Coverage, 6163, |
| 41358 | GIR_EraseRootFromParent_Done, |
| 41359 | // Label 2254: @133322 |
| 41360 | GIM_Try, /*On fail goto*//*Label 2255*/ GIMT_Encode4(133394), // Rule ID 4109 // |
| 41361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41362 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41363 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41364 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41366 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41367 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41368 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 41370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41376 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41377 | GIR_RootConstrainSelectedInstOperands, |
| 41378 | // GIR_Coverage, 4109, |
| 41379 | GIR_EraseRootFromParent_Done, |
| 41380 | // Label 2255: @133394 |
| 41381 | GIM_Try, /*On fail goto*//*Label 2256*/ GIMT_Encode4(133463), // Rule ID 4111 // |
| 41382 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41383 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41384 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41388 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 41390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41397 | GIR_RootConstrainSelectedInstOperands, |
| 41398 | // GIR_Coverage, 4111, |
| 41399 | GIR_EraseRootFromParent_Done, |
| 41400 | // Label 2256: @133463 |
| 41401 | GIM_Try, /*On fail goto*//*Label 2257*/ GIMT_Encode4(133535), // Rule ID 4121 // |
| 41402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41403 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41404 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41405 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41409 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 41411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41418 | GIR_RootConstrainSelectedInstOperands, |
| 41419 | // GIR_Coverage, 4121, |
| 41420 | GIR_EraseRootFromParent_Done, |
| 41421 | // Label 2257: @133535 |
| 41422 | GIM_Try, /*On fail goto*//*Label 2258*/ GIMT_Encode4(133604), // Rule ID 4123 // |
| 41423 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41424 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41425 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41429 | // (ld:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 41431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 41432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41437 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41438 | GIR_RootConstrainSelectedInstOperands, |
| 41439 | // GIR_Coverage, 4123, |
| 41440 | GIR_EraseRootFromParent_Done, |
| 41441 | // Label 2258: @133604 |
| 41442 | GIM_Try, /*On fail goto*//*Label 2259*/ GIMT_Encode4(133666), // Rule ID 7441 // |
| 41443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 41444 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41445 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41446 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41450 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi8_glue>><<P:Predicate_zextloadi8_local_m0>> => (DS_READ_U8:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8), |
| 41452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41456 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41457 | GIR_RootConstrainSelectedInstOperands, |
| 41458 | // GIR_Coverage, 7441, |
| 41459 | GIR_EraseRootFromParent_Done, |
| 41460 | // Label 2259: @133666 |
| 41461 | GIM_Try, /*On fail goto*//*Label 2260*/ GIMT_Encode4(133728), // Rule ID 7442 // |
| 41462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 41463 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41464 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41465 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41467 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41468 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41469 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_local>> => (DS_READ_U8_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U8_gfx9), |
| 41471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41475 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41476 | GIR_RootConstrainSelectedInstOperands, |
| 41477 | // GIR_Coverage, 7442, |
| 41478 | GIR_EraseRootFromParent_Done, |
| 41479 | // Label 2260: @133728 |
| 41480 | GIM_Try, /*On fail goto*//*Label 2261*/ GIMT_Encode4(133790), // Rule ID 7453 // |
| 41481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 41482 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41483 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41484 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41488 | // (AMDGPUld_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload_glue>><<P:Predicate_zextload_glue>><<P:Predicate_zextloadi16_glue>><<P:Predicate_zextloadi16_local_m0>> => (DS_READ_U16:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16), |
| 41490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41494 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41495 | GIR_RootConstrainSelectedInstOperands, |
| 41496 | // GIR_Coverage, 7453, |
| 41497 | GIR_EraseRootFromParent_Done, |
| 41498 | // Label 2261: @133790 |
| 41499 | GIM_Try, /*On fail goto*//*Label 2262*/ GIMT_Encode4(133852), // Rule ID 7454 // |
| 41500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 41501 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41502 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41503 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41505 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41507 | // (ld:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_local>> => (DS_READ_U16_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_READ_U16_gfx9), |
| 41509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41514 | GIR_RootConstrainSelectedInstOperands, |
| 41515 | // GIR_Coverage, 7454, |
| 41516 | GIR_EraseRootFromParent_Done, |
| 41517 | // Label 2262: @133852 |
| 41518 | GIM_Try, /*On fail goto*//*Label 2263*/ GIMT_Encode4(133921), // Rule ID 3433 // |
| 41519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41520 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41521 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41522 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41524 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 41526 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (GLOBAL_LOAD_UBYTE_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 41527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE_SADDR), |
| 41528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 41531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41533 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41534 | GIR_RootConstrainSelectedInstOperands, |
| 41535 | // GIR_Coverage, 3433, |
| 41536 | GIR_EraseRootFromParent_Done, |
| 41537 | // Label 2263: @133921 |
| 41538 | GIM_Try, /*On fail goto*//*Label 2264*/ GIMT_Encode4(133990), // Rule ID 3445 // |
| 41539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41540 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41541 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41542 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 41546 | // (ld:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (GLOBAL_LOAD_USHORT_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 41547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT_SADDR), |
| 41548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 41551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41554 | GIR_RootConstrainSelectedInstOperands, |
| 41555 | // GIR_Coverage, 3445, |
| 41556 | GIR_EraseRootFromParent_Done, |
| 41557 | // Label 2264: @133990 |
| 41558 | GIM_Try, /*On fail goto*//*Label 2265*/ GIMT_Encode4(134054), // Rule ID 3432 // |
| 41559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41560 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41561 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41562 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41564 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41565 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 41566 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_global>> => (GLOBAL_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_UBYTE), |
| 41568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41573 | GIR_RootConstrainSelectedInstOperands, |
| 41574 | // GIR_Coverage, 3432, |
| 41575 | GIR_EraseRootFromParent_Done, |
| 41576 | // Label 2265: @134054 |
| 41577 | GIM_Try, /*On fail goto*//*Label 2266*/ GIMT_Encode4(134118), // Rule ID 3444 // |
| 41578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41579 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41580 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41581 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41583 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41584 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 41585 | // (ld:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_global>> => (GLOBAL_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_USHORT), |
| 41587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41592 | GIR_RootConstrainSelectedInstOperands, |
| 41593 | // GIR_Coverage, 3444, |
| 41594 | GIR_EraseRootFromParent_Done, |
| 41595 | // Label 2266: @134118 |
| 41596 | GIM_Try, /*On fail goto*//*Label 2267*/ GIMT_Encode4(134183), // Rule ID 3215 // |
| 41597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 41598 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 41599 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41600 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41602 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41603 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 41604 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi8>><<P:Predicate_zextloadi8_flat>> => (FLAT_LOAD_UBYTE:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_UBYTE), |
| 41606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41611 | GIR_RootConstrainSelectedInstOperands, |
| 41612 | // GIR_Coverage, 3215, |
| 41613 | GIR_EraseRootFromParent_Done, |
| 41614 | // Label 2267: @134183 |
| 41615 | GIM_Try, /*On fail goto*//*Label 2268*/ GIMT_Encode4(134248), // Rule ID 3221 // |
| 41616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 41617 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 41618 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 41619 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 41621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 41623 | // (ld:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedload>><<P:Predicate_zextload>><<P:Predicate_zextloadi16>><<P:Predicate_zextloadi16_flat>> => (FLAT_LOAD_USHORT:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_LOAD_USHORT), |
| 41625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 41626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41630 | GIR_RootConstrainSelectedInstOperands, |
| 41631 | // GIR_Coverage, 3221, |
| 41632 | GIR_EraseRootFromParent_Done, |
| 41633 | // Label 2268: @134248 |
| 41634 | GIM_Reject, |
| 41635 | // Label 2209: @134249 |
| 41636 | GIM_Reject, |
| 41637 | // Label 16: @134250 |
| 41638 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(23), /*)*//*default:*//*Label 2286*/ GIMT_Encode4(170155), |
| 41639 | /*GILLT_p0s64*//*Label 2269*/ GIMT_Encode4(134353), |
| 41640 | /*GILLT_p1s64*//*Label 2270*/ GIMT_Encode4(135385), |
| 41641 | /*GILLT_p2s32*//*Label 2271*/ GIMT_Encode4(136417), |
| 41642 | /*GILLT_p3s32*//*Label 2272*/ GIMT_Encode4(137327), |
| 41643 | /*GILLT_p4s64*//*Label 2273*/ GIMT_Encode4(138237), |
| 41644 | /*GILLT_p5s32*//*Label 2274*/ GIMT_Encode4(139269), |
| 41645 | /*GILLT_p6s32*//*Label 2275*/ GIMT_Encode4(140179), GIMT_Encode4(0), |
| 41646 | /*GILLT_s16*//*Label 2276*/ GIMT_Encode4(141089), |
| 41647 | /*GILLT_s32*//*Label 2277*/ GIMT_Encode4(143542), |
| 41648 | /*GILLT_s64*//*Label 2278*/ GIMT_Encode4(150644), |
| 41649 | /*GILLT_v2s16*//*Label 2279*/ GIMT_Encode4(153074), |
| 41650 | /*GILLT_v2s32*//*Label 2280*/ GIMT_Encode4(155802), |
| 41651 | /*GILLT_v2s64*//*Label 2281*/ GIMT_Encode4(158111), |
| 41652 | /*GILLT_v3s32*//*Label 2282*/ GIMT_Encode4(160174), GIMT_Encode4(0), |
| 41653 | /*GILLT_v4s16*//*Label 2283*/ GIMT_Encode4(161658), |
| 41654 | /*GILLT_v4s32*//*Label 2284*/ GIMT_Encode4(164752), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 41655 | /*GILLT_v8s16*//*Label 2285*/ GIMT_Encode4(167061), |
| 41656 | // Label 2269: @134353 |
| 41657 | GIM_Try, /*On fail goto*//*Label 2287*/ GIMT_Encode4(134417), // Rule ID 7713 // |
| 41658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 41659 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 41660 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41661 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41662 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41663 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41664 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 41665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41666 | // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 41668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41669 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 41670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41672 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41673 | GIR_RootConstrainSelectedInstOperands, |
| 41674 | // GIR_Coverage, 7713, |
| 41675 | GIR_EraseRootFromParent_Done, |
| 41676 | // Label 2287: @134417 |
| 41677 | GIM_Try, /*On fail goto*//*Label 2288*/ GIMT_Encode4(134476), // Rule ID 7637 // |
| 41678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 41679 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 41680 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41681 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 41682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41683 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41685 | // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 41687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41688 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 41689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41692 | GIR_RootConstrainSelectedInstOperands, |
| 41693 | // GIR_Coverage, 7637, |
| 41694 | GIR_EraseRootFromParent_Done, |
| 41695 | // Label 2288: @134476 |
| 41696 | GIM_Try, /*On fail goto*//*Label 2289*/ GIMT_Encode4(134536), // Rule ID 7714 // |
| 41697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 41698 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41699 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41700 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41701 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41702 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 41703 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41704 | // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 41706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41707 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 41708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41710 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41711 | GIR_RootConstrainSelectedInstOperands, |
| 41712 | // GIR_Coverage, 7714, |
| 41713 | GIR_EraseRootFromParent_Done, |
| 41714 | // Label 2289: @134536 |
| 41715 | GIM_Try, /*On fail goto*//*Label 2290*/ GIMT_Encode4(134591), // Rule ID 7638 // |
| 41716 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 41717 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41718 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 41719 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41721 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41722 | // (st p0:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 41724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41725 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 41726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41729 | GIR_RootConstrainSelectedInstOperands, |
| 41730 | // GIR_Coverage, 7638, |
| 41731 | GIR_EraseRootFromParent_Done, |
| 41732 | // Label 2290: @134591 |
| 41733 | GIM_Try, /*On fail goto*//*Label 2291*/ GIMT_Encode4(134647), // Rule ID 3975 // |
| 41734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 41735 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41736 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41737 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 41739 | // (st p0:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 41740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 41741 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 41744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41746 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41747 | GIR_RootConstrainSelectedInstOperands, |
| 41748 | // GIR_Coverage, 3975, |
| 41749 | GIR_EraseRootFromParent_Done, |
| 41750 | // Label 2291: @134647 |
| 41751 | GIM_Try, /*On fail goto*//*Label 2292*/ GIMT_Encode4(134698), // Rule ID 3974 // |
| 41752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41753 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41754 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41755 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41756 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 41757 | // (st p0:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 41758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 41759 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41764 | GIR_RootConstrainSelectedInstOperands, |
| 41765 | // GIR_Coverage, 3974, |
| 41766 | GIR_EraseRootFromParent_Done, |
| 41767 | // Label 2292: @134698 |
| 41768 | GIM_Try, /*On fail goto*//*Label 2293*/ GIMT_Encode4(134749), // Rule ID 3973 // |
| 41769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 41770 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 41771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 41774 | // (st p0:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 41775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 41776 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41781 | GIR_RootConstrainSelectedInstOperands, |
| 41782 | // GIR_Coverage, 3973, |
| 41783 | GIR_EraseRootFromParent_Done, |
| 41784 | // Label 2293: @134749 |
| 41785 | GIM_Try, /*On fail goto*//*Label 2294*/ GIMT_Encode4(134813), // Rule ID 4312 // |
| 41786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41788 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41791 | // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 41793 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 41794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41801 | GIR_RootConstrainSelectedInstOperands, |
| 41802 | // GIR_Coverage, 4312, |
| 41803 | GIR_EraseRootFromParent_Done, |
| 41804 | // Label 2294: @134813 |
| 41805 | GIM_Try, /*On fail goto*//*Label 2295*/ GIMT_Encode4(134874), // Rule ID 4314 // |
| 41806 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41807 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 41810 | // (st p0:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p0:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 41812 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 41813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 41814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 41816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 41817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41820 | GIR_RootConstrainSelectedInstOperands, |
| 41821 | // GIR_Coverage, 4314, |
| 41822 | GIR_EraseRootFromParent_Done, |
| 41823 | // Label 2295: @134874 |
| 41824 | GIM_Try, /*On fail goto*//*Label 2296*/ GIMT_Encode4(134994), // Rule ID 7572 // |
| 41825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 41826 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 41827 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 41831 | // (AMDGPUst_glue p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 41832 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41833 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41834 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41835 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41836 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 41837 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 41838 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 41839 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41840 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41841 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 41842 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 41843 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 41844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 41845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41846 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41847 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 41848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 41849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 41850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41852 | GIR_RootConstrainSelectedInstOperands, |
| 41853 | // GIR_Coverage, 7572, |
| 41854 | GIR_EraseRootFromParent_Done, |
| 41855 | // Label 2296: @134994 |
| 41856 | GIM_Try, /*On fail goto*//*Label 2297*/ GIMT_Encode4(135053), // Rule ID 4311 // |
| 41857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 41858 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41859 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41860 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41861 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41862 | // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 41864 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 41865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41870 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41871 | GIR_RootConstrainSelectedInstOperands, |
| 41872 | // GIR_Coverage, 4311, |
| 41873 | GIR_EraseRootFromParent_Done, |
| 41874 | // Label 2297: @135053 |
| 41875 | GIM_Try, /*On fail goto*//*Label 2298*/ GIMT_Encode4(135109), // Rule ID 4313 // |
| 41876 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41877 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41878 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41879 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 41880 | // (st p0:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 41881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 41882 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 41883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 41884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 41885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41889 | GIR_RootConstrainSelectedInstOperands, |
| 41890 | // GIR_Coverage, 4313, |
| 41891 | GIR_EraseRootFromParent_Done, |
| 41892 | // Label 2298: @135109 |
| 41893 | GIM_Try, /*On fail goto*//*Label 2299*/ GIMT_Encode4(135225), // Rule ID 7574 // |
| 41894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 41895 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41896 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 41899 | // (st p0:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 41900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 41901 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 41902 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41903 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41904 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 41905 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 41906 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 41907 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 41908 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 41909 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 41910 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 41911 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 41912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 41913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41914 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 41915 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 41916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 41917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 41918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41919 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41920 | GIR_RootConstrainSelectedInstOperands, |
| 41921 | // GIR_Coverage, 7574, |
| 41922 | GIR_EraseRootFromParent_Done, |
| 41923 | // Label 2299: @135225 |
| 41924 | GIM_Try, /*On fail goto*//*Label 2300*/ GIMT_Encode4(135281), // Rule ID 3515 // |
| 41925 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41926 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41927 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41929 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 41930 | // (st p0:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 41931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 41932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 41933 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 41935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 41936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41938 | GIR_RootConstrainSelectedInstOperands, |
| 41939 | // GIR_Coverage, 3515, |
| 41940 | GIR_EraseRootFromParent_Done, |
| 41941 | // Label 2300: @135281 |
| 41942 | GIM_Try, /*On fail goto*//*Label 2301*/ GIMT_Encode4(135332), // Rule ID 3514 // |
| 41943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 41944 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 41945 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41946 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 41948 | // (st p0:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 41949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 41950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41951 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41954 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41955 | GIR_RootConstrainSelectedInstOperands, |
| 41956 | // GIR_Coverage, 3514, |
| 41957 | GIR_EraseRootFromParent_Done, |
| 41958 | // Label 2301: @135332 |
| 41959 | GIM_Try, /*On fail goto*//*Label 2302*/ GIMT_Encode4(135384), // Rule ID 3261 // |
| 41960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 41961 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 41962 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41963 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41964 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 41965 | // (st p0:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 41966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 41967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 41968 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 41969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41971 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41972 | GIR_RootConstrainSelectedInstOperands, |
| 41973 | // GIR_Coverage, 3261, |
| 41974 | GIR_EraseRootFromParent_Done, |
| 41975 | // Label 2302: @135384 |
| 41976 | GIM_Reject, |
| 41977 | // Label 2270: @135385 |
| 41978 | GIM_Try, /*On fail goto*//*Label 2303*/ GIMT_Encode4(135449), // Rule ID 7717 // |
| 41979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 41980 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 41981 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41982 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 41983 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 41984 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 41985 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 41986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 41987 | // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 41988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 41989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 41990 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 41991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 41992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 41993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 41994 | GIR_RootConstrainSelectedInstOperands, |
| 41995 | // GIR_Coverage, 7717, |
| 41996 | GIR_EraseRootFromParent_Done, |
| 41997 | // Label 2303: @135449 |
| 41998 | GIM_Try, /*On fail goto*//*Label 2304*/ GIMT_Encode4(135508), // Rule ID 7641 // |
| 41999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 42000 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42001 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42002 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 42003 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42006 | // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 42008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42009 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42013 | GIR_RootConstrainSelectedInstOperands, |
| 42014 | // GIR_Coverage, 7641, |
| 42015 | GIR_EraseRootFromParent_Done, |
| 42016 | // Label 2304: @135508 |
| 42017 | GIM_Try, /*On fail goto*//*Label 2305*/ GIMT_Encode4(135568), // Rule ID 7718 // |
| 42018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 42019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42020 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42021 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42023 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 42024 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42025 | // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 42027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42028 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42032 | GIR_RootConstrainSelectedInstOperands, |
| 42033 | // GIR_Coverage, 7718, |
| 42034 | GIR_EraseRootFromParent_Done, |
| 42035 | // Label 2305: @135568 |
| 42036 | GIM_Try, /*On fail goto*//*Label 2306*/ GIMT_Encode4(135623), // Rule ID 7642 // |
| 42037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 42038 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42039 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 42040 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42041 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42043 | // (st p1:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 42045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42046 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42049 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42050 | GIR_RootConstrainSelectedInstOperands, |
| 42051 | // GIR_Coverage, 7642, |
| 42052 | GIR_EraseRootFromParent_Done, |
| 42053 | // Label 2306: @135623 |
| 42054 | GIM_Try, /*On fail goto*//*Label 2307*/ GIMT_Encode4(135679), // Rule ID 3981 // |
| 42055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 42056 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42057 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42058 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 42060 | // (st p1:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 42062 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 42065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42067 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42068 | GIR_RootConstrainSelectedInstOperands, |
| 42069 | // GIR_Coverage, 3981, |
| 42070 | GIR_EraseRootFromParent_Done, |
| 42071 | // Label 2307: @135679 |
| 42072 | GIM_Try, /*On fail goto*//*Label 2308*/ GIMT_Encode4(135730), // Rule ID 3980 // |
| 42073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42074 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42075 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42076 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42077 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 42078 | // (st p1:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 42080 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42084 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42085 | GIR_RootConstrainSelectedInstOperands, |
| 42086 | // GIR_Coverage, 3980, |
| 42087 | GIR_EraseRootFromParent_Done, |
| 42088 | // Label 2308: @135730 |
| 42089 | GIM_Try, /*On fail goto*//*Label 2309*/ GIMT_Encode4(135781), // Rule ID 3979 // |
| 42090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42091 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42092 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42093 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42094 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 42095 | // (st p1:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 42096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 42097 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42102 | GIR_RootConstrainSelectedInstOperands, |
| 42103 | // GIR_Coverage, 3979, |
| 42104 | GIR_EraseRootFromParent_Done, |
| 42105 | // Label 2309: @135781 |
| 42106 | GIM_Try, /*On fail goto*//*Label 2310*/ GIMT_Encode4(135845), // Rule ID 4316 // |
| 42107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42108 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42109 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42112 | // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 42114 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42121 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42122 | GIR_RootConstrainSelectedInstOperands, |
| 42123 | // GIR_Coverage, 4316, |
| 42124 | GIR_EraseRootFromParent_Done, |
| 42125 | // Label 2310: @135845 |
| 42126 | GIM_Try, /*On fail goto*//*Label 2311*/ GIMT_Encode4(135906), // Rule ID 4318 // |
| 42127 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42128 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42131 | // (st p1:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p1:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 42133 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42140 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42141 | GIR_RootConstrainSelectedInstOperands, |
| 42142 | // GIR_Coverage, 4318, |
| 42143 | GIR_EraseRootFromParent_Done, |
| 42144 | // Label 2311: @135906 |
| 42145 | GIM_Try, /*On fail goto*//*Label 2312*/ GIMT_Encode4(136026), // Rule ID 7576 // |
| 42146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 42147 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42148 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42149 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42150 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42151 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 42152 | // (AMDGPUst_glue p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 42153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42154 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 42155 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42156 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42157 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 42158 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 42159 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 42160 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42161 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42162 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 42163 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 42164 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 42165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 42166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42167 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42168 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 42169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 42170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 42171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42173 | GIR_RootConstrainSelectedInstOperands, |
| 42174 | // GIR_Coverage, 7576, |
| 42175 | GIR_EraseRootFromParent_Done, |
| 42176 | // Label 2312: @136026 |
| 42177 | GIM_Try, /*On fail goto*//*Label 2313*/ GIMT_Encode4(136085), // Rule ID 4315 // |
| 42178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42179 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42180 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42181 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42183 | // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 42185 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42191 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42192 | GIR_RootConstrainSelectedInstOperands, |
| 42193 | // GIR_Coverage, 4315, |
| 42194 | GIR_EraseRootFromParent_Done, |
| 42195 | // Label 2313: @136085 |
| 42196 | GIM_Try, /*On fail goto*//*Label 2314*/ GIMT_Encode4(136141), // Rule ID 4317 // |
| 42197 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42198 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42201 | // (st p1:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p1:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 42203 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42210 | GIR_RootConstrainSelectedInstOperands, |
| 42211 | // GIR_Coverage, 4317, |
| 42212 | GIR_EraseRootFromParent_Done, |
| 42213 | // Label 2314: @136141 |
| 42214 | GIM_Try, /*On fail goto*//*Label 2315*/ GIMT_Encode4(136257), // Rule ID 7578 // |
| 42215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 42216 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42217 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42218 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42219 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 42220 | // (st p1:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 42221 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 42222 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 42223 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42224 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42225 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 42226 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 42227 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 42228 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 42229 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 42230 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 42231 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 42232 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 42233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 42234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42235 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 42236 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 42237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 42238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 42239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42240 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42241 | GIR_RootConstrainSelectedInstOperands, |
| 42242 | // GIR_Coverage, 7578, |
| 42243 | GIR_EraseRootFromParent_Done, |
| 42244 | // Label 2315: @136257 |
| 42245 | GIM_Try, /*On fail goto*//*Label 2316*/ GIMT_Encode4(136313), // Rule ID 3519 // |
| 42246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42247 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42248 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42249 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 42251 | // (st p1:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 42253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 42254 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42259 | GIR_RootConstrainSelectedInstOperands, |
| 42260 | // GIR_Coverage, 3519, |
| 42261 | GIR_EraseRootFromParent_Done, |
| 42262 | // Label 2316: @136313 |
| 42263 | GIM_Try, /*On fail goto*//*Label 2317*/ GIMT_Encode4(136364), // Rule ID 3518 // |
| 42264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42265 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42266 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 42269 | // (st p1:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 42270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 42271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42272 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42276 | GIR_RootConstrainSelectedInstOperands, |
| 42277 | // GIR_Coverage, 3518, |
| 42278 | GIR_EraseRootFromParent_Done, |
| 42279 | // Label 2317: @136364 |
| 42280 | GIM_Try, /*On fail goto*//*Label 2318*/ GIMT_Encode4(136416), // Rule ID 3263 // |
| 42281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 42282 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 42283 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42285 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 42286 | // (st p1:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 42287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 42288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42289 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42292 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42293 | GIR_RootConstrainSelectedInstOperands, |
| 42294 | // GIR_Coverage, 3263, |
| 42295 | GIR_EraseRootFromParent_Done, |
| 42296 | // Label 2318: @136416 |
| 42297 | GIM_Reject, |
| 42298 | // Label 2271: @136417 |
| 42299 | GIM_Try, /*On fail goto*//*Label 2319*/ GIMT_Encode4(136476), // Rule ID 6316 // |
| 42300 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 42301 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42302 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42303 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 42305 | // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 42307 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42313 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42314 | GIR_RootConstrainSelectedInstOperands, |
| 42315 | // GIR_Coverage, 6316, |
| 42316 | GIR_EraseRootFromParent_Done, |
| 42317 | // Label 2319: @136476 |
| 42318 | GIM_Try, /*On fail goto*//*Label 2320*/ GIMT_Encode4(136535), // Rule ID 6318 // |
| 42319 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 42320 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42321 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42322 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 42324 | // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 42326 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42333 | GIR_RootConstrainSelectedInstOperands, |
| 42334 | // GIR_Coverage, 6318, |
| 42335 | GIR_EraseRootFromParent_Done, |
| 42336 | // Label 2320: @136535 |
| 42337 | GIM_Try, /*On fail goto*//*Label 2321*/ GIMT_Encode4(136591), // Rule ID 3909 // |
| 42338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 42339 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42340 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 42343 | // (st p2:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 42345 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 42348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42351 | GIR_RootConstrainSelectedInstOperands, |
| 42352 | // GIR_Coverage, 3909, |
| 42353 | GIR_EraseRootFromParent_Done, |
| 42354 | // Label 2321: @136591 |
| 42355 | GIM_Try, /*On fail goto*//*Label 2322*/ GIMT_Encode4(136642), // Rule ID 3908 // |
| 42356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42357 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42358 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42359 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 42361 | // (st p2:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 42363 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42368 | GIR_RootConstrainSelectedInstOperands, |
| 42369 | // GIR_Coverage, 3908, |
| 42370 | GIR_EraseRootFromParent_Done, |
| 42371 | // Label 2322: @136642 |
| 42372 | GIM_Try, /*On fail goto*//*Label 2323*/ GIMT_Encode4(136693), // Rule ID 3907 // |
| 42373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42374 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 42378 | // (st p2:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 42379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 42380 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42385 | GIR_RootConstrainSelectedInstOperands, |
| 42386 | // GIR_Coverage, 3907, |
| 42387 | GIR_EraseRootFromParent_Done, |
| 42388 | // Label 2323: @136693 |
| 42389 | GIM_Try, /*On fail goto*//*Label 2324*/ GIMT_Encode4(136757), // Rule ID 4268 // |
| 42390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42391 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42392 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42395 | // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 42397 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42404 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42405 | GIR_RootConstrainSelectedInstOperands, |
| 42406 | // GIR_Coverage, 4268, |
| 42407 | GIR_EraseRootFromParent_Done, |
| 42408 | // Label 2324: @136757 |
| 42409 | GIM_Try, /*On fail goto*//*Label 2325*/ GIMT_Encode4(136818), // Rule ID 4270 // |
| 42410 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42411 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42414 | // (st p2:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p2:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 42416 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42424 | GIR_RootConstrainSelectedInstOperands, |
| 42425 | // GIR_Coverage, 4270, |
| 42426 | GIR_EraseRootFromParent_Done, |
| 42427 | // Label 2325: @136818 |
| 42428 | GIM_Try, /*On fail goto*//*Label 2326*/ GIMT_Encode4(136882), // Rule ID 6315 // |
| 42429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 42430 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42431 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 42434 | // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 42436 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42443 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42444 | GIR_RootConstrainSelectedInstOperands, |
| 42445 | // GIR_Coverage, 6315, |
| 42446 | GIR_EraseRootFromParent_Done, |
| 42447 | // Label 2326: @136882 |
| 42448 | GIM_Try, /*On fail goto*//*Label 2327*/ GIMT_Encode4(136946), // Rule ID 6317 // |
| 42449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 42450 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42451 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 42454 | // (st p2:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 42456 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42463 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42464 | GIR_RootConstrainSelectedInstOperands, |
| 42465 | // GIR_Coverage, 6317, |
| 42466 | GIR_EraseRootFromParent_Done, |
| 42467 | // Label 2327: @136946 |
| 42468 | GIM_Try, /*On fail goto*//*Label 2328*/ GIMT_Encode4(137005), // Rule ID 4267 // |
| 42469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42470 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42471 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42472 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42473 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42474 | // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 42476 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42483 | GIR_RootConstrainSelectedInstOperands, |
| 42484 | // GIR_Coverage, 4267, |
| 42485 | GIR_EraseRootFromParent_Done, |
| 42486 | // Label 2328: @137005 |
| 42487 | GIM_Try, /*On fail goto*//*Label 2329*/ GIMT_Encode4(137061), // Rule ID 4269 // |
| 42488 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42489 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42492 | // (st p2:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 42494 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42501 | GIR_RootConstrainSelectedInstOperands, |
| 42502 | // GIR_Coverage, 4269, |
| 42503 | GIR_EraseRootFromParent_Done, |
| 42504 | // Label 2329: @137061 |
| 42505 | GIM_Try, /*On fail goto*//*Label 2330*/ GIMT_Encode4(137116), // Rule ID 7517 // |
| 42506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 42507 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42508 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42509 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42512 | // (AMDGPUst_glue p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 42514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42515 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42518 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42519 | GIR_RootConstrainSelectedInstOperands, |
| 42520 | // GIR_Coverage, 7517, |
| 42521 | GIR_EraseRootFromParent_Done, |
| 42522 | // Label 2330: @137116 |
| 42523 | GIM_Try, /*On fail goto*//*Label 2331*/ GIMT_Encode4(137167), // Rule ID 7518 // |
| 42524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 42525 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42526 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42527 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42529 | // (st p2:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 42531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42532 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42535 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42536 | GIR_RootConstrainSelectedInstOperands, |
| 42537 | // GIR_Coverage, 7518, |
| 42538 | GIR_EraseRootFromParent_Done, |
| 42539 | // Label 2331: @137167 |
| 42540 | GIM_Try, /*On fail goto*//*Label 2332*/ GIMT_Encode4(137223), // Rule ID 3471 // |
| 42541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42542 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42543 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42544 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 42546 | // (st p2:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 42548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 42549 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42554 | GIR_RootConstrainSelectedInstOperands, |
| 42555 | // GIR_Coverage, 3471, |
| 42556 | GIR_EraseRootFromParent_Done, |
| 42557 | // Label 2332: @137223 |
| 42558 | GIM_Try, /*On fail goto*//*Label 2333*/ GIMT_Encode4(137274), // Rule ID 3470 // |
| 42559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42560 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 42564 | // (st p2:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 42565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 42566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42567 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42571 | GIR_RootConstrainSelectedInstOperands, |
| 42572 | // GIR_Coverage, 3470, |
| 42573 | GIR_EraseRootFromParent_Done, |
| 42574 | // Label 2333: @137274 |
| 42575 | GIM_Try, /*On fail goto*//*Label 2334*/ GIMT_Encode4(137326), // Rule ID 3240 // |
| 42576 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 42577 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 42578 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42579 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 42581 | // (st p2:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 42582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 42583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42584 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42587 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42588 | GIR_RootConstrainSelectedInstOperands, |
| 42589 | // GIR_Coverage, 3240, |
| 42590 | GIR_EraseRootFromParent_Done, |
| 42591 | // Label 2334: @137326 |
| 42592 | GIM_Reject, |
| 42593 | // Label 2272: @137327 |
| 42594 | GIM_Try, /*On fail goto*//*Label 2335*/ GIMT_Encode4(137386), // Rule ID 6320 // |
| 42595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 42596 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 42600 | // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 42602 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42609 | GIR_RootConstrainSelectedInstOperands, |
| 42610 | // GIR_Coverage, 6320, |
| 42611 | GIR_EraseRootFromParent_Done, |
| 42612 | // Label 2335: @137386 |
| 42613 | GIM_Try, /*On fail goto*//*Label 2336*/ GIMT_Encode4(137445), // Rule ID 6322 // |
| 42614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 42615 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42616 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 42619 | // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 42621 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42628 | GIR_RootConstrainSelectedInstOperands, |
| 42629 | // GIR_Coverage, 6322, |
| 42630 | GIR_EraseRootFromParent_Done, |
| 42631 | // Label 2336: @137445 |
| 42632 | GIM_Try, /*On fail goto*//*Label 2337*/ GIMT_Encode4(137501), // Rule ID 3915 // |
| 42633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 42634 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42635 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 42638 | // (st p3:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 42640 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 42643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42646 | GIR_RootConstrainSelectedInstOperands, |
| 42647 | // GIR_Coverage, 3915, |
| 42648 | GIR_EraseRootFromParent_Done, |
| 42649 | // Label 2337: @137501 |
| 42650 | GIM_Try, /*On fail goto*//*Label 2338*/ GIMT_Encode4(137552), // Rule ID 3914 // |
| 42651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42652 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42653 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 42656 | // (st p3:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 42658 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42662 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42663 | GIR_RootConstrainSelectedInstOperands, |
| 42664 | // GIR_Coverage, 3914, |
| 42665 | GIR_EraseRootFromParent_Done, |
| 42666 | // Label 2338: @137552 |
| 42667 | GIM_Try, /*On fail goto*//*Label 2339*/ GIMT_Encode4(137603), // Rule ID 3913 // |
| 42668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42669 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42670 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42671 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 42673 | // (st p3:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 42674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 42675 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42679 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42680 | GIR_RootConstrainSelectedInstOperands, |
| 42681 | // GIR_Coverage, 3913, |
| 42682 | GIR_EraseRootFromParent_Done, |
| 42683 | // Label 2339: @137603 |
| 42684 | GIM_Try, /*On fail goto*//*Label 2340*/ GIMT_Encode4(137667), // Rule ID 4272 // |
| 42685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42686 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42687 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42690 | // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 42692 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42699 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42700 | GIR_RootConstrainSelectedInstOperands, |
| 42701 | // GIR_Coverage, 4272, |
| 42702 | GIR_EraseRootFromParent_Done, |
| 42703 | // Label 2340: @137667 |
| 42704 | GIM_Try, /*On fail goto*//*Label 2341*/ GIMT_Encode4(137728), // Rule ID 4274 // |
| 42705 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42706 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42707 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 42709 | // (st p3:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p3:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 42711 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42718 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42719 | GIR_RootConstrainSelectedInstOperands, |
| 42720 | // GIR_Coverage, 4274, |
| 42721 | GIR_EraseRootFromParent_Done, |
| 42722 | // Label 2341: @137728 |
| 42723 | GIM_Try, /*On fail goto*//*Label 2342*/ GIMT_Encode4(137792), // Rule ID 6319 // |
| 42724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 42725 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42726 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42727 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42728 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 42729 | // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 42731 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42738 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42739 | GIR_RootConstrainSelectedInstOperands, |
| 42740 | // GIR_Coverage, 6319, |
| 42741 | GIR_EraseRootFromParent_Done, |
| 42742 | // Label 2342: @137792 |
| 42743 | GIM_Try, /*On fail goto*//*Label 2343*/ GIMT_Encode4(137856), // Rule ID 6321 // |
| 42744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 42745 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42746 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42747 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 42749 | // (st p3:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 42750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 42751 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 42753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 42755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 42756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42759 | GIR_RootConstrainSelectedInstOperands, |
| 42760 | // GIR_Coverage, 6321, |
| 42761 | GIR_EraseRootFromParent_Done, |
| 42762 | // Label 2343: @137856 |
| 42763 | GIM_Try, /*On fail goto*//*Label 2344*/ GIMT_Encode4(137915), // Rule ID 4271 // |
| 42764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 42765 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42766 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42767 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42769 | // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 42771 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42778 | GIR_RootConstrainSelectedInstOperands, |
| 42779 | // GIR_Coverage, 4271, |
| 42780 | GIR_EraseRootFromParent_Done, |
| 42781 | // Label 2344: @137915 |
| 42782 | GIM_Try, /*On fail goto*//*Label 2345*/ GIMT_Encode4(137971), // Rule ID 4273 // |
| 42783 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42784 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 42787 | // (st p3:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 42788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 42789 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 42790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 42791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 42792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42796 | GIR_RootConstrainSelectedInstOperands, |
| 42797 | // GIR_Coverage, 4273, |
| 42798 | GIR_EraseRootFromParent_Done, |
| 42799 | // Label 2345: @137971 |
| 42800 | GIM_Try, /*On fail goto*//*Label 2346*/ GIMT_Encode4(138026), // Rule ID 7519 // |
| 42801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 42802 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42803 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42804 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42807 | // (AMDGPUst_glue p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 42809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42810 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42813 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42814 | GIR_RootConstrainSelectedInstOperands, |
| 42815 | // GIR_Coverage, 7519, |
| 42816 | GIR_EraseRootFromParent_Done, |
| 42817 | // Label 2346: @138026 |
| 42818 | GIM_Try, /*On fail goto*//*Label 2347*/ GIMT_Encode4(138077), // Rule ID 7520 // |
| 42819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 42820 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42821 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42822 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42824 | // (st p3:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 42826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42827 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42831 | GIR_RootConstrainSelectedInstOperands, |
| 42832 | // GIR_Coverage, 7520, |
| 42833 | GIR_EraseRootFromParent_Done, |
| 42834 | // Label 2347: @138077 |
| 42835 | GIM_Try, /*On fail goto*//*Label 2348*/ GIMT_Encode4(138133), // Rule ID 3475 // |
| 42836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42837 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42838 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42839 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 42841 | // (st p3:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 42843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 42844 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42849 | GIR_RootConstrainSelectedInstOperands, |
| 42850 | // GIR_Coverage, 3475, |
| 42851 | GIR_EraseRootFromParent_Done, |
| 42852 | // Label 2348: @138133 |
| 42853 | GIM_Try, /*On fail goto*//*Label 2349*/ GIMT_Encode4(138184), // Rule ID 3474 // |
| 42854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 42855 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 42856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 42859 | // (st p3:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 42860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 42861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42862 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42865 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42866 | GIR_RootConstrainSelectedInstOperands, |
| 42867 | // GIR_Coverage, 3474, |
| 42868 | GIR_EraseRootFromParent_Done, |
| 42869 | // Label 2349: @138184 |
| 42870 | GIM_Try, /*On fail goto*//*Label 2350*/ GIMT_Encode4(138236), // Rule ID 3242 // |
| 42871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 42872 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 42873 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42874 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 42876 | // (st p3:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 42877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 42878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42879 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42883 | GIR_RootConstrainSelectedInstOperands, |
| 42884 | // GIR_Coverage, 3242, |
| 42885 | GIR_EraseRootFromParent_Done, |
| 42886 | // Label 2350: @138236 |
| 42887 | GIM_Reject, |
| 42888 | // Label 2273: @138237 |
| 42889 | GIM_Try, /*On fail goto*//*Label 2351*/ GIMT_Encode4(138301), // Rule ID 7721 // |
| 42890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 42891 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42892 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42893 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42894 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42896 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 42897 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42898 | // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 42900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42901 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42904 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42905 | GIR_RootConstrainSelectedInstOperands, |
| 42906 | // GIR_Coverage, 7721, |
| 42907 | GIR_EraseRootFromParent_Done, |
| 42908 | // Label 2351: @138301 |
| 42909 | GIM_Try, /*On fail goto*//*Label 2352*/ GIMT_Encode4(138360), // Rule ID 7645 // |
| 42910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 42911 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 42912 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42913 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 42914 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42916 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42917 | // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 42919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42920 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42924 | GIR_RootConstrainSelectedInstOperands, |
| 42925 | // GIR_Coverage, 7645, |
| 42926 | GIR_EraseRootFromParent_Done, |
| 42927 | // Label 2352: @138360 |
| 42928 | GIM_Try, /*On fail goto*//*Label 2353*/ GIMT_Encode4(138420), // Rule ID 7722 // |
| 42929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 42930 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42931 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42932 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42933 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42934 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 42935 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42936 | // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 42938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42939 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42943 | GIR_RootConstrainSelectedInstOperands, |
| 42944 | // GIR_Coverage, 7722, |
| 42945 | GIR_EraseRootFromParent_Done, |
| 42946 | // Label 2353: @138420 |
| 42947 | GIM_Try, /*On fail goto*//*Label 2354*/ GIMT_Encode4(138475), // Rule ID 7646 // |
| 42948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 42949 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 42950 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 42951 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 42954 | // (st p4:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 42955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 42956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 42957 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 42958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42961 | GIR_RootConstrainSelectedInstOperands, |
| 42962 | // GIR_Coverage, 7646, |
| 42963 | GIR_EraseRootFromParent_Done, |
| 42964 | // Label 2354: @138475 |
| 42965 | GIM_Try, /*On fail goto*//*Label 2355*/ GIMT_Encode4(138531), // Rule ID 3987 // |
| 42966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 42967 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42968 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 42971 | // (st p4:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 42973 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 42975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 42976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 42977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42978 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42979 | GIR_RootConstrainSelectedInstOperands, |
| 42980 | // GIR_Coverage, 3987, |
| 42981 | GIR_EraseRootFromParent_Done, |
| 42982 | // Label 2355: @138531 |
| 42983 | GIM_Try, /*On fail goto*//*Label 2356*/ GIMT_Encode4(138582), // Rule ID 3986 // |
| 42984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 42985 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 42986 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 42987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 42988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 42989 | // (st p4:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 42990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 42991 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 42992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 42993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 42994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 42995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 42996 | GIR_RootConstrainSelectedInstOperands, |
| 42997 | // GIR_Coverage, 3986, |
| 42998 | GIR_EraseRootFromParent_Done, |
| 42999 | // Label 2356: @138582 |
| 43000 | GIM_Try, /*On fail goto*//*Label 2357*/ GIMT_Encode4(138633), // Rule ID 3985 // |
| 43001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43002 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43003 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 43006 | // (st p4:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 43007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 43008 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43013 | GIR_RootConstrainSelectedInstOperands, |
| 43014 | // GIR_Coverage, 3985, |
| 43015 | GIR_EraseRootFromParent_Done, |
| 43016 | // Label 2357: @138633 |
| 43017 | GIM_Try, /*On fail goto*//*Label 2358*/ GIMT_Encode4(138697), // Rule ID 4320 // |
| 43018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43020 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43023 | // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 43025 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43033 | GIR_RootConstrainSelectedInstOperands, |
| 43034 | // GIR_Coverage, 4320, |
| 43035 | GIR_EraseRootFromParent_Done, |
| 43036 | // Label 2358: @138697 |
| 43037 | GIM_Try, /*On fail goto*//*Label 2359*/ GIMT_Encode4(138758), // Rule ID 4322 // |
| 43038 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43040 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43042 | // (st p4:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 p4:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 43044 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43052 | GIR_RootConstrainSelectedInstOperands, |
| 43053 | // GIR_Coverage, 4322, |
| 43054 | GIR_EraseRootFromParent_Done, |
| 43055 | // Label 2359: @138758 |
| 43056 | GIM_Try, /*On fail goto*//*Label 2360*/ GIMT_Encode4(138878), // Rule ID 7580 // |
| 43057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 43058 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43059 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43060 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43061 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43062 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 43063 | // (AMDGPUst_glue p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 43064 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43065 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 43066 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43067 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43068 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 43069 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 43070 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 43071 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43072 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43073 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 43074 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 43075 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 43076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 43077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43078 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43079 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 43080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 43081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 43082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43084 | GIR_RootConstrainSelectedInstOperands, |
| 43085 | // GIR_Coverage, 7580, |
| 43086 | GIR_EraseRootFromParent_Done, |
| 43087 | // Label 2360: @138878 |
| 43088 | GIM_Try, /*On fail goto*//*Label 2361*/ GIMT_Encode4(138937), // Rule ID 4319 // |
| 43089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43090 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43091 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43092 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43093 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43094 | // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 43096 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43102 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43103 | GIR_RootConstrainSelectedInstOperands, |
| 43104 | // GIR_Coverage, 4319, |
| 43105 | GIR_EraseRootFromParent_Done, |
| 43106 | // Label 2361: @138937 |
| 43107 | GIM_Try, /*On fail goto*//*Label 2362*/ GIMT_Encode4(138993), // Rule ID 4321 // |
| 43108 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43109 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43112 | // (st p4:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET p4:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 43114 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43121 | GIR_RootConstrainSelectedInstOperands, |
| 43122 | // GIR_Coverage, 4321, |
| 43123 | GIR_EraseRootFromParent_Done, |
| 43124 | // Label 2362: @138993 |
| 43125 | GIM_Try, /*On fail goto*//*Label 2363*/ GIMT_Encode4(139109), // Rule ID 7582 // |
| 43126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 43127 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43128 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 43131 | // (st p4:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 43132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 43133 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 43134 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43135 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43136 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 43137 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 43138 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 43139 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 43140 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 43141 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 43142 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 43143 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 43144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 43145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43146 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 43147 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 43148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 43149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 43150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43151 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43152 | GIR_RootConstrainSelectedInstOperands, |
| 43153 | // GIR_Coverage, 7582, |
| 43154 | GIR_EraseRootFromParent_Done, |
| 43155 | // Label 2363: @139109 |
| 43156 | GIM_Try, /*On fail goto*//*Label 2364*/ GIMT_Encode4(139165), // Rule ID 3523 // |
| 43157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43158 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43159 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43160 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 43162 | // (st p4:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 43164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 43165 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43170 | GIR_RootConstrainSelectedInstOperands, |
| 43171 | // GIR_Coverage, 3523, |
| 43172 | GIR_EraseRootFromParent_Done, |
| 43173 | // Label 2364: @139165 |
| 43174 | GIM_Try, /*On fail goto*//*Label 2365*/ GIMT_Encode4(139216), // Rule ID 3522 // |
| 43175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43176 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43177 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 43180 | // (st p4:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 43181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 43182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43183 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43186 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43187 | GIR_RootConstrainSelectedInstOperands, |
| 43188 | // GIR_Coverage, 3522, |
| 43189 | GIR_EraseRootFromParent_Done, |
| 43190 | // Label 2365: @139216 |
| 43191 | GIM_Try, /*On fail goto*//*Label 2366*/ GIMT_Encode4(139268), // Rule ID 3265 // |
| 43192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 43193 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 43194 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 43197 | // (st p4:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 43198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 43199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43200 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43203 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43204 | GIR_RootConstrainSelectedInstOperands, |
| 43205 | // GIR_Coverage, 3265, |
| 43206 | GIR_EraseRootFromParent_Done, |
| 43207 | // Label 2366: @139268 |
| 43208 | GIM_Reject, |
| 43209 | // Label 2274: @139269 |
| 43210 | GIM_Try, /*On fail goto*//*Label 2367*/ GIMT_Encode4(139328), // Rule ID 6324 // |
| 43211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43212 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43213 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43214 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43216 | // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 43218 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43224 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43225 | GIR_RootConstrainSelectedInstOperands, |
| 43226 | // GIR_Coverage, 6324, |
| 43227 | GIR_EraseRootFromParent_Done, |
| 43228 | // Label 2367: @139328 |
| 43229 | GIM_Try, /*On fail goto*//*Label 2368*/ GIMT_Encode4(139387), // Rule ID 6326 // |
| 43230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43231 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43232 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43235 | // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 43237 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43243 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43244 | GIR_RootConstrainSelectedInstOperands, |
| 43245 | // GIR_Coverage, 6326, |
| 43246 | GIR_EraseRootFromParent_Done, |
| 43247 | // Label 2368: @139387 |
| 43248 | GIM_Try, /*On fail goto*//*Label 2369*/ GIMT_Encode4(139443), // Rule ID 3921 // |
| 43249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 43250 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43251 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43252 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43253 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 43254 | // (st p5:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 43256 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 43259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43261 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43262 | GIR_RootConstrainSelectedInstOperands, |
| 43263 | // GIR_Coverage, 3921, |
| 43264 | GIR_EraseRootFromParent_Done, |
| 43265 | // Label 2369: @139443 |
| 43266 | GIM_Try, /*On fail goto*//*Label 2370*/ GIMT_Encode4(139494), // Rule ID 3920 // |
| 43267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43268 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43269 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43270 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43271 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 43272 | // (st p5:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 43274 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43279 | GIR_RootConstrainSelectedInstOperands, |
| 43280 | // GIR_Coverage, 3920, |
| 43281 | GIR_EraseRootFromParent_Done, |
| 43282 | // Label 2370: @139494 |
| 43283 | GIM_Try, /*On fail goto*//*Label 2371*/ GIMT_Encode4(139545), // Rule ID 3919 // |
| 43284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43285 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43286 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 43289 | // (st p5:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 43290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 43291 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43296 | GIR_RootConstrainSelectedInstOperands, |
| 43297 | // GIR_Coverage, 3919, |
| 43298 | GIR_EraseRootFromParent_Done, |
| 43299 | // Label 2371: @139545 |
| 43300 | GIM_Try, /*On fail goto*//*Label 2372*/ GIMT_Encode4(139609), // Rule ID 4276 // |
| 43301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43302 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43303 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43306 | // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 43308 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43316 | GIR_RootConstrainSelectedInstOperands, |
| 43317 | // GIR_Coverage, 4276, |
| 43318 | GIR_EraseRootFromParent_Done, |
| 43319 | // Label 2372: @139609 |
| 43320 | GIM_Try, /*On fail goto*//*Label 2373*/ GIMT_Encode4(139670), // Rule ID 4278 // |
| 43321 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43322 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43325 | // (st p5:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p5:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 43327 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43335 | GIR_RootConstrainSelectedInstOperands, |
| 43336 | // GIR_Coverage, 4278, |
| 43337 | GIR_EraseRootFromParent_Done, |
| 43338 | // Label 2373: @139670 |
| 43339 | GIM_Try, /*On fail goto*//*Label 2374*/ GIMT_Encode4(139734), // Rule ID 6323 // |
| 43340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43341 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43342 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43343 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 43345 | // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 43347 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43354 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43355 | GIR_RootConstrainSelectedInstOperands, |
| 43356 | // GIR_Coverage, 6323, |
| 43357 | GIR_EraseRootFromParent_Done, |
| 43358 | // Label 2374: @139734 |
| 43359 | GIM_Try, /*On fail goto*//*Label 2375*/ GIMT_Encode4(139798), // Rule ID 6325 // |
| 43360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43361 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43362 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 43365 | // (st p5:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 43367 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43374 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43375 | GIR_RootConstrainSelectedInstOperands, |
| 43376 | // GIR_Coverage, 6325, |
| 43377 | GIR_EraseRootFromParent_Done, |
| 43378 | // Label 2375: @139798 |
| 43379 | GIM_Try, /*On fail goto*//*Label 2376*/ GIMT_Encode4(139857), // Rule ID 4275 // |
| 43380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43381 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43382 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43385 | // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 43387 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43394 | GIR_RootConstrainSelectedInstOperands, |
| 43395 | // GIR_Coverage, 4275, |
| 43396 | GIR_EraseRootFromParent_Done, |
| 43397 | // Label 2376: @139857 |
| 43398 | GIM_Try, /*On fail goto*//*Label 2377*/ GIMT_Encode4(139913), // Rule ID 4277 // |
| 43399 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43400 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43403 | // (st p5:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 43405 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43411 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43412 | GIR_RootConstrainSelectedInstOperands, |
| 43413 | // GIR_Coverage, 4277, |
| 43414 | GIR_EraseRootFromParent_Done, |
| 43415 | // Label 2377: @139913 |
| 43416 | GIM_Try, /*On fail goto*//*Label 2378*/ GIMT_Encode4(139968), // Rule ID 7521 // |
| 43417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 43418 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43419 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43420 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43421 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 43423 | // (AMDGPUst_glue p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 43424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 43425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43426 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43429 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43430 | GIR_RootConstrainSelectedInstOperands, |
| 43431 | // GIR_Coverage, 7521, |
| 43432 | GIR_EraseRootFromParent_Done, |
| 43433 | // Label 2378: @139968 |
| 43434 | GIM_Try, /*On fail goto*//*Label 2379*/ GIMT_Encode4(140019), // Rule ID 7522 // |
| 43435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 43436 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43437 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 43440 | // (st p5:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 43441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 43442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43443 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43447 | GIR_RootConstrainSelectedInstOperands, |
| 43448 | // GIR_Coverage, 7522, |
| 43449 | GIR_EraseRootFromParent_Done, |
| 43450 | // Label 2379: @140019 |
| 43451 | GIM_Try, /*On fail goto*//*Label 2380*/ GIMT_Encode4(140075), // Rule ID 3479 // |
| 43452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43453 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43454 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43455 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43456 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 43457 | // (st p5:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 43459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 43460 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43465 | GIR_RootConstrainSelectedInstOperands, |
| 43466 | // GIR_Coverage, 3479, |
| 43467 | GIR_EraseRootFromParent_Done, |
| 43468 | // Label 2380: @140075 |
| 43469 | GIM_Try, /*On fail goto*//*Label 2381*/ GIMT_Encode4(140126), // Rule ID 3478 // |
| 43470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43471 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43472 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43473 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 43475 | // (st p5:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 43476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 43477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43478 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43482 | GIR_RootConstrainSelectedInstOperands, |
| 43483 | // GIR_Coverage, 3478, |
| 43484 | GIR_EraseRootFromParent_Done, |
| 43485 | // Label 2381: @140126 |
| 43486 | GIM_Try, /*On fail goto*//*Label 2382*/ GIMT_Encode4(140178), // Rule ID 3244 // |
| 43487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 43488 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 43489 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 43492 | // (st p5:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 43493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 43494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43495 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43499 | GIR_RootConstrainSelectedInstOperands, |
| 43500 | // GIR_Coverage, 3244, |
| 43501 | GIR_EraseRootFromParent_Done, |
| 43502 | // Label 2382: @140178 |
| 43503 | GIM_Reject, |
| 43504 | // Label 2275: @140179 |
| 43505 | GIM_Try, /*On fail goto*//*Label 2383*/ GIMT_Encode4(140238), // Rule ID 6328 // |
| 43506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43507 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43508 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43509 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43510 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43511 | // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 43513 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43519 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43520 | GIR_RootConstrainSelectedInstOperands, |
| 43521 | // GIR_Coverage, 6328, |
| 43522 | GIR_EraseRootFromParent_Done, |
| 43523 | // Label 2383: @140238 |
| 43524 | GIM_Try, /*On fail goto*//*Label 2384*/ GIMT_Encode4(140297), // Rule ID 6330 // |
| 43525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43526 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43527 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43528 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43529 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43530 | // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 43532 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43538 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43539 | GIR_RootConstrainSelectedInstOperands, |
| 43540 | // GIR_Coverage, 6330, |
| 43541 | GIR_EraseRootFromParent_Done, |
| 43542 | // Label 2384: @140297 |
| 43543 | GIM_Try, /*On fail goto*//*Label 2385*/ GIMT_Encode4(140353), // Rule ID 3927 // |
| 43544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 43545 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43546 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43547 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 43549 | // (st p6:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 43551 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 43554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43557 | GIR_RootConstrainSelectedInstOperands, |
| 43558 | // GIR_Coverage, 3927, |
| 43559 | GIR_EraseRootFromParent_Done, |
| 43560 | // Label 2385: @140353 |
| 43561 | GIM_Try, /*On fail goto*//*Label 2386*/ GIMT_Encode4(140404), // Rule ID 3926 // |
| 43562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43563 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43564 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 43567 | // (st p6:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 43569 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43574 | GIR_RootConstrainSelectedInstOperands, |
| 43575 | // GIR_Coverage, 3926, |
| 43576 | GIR_EraseRootFromParent_Done, |
| 43577 | // Label 2386: @140404 |
| 43578 | GIM_Try, /*On fail goto*//*Label 2387*/ GIMT_Encode4(140455), // Rule ID 3925 // |
| 43579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43580 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43581 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43582 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 43584 | // (st p6:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 43585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 43586 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43590 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43591 | GIR_RootConstrainSelectedInstOperands, |
| 43592 | // GIR_Coverage, 3925, |
| 43593 | GIR_EraseRootFromParent_Done, |
| 43594 | // Label 2387: @140455 |
| 43595 | GIM_Try, /*On fail goto*//*Label 2388*/ GIMT_Encode4(140519), // Rule ID 4280 // |
| 43596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43597 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43598 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43601 | // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 43603 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43611 | GIR_RootConstrainSelectedInstOperands, |
| 43612 | // GIR_Coverage, 4280, |
| 43613 | GIR_EraseRootFromParent_Done, |
| 43614 | // Label 2388: @140519 |
| 43615 | GIM_Try, /*On fail goto*//*Label 2389*/ GIMT_Encode4(140580), // Rule ID 4282 // |
| 43616 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43617 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43618 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43619 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43620 | // (st p6:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 p6:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 43622 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43630 | GIR_RootConstrainSelectedInstOperands, |
| 43631 | // GIR_Coverage, 4282, |
| 43632 | GIR_EraseRootFromParent_Done, |
| 43633 | // Label 2389: @140580 |
| 43634 | GIM_Try, /*On fail goto*//*Label 2390*/ GIMT_Encode4(140644), // Rule ID 6327 // |
| 43635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43636 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43637 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43638 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43639 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 43640 | // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 43642 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43650 | GIR_RootConstrainSelectedInstOperands, |
| 43651 | // GIR_Coverage, 6327, |
| 43652 | GIR_EraseRootFromParent_Done, |
| 43653 | // Label 2390: @140644 |
| 43654 | GIM_Try, /*On fail goto*//*Label 2391*/ GIMT_Encode4(140708), // Rule ID 6329 // |
| 43655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43656 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43657 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 43660 | // (st p6:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 43662 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 43664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 43666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 43667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43670 | GIR_RootConstrainSelectedInstOperands, |
| 43671 | // GIR_Coverage, 6329, |
| 43672 | GIR_EraseRootFromParent_Done, |
| 43673 | // Label 2391: @140708 |
| 43674 | GIM_Try, /*On fail goto*//*Label 2392*/ GIMT_Encode4(140767), // Rule ID 4279 // |
| 43675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 43676 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43677 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43680 | // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 43682 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43689 | GIR_RootConstrainSelectedInstOperands, |
| 43690 | // GIR_Coverage, 4279, |
| 43691 | GIR_EraseRootFromParent_Done, |
| 43692 | // Label 2392: @140767 |
| 43693 | GIM_Try, /*On fail goto*//*Label 2393*/ GIMT_Encode4(140823), // Rule ID 4281 // |
| 43694 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 43698 | // (st p6:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 43699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 43700 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 43701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43707 | GIR_RootConstrainSelectedInstOperands, |
| 43708 | // GIR_Coverage, 4281, |
| 43709 | GIR_EraseRootFromParent_Done, |
| 43710 | // Label 2393: @140823 |
| 43711 | GIM_Try, /*On fail goto*//*Label 2394*/ GIMT_Encode4(140878), // Rule ID 7523 // |
| 43712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 43713 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43714 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 43718 | // (AMDGPUst_glue p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 43719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 43720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43721 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43724 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43725 | GIR_RootConstrainSelectedInstOperands, |
| 43726 | // GIR_Coverage, 7523, |
| 43727 | GIR_EraseRootFromParent_Done, |
| 43728 | // Label 2394: @140878 |
| 43729 | GIM_Try, /*On fail goto*//*Label 2395*/ GIMT_Encode4(140929), // Rule ID 7524 // |
| 43730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 43731 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 43732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43734 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 43735 | // (st p6:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 43736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 43737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 43738 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43742 | GIR_RootConstrainSelectedInstOperands, |
| 43743 | // GIR_Coverage, 7524, |
| 43744 | GIR_EraseRootFromParent_Done, |
| 43745 | // Label 2395: @140929 |
| 43746 | GIM_Try, /*On fail goto*//*Label 2396*/ GIMT_Encode4(140985), // Rule ID 3483 // |
| 43747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43748 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43749 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 43752 | // (st p6:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 43754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 43755 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43760 | GIR_RootConstrainSelectedInstOperands, |
| 43761 | // GIR_Coverage, 3483, |
| 43762 | GIR_EraseRootFromParent_Done, |
| 43763 | // Label 2396: @140985 |
| 43764 | GIM_Try, /*On fail goto*//*Label 2397*/ GIMT_Encode4(141036), // Rule ID 3482 // |
| 43765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 43766 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43767 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43768 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43769 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 43770 | // (st p6:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 43771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 43772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43773 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43776 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43777 | GIR_RootConstrainSelectedInstOperands, |
| 43778 | // GIR_Coverage, 3482, |
| 43779 | GIR_EraseRootFromParent_Done, |
| 43780 | // Label 2397: @141036 |
| 43781 | GIM_Try, /*On fail goto*//*Label 2398*/ GIMT_Encode4(141088), // Rule ID 3246 // |
| 43782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 43783 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 43784 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43785 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 43787 | // (st p6:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 43788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 43789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43790 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43794 | GIR_RootConstrainSelectedInstOperands, |
| 43795 | // GIR_Coverage, 3246, |
| 43796 | GIR_EraseRootFromParent_Done, |
| 43797 | // Label 2398: @141088 |
| 43798 | GIM_Reject, |
| 43799 | // Label 2276: @141089 |
| 43800 | GIM_Try, /*On fail goto*//*Label 2399*/ GIMT_Encode4(141159), // Rule ID 6288 // |
| 43801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43802 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43803 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43804 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43805 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43806 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43808 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET), |
| 43810 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43817 | GIR_RootConstrainSelectedInstOperands, |
| 43818 | // GIR_Coverage, 6288, |
| 43819 | GIR_EraseRootFromParent_Done, |
| 43820 | // Label 2399: @141159 |
| 43821 | GIM_Try, /*On fail goto*//*Label 2400*/ GIMT_Encode4(141229), // Rule ID 6290 // |
| 43822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43823 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43824 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43825 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43826 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43829 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET), |
| 43831 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43838 | GIR_RootConstrainSelectedInstOperands, |
| 43839 | // GIR_Coverage, 6290, |
| 43840 | GIR_EraseRootFromParent_Done, |
| 43841 | // Label 2400: @141229 |
| 43842 | GIM_Try, /*On fail goto*//*Label 2401*/ GIMT_Encode4(141288), // Rule ID 6292 // |
| 43843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 43844 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43848 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET), |
| 43850 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43857 | GIR_RootConstrainSelectedInstOperands, |
| 43858 | // GIR_Coverage, 6292, |
| 43859 | GIR_EraseRootFromParent_Done, |
| 43860 | // Label 2401: @141288 |
| 43861 | GIM_Try, /*On fail goto*//*Label 2402*/ GIMT_Encode4(141347), // Rule ID 6294 // |
| 43862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 43863 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43864 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 43867 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 43868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET), |
| 43869 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 43870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 43871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 43872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43875 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43876 | GIR_RootConstrainSelectedInstOperands, |
| 43877 | // GIR_Coverage, 6294, |
| 43878 | GIR_EraseRootFromParent_Done, |
| 43879 | // Label 2402: @141347 |
| 43880 | GIM_Try, /*On fail goto*//*Label 2403*/ GIMT_Encode4(141414), // Rule ID 4038 // |
| 43881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 43882 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43883 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43884 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43885 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 43888 | // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE_SVS anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS), |
| 43890 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 43893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43895 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43896 | GIR_RootConstrainSelectedInstOperands, |
| 43897 | // GIR_Coverage, 4038, |
| 43898 | GIR_EraseRootFromParent_Done, |
| 43899 | // Label 2403: @141414 |
| 43900 | GIM_Try, /*On fail goto*//*Label 2404*/ GIMT_Encode4(141470), // Rule ID 4044 // |
| 43901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 43902 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43903 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43904 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 43906 | // (st i16:{ *:[i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_SHORT_SVS anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS), |
| 43908 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 43911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 43912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43913 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43914 | GIR_RootConstrainSelectedInstOperands, |
| 43915 | // GIR_Coverage, 4044, |
| 43916 | GIR_EraseRootFromParent_Done, |
| 43917 | // Label 2404: @141470 |
| 43918 | GIM_Try, /*On fail goto*//*Label 2405*/ GIMT_Encode4(141532), // Rule ID 4037 // |
| 43919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43920 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43921 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43922 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43923 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43924 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 43926 | // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE_SADDR anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR), |
| 43928 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43932 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43933 | GIR_RootConstrainSelectedInstOperands, |
| 43934 | // GIR_Coverage, 4037, |
| 43935 | GIR_EraseRootFromParent_Done, |
| 43936 | // Label 2405: @141532 |
| 43937 | GIM_Try, /*On fail goto*//*Label 2406*/ GIMT_Encode4(141583), // Rule ID 4043 // |
| 43938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43939 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43940 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43941 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 43943 | // (st i16:{ *:[i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_SHORT_SADDR anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 43944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR), |
| 43945 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 43947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43950 | GIR_RootConstrainSelectedInstOperands, |
| 43951 | // GIR_Coverage, 4043, |
| 43952 | GIR_EraseRootFromParent_Done, |
| 43953 | // Label 2406: @141583 |
| 43954 | GIM_Try, /*On fail goto*//*Label 2407*/ GIMT_Encode4(141645), // Rule ID 4036 // |
| 43955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43956 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 43957 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43958 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43959 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 43962 | // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 43963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE), |
| 43964 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43969 | GIR_RootConstrainSelectedInstOperands, |
| 43970 | // GIR_Coverage, 4036, |
| 43971 | GIR_EraseRootFromParent_Done, |
| 43972 | // Label 2407: @141645 |
| 43973 | GIM_Try, /*On fail goto*//*Label 2408*/ GIMT_Encode4(141696), // Rule ID 4042 // |
| 43974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 43975 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 43976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 43977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 43979 | // (st i16:{ *:[i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_SHORT anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 43980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT), |
| 43981 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 43982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 43983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 43984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 43985 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 43986 | GIR_RootConstrainSelectedInstOperands, |
| 43987 | // GIR_Coverage, 4042, |
| 43988 | GIR_EraseRootFromParent_Done, |
| 43989 | // Label 2408: @141696 |
| 43990 | GIM_Try, /*On fail goto*//*Label 2409*/ GIMT_Encode4(141767), // Rule ID 6265 // |
| 43991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 43992 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 43993 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 43994 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 43995 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 43996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 43997 | // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 43998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64), |
| 43999 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 44000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44006 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44007 | GIR_RootConstrainSelectedInstOperands, |
| 44008 | // GIR_Coverage, 6265, |
| 44009 | GIR_EraseRootFromParent_Done, |
| 44010 | // Label 2409: @141767 |
| 44011 | GIM_Try, /*On fail goto*//*Label 2410*/ GIMT_Encode4(141838), // Rule ID 6269 // |
| 44012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 44013 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44014 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44015 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44016 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44017 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 44018 | // (atomic_store i16:{ *:[i16] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i16] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 44019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64), |
| 44020 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 44021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44027 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44028 | GIR_RootConstrainSelectedInstOperands, |
| 44029 | // GIR_Coverage, 6269, |
| 44030 | GIR_EraseRootFromParent_Done, |
| 44031 | // Label 2410: @141838 |
| 44032 | GIM_Try, /*On fail goto*//*Label 2411*/ GIMT_Encode4(141913), // Rule ID 6287 // |
| 44033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 44034 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44035 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44036 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44037 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44038 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44040 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN), |
| 44042 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44049 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44050 | GIR_RootConstrainSelectedInstOperands, |
| 44051 | // GIR_Coverage, 6287, |
| 44052 | GIR_EraseRootFromParent_Done, |
| 44053 | // Label 2411: @141913 |
| 44054 | GIM_Try, /*On fail goto*//*Label 2412*/ GIMT_Encode4(141988), // Rule ID 6289 // |
| 44055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 44056 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44057 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44058 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44059 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44060 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44061 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44062 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN), |
| 44064 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44072 | GIR_RootConstrainSelectedInstOperands, |
| 44073 | // GIR_Coverage, 6289, |
| 44074 | GIR_EraseRootFromParent_Done, |
| 44075 | // Label 2412: @141988 |
| 44076 | GIM_Try, /*On fail goto*//*Label 2413*/ GIMT_Encode4(142052), // Rule ID 6291 // |
| 44077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 44078 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44079 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44080 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44082 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN), |
| 44084 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44091 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44092 | GIR_RootConstrainSelectedInstOperands, |
| 44093 | // GIR_Coverage, 6291, |
| 44094 | GIR_EraseRootFromParent_Done, |
| 44095 | // Label 2413: @142052 |
| 44096 | GIM_Try, /*On fail goto*//*Label 2414*/ GIMT_Encode4(142116), // Rule ID 6293 // |
| 44097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 44098 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44099 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44100 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44102 | // (st i16:{ *:[i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN), |
| 44104 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44111 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44112 | GIR_RootConstrainSelectedInstOperands, |
| 44113 | // GIR_Coverage, 6293, |
| 44114 | GIR_EraseRootFromParent_Done, |
| 44115 | // Label 2414: @142116 |
| 44116 | GIM_Try, /*On fail goto*//*Label 2415*/ GIMT_Encode4(142186), // Rule ID 6275 // |
| 44117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 44118 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44119 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44120 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44121 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 44124 | // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 44125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET), |
| 44126 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 44127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44132 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44133 | GIR_RootConstrainSelectedInstOperands, |
| 44134 | // GIR_Coverage, 6275, |
| 44135 | GIR_EraseRootFromParent_Done, |
| 44136 | // Label 2415: @142186 |
| 44137 | GIM_Try, /*On fail goto*//*Label 2416*/ GIMT_Encode4(142253), // Rule ID 6276 // |
| 44138 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44139 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44140 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44141 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 44144 | // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 44145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET), |
| 44146 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 44147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44153 | GIR_RootConstrainSelectedInstOperands, |
| 44154 | // GIR_Coverage, 6276, |
| 44155 | GIR_EraseRootFromParent_Done, |
| 44156 | // Label 2416: @142253 |
| 44157 | GIM_Try, /*On fail goto*//*Label 2417*/ GIMT_Encode4(142312), // Rule ID 6277 // |
| 44158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 44159 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44160 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 44163 | // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_SHORT_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 44164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET), |
| 44165 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 44166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44172 | GIR_RootConstrainSelectedInstOperands, |
| 44173 | // GIR_Coverage, 6277, |
| 44174 | GIR_EraseRootFromParent_Done, |
| 44175 | // Label 2417: @142312 |
| 44176 | GIM_Try, /*On fail goto*//*Label 2418*/ GIMT_Encode4(142368), // Rule ID 6278 // |
| 44177 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44178 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 44181 | // (st i16:{ *:[i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_SHORT_VBUFFER_OFFSET ?:{ *:[i16] }:$vdata, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 44182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET), |
| 44183 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 44184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44189 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44190 | GIR_RootConstrainSelectedInstOperands, |
| 44191 | // GIR_Coverage, 6278, |
| 44192 | GIR_EraseRootFromParent_Done, |
| 44193 | // Label 2418: @142368 |
| 44194 | GIM_Try, /*On fail goto*//*Label 2419*/ GIMT_Encode4(142426), // Rule ID 7525 // |
| 44195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 44196 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44197 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44198 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44199 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44201 | // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>> => (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8), |
| 44203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44204 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44207 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44208 | GIR_RootConstrainSelectedInstOperands, |
| 44209 | // GIR_Coverage, 7525, |
| 44210 | GIR_EraseRootFromParent_Done, |
| 44211 | // Label 2419: @142426 |
| 44212 | GIM_Try, /*On fail goto*//*Label 2420*/ GIMT_Encode4(142484), // Rule ID 7526 // |
| 44213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 44214 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44215 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44216 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44219 | // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>> => (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9), |
| 44221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44222 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44225 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44226 | GIR_RootConstrainSelectedInstOperands, |
| 44227 | // GIR_Coverage, 7526, |
| 44228 | GIR_EraseRootFromParent_Done, |
| 44229 | // Label 2420: @142484 |
| 44230 | GIM_Try, /*On fail goto*//*Label 2421*/ GIMT_Encode4(142542), // Rule ID 7529 // |
| 44231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 44232 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44233 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44234 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44236 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44237 | // (AMDGPUatomic_st_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>> => (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16), |
| 44239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44240 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44243 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44244 | GIR_RootConstrainSelectedInstOperands, |
| 44245 | // GIR_Coverage, 7529, |
| 44246 | GIR_EraseRootFromParent_Done, |
| 44247 | // Label 2421: @142542 |
| 44248 | GIM_Try, /*On fail goto*//*Label 2422*/ GIMT_Encode4(142600), // Rule ID 7530 // |
| 44249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 44250 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44251 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44252 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44253 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44254 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44255 | // (atomic_store i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>> => (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9), |
| 44257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44258 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44261 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44262 | GIR_RootConstrainSelectedInstOperands, |
| 44263 | // GIR_Coverage, 7530, |
| 44264 | GIR_EraseRootFromParent_Done, |
| 44265 | // Label 2422: @142600 |
| 44266 | GIM_Try, /*On fail goto*//*Label 2423*/ GIMT_Encode4(142662), // Rule ID 7503 // |
| 44267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 44268 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44269 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44270 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44271 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44272 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44274 | // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>> => (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8), |
| 44276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44277 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44281 | GIR_RootConstrainSelectedInstOperands, |
| 44282 | // GIR_Coverage, 7503, |
| 44283 | GIR_EraseRootFromParent_Done, |
| 44284 | // Label 2423: @142662 |
| 44285 | GIM_Try, /*On fail goto*//*Label 2424*/ GIMT_Encode4(142724), // Rule ID 7504 // |
| 44286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 44287 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44288 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44289 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44290 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44293 | // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>> => (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9), |
| 44295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44296 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44300 | GIR_RootConstrainSelectedInstOperands, |
| 44301 | // GIR_Coverage, 7504, |
| 44302 | GIR_EraseRootFromParent_Done, |
| 44303 | // Label 2424: @142724 |
| 44304 | GIM_Try, /*On fail goto*//*Label 2425*/ GIMT_Encode4(142779), // Rule ID 7505 // |
| 44305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 44306 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44307 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44308 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44309 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44310 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44311 | // (AMDGPUst_glue i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16), |
| 44313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44314 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44317 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44318 | GIR_RootConstrainSelectedInstOperands, |
| 44319 | // GIR_Coverage, 7505, |
| 44320 | GIR_EraseRootFromParent_Done, |
| 44321 | // Label 2425: @142779 |
| 44322 | GIM_Try, /*On fail goto*//*Label 2426*/ GIMT_Encode4(142830), // Rule ID 7506 // |
| 44323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 44324 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 44325 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44326 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 44328 | // (st i16:{ *:[i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 44329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9), |
| 44330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 44331 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44334 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44335 | GIR_RootConstrainSelectedInstOperands, |
| 44336 | // GIR_Coverage, 7506, |
| 44337 | GIR_EraseRootFromParent_Done, |
| 44338 | // Label 2426: @142830 |
| 44339 | GIM_Try, /*On fail goto*//*Label 2427*/ GIMT_Encode4(142893), // Rule ID 3597 // |
| 44340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44342 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44343 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44344 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 44346 | // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR), |
| 44348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 44349 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44354 | GIR_RootConstrainSelectedInstOperands, |
| 44355 | // GIR_Coverage, 3597, |
| 44356 | GIR_EraseRootFromParent_Done, |
| 44357 | // Label 2427: @142893 |
| 44358 | GIM_Try, /*On fail goto*//*Label 2428*/ GIMT_Encode4(142956), // Rule ID 3601 // |
| 44359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44360 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44361 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44362 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 44365 | // (atomic_store i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR), |
| 44367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 44368 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44373 | GIR_RootConstrainSelectedInstOperands, |
| 44374 | // GIR_Coverage, 3601, |
| 44375 | GIR_EraseRootFromParent_Done, |
| 44376 | // Label 2428: @142956 |
| 44377 | GIM_Try, /*On fail goto*//*Label 2429*/ GIMT_Encode4(143023), // Rule ID 3561 // |
| 44378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44379 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44380 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44381 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44382 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 44385 | // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR), |
| 44387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 44388 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44392 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44393 | GIR_RootConstrainSelectedInstOperands, |
| 44394 | // GIR_Coverage, 3561, |
| 44395 | GIR_EraseRootFromParent_Done, |
| 44396 | // Label 2429: @143023 |
| 44397 | GIM_Try, /*On fail goto*//*Label 2430*/ GIMT_Encode4(143079), // Rule ID 3565 // |
| 44398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44399 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44400 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 44403 | // (st i16:{ *:[i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR), |
| 44405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 44406 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44410 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44411 | GIR_RootConstrainSelectedInstOperands, |
| 44412 | // GIR_Coverage, 3565, |
| 44413 | GIR_EraseRootFromParent_Done, |
| 44414 | // Label 2430: @143079 |
| 44415 | GIM_Try, /*On fail goto*//*Label 2431*/ GIMT_Encode4(143137), // Rule ID 3596 // |
| 44416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44417 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44418 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44419 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 44422 | // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE), |
| 44424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44425 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44428 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44429 | GIR_RootConstrainSelectedInstOperands, |
| 44430 | // GIR_Coverage, 3596, |
| 44431 | GIR_EraseRootFromParent_Done, |
| 44432 | // Label 2431: @143137 |
| 44433 | GIM_Try, /*On fail goto*//*Label 2432*/ GIMT_Encode4(143195), // Rule ID 3600 // |
| 44434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44435 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44436 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44437 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 44440 | // (atomic_store i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT), |
| 44442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44443 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44447 | GIR_RootConstrainSelectedInstOperands, |
| 44448 | // GIR_Coverage, 3600, |
| 44449 | GIR_EraseRootFromParent_Done, |
| 44450 | // Label 2432: @143195 |
| 44451 | GIM_Try, /*On fail goto*//*Label 2433*/ GIMT_Encode4(143257), // Rule ID 3560 // |
| 44452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44453 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44454 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44455 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44456 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 44459 | // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE), |
| 44461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44462 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44466 | GIR_RootConstrainSelectedInstOperands, |
| 44467 | // GIR_Coverage, 3560, |
| 44468 | GIR_EraseRootFromParent_Done, |
| 44469 | // Label 2433: @143257 |
| 44470 | GIM_Try, /*On fail goto*//*Label 2434*/ GIMT_Encode4(143308), // Rule ID 3564 // |
| 44471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 44472 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 44473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 44476 | // (st i16:{ *:[i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT), |
| 44478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44479 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44483 | GIR_RootConstrainSelectedInstOperands, |
| 44484 | // GIR_Coverage, 3564, |
| 44485 | GIR_EraseRootFromParent_Done, |
| 44486 | // Label 2434: @143308 |
| 44487 | GIM_Try, /*On fail goto*//*Label 2435*/ GIMT_Encode4(143367), // Rule ID 3285 // |
| 44488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 44489 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44490 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 44491 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44492 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44493 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 44494 | // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>> => (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE), |
| 44496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44497 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44501 | GIR_RootConstrainSelectedInstOperands, |
| 44502 | // GIR_Coverage, 3285, |
| 44503 | GIR_EraseRootFromParent_Done, |
| 44504 | // Label 2435: @143367 |
| 44505 | GIM_Try, /*On fail goto*//*Label 2436*/ GIMT_Encode4(143426), // Rule ID 3287 // |
| 44506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 44507 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44508 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 44509 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 44510 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 44512 | // (atomic_store i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>> => (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT), |
| 44514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44515 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44518 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44519 | GIR_RootConstrainSelectedInstOperands, |
| 44520 | // GIR_Coverage, 3287, |
| 44521 | GIR_EraseRootFromParent_Done, |
| 44522 | // Label 2436: @143426 |
| 44523 | GIM_Try, /*On fail goto*//*Label 2437*/ GIMT_Encode4(143489), // Rule ID 3408 // |
| 44524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 44525 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44526 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44527 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 44528 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44529 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 44531 | // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>> => (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE), |
| 44533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44534 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44537 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44538 | GIR_RootConstrainSelectedInstOperands, |
| 44539 | // GIR_Coverage, 3408, |
| 44540 | GIR_EraseRootFromParent_Done, |
| 44541 | // Label 2437: @143489 |
| 44542 | GIM_Try, /*On fail goto*//*Label 2438*/ GIMT_Encode4(143541), // Rule ID 3409 // |
| 44543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 44544 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 44545 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44546 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44547 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 44548 | // (st i16:{ *:[i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i16] }:$data, ?:{ *:[i32] }:$offset) |
| 44549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT), |
| 44550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44551 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 44552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44555 | GIR_RootConstrainSelectedInstOperands, |
| 44556 | // GIR_Coverage, 3409, |
| 44557 | GIR_EraseRootFromParent_Done, |
| 44558 | // Label 2438: @143541 |
| 44559 | GIM_Reject, |
| 44560 | // Label 2277: @143542 |
| 44561 | GIM_Try, /*On fail goto*//*Label 2439*/ GIMT_Encode4(143637), // Rule ID 6344 // |
| 44562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset), |
| 44563 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44564 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44565 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44566 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44570 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44571 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44572 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44573 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44575 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>> => (BUFFER_STORE_SHORT_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFSET), |
| 44577 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44583 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44584 | GIR_RootConstrainSelectedInstOperands, |
| 44585 | // GIR_Coverage, 6344, |
| 44586 | GIR_EraseRootFromParent_Done, |
| 44587 | // Label 2439: @143637 |
| 44588 | GIM_Try, /*On fail goto*//*Label 2440*/ GIMT_Encode4(143732), // Rule ID 6346 // |
| 44589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore), |
| 44590 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44591 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44592 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44593 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44594 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44595 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44596 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44597 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44598 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44600 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44601 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44602 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>> => (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFSET), |
| 44604 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44611 | GIR_RootConstrainSelectedInstOperands, |
| 44612 | // GIR_Coverage, 6346, |
| 44613 | GIR_EraseRootFromParent_Done, |
| 44614 | // Label 2440: @143732 |
| 44615 | GIM_Try, /*On fail goto*//*Label 2441*/ GIMT_Encode4(143827), // Rule ID 6348 // |
| 44616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset), |
| 44617 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44618 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44619 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44620 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44622 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44624 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44625 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44626 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44627 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44628 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44629 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (BUFFER_STORE_BYTE_D16_HI_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFSET), |
| 44631 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44637 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44638 | GIR_RootConstrainSelectedInstOperands, |
| 44639 | // GIR_Coverage, 6348, |
| 44640 | GIR_EraseRootFromParent_Done, |
| 44641 | // Label 2441: @143827 |
| 44642 | GIM_Try, /*On fail goto*//*Label 2442*/ GIMT_Encode4(143922), // Rule ID 6350 // |
| 44643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore), |
| 44644 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44645 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44646 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44647 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44652 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44654 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44656 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFSET), |
| 44658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44665 | GIR_RootConstrainSelectedInstOperands, |
| 44666 | // GIR_Coverage, 6350, |
| 44667 | GIR_EraseRootFromParent_Done, |
| 44668 | // Label 2442: @143922 |
| 44669 | GIM_Try, /*On fail goto*//*Label 2443*/ GIMT_Encode4(144014), // Rule ID 4050 // |
| 44670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 44671 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44672 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44673 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44675 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44676 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44677 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44678 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44679 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44680 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44681 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44682 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 44683 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>> => (SCRATCH_STORE_SHORT_D16_HI_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SVS), |
| 44685 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 44688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44690 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44691 | GIR_RootConstrainSelectedInstOperands, |
| 44692 | // GIR_Coverage, 4050, |
| 44693 | GIR_EraseRootFromParent_Done, |
| 44694 | // Label 2443: @144014 |
| 44695 | GIM_Try, /*On fail goto*//*Label 2444*/ GIMT_Encode4(144106), // Rule ID 4053 // |
| 44696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 44697 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44698 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44699 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44700 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44701 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44702 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44703 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44704 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44705 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44706 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44707 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 44709 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (SCRATCH_STORE_BYTE_D16_HI_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SVS), |
| 44711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 44714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44717 | GIR_RootConstrainSelectedInstOperands, |
| 44718 | // GIR_Coverage, 4053, |
| 44719 | GIR_EraseRootFromParent_Done, |
| 44720 | // Label 2444: @144106 |
| 44721 | GIM_Try, /*On fail goto*//*Label 2445*/ GIMT_Encode4(144193), // Rule ID 4049 // |
| 44722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts), |
| 44723 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44724 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44725 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44726 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44727 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44728 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44729 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44730 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44731 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44733 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44734 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 44735 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>> => (SCRATCH_STORE_SHORT_D16_HI_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI_SADDR), |
| 44737 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44742 | GIR_RootConstrainSelectedInstOperands, |
| 44743 | // GIR_Coverage, 4049, |
| 44744 | GIR_EraseRootFromParent_Done, |
| 44745 | // Label 2445: @144193 |
| 44746 | GIM_Try, /*On fail goto*//*Label 2446*/ GIMT_Encode4(144280), // Rule ID 4052 // |
| 44747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts), |
| 44748 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44749 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44750 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44751 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44753 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44754 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44755 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44756 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44758 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44759 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 44760 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (SCRATCH_STORE_BYTE_D16_HI_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 44761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI_SADDR), |
| 44762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 44764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44766 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44767 | GIR_RootConstrainSelectedInstOperands, |
| 44768 | // GIR_Coverage, 4052, |
| 44769 | GIR_EraseRootFromParent_Done, |
| 44770 | // Label 2446: @144280 |
| 44771 | GIM_Try, /*On fail goto*//*Label 2447*/ GIMT_Encode4(144367), // Rule ID 4048 // |
| 44772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts), |
| 44773 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44774 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44775 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44776 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44777 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44778 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44779 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44780 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44781 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44782 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44783 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 44785 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_private>> => (SCRATCH_STORE_SHORT_D16_HI anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 44786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_D16_HI), |
| 44787 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44791 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44792 | GIR_RootConstrainSelectedInstOperands, |
| 44793 | // GIR_Coverage, 4048, |
| 44794 | GIR_EraseRootFromParent_Done, |
| 44795 | // Label 2447: @144367 |
| 44796 | GIM_Try, /*On fail goto*//*Label 2448*/ GIMT_Encode4(144454), // Rule ID 4051 // |
| 44797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasD16LoadStore_HasFlatScratchInsts), |
| 44798 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44799 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44800 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44801 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44802 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44803 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44804 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44805 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44806 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44807 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44808 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 44810 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (SCRATCH_STORE_BYTE_D16_HI anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 44811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_D16_HI), |
| 44812 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 44813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 44814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 44815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44817 | GIR_RootConstrainSelectedInstOperands, |
| 44818 | // GIR_Coverage, 4051, |
| 44819 | GIR_EraseRootFromParent_Done, |
| 44820 | // Label 2448: @144454 |
| 44821 | GIM_Try, /*On fail goto*//*Label 2449*/ GIMT_Encode4(144554), // Rule ID 6343 // |
| 44822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset), |
| 44823 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44824 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44825 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44826 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44827 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44828 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44829 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44830 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44831 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44832 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44834 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44835 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>> => (BUFFER_STORE_SHORT_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_OFFEN), |
| 44837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44845 | GIR_RootConstrainSelectedInstOperands, |
| 44846 | // GIR_Coverage, 6343, |
| 44847 | GIR_EraseRootFromParent_Done, |
| 44848 | // Label 2449: @144554 |
| 44849 | GIM_Try, /*On fail goto*//*Label 2450*/ GIMT_Encode4(144654), // Rule ID 6345 // |
| 44850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore), |
| 44851 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44852 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44853 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44854 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44855 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44856 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44857 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44858 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44859 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44860 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44861 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44862 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44863 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_private>> => (BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_D16_HI_VBUFFER_OFFEN), |
| 44865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44873 | GIR_RootConstrainSelectedInstOperands, |
| 44874 | // GIR_Coverage, 6345, |
| 44875 | GIR_EraseRootFromParent_Done, |
| 44876 | // Label 2450: @144654 |
| 44877 | GIM_Try, /*On fail goto*//*Label 2451*/ GIMT_Encode4(144754), // Rule ID 6347 // |
| 44878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore_HasUnrestrictedSOffset), |
| 44879 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44880 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44881 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44882 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44884 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44885 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44886 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44887 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44888 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44889 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44891 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (BUFFER_STORE_BYTE_D16_HI_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_OFFEN), |
| 44893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44900 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44901 | GIR_RootConstrainSelectedInstOperands, |
| 44902 | // GIR_Coverage, 6347, |
| 44903 | GIR_EraseRootFromParent_Done, |
| 44904 | // Label 2451: @144754 |
| 44905 | GIM_Try, /*On fail goto*//*Label 2452*/ GIMT_Encode4(144854), // Rule ID 6349 // |
| 44906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasD16LoadStore), |
| 44907 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44908 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44909 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44910 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44911 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 44912 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 44913 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 44914 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 44915 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 44916 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44917 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 44918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 44919 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_private>> => (BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_D16_HI_VBUFFER_OFFEN), |
| 44921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 44922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 44923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 44925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 44926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 44929 | GIR_RootConstrainSelectedInstOperands, |
| 44930 | // GIR_Coverage, 6349, |
| 44931 | GIR_EraseRootFromParent_Done, |
| 44932 | // Label 2452: @144854 |
| 44933 | GIM_Try, /*On fail goto*//*Label 2453*/ GIMT_Encode4(144924), // Rule ID 6280 // |
| 44934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 44935 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44936 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44937 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44938 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44939 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44941 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET), |
| 44943 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44950 | GIR_RootConstrainSelectedInstOperands, |
| 44951 | // GIR_Coverage, 6280, |
| 44952 | GIR_EraseRootFromParent_Done, |
| 44953 | // Label 2453: @144924 |
| 44954 | GIM_Try, /*On fail goto*//*Label 2454*/ GIMT_Encode4(144994), // Rule ID 6282 // |
| 44955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 44956 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44957 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 44958 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44959 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44962 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET), |
| 44964 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44971 | GIR_RootConstrainSelectedInstOperands, |
| 44972 | // GIR_Coverage, 6282, |
| 44973 | GIR_EraseRootFromParent_Done, |
| 44974 | // Label 2454: @144994 |
| 44975 | GIM_Try, /*On fail goto*//*Label 2455*/ GIMT_Encode4(145064), // Rule ID 6284 // |
| 44976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 44977 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44978 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 44979 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 44980 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 44981 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 44982 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 44983 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (BUFFER_STORE_SHORT_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 44984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET), |
| 44985 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 44986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 44987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 44988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 44989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 44991 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 44992 | GIR_RootConstrainSelectedInstOperands, |
| 44993 | // GIR_Coverage, 6284, |
| 44994 | GIR_EraseRootFromParent_Done, |
| 44995 | // Label 2455: @145064 |
| 44996 | GIM_Try, /*On fail goto*//*Label 2456*/ GIMT_Encode4(145134), // Rule ID 6286 // |
| 44997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 44998 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 44999 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45000 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45001 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45003 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 45004 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (BUFFER_STORE_SHORT_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET), |
| 45006 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45013 | GIR_RootConstrainSelectedInstOperands, |
| 45014 | // GIR_Coverage, 6286, |
| 45015 | GIR_EraseRootFromParent_Done, |
| 45016 | // Label 2456: @145134 |
| 45017 | GIM_Try, /*On fail goto*//*Label 2457*/ GIMT_Encode4(145193), // Rule ID 6296 // |
| 45018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45020 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 45023 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 45025 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45032 | GIR_RootConstrainSelectedInstOperands, |
| 45033 | // GIR_Coverage, 6296, |
| 45034 | GIR_EraseRootFromParent_Done, |
| 45035 | // Label 2457: @145193 |
| 45036 | GIM_Try, /*On fail goto*//*Label 2458*/ GIMT_Encode4(145252), // Rule ID 6298 // |
| 45037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45038 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45039 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45040 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 45042 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 45044 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45050 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45051 | GIR_RootConstrainSelectedInstOperands, |
| 45052 | // GIR_Coverage, 6298, |
| 45053 | GIR_EraseRootFromParent_Done, |
| 45054 | // Label 2458: @145252 |
| 45055 | GIM_Try, /*On fail goto*//*Label 2459*/ GIMT_Encode4(145311), // Rule ID 6300 // |
| 45056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45057 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45058 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45059 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 45061 | // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 45063 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45070 | GIR_RootConstrainSelectedInstOperands, |
| 45071 | // GIR_Coverage, 6300, |
| 45072 | GIR_EraseRootFromParent_Done, |
| 45073 | // Label 2459: @145311 |
| 45074 | GIM_Try, /*On fail goto*//*Label 2460*/ GIMT_Encode4(145370), // Rule ID 6302 // |
| 45075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45076 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45077 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45078 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45079 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 45080 | // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[f32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 45082 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45088 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45089 | GIR_RootConstrainSelectedInstOperands, |
| 45090 | // GIR_Coverage, 6302, |
| 45091 | GIR_EraseRootFromParent_Done, |
| 45092 | // Label 2460: @145370 |
| 45093 | GIM_Try, /*On fail goto*//*Label 2461*/ GIMT_Encode4(145437), // Rule ID 4035 // |
| 45094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 45095 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45096 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45097 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45098 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45099 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 45101 | // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SVS), |
| 45103 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 45106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45108 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45109 | GIR_RootConstrainSelectedInstOperands, |
| 45110 | // GIR_Coverage, 4035, |
| 45111 | GIR_EraseRootFromParent_Done, |
| 45112 | // Label 2461: @145437 |
| 45113 | GIM_Try, /*On fail goto*//*Label 2462*/ GIMT_Encode4(145504), // Rule ID 4041 // |
| 45114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 45115 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45116 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45117 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45118 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45119 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 45121 | // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (SCRATCH_STORE_SHORT_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SVS), |
| 45123 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 45126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45128 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45129 | GIR_RootConstrainSelectedInstOperands, |
| 45130 | // GIR_Coverage, 4041, |
| 45131 | GIR_EraseRootFromParent_Done, |
| 45132 | // Label 2462: @145504 |
| 45133 | GIM_Try, /*On fail goto*//*Label 2463*/ GIMT_Encode4(145560), // Rule ID 3206 // |
| 45134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 45135 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45136 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 45139 | // (st i32:{ *:[i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 45141 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 45144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45146 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45147 | GIR_RootConstrainSelectedInstOperands, |
| 45148 | // GIR_Coverage, 3206, |
| 45149 | GIR_EraseRootFromParent_Done, |
| 45150 | // Label 2463: @145560 |
| 45151 | GIM_Try, /*On fail goto*//*Label 2464*/ GIMT_Encode4(145616), // Rule ID 3885 // |
| 45152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 45153 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45154 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45155 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45156 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 45157 | // (st f32:{ *:[f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 45159 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 45162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45165 | GIR_RootConstrainSelectedInstOperands, |
| 45166 | // GIR_Coverage, 3885, |
| 45167 | GIR_EraseRootFromParent_Done, |
| 45168 | // Label 2464: @145616 |
| 45169 | GIM_Try, /*On fail goto*//*Label 2465*/ GIMT_Encode4(145678), // Rule ID 4034 // |
| 45170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45171 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45172 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45173 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45174 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 45177 | // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE_SADDR), |
| 45179 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45184 | GIR_RootConstrainSelectedInstOperands, |
| 45185 | // GIR_Coverage, 4034, |
| 45186 | GIR_EraseRootFromParent_Done, |
| 45187 | // Label 2465: @145678 |
| 45188 | GIM_Try, /*On fail goto*//*Label 2466*/ GIMT_Encode4(145740), // Rule ID 4040 // |
| 45189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45190 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45191 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45192 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45193 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45194 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45195 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 45196 | // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (SCRATCH_STORE_SHORT_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT_SADDR), |
| 45198 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45202 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45203 | GIR_RootConstrainSelectedInstOperands, |
| 45204 | // GIR_Coverage, 4040, |
| 45205 | GIR_EraseRootFromParent_Done, |
| 45206 | // Label 2466: @145740 |
| 45207 | GIM_Try, /*On fail goto*//*Label 2467*/ GIMT_Encode4(145791), // Rule ID 3205 // |
| 45208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45209 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45210 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45211 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45212 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 45213 | // (st i32:{ *:[i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 45215 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45220 | GIR_RootConstrainSelectedInstOperands, |
| 45221 | // GIR_Coverage, 3205, |
| 45222 | GIR_EraseRootFromParent_Done, |
| 45223 | // Label 2467: @145791 |
| 45224 | GIM_Try, /*On fail goto*//*Label 2468*/ GIMT_Encode4(145842), // Rule ID 3884 // |
| 45225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45226 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45227 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45228 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45229 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 45230 | // (st f32:{ *:[f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 45232 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45236 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45237 | GIR_RootConstrainSelectedInstOperands, |
| 45238 | // GIR_Coverage, 3884, |
| 45239 | GIR_EraseRootFromParent_Done, |
| 45240 | // Label 2468: @145842 |
| 45241 | GIM_Try, /*On fail goto*//*Label 2469*/ GIMT_Encode4(145904), // Rule ID 4033 // |
| 45242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45243 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45244 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45246 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 45249 | // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (SCRATCH_STORE_BYTE anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 45250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_BYTE), |
| 45251 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45255 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45256 | GIR_RootConstrainSelectedInstOperands, |
| 45257 | // GIR_Coverage, 4033, |
| 45258 | GIR_EraseRootFromParent_Done, |
| 45259 | // Label 2469: @145904 |
| 45260 | GIM_Try, /*On fail goto*//*Label 2470*/ GIMT_Encode4(145966), // Rule ID 4039 // |
| 45261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45262 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45263 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45264 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45265 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45266 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 45268 | // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (SCRATCH_STORE_SHORT anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 45269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_SHORT), |
| 45270 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45275 | GIR_RootConstrainSelectedInstOperands, |
| 45276 | // GIR_Coverage, 4039, |
| 45277 | GIR_EraseRootFromParent_Done, |
| 45278 | // Label 2470: @145966 |
| 45279 | GIM_Try, /*On fail goto*//*Label 2471*/ GIMT_Encode4(146017), // Rule ID 3204 // |
| 45280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45281 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45282 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45284 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 45285 | // (st i32:{ *:[i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 45286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 45287 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45291 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45292 | GIR_RootConstrainSelectedInstOperands, |
| 45293 | // GIR_Coverage, 3204, |
| 45294 | GIR_EraseRootFromParent_Done, |
| 45295 | // Label 2471: @146017 |
| 45296 | GIM_Try, /*On fail goto*//*Label 2472*/ GIMT_Encode4(146068), // Rule ID 3883 // |
| 45297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 45298 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45299 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 45302 | // (st f32:{ *:[f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 45303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 45304 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 45305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45309 | GIR_RootConstrainSelectedInstOperands, |
| 45310 | // GIR_Coverage, 3883, |
| 45311 | GIR_EraseRootFromParent_Done, |
| 45312 | // Label 2472: @146068 |
| 45313 | GIM_Try, /*On fail goto*//*Label 2473*/ GIMT_Encode4(146155), // Rule ID 7537 // |
| 45314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45315 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45316 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45317 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 45318 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 45322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 45323 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 45324 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45325 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 45327 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_store_hi16_local>> => (DS_WRITE_B16_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 45328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_D16_HI), |
| 45329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 45330 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 45331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 45334 | GIR_RootConstrainSelectedInstOperands, |
| 45335 | // GIR_Coverage, 7537, |
| 45336 | GIR_EraseRootFromParent_Done, |
| 45337 | // Label 2473: @146155 |
| 45338 | GIM_Try, /*On fail goto*//*Label 2474*/ GIMT_Encode4(146242), // Rule ID 7538 // |
| 45339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45340 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45341 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45342 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 45343 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45344 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45345 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45346 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 45347 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 45348 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 45349 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45350 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 45352 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$value, 16:{ *:[i32] }), (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_local>> => (DS_WRITE_B8_D16_HI ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 45353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_D16_HI), |
| 45354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 45355 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // value |
| 45356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45358 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 45359 | GIR_RootConstrainSelectedInstOperands, |
| 45360 | // GIR_Coverage, 7538, |
| 45361 | GIR_EraseRootFromParent_Done, |
| 45362 | // Label 2474: @146242 |
| 45363 | GIM_Try, /*On fail goto*//*Label 2475*/ GIMT_Encode4(146313), // Rule ID 6263 // |
| 45364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 45365 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45366 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45367 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 45368 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45370 | // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (BUFFER_STORE_BYTE_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 45371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64), |
| 45372 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 45373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45379 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45380 | GIR_RootConstrainSelectedInstOperands, |
| 45381 | // GIR_Coverage, 6263, |
| 45382 | GIR_EraseRootFromParent_Done, |
| 45383 | // Label 2475: @146313 |
| 45384 | GIM_Try, /*On fail goto*//*Label 2476*/ GIMT_Encode4(146384), // Rule ID 6267 // |
| 45385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 45386 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45387 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45388 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 45389 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45390 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45391 | // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (BUFFER_STORE_SHORT_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 45392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64), |
| 45393 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 45394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45401 | GIR_RootConstrainSelectedInstOperands, |
| 45402 | // GIR_Coverage, 6267, |
| 45403 | GIR_EraseRootFromParent_Done, |
| 45404 | // Label 2476: @146384 |
| 45405 | GIM_Try, /*On fail goto*//*Label 2477*/ GIMT_Encode4(146455), // Rule ID 6271 // |
| 45406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 45407 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 45408 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45409 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 45410 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45412 | // (atomic_store i32:{ *:[i32] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>> => (BUFFER_STORE_DWORD_ADDR64 ?:{ *:[i32] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 45413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 45414 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 45415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45422 | GIR_RootConstrainSelectedInstOperands, |
| 45423 | // GIR_Coverage, 6271, |
| 45424 | GIR_EraseRootFromParent_Done, |
| 45425 | // Label 2477: @146455 |
| 45426 | GIM_Try, /*On fail goto*//*Label 2478*/ GIMT_Encode4(146530), // Rule ID 4090 // |
| 45427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45428 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45429 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45430 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45431 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45432 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45434 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_ADDR64), |
| 45436 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45443 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45444 | GIR_RootConstrainSelectedInstOperands, |
| 45445 | // GIR_Coverage, 4090, |
| 45446 | GIR_EraseRootFromParent_Done, |
| 45447 | // Label 2478: @146530 |
| 45448 | GIM_Try, /*On fail goto*//*Label 2479*/ GIMT_Encode4(146602), // Rule ID 4242 // |
| 45449 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45450 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45451 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45452 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45453 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45454 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45455 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_ADDR64), |
| 45457 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45465 | GIR_RootConstrainSelectedInstOperands, |
| 45466 | // GIR_Coverage, 4242, |
| 45467 | GIR_EraseRootFromParent_Done, |
| 45468 | // Label 2479: @146602 |
| 45469 | GIM_Try, /*On fail goto*//*Label 2480*/ GIMT_Encode4(146677), // Rule ID 4244 // |
| 45470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45471 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45472 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45473 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45474 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45477 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (BUFFER_STORE_SHORT_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_ADDR64), |
| 45479 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45487 | GIR_RootConstrainSelectedInstOperands, |
| 45488 | // GIR_Coverage, 4244, |
| 45489 | GIR_EraseRootFromParent_Done, |
| 45490 | // Label 2480: @146677 |
| 45491 | GIM_Try, /*On fail goto*//*Label 2481*/ GIMT_Encode4(146749), // Rule ID 4246 // |
| 45492 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45493 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45495 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45498 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (BUFFER_STORE_SHORT_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_ADDR64), |
| 45500 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45508 | GIR_RootConstrainSelectedInstOperands, |
| 45509 | // GIR_Coverage, 4246, |
| 45510 | GIR_EraseRootFromParent_Done, |
| 45511 | // Label 2481: @146749 |
| 45512 | GIM_Try, /*On fail goto*//*Label 2482*/ GIMT_Encode4(146824), // Rule ID 6279 // |
| 45513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45514 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45515 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45516 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45517 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45518 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45519 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45520 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN), |
| 45522 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45530 | GIR_RootConstrainSelectedInstOperands, |
| 45531 | // GIR_Coverage, 6279, |
| 45532 | GIR_EraseRootFromParent_Done, |
| 45533 | // Label 2482: @146824 |
| 45534 | GIM_Try, /*On fail goto*//*Label 2483*/ GIMT_Encode4(146899), // Rule ID 6281 // |
| 45535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45536 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45537 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45538 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45539 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45542 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_private>> => (BUFFER_STORE_BYTE_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN), |
| 45544 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45551 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45552 | GIR_RootConstrainSelectedInstOperands, |
| 45553 | // GIR_Coverage, 6281, |
| 45554 | GIR_EraseRootFromParent_Done, |
| 45555 | // Label 2483: @146899 |
| 45556 | GIM_Try, /*On fail goto*//*Label 2484*/ GIMT_Encode4(146974), // Rule ID 6283 // |
| 45557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45558 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45559 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45560 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45561 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45564 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (BUFFER_STORE_SHORT_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN), |
| 45566 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45574 | GIR_RootConstrainSelectedInstOperands, |
| 45575 | // GIR_Coverage, 6283, |
| 45576 | GIR_EraseRootFromParent_Done, |
| 45577 | // Label 2484: @146974 |
| 45578 | GIM_Try, /*On fail goto*//*Label 2485*/ GIMT_Encode4(147049), // Rule ID 6285 // |
| 45579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45580 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45581 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45583 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45584 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45586 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_private>> => (BUFFER_STORE_SHORT_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN), |
| 45588 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45596 | GIR_RootConstrainSelectedInstOperands, |
| 45597 | // GIR_Coverage, 6285, |
| 45598 | GIR_EraseRootFromParent_Done, |
| 45599 | // Label 2485: @147049 |
| 45600 | GIM_Try, /*On fail goto*//*Label 2486*/ GIMT_Encode4(147113), // Rule ID 4248 // |
| 45601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45602 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45603 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45604 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45606 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 45608 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45615 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45616 | GIR_RootConstrainSelectedInstOperands, |
| 45617 | // GIR_Coverage, 4248, |
| 45618 | GIR_EraseRootFromParent_Done, |
| 45619 | // Label 2486: @147113 |
| 45620 | GIM_Try, /*On fail goto*//*Label 2487*/ GIMT_Encode4(147174), // Rule ID 4250 // |
| 45621 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45622 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45623 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45624 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45625 | // (st i32:{ *:[i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 i32:{ *:[i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 45627 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45634 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45635 | GIR_RootConstrainSelectedInstOperands, |
| 45636 | // GIR_Coverage, 4250, |
| 45637 | GIR_EraseRootFromParent_Done, |
| 45638 | // Label 2487: @147174 |
| 45639 | GIM_Try, /*On fail goto*//*Label 2488*/ GIMT_Encode4(147238), // Rule ID 4252 // |
| 45640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45641 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45642 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45643 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45644 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45645 | // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 45647 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45654 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45655 | GIR_RootConstrainSelectedInstOperands, |
| 45656 | // GIR_Coverage, 4252, |
| 45657 | GIR_EraseRootFromParent_Done, |
| 45658 | // Label 2488: @147238 |
| 45659 | GIM_Try, /*On fail goto*//*Label 2489*/ GIMT_Encode4(147299), // Rule ID 4254 // |
| 45660 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45661 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45662 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45663 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 45664 | // (st f32:{ *:[f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 f32:{ *:[f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 45666 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45673 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45674 | GIR_RootConstrainSelectedInstOperands, |
| 45675 | // GIR_Coverage, 4254, |
| 45676 | GIR_EraseRootFromParent_Done, |
| 45677 | // Label 2489: @147299 |
| 45678 | GIM_Try, /*On fail goto*//*Label 2490*/ GIMT_Encode4(147363), // Rule ID 6295 // |
| 45679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45680 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45682 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45683 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45684 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 45686 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45693 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45694 | GIR_RootConstrainSelectedInstOperands, |
| 45695 | // GIR_Coverage, 6295, |
| 45696 | GIR_EraseRootFromParent_Done, |
| 45697 | // Label 2490: @147363 |
| 45698 | GIM_Try, /*On fail goto*//*Label 2491*/ GIMT_Encode4(147427), // Rule ID 6297 // |
| 45699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45700 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45701 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45702 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45703 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45704 | // (st i32:{ *:[i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 45706 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45714 | GIR_RootConstrainSelectedInstOperands, |
| 45715 | // GIR_Coverage, 6297, |
| 45716 | GIR_EraseRootFromParent_Done, |
| 45717 | // Label 2491: @147427 |
| 45718 | GIM_Try, /*On fail goto*//*Label 2492*/ GIMT_Encode4(147491), // Rule ID 6299 // |
| 45719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 45720 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45724 | // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 45726 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45734 | GIR_RootConstrainSelectedInstOperands, |
| 45735 | // GIR_Coverage, 6299, |
| 45736 | GIR_EraseRootFromParent_Done, |
| 45737 | // Label 2492: @147491 |
| 45738 | GIM_Try, /*On fail goto*//*Label 2493*/ GIMT_Encode4(147555), // Rule ID 6301 // |
| 45739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 45740 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 45741 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45742 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 45744 | // (st f32:{ *:[f32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[f32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 45745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 45746 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 45747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 45748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 45750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 45751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45753 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45754 | GIR_RootConstrainSelectedInstOperands, |
| 45755 | // GIR_Coverage, 6301, |
| 45756 | GIR_EraseRootFromParent_Done, |
| 45757 | // Label 2493: @147555 |
| 45758 | GIM_Try, /*On fail goto*//*Label 2494*/ GIMT_Encode4(147647), // Rule ID 3569 // |
| 45759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45760 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45761 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45762 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45763 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45765 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45766 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 45767 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 45768 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 45769 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45770 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 45772 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>> => (GLOBAL_STORE_SHORT_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI_SADDR), |
| 45774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 45775 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 45776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 45780 | GIR_RootConstrainSelectedInstOperands, |
| 45781 | // GIR_Coverage, 3569, |
| 45782 | GIR_EraseRootFromParent_Done, |
| 45783 | // Label 2494: @147647 |
| 45784 | GIM_Try, /*On fail goto*//*Label 2495*/ GIMT_Encode4(147739), // Rule ID 3571 // |
| 45785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45786 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45787 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45788 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45790 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45791 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45792 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 45793 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 45794 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 45795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45796 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45797 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 45798 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>> => (GLOBAL_STORE_BYTE_D16_HI_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 45799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI_SADDR), |
| 45800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 45801 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 45802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 45803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45805 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 45806 | GIR_RootConstrainSelectedInstOperands, |
| 45807 | // GIR_Coverage, 3571, |
| 45808 | GIR_EraseRootFromParent_Done, |
| 45809 | // Label 2495: @147739 |
| 45810 | GIM_Try, /*On fail goto*//*Label 2496*/ GIMT_Encode4(147809), // Rule ID 4089 // |
| 45811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45812 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45813 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45814 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45815 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45816 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45817 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45818 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET), |
| 45820 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45826 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45827 | GIR_RootConstrainSelectedInstOperands, |
| 45828 | // GIR_Coverage, 4089, |
| 45829 | GIR_EraseRootFromParent_Done, |
| 45830 | // Label 2496: @147809 |
| 45831 | GIM_Try, /*On fail goto*//*Label 2497*/ GIMT_Encode4(147876), // Rule ID 4241 // |
| 45832 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45833 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45834 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45835 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45836 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45838 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (BUFFER_STORE_BYTE_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET), |
| 45840 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45846 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45847 | GIR_RootConstrainSelectedInstOperands, |
| 45848 | // GIR_Coverage, 4241, |
| 45849 | GIR_EraseRootFromParent_Done, |
| 45850 | // Label 2497: @147876 |
| 45851 | GIM_Try, /*On fail goto*//*Label 2498*/ GIMT_Encode4(147946), // Rule ID 4243 // |
| 45852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45853 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45854 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45855 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45859 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (BUFFER_STORE_SHORT_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET), |
| 45861 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45868 | GIR_RootConstrainSelectedInstOperands, |
| 45869 | // GIR_Coverage, 4243, |
| 45870 | GIR_EraseRootFromParent_Done, |
| 45871 | // Label 2498: @147946 |
| 45872 | GIM_Try, /*On fail goto*//*Label 2499*/ GIMT_Encode4(148013), // Rule ID 4245 // |
| 45873 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45874 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45875 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45876 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45877 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45879 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (BUFFER_STORE_SHORT_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET), |
| 45881 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45887 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45888 | GIR_RootConstrainSelectedInstOperands, |
| 45889 | // GIR_Coverage, 4245, |
| 45890 | GIR_EraseRootFromParent_Done, |
| 45891 | // Label 2499: @148013 |
| 45892 | GIM_Try, /*On fail goto*//*Label 2500*/ GIMT_Encode4(148072), // Rule ID 4247 // |
| 45893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45894 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45895 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45896 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45897 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45898 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 45900 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45907 | GIR_RootConstrainSelectedInstOperands, |
| 45908 | // GIR_Coverage, 4247, |
| 45909 | GIR_EraseRootFromParent_Done, |
| 45910 | // Label 2500: @148072 |
| 45911 | GIM_Try, /*On fail goto*//*Label 2501*/ GIMT_Encode4(148128), // Rule ID 4249 // |
| 45912 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45913 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45914 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45916 | // (st i32:{ *:[i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 45918 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45924 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45925 | GIR_RootConstrainSelectedInstOperands, |
| 45926 | // GIR_Coverage, 4249, |
| 45927 | GIR_EraseRootFromParent_Done, |
| 45928 | // Label 2501: @148128 |
| 45929 | GIM_Try, /*On fail goto*//*Label 2502*/ GIMT_Encode4(148187), // Rule ID 4251 // |
| 45930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 45931 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45932 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45933 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45935 | // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 45937 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45944 | GIR_RootConstrainSelectedInstOperands, |
| 45945 | // GIR_Coverage, 4251, |
| 45946 | GIR_EraseRootFromParent_Done, |
| 45947 | // Label 2502: @148187 |
| 45948 | GIM_Try, /*On fail goto*//*Label 2503*/ GIMT_Encode4(148243), // Rule ID 4253 // |
| 45949 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45950 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45951 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 45953 | // (st f32:{ *:[f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 45954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 45955 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 45956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 45957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 45958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 45959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45961 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 45962 | GIR_RootConstrainSelectedInstOperands, |
| 45963 | // GIR_Coverage, 4253, |
| 45964 | GIR_EraseRootFromParent_Done, |
| 45965 | // Label 2503: @148243 |
| 45966 | GIM_Try, /*On fail goto*//*Label 2504*/ GIMT_Encode4(148330), // Rule ID 3568 // |
| 45967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45968 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45969 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 45970 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45971 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45973 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45974 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 45975 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 45976 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 45977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 45978 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 45979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 45980 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_global>> => (GLOBAL_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 45981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_D16_HI), |
| 45982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 45983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 45984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 45985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 45986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 45987 | GIR_RootConstrainSelectedInstOperands, |
| 45988 | // GIR_Coverage, 3568, |
| 45989 | GIR_EraseRootFromParent_Done, |
| 45990 | // Label 2504: @148330 |
| 45991 | GIM_Try, /*On fail goto*//*Label 2505*/ GIMT_Encode4(148417), // Rule ID 3570 // |
| 45992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 45993 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 45994 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 45995 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 45996 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 45997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 45998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 45999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46000 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 46001 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 46002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46003 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46004 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46005 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_global>> => (GLOBAL_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_D16_HI), |
| 46007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 46009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46011 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 46012 | GIR_RootConstrainSelectedInstOperands, |
| 46013 | // GIR_Coverage, 3570, |
| 46014 | GIR_EraseRootFromParent_Done, |
| 46015 | // Label 2505: @148417 |
| 46016 | GIM_Try, /*On fail goto*//*Label 2506*/ GIMT_Encode4(148475), // Rule ID 7527 // |
| 46017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46018 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46020 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46023 | // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8_glue>><<P:Predicate_atomic_store_8_local_m0>> => (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8), |
| 46025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46026 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46030 | GIR_RootConstrainSelectedInstOperands, |
| 46031 | // GIR_Coverage, 7527, |
| 46032 | GIR_EraseRootFromParent_Done, |
| 46033 | // Label 2506: @148475 |
| 46034 | GIM_Try, /*On fail goto*//*Label 2507*/ GIMT_Encode4(148533), // Rule ID 7528 // |
| 46035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46036 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46037 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46038 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46039 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46040 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46041 | // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_local>> => (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9), |
| 46043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46044 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46048 | GIR_RootConstrainSelectedInstOperands, |
| 46049 | // GIR_Coverage, 7528, |
| 46050 | GIR_EraseRootFromParent_Done, |
| 46051 | // Label 2507: @148533 |
| 46052 | GIM_Try, /*On fail goto*//*Label 2508*/ GIMT_Encode4(148591), // Rule ID 7531 // |
| 46053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46054 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46055 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46056 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46057 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46058 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46059 | // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16_glue>><<P:Predicate_atomic_store_16_local_m0>> => (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16), |
| 46061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46062 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46066 | GIR_RootConstrainSelectedInstOperands, |
| 46067 | // GIR_Coverage, 7531, |
| 46068 | GIR_EraseRootFromParent_Done, |
| 46069 | // Label 2508: @148591 |
| 46070 | GIM_Try, /*On fail goto*//*Label 2509*/ GIMT_Encode4(148649), // Rule ID 7532 // |
| 46071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46072 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46073 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46074 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46075 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46077 | // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_local>> => (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9), |
| 46079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46080 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46084 | GIR_RootConstrainSelectedInstOperands, |
| 46085 | // GIR_Coverage, 7532, |
| 46086 | GIR_EraseRootFromParent_Done, |
| 46087 | // Label 2509: @148649 |
| 46088 | GIM_Try, /*On fail goto*//*Label 2510*/ GIMT_Encode4(148707), // Rule ID 7533 // |
| 46089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46090 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 46091 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46092 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46093 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46094 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46095 | // (AMDGPUatomic_st_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32_glue>><<P:Predicate_atomic_store_32_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 46097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46098 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46102 | GIR_RootConstrainSelectedInstOperands, |
| 46103 | // GIR_Coverage, 7533, |
| 46104 | GIR_EraseRootFromParent_Done, |
| 46105 | // Label 2510: @148707 |
| 46106 | GIM_Try, /*On fail goto*//*Label 2511*/ GIMT_Encode4(148765), // Rule ID 7534 // |
| 46107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46108 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 46109 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46110 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46111 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46112 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46113 | // (atomic_store i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 46115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46116 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46119 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46120 | GIR_RootConstrainSelectedInstOperands, |
| 46121 | // GIR_Coverage, 7534, |
| 46122 | GIR_EraseRootFromParent_Done, |
| 46123 | // Label 2511: @148765 |
| 46124 | GIM_Try, /*On fail goto*//*Label 2512*/ GIMT_Encode4(148827), // Rule ID 7499 // |
| 46125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46126 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46127 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46128 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46129 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46130 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46131 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46132 | // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei8_glue>><<P:Predicate_truncstorei8_local_m0>> => (DS_WRITE_B8 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8), |
| 46134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46135 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46139 | GIR_RootConstrainSelectedInstOperands, |
| 46140 | // GIR_Coverage, 7499, |
| 46141 | GIR_EraseRootFromParent_Done, |
| 46142 | // Label 2512: @148827 |
| 46143 | GIM_Try, /*On fail goto*//*Label 2513*/ GIMT_Encode4(148889), // Rule ID 7500 // |
| 46144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46145 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46146 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46147 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46148 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46150 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46151 | // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_local>> => (DS_WRITE_B8_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B8_gfx9), |
| 46153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46154 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46158 | GIR_RootConstrainSelectedInstOperands, |
| 46159 | // GIR_Coverage, 7500, |
| 46160 | GIR_EraseRootFromParent_Done, |
| 46161 | // Label 2513: @148889 |
| 46162 | GIM_Try, /*On fail goto*//*Label 2514*/ GIMT_Encode4(148951), // Rule ID 7501 // |
| 46163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46164 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46165 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46166 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46167 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46168 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46169 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46170 | // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_truncstore_glue>><<P:Predicate_truncstorei16_glue>><<P:Predicate_truncstorei16_local_m0>> => (DS_WRITE_B16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16), |
| 46172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46173 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46177 | GIR_RootConstrainSelectedInstOperands, |
| 46178 | // GIR_Coverage, 7501, |
| 46179 | GIR_EraseRootFromParent_Done, |
| 46180 | // Label 2514: @148951 |
| 46181 | GIM_Try, /*On fail goto*//*Label 2515*/ GIMT_Encode4(149013), // Rule ID 7502 // |
| 46182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46183 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46184 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46185 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46186 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46187 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46188 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46189 | // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_local>> => (DS_WRITE_B16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B16_gfx9), |
| 46191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46192 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46196 | GIR_RootConstrainSelectedInstOperands, |
| 46197 | // GIR_Coverage, 7502, |
| 46198 | GIR_EraseRootFromParent_Done, |
| 46199 | // Label 2515: @149013 |
| 46200 | GIM_Try, /*On fail goto*//*Label 2516*/ GIMT_Encode4(149068), // Rule ID 7507 // |
| 46201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46202 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46203 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46204 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46205 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46207 | // (AMDGPUst_glue i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 46209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46210 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46213 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46214 | GIR_RootConstrainSelectedInstOperands, |
| 46215 | // GIR_Coverage, 7507, |
| 46216 | GIR_EraseRootFromParent_Done, |
| 46217 | // Label 2516: @149068 |
| 46218 | GIM_Try, /*On fail goto*//*Label 2517*/ GIMT_Encode4(149123), // Rule ID 7509 // |
| 46219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46220 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46221 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46222 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46223 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46225 | // (AMDGPUst_glue f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 46227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46228 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46231 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46232 | GIR_RootConstrainSelectedInstOperands, |
| 46233 | // GIR_Coverage, 7509, |
| 46234 | GIR_EraseRootFromParent_Done, |
| 46235 | // Label 2517: @149123 |
| 46236 | GIM_Try, /*On fail goto*//*Label 2518*/ GIMT_Encode4(149174), // Rule ID 7508 // |
| 46237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46238 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46239 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46242 | // (st i32:{ *:[i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 46244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46245 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46249 | GIR_RootConstrainSelectedInstOperands, |
| 46250 | // GIR_Coverage, 7508, |
| 46251 | GIR_EraseRootFromParent_Done, |
| 46252 | // Label 2518: @149174 |
| 46253 | GIM_Try, /*On fail goto*//*Label 2519*/ GIMT_Encode4(149225), // Rule ID 7510 // |
| 46254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46255 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46256 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46257 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46259 | // (st f32:{ *:[f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 46261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46262 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46266 | GIR_RootConstrainSelectedInstOperands, |
| 46267 | // GIR_Coverage, 7510, |
| 46268 | GIR_EraseRootFromParent_Done, |
| 46269 | // Label 2519: @149225 |
| 46270 | GIM_Try, /*On fail goto*//*Label 2520*/ GIMT_Encode4(149288), // Rule ID 3595 // |
| 46271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46272 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46273 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46274 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46275 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46277 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR), |
| 46279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46280 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46284 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46285 | GIR_RootConstrainSelectedInstOperands, |
| 46286 | // GIR_Coverage, 3595, |
| 46287 | GIR_EraseRootFromParent_Done, |
| 46288 | // Label 2520: @149288 |
| 46289 | GIM_Try, /*On fail goto*//*Label 2521*/ GIMT_Encode4(149351), // Rule ID 3599 // |
| 46290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46291 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46292 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46293 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46294 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46296 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR), |
| 46298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46299 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46304 | GIR_RootConstrainSelectedInstOperands, |
| 46305 | // GIR_Coverage, 3599, |
| 46306 | GIR_EraseRootFromParent_Done, |
| 46307 | // Label 2521: @149351 |
| 46308 | GIM_Try, /*On fail goto*//*Label 2522*/ GIMT_Encode4(149414), // Rule ID 3603 // |
| 46309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46310 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 46311 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46312 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46315 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 46317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46318 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46323 | GIR_RootConstrainSelectedInstOperands, |
| 46324 | // GIR_Coverage, 3603, |
| 46325 | GIR_EraseRootFromParent_Done, |
| 46326 | // Label 2522: @149414 |
| 46327 | GIM_Try, /*On fail goto*//*Label 2523*/ GIMT_Encode4(149481), // Rule ID 3559 // |
| 46328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46329 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46330 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46331 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46332 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46335 | // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (GLOBAL_STORE_BYTE_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE_SADDR), |
| 46337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46338 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46342 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46343 | GIR_RootConstrainSelectedInstOperands, |
| 46344 | // GIR_Coverage, 3559, |
| 46345 | GIR_EraseRootFromParent_Done, |
| 46346 | // Label 2523: @149481 |
| 46347 | GIM_Try, /*On fail goto*//*Label 2524*/ GIMT_Encode4(149548), // Rule ID 3563 // |
| 46348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46349 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46350 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46351 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46352 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46353 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46355 | // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (GLOBAL_STORE_SHORT_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT_SADDR), |
| 46357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46358 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46362 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46363 | GIR_RootConstrainSelectedInstOperands, |
| 46364 | // GIR_Coverage, 3563, |
| 46365 | GIR_EraseRootFromParent_Done, |
| 46366 | // Label 2524: @149548 |
| 46367 | GIM_Try, /*On fail goto*//*Label 2525*/ GIMT_Encode4(149604), // Rule ID 3196 // |
| 46368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46369 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46370 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46373 | // (st i32:{ *:[i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 46375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46376 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46381 | GIR_RootConstrainSelectedInstOperands, |
| 46382 | // GIR_Coverage, 3196, |
| 46383 | GIR_EraseRootFromParent_Done, |
| 46384 | // Label 2525: @149604 |
| 46385 | GIM_Try, /*On fail goto*//*Label 2526*/ GIMT_Encode4(149660), // Rule ID 3455 // |
| 46386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46387 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46388 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46389 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46390 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 46391 | // (st f32:{ *:[f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 46393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 46394 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46399 | GIR_RootConstrainSelectedInstOperands, |
| 46400 | // GIR_Coverage, 3455, |
| 46401 | GIR_EraseRootFromParent_Done, |
| 46402 | // Label 2526: @149660 |
| 46403 | GIM_Try, /*On fail goto*//*Label 2527*/ GIMT_Encode4(149718), // Rule ID 3594 // |
| 46404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46405 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46406 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46407 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46408 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46410 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_global>> => (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE), |
| 46412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46413 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46417 | GIR_RootConstrainSelectedInstOperands, |
| 46418 | // GIR_Coverage, 3594, |
| 46419 | GIR_EraseRootFromParent_Done, |
| 46420 | // Label 2527: @149718 |
| 46421 | GIM_Try, /*On fail goto*//*Label 2528*/ GIMT_Encode4(149776), // Rule ID 3598 // |
| 46422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46423 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46424 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46425 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46426 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46427 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46428 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_global>> => (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT), |
| 46430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46431 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46435 | GIR_RootConstrainSelectedInstOperands, |
| 46436 | // GIR_Coverage, 3598, |
| 46437 | GIR_EraseRootFromParent_Done, |
| 46438 | // Label 2528: @149776 |
| 46439 | GIM_Try, /*On fail goto*//*Label 2529*/ GIMT_Encode4(149834), // Rule ID 3602 // |
| 46440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46441 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 46442 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46443 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46446 | // (atomic_store i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 46448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46449 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46453 | GIR_RootConstrainSelectedInstOperands, |
| 46454 | // GIR_Coverage, 3602, |
| 46455 | GIR_EraseRootFromParent_Done, |
| 46456 | // Label 2529: @149834 |
| 46457 | GIM_Try, /*On fail goto*//*Label 2530*/ GIMT_Encode4(149896), // Rule ID 3558 // |
| 46458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46459 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46460 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46461 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46463 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46464 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46465 | // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_global>> => (GLOBAL_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_BYTE), |
| 46467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46468 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46471 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46472 | GIR_RootConstrainSelectedInstOperands, |
| 46473 | // GIR_Coverage, 3558, |
| 46474 | GIR_EraseRootFromParent_Done, |
| 46475 | // Label 2530: @149896 |
| 46476 | GIM_Try, /*On fail goto*//*Label 2531*/ GIMT_Encode4(149958), // Rule ID 3562 // |
| 46477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46478 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46479 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46480 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46481 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46484 | // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_global>> => (GLOBAL_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_SHORT), |
| 46486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46487 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46490 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46491 | GIR_RootConstrainSelectedInstOperands, |
| 46492 | // GIR_Coverage, 3562, |
| 46493 | GIR_EraseRootFromParent_Done, |
| 46494 | // Label 2531: @149958 |
| 46495 | GIM_Try, /*On fail goto*//*Label 2532*/ GIMT_Encode4(150009), // Rule ID 3195 // |
| 46496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46497 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46498 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46499 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46500 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46501 | // (st i32:{ *:[i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 46503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46504 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46508 | GIR_RootConstrainSelectedInstOperands, |
| 46509 | // GIR_Coverage, 3195, |
| 46510 | GIR_EraseRootFromParent_Done, |
| 46511 | // Label 2532: @150009 |
| 46512 | GIM_Try, /*On fail goto*//*Label 2533*/ GIMT_Encode4(150060), // Rule ID 3454 // |
| 46513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 46514 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46515 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46516 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46517 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 46518 | // (st f32:{ *:[f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 46519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 46520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46521 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46524 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46525 | GIR_RootConstrainSelectedInstOperands, |
| 46526 | // GIR_Coverage, 3454, |
| 46527 | GIR_EraseRootFromParent_Done, |
| 46528 | // Label 2533: @150060 |
| 46529 | GIM_Try, /*On fail goto*//*Label 2534*/ GIMT_Encode4(150148), // Rule ID 3410 // |
| 46530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 46531 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46532 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46533 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46534 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46535 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 46536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 46537 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46538 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 46539 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 46540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46541 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46543 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_hi16_flat>> => (FLAT_STORE_SHORT_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT_D16_HI), |
| 46545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 46547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 46550 | GIR_RootConstrainSelectedInstOperands, |
| 46551 | // GIR_Coverage, 3410, |
| 46552 | GIR_EraseRootFromParent_Done, |
| 46553 | // Label 2534: @150148 |
| 46554 | GIM_Try, /*On fail goto*//*Label 2535*/ GIMT_Encode4(150236), // Rule ID 3411 // |
| 46555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasD16LoadStore), |
| 46556 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46557 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46558 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46559 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/0, // MIs[1] |
| 46561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 46562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 46563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 46564 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, 16, |
| 46565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46566 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 46567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46568 | // (st (srl:{ *:[i32] } i32:{ *:[i32] }:$data, 16:{ *:[i32] }), (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_hi16_flat>> => (FLAT_STORE_BYTE_D16_HI ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE_D16_HI), |
| 46570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46571 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // data |
| 46572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46574 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 46575 | GIR_RootConstrainSelectedInstOperands, |
| 46576 | // GIR_Coverage, 3411, |
| 46577 | GIR_EraseRootFromParent_Done, |
| 46578 | // Label 2535: @150236 |
| 46579 | GIM_Try, /*On fail goto*//*Label 2536*/ GIMT_Encode4(150295), // Rule ID 3282 // |
| 46580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46581 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(4), |
| 46582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46583 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46584 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46586 | // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_32>><<P:Predicate_atomic_store_32_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 46588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46589 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46592 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46593 | GIR_RootConstrainSelectedInstOperands, |
| 46594 | // GIR_Coverage, 3282, |
| 46595 | GIR_EraseRootFromParent_Done, |
| 46596 | // Label 2536: @150295 |
| 46597 | GIM_Try, /*On fail goto*//*Label 2537*/ GIMT_Encode4(150354), // Rule ID 3284 // |
| 46598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46599 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46600 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46601 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46602 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46603 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46604 | // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_8>><<P:Predicate_atomic_store_8_flat>> => (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE), |
| 46606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46607 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46611 | GIR_RootConstrainSelectedInstOperands, |
| 46612 | // GIR_Coverage, 3284, |
| 46613 | GIR_EraseRootFromParent_Done, |
| 46614 | // Label 2537: @150354 |
| 46615 | GIM_Try, /*On fail goto*//*Label 2538*/ GIMT_Encode4(150413), // Rule ID 3286 // |
| 46616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46617 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46618 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46619 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46620 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46621 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46622 | // (atomic_store i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_16>><<P:Predicate_atomic_store_16_flat>> => (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT), |
| 46624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46625 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46629 | GIR_RootConstrainSelectedInstOperands, |
| 46630 | // GIR_Coverage, 3286, |
| 46631 | GIR_EraseRootFromParent_Done, |
| 46632 | // Label 2538: @150413 |
| 46633 | GIM_Try, /*On fail goto*//*Label 2539*/ GIMT_Encode4(150476), // Rule ID 3227 // |
| 46634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46635 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46636 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(1), |
| 46637 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46638 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46639 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46640 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46641 | // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei8>><<P:Predicate_truncstorei8_flat>> => (FLAT_STORE_BYTE ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_BYTE), |
| 46643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46644 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46648 | GIR_RootConstrainSelectedInstOperands, |
| 46649 | // GIR_Coverage, 3227, |
| 46650 | GIR_EraseRootFromParent_Done, |
| 46651 | // Label 2539: @150476 |
| 46652 | GIM_Try, /*On fail goto*//*Label 2540*/ GIMT_Encode4(150539), // Rule ID 3228 // |
| 46653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46654 | GIM_CheckMemorySizeLessThanLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46655 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(2), |
| 46656 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46657 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46658 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46660 | // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_truncstore>><<P:Predicate_truncstorei16>><<P:Predicate_truncstorei16_flat>> => (FLAT_STORE_SHORT ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_SHORT), |
| 46662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46663 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46667 | GIR_RootConstrainSelectedInstOperands, |
| 46668 | // GIR_Coverage, 3228, |
| 46669 | GIR_EraseRootFromParent_Done, |
| 46670 | // Label 2540: @150539 |
| 46671 | GIM_Try, /*On fail goto*//*Label 2541*/ GIMT_Encode4(150591), // Rule ID 3230 // |
| 46672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46673 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46674 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46675 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46676 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46677 | // (st i32:{ *:[i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 46678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 46679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46680 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46683 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46684 | GIR_RootConstrainSelectedInstOperands, |
| 46685 | // GIR_Coverage, 3230, |
| 46686 | GIR_EraseRootFromParent_Done, |
| 46687 | // Label 2541: @150591 |
| 46688 | GIM_Try, /*On fail goto*//*Label 2542*/ GIMT_Encode4(150643), // Rule ID 3232 // |
| 46689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 46690 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 46691 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46692 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46693 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 46694 | // (st f32:{ *:[f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 46695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 46696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46697 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46700 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46701 | GIR_RootConstrainSelectedInstOperands, |
| 46702 | // GIR_Coverage, 3232, |
| 46703 | GIR_EraseRootFromParent_Done, |
| 46704 | // Label 2542: @150643 |
| 46705 | GIM_Reject, |
| 46706 | // Label 2278: @150644 |
| 46707 | GIM_Try, /*On fail goto*//*Label 2543*/ GIMT_Encode4(150708), // Rule ID 7685 // |
| 46708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 46709 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46710 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46711 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46712 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46713 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46714 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 46715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46716 | // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 46718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46719 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46722 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46723 | GIR_RootConstrainSelectedInstOperands, |
| 46724 | // GIR_Coverage, 7685, |
| 46725 | GIR_EraseRootFromParent_Done, |
| 46726 | // Label 2543: @150708 |
| 46727 | GIM_Try, /*On fail goto*//*Label 2544*/ GIMT_Encode4(150772), // Rule ID 7689 // |
| 46728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 46729 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46730 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46731 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46734 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 46735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46736 | // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 46738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46739 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46743 | GIR_RootConstrainSelectedInstOperands, |
| 46744 | // GIR_Coverage, 7689, |
| 46745 | GIR_EraseRootFromParent_Done, |
| 46746 | // Label 2544: @150772 |
| 46747 | GIM_Try, /*On fail goto*//*Label 2545*/ GIMT_Encode4(150831), // Rule ID 7609 // |
| 46748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46749 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46750 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46751 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 46752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46755 | // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 46757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46758 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46761 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46762 | GIR_RootConstrainSelectedInstOperands, |
| 46763 | // GIR_Coverage, 7609, |
| 46764 | GIR_EraseRootFromParent_Done, |
| 46765 | // Label 2545: @150831 |
| 46766 | GIM_Try, /*On fail goto*//*Label 2546*/ GIMT_Encode4(150890), // Rule ID 7613 // |
| 46767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 46768 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 46769 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46770 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 46771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46774 | // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 46776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46777 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46781 | GIR_RootConstrainSelectedInstOperands, |
| 46782 | // GIR_Coverage, 7613, |
| 46783 | GIR_EraseRootFromParent_Done, |
| 46784 | // Label 2546: @150890 |
| 46785 | GIM_Try, /*On fail goto*//*Label 2547*/ GIMT_Encode4(150950), // Rule ID 7686 // |
| 46786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 46787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46788 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46789 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46790 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46791 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 46792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46793 | // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 46795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46796 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46800 | GIR_RootConstrainSelectedInstOperands, |
| 46801 | // GIR_Coverage, 7686, |
| 46802 | GIR_EraseRootFromParent_Done, |
| 46803 | // Label 2547: @150950 |
| 46804 | GIM_Try, /*On fail goto*//*Label 2548*/ GIMT_Encode4(151010), // Rule ID 7690 // |
| 46805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 46806 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46807 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46808 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46809 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46810 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 46811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46812 | // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 46814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46815 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46819 | GIR_RootConstrainSelectedInstOperands, |
| 46820 | // GIR_Coverage, 7690, |
| 46821 | GIR_EraseRootFromParent_Done, |
| 46822 | // Label 2548: @151010 |
| 46823 | GIM_Try, /*On fail goto*//*Label 2549*/ GIMT_Encode4(151065), // Rule ID 7610 // |
| 46824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46825 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46826 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 46827 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46828 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46829 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46830 | // (st i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 46832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46833 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46837 | GIR_RootConstrainSelectedInstOperands, |
| 46838 | // GIR_Coverage, 7610, |
| 46839 | GIR_EraseRootFromParent_Done, |
| 46840 | // Label 2549: @151065 |
| 46841 | GIM_Try, /*On fail goto*//*Label 2550*/ GIMT_Encode4(151120), // Rule ID 7614 // |
| 46842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 46843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 46844 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 46845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 46848 | // (st f64:{ *:[f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 46849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 46850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 46851 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 46852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46855 | GIR_RootConstrainSelectedInstOperands, |
| 46856 | // GIR_Coverage, 7614, |
| 46857 | GIR_EraseRootFromParent_Done, |
| 46858 | // Label 2550: @151120 |
| 46859 | GIM_Try, /*On fail goto*//*Label 2551*/ GIMT_Encode4(151176), // Rule ID 3933 // |
| 46860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 46861 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46862 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 46865 | // (st i64:{ *:[i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 46867 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 46870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46873 | GIR_RootConstrainSelectedInstOperands, |
| 46874 | // GIR_Coverage, 3933, |
| 46875 | GIR_EraseRootFromParent_Done, |
| 46876 | // Label 2551: @151176 |
| 46877 | GIM_Try, /*On fail goto*//*Label 2552*/ GIMT_Encode4(151232), // Rule ID 3939 // |
| 46878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 46879 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46880 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 46883 | // (st f64:{ *:[f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 46885 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 46888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 46889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46891 | GIR_RootConstrainSelectedInstOperands, |
| 46892 | // GIR_Coverage, 3939, |
| 46893 | GIR_EraseRootFromParent_Done, |
| 46894 | // Label 2552: @151232 |
| 46895 | GIM_Try, /*On fail goto*//*Label 2553*/ GIMT_Encode4(151283), // Rule ID 3932 // |
| 46896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 46897 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46898 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46899 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 46901 | // (st i64:{ *:[i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 46903 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46907 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46908 | GIR_RootConstrainSelectedInstOperands, |
| 46909 | // GIR_Coverage, 3932, |
| 46910 | GIR_EraseRootFromParent_Done, |
| 46911 | // Label 2553: @151283 |
| 46912 | GIM_Try, /*On fail goto*//*Label 2554*/ GIMT_Encode4(151334), // Rule ID 3938 // |
| 46913 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 46914 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46915 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46916 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 46918 | // (st f64:{ *:[f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 46919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 46920 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 46922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46924 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46925 | GIR_RootConstrainSelectedInstOperands, |
| 46926 | // GIR_Coverage, 3938, |
| 46927 | GIR_EraseRootFromParent_Done, |
| 46928 | // Label 2554: @151334 |
| 46929 | GIM_Try, /*On fail goto*//*Label 2555*/ GIMT_Encode4(151385), // Rule ID 3931 // |
| 46930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 46931 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46932 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46933 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 46935 | // (st i64:{ *:[i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 46936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 46937 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46942 | GIR_RootConstrainSelectedInstOperands, |
| 46943 | // GIR_Coverage, 3931, |
| 46944 | GIR_EraseRootFromParent_Done, |
| 46945 | // Label 2555: @151385 |
| 46946 | GIM_Try, /*On fail goto*//*Label 2556*/ GIMT_Encode4(151436), // Rule ID 3937 // |
| 46947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 46948 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 46949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46950 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 46952 | // (st f64:{ *:[f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 46953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 46954 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 46955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 46956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 46957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46959 | GIR_RootConstrainSelectedInstOperands, |
| 46960 | // GIR_Coverage, 3937, |
| 46961 | GIR_EraseRootFromParent_Done, |
| 46962 | // Label 2556: @151436 |
| 46963 | GIM_Try, /*On fail goto*//*Label 2557*/ GIMT_Encode4(151507), // Rule ID 6273 // |
| 46964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 46965 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 46966 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46967 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 46968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 46970 | // (atomic_store i64:{ *:[i64] }:$val, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>> => (BUFFER_STORE_DWORDX2_ADDR64 ?:{ *:[i64] }:$val, ?:{ *:[i64] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset) |
| 46971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 46972 | GIR_RootToRootCopy, /*OpIdx*/0, // val |
| 46973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 46974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 46975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 46976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 46977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46979 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 46980 | GIR_RootConstrainSelectedInstOperands, |
| 46981 | // GIR_Coverage, 6273, |
| 46982 | GIR_EraseRootFromParent_Done, |
| 46983 | // Label 2557: @151507 |
| 46984 | GIM_Try, /*On fail goto*//*Label 2558*/ GIMT_Encode4(151571), // Rule ID 4284 // |
| 46985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 46986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 46987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 46988 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 46989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 46990 | // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 46991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 46992 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 46993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 46994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 46995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 46996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 46997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 46999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47000 | GIR_RootConstrainSelectedInstOperands, |
| 47001 | // GIR_Coverage, 4284, |
| 47002 | GIR_EraseRootFromParent_Done, |
| 47003 | // Label 2558: @151571 |
| 47004 | GIM_Try, /*On fail goto*//*Label 2559*/ GIMT_Encode4(151632), // Rule ID 4286 // |
| 47005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47009 | // (st i64:{ *:[i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 i64:{ *:[i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 47011 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47019 | GIR_RootConstrainSelectedInstOperands, |
| 47020 | // GIR_Coverage, 4286, |
| 47021 | GIR_EraseRootFromParent_Done, |
| 47022 | // Label 2559: @151632 |
| 47023 | GIM_Try, /*On fail goto*//*Label 2560*/ GIMT_Encode4(151696), // Rule ID 4288 // |
| 47024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47025 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47026 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47027 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47029 | // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 47031 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47038 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47039 | GIR_RootConstrainSelectedInstOperands, |
| 47040 | // GIR_Coverage, 4288, |
| 47041 | GIR_EraseRootFromParent_Done, |
| 47042 | // Label 2560: @151696 |
| 47043 | GIM_Try, /*On fail goto*//*Label 2561*/ GIMT_Encode4(151757), // Rule ID 4290 // |
| 47044 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47045 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47048 | // (st f64:{ *:[f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 f64:{ *:[f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 47050 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47058 | GIR_RootConstrainSelectedInstOperands, |
| 47059 | // GIR_Coverage, 4290, |
| 47060 | GIR_EraseRootFromParent_Done, |
| 47061 | // Label 2561: @151757 |
| 47062 | GIM_Try, /*On fail goto*//*Label 2562*/ GIMT_Encode4(151877), // Rule ID 7540 // |
| 47063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 47064 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 47065 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47066 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47067 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47068 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 47069 | // (AMDGPUst_glue i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 47070 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47071 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 47072 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47073 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47074 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 47075 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47076 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47077 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47078 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47079 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 47080 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47081 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 47083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47084 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47085 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 47086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 47087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 47088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47089 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47090 | GIR_RootConstrainSelectedInstOperands, |
| 47091 | // GIR_Coverage, 7540, |
| 47092 | GIR_EraseRootFromParent_Done, |
| 47093 | // Label 2562: @151877 |
| 47094 | GIM_Try, /*On fail goto*//*Label 2563*/ GIMT_Encode4(151997), // Rule ID 7548 // |
| 47095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 47096 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 47097 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47098 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47099 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 47101 | // (AMDGPUst_glue f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 47102 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47103 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 47104 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47105 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47106 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 47107 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47108 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47109 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47110 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47111 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 47112 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47113 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 47115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47116 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47117 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 47118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 47119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 47120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47121 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47122 | GIR_RootConstrainSelectedInstOperands, |
| 47123 | // GIR_Coverage, 7548, |
| 47124 | GIR_EraseRootFromParent_Done, |
| 47125 | // Label 2563: @151997 |
| 47126 | GIM_Try, /*On fail goto*//*Label 2564*/ GIMT_Encode4(152056), // Rule ID 4283 // |
| 47127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47128 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47129 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47130 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47131 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47132 | // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 47134 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47140 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47141 | GIR_RootConstrainSelectedInstOperands, |
| 47142 | // GIR_Coverage, 4283, |
| 47143 | GIR_EraseRootFromParent_Done, |
| 47144 | // Label 2564: @152056 |
| 47145 | GIM_Try, /*On fail goto*//*Label 2565*/ GIMT_Encode4(152112), // Rule ID 4285 // |
| 47146 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47147 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47148 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47150 | // (st i64:{ *:[i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 47152 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47159 | GIR_RootConstrainSelectedInstOperands, |
| 47160 | // GIR_Coverage, 4285, |
| 47161 | GIR_EraseRootFromParent_Done, |
| 47162 | // Label 2565: @152112 |
| 47163 | GIM_Try, /*On fail goto*//*Label 2566*/ GIMT_Encode4(152171), // Rule ID 4287 // |
| 47164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47165 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47166 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47167 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47168 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47169 | // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 47171 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47177 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47178 | GIR_RootConstrainSelectedInstOperands, |
| 47179 | // GIR_Coverage, 4287, |
| 47180 | GIR_EraseRootFromParent_Done, |
| 47181 | // Label 2566: @152171 |
| 47182 | GIM_Try, /*On fail goto*//*Label 2567*/ GIMT_Encode4(152227), // Rule ID 4289 // |
| 47183 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47184 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47187 | // (st f64:{ *:[f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 47189 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47196 | GIR_RootConstrainSelectedInstOperands, |
| 47197 | // GIR_Coverage, 4289, |
| 47198 | GIR_EraseRootFromParent_Done, |
| 47199 | // Label 2567: @152227 |
| 47200 | GIM_Try, /*On fail goto*//*Label 2568*/ GIMT_Encode4(152343), // Rule ID 7542 // |
| 47201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 47202 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 47206 | // (st i64:{ *:[i64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 47207 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47208 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 47209 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47210 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47211 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 47212 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47213 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47216 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 47217 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47218 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 47220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47221 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47222 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 47223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 47224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 47225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47226 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47227 | GIR_RootConstrainSelectedInstOperands, |
| 47228 | // GIR_Coverage, 7542, |
| 47229 | GIR_EraseRootFromParent_Done, |
| 47230 | // Label 2568: @152343 |
| 47231 | GIM_Try, /*On fail goto*//*Label 2569*/ GIMT_Encode4(152459), // Rule ID 7550 // |
| 47232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 47233 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47234 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47235 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47236 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 47237 | // (st f64:{ *:[f64] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 47238 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 47239 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 47240 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47241 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47242 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 47243 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47244 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 47246 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 47247 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 47248 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 47249 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 47250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 47251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47252 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 47253 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 47254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 47255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 47256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47257 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47258 | GIR_RootConstrainSelectedInstOperands, |
| 47259 | // GIR_Coverage, 7550, |
| 47260 | GIR_EraseRootFromParent_Done, |
| 47261 | // Label 2569: @152459 |
| 47262 | GIM_Try, /*On fail goto*//*Label 2570*/ GIMT_Encode4(152517), // Rule ID 7535 // |
| 47263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 47264 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 47265 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47266 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 47267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 47269 | // (AMDGPUatomic_st_glue i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64_glue>><<P:Predicate_atomic_store_64_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 47270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 47271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47272 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47276 | GIR_RootConstrainSelectedInstOperands, |
| 47277 | // GIR_Coverage, 7535, |
| 47278 | GIR_EraseRootFromParent_Done, |
| 47279 | // Label 2570: @152517 |
| 47280 | GIM_Try, /*On fail goto*//*Label 2571*/ GIMT_Encode4(152575), // Rule ID 7536 // |
| 47281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 47282 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 47283 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 47284 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 47285 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47286 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 47287 | // (atomic_store i64:{ *:[i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 47288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 47289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 47290 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47293 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47294 | GIR_RootConstrainSelectedInstOperands, |
| 47295 | // GIR_Coverage, 7536, |
| 47296 | GIR_EraseRootFromParent_Done, |
| 47297 | // Label 2571: @152575 |
| 47298 | GIM_Try, /*On fail goto*//*Label 2572*/ GIMT_Encode4(152638), // Rule ID 3605 // |
| 47299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47300 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 47301 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47302 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 47303 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 47305 | // (atomic_store i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 47307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 47308 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47313 | GIR_RootConstrainSelectedInstOperands, |
| 47314 | // GIR_Coverage, 3605, |
| 47315 | GIR_EraseRootFromParent_Done, |
| 47316 | // Label 2572: @152638 |
| 47317 | GIM_Try, /*On fail goto*//*Label 2573*/ GIMT_Encode4(152694), // Rule ID 3487 // |
| 47318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47320 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 47323 | // (st i64:{ *:[i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 47325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 47326 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47330 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47331 | GIR_RootConstrainSelectedInstOperands, |
| 47332 | // GIR_Coverage, 3487, |
| 47333 | GIR_EraseRootFromParent_Done, |
| 47334 | // Label 2573: @152694 |
| 47335 | GIM_Try, /*On fail goto*//*Label 2574*/ GIMT_Encode4(152750), // Rule ID 3491 // |
| 47336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47337 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47338 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47339 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 47341 | // (st f64:{ *:[f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 47343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 47344 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47349 | GIR_RootConstrainSelectedInstOperands, |
| 47350 | // GIR_Coverage, 3491, |
| 47351 | GIR_EraseRootFromParent_Done, |
| 47352 | // Label 2574: @152750 |
| 47353 | GIM_Try, /*On fail goto*//*Label 2575*/ GIMT_Encode4(152808), // Rule ID 3604 // |
| 47354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47355 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 47356 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47357 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 47358 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 47360 | // (atomic_store i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 47361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 47362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47363 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47367 | GIR_RootConstrainSelectedInstOperands, |
| 47368 | // GIR_Coverage, 3604, |
| 47369 | GIR_EraseRootFromParent_Done, |
| 47370 | // Label 2575: @152808 |
| 47371 | GIM_Try, /*On fail goto*//*Label 2576*/ GIMT_Encode4(152859), // Rule ID 3486 // |
| 47372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47373 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47374 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47375 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47376 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 47377 | // (st i64:{ *:[i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 47378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 47379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47380 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47384 | GIR_RootConstrainSelectedInstOperands, |
| 47385 | // GIR_Coverage, 3486, |
| 47386 | GIR_EraseRootFromParent_Done, |
| 47387 | // Label 2576: @152859 |
| 47388 | GIM_Try, /*On fail goto*//*Label 2577*/ GIMT_Encode4(152910), // Rule ID 3490 // |
| 47389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 47390 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47391 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47392 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 47394 | // (st f64:{ *:[f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 47395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 47396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47397 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47401 | GIR_RootConstrainSelectedInstOperands, |
| 47402 | // GIR_Coverage, 3490, |
| 47403 | GIR_EraseRootFromParent_Done, |
| 47404 | // Label 2577: @152910 |
| 47405 | GIM_Try, /*On fail goto*//*Label 2578*/ GIMT_Encode4(152969), // Rule ID 3283 // |
| 47406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 47407 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(8), |
| 47408 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 47409 | GIM_CheckAtomicOrderingOrStrongerThan, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::Unordered, |
| 47410 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 47412 | // (atomic_store i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_atomic_store_64>><<P:Predicate_atomic_store_64_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 47413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 47414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47415 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47418 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47419 | GIR_RootConstrainSelectedInstOperands, |
| 47420 | // GIR_Coverage, 3283, |
| 47421 | GIR_EraseRootFromParent_Done, |
| 47422 | // Label 2578: @152969 |
| 47423 | GIM_Try, /*On fail goto*//*Label 2579*/ GIMT_Encode4(153021), // Rule ID 3247 // |
| 47424 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 47425 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 47426 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47427 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 47429 | // (st i64:{ *:[i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 47430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 47431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47432 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47435 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47436 | GIR_RootConstrainSelectedInstOperands, |
| 47437 | // GIR_Coverage, 3247, |
| 47438 | GIR_EraseRootFromParent_Done, |
| 47439 | // Label 2579: @153021 |
| 47440 | GIM_Try, /*On fail goto*//*Label 2580*/ GIMT_Encode4(153073), // Rule ID 3249 // |
| 47441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 47442 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 47443 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 47446 | // (st f64:{ *:[f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 47447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 47448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47449 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47453 | GIR_RootConstrainSelectedInstOperands, |
| 47454 | // GIR_Coverage, 3249, |
| 47455 | GIR_EraseRootFromParent_Done, |
| 47456 | // Label 2580: @153073 |
| 47457 | GIM_Reject, |
| 47458 | // Label 2279: @153074 |
| 47459 | GIM_Try, /*On fail goto*//*Label 2581*/ GIMT_Encode4(153133), // Rule ID 6304 // |
| 47460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47461 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47462 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47463 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47464 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47465 | // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 47467 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47474 | GIR_RootConstrainSelectedInstOperands, |
| 47475 | // GIR_Coverage, 6304, |
| 47476 | GIR_EraseRootFromParent_Done, |
| 47477 | // Label 2581: @153133 |
| 47478 | GIM_Try, /*On fail goto*//*Label 2582*/ GIMT_Encode4(153192), // Rule ID 6306 // |
| 47479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47480 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47481 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47482 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47484 | // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 47486 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47493 | GIR_RootConstrainSelectedInstOperands, |
| 47494 | // GIR_Coverage, 6306, |
| 47495 | GIR_EraseRootFromParent_Done, |
| 47496 | // Label 2582: @153192 |
| 47497 | GIM_Try, /*On fail goto*//*Label 2583*/ GIMT_Encode4(153251), // Rule ID 6308 // |
| 47498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47499 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47500 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47501 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47503 | // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 47505 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47511 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47512 | GIR_RootConstrainSelectedInstOperands, |
| 47513 | // GIR_Coverage, 6308, |
| 47514 | GIR_EraseRootFromParent_Done, |
| 47515 | // Label 2583: @153251 |
| 47516 | GIM_Try, /*On fail goto*//*Label 2584*/ GIMT_Encode4(153310), // Rule ID 6310 // |
| 47517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47518 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47519 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47522 | // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 47524 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47531 | GIR_RootConstrainSelectedInstOperands, |
| 47532 | // GIR_Coverage, 6310, |
| 47533 | GIR_EraseRootFromParent_Done, |
| 47534 | // Label 2584: @153310 |
| 47535 | GIM_Try, /*On fail goto*//*Label 2585*/ GIMT_Encode4(153369), // Rule ID 6312 // |
| 47536 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47537 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47538 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47539 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47541 | // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFSET VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 47543 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47550 | GIR_RootConstrainSelectedInstOperands, |
| 47551 | // GIR_Coverage, 6312, |
| 47552 | GIR_EraseRootFromParent_Done, |
| 47553 | // Label 2585: @153369 |
| 47554 | GIM_Try, /*On fail goto*//*Label 2586*/ GIMT_Encode4(153428), // Rule ID 6314 // |
| 47555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47556 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47557 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47558 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 47560 | // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 47562 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47569 | GIR_RootConstrainSelectedInstOperands, |
| 47570 | // GIR_Coverage, 6314, |
| 47571 | GIR_EraseRootFromParent_Done, |
| 47572 | // Label 2586: @153428 |
| 47573 | GIM_Try, /*On fail goto*//*Label 2587*/ GIMT_Encode4(153484), // Rule ID 3891 // |
| 47574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 47575 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47576 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47577 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47578 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 47579 | // (st v2i16:{ *:[v2i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 47581 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 47584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47587 | GIR_RootConstrainSelectedInstOperands, |
| 47588 | // GIR_Coverage, 3891, |
| 47589 | GIR_EraseRootFromParent_Done, |
| 47590 | // Label 2587: @153484 |
| 47591 | GIM_Try, /*On fail goto*//*Label 2588*/ GIMT_Encode4(153540), // Rule ID 3897 // |
| 47592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 47593 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47594 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47595 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 47597 | // (st v2f16:{ *:[v2f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 47599 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 47602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47605 | GIR_RootConstrainSelectedInstOperands, |
| 47606 | // GIR_Coverage, 3897, |
| 47607 | GIR_EraseRootFromParent_Done, |
| 47608 | // Label 2588: @153540 |
| 47609 | GIM_Try, /*On fail goto*//*Label 2589*/ GIMT_Encode4(153596), // Rule ID 3903 // |
| 47610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 47611 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47612 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47613 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 47615 | // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SVS anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SVS), |
| 47617 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 47620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47623 | GIR_RootConstrainSelectedInstOperands, |
| 47624 | // GIR_Coverage, 3903, |
| 47625 | GIR_EraseRootFromParent_Done, |
| 47626 | // Label 2589: @153596 |
| 47627 | GIM_Try, /*On fail goto*//*Label 2590*/ GIMT_Encode4(153647), // Rule ID 3890 // |
| 47628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47629 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47630 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 47633 | // (st v2i16:{ *:[v2i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 47635 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47640 | GIR_RootConstrainSelectedInstOperands, |
| 47641 | // GIR_Coverage, 3890, |
| 47642 | GIR_EraseRootFromParent_Done, |
| 47643 | // Label 2590: @153647 |
| 47644 | GIM_Try, /*On fail goto*//*Label 2591*/ GIMT_Encode4(153698), // Rule ID 3896 // |
| 47645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47646 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47647 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47648 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 47650 | // (st v2f16:{ *:[v2f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 47652 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47656 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47657 | GIR_RootConstrainSelectedInstOperands, |
| 47658 | // GIR_Coverage, 3896, |
| 47659 | GIR_EraseRootFromParent_Done, |
| 47660 | // Label 2591: @153698 |
| 47661 | GIM_Try, /*On fail goto*//*Label 2592*/ GIMT_Encode4(153749), // Rule ID 3902 // |
| 47662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47663 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47664 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47665 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 47667 | // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD_SADDR anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 47668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD_SADDR), |
| 47669 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 47671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47673 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47674 | GIR_RootConstrainSelectedInstOperands, |
| 47675 | // GIR_Coverage, 3902, |
| 47676 | GIR_EraseRootFromParent_Done, |
| 47677 | // Label 2592: @153749 |
| 47678 | GIM_Try, /*On fail goto*//*Label 2593*/ GIMT_Encode4(153800), // Rule ID 3889 // |
| 47679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47680 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47681 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47682 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47683 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 47684 | // (st v2i16:{ *:[v2i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 47685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 47686 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47690 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47691 | GIR_RootConstrainSelectedInstOperands, |
| 47692 | // GIR_Coverage, 3889, |
| 47693 | GIR_EraseRootFromParent_Done, |
| 47694 | // Label 2593: @153800 |
| 47695 | GIM_Try, /*On fail goto*//*Label 2594*/ GIMT_Encode4(153851), // Rule ID 3895 // |
| 47696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47697 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47698 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47700 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 47701 | // (st v2f16:{ *:[v2f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 47702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 47703 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47707 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47708 | GIR_RootConstrainSelectedInstOperands, |
| 47709 | // GIR_Coverage, 3895, |
| 47710 | GIR_EraseRootFromParent_Done, |
| 47711 | // Label 2594: @153851 |
| 47712 | GIM_Try, /*On fail goto*//*Label 2595*/ GIMT_Encode4(153902), // Rule ID 3901 // |
| 47713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 47714 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 47718 | // (st v2bf16:{ *:[v2bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORD anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 47719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORD), |
| 47720 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 47721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 47722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 47723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47724 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47725 | GIR_RootConstrainSelectedInstOperands, |
| 47726 | // GIR_Coverage, 3901, |
| 47727 | GIR_EraseRootFromParent_Done, |
| 47728 | // Label 2595: @153902 |
| 47729 | GIM_Try, /*On fail goto*//*Label 2596*/ GIMT_Encode4(153966), // Rule ID 4256 // |
| 47730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47731 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47732 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47733 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47734 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47735 | // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 47737 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47745 | GIR_RootConstrainSelectedInstOperands, |
| 47746 | // GIR_Coverage, 4256, |
| 47747 | GIR_EraseRootFromParent_Done, |
| 47748 | // Label 2596: @153966 |
| 47749 | GIM_Try, /*On fail goto*//*Label 2597*/ GIMT_Encode4(154027), // Rule ID 4258 // |
| 47750 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47751 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47752 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47754 | // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2i16:{ *:[v2i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 47756 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47764 | GIR_RootConstrainSelectedInstOperands, |
| 47765 | // GIR_Coverage, 4258, |
| 47766 | GIR_EraseRootFromParent_Done, |
| 47767 | // Label 2597: @154027 |
| 47768 | GIM_Try, /*On fail goto*//*Label 2598*/ GIMT_Encode4(154091), // Rule ID 4260 // |
| 47769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47770 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47771 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47774 | // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 47776 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47782 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47783 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47784 | GIR_RootConstrainSelectedInstOperands, |
| 47785 | // GIR_Coverage, 4260, |
| 47786 | GIR_EraseRootFromParent_Done, |
| 47787 | // Label 2598: @154091 |
| 47788 | GIM_Try, /*On fail goto*//*Label 2599*/ GIMT_Encode4(154152), // Rule ID 4262 // |
| 47789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47790 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47793 | // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2f16:{ *:[v2f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 47795 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47803 | GIR_RootConstrainSelectedInstOperands, |
| 47804 | // GIR_Coverage, 4262, |
| 47805 | GIR_EraseRootFromParent_Done, |
| 47806 | // Label 2599: @154152 |
| 47807 | GIM_Try, /*On fail goto*//*Label 2600*/ GIMT_Encode4(154216), // Rule ID 4264 // |
| 47808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47809 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47813 | // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_ADDR64 v2bf16:{ *:[v2bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_ADDR64), |
| 47815 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47823 | GIR_RootConstrainSelectedInstOperands, |
| 47824 | // GIR_Coverage, 4264, |
| 47825 | GIR_EraseRootFromParent_Done, |
| 47826 | // Label 2600: @154216 |
| 47827 | GIM_Try, /*On fail goto*//*Label 2601*/ GIMT_Encode4(154277), // Rule ID 4266 // |
| 47828 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47829 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47830 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 47832 | // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_ADDR64 v2bf16:{ *:[v2bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_ADDR64), |
| 47834 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47842 | GIR_RootConstrainSelectedInstOperands, |
| 47843 | // GIR_Coverage, 4266, |
| 47844 | GIR_EraseRootFromParent_Done, |
| 47845 | // Label 2601: @154277 |
| 47846 | GIM_Try, /*On fail goto*//*Label 2602*/ GIMT_Encode4(154341), // Rule ID 6303 // |
| 47847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47848 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47849 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47850 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47852 | // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 47854 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47861 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47862 | GIR_RootConstrainSelectedInstOperands, |
| 47863 | // GIR_Coverage, 6303, |
| 47864 | GIR_EraseRootFromParent_Done, |
| 47865 | // Label 2602: @154341 |
| 47866 | GIM_Try, /*On fail goto*//*Label 2603*/ GIMT_Encode4(154405), // Rule ID 6305 // |
| 47867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47868 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47869 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47870 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47871 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47872 | // (st v2i16:{ *:[v2i16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2i16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 47874 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47882 | GIR_RootConstrainSelectedInstOperands, |
| 47883 | // GIR_Coverage, 6305, |
| 47884 | GIR_EraseRootFromParent_Done, |
| 47885 | // Label 2603: @154405 |
| 47886 | GIM_Try, /*On fail goto*//*Label 2604*/ GIMT_Encode4(154469), // Rule ID 6307 // |
| 47887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47888 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47889 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47892 | // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 47894 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47902 | GIR_RootConstrainSelectedInstOperands, |
| 47903 | // GIR_Coverage, 6307, |
| 47904 | GIR_EraseRootFromParent_Done, |
| 47905 | // Label 2604: @154469 |
| 47906 | GIM_Try, /*On fail goto*//*Label 2605*/ GIMT_Encode4(154533), // Rule ID 6309 // |
| 47907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47908 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47909 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47910 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47912 | // (st v2f16:{ *:[v2f16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2f16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 47914 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47922 | GIR_RootConstrainSelectedInstOperands, |
| 47923 | // GIR_Coverage, 6309, |
| 47924 | GIR_EraseRootFromParent_Done, |
| 47925 | // Label 2605: @154533 |
| 47926 | GIM_Try, /*On fail goto*//*Label 2606*/ GIMT_Encode4(154597), // Rule ID 6311 // |
| 47927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 47928 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47929 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47932 | // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_OFFEN VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN), |
| 47934 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47942 | GIR_RootConstrainSelectedInstOperands, |
| 47943 | // GIR_Coverage, 6311, |
| 47944 | GIR_EraseRootFromParent_Done, |
| 47945 | // Label 2606: @154597 |
| 47946 | GIM_Try, /*On fail goto*//*Label 2607*/ GIMT_Encode4(154661), // Rule ID 6313 // |
| 47947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 47948 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 47949 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47950 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 47952 | // (st v2bf16:{ *:[v2bf16] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORD_VBUFFER_OFFEN VGPR_32:{ *:[v2bf16] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 47953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN), |
| 47954 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 47955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 47956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 47958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 47959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47961 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47962 | GIR_RootConstrainSelectedInstOperands, |
| 47963 | // GIR_Coverage, 6313, |
| 47964 | GIR_EraseRootFromParent_Done, |
| 47965 | // Label 2607: @154661 |
| 47966 | GIM_Try, /*On fail goto*//*Label 2608*/ GIMT_Encode4(154720), // Rule ID 4255 // |
| 47967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 47968 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47969 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47970 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47971 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47972 | // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 47974 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47981 | GIR_RootConstrainSelectedInstOperands, |
| 47982 | // GIR_Coverage, 4255, |
| 47983 | GIR_EraseRootFromParent_Done, |
| 47984 | // Label 2608: @154720 |
| 47985 | GIM_Try, /*On fail goto*//*Label 2609*/ GIMT_Encode4(154776), // Rule ID 4257 // |
| 47986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 47987 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 47988 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 47989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 47990 | // (st v2i16:{ *:[v2i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 47991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 47992 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 47993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 47994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 47995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 47996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 47998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 47999 | GIR_RootConstrainSelectedInstOperands, |
| 48000 | // GIR_Coverage, 4257, |
| 48001 | GIR_EraseRootFromParent_Done, |
| 48002 | // Label 2609: @154776 |
| 48003 | GIM_Try, /*On fail goto*//*Label 2610*/ GIMT_Encode4(154835), // Rule ID 4259 // |
| 48004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48006 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48009 | // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 48011 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48018 | GIR_RootConstrainSelectedInstOperands, |
| 48019 | // GIR_Coverage, 4259, |
| 48020 | GIR_EraseRootFromParent_Done, |
| 48021 | // Label 2610: @154835 |
| 48022 | GIM_Try, /*On fail goto*//*Label 2611*/ GIMT_Encode4(154891), // Rule ID 4261 // |
| 48023 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48024 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48025 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48026 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48027 | // (st v2f16:{ *:[v2f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 48029 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48036 | GIR_RootConstrainSelectedInstOperands, |
| 48037 | // GIR_Coverage, 4261, |
| 48038 | GIR_EraseRootFromParent_Done, |
| 48039 | // Label 2611: @154891 |
| 48040 | GIM_Try, /*On fail goto*//*Label 2612*/ GIMT_Encode4(154950), // Rule ID 4263 // |
| 48041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48042 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48043 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48044 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48046 | // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_OFFSET v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET), |
| 48048 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48054 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48055 | GIR_RootConstrainSelectedInstOperands, |
| 48056 | // GIR_Coverage, 4263, |
| 48057 | GIR_EraseRootFromParent_Done, |
| 48058 | // Label 2612: @154950 |
| 48059 | GIM_Try, /*On fail goto*//*Label 2613*/ GIMT_Encode4(155006), // Rule ID 4265 // |
| 48060 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48061 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48062 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48064 | // (st v2bf16:{ *:[v2bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORD_VBUFFER_OFFSET v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET), |
| 48066 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48071 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48073 | GIR_RootConstrainSelectedInstOperands, |
| 48074 | // GIR_Coverage, 4265, |
| 48075 | GIR_EraseRootFromParent_Done, |
| 48076 | // Label 2613: @155006 |
| 48077 | GIM_Try, /*On fail goto*//*Label 2614*/ GIMT_Encode4(155061), // Rule ID 7511 // |
| 48078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 48079 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48080 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48081 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48082 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48084 | // (AMDGPUst_glue v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 48086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48087 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48090 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48091 | GIR_RootConstrainSelectedInstOperands, |
| 48092 | // GIR_Coverage, 7511, |
| 48093 | GIR_EraseRootFromParent_Done, |
| 48094 | // Label 2614: @155061 |
| 48095 | GIM_Try, /*On fail goto*//*Label 2615*/ GIMT_Encode4(155116), // Rule ID 7513 // |
| 48096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 48097 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48098 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48099 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48100 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48102 | // (AMDGPUst_glue v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 48104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48105 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48108 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48109 | GIR_RootConstrainSelectedInstOperands, |
| 48110 | // GIR_Coverage, 7513, |
| 48111 | GIR_EraseRootFromParent_Done, |
| 48112 | // Label 2615: @155116 |
| 48113 | GIM_Try, /*On fail goto*//*Label 2616*/ GIMT_Encode4(155171), // Rule ID 7515 // |
| 48114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 48115 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48116 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48117 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48118 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48120 | // (AMDGPUst_glue v2bf16:{ *:[v2bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32), |
| 48122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48123 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48127 | GIR_RootConstrainSelectedInstOperands, |
| 48128 | // GIR_Coverage, 7515, |
| 48129 | GIR_EraseRootFromParent_Done, |
| 48130 | // Label 2616: @155171 |
| 48131 | GIM_Try, /*On fail goto*//*Label 2617*/ GIMT_Encode4(155222), // Rule ID 7512 // |
| 48132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48133 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48134 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48135 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48136 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48137 | // (st v2i16:{ *:[v2i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 48139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48140 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48143 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48144 | GIR_RootConstrainSelectedInstOperands, |
| 48145 | // GIR_Coverage, 7512, |
| 48146 | GIR_EraseRootFromParent_Done, |
| 48147 | // Label 2617: @155222 |
| 48148 | GIM_Try, /*On fail goto*//*Label 2618*/ GIMT_Encode4(155273), // Rule ID 7514 // |
| 48149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48150 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48151 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48152 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48154 | // (st v2f16:{ *:[v2f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 48156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48157 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48160 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48161 | GIR_RootConstrainSelectedInstOperands, |
| 48162 | // GIR_Coverage, 7514, |
| 48163 | GIR_EraseRootFromParent_Done, |
| 48164 | // Label 2618: @155273 |
| 48165 | GIM_Try, /*On fail goto*//*Label 2619*/ GIMT_Encode4(155324), // Rule ID 7516 // |
| 48166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48167 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48168 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48169 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48170 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48171 | // (st v2bf16:{ *:[v2bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B32_gfx9), |
| 48173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48174 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48177 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48178 | GIR_RootConstrainSelectedInstOperands, |
| 48179 | // GIR_Coverage, 7516, |
| 48180 | GIR_EraseRootFromParent_Done, |
| 48181 | // Label 2619: @155324 |
| 48182 | GIM_Try, /*On fail goto*//*Label 2620*/ GIMT_Encode4(155380), // Rule ID 3459 // |
| 48183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48184 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48185 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48186 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 48188 | // (st v2i16:{ *:[v2i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 48190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 48191 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48196 | GIR_RootConstrainSelectedInstOperands, |
| 48197 | // GIR_Coverage, 3459, |
| 48198 | GIR_EraseRootFromParent_Done, |
| 48199 | // Label 2620: @155380 |
| 48200 | GIM_Try, /*On fail goto*//*Label 2621*/ GIMT_Encode4(155436), // Rule ID 3463 // |
| 48201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48202 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 48206 | // (st v2f16:{ *:[v2f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 48208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 48209 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48213 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48214 | GIR_RootConstrainSelectedInstOperands, |
| 48215 | // GIR_Coverage, 3463, |
| 48216 | GIR_EraseRootFromParent_Done, |
| 48217 | // Label 2621: @155436 |
| 48218 | GIM_Try, /*On fail goto*//*Label 2622*/ GIMT_Encode4(155492), // Rule ID 3467 // |
| 48219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48220 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48221 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48222 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48223 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 48224 | // (st v2bf16:{ *:[v2bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD_SADDR), |
| 48226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 48227 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48231 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48232 | GIR_RootConstrainSelectedInstOperands, |
| 48233 | // GIR_Coverage, 3467, |
| 48234 | GIR_EraseRootFromParent_Done, |
| 48235 | // Label 2622: @155492 |
| 48236 | GIM_Try, /*On fail goto*//*Label 2623*/ GIMT_Encode4(155543), // Rule ID 3458 // |
| 48237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48238 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48239 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 48242 | // (st v2i16:{ *:[v2i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 48243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 48244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48245 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48249 | GIR_RootConstrainSelectedInstOperands, |
| 48250 | // GIR_Coverage, 3458, |
| 48251 | GIR_EraseRootFromParent_Done, |
| 48252 | // Label 2623: @155543 |
| 48253 | GIM_Try, /*On fail goto*//*Label 2624*/ GIMT_Encode4(155594), // Rule ID 3462 // |
| 48254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48255 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48256 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48257 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 48259 | // (st v2f16:{ *:[v2f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 48260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 48261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48262 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48266 | GIR_RootConstrainSelectedInstOperands, |
| 48267 | // GIR_Coverage, 3462, |
| 48268 | GIR_EraseRootFromParent_Done, |
| 48269 | // Label 2624: @155594 |
| 48270 | GIM_Try, /*On fail goto*//*Label 2625*/ GIMT_Encode4(155645), // Rule ID 3466 // |
| 48271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48272 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48273 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48274 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48275 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 48276 | // (st v2bf16:{ *:[v2bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 48277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORD), |
| 48278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48279 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48282 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48283 | GIR_RootConstrainSelectedInstOperands, |
| 48284 | // GIR_Coverage, 3466, |
| 48285 | GIR_EraseRootFromParent_Done, |
| 48286 | // Label 2625: @155645 |
| 48287 | GIM_Try, /*On fail goto*//*Label 2626*/ GIMT_Encode4(155697), // Rule ID 3234 // |
| 48288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 48289 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 48290 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48291 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 48293 | // (st v2i16:{ *:[v2i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 48294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 48295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48296 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48300 | GIR_RootConstrainSelectedInstOperands, |
| 48301 | // GIR_Coverage, 3234, |
| 48302 | GIR_EraseRootFromParent_Done, |
| 48303 | // Label 2626: @155697 |
| 48304 | GIM_Try, /*On fail goto*//*Label 2627*/ GIMT_Encode4(155749), // Rule ID 3236 // |
| 48305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 48306 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 48307 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48308 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48309 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 48310 | // (st v2f16:{ *:[v2f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 48311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 48312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48313 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48316 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48317 | GIR_RootConstrainSelectedInstOperands, |
| 48318 | // GIR_Coverage, 3236, |
| 48319 | GIR_EraseRootFromParent_Done, |
| 48320 | // Label 2627: @155749 |
| 48321 | GIM_Try, /*On fail goto*//*Label 2628*/ GIMT_Encode4(155801), // Rule ID 3238 // |
| 48322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 48323 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 48324 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48325 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 48327 | // (st v2bf16:{ *:[v2bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORD ?:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 48328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORD), |
| 48329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48330 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48334 | GIR_RootConstrainSelectedInstOperands, |
| 48335 | // GIR_Coverage, 3238, |
| 48336 | GIR_EraseRootFromParent_Done, |
| 48337 | // Label 2628: @155801 |
| 48338 | GIM_Reject, |
| 48339 | // Label 2280: @155802 |
| 48340 | GIM_Try, /*On fail goto*//*Label 2629*/ GIMT_Encode4(155866), // Rule ID 7693 // |
| 48341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 48342 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48343 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48344 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48345 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48346 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48347 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 48348 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48349 | // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 48351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48352 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48356 | GIR_RootConstrainSelectedInstOperands, |
| 48357 | // GIR_Coverage, 7693, |
| 48358 | GIR_EraseRootFromParent_Done, |
| 48359 | // Label 2629: @155866 |
| 48360 | GIM_Try, /*On fail goto*//*Label 2630*/ GIMT_Encode4(155930), // Rule ID 7697 // |
| 48361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 48362 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48363 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48364 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48365 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48366 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48367 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 48368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48369 | // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 48371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48372 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48376 | GIR_RootConstrainSelectedInstOperands, |
| 48377 | // GIR_Coverage, 7697, |
| 48378 | GIR_EraseRootFromParent_Done, |
| 48379 | // Label 2630: @155930 |
| 48380 | GIM_Try, /*On fail goto*//*Label 2631*/ GIMT_Encode4(155989), // Rule ID 7617 // |
| 48381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 48382 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48383 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48384 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 48385 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48388 | // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 48390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48391 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48395 | GIR_RootConstrainSelectedInstOperands, |
| 48396 | // GIR_Coverage, 7617, |
| 48397 | GIR_EraseRootFromParent_Done, |
| 48398 | // Label 2631: @155989 |
| 48399 | GIM_Try, /*On fail goto*//*Label 2632*/ GIMT_Encode4(156048), // Rule ID 7621 // |
| 48400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 48401 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48402 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48403 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 48404 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48407 | // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 48409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48410 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48414 | GIR_RootConstrainSelectedInstOperands, |
| 48415 | // GIR_Coverage, 7621, |
| 48416 | GIR_EraseRootFromParent_Done, |
| 48417 | // Label 2632: @156048 |
| 48418 | GIM_Try, /*On fail goto*//*Label 2633*/ GIMT_Encode4(156108), // Rule ID 7694 // |
| 48419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 48420 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48421 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48422 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48423 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48424 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 48425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48426 | // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 48428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48429 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48433 | GIR_RootConstrainSelectedInstOperands, |
| 48434 | // GIR_Coverage, 7694, |
| 48435 | GIR_EraseRootFromParent_Done, |
| 48436 | // Label 2633: @156108 |
| 48437 | GIM_Try, /*On fail goto*//*Label 2634*/ GIMT_Encode4(156168), // Rule ID 7698 // |
| 48438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 48439 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48440 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48441 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48443 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 48444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48445 | // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 48447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48448 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48452 | GIR_RootConstrainSelectedInstOperands, |
| 48453 | // GIR_Coverage, 7698, |
| 48454 | GIR_EraseRootFromParent_Done, |
| 48455 | // Label 2634: @156168 |
| 48456 | GIM_Try, /*On fail goto*//*Label 2635*/ GIMT_Encode4(156223), // Rule ID 7618 // |
| 48457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48458 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48459 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 48460 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48463 | // (st v2i32:{ *:[v2i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 48465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48466 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48470 | GIR_RootConstrainSelectedInstOperands, |
| 48471 | // GIR_Coverage, 7618, |
| 48472 | GIR_EraseRootFromParent_Done, |
| 48473 | // Label 2635: @156223 |
| 48474 | GIM_Try, /*On fail goto*//*Label 2636*/ GIMT_Encode4(156278), // Rule ID 7622 // |
| 48475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48476 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48477 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 48478 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48480 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 48481 | // (st v2f32:{ *:[v2f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v2f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 48482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 48483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48484 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48488 | GIR_RootConstrainSelectedInstOperands, |
| 48489 | // GIR_Coverage, 7622, |
| 48490 | GIR_EraseRootFromParent_Done, |
| 48491 | // Label 2636: @156278 |
| 48492 | GIM_Try, /*On fail goto*//*Label 2637*/ GIMT_Encode4(156337), // Rule ID 6332 // |
| 48493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 48494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48495 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 48498 | // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX2_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 48499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 48500 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48507 | GIR_RootConstrainSelectedInstOperands, |
| 48508 | // GIR_Coverage, 6332, |
| 48509 | GIR_EraseRootFromParent_Done, |
| 48510 | // Label 2637: @156337 |
| 48511 | GIM_Try, /*On fail goto*//*Label 2638*/ GIMT_Encode4(156396), // Rule ID 6334 // |
| 48512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 48513 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 48517 | // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 48518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 48519 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48525 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48526 | GIR_RootConstrainSelectedInstOperands, |
| 48527 | // GIR_Coverage, 6334, |
| 48528 | GIR_EraseRootFromParent_Done, |
| 48529 | // Label 2638: @156396 |
| 48530 | GIM_Try, /*On fail goto*//*Label 2639*/ GIMT_Encode4(156452), // Rule ID 3945 // |
| 48531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 48532 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48533 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48534 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 48536 | // (st v2i32:{ *:[v2i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 48538 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 48541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48543 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48544 | GIR_RootConstrainSelectedInstOperands, |
| 48545 | // GIR_Coverage, 3945, |
| 48546 | GIR_EraseRootFromParent_Done, |
| 48547 | // Label 2639: @156452 |
| 48548 | GIM_Try, /*On fail goto*//*Label 2640*/ GIMT_Encode4(156508), // Rule ID 3951 // |
| 48549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 48550 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48551 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48552 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 48554 | // (st v2f32:{ *:[v2f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 48556 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 48559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48561 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48562 | GIR_RootConstrainSelectedInstOperands, |
| 48563 | // GIR_Coverage, 3951, |
| 48564 | GIR_EraseRootFromParent_Done, |
| 48565 | // Label 2640: @156508 |
| 48566 | GIM_Try, /*On fail goto*//*Label 2641*/ GIMT_Encode4(156559), // Rule ID 3944 // |
| 48567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 48568 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48569 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48570 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 48572 | // (st v2i32:{ *:[v2i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 48574 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48578 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48579 | GIR_RootConstrainSelectedInstOperands, |
| 48580 | // GIR_Coverage, 3944, |
| 48581 | GIR_EraseRootFromParent_Done, |
| 48582 | // Label 2641: @156559 |
| 48583 | GIM_Try, /*On fail goto*//*Label 2642*/ GIMT_Encode4(156610), // Rule ID 3950 // |
| 48584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 48585 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48586 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48587 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48588 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 48589 | // (st v2f32:{ *:[v2f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 48591 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48596 | GIR_RootConstrainSelectedInstOperands, |
| 48597 | // GIR_Coverage, 3950, |
| 48598 | GIR_EraseRootFromParent_Done, |
| 48599 | // Label 2642: @156610 |
| 48600 | GIM_Try, /*On fail goto*//*Label 2643*/ GIMT_Encode4(156661), // Rule ID 3943 // |
| 48601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 48602 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48603 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48604 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 48606 | // (st v2i32:{ *:[v2i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 48607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 48608 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48612 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48613 | GIR_RootConstrainSelectedInstOperands, |
| 48614 | // GIR_Coverage, 3943, |
| 48615 | GIR_EraseRootFromParent_Done, |
| 48616 | // Label 2643: @156661 |
| 48617 | GIM_Try, /*On fail goto*//*Label 2644*/ GIMT_Encode4(156712), // Rule ID 3949 // |
| 48618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 48619 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48620 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 48623 | // (st v2f32:{ *:[v2f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 48624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 48625 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48629 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48630 | GIR_RootConstrainSelectedInstOperands, |
| 48631 | // GIR_Coverage, 3949, |
| 48632 | GIR_EraseRootFromParent_Done, |
| 48633 | // Label 2644: @156712 |
| 48634 | GIM_Try, /*On fail goto*//*Label 2645*/ GIMT_Encode4(156776), // Rule ID 4292 // |
| 48635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48636 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48637 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48638 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48639 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 48640 | // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 48642 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48650 | GIR_RootConstrainSelectedInstOperands, |
| 48651 | // GIR_Coverage, 4292, |
| 48652 | GIR_EraseRootFromParent_Done, |
| 48653 | // Label 2645: @156776 |
| 48654 | GIM_Try, /*On fail goto*//*Label 2646*/ GIMT_Encode4(156837), // Rule ID 4294 // |
| 48655 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48656 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 48659 | // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2i32:{ *:[v2i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 48661 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48669 | GIR_RootConstrainSelectedInstOperands, |
| 48670 | // GIR_Coverage, 4294, |
| 48671 | GIR_EraseRootFromParent_Done, |
| 48672 | // Label 2646: @156837 |
| 48673 | GIM_Try, /*On fail goto*//*Label 2647*/ GIMT_Encode4(156901), // Rule ID 4296 // |
| 48674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48675 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48676 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 48679 | // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 48681 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48689 | GIR_RootConstrainSelectedInstOperands, |
| 48690 | // GIR_Coverage, 4296, |
| 48691 | GIR_EraseRootFromParent_Done, |
| 48692 | // Label 2647: @156901 |
| 48693 | GIM_Try, /*On fail goto*//*Label 2648*/ GIMT_Encode4(156962), // Rule ID 4298 // |
| 48694 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 48698 | // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v2f32:{ *:[v2f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 48700 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48707 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48708 | GIR_RootConstrainSelectedInstOperands, |
| 48709 | // GIR_Coverage, 4298, |
| 48710 | GIR_EraseRootFromParent_Done, |
| 48711 | // Label 2648: @156962 |
| 48712 | GIM_Try, /*On fail goto*//*Label 2649*/ GIMT_Encode4(157026), // Rule ID 6331 // |
| 48713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 48714 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 48718 | // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX2_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 48719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN), |
| 48720 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48727 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48728 | GIR_RootConstrainSelectedInstOperands, |
| 48729 | // GIR_Coverage, 6331, |
| 48730 | GIR_EraseRootFromParent_Done, |
| 48731 | // Label 2649: @157026 |
| 48732 | GIM_Try, /*On fail goto*//*Label 2650*/ GIMT_Encode4(157090), // Rule ID 6333 // |
| 48733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 48734 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 48735 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 48738 | // (st v2i32:{ *:[v2i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN VReg_64:{ *:[v2i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 48739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN), |
| 48740 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 48741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 48742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 48744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 48745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48747 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48748 | GIR_RootConstrainSelectedInstOperands, |
| 48749 | // GIR_Coverage, 6333, |
| 48750 | GIR_EraseRootFromParent_Done, |
| 48751 | // Label 2650: @157090 |
| 48752 | GIM_Try, /*On fail goto*//*Label 2651*/ GIMT_Encode4(157210), // Rule ID 7552 // |
| 48753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 48754 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48755 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48756 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 48759 | // (AMDGPUst_glue v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 48760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48761 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 48762 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48763 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48764 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 48765 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48766 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48769 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 48770 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48771 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 48773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48774 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48775 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 48777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 48778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48780 | GIR_RootConstrainSelectedInstOperands, |
| 48781 | // GIR_Coverage, 7552, |
| 48782 | GIR_EraseRootFromParent_Done, |
| 48783 | // Label 2651: @157210 |
| 48784 | GIM_Try, /*On fail goto*//*Label 2652*/ GIMT_Encode4(157330), // Rule ID 7556 // |
| 48785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 48786 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 48787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48788 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 48791 | // (AMDGPUst_glue v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 48792 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48793 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 48794 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48795 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48796 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 48797 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48798 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48800 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48801 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 48802 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48803 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 48805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48806 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48807 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 48809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 48810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48811 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48812 | GIR_RootConstrainSelectedInstOperands, |
| 48813 | // GIR_Coverage, 7556, |
| 48814 | GIR_EraseRootFromParent_Done, |
| 48815 | // Label 2652: @157330 |
| 48816 | GIM_Try, /*On fail goto*//*Label 2653*/ GIMT_Encode4(157389), // Rule ID 4291 // |
| 48817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48818 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48819 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48820 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48821 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48822 | // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 48824 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48831 | GIR_RootConstrainSelectedInstOperands, |
| 48832 | // GIR_Coverage, 4291, |
| 48833 | GIR_EraseRootFromParent_Done, |
| 48834 | // Label 2653: @157389 |
| 48835 | GIM_Try, /*On fail goto*//*Label 2654*/ GIMT_Encode4(157445), // Rule ID 4293 // |
| 48836 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48837 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48838 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48840 | // (st v2i32:{ *:[v2i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 48842 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48849 | GIR_RootConstrainSelectedInstOperands, |
| 48850 | // GIR_Coverage, 4293, |
| 48851 | GIR_EraseRootFromParent_Done, |
| 48852 | // Label 2654: @157445 |
| 48853 | GIM_Try, /*On fail goto*//*Label 2655*/ GIMT_Encode4(157504), // Rule ID 4295 // |
| 48854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 48855 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48856 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48859 | // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 48861 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48868 | GIR_RootConstrainSelectedInstOperands, |
| 48869 | // GIR_Coverage, 4295, |
| 48870 | GIR_EraseRootFromParent_Done, |
| 48871 | // Label 2655: @157504 |
| 48872 | GIM_Try, /*On fail goto*//*Label 2656*/ GIMT_Encode4(157560), // Rule ID 4297 // |
| 48873 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48874 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48875 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48876 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 48877 | // (st v2f32:{ *:[v2f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 48878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 48879 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 48880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 48881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 48882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48885 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48886 | GIR_RootConstrainSelectedInstOperands, |
| 48887 | // GIR_Coverage, 4297, |
| 48888 | GIR_EraseRootFromParent_Done, |
| 48889 | // Label 2656: @157560 |
| 48890 | GIM_Try, /*On fail goto*//*Label 2657*/ GIMT_Encode4(157676), // Rule ID 7554 // |
| 48891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48892 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48893 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48894 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48895 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 48896 | // (st v2i32:{ *:[v2i32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2i32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 48897 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48898 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 48899 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48900 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48901 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 48902 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48903 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48906 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 48907 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48908 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 48910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48912 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 48914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 48915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48917 | GIR_RootConstrainSelectedInstOperands, |
| 48918 | // GIR_Coverage, 7554, |
| 48919 | GIR_EraseRootFromParent_Done, |
| 48920 | // Label 2657: @157676 |
| 48921 | GIM_Try, /*On fail goto*//*Label 2658*/ GIMT_Encode4(157792), // Rule ID 7558 // |
| 48922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 48923 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 48924 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 48927 | // (st v2f32:{ *:[v2f32] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v2f32] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 48928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 48929 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 48930 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48931 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48932 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 48933 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48934 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48935 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 48936 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 48937 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 48938 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 48939 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 48940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 48941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 48942 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 48943 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 48944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 48945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 48946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48948 | GIR_RootConstrainSelectedInstOperands, |
| 48949 | // GIR_Coverage, 7558, |
| 48950 | GIR_EraseRootFromParent_Done, |
| 48951 | // Label 2658: @157792 |
| 48952 | GIM_Try, /*On fail goto*//*Label 2659*/ GIMT_Encode4(157848), // Rule ID 3495 // |
| 48953 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48954 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48955 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48956 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48957 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 48958 | // (st v2i32:{ *:[v2i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 48960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 48961 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48965 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48966 | GIR_RootConstrainSelectedInstOperands, |
| 48967 | // GIR_Coverage, 3495, |
| 48968 | GIR_EraseRootFromParent_Done, |
| 48969 | // Label 2659: @157848 |
| 48970 | GIM_Try, /*On fail goto*//*Label 2660*/ GIMT_Encode4(157904), // Rule ID 3499 // |
| 48971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48972 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48973 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48974 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48975 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 48976 | // (st v2f32:{ *:[v2f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 48977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 48978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 48979 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 48981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 48982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 48983 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 48984 | GIR_RootConstrainSelectedInstOperands, |
| 48985 | // GIR_Coverage, 3499, |
| 48986 | GIR_EraseRootFromParent_Done, |
| 48987 | // Label 2660: @157904 |
| 48988 | GIM_Try, /*On fail goto*//*Label 2661*/ GIMT_Encode4(157955), // Rule ID 3494 // |
| 48989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 48990 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 48991 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 48992 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 48993 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 48994 | // (st v2i32:{ *:[v2i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 48995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 48996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 48997 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 48998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 48999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49000 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49001 | GIR_RootConstrainSelectedInstOperands, |
| 49002 | // GIR_Coverage, 3494, |
| 49003 | GIR_EraseRootFromParent_Done, |
| 49004 | // Label 2661: @157955 |
| 49005 | GIM_Try, /*On fail goto*//*Label 2662*/ GIMT_Encode4(158006), // Rule ID 3498 // |
| 49006 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 49007 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49008 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49009 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 49011 | // (st v2f32:{ *:[v2f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset) |
| 49012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 49013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49014 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49018 | GIR_RootConstrainSelectedInstOperands, |
| 49019 | // GIR_Coverage, 3498, |
| 49020 | GIR_EraseRootFromParent_Done, |
| 49021 | // Label 2662: @158006 |
| 49022 | GIM_Try, /*On fail goto*//*Label 2663*/ GIMT_Encode4(158058), // Rule ID 3251 // |
| 49023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 49024 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 49025 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 49028 | // (st v2i32:{ *:[v2i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 49029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 49030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49031 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49034 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49035 | GIR_RootConstrainSelectedInstOperands, |
| 49036 | // GIR_Coverage, 3251, |
| 49037 | GIR_EraseRootFromParent_Done, |
| 49038 | // Label 2663: @158058 |
| 49039 | GIM_Try, /*On fail goto*//*Label 2664*/ GIMT_Encode4(158110), // Rule ID 3253 // |
| 49040 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 49041 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 49042 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49043 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 49045 | // (st v2f32:{ *:[v2f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2f32] }:$data, ?:{ *:[i32] }:$offset) |
| 49046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 49047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49048 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49052 | GIR_RootConstrainSelectedInstOperands, |
| 49053 | // GIR_Coverage, 3253, |
| 49054 | GIR_EraseRootFromParent_Done, |
| 49055 | // Label 2664: @158110 |
| 49056 | GIM_Reject, |
| 49057 | // Label 2281: @158111 |
| 49058 | GIM_Try, /*On fail goto*//*Label 2665*/ GIMT_Encode4(158175), // Rule ID 7741 // |
| 49059 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 49060 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49061 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49062 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49063 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49064 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49065 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 49066 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49067 | // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 49069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49070 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49073 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49074 | GIR_RootConstrainSelectedInstOperands, |
| 49075 | // GIR_Coverage, 7741, |
| 49076 | GIR_EraseRootFromParent_Done, |
| 49077 | // Label 2665: @158175 |
| 49078 | GIM_Try, /*On fail goto*//*Label 2666*/ GIMT_Encode4(158239), // Rule ID 7745 // |
| 49079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 49080 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49081 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49082 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49083 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49084 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49085 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 49086 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49087 | // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 49089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49090 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49094 | GIR_RootConstrainSelectedInstOperands, |
| 49095 | // GIR_Coverage, 7745, |
| 49096 | GIR_EraseRootFromParent_Done, |
| 49097 | // Label 2666: @158239 |
| 49098 | GIM_Try, /*On fail goto*//*Label 2667*/ GIMT_Encode4(158298), // Rule ID 7665 // |
| 49099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49100 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49101 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49102 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49103 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49106 | // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 49108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49109 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49113 | GIR_RootConstrainSelectedInstOperands, |
| 49114 | // GIR_Coverage, 7665, |
| 49115 | GIR_EraseRootFromParent_Done, |
| 49116 | // Label 2667: @158298 |
| 49117 | GIM_Try, /*On fail goto*//*Label 2668*/ GIMT_Encode4(158357), // Rule ID 7669 // |
| 49118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49119 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49120 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49121 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49123 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49125 | // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 49127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49128 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49132 | GIR_RootConstrainSelectedInstOperands, |
| 49133 | // GIR_Coverage, 7669, |
| 49134 | GIR_EraseRootFromParent_Done, |
| 49135 | // Label 2668: @158357 |
| 49136 | GIM_Try, /*On fail goto*//*Label 2669*/ GIMT_Encode4(158417), // Rule ID 7742 // |
| 49137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 49138 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49139 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 49143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49144 | // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 49146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49147 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49151 | GIR_RootConstrainSelectedInstOperands, |
| 49152 | // GIR_Coverage, 7742, |
| 49153 | GIR_EraseRootFromParent_Done, |
| 49154 | // Label 2669: @158417 |
| 49155 | GIM_Try, /*On fail goto*//*Label 2670*/ GIMT_Encode4(158477), // Rule ID 7746 // |
| 49156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 49157 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49158 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49159 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49160 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49161 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 49162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49163 | // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 49165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49166 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49170 | GIR_RootConstrainSelectedInstOperands, |
| 49171 | // GIR_Coverage, 7746, |
| 49172 | GIR_EraseRootFromParent_Done, |
| 49173 | // Label 2670: @158477 |
| 49174 | GIM_Try, /*On fail goto*//*Label 2671*/ GIMT_Encode4(158532), // Rule ID 7666 // |
| 49175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 49176 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49177 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49178 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49181 | // (st v2i64:{ *:[v2i64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 49183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49184 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49187 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49188 | GIR_RootConstrainSelectedInstOperands, |
| 49189 | // GIR_Coverage, 7666, |
| 49190 | GIR_EraseRootFromParent_Done, |
| 49191 | // Label 2671: @158532 |
| 49192 | GIM_Try, /*On fail goto*//*Label 2672*/ GIMT_Encode4(158587), // Rule ID 7670 // |
| 49193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 49194 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49195 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49196 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49199 | // (st v2f64:{ *:[v2f64] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v2f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 49201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49202 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49206 | GIR_RootConstrainSelectedInstOperands, |
| 49207 | // GIR_Coverage, 7670, |
| 49208 | GIR_EraseRootFromParent_Done, |
| 49209 | // Label 2672: @158587 |
| 49210 | GIM_Try, /*On fail goto*//*Label 2673*/ GIMT_Encode4(158643), // Rule ID 4008 // |
| 49211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 49212 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49213 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49214 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 49216 | // (st v2i64:{ *:[v2i64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 49218 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 49221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49223 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49224 | GIR_RootConstrainSelectedInstOperands, |
| 49225 | // GIR_Coverage, 4008, |
| 49226 | GIR_EraseRootFromParent_Done, |
| 49227 | // Label 2673: @158643 |
| 49228 | GIM_Try, /*On fail goto*//*Label 2674*/ GIMT_Encode4(158699), // Rule ID 4014 // |
| 49229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 49230 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49231 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49232 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 49234 | // (st v2f64:{ *:[v2f64] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 49236 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 49239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49241 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49242 | GIR_RootConstrainSelectedInstOperands, |
| 49243 | // GIR_Coverage, 4014, |
| 49244 | GIR_EraseRootFromParent_Done, |
| 49245 | // Label 2674: @158699 |
| 49246 | GIM_Try, /*On fail goto*//*Label 2675*/ GIMT_Encode4(158750), // Rule ID 4007 // |
| 49247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49248 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49249 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49250 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49251 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 49252 | // (st v2i64:{ *:[v2i64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 49254 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 49256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49258 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49259 | GIR_RootConstrainSelectedInstOperands, |
| 49260 | // GIR_Coverage, 4007, |
| 49261 | GIR_EraseRootFromParent_Done, |
| 49262 | // Label 2675: @158750 |
| 49263 | GIM_Try, /*On fail goto*//*Label 2676*/ GIMT_Encode4(158801), // Rule ID 4013 // |
| 49264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49265 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49266 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49267 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 49269 | // (st v2f64:{ *:[v2f64] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 49271 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 49273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49276 | GIR_RootConstrainSelectedInstOperands, |
| 49277 | // GIR_Coverage, 4013, |
| 49278 | GIR_EraseRootFromParent_Done, |
| 49279 | // Label 2676: @158801 |
| 49280 | GIM_Try, /*On fail goto*//*Label 2677*/ GIMT_Encode4(158852), // Rule ID 4006 // |
| 49281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49282 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49283 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49284 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49285 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 49286 | // (st v2i64:{ *:[v2i64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 49287 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 49288 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49292 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49293 | GIR_RootConstrainSelectedInstOperands, |
| 49294 | // GIR_Coverage, 4006, |
| 49295 | GIR_EraseRootFromParent_Done, |
| 49296 | // Label 2677: @158852 |
| 49297 | GIM_Try, /*On fail goto*//*Label 2678*/ GIMT_Encode4(158903), // Rule ID 4012 // |
| 49298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49299 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49300 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 49303 | // (st v2f64:{ *:[v2f64] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 49304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 49305 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49310 | GIR_RootConstrainSelectedInstOperands, |
| 49311 | // GIR_Coverage, 4012, |
| 49312 | GIR_EraseRootFromParent_Done, |
| 49313 | // Label 2678: @158903 |
| 49314 | GIM_Try, /*On fail goto*//*Label 2679*/ GIMT_Encode4(158967), // Rule ID 4340 // |
| 49315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49316 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49317 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49318 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49320 | // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 49322 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49330 | GIR_RootConstrainSelectedInstOperands, |
| 49331 | // GIR_Coverage, 4340, |
| 49332 | GIR_EraseRootFromParent_Done, |
| 49333 | // Label 2679: @158967 |
| 49334 | GIM_Try, /*On fail goto*//*Label 2680*/ GIMT_Encode4(159028), // Rule ID 4342 // |
| 49335 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49336 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49337 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49339 | // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2i64:{ *:[v2i64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 49341 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49349 | GIR_RootConstrainSelectedInstOperands, |
| 49350 | // GIR_Coverage, 4342, |
| 49351 | GIR_EraseRootFromParent_Done, |
| 49352 | // Label 2680: @159028 |
| 49353 | GIM_Try, /*On fail goto*//*Label 2681*/ GIMT_Encode4(159092), // Rule ID 4344 // |
| 49354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49355 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49356 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49357 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49358 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49359 | // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 49361 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49369 | GIR_RootConstrainSelectedInstOperands, |
| 49370 | // GIR_Coverage, 4344, |
| 49371 | GIR_EraseRootFromParent_Done, |
| 49372 | // Label 2681: @159092 |
| 49373 | GIM_Try, /*On fail goto*//*Label 2682*/ GIMT_Encode4(159153), // Rule ID 4346 // |
| 49374 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49375 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49378 | // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v2f64:{ *:[v2f64] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 49380 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49387 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49388 | GIR_RootConstrainSelectedInstOperands, |
| 49389 | // GIR_Coverage, 4346, |
| 49390 | GIR_EraseRootFromParent_Done, |
| 49391 | // Label 2682: @159153 |
| 49392 | GIM_Try, /*On fail goto*//*Label 2683*/ GIMT_Encode4(159273), // Rule ID 7588 // |
| 49393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49394 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49395 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49396 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49397 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 49399 | // (AMDGPUst_glue v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 49400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 49401 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 49402 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49403 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49404 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 49405 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49406 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49407 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49408 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49409 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 49410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49411 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 49413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49414 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49415 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 49416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 49417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 49418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49420 | GIR_RootConstrainSelectedInstOperands, |
| 49421 | // GIR_Coverage, 7588, |
| 49422 | GIR_EraseRootFromParent_Done, |
| 49423 | // Label 2683: @159273 |
| 49424 | GIM_Try, /*On fail goto*//*Label 2684*/ GIMT_Encode4(159393), // Rule ID 7592 // |
| 49425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49426 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49427 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49428 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49429 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49430 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 49431 | // (AMDGPUst_glue v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 49432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 49433 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 49434 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49435 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49436 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 49437 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49438 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49439 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49440 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49441 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 49442 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49443 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 49445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49447 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 49448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 49449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 49450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49452 | GIR_RootConstrainSelectedInstOperands, |
| 49453 | // GIR_Coverage, 7592, |
| 49454 | GIR_EraseRootFromParent_Done, |
| 49455 | // Label 2684: @159393 |
| 49456 | GIM_Try, /*On fail goto*//*Label 2685*/ GIMT_Encode4(159452), // Rule ID 4339 // |
| 49457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49458 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49459 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49460 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 49462 | // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 49464 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49471 | GIR_RootConstrainSelectedInstOperands, |
| 49472 | // GIR_Coverage, 4339, |
| 49473 | GIR_EraseRootFromParent_Done, |
| 49474 | // Label 2685: @159452 |
| 49475 | GIM_Try, /*On fail goto*//*Label 2686*/ GIMT_Encode4(159508), // Rule ID 4341 // |
| 49476 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49477 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49478 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49479 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 49480 | // (st v2i64:{ *:[v2i64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 49482 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49489 | GIR_RootConstrainSelectedInstOperands, |
| 49490 | // GIR_Coverage, 4341, |
| 49491 | GIR_EraseRootFromParent_Done, |
| 49492 | // Label 2686: @159508 |
| 49493 | GIM_Try, /*On fail goto*//*Label 2687*/ GIMT_Encode4(159567), // Rule ID 4343 // |
| 49494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49495 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49496 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 49499 | // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 49501 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49508 | GIR_RootConstrainSelectedInstOperands, |
| 49509 | // GIR_Coverage, 4343, |
| 49510 | GIR_EraseRootFromParent_Done, |
| 49511 | // Label 2687: @159567 |
| 49512 | GIM_Try, /*On fail goto*//*Label 2688*/ GIMT_Encode4(159623), // Rule ID 4345 // |
| 49513 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 49517 | // (st v2f64:{ *:[v2f64] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 49519 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49525 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49526 | GIR_RootConstrainSelectedInstOperands, |
| 49527 | // GIR_Coverage, 4345, |
| 49528 | GIR_EraseRootFromParent_Done, |
| 49529 | // Label 2688: @159623 |
| 49530 | GIM_Try, /*On fail goto*//*Label 2689*/ GIMT_Encode4(159739), // Rule ID 7590 // |
| 49531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 49532 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49533 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49534 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 49536 | // (st v2i64:{ *:[v2i64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2i64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 49537 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 49538 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 49539 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49540 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49541 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 49542 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49543 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49546 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 49547 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49548 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 49550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49551 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49552 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 49553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 49554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 49555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49557 | GIR_RootConstrainSelectedInstOperands, |
| 49558 | // GIR_Coverage, 7590, |
| 49559 | GIR_EraseRootFromParent_Done, |
| 49560 | // Label 2689: @159739 |
| 49561 | GIM_Try, /*On fail goto*//*Label 2690*/ GIMT_Encode4(159855), // Rule ID 7594 // |
| 49562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 49563 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49564 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 49567 | // (st v2f64:{ *:[v2f64] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v2f64] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 49568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 49569 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 49570 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49571 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49572 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 49573 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49574 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 49576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 49577 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 49578 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 49579 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 49580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 49581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49582 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 49583 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 49584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 49585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 49586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49587 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49588 | GIR_RootConstrainSelectedInstOperands, |
| 49589 | // GIR_Coverage, 7594, |
| 49590 | GIR_EraseRootFromParent_Done, |
| 49591 | // Label 2690: @159855 |
| 49592 | GIM_Try, /*On fail goto*//*Label 2691*/ GIMT_Encode4(159911), // Rule ID 3537 // |
| 49593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 49594 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49595 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 49598 | // (st v2i64:{ *:[v2i64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 49600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 49601 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 49603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49605 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49606 | GIR_RootConstrainSelectedInstOperands, |
| 49607 | // GIR_Coverage, 3537, |
| 49608 | GIR_EraseRootFromParent_Done, |
| 49609 | // Label 2691: @159911 |
| 49610 | GIM_Try, /*On fail goto*//*Label 2692*/ GIMT_Encode4(159967), // Rule ID 3541 // |
| 49611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 49612 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49613 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 49616 | // (st v2f64:{ *:[v2f64] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 49618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 49619 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 49621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49623 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49624 | GIR_RootConstrainSelectedInstOperands, |
| 49625 | // GIR_Coverage, 3541, |
| 49626 | GIR_EraseRootFromParent_Done, |
| 49627 | // Label 2692: @159967 |
| 49628 | GIM_Try, /*On fail goto*//*Label 2693*/ GIMT_Encode4(160018), // Rule ID 3536 // |
| 49629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 49630 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49631 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49632 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 49634 | // (st v2i64:{ *:[v2i64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 49635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 49636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49637 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49641 | GIR_RootConstrainSelectedInstOperands, |
| 49642 | // GIR_Coverage, 3536, |
| 49643 | GIR_EraseRootFromParent_Done, |
| 49644 | // Label 2693: @160018 |
| 49645 | GIM_Try, /*On fail goto*//*Label 2694*/ GIMT_Encode4(160069), // Rule ID 3540 // |
| 49646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 49647 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49648 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49649 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 49651 | // (st v2f64:{ *:[v2f64] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset) |
| 49652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 49653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49654 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49657 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49658 | GIR_RootConstrainSelectedInstOperands, |
| 49659 | // GIR_Coverage, 3540, |
| 49660 | GIR_EraseRootFromParent_Done, |
| 49661 | // Label 2694: @160069 |
| 49662 | GIM_Try, /*On fail goto*//*Label 2695*/ GIMT_Encode4(160121), // Rule ID 3273 // |
| 49663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 49664 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 49665 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49666 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49667 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 49668 | // (st v2i64:{ *:[v2i64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 49669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 49670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49671 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49675 | GIR_RootConstrainSelectedInstOperands, |
| 49676 | // GIR_Coverage, 3273, |
| 49677 | GIR_EraseRootFromParent_Done, |
| 49678 | // Label 2695: @160121 |
| 49679 | GIM_Try, /*On fail goto*//*Label 2696*/ GIMT_Encode4(160173), // Rule ID 3275 // |
| 49680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 49681 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 49682 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49683 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 49685 | // (st v2f64:{ *:[v2f64] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2f64] }:$data, ?:{ *:[i32] }:$offset) |
| 49686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 49687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49688 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49692 | GIR_RootConstrainSelectedInstOperands, |
| 49693 | // GIR_Coverage, 3275, |
| 49694 | GIR_EraseRootFromParent_Done, |
| 49695 | // Label 2696: @160173 |
| 49696 | GIM_Reject, |
| 49697 | // Label 2282: @160174 |
| 49698 | GIM_Try, /*On fail goto*//*Label 2697*/ GIMT_Encode4(160229), // Rule ID 7725 // |
| 49699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 49700 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49701 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49702 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49705 | // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96), |
| 49707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49708 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49712 | GIR_RootConstrainSelectedInstOperands, |
| 49713 | // GIR_Coverage, 7725, |
| 49714 | GIR_EraseRootFromParent_Done, |
| 49715 | // Label 2697: @160229 |
| 49716 | GIM_Try, /*On fail goto*//*Label 2698*/ GIMT_Encode4(160284), // Rule ID 7729 // |
| 49717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 49718 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49719 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49720 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49723 | // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96), |
| 49725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49726 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49729 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49730 | GIR_RootConstrainSelectedInstOperands, |
| 49731 | // GIR_Coverage, 7729, |
| 49732 | GIR_EraseRootFromParent_Done, |
| 49733 | // Label 2698: @160284 |
| 49734 | GIM_Try, /*On fail goto*//*Label 2699*/ GIMT_Encode4(160343), // Rule ID 7649 // |
| 49735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49736 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49737 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49738 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49739 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49742 | // (AMDGPUst_glue v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96), |
| 49744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49745 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49749 | GIR_RootConstrainSelectedInstOperands, |
| 49750 | // GIR_Coverage, 7649, |
| 49751 | GIR_EraseRootFromParent_Done, |
| 49752 | // Label 2699: @160343 |
| 49753 | GIM_Try, /*On fail goto*//*Label 2700*/ GIMT_Encode4(160402), // Rule ID 7653 // |
| 49754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 49755 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 49756 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49757 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49758 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49759 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49761 | // (AMDGPUst_glue v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B96 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96), |
| 49763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49764 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49767 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49768 | GIR_RootConstrainSelectedInstOperands, |
| 49769 | // GIR_Coverage, 7653, |
| 49770 | GIR_EraseRootFromParent_Done, |
| 49771 | // Label 2700: @160402 |
| 49772 | GIM_Try, /*On fail goto*//*Label 2701*/ GIMT_Encode4(160453), // Rule ID 7726 // |
| 49773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 49774 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49775 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49776 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49777 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49778 | // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9), |
| 49780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49781 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49785 | GIR_RootConstrainSelectedInstOperands, |
| 49786 | // GIR_Coverage, 7726, |
| 49787 | GIR_EraseRootFromParent_Done, |
| 49788 | // Label 2701: @160453 |
| 49789 | GIM_Try, /*On fail goto*//*Label 2702*/ GIMT_Encode4(160504), // Rule ID 7730 // |
| 49790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 49791 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49792 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49793 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49795 | // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9), |
| 49797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49798 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49802 | GIR_RootConstrainSelectedInstOperands, |
| 49803 | // GIR_Coverage, 7730, |
| 49804 | GIR_EraseRootFromParent_Done, |
| 49805 | // Label 2702: @160504 |
| 49806 | GIM_Try, /*On fail goto*//*Label 2703*/ GIMT_Encode4(160559), // Rule ID 7650 // |
| 49807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 49808 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49809 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49810 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49811 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49813 | // (st v3i32:{ *:[v3i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9), |
| 49815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49816 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49820 | GIR_RootConstrainSelectedInstOperands, |
| 49821 | // GIR_Coverage, 7650, |
| 49822 | GIR_EraseRootFromParent_Done, |
| 49823 | // Label 2703: @160559 |
| 49824 | GIM_Try, /*On fail goto*//*Label 2704*/ GIMT_Encode4(160614), // Rule ID 7654 // |
| 49825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 49826 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 49827 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 49828 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 49831 | // (st v3f32:{ *:[v3f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B96_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15874:{ *:[v3f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 49832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B96_gfx9), |
| 49833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 49834 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49838 | GIR_RootConstrainSelectedInstOperands, |
| 49839 | // GIR_Coverage, 7654, |
| 49840 | GIR_EraseRootFromParent_Done, |
| 49841 | // Label 2704: @160614 |
| 49842 | GIM_Try, /*On fail goto*//*Label 2705*/ GIMT_Encode4(160673), // Rule ID 6336 // |
| 49843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 49844 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49845 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 49848 | // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX3_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 49849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET), |
| 49850 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49857 | GIR_RootConstrainSelectedInstOperands, |
| 49858 | // GIR_Coverage, 6336, |
| 49859 | GIR_EraseRootFromParent_Done, |
| 49860 | // Label 2705: @160673 |
| 49861 | GIM_Try, /*On fail goto*//*Label 2706*/ GIMT_Encode4(160732), // Rule ID 6338 // |
| 49862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 49863 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49864 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49865 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 49867 | // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET VReg_96:{ *:[v3i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 49868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET), |
| 49869 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 49870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 49872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49875 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49876 | GIR_RootConstrainSelectedInstOperands, |
| 49877 | // GIR_Coverage, 6338, |
| 49878 | GIR_EraseRootFromParent_Done, |
| 49879 | // Label 2706: @160732 |
| 49880 | GIM_Try, /*On fail goto*//*Label 2707*/ GIMT_Encode4(160788), // Rule ID 4047 // |
| 49881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 49882 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49883 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49884 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49885 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 49886 | // (st v3i32:{ *:[v3i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX3_SVS anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SVS), |
| 49888 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 49891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 49892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49893 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49894 | GIR_RootConstrainSelectedInstOperands, |
| 49895 | // GIR_Coverage, 4047, |
| 49896 | GIR_EraseRootFromParent_Done, |
| 49897 | // Label 2707: @160788 |
| 49898 | GIM_Try, /*On fail goto*//*Label 2708*/ GIMT_Encode4(160839), // Rule ID 4046 // |
| 49899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49900 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49901 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49902 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49903 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 49904 | // (st v3i32:{ *:[v3i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX3_SADDR anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 49905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3_SADDR), |
| 49906 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 49908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49910 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49911 | GIR_RootConstrainSelectedInstOperands, |
| 49912 | // GIR_Coverage, 4046, |
| 49913 | GIR_EraseRootFromParent_Done, |
| 49914 | // Label 2708: @160839 |
| 49915 | GIM_Try, /*On fail goto*//*Label 2709*/ GIMT_Encode4(160890), // Rule ID 4045 // |
| 49916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 49917 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 49918 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49919 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 49921 | // (st v3i32:{ *:[v3i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX3 anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 49922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX3), |
| 49923 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 49924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 49925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 49926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49927 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49928 | GIR_RootConstrainSelectedInstOperands, |
| 49929 | // GIR_Coverage, 4045, |
| 49930 | GIR_EraseRootFromParent_Done, |
| 49931 | // Label 2709: @160890 |
| 49932 | GIM_Try, /*On fail goto*//*Label 2710*/ GIMT_Encode4(160954), // Rule ID 4324 // |
| 49933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49934 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49935 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49936 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49937 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49938 | // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64), |
| 49940 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49948 | GIR_RootConstrainSelectedInstOperands, |
| 49949 | // GIR_Coverage, 4324, |
| 49950 | GIR_EraseRootFromParent_Done, |
| 49951 | // Label 2710: @160954 |
| 49952 | GIM_Try, /*On fail goto*//*Label 2711*/ GIMT_Encode4(161015), // Rule ID 4326 // |
| 49953 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49954 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49957 | // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3i32:{ *:[v3i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64), |
| 49959 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49966 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49967 | GIR_RootConstrainSelectedInstOperands, |
| 49968 | // GIR_Coverage, 4326, |
| 49969 | GIR_EraseRootFromParent_Done, |
| 49970 | // Label 2711: @161015 |
| 49971 | GIM_Try, /*On fail goto*//*Label 2712*/ GIMT_Encode4(161079), // Rule ID 4328 // |
| 49972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 49973 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49974 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49975 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49977 | // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_ADDR64), |
| 49979 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 49981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 49982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 49983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 49984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 49986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 49987 | GIR_RootConstrainSelectedInstOperands, |
| 49988 | // GIR_Coverage, 4328, |
| 49989 | GIR_EraseRootFromParent_Done, |
| 49990 | // Label 2712: @161079 |
| 49991 | GIM_Try, /*On fail goto*//*Label 2713*/ GIMT_Encode4(161140), // Rule ID 4330 // |
| 49992 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 49993 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 49994 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 49995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 49996 | // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_VBUFFER_ADDR64 v3f32:{ *:[v3f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 49997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_ADDR64), |
| 49998 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 49999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50005 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50006 | GIR_RootConstrainSelectedInstOperands, |
| 50007 | // GIR_Coverage, 4330, |
| 50008 | GIR_EraseRootFromParent_Done, |
| 50009 | // Label 2713: @161140 |
| 50010 | GIM_Try, /*On fail goto*//*Label 2714*/ GIMT_Encode4(161204), // Rule ID 6335 // |
| 50011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 50012 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50013 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50014 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 50016 | // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX3_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 50017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN), |
| 50018 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50025 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50026 | GIR_RootConstrainSelectedInstOperands, |
| 50027 | // GIR_Coverage, 6335, |
| 50028 | GIR_EraseRootFromParent_Done, |
| 50029 | // Label 2714: @161204 |
| 50030 | GIM_Try, /*On fail goto*//*Label 2715*/ GIMT_Encode4(161268), // Rule ID 6337 // |
| 50031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 50032 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50033 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50034 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 50036 | // (st v3i32:{ *:[v3i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN VReg_96:{ *:[v3i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 50037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN), |
| 50038 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50046 | GIR_RootConstrainSelectedInstOperands, |
| 50047 | // GIR_Coverage, 6337, |
| 50048 | GIR_EraseRootFromParent_Done, |
| 50049 | // Label 2715: @161268 |
| 50050 | GIM_Try, /*On fail goto*//*Label 2716*/ GIMT_Encode4(161327), // Rule ID 4323 // |
| 50051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50052 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50053 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50055 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50056 | // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET), |
| 50058 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50065 | GIR_RootConstrainSelectedInstOperands, |
| 50066 | // GIR_Coverage, 4323, |
| 50067 | GIR_EraseRootFromParent_Done, |
| 50068 | // Label 2716: @161327 |
| 50069 | GIM_Try, /*On fail goto*//*Label 2717*/ GIMT_Encode4(161383), // Rule ID 4325 // |
| 50070 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50071 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50074 | // (st v3i32:{ *:[v3i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET), |
| 50076 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50082 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50083 | GIR_RootConstrainSelectedInstOperands, |
| 50084 | // GIR_Coverage, 4325, |
| 50085 | GIR_EraseRootFromParent_Done, |
| 50086 | // Label 2717: @161383 |
| 50087 | GIM_Try, /*On fail goto*//*Label 2718*/ GIMT_Encode4(161442), // Rule ID 4327 // |
| 50088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50089 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50090 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50093 | // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET), |
| 50095 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50102 | GIR_RootConstrainSelectedInstOperands, |
| 50103 | // GIR_Coverage, 4327, |
| 50104 | GIR_EraseRootFromParent_Done, |
| 50105 | // Label 2718: @161442 |
| 50106 | GIM_Try, /*On fail goto*//*Label 2719*/ GIMT_Encode4(161498), // Rule ID 4329 // |
| 50107 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50108 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50109 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50111 | // (st v3f32:{ *:[v3f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET), |
| 50113 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50119 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50120 | GIR_RootConstrainSelectedInstOperands, |
| 50121 | // GIR_Coverage, 4329, |
| 50122 | GIR_EraseRootFromParent_Done, |
| 50123 | // Label 2719: @161498 |
| 50124 | GIM_Try, /*On fail goto*//*Label 2720*/ GIMT_Encode4(161554), // Rule ID 3567 // |
| 50125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 50126 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50127 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50128 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 50130 | // (st v3i32:{ *:[v3i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX3_SADDR ?:{ *:[i32] }:$voffset, anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3_SADDR), |
| 50132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 50133 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 50135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50138 | GIR_RootConstrainSelectedInstOperands, |
| 50139 | // GIR_Coverage, 3567, |
| 50140 | GIR_EraseRootFromParent_Done, |
| 50141 | // Label 2720: @161554 |
| 50142 | GIM_Try, /*On fail goto*//*Label 2721*/ GIMT_Encode4(161605), // Rule ID 3566 // |
| 50143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 50144 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50145 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 50148 | // (st v3i32:{ *:[v3i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset) |
| 50149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX3), |
| 50150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50151 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50154 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50155 | GIR_RootConstrainSelectedInstOperands, |
| 50156 | // GIR_Coverage, 3566, |
| 50157 | GIR_EraseRootFromParent_Done, |
| 50158 | // Label 2721: @161605 |
| 50159 | GIM_Try, /*On fail goto*//*Label 2722*/ GIMT_Encode4(161657), // Rule ID 3267 // |
| 50160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 50161 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 50162 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 50165 | // (st v3i32:{ *:[v3i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX3 ?:{ *:[i64] }:$vaddr, anonymous_15874:{ *:[v3i32] }:$data, ?:{ *:[i32] }:$offset) |
| 50166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX3), |
| 50167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50168 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50172 | GIR_RootConstrainSelectedInstOperands, |
| 50173 | // GIR_Coverage, 3267, |
| 50174 | GIR_EraseRootFromParent_Done, |
| 50175 | // Label 2722: @161657 |
| 50176 | GIM_Reject, |
| 50177 | // Label 2283: @161658 |
| 50178 | GIM_Try, /*On fail goto*//*Label 2723*/ GIMT_Encode4(161722), // Rule ID 7701 // |
| 50179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 50180 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50181 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50182 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50183 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50184 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50185 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 50186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50187 | // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50190 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50193 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50194 | GIR_RootConstrainSelectedInstOperands, |
| 50195 | // GIR_Coverage, 7701, |
| 50196 | GIR_EraseRootFromParent_Done, |
| 50197 | // Label 2723: @161722 |
| 50198 | GIM_Try, /*On fail goto*//*Label 2724*/ GIMT_Encode4(161786), // Rule ID 7705 // |
| 50199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 50200 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50201 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50202 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50203 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50204 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50205 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 50206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50207 | // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50210 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50213 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50214 | GIR_RootConstrainSelectedInstOperands, |
| 50215 | // GIR_Coverage, 7705, |
| 50216 | GIR_EraseRootFromParent_Done, |
| 50217 | // Label 2724: @161786 |
| 50218 | GIM_Try, /*On fail goto*//*Label 2725*/ GIMT_Encode4(161850), // Rule ID 7709 // |
| 50219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 50220 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50221 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50222 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50223 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 50226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50227 | // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50230 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50233 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50234 | GIR_RootConstrainSelectedInstOperands, |
| 50235 | // GIR_Coverage, 7709, |
| 50236 | GIR_EraseRootFromParent_Done, |
| 50237 | // Label 2725: @161850 |
| 50238 | GIM_Try, /*On fail goto*//*Label 2726*/ GIMT_Encode4(161909), // Rule ID 7625 // |
| 50239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 50240 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50241 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50242 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50243 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50244 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50246 | // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50249 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50253 | GIR_RootConstrainSelectedInstOperands, |
| 50254 | // GIR_Coverage, 7625, |
| 50255 | GIR_EraseRootFromParent_Done, |
| 50256 | // Label 2726: @161909 |
| 50257 | GIM_Try, /*On fail goto*//*Label 2727*/ GIMT_Encode4(161968), // Rule ID 7629 // |
| 50258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 50259 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50260 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50261 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50262 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50265 | // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50268 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50271 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50272 | GIR_RootConstrainSelectedInstOperands, |
| 50273 | // GIR_Coverage, 7629, |
| 50274 | GIR_EraseRootFromParent_Done, |
| 50275 | // Label 2727: @161968 |
| 50276 | GIM_Try, /*On fail goto*//*Label 2728*/ GIMT_Encode4(162027), // Rule ID 7633 // |
| 50277 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 50278 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50279 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50280 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50284 | // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align8_local_m0>> => (DS_WRITE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64), |
| 50286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50287 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50291 | GIR_RootConstrainSelectedInstOperands, |
| 50292 | // GIR_Coverage, 7633, |
| 50293 | GIR_EraseRootFromParent_Done, |
| 50294 | // Label 2728: @162027 |
| 50295 | GIM_Try, /*On fail goto*//*Label 2729*/ GIMT_Encode4(162087), // Rule ID 7702 // |
| 50296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 50297 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50298 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50299 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50301 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 50302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50303 | // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50306 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50310 | GIR_RootConstrainSelectedInstOperands, |
| 50311 | // GIR_Coverage, 7702, |
| 50312 | GIR_EraseRootFromParent_Done, |
| 50313 | // Label 2729: @162087 |
| 50314 | GIM_Try, /*On fail goto*//*Label 2730*/ GIMT_Encode4(162147), // Rule ID 7706 // |
| 50315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 50316 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50317 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50318 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50320 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 50321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50322 | // (st v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50325 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50328 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50329 | GIR_RootConstrainSelectedInstOperands, |
| 50330 | // GIR_Coverage, 7706, |
| 50331 | GIR_EraseRootFromParent_Done, |
| 50332 | // Label 2730: @162147 |
| 50333 | GIM_Try, /*On fail goto*//*Label 2731*/ GIMT_Encode4(162207), // Rule ID 7710 // |
| 50334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 50335 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50336 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50337 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50338 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50339 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 50340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50341 | // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50344 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50348 | GIR_RootConstrainSelectedInstOperands, |
| 50349 | // GIR_Coverage, 7710, |
| 50350 | GIR_EraseRootFromParent_Done, |
| 50351 | // Label 2731: @162207 |
| 50352 | GIM_Try, /*On fail goto*//*Label 2732*/ GIMT_Encode4(162262), // Rule ID 7626 // |
| 50353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50354 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50355 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50356 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50357 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50358 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50359 | // (st v4f16:{ *:[v4f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50362 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50365 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50366 | GIR_RootConstrainSelectedInstOperands, |
| 50367 | // GIR_Coverage, 7626, |
| 50368 | GIR_EraseRootFromParent_Done, |
| 50369 | // Label 2732: @162262 |
| 50370 | GIM_Try, /*On fail goto*//*Label 2733*/ GIMT_Encode4(162317), // Rule ID 7630 // |
| 50371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50372 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50373 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50374 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50375 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50376 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50377 | // (st v4bf16:{ *:[v4bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50380 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50384 | GIR_RootConstrainSelectedInstOperands, |
| 50385 | // GIR_Coverage, 7630, |
| 50386 | GIR_EraseRootFromParent_Done, |
| 50387 | // Label 2733: @162317 |
| 50388 | GIM_Try, /*On fail goto*//*Label 2734*/ GIMT_Encode4(162372), // Rule ID 7634 // |
| 50389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50390 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50391 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/8, |
| 50392 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 50395 | // (st v4i16:{ *:[v4i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align8_local>> => (DS_WRITE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[v4i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 50396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B64_gfx9), |
| 50397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50398 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 50399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50402 | GIR_RootConstrainSelectedInstOperands, |
| 50403 | // GIR_Coverage, 7634, |
| 50404 | GIR_EraseRootFromParent_Done, |
| 50405 | // Label 2734: @162372 |
| 50406 | GIM_Try, /*On fail goto*//*Label 2735*/ GIMT_Encode4(162428), // Rule ID 3957 // |
| 50407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 50408 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50409 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50410 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 50412 | // (st v4f16:{ *:[v4f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 50414 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 50417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50420 | GIR_RootConstrainSelectedInstOperands, |
| 50421 | // GIR_Coverage, 3957, |
| 50422 | GIR_EraseRootFromParent_Done, |
| 50423 | // Label 2735: @162428 |
| 50424 | GIM_Try, /*On fail goto*//*Label 2736*/ GIMT_Encode4(162484), // Rule ID 3963 // |
| 50425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 50426 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50427 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50428 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50429 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 50430 | // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 50432 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 50435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50437 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50438 | GIR_RootConstrainSelectedInstOperands, |
| 50439 | // GIR_Coverage, 3963, |
| 50440 | GIR_EraseRootFromParent_Done, |
| 50441 | // Label 2736: @162484 |
| 50442 | GIM_Try, /*On fail goto*//*Label 2737*/ GIMT_Encode4(162540), // Rule ID 3969 // |
| 50443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 50444 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50445 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50446 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 50448 | // (st v4i16:{ *:[v4i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SVS anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SVS), |
| 50450 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 50453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50455 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50456 | GIR_RootConstrainSelectedInstOperands, |
| 50457 | // GIR_Coverage, 3969, |
| 50458 | GIR_EraseRootFromParent_Done, |
| 50459 | // Label 2737: @162540 |
| 50460 | GIM_Try, /*On fail goto*//*Label 2738*/ GIMT_Encode4(162591), // Rule ID 3956 // |
| 50461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50462 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50463 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50464 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 50466 | // (st v4f16:{ *:[v4f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 50468 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 50470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50473 | GIR_RootConstrainSelectedInstOperands, |
| 50474 | // GIR_Coverage, 3956, |
| 50475 | GIR_EraseRootFromParent_Done, |
| 50476 | // Label 2738: @162591 |
| 50477 | GIM_Try, /*On fail goto*//*Label 2739*/ GIMT_Encode4(162642), // Rule ID 3962 // |
| 50478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50479 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50480 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50481 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 50483 | // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 50485 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 50487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50490 | GIR_RootConstrainSelectedInstOperands, |
| 50491 | // GIR_Coverage, 3962, |
| 50492 | GIR_EraseRootFromParent_Done, |
| 50493 | // Label 2739: @162642 |
| 50494 | GIM_Try, /*On fail goto*//*Label 2740*/ GIMT_Encode4(162693), // Rule ID 3968 // |
| 50495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50496 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50497 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50498 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 50500 | // (st v4i16:{ *:[v4i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2_SADDR anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2_SADDR), |
| 50502 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 50504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50507 | GIR_RootConstrainSelectedInstOperands, |
| 50508 | // GIR_Coverage, 3968, |
| 50509 | GIR_EraseRootFromParent_Done, |
| 50510 | // Label 2740: @162693 |
| 50511 | GIM_Try, /*On fail goto*//*Label 2741*/ GIMT_Encode4(162744), // Rule ID 3955 // |
| 50512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50513 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50514 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 50517 | // (st v4f16:{ *:[v4f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 50518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 50519 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50523 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50524 | GIR_RootConstrainSelectedInstOperands, |
| 50525 | // GIR_Coverage, 3955, |
| 50526 | GIR_EraseRootFromParent_Done, |
| 50527 | // Label 2741: @162744 |
| 50528 | GIM_Try, /*On fail goto*//*Label 2742*/ GIMT_Encode4(162795), // Rule ID 3961 // |
| 50529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50530 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50531 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50532 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 50534 | // (st v4bf16:{ *:[v4bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 50535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 50536 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50541 | GIR_RootConstrainSelectedInstOperands, |
| 50542 | // GIR_Coverage, 3961, |
| 50543 | GIR_EraseRootFromParent_Done, |
| 50544 | // Label 2742: @162795 |
| 50545 | GIM_Try, /*On fail goto*//*Label 2743*/ GIMT_Encode4(162846), // Rule ID 3967 // |
| 50546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 50547 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 50548 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 50551 | // (st v4i16:{ *:[v4i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX2 anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 50552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX2), |
| 50553 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 50555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 50556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50557 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50558 | GIR_RootConstrainSelectedInstOperands, |
| 50559 | // GIR_Coverage, 3967, |
| 50560 | GIR_EraseRootFromParent_Done, |
| 50561 | // Label 2743: @162846 |
| 50562 | GIM_Try, /*On fail goto*//*Label 2744*/ GIMT_Encode4(162910), // Rule ID 4300 // |
| 50563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50564 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50565 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50566 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50568 | // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 50570 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50577 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50578 | GIR_RootConstrainSelectedInstOperands, |
| 50579 | // GIR_Coverage, 4300, |
| 50580 | GIR_EraseRootFromParent_Done, |
| 50581 | // Label 2744: @162910 |
| 50582 | GIM_Try, /*On fail goto*//*Label 2745*/ GIMT_Encode4(162971), // Rule ID 4302 // |
| 50583 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50584 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50587 | // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4f16:{ *:[v4f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 50589 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50597 | GIR_RootConstrainSelectedInstOperands, |
| 50598 | // GIR_Coverage, 4302, |
| 50599 | GIR_EraseRootFromParent_Done, |
| 50600 | // Label 2745: @162971 |
| 50601 | GIM_Try, /*On fail goto*//*Label 2746*/ GIMT_Encode4(163035), // Rule ID 4304 // |
| 50602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50603 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50604 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50605 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50607 | // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 v4bf16:{ *:[v4bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 50609 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50617 | GIR_RootConstrainSelectedInstOperands, |
| 50618 | // GIR_Coverage, 4304, |
| 50619 | GIR_EraseRootFromParent_Done, |
| 50620 | // Label 2746: @163035 |
| 50621 | GIM_Try, /*On fail goto*//*Label 2747*/ GIMT_Encode4(163096), // Rule ID 4306 // |
| 50622 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50623 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50624 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50626 | // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4bf16:{ *:[v4bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 50628 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50635 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50636 | GIR_RootConstrainSelectedInstOperands, |
| 50637 | // GIR_Coverage, 4306, |
| 50638 | GIR_EraseRootFromParent_Done, |
| 50639 | // Label 2747: @163096 |
| 50640 | GIM_Try, /*On fail goto*//*Label 2748*/ GIMT_Encode4(163160), // Rule ID 4308 // |
| 50641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50642 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50643 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50644 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50645 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50646 | // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_ADDR64), |
| 50648 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50655 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50656 | GIR_RootConstrainSelectedInstOperands, |
| 50657 | // GIR_Coverage, 4308, |
| 50658 | GIR_EraseRootFromParent_Done, |
| 50659 | // Label 2748: @163160 |
| 50660 | GIM_Try, /*On fail goto*//*Label 2749*/ GIMT_Encode4(163221), // Rule ID 4310 // |
| 50661 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50662 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50663 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 50665 | // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_ADDR64 v4i16:{ *:[v4i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_ADDR64), |
| 50667 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 50669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 50671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 50672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50675 | GIR_RootConstrainSelectedInstOperands, |
| 50676 | // GIR_Coverage, 4310, |
| 50677 | GIR_EraseRootFromParent_Done, |
| 50678 | // Label 2749: @163221 |
| 50679 | GIM_Try, /*On fail goto*//*Label 2750*/ GIMT_Encode4(163341), // Rule ID 7560 // |
| 50680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 50681 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50682 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50683 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50686 | // (AMDGPUst_glue v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50687 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50688 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50689 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50690 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50691 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50692 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50693 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50696 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50697 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50698 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 50700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50702 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50707 | GIR_RootConstrainSelectedInstOperands, |
| 50708 | // GIR_Coverage, 7560, |
| 50709 | GIR_EraseRootFromParent_Done, |
| 50710 | // Label 2750: @163341 |
| 50711 | GIM_Try, /*On fail goto*//*Label 2751*/ GIMT_Encode4(163461), // Rule ID 7564 // |
| 50712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 50713 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50714 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50715 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50716 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50718 | // (AMDGPUst_glue v4bf16:{ *:[v4bf16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50719 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50720 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50721 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50722 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50723 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50724 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50725 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50726 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50727 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50728 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50729 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50730 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 50732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50733 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50738 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50739 | GIR_RootConstrainSelectedInstOperands, |
| 50740 | // GIR_Coverage, 7564, |
| 50741 | GIR_EraseRootFromParent_Done, |
| 50742 | // Label 2751: @163461 |
| 50743 | GIM_Try, /*On fail goto*//*Label 2752*/ GIMT_Encode4(163581), // Rule ID 7568 // |
| 50744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 50745 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 50746 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50750 | // (AMDGPUst_glue v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B32 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50751 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50752 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50753 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50754 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50755 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50756 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50757 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50758 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50759 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50760 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50761 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50762 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32), |
| 50764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50765 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50770 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50771 | GIR_RootConstrainSelectedInstOperands, |
| 50772 | // GIR_Coverage, 7568, |
| 50773 | GIR_EraseRootFromParent_Done, |
| 50774 | // Label 2752: @163581 |
| 50775 | GIM_Try, /*On fail goto*//*Label 2753*/ GIMT_Encode4(163640), // Rule ID 4299 // |
| 50776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50777 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50778 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50779 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50780 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50781 | // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 50783 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50789 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50790 | GIR_RootConstrainSelectedInstOperands, |
| 50791 | // GIR_Coverage, 4299, |
| 50792 | GIR_EraseRootFromParent_Done, |
| 50793 | // Label 2753: @163640 |
| 50794 | GIM_Try, /*On fail goto*//*Label 2754*/ GIMT_Encode4(163696), // Rule ID 4301 // |
| 50795 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50796 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50797 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50799 | // (st v4f16:{ *:[v4f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 50801 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50807 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50808 | GIR_RootConstrainSelectedInstOperands, |
| 50809 | // GIR_Coverage, 4301, |
| 50810 | GIR_EraseRootFromParent_Done, |
| 50811 | // Label 2754: @163696 |
| 50812 | GIM_Try, /*On fail goto*//*Label 2755*/ GIMT_Encode4(163755), // Rule ID 4303 // |
| 50813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50814 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50815 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50816 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50817 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50818 | // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 50820 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50826 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50827 | GIR_RootConstrainSelectedInstOperands, |
| 50828 | // GIR_Coverage, 4303, |
| 50829 | GIR_EraseRootFromParent_Done, |
| 50830 | // Label 2755: @163755 |
| 50831 | GIM_Try, /*On fail goto*//*Label 2756*/ GIMT_Encode4(163811), // Rule ID 4305 // |
| 50832 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50833 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50834 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50835 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50836 | // (st v4bf16:{ *:[v4bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 50838 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50845 | GIR_RootConstrainSelectedInstOperands, |
| 50846 | // GIR_Coverage, 4305, |
| 50847 | GIR_EraseRootFromParent_Done, |
| 50848 | // Label 2756: @163811 |
| 50849 | GIM_Try, /*On fail goto*//*Label 2757*/ GIMT_Encode4(163870), // Rule ID 4307 // |
| 50850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 50851 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50852 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50853 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50855 | // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET), |
| 50857 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50864 | GIR_RootConstrainSelectedInstOperands, |
| 50865 | // GIR_Coverage, 4307, |
| 50866 | GIR_EraseRootFromParent_Done, |
| 50867 | // Label 2757: @163870 |
| 50868 | GIM_Try, /*On fail goto*//*Label 2758*/ GIMT_Encode4(163926), // Rule ID 4309 // |
| 50869 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50870 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 50873 | // (st v4i16:{ *:[v4i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 50874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET), |
| 50875 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 50876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 50877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 50878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50882 | GIR_RootConstrainSelectedInstOperands, |
| 50883 | // GIR_Coverage, 4309, |
| 50884 | GIR_EraseRootFromParent_Done, |
| 50885 | // Label 2758: @163926 |
| 50886 | GIM_Try, /*On fail goto*//*Label 2759*/ GIMT_Encode4(164042), // Rule ID 7562 // |
| 50887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50888 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50889 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50890 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50892 | // (st v4f16:{ *:[v4f16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4f16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50893 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50894 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50895 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50896 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50897 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50898 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50899 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50900 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50901 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50902 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50903 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50904 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 50906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50907 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50912 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50913 | GIR_RootConstrainSelectedInstOperands, |
| 50914 | // GIR_Coverage, 7562, |
| 50915 | GIR_EraseRootFromParent_Done, |
| 50916 | // Label 2759: @164042 |
| 50917 | GIM_Try, /*On fail goto*//*Label 2760*/ GIMT_Encode4(164158), // Rule ID 7566 // |
| 50918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50919 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50920 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50923 | // (st v4bf16:{ *:[v4bf16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4bf16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50924 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50925 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50926 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50927 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50928 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50929 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50930 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50931 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50932 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50933 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50934 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50935 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 50937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50938 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50944 | GIR_RootConstrainSelectedInstOperands, |
| 50945 | // GIR_Coverage, 7566, |
| 50946 | GIR_EraseRootFromParent_Done, |
| 50947 | // Label 2760: @164158 |
| 50948 | GIM_Try, /*On fail goto*//*Label 2761*/ GIMT_Encode4(164274), // Rule ID 7570 // |
| 50949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 50950 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 50951 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_64bit_4byte_aligned), |
| 50954 | // (st v4i16:{ *:[v4i16] }:$value, (DS64Bit4ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B32_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[v4i16] }:$value, sub1:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 50955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 50956 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 50957 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50958 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50959 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(11), // value |
| 50960 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50961 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 50963 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 50964 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(3), // value |
| 50965 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 50966 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 50967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B32_gfx9), |
| 50968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 50969 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 50970 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 50971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 50972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 50973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50974 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50975 | GIR_RootConstrainSelectedInstOperands, |
| 50976 | // GIR_Coverage, 7570, |
| 50977 | GIR_EraseRootFromParent_Done, |
| 50978 | // Label 2761: @164274 |
| 50979 | GIM_Try, /*On fail goto*//*Label 2762*/ GIMT_Encode4(164330), // Rule ID 3503 // |
| 50980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 50981 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 50982 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 50983 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 50984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 50985 | // (st v4f16:{ *:[v4f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 50986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 50987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 50988 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 50989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 50990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 50991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 50992 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 50993 | GIR_RootConstrainSelectedInstOperands, |
| 50994 | // GIR_Coverage, 3503, |
| 50995 | GIR_EraseRootFromParent_Done, |
| 50996 | // Label 2762: @164330 |
| 50997 | GIM_Try, /*On fail goto*//*Label 2763*/ GIMT_Encode4(164386), // Rule ID 3507 // |
| 50998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 50999 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51000 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51001 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 51003 | // (st v4bf16:{ *:[v4bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 51005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 51006 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51011 | GIR_RootConstrainSelectedInstOperands, |
| 51012 | // GIR_Coverage, 3507, |
| 51013 | GIR_EraseRootFromParent_Done, |
| 51014 | // Label 2763: @164386 |
| 51015 | GIM_Try, /*On fail goto*//*Label 2764*/ GIMT_Encode4(164442), // Rule ID 3511 // |
| 51016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51017 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51018 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51019 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 51021 | // (st v4i16:{ *:[v4i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2_SADDR), |
| 51023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 51024 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51029 | GIR_RootConstrainSelectedInstOperands, |
| 51030 | // GIR_Coverage, 3511, |
| 51031 | GIR_EraseRootFromParent_Done, |
| 51032 | // Label 2764: @164442 |
| 51033 | GIM_Try, /*On fail goto*//*Label 2765*/ GIMT_Encode4(164493), // Rule ID 3502 // |
| 51034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51035 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51036 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 51039 | // (st v4f16:{ *:[v4f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset) |
| 51040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 51041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51042 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51046 | GIR_RootConstrainSelectedInstOperands, |
| 51047 | // GIR_Coverage, 3502, |
| 51048 | GIR_EraseRootFromParent_Done, |
| 51049 | // Label 2765: @164493 |
| 51050 | GIM_Try, /*On fail goto*//*Label 2766*/ GIMT_Encode4(164544), // Rule ID 3506 // |
| 51051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51052 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51053 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51055 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 51056 | // (st v4bf16:{ *:[v4bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 51057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 51058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51059 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51062 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51063 | GIR_RootConstrainSelectedInstOperands, |
| 51064 | // GIR_Coverage, 3506, |
| 51065 | GIR_EraseRootFromParent_Done, |
| 51066 | // Label 2766: @164544 |
| 51067 | GIM_Try, /*On fail goto*//*Label 2767*/ GIMT_Encode4(164595), // Rule ID 3510 // |
| 51068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51069 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51070 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51071 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 51073 | // (st v4i16:{ *:[v4i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset) |
| 51074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX2), |
| 51075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51076 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51080 | GIR_RootConstrainSelectedInstOperands, |
| 51081 | // GIR_Coverage, 3510, |
| 51082 | GIR_EraseRootFromParent_Done, |
| 51083 | // Label 2767: @164595 |
| 51084 | GIM_Try, /*On fail goto*//*Label 2768*/ GIMT_Encode4(164647), // Rule ID 3255 // |
| 51085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 51086 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 51087 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51088 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 51090 | // (st v4f16:{ *:[v4f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4f16] }:$data, ?:{ *:[i32] }:$offset) |
| 51091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 51092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51093 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51097 | GIR_RootConstrainSelectedInstOperands, |
| 51098 | // GIR_Coverage, 3255, |
| 51099 | GIR_EraseRootFromParent_Done, |
| 51100 | // Label 2768: @164647 |
| 51101 | GIM_Try, /*On fail goto*//*Label 2769*/ GIMT_Encode4(164699), // Rule ID 3257 // |
| 51102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 51103 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 51104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 51107 | // (st v4bf16:{ *:[v4bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 51108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 51109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51110 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51113 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51114 | GIR_RootConstrainSelectedInstOperands, |
| 51115 | // GIR_Coverage, 3257, |
| 51116 | GIR_EraseRootFromParent_Done, |
| 51117 | // Label 2769: @164699 |
| 51118 | GIM_Try, /*On fail goto*//*Label 2770*/ GIMT_Encode4(164751), // Rule ID 3259 // |
| 51119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 51120 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 51121 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51122 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 51124 | // (st v4i16:{ *:[v4i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX2 ?:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v4i16] }:$data, ?:{ *:[i32] }:$offset) |
| 51125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX2), |
| 51126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51127 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51131 | GIR_RootConstrainSelectedInstOperands, |
| 51132 | // GIR_Coverage, 3259, |
| 51133 | GIR_EraseRootFromParent_Done, |
| 51134 | // Label 2770: @164751 |
| 51135 | GIM_Reject, |
| 51136 | // Label 2284: @164752 |
| 51137 | GIM_Try, /*On fail goto*//*Label 2771*/ GIMT_Encode4(164816), // Rule ID 7733 // |
| 51138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 51139 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51140 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51141 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51142 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51143 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51144 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 51145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51146 | // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51149 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51153 | GIR_RootConstrainSelectedInstOperands, |
| 51154 | // GIR_Coverage, 7733, |
| 51155 | GIR_EraseRootFromParent_Done, |
| 51156 | // Label 2771: @164816 |
| 51157 | GIM_Try, /*On fail goto*//*Label 2772*/ GIMT_Encode4(164880), // Rule ID 7737 // |
| 51158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 51159 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51160 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51161 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51162 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51163 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51164 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 51165 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51166 | // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51169 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51173 | GIR_RootConstrainSelectedInstOperands, |
| 51174 | // GIR_Coverage, 7737, |
| 51175 | GIR_EraseRootFromParent_Done, |
| 51176 | // Label 2772: @164880 |
| 51177 | GIM_Try, /*On fail goto*//*Label 2773*/ GIMT_Encode4(164939), // Rule ID 7657 // |
| 51178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51179 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51180 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51181 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51182 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51183 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51185 | // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51188 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51191 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51192 | GIR_RootConstrainSelectedInstOperands, |
| 51193 | // GIR_Coverage, 7657, |
| 51194 | GIR_EraseRootFromParent_Done, |
| 51195 | // Label 2773: @164939 |
| 51196 | GIM_Try, /*On fail goto*//*Label 2774*/ GIMT_Encode4(164998), // Rule ID 7661 // |
| 51197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51198 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51199 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51200 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51201 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51202 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51203 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51204 | // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51207 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51210 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51211 | GIR_RootConstrainSelectedInstOperands, |
| 51212 | // GIR_Coverage, 7661, |
| 51213 | GIR_EraseRootFromParent_Done, |
| 51214 | // Label 2774: @164998 |
| 51215 | GIM_Try, /*On fail goto*//*Label 2775*/ GIMT_Encode4(165058), // Rule ID 7734 // |
| 51216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 51217 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51218 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51219 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51220 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51221 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 51222 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51223 | // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 51225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51226 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51230 | GIR_RootConstrainSelectedInstOperands, |
| 51231 | // GIR_Coverage, 7734, |
| 51232 | GIR_EraseRootFromParent_Done, |
| 51233 | // Label 2775: @165058 |
| 51234 | GIM_Try, /*On fail goto*//*Label 2776*/ GIMT_Encode4(165118), // Rule ID 7738 // |
| 51235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 51236 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51237 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51238 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51239 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51240 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 51241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51242 | // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 51244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51245 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51249 | GIR_RootConstrainSelectedInstOperands, |
| 51250 | // GIR_Coverage, 7738, |
| 51251 | GIR_EraseRootFromParent_Done, |
| 51252 | // Label 2776: @165118 |
| 51253 | GIM_Try, /*On fail goto*//*Label 2777*/ GIMT_Encode4(165173), // Rule ID 7658 // |
| 51254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 51255 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51256 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51257 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51258 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51259 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51260 | // (st v4i32:{ *:[v4i32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 51262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51263 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51266 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51267 | GIR_RootConstrainSelectedInstOperands, |
| 51268 | // GIR_Coverage, 7658, |
| 51269 | GIR_EraseRootFromParent_Done, |
| 51270 | // Label 2777: @165173 |
| 51271 | GIM_Try, /*On fail goto*//*Label 2778*/ GIMT_Encode4(165228), // Rule ID 7662 // |
| 51272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 51273 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51274 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51275 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51276 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51278 | // (st v4f32:{ *:[v4f32] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v4f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 51280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51281 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51284 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51285 | GIR_RootConstrainSelectedInstOperands, |
| 51286 | // GIR_Coverage, 7662, |
| 51287 | GIR_EraseRootFromParent_Done, |
| 51288 | // Label 2778: @165228 |
| 51289 | GIM_Try, /*On fail goto*//*Label 2779*/ GIMT_Encode4(165287), // Rule ID 6340 // |
| 51290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 51291 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51292 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51293 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51294 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 51295 | // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX4_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 51296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 51297 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51304 | GIR_RootConstrainSelectedInstOperands, |
| 51305 | // GIR_Coverage, 6340, |
| 51306 | GIR_EraseRootFromParent_Done, |
| 51307 | // Label 2779: @165287 |
| 51308 | GIM_Try, /*On fail goto*//*Label 2780*/ GIMT_Encode4(165346), // Rule ID 6342 // |
| 51309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 51310 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51311 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51312 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offset), |
| 51314 | // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET VReg_128:{ *:[v4i32] }:$value, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 51315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 51316 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51323 | GIR_RootConstrainSelectedInstOperands, |
| 51324 | // GIR_Coverage, 6342, |
| 51325 | GIR_EraseRootFromParent_Done, |
| 51326 | // Label 2780: @165346 |
| 51327 | GIM_Try, /*On fail goto*//*Label 2781*/ GIMT_Encode4(165402), // Rule ID 3996 // |
| 51328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 51329 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51330 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51331 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 51333 | // (st v4i32:{ *:[v4i32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 51335 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 51338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51340 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51341 | GIR_RootConstrainSelectedInstOperands, |
| 51342 | // GIR_Coverage, 3996, |
| 51343 | GIR_EraseRootFromParent_Done, |
| 51344 | // Label 2781: @165402 |
| 51345 | GIM_Try, /*On fail goto*//*Label 2782*/ GIMT_Encode4(165458), // Rule ID 4002 // |
| 51346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 51347 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51348 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51349 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 51351 | // (st v4f32:{ *:[v4f32] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 51353 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 51356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51358 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51359 | GIR_RootConstrainSelectedInstOperands, |
| 51360 | // GIR_Coverage, 4002, |
| 51361 | GIR_EraseRootFromParent_Done, |
| 51362 | // Label 2782: @165458 |
| 51363 | GIM_Try, /*On fail goto*//*Label 2783*/ GIMT_Encode4(165509), // Rule ID 3995 // |
| 51364 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 51365 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51366 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51367 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 51369 | // (st v4i32:{ *:[v4i32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 51371 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51376 | GIR_RootConstrainSelectedInstOperands, |
| 51377 | // GIR_Coverage, 3995, |
| 51378 | GIR_EraseRootFromParent_Done, |
| 51379 | // Label 2783: @165509 |
| 51380 | GIM_Try, /*On fail goto*//*Label 2784*/ GIMT_Encode4(165560), // Rule ID 4001 // |
| 51381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 51382 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51383 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51384 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 51386 | // (st v4f32:{ *:[v4f32] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 51388 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51392 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51393 | GIR_RootConstrainSelectedInstOperands, |
| 51394 | // GIR_Coverage, 4001, |
| 51395 | GIR_EraseRootFromParent_Done, |
| 51396 | // Label 2784: @165560 |
| 51397 | GIM_Try, /*On fail goto*//*Label 2785*/ GIMT_Encode4(165611), // Rule ID 3994 // |
| 51398 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 51399 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51400 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 51403 | // (st v4i32:{ *:[v4i32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 51404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 51405 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51410 | GIR_RootConstrainSelectedInstOperands, |
| 51411 | // GIR_Coverage, 3994, |
| 51412 | GIR_EraseRootFromParent_Done, |
| 51413 | // Label 2785: @165611 |
| 51414 | GIM_Try, /*On fail goto*//*Label 2786*/ GIMT_Encode4(165662), // Rule ID 4000 // |
| 51415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 51416 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51417 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51418 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51419 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 51420 | // (st v4f32:{ *:[v4f32] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 51421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 51422 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51426 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51427 | GIR_RootConstrainSelectedInstOperands, |
| 51428 | // GIR_Coverage, 4000, |
| 51429 | GIR_EraseRootFromParent_Done, |
| 51430 | // Label 2786: @165662 |
| 51431 | GIM_Try, /*On fail goto*//*Label 2787*/ GIMT_Encode4(165726), // Rule ID 4332 // |
| 51432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 51433 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51434 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51435 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51436 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 51437 | // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 51439 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51447 | GIR_RootConstrainSelectedInstOperands, |
| 51448 | // GIR_Coverage, 4332, |
| 51449 | GIR_EraseRootFromParent_Done, |
| 51450 | // Label 2787: @165726 |
| 51451 | GIM_Try, /*On fail goto*//*Label 2788*/ GIMT_Encode4(165787), // Rule ID 4334 // |
| 51452 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51453 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51454 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 51456 | // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4i32:{ *:[v4i32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 51458 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51466 | GIR_RootConstrainSelectedInstOperands, |
| 51467 | // GIR_Coverage, 4334, |
| 51468 | GIR_EraseRootFromParent_Done, |
| 51469 | // Label 2788: @165787 |
| 51470 | GIM_Try, /*On fail goto*//*Label 2789*/ GIMT_Encode4(165851), // Rule ID 4336 // |
| 51471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 51472 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 51476 | // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 51478 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51486 | GIR_RootConstrainSelectedInstOperands, |
| 51487 | // GIR_Coverage, 4336, |
| 51488 | GIR_EraseRootFromParent_Done, |
| 51489 | // Label 2789: @165851 |
| 51490 | GIM_Try, /*On fail goto*//*Label 2790*/ GIMT_Encode4(165912), // Rule ID 4338 // |
| 51491 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 51495 | // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v4f32:{ *:[v4f32] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 51497 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51505 | GIR_RootConstrainSelectedInstOperands, |
| 51506 | // GIR_Coverage, 4338, |
| 51507 | GIR_EraseRootFromParent_Done, |
| 51508 | // Label 2790: @165912 |
| 51509 | GIM_Try, /*On fail goto*//*Label 2791*/ GIMT_Encode4(165976), // Rule ID 6339 // |
| 51510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch_HasUnrestrictedSOffset), |
| 51511 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51512 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51513 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 51515 | // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX4_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 51516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN), |
| 51517 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51524 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51525 | GIR_RootConstrainSelectedInstOperands, |
| 51526 | // GIR_Coverage, 6339, |
| 51527 | GIR_EraseRootFromParent_Done, |
| 51528 | // Label 2791: @165976 |
| 51529 | GIM_Try, /*On fail goto*//*Label 2792*/ GIMT_Encode4(166040), // Rule ID 6341 // |
| 51530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_DisableFlatScratch), |
| 51531 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 51532 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51533 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_scratch_offen), |
| 51535 | // (st v4i32:{ *:[v4i32] }:$value, (MUBUFScratchOffen:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN VReg_128:{ *:[v4i32] }:$value, ?:{ *:[i32] }:$vaddr, ?:{ *:[v4i32] }:$srsrc, ?:{ *:[i32] }:$soffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }, 0:{ *:[i1] }) |
| 51536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN), |
| 51537 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 51539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 51541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 51542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51544 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51545 | GIR_RootConstrainSelectedInstOperands, |
| 51546 | // GIR_Coverage, 6341, |
| 51547 | GIR_EraseRootFromParent_Done, |
| 51548 | // Label 2792: @166040 |
| 51549 | GIM_Try, /*On fail goto*//*Label 2793*/ GIMT_Encode4(166160), // Rule ID 7544 // |
| 51550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51551 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51552 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51553 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51554 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51555 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 51556 | // (AMDGPUst_glue v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 51557 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51558 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 51559 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51560 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51561 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 51562 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51563 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51564 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51565 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51566 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 51567 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51568 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 51570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51571 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51572 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 51573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 51574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 51575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51577 | GIR_RootConstrainSelectedInstOperands, |
| 51578 | // GIR_Coverage, 7544, |
| 51579 | GIR_EraseRootFromParent_Done, |
| 51580 | // Label 2793: @166160 |
| 51581 | GIM_Try, /*On fail goto*//*Label 2794*/ GIMT_Encode4(166280), // Rule ID 7584 // |
| 51582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51583 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51584 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51585 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51586 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 51588 | // (AMDGPUst_glue v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 51589 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51590 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 51591 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51592 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51593 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 51594 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51595 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51597 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51598 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 51599 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51600 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 51602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 51605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 51606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 51607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51609 | GIR_RootConstrainSelectedInstOperands, |
| 51610 | // GIR_Coverage, 7584, |
| 51611 | GIR_EraseRootFromParent_Done, |
| 51612 | // Label 2794: @166280 |
| 51613 | GIM_Try, /*On fail goto*//*Label 2795*/ GIMT_Encode4(166339), // Rule ID 4331 // |
| 51614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 51615 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51616 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 51619 | // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 51621 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51628 | GIR_RootConstrainSelectedInstOperands, |
| 51629 | // GIR_Coverage, 4331, |
| 51630 | GIR_EraseRootFromParent_Done, |
| 51631 | // Label 2795: @166339 |
| 51632 | GIM_Try, /*On fail goto*//*Label 2796*/ GIMT_Encode4(166395), // Rule ID 4333 // |
| 51633 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51634 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 51637 | // (st v4i32:{ *:[v4i32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 51639 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51646 | GIR_RootConstrainSelectedInstOperands, |
| 51647 | // GIR_Coverage, 4333, |
| 51648 | GIR_EraseRootFromParent_Done, |
| 51649 | // Label 2796: @166395 |
| 51650 | GIM_Try, /*On fail goto*//*Label 2797*/ GIMT_Encode4(166454), // Rule ID 4335 // |
| 51651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 51652 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51653 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 51656 | // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 51658 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51665 | GIR_RootConstrainSelectedInstOperands, |
| 51666 | // GIR_Coverage, 4335, |
| 51667 | GIR_EraseRootFromParent_Done, |
| 51668 | // Label 2797: @166454 |
| 51669 | GIM_Try, /*On fail goto*//*Label 2798*/ GIMT_Encode4(166510), // Rule ID 4337 // |
| 51670 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51671 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51672 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 51674 | // (st v4f32:{ *:[v4f32] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 51675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 51676 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 51677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 51678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 51679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51683 | GIR_RootConstrainSelectedInstOperands, |
| 51684 | // GIR_Coverage, 4337, |
| 51685 | GIR_EraseRootFromParent_Done, |
| 51686 | // Label 2798: @166510 |
| 51687 | GIM_Try, /*On fail goto*//*Label 2799*/ GIMT_Encode4(166626), // Rule ID 7546 // |
| 51688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 51689 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51690 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 51693 | // (st v4i32:{ *:[v4i32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4i32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 51694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51695 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 51696 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51697 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51698 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 51699 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51700 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51701 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51702 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51703 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 51704 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51705 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 51707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51708 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51709 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 51710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 51711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 51712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51714 | GIR_RootConstrainSelectedInstOperands, |
| 51715 | // GIR_Coverage, 7546, |
| 51716 | GIR_EraseRootFromParent_Done, |
| 51717 | // Label 2799: @166626 |
| 51718 | GIM_Try, /*On fail goto*//*Label 2800*/ GIMT_Encode4(166742), // Rule ID 7586 // |
| 51719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 51720 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51721 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 51724 | // (st v4f32:{ *:[v4f32] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v4f32] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 51725 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 51726 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 51727 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51728 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51729 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 51730 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51731 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51732 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 51733 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 51734 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 51735 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 51736 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 51737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 51738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51739 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 51740 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 51741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 51742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 51743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51745 | GIR_RootConstrainSelectedInstOperands, |
| 51746 | // GIR_Coverage, 7586, |
| 51747 | GIR_EraseRootFromParent_Done, |
| 51748 | // Label 2800: @166742 |
| 51749 | GIM_Try, /*On fail goto*//*Label 2801*/ GIMT_Encode4(166798), // Rule ID 3529 // |
| 51750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51751 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51752 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51753 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 51755 | // (st v4i32:{ *:[v4i32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 51757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 51758 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51762 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51763 | GIR_RootConstrainSelectedInstOperands, |
| 51764 | // GIR_Coverage, 3529, |
| 51765 | GIR_EraseRootFromParent_Done, |
| 51766 | // Label 2801: @166798 |
| 51767 | GIM_Try, /*On fail goto*//*Label 2802*/ GIMT_Encode4(166854), // Rule ID 3533 // |
| 51768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51769 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51770 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51771 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 51773 | // (st v4f32:{ *:[v4f32] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 51774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 51775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 51776 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 51778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 51779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51781 | GIR_RootConstrainSelectedInstOperands, |
| 51782 | // GIR_Coverage, 3533, |
| 51783 | GIR_EraseRootFromParent_Done, |
| 51784 | // Label 2802: @166854 |
| 51785 | GIM_Try, /*On fail goto*//*Label 2803*/ GIMT_Encode4(166905), // Rule ID 3528 // |
| 51786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51787 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51788 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51789 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 51791 | // (st v4i32:{ *:[v4i32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset) |
| 51792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 51793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51794 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51798 | GIR_RootConstrainSelectedInstOperands, |
| 51799 | // GIR_Coverage, 3528, |
| 51800 | GIR_EraseRootFromParent_Done, |
| 51801 | // Label 2803: @166905 |
| 51802 | GIM_Try, /*On fail goto*//*Label 2804*/ GIMT_Encode4(166956), // Rule ID 3532 // |
| 51803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 51804 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 51805 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51806 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 51808 | // (st v4f32:{ *:[v4f32] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset) |
| 51809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 51810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51811 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51815 | GIR_RootConstrainSelectedInstOperands, |
| 51816 | // GIR_Coverage, 3532, |
| 51817 | GIR_EraseRootFromParent_Done, |
| 51818 | // Label 2804: @166956 |
| 51819 | GIM_Try, /*On fail goto*//*Label 2805*/ GIMT_Encode4(167008), // Rule ID 3269 // |
| 51820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 51821 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 51822 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 51825 | // (st v4i32:{ *:[v4i32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v4i32] }:$data, ?:{ *:[i32] }:$offset) |
| 51826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 51827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51828 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51832 | GIR_RootConstrainSelectedInstOperands, |
| 51833 | // GIR_Coverage, 3269, |
| 51834 | GIR_EraseRootFromParent_Done, |
| 51835 | // Label 2805: @167008 |
| 51836 | GIM_Try, /*On fail goto*//*Label 2806*/ GIMT_Encode4(167060), // Rule ID 3271 // |
| 51837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 51838 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 51839 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 51842 | // (st v4f32:{ *:[v4f32] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v4f32] }:$data, ?:{ *:[i32] }:$offset) |
| 51843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 51844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 51845 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 51846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51849 | GIR_RootConstrainSelectedInstOperands, |
| 51850 | // GIR_Coverage, 3271, |
| 51851 | GIR_EraseRootFromParent_Done, |
| 51852 | // Label 2806: @167060 |
| 51853 | GIM_Reject, |
| 51854 | // Label 2285: @167061 |
| 51855 | GIM_Try, /*On fail goto*//*Label 2807*/ GIMT_Encode4(167125), // Rule ID 7749 // |
| 51856 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 51857 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51858 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51859 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51860 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51861 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51862 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 51863 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51864 | // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51867 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51870 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51871 | GIR_RootConstrainSelectedInstOperands, |
| 51872 | // GIR_Coverage, 7749, |
| 51873 | GIR_EraseRootFromParent_Done, |
| 51874 | // Label 2807: @167125 |
| 51875 | GIM_Try, /*On fail goto*//*Label 2808*/ GIMT_Encode4(167189), // Rule ID 7753 // |
| 51876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 51877 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51878 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51879 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51880 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51882 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 51883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51884 | // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51887 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51891 | GIR_RootConstrainSelectedInstOperands, |
| 51892 | // GIR_Coverage, 7753, |
| 51893 | GIR_EraseRootFromParent_Done, |
| 51894 | // Label 2808: @167189 |
| 51895 | GIM_Try, /*On fail goto*//*Label 2809*/ GIMT_Encode4(167253), // Rule ID 7757 // |
| 51896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_LDSRequiresM0Init), |
| 51897 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51898 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51899 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51900 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51901 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local_m0), |
| 51903 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51904 | // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align_less_than_4_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51907 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51910 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51911 | GIR_RootConstrainSelectedInstOperands, |
| 51912 | // GIR_Coverage, 7757, |
| 51913 | GIR_EraseRootFromParent_Done, |
| 51914 | // Label 2809: @167253 |
| 51915 | GIM_Try, /*On fail goto*//*Label 2810*/ GIMT_Encode4(167312), // Rule ID 7673 // |
| 51916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51917 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51918 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51919 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51920 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51921 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51923 | // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51926 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51930 | GIR_RootConstrainSelectedInstOperands, |
| 51931 | // GIR_Coverage, 7673, |
| 51932 | GIR_EraseRootFromParent_Done, |
| 51933 | // Label 2810: @167312 |
| 51934 | GIM_Try, /*On fail goto*//*Label 2811*/ GIMT_Encode4(167371), // Rule ID 7677 // |
| 51935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51936 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51937 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51938 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51939 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51941 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51942 | // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51945 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51948 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51949 | GIR_RootConstrainSelectedInstOperands, |
| 51950 | // GIR_Coverage, 7677, |
| 51951 | GIR_EraseRootFromParent_Done, |
| 51952 | // Label 2811: @167371 |
| 51953 | GIM_Try, /*On fail goto*//*Label 2812*/ GIMT_Encode4(167430), // Rule ID 7681 // |
| 51954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 51955 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 51956 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51957 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 51958 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51959 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51961 | // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>><<P:Predicate_store_align16_local_m0>> => (DS_WRITE_B128 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128), |
| 51963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51964 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51968 | GIR_RootConstrainSelectedInstOperands, |
| 51969 | // GIR_Coverage, 7681, |
| 51970 | GIR_EraseRootFromParent_Done, |
| 51971 | // Label 2812: @167430 |
| 51972 | GIM_Try, /*On fail goto*//*Label 2813*/ GIMT_Encode4(167490), // Rule ID 7750 // |
| 51973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 51974 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51975 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51976 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51978 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 51979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51980 | // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 51981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 51982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 51983 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 51984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 51985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 51986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 51987 | GIR_RootConstrainSelectedInstOperands, |
| 51988 | // GIR_Coverage, 7750, |
| 51989 | GIR_EraseRootFromParent_Done, |
| 51990 | // Label 2813: @167490 |
| 51991 | GIM_Try, /*On fail goto*//*Label 2814*/ GIMT_Encode4(167550), // Rule ID 7754 // |
| 51992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 51993 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51994 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 51995 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 51996 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 51997 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 51998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 51999 | // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 52001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52002 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 52003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52005 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52006 | GIR_RootConstrainSelectedInstOperands, |
| 52007 | // GIR_Coverage, 7754, |
| 52008 | GIR_EraseRootFromParent_Done, |
| 52009 | // Label 2814: @167550 |
| 52010 | GIM_Try, /*On fail goto*//*Label 2815*/ GIMT_Encode4(167610), // Rule ID 7758 // |
| 52011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnalignedAccessMode_NotLDSRequiresM0Init), |
| 52012 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52013 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52014 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52015 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52016 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_store_align_less_than_4_local), |
| 52017 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52018 | // (st v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align_less_than_4_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 52020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52021 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 52022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52024 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52025 | GIR_RootConstrainSelectedInstOperands, |
| 52026 | // GIR_Coverage, 7758, |
| 52027 | GIR_EraseRootFromParent_Done, |
| 52028 | // Label 2815: @167610 |
| 52029 | GIM_Try, /*On fail goto*//*Label 2816*/ GIMT_Encode4(167665), // Rule ID 7674 // |
| 52030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 52031 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52032 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 52033 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52034 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52036 | // (st v8i16:{ *:[v8i16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8i16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 52038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52039 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 52040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52042 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52043 | GIR_RootConstrainSelectedInstOperands, |
| 52044 | // GIR_Coverage, 7674, |
| 52045 | GIR_EraseRootFromParent_Done, |
| 52046 | // Label 2816: @167665 |
| 52047 | GIM_Try, /*On fail goto*//*Label 2817*/ GIMT_Encode4(167720), // Rule ID 7678 // |
| 52048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 52049 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52050 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 52051 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52052 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52054 | // (st v8f16:{ *:[v8f16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 52056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52057 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 52058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52060 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52061 | GIR_RootConstrainSelectedInstOperands, |
| 52062 | // GIR_Coverage, 7678, |
| 52063 | GIR_EraseRootFromParent_Done, |
| 52064 | // Label 2817: @167720 |
| 52065 | GIM_Try, /*On fail goto*//*Label 2818*/ GIMT_Encode4(167775), // Rule ID 7682 // |
| 52066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX7Plus), |
| 52067 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52068 | GIM_CheckMemoryAlignment, /*MI*/0, /*MMO*/0, /*MinAlign*/16, |
| 52069 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52070 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52072 | // (st v8bf16:{ *:[v8bf16] }:$value, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>><<P:Predicate_store_align16_local>> => (DS_WRITE_B128_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15873:{ *:[v8bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE_B128_gfx9), |
| 52074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52075 | GIR_RootToRootCopy, /*OpIdx*/0, // value |
| 52076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52079 | GIR_RootConstrainSelectedInstOperands, |
| 52080 | // GIR_Coverage, 7682, |
| 52081 | GIR_EraseRootFromParent_Done, |
| 52082 | // Label 2818: @167775 |
| 52083 | GIM_Try, /*On fail goto*//*Label 2819*/ GIMT_Encode4(167831), // Rule ID 4020 // |
| 52084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 52085 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52086 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52087 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52088 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 52089 | // (st v8i16:{ *:[v8i16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 52091 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 52094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52097 | GIR_RootConstrainSelectedInstOperands, |
| 52098 | // GIR_Coverage, 4020, |
| 52099 | GIR_EraseRootFromParent_Done, |
| 52100 | // Label 2819: @167831 |
| 52101 | GIM_Try, /*On fail goto*//*Label 2820*/ GIMT_Encode4(167887), // Rule ID 4026 // |
| 52102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 52103 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52104 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52105 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 52107 | // (st v8f16:{ *:[v8f16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 52109 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 52112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52114 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52115 | GIR_RootConstrainSelectedInstOperands, |
| 52116 | // GIR_Coverage, 4026, |
| 52117 | GIR_EraseRootFromParent_Done, |
| 52118 | // Label 2820: @167887 |
| 52119 | GIM_Try, /*On fail goto*//*Label 2821*/ GIMT_Encode4(167943), // Rule ID 4032 // |
| 52120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts_HasFlatScratchSVSMode), |
| 52121 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52122 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52123 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_svaddr), |
| 52125 | // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchSVAddr:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SVS anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SVS), |
| 52127 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // saddr |
| 52130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52132 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52133 | GIR_RootConstrainSelectedInstOperands, |
| 52134 | // GIR_Coverage, 4032, |
| 52135 | GIR_EraseRootFromParent_Done, |
| 52136 | // Label 2821: @167943 |
| 52137 | GIM_Try, /*On fail goto*//*Label 2822*/ GIMT_Encode4(167994), // Rule ID 4019 // |
| 52138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52139 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52140 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 52143 | // (st v8i16:{ *:[v8i16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 52145 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52149 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52150 | GIR_RootConstrainSelectedInstOperands, |
| 52151 | // GIR_Coverage, 4019, |
| 52152 | GIR_EraseRootFromParent_Done, |
| 52153 | // Label 2822: @167994 |
| 52154 | GIM_Try, /*On fail goto*//*Label 2823*/ GIMT_Encode4(168045), // Rule ID 4025 // |
| 52155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52156 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52157 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52158 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 52160 | // (st v8f16:{ *:[v8f16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 52162 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52166 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52167 | GIR_RootConstrainSelectedInstOperands, |
| 52168 | // GIR_Coverage, 4025, |
| 52169 | GIR_EraseRootFromParent_Done, |
| 52170 | // Label 2823: @168045 |
| 52171 | GIM_Try, /*On fail goto*//*Label 2824*/ GIMT_Encode4(168096), // Rule ID 4031 // |
| 52172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52173 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52174 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_saddr), |
| 52177 | // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchSAddr:{ *:[iPTR] } SGPR_32:{ *:[i32] }:$saddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4_SADDR anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4_SADDR), |
| 52179 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52184 | GIR_RootConstrainSelectedInstOperands, |
| 52185 | // GIR_Coverage, 4031, |
| 52186 | GIR_EraseRootFromParent_Done, |
| 52187 | // Label 2824: @168096 |
| 52188 | GIM_Try, /*On fail goto*//*Label 2825*/ GIMT_Encode4(168147), // Rule ID 4018 // |
| 52189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52190 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52191 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52192 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52193 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 52194 | // (st v8i16:{ *:[v8i16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 52195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 52196 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52200 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52201 | GIR_RootConstrainSelectedInstOperands, |
| 52202 | // GIR_Coverage, 4018, |
| 52203 | GIR_EraseRootFromParent_Done, |
| 52204 | // Label 2825: @168147 |
| 52205 | GIM_Try, /*On fail goto*//*Label 2826*/ GIMT_Encode4(168198), // Rule ID 4024 // |
| 52206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52207 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52208 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52209 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 52211 | // (st v8f16:{ *:[v8f16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 52212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 52213 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52217 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52218 | GIR_RootConstrainSelectedInstOperands, |
| 52219 | // GIR_Coverage, 4024, |
| 52220 | GIR_EraseRootFromParent_Done, |
| 52221 | // Label 2826: @168198 |
| 52222 | GIM_Try, /*On fail goto*//*Label 2827*/ GIMT_Encode4(168249), // Rule ID 4030 // |
| 52223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableFlatScratch_HasFlatScratchInsts), |
| 52224 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/5, |
| 52225 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52226 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_scratch_offset), |
| 52228 | // (st v8bf16:{ *:[v8bf16] }:$data, (ScratchOffset:{ *:[iPTR] } VGPR_32:{ *:[i32] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_private>> => (SCRATCH_STORE_DWORDX4 anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 52229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCRATCH_STORE_DWORDX4), |
| 52230 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52235 | GIR_RootConstrainSelectedInstOperands, |
| 52236 | // GIR_Coverage, 4030, |
| 52237 | GIR_EraseRootFromParent_Done, |
| 52238 | // Label 2827: @168249 |
| 52239 | GIM_Try, /*On fail goto*//*Label 2828*/ GIMT_Encode4(168313), // Rule ID 4348 // |
| 52240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52241 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52242 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52243 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52245 | // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 52247 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52255 | GIR_RootConstrainSelectedInstOperands, |
| 52256 | // GIR_Coverage, 4348, |
| 52257 | GIR_EraseRootFromParent_Done, |
| 52258 | // Label 2828: @168313 |
| 52259 | GIM_Try, /*On fail goto*//*Label 2829*/ GIMT_Encode4(168374), // Rule ID 4350 // |
| 52260 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52261 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52262 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52263 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52264 | // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8i16:{ *:[v8i16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 52266 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52274 | GIR_RootConstrainSelectedInstOperands, |
| 52275 | // GIR_Coverage, 4350, |
| 52276 | GIR_EraseRootFromParent_Done, |
| 52277 | // Label 2829: @168374 |
| 52278 | GIM_Try, /*On fail goto*//*Label 2830*/ GIMT_Encode4(168438), // Rule ID 4352 // |
| 52279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52280 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52281 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52284 | // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 52286 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52293 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52294 | GIR_RootConstrainSelectedInstOperands, |
| 52295 | // GIR_Coverage, 4352, |
| 52296 | GIR_EraseRootFromParent_Done, |
| 52297 | // Label 2830: @168438 |
| 52298 | GIM_Try, /*On fail goto*//*Label 2831*/ GIMT_Encode4(168499), // Rule ID 4354 // |
| 52299 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52300 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52303 | // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8f16:{ *:[v8f16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 52305 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52313 | GIR_RootConstrainSelectedInstOperands, |
| 52314 | // GIR_Coverage, 4354, |
| 52315 | GIR_EraseRootFromParent_Done, |
| 52316 | // Label 2831: @168499 |
| 52317 | GIM_Try, /*On fail goto*//*Label 2832*/ GIMT_Encode4(168563), // Rule ID 4356 // |
| 52318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52320 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52323 | // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_ADDR64 v8bf16:{ *:[v8bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_ADDR64), |
| 52325 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52333 | GIR_RootConstrainSelectedInstOperands, |
| 52334 | // GIR_Coverage, 4356, |
| 52335 | GIR_EraseRootFromParent_Done, |
| 52336 | // Label 2832: @168563 |
| 52337 | GIM_Try, /*On fail goto*//*Label 2833*/ GIMT_Encode4(168624), // Rule ID 4358 // |
| 52338 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52339 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52340 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 52342 | // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_ADDR64 v8bf16:{ *:[v8bf16] }:$vdata, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_ADDR64), |
| 52344 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 52346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 52348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 52349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52351 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52352 | GIR_RootConstrainSelectedInstOperands, |
| 52353 | // GIR_Coverage, 4358, |
| 52354 | GIR_EraseRootFromParent_Done, |
| 52355 | // Label 2833: @168624 |
| 52356 | GIM_Try, /*On fail goto*//*Label 2834*/ GIMT_Encode4(168744), // Rule ID 7596 // |
| 52357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 52358 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 52359 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52360 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52363 | // (AMDGPUst_glue v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52365 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52366 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52367 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52368 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52369 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52370 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52371 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52372 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52373 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52374 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52375 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 52377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52379 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52384 | GIR_RootConstrainSelectedInstOperands, |
| 52385 | // GIR_Coverage, 7596, |
| 52386 | GIR_EraseRootFromParent_Done, |
| 52387 | // Label 2834: @168744 |
| 52388 | GIM_Try, /*On fail goto*//*Label 2835*/ GIMT_Encode4(168864), // Rule ID 7600 // |
| 52389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 52390 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 52391 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52392 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52393 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52395 | // (AMDGPUst_glue v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52396 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52397 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52398 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52399 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52400 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52401 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52402 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52403 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52404 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52405 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52406 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52407 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 52409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52410 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52411 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52415 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52416 | GIR_RootConstrainSelectedInstOperands, |
| 52417 | // GIR_Coverage, 7600, |
| 52418 | GIR_EraseRootFromParent_Done, |
| 52419 | // Label 2835: @168864 |
| 52420 | GIM_Try, /*On fail goto*//*Label 2836*/ GIMT_Encode4(168984), // Rule ID 7604 // |
| 52421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX7Plus), |
| 52422 | GIM_CheckMemorySizeEqualToLLT, /*MI*/0, /*MMO*/0, /*OpIdx*/0, |
| 52423 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52424 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52425 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52427 | // (AMDGPUst_glue v8bf16:{ *:[v8bf16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore_glue>><<P:Predicate_store_glue>><<P:Predicate_store_local_m0>> => (DS_WRITE2_B64 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52429 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52430 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52431 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52432 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52433 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52434 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52435 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52436 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52437 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52438 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52439 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64), |
| 52441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52448 | GIR_RootConstrainSelectedInstOperands, |
| 52449 | // GIR_Coverage, 7604, |
| 52450 | GIR_EraseRootFromParent_Done, |
| 52451 | // Label 2836: @168984 |
| 52452 | GIM_Try, /*On fail goto*//*Label 2837*/ GIMT_Encode4(169043), // Rule ID 4347 // |
| 52453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52454 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52455 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52457 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52458 | // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 52460 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52467 | GIR_RootConstrainSelectedInstOperands, |
| 52468 | // GIR_Coverage, 4347, |
| 52469 | GIR_EraseRootFromParent_Done, |
| 52470 | // Label 2837: @169043 |
| 52471 | GIM_Try, /*On fail goto*//*Label 2838*/ GIMT_Encode4(169099), // Rule ID 4349 // |
| 52472 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52473 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52476 | // (st v8i16:{ *:[v8i16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 52478 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52485 | GIR_RootConstrainSelectedInstOperands, |
| 52486 | // GIR_Coverage, 4349, |
| 52487 | GIR_EraseRootFromParent_Done, |
| 52488 | // Label 2838: @169099 |
| 52489 | GIM_Try, /*On fail goto*//*Label 2839*/ GIMT_Encode4(169158), // Rule ID 4351 // |
| 52490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52491 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52492 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52495 | // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 52497 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52503 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52504 | GIR_RootConstrainSelectedInstOperands, |
| 52505 | // GIR_Coverage, 4351, |
| 52506 | GIR_EraseRootFromParent_Done, |
| 52507 | // Label 2839: @169158 |
| 52508 | GIM_Try, /*On fail goto*//*Label 2840*/ GIMT_Encode4(169214), // Rule ID 4353 // |
| 52509 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52510 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52513 | // (st v8f16:{ *:[v8f16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 52515 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52522 | GIR_RootConstrainSelectedInstOperands, |
| 52523 | // GIR_Coverage, 4353, |
| 52524 | GIR_EraseRootFromParent_Done, |
| 52525 | // Label 2840: @169214 |
| 52526 | GIM_Try, /*On fail goto*//*Label 2841*/ GIMT_Encode4(169273), // Rule ID 4355 // |
| 52527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 52528 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52529 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52532 | // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_OFFSET v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET), |
| 52534 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52541 | GIR_RootConstrainSelectedInstOperands, |
| 52542 | // GIR_Coverage, 4355, |
| 52543 | GIR_EraseRootFromParent_Done, |
| 52544 | // Label 2841: @169273 |
| 52545 | GIM_Try, /*On fail goto*//*Label 2842*/ GIMT_Encode4(169329), // Rule ID 4357 // |
| 52546 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52547 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52548 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 52550 | // (st v8bf16:{ *:[v8bf16] }:$vdata, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 52551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET), |
| 52552 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 52553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 52554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 52555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52558 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52559 | GIR_RootConstrainSelectedInstOperands, |
| 52560 | // GIR_Coverage, 4357, |
| 52561 | GIR_EraseRootFromParent_Done, |
| 52562 | // Label 2842: @169329 |
| 52563 | GIM_Try, /*On fail goto*//*Label 2843*/ GIMT_Encode4(169445), // Rule ID 7598 // |
| 52564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 52565 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52566 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52567 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52568 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52569 | // (st v8i16:{ *:[v8i16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8i16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52570 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52571 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52572 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52573 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52574 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52575 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52576 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52579 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52580 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 52583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52584 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52585 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52590 | GIR_RootConstrainSelectedInstOperands, |
| 52591 | // GIR_Coverage, 7598, |
| 52592 | GIR_EraseRootFromParent_Done, |
| 52593 | // Label 2843: @169445 |
| 52594 | GIM_Try, /*On fail goto*//*Label 2844*/ GIMT_Encode4(169561), // Rule ID 7602 // |
| 52595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 52596 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52597 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52600 | // (st v8f16:{ *:[v8f16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8f16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52601 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52602 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52603 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52604 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52605 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52606 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52607 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52610 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52611 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52612 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 52614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52615 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52616 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52620 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52621 | GIR_RootConstrainSelectedInstOperands, |
| 52622 | // GIR_Coverage, 7602, |
| 52623 | GIR_EraseRootFromParent_Done, |
| 52624 | // Label 2844: @169561 |
| 52625 | GIM_Try, /*On fail goto*//*Label 2845*/ GIMT_Encode4(169677), // Rule ID 7606 // |
| 52626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 52627 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52628 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52629 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_128bit_8byte_aligned), |
| 52631 | // (st v8bf16:{ *:[v8bf16] }:$value, (DS128Bit8ByteAligned:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i8:{ *:[i8] }:$offset0, i8:{ *:[i8] }:$offset1))<<P:Predicate_unindexedstore>><<P:Predicate_store_local>> => (DS_WRITE2_B64_gfx9 ?:{ *:[i32] }:$ptr, (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub0_sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i64] } VReg_128:{ *:[v8bf16] }:$value, sub2_sub3:{ *:[i32] }), ?:{ *:[i8] }:$offset0, ?:{ *:[i8] }:$offset1, 0:{ *:[i1] }) |
| 52632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 52633 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 52634 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52635 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52636 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(24), // value |
| 52637 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52638 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 52640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 52641 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, /*SubRegIdx*/GIMT_Encode2(4), // value |
| 52642 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 52643 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 52644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRITE2_B64_gfx9), |
| 52645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 52647 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 52648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset0 |
| 52649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset1 |
| 52650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52651 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52652 | GIR_RootConstrainSelectedInstOperands, |
| 52653 | // GIR_Coverage, 7606, |
| 52654 | GIR_EraseRootFromParent_Done, |
| 52655 | // Label 2845: @169677 |
| 52656 | GIM_Try, /*On fail goto*//*Label 2846*/ GIMT_Encode4(169733), // Rule ID 3545 // |
| 52657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52658 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52659 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52660 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 52662 | // (st v8i16:{ *:[v8i16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 52664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 52665 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52670 | GIR_RootConstrainSelectedInstOperands, |
| 52671 | // GIR_Coverage, 3545, |
| 52672 | GIR_EraseRootFromParent_Done, |
| 52673 | // Label 2846: @169733 |
| 52674 | GIM_Try, /*On fail goto*//*Label 2847*/ GIMT_Encode4(169789), // Rule ID 3549 // |
| 52675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52676 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52677 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 52680 | // (st v8f16:{ *:[v8f16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 52682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 52683 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52688 | GIR_RootConstrainSelectedInstOperands, |
| 52689 | // GIR_Coverage, 3549, |
| 52690 | GIR_EraseRootFromParent_Done, |
| 52691 | // Label 2847: @169789 |
| 52692 | GIM_Try, /*On fail goto*//*Label 2848*/ GIMT_Encode4(169845), // Rule ID 3553 // |
| 52693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52694 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52695 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52696 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 52698 | // (st v8bf16:{ *:[v8bf16] }:$data, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 52699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4_SADDR), |
| 52700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 52701 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 52703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 52704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52706 | GIR_RootConstrainSelectedInstOperands, |
| 52707 | // GIR_Coverage, 3553, |
| 52708 | GIR_EraseRootFromParent_Done, |
| 52709 | // Label 2848: @169845 |
| 52710 | GIM_Try, /*On fail goto*//*Label 2849*/ GIMT_Encode4(169896), // Rule ID 3544 // |
| 52711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52712 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52713 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52714 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 52716 | // (st v8i16:{ *:[v8i16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset) |
| 52717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 52718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52719 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52722 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52723 | GIR_RootConstrainSelectedInstOperands, |
| 52724 | // GIR_Coverage, 3544, |
| 52725 | GIR_EraseRootFromParent_Done, |
| 52726 | // Label 2849: @169896 |
| 52727 | GIM_Try, /*On fail goto*//*Label 2850*/ GIMT_Encode4(169947), // Rule ID 3548 // |
| 52728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52729 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52730 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52731 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52732 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 52733 | // (st v8f16:{ *:[v8f16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset) |
| 52734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 52735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52736 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52740 | GIR_RootConstrainSelectedInstOperands, |
| 52741 | // GIR_Coverage, 3548, |
| 52742 | GIR_EraseRootFromParent_Done, |
| 52743 | // Label 2850: @169947 |
| 52744 | GIM_Try, /*On fail goto*//*Label 2851*/ GIMT_Encode4(169998), // Rule ID 3552 // |
| 52745 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 52746 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/1, |
| 52747 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 52750 | // (st v8bf16:{ *:[v8bf16] }:$data, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_global>> => (GLOBAL_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 52751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_STORE_DWORDX4), |
| 52752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52753 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52756 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52757 | GIR_RootConstrainSelectedInstOperands, |
| 52758 | // GIR_Coverage, 3552, |
| 52759 | GIR_EraseRootFromParent_Done, |
| 52760 | // Label 2851: @169998 |
| 52761 | GIM_Try, /*On fail goto*//*Label 2852*/ GIMT_Encode4(170050), // Rule ID 3277 // |
| 52762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 52763 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 52764 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52765 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 52767 | // (st v8i16:{ *:[v8i16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8i16] }:$data, ?:{ *:[i32] }:$offset) |
| 52768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 52769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52770 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52774 | GIR_RootConstrainSelectedInstOperands, |
| 52775 | // GIR_Coverage, 3277, |
| 52776 | GIR_EraseRootFromParent_Done, |
| 52777 | // Label 2852: @170050 |
| 52778 | GIM_Try, /*On fail goto*//*Label 2853*/ GIMT_Encode4(170102), // Rule ID 3279 // |
| 52779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 52780 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 52781 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52782 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52783 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 52784 | // (st v8f16:{ *:[v8f16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8f16] }:$data, ?:{ *:[i32] }:$offset) |
| 52785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 52786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52787 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52790 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52791 | GIR_RootConstrainSelectedInstOperands, |
| 52792 | // GIR_Coverage, 3279, |
| 52793 | GIR_EraseRootFromParent_Done, |
| 52794 | // Label 2853: @170102 |
| 52795 | GIM_Try, /*On fail goto*//*Label 2854*/ GIMT_Encode4(170154), // Rule ID 3281 // |
| 52796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 52797 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/2, /*AddrSpace*/0, /*AddrSpace*/1, |
| 52798 | GIM_CheckAtomicOrdering, /*MI*/0, /*Order*/(uint8_t)AtomicOrdering::NotAtomic, |
| 52799 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 52801 | // (st v8bf16:{ *:[v8bf16] }:$data, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset))<<P:Predicate_unindexedstore>><<P:Predicate_store_flat>> => (FLAT_STORE_DWORDX4 ?:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v8bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 52802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_STORE_DWORDX4), |
| 52803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 52804 | GIR_RootToRootCopy, /*OpIdx*/0, // data |
| 52805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52807 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52808 | GIR_RootConstrainSelectedInstOperands, |
| 52809 | // GIR_Coverage, 3281, |
| 52810 | GIR_EraseRootFromParent_Done, |
| 52811 | // Label 2854: @170154 |
| 52812 | GIM_Reject, |
| 52813 | // Label 2286: @170155 |
| 52814 | GIM_Reject, |
| 52815 | // Label 17: @170156 |
| 52816 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2857*/ GIMT_Encode4(171281), |
| 52817 | /*GILLT_s32*//*Label 2855*/ GIMT_Encode4(170175), |
| 52818 | /*GILLT_s64*//*Label 2856*/ GIMT_Encode4(170728), |
| 52819 | // Label 2855: @170175 |
| 52820 | GIM_Try, /*On fail goto*//*Label 2858*/ GIMT_Encode4(170727), |
| 52821 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 52822 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 52823 | GIM_Try, /*On fail goto*//*Label 2859*/ GIMT_Encode4(170238), // Rule ID 7769 // |
| 52824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 52825 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52826 | GIM_CheckHasNoUse, /*MI*/0, |
| 52827 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52829 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i32>> => (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32), |
| 52831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52832 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52833 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52837 | GIR_RootConstrainSelectedInstOperands, |
| 52838 | // GIR_Coverage, 7769, |
| 52839 | GIR_EraseRootFromParent_Done, |
| 52840 | // Label 2859: @170238 |
| 52841 | GIM_Try, /*On fail goto*//*Label 2860*/ GIMT_Encode4(170290), // Rule ID 7771 // |
| 52842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 52843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52844 | GIM_CheckHasNoUse, /*MI*/0, |
| 52845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52847 | // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i32>> => (DS_CMPST_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32_gfx9), |
| 52849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52850 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52851 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52855 | GIR_RootConstrainSelectedInstOperands, |
| 52856 | // GIR_Coverage, 7771, |
| 52857 | GIR_EraseRootFromParent_Done, |
| 52858 | // Label 2860: @170290 |
| 52859 | GIM_Try, /*On fail goto*//*Label 2861*/ GIMT_Encode4(170342), // Rule ID 7773 // |
| 52860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10), |
| 52861 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 52862 | GIM_CheckHasNoUse, /*MI*/0, |
| 52863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52865 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i32>> => (DS_CMPST_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 52866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B32), |
| 52867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52868 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52869 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 52872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52873 | GIR_RootConstrainSelectedInstOperands, |
| 52874 | // GIR_Coverage, 7773, |
| 52875 | GIR_EraseRootFromParent_Done, |
| 52876 | // Label 2861: @170342 |
| 52877 | GIM_Try, /*On fail goto*//*Label 2862*/ GIMT_Encode4(170394), // Rule ID 7775 // |
| 52878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 52879 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52880 | GIM_CheckHasNoUse, /*MI*/0, |
| 52881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52883 | // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i32>> => (DS_CMPSTORE_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$swap, anonymous_15876:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32_gfx9), |
| 52885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52886 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52887 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52891 | GIR_RootConstrainSelectedInstOperands, |
| 52892 | // GIR_Coverage, 7775, |
| 52893 | GIR_EraseRootFromParent_Done, |
| 52894 | // Label 2862: @170394 |
| 52895 | GIM_Try, /*On fail goto*//*Label 2863*/ GIMT_Encode4(170446), // Rule ID 7777 // |
| 52896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus), |
| 52897 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 52898 | GIM_CheckHasNoUse, /*MI*/0, |
| 52899 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52901 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i32>> => (DS_CMPSTORE_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$swap, anonymous_15876:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 52902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B32), |
| 52903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52904 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52905 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 52908 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52909 | GIR_RootConstrainSelectedInstOperands, |
| 52910 | // GIR_Coverage, 7777, |
| 52911 | GIR_EraseRootFromParent_Done, |
| 52912 | // Label 2863: @170446 |
| 52913 | GIM_Try, /*On fail goto*//*Label 2864*/ GIMT_Encode4(170502), // Rule ID 7768 // |
| 52914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 52915 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 52917 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52919 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i32>> => (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32), |
| 52921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 52922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52923 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52924 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52926 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52927 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52928 | GIR_RootConstrainSelectedInstOperands, |
| 52929 | // GIR_Coverage, 7768, |
| 52930 | GIR_EraseRootFromParent_Done, |
| 52931 | // Label 2864: @170502 |
| 52932 | GIM_Try, /*On fail goto*//*Label 2865*/ GIMT_Encode4(170558), // Rule ID 7770 // |
| 52933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 52934 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 52936 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52937 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52938 | // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i32>> => (DS_CMPST_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32_gfx9), |
| 52940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 52941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52942 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52943 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52947 | GIR_RootConstrainSelectedInstOperands, |
| 52948 | // GIR_Coverage, 7770, |
| 52949 | GIR_EraseRootFromParent_Done, |
| 52950 | // Label 2865: @170558 |
| 52951 | GIM_Try, /*On fail goto*//*Label 2866*/ GIMT_Encode4(170614), // Rule ID 7772 // |
| 52952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10), |
| 52953 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 52954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 52955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52957 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i32>> => (DS_CMPST_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$cmp, anonymous_15876:{ *:[i32] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 52958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B32), |
| 52959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 52960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52961 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52962 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 52965 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52966 | GIR_RootConstrainSelectedInstOperands, |
| 52967 | // GIR_Coverage, 7772, |
| 52968 | GIR_EraseRootFromParent_Done, |
| 52969 | // Label 2866: @170614 |
| 52970 | GIM_Try, /*On fail goto*//*Label 2867*/ GIMT_Encode4(170670), // Rule ID 7774 // |
| 52971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 52972 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 52973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 52974 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52975 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52976 | // (atomic_cmp_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i32>> => (DS_CMPSTORE_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$swap, anonymous_15876:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 52977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32_gfx9), |
| 52978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 52979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52980 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 52981 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 52982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 52983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 52984 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 52985 | GIR_RootConstrainSelectedInstOperands, |
| 52986 | // GIR_Coverage, 7774, |
| 52987 | GIR_EraseRootFromParent_Done, |
| 52988 | // Label 2867: @170670 |
| 52989 | GIM_Try, /*On fail goto*//*Label 2868*/ GIMT_Encode4(170726), // Rule ID 7776 // |
| 52990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus), |
| 52991 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 52992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 52993 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 52994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 52995 | // (atomic_cmp_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$cmp, i32:{ *:[i32] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i32>> => (DS_CMPSTORE_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$swap, anonymous_15876:{ *:[i32] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 52996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B32), |
| 52997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 52998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 52999 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53000 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53003 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53004 | GIR_RootConstrainSelectedInstOperands, |
| 53005 | // GIR_Coverage, 7776, |
| 53006 | GIR_EraseRootFromParent_Done, |
| 53007 | // Label 2868: @170726 |
| 53008 | GIM_Reject, |
| 53009 | // Label 2858: @170727 |
| 53010 | GIM_Reject, |
| 53011 | // Label 2856: @170728 |
| 53012 | GIM_Try, /*On fail goto*//*Label 2869*/ GIMT_Encode4(171280), |
| 53013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 53014 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 53015 | GIM_Try, /*On fail goto*//*Label 2870*/ GIMT_Encode4(170791), // Rule ID 7950 // |
| 53016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 53017 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53018 | GIM_CheckHasNoUse, /*MI*/0, |
| 53019 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53021 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_noret_i64>> => (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64), |
| 53023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53024 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53025 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53029 | GIR_RootConstrainSelectedInstOperands, |
| 53030 | // GIR_Coverage, 7950, |
| 53031 | GIR_EraseRootFromParent_Done, |
| 53032 | // Label 2870: @170791 |
| 53033 | GIM_Try, /*On fail goto*//*Label 2871*/ GIMT_Encode4(170843), // Rule ID 7952 // |
| 53034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 53035 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53036 | GIM_CheckHasNoUse, /*MI*/0, |
| 53037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53039 | // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>> => (DS_CMPST_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64_gfx9), |
| 53041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53042 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53043 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53046 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53047 | GIR_RootConstrainSelectedInstOperands, |
| 53048 | // GIR_Coverage, 7952, |
| 53049 | GIR_EraseRootFromParent_Done, |
| 53050 | // Label 2871: @170843 |
| 53051 | GIM_Try, /*On fail goto*//*Label 2872*/ GIMT_Encode4(170895), // Rule ID 7954 // |
| 53052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10), |
| 53053 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53054 | GIM_CheckHasNoUse, /*MI*/0, |
| 53055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53057 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>> => (DS_CMPST_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_B64), |
| 53059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53060 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53061 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53065 | GIR_RootConstrainSelectedInstOperands, |
| 53066 | // GIR_Coverage, 7954, |
| 53067 | GIR_EraseRootFromParent_Done, |
| 53068 | // Label 2872: @170895 |
| 53069 | GIM_Try, /*On fail goto*//*Label 2873*/ GIMT_Encode4(170947), // Rule ID 7956 // |
| 53070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 53071 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53072 | GIM_CheckHasNoUse, /*MI*/0, |
| 53073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53074 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53075 | // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_noret_i64>> => (DS_CMPSTORE_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$swap, anonymous_15875:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64_gfx9), |
| 53077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53078 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53079 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53082 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53083 | GIR_RootConstrainSelectedInstOperands, |
| 53084 | // GIR_Coverage, 7956, |
| 53085 | GIR_EraseRootFromParent_Done, |
| 53086 | // Label 2873: @170947 |
| 53087 | GIM_Try, /*On fail goto*//*Label 2874*/ GIMT_Encode4(170999), // Rule ID 7958 // |
| 53088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus), |
| 53089 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53090 | GIM_CheckHasNoUse, /*MI*/0, |
| 53091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53093 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_noret_i64>> => (DS_CMPSTORE_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$swap, anonymous_15875:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_B64), |
| 53095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53096 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53097 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53100 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53101 | GIR_RootConstrainSelectedInstOperands, |
| 53102 | // GIR_Coverage, 7958, |
| 53103 | GIR_EraseRootFromParent_Done, |
| 53104 | // Label 2874: @170999 |
| 53105 | GIM_Try, /*On fail goto*//*Label 2875*/ GIMT_Encode4(171055), // Rule ID 7949 // |
| 53106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 53107 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53109 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53111 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_m0_i64>> => (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64), |
| 53113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53115 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53116 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53119 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53120 | GIR_RootConstrainSelectedInstOperands, |
| 53121 | // GIR_Coverage, 7949, |
| 53122 | GIR_EraseRootFromParent_Done, |
| 53123 | // Label 2875: @171055 |
| 53124 | GIM_Try, /*On fail goto*//*Label 2876*/ GIMT_Encode4(171111), // Rule ID 7951 // |
| 53125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init_isGFX6GFX7GFX8GFX9GFX10), |
| 53126 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53128 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53130 | // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>> => (DS_CMPST_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64_gfx9), |
| 53132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53134 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53135 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53139 | GIR_RootConstrainSelectedInstOperands, |
| 53140 | // GIR_Coverage, 7951, |
| 53141 | GIR_EraseRootFromParent_Done, |
| 53142 | // Label 2876: @171111 |
| 53143 | GIM_Try, /*On fail goto*//*Label 2877*/ GIMT_Encode4(171167), // Rule ID 7953 // |
| 53144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX6GFX7GFX8GFX9GFX10), |
| 53145 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53149 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>> => (DS_CMPST_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$cmp, anonymous_15875:{ *:[i64] }:$swap, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPST_RTN_B64), |
| 53151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53153 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53154 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53158 | GIR_RootConstrainSelectedInstOperands, |
| 53159 | // GIR_Coverage, 7953, |
| 53160 | GIR_EraseRootFromParent_Done, |
| 53161 | // Label 2877: @171167 |
| 53162 | GIM_Try, /*On fail goto*//*Label 2878*/ GIMT_Encode4(171223), // Rule ID 7955 // |
| 53163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 53164 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53166 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53167 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53168 | // (atomic_cmp_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_local_i64>> => (DS_CMPSTORE_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$swap, anonymous_15875:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64_gfx9), |
| 53170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53172 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53173 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53177 | GIR_RootConstrainSelectedInstOperands, |
| 53178 | // GIR_Coverage, 7955, |
| 53179 | GIR_EraseRootFromParent_Done, |
| 53180 | // Label 2878: @171223 |
| 53181 | GIM_Try, /*On fail goto*//*Label 2879*/ GIMT_Encode4(171279), // Rule ID 7957 // |
| 53182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_isGFX11Plus), |
| 53183 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53185 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53187 | // (atomic_cmp_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$cmp, i64:{ *:[i64] }:$swap)<<P:Predicate_atomic_cmp_swap_region_m0_i64>> => (DS_CMPSTORE_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$swap, anonymous_15875:{ *:[i64] }:$cmp, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_CMPSTORE_RTN_B64), |
| 53189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53191 | GIR_RootToRootCopy, /*OpIdx*/3, // swap |
| 53192 | GIR_RootToRootCopy, /*OpIdx*/2, // cmp |
| 53193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53195 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53196 | GIR_RootConstrainSelectedInstOperands, |
| 53197 | // GIR_Coverage, 7957, |
| 53198 | GIR_EraseRootFromParent_Done, |
| 53199 | // Label 2879: @171279 |
| 53200 | GIM_Reject, |
| 53201 | // Label 2869: @171280 |
| 53202 | GIM_Reject, |
| 53203 | // Label 2857: @171281 |
| 53204 | GIM_Reject, |
| 53205 | // Label 18: @171282 |
| 53206 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2882*/ GIMT_Encode4(173493), |
| 53207 | /*GILLT_s32*//*Label 2880*/ GIMT_Encode4(171301), |
| 53208 | /*GILLT_s64*//*Label 2881*/ GIMT_Encode4(172397), |
| 53209 | // Label 2880: @171301 |
| 53210 | GIM_Try, /*On fail goto*//*Label 2883*/ GIMT_Encode4(172396), |
| 53211 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53212 | GIM_Try, /*On fail goto*//*Label 2884*/ GIMT_Encode4(171371), // Rule ID 5252 // |
| 53213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53214 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53215 | GIM_CheckHasNoUse, /*MI*/0, |
| 53216 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53218 | // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>> => (BUFFER_ATOMIC_SWAP_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64), |
| 53220 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53226 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53227 | GIR_RootConstrainSelectedInstOperands, |
| 53228 | // GIR_Coverage, 5252, |
| 53229 | GIR_EraseRootFromParent_Done, |
| 53230 | // Label 2884: @171371 |
| 53231 | GIM_Try, /*On fail goto*//*Label 2885*/ GIMT_Encode4(171430), // Rule ID 5256 // |
| 53232 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53233 | GIM_CheckHasNoUse, /*MI*/0, |
| 53234 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53235 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53236 | // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>> => (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64), |
| 53238 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53245 | GIR_RootConstrainSelectedInstOperands, |
| 53246 | // GIR_Coverage, 5256, |
| 53247 | GIR_EraseRootFromParent_Done, |
| 53248 | // Label 2885: @171430 |
| 53249 | GIM_Try, /*On fail goto*//*Label 2886*/ GIMT_Encode4(171496), // Rule ID 5248 // |
| 53250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53251 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53253 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53254 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53255 | // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>> => (BUFFER_ATOMIC_SWAP_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_ADDR64_RTN), |
| 53257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53258 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53264 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53265 | GIR_RootConstrainSelectedInstOperands, |
| 53266 | // GIR_Coverage, 5248, |
| 53267 | GIR_EraseRootFromParent_Done, |
| 53268 | // Label 2886: @171496 |
| 53269 | GIM_Try, /*On fail goto*//*Label 2887*/ GIMT_Encode4(171559), // Rule ID 5254 // |
| 53270 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53272 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53274 | // (atomic_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>> => (BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_ADDR64_RTN), |
| 53276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53277 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53283 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53284 | GIR_RootConstrainSelectedInstOperands, |
| 53285 | // GIR_Coverage, 5254, |
| 53286 | GIR_EraseRootFromParent_Done, |
| 53287 | // Label 2887: @171559 |
| 53288 | GIM_Try, /*On fail goto*//*Label 2888*/ GIMT_Encode4(171616), // Rule ID 5251 // |
| 53289 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53290 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53291 | GIM_CheckHasNoUse, /*MI*/0, |
| 53292 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53293 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53294 | // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>> => (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET), |
| 53296 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53302 | GIR_RootConstrainSelectedInstOperands, |
| 53303 | // GIR_Coverage, 5251, |
| 53304 | GIR_EraseRootFromParent_Done, |
| 53305 | // Label 2888: @171616 |
| 53306 | GIM_Try, /*On fail goto*//*Label 2889*/ GIMT_Encode4(171670), // Rule ID 5255 // |
| 53307 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53308 | GIM_CheckHasNoUse, /*MI*/0, |
| 53309 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53310 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53311 | // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i32>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET), |
| 53313 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53318 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53319 | GIR_RootConstrainSelectedInstOperands, |
| 53320 | // GIR_Coverage, 5255, |
| 53321 | GIR_EraseRootFromParent_Done, |
| 53322 | // Label 2889: @171670 |
| 53323 | GIM_Try, /*On fail goto*//*Label 2890*/ GIMT_Encode4(171731), // Rule ID 5247 // |
| 53324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53325 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53327 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53329 | // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>> => (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN), |
| 53331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53332 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53338 | GIR_RootConstrainSelectedInstOperands, |
| 53339 | // GIR_Coverage, 5247, |
| 53340 | GIR_EraseRootFromParent_Done, |
| 53341 | // Label 2890: @171731 |
| 53342 | GIM_Try, /*On fail goto*//*Label 2891*/ GIMT_Encode4(171789), // Rule ID 5253 // |
| 53343 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53345 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53346 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53347 | // (atomic_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_swap_global_i32>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN), |
| 53349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53350 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53355 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53356 | GIR_RootConstrainSelectedInstOperands, |
| 53357 | // GIR_Coverage, 5253, |
| 53358 | GIR_EraseRootFromParent_Done, |
| 53359 | // Label 2891: @171789 |
| 53360 | GIM_Try, /*On fail goto*//*Label 2892*/ GIMT_Encode4(171843), // Rule ID 7759 // |
| 53361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 53362 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53363 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53366 | // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_m0_i32>> => (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32), |
| 53368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53370 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53374 | GIR_RootConstrainSelectedInstOperands, |
| 53375 | // GIR_Coverage, 7759, |
| 53376 | GIR_EraseRootFromParent_Done, |
| 53377 | // Label 2892: @171843 |
| 53378 | GIM_Try, /*On fail goto*//*Label 2893*/ GIMT_Encode4(171897), // Rule ID 7760 // |
| 53379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 53380 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53382 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53384 | // (atomic_swap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_local_i32>> => (DS_WRXCHG_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32_gfx9), |
| 53386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53388 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53391 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53392 | GIR_RootConstrainSelectedInstOperands, |
| 53393 | // GIR_Coverage, 7760, |
| 53394 | GIR_EraseRootFromParent_Done, |
| 53395 | // Label 2893: @171897 |
| 53396 | GIM_Try, /*On fail goto*//*Label 2894*/ GIMT_Encode4(171951), // Rule ID 7761 // |
| 53397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 53398 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53402 | // (atomic_swap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_swap_region_m0_i32>> => (DS_WRXCHG_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B32), |
| 53404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53406 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53410 | GIR_RootConstrainSelectedInstOperands, |
| 53411 | // GIR_Coverage, 7761, |
| 53412 | GIR_EraseRootFromParent_Done, |
| 53413 | // Label 2894: @171951 |
| 53414 | GIM_Try, /*On fail goto*//*Label 2895*/ GIMT_Encode4(172008), // Rule ID 3643 // |
| 53415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53416 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53417 | GIM_CheckHasNoUse, /*MI*/0, |
| 53418 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53419 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 53420 | // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>> => (GLOBAL_ATOMIC_SWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 53421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR), |
| 53422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 53423 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 53425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53427 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53428 | GIR_RootConstrainSelectedInstOperands, |
| 53429 | // GIR_Coverage, 3643, |
| 53430 | GIR_EraseRootFromParent_Done, |
| 53431 | // Label 2895: @172008 |
| 53432 | GIM_Try, /*On fail goto*//*Label 2896*/ GIMT_Encode4(172069), // Rule ID 3645 // |
| 53433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53434 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53435 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53436 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 53438 | // (atomic_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>> => (GLOBAL_ATOMIC_SWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 53439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_SADDR_RTN), |
| 53440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 53442 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 53444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53447 | GIR_RootConstrainSelectedInstOperands, |
| 53448 | // GIR_Coverage, 3645, |
| 53449 | GIR_EraseRootFromParent_Done, |
| 53450 | // Label 2896: @172069 |
| 53451 | GIM_Try, /*On fail goto*//*Label 2897*/ GIMT_Encode4(172121), // Rule ID 3642 // |
| 53452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53453 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53454 | GIM_CheckHasNoUse, /*MI*/0, |
| 53455 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53456 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 53457 | // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>> => (GLOBAL_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP), |
| 53459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53460 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53463 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53464 | GIR_RootConstrainSelectedInstOperands, |
| 53465 | // GIR_Coverage, 3642, |
| 53466 | GIR_EraseRootFromParent_Done, |
| 53467 | // Label 2897: @172121 |
| 53468 | GIM_Try, /*On fail goto*//*Label 2898*/ GIMT_Encode4(172177), // Rule ID 3644 // |
| 53469 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53470 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53472 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53473 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 53474 | // (atomic_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>> => (GLOBAL_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_RTN), |
| 53476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53478 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53482 | GIR_RootConstrainSelectedInstOperands, |
| 53483 | // GIR_Coverage, 3644, |
| 53484 | GIR_EraseRootFromParent_Done, |
| 53485 | // Label 2898: @172177 |
| 53486 | GIM_Try, /*On fail goto*//*Label 2899*/ GIMT_Encode4(172230), // Rule ID 3307 // |
| 53487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53488 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53489 | GIM_CheckHasNoUse, /*MI*/0, |
| 53490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53492 | // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_noret_i32>> => (FLAT_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP), |
| 53494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53495 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53499 | GIR_RootConstrainSelectedInstOperands, |
| 53500 | // GIR_Coverage, 3307, |
| 53501 | GIR_EraseRootFromParent_Done, |
| 53502 | // Label 2899: @172230 |
| 53503 | GIM_Try, /*On fail goto*//*Label 2900*/ GIMT_Encode4(172282), // Rule ID 3367 // |
| 53504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53505 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53506 | GIM_CheckHasNoUse, /*MI*/0, |
| 53507 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53509 | // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_noret_i32>> => (FLAT_ATOMIC_SWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP), |
| 53511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53512 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53515 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53516 | GIR_RootConstrainSelectedInstOperands, |
| 53517 | // GIR_Coverage, 3367, |
| 53518 | GIR_EraseRootFromParent_Done, |
| 53519 | // Label 2900: @172282 |
| 53520 | GIM_Try, /*On fail goto*//*Label 2901*/ GIMT_Encode4(172339), // Rule ID 3306 // |
| 53521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53522 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53524 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53526 | // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_flat_i32>> => (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN), |
| 53528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53530 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53533 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53534 | GIR_RootConstrainSelectedInstOperands, |
| 53535 | // GIR_Coverage, 3306, |
| 53536 | GIR_EraseRootFromParent_Done, |
| 53537 | // Label 2901: @172339 |
| 53538 | GIM_Try, /*On fail goto*//*Label 2902*/ GIMT_Encode4(172395), // Rule ID 3366 // |
| 53539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53540 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53542 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53543 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53544 | // (atomic_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_swap_global_i32>> => (FLAT_ATOMIC_SWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 53545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_RTN), |
| 53546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53548 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53551 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53552 | GIR_RootConstrainSelectedInstOperands, |
| 53553 | // GIR_Coverage, 3366, |
| 53554 | GIR_EraseRootFromParent_Done, |
| 53555 | // Label 2902: @172395 |
| 53556 | GIM_Reject, |
| 53557 | // Label 2883: @172396 |
| 53558 | GIM_Reject, |
| 53559 | // Label 2881: @172397 |
| 53560 | GIM_Try, /*On fail goto*//*Label 2903*/ GIMT_Encode4(173492), |
| 53561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 53562 | GIM_Try, /*On fail goto*//*Label 2904*/ GIMT_Encode4(172467), // Rule ID 5348 // |
| 53563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53564 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53565 | GIM_CheckHasNoUse, /*MI*/0, |
| 53566 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53568 | // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>> => (BUFFER_ATOMIC_SWAP_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64), |
| 53570 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53577 | GIR_RootConstrainSelectedInstOperands, |
| 53578 | // GIR_Coverage, 5348, |
| 53579 | GIR_EraseRootFromParent_Done, |
| 53580 | // Label 2904: @172467 |
| 53581 | GIM_Try, /*On fail goto*//*Label 2905*/ GIMT_Encode4(172526), // Rule ID 5352 // |
| 53582 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53583 | GIM_CheckHasNoUse, /*MI*/0, |
| 53584 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53586 | // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64), |
| 53588 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53594 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53595 | GIR_RootConstrainSelectedInstOperands, |
| 53596 | // GIR_Coverage, 5352, |
| 53597 | GIR_EraseRootFromParent_Done, |
| 53598 | // Label 2905: @172526 |
| 53599 | GIM_Try, /*On fail goto*//*Label 2906*/ GIMT_Encode4(172592), // Rule ID 5346 // |
| 53600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53601 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53603 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53605 | // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>> => (BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_ADDR64_RTN), |
| 53607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53608 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53614 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53615 | GIR_RootConstrainSelectedInstOperands, |
| 53616 | // GIR_Coverage, 5346, |
| 53617 | GIR_EraseRootFromParent_Done, |
| 53618 | // Label 2906: @172592 |
| 53619 | GIM_Try, /*On fail goto*//*Label 2907*/ GIMT_Encode4(172655), // Rule ID 5350 // |
| 53620 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53622 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53623 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53624 | // (atomic_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_ADDR64_RTN), |
| 53626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53627 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53633 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53634 | GIR_RootConstrainSelectedInstOperands, |
| 53635 | // GIR_Coverage, 5350, |
| 53636 | GIR_EraseRootFromParent_Done, |
| 53637 | // Label 2907: @172655 |
| 53638 | GIM_Try, /*On fail goto*//*Label 2908*/ GIMT_Encode4(172712), // Rule ID 5347 // |
| 53639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53640 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53641 | GIM_CheckHasNoUse, /*MI*/0, |
| 53642 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53643 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53644 | // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>> => (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET), |
| 53646 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53651 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53652 | GIR_RootConstrainSelectedInstOperands, |
| 53653 | // GIR_Coverage, 5347, |
| 53654 | GIR_EraseRootFromParent_Done, |
| 53655 | // Label 2908: @172712 |
| 53656 | GIM_Try, /*On fail goto*//*Label 2909*/ GIMT_Encode4(172766), // Rule ID 5351 // |
| 53657 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53658 | GIM_CheckHasNoUse, /*MI*/0, |
| 53659 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53661 | // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_noret_i64>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET), |
| 53663 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53667 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53669 | GIR_RootConstrainSelectedInstOperands, |
| 53670 | // GIR_Coverage, 5351, |
| 53671 | GIR_EraseRootFromParent_Done, |
| 53672 | // Label 2909: @172766 |
| 53673 | GIM_Try, /*On fail goto*//*Label 2910*/ GIMT_Encode4(172827), // Rule ID 5345 // |
| 53674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53675 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53677 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53679 | // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>> => (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN), |
| 53681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53682 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53688 | GIR_RootConstrainSelectedInstOperands, |
| 53689 | // GIR_Coverage, 5345, |
| 53690 | GIR_EraseRootFromParent_Done, |
| 53691 | // Label 2910: @172827 |
| 53692 | GIM_Try, /*On fail goto*//*Label 2911*/ GIMT_Encode4(172885), // Rule ID 5349 // |
| 53693 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53695 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53696 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 53697 | // (atomic_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_swap_global_i64>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN), |
| 53699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53700 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 53703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53706 | GIR_RootConstrainSelectedInstOperands, |
| 53707 | // GIR_Coverage, 5349, |
| 53708 | GIR_EraseRootFromParent_Done, |
| 53709 | // Label 2911: @172885 |
| 53710 | GIM_Try, /*On fail goto*//*Label 2912*/ GIMT_Encode4(172939), // Rule ID 7868 // |
| 53711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 53712 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53714 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53716 | // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_m0_i64>> => (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64), |
| 53718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53720 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53724 | GIR_RootConstrainSelectedInstOperands, |
| 53725 | // GIR_Coverage, 7868, |
| 53726 | GIR_EraseRootFromParent_Done, |
| 53727 | // Label 2912: @172939 |
| 53728 | GIM_Try, /*On fail goto*//*Label 2913*/ GIMT_Encode4(172993), // Rule ID 7869 // |
| 53729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 53730 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 53731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53734 | // (atomic_swap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_local_i64>> => (DS_WRXCHG_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 53735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64_gfx9), |
| 53736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53738 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53742 | GIR_RootConstrainSelectedInstOperands, |
| 53743 | // GIR_Coverage, 7869, |
| 53744 | GIR_EraseRootFromParent_Done, |
| 53745 | // Label 2913: @172993 |
| 53746 | GIM_Try, /*On fail goto*//*Label 2914*/ GIMT_Encode4(173047), // Rule ID 7870 // |
| 53747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 53748 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 53749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 53752 | // (atomic_swap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_swap_region_m0_i64>> => (DS_WRXCHG_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 53753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_WRXCHG_RTN_B64), |
| 53754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 53756 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 53757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53760 | GIR_RootConstrainSelectedInstOperands, |
| 53761 | // GIR_Coverage, 7870, |
| 53762 | GIR_EraseRootFromParent_Done, |
| 53763 | // Label 2914: @173047 |
| 53764 | GIM_Try, /*On fail goto*//*Label 2915*/ GIMT_Encode4(173104), // Rule ID 3699 // |
| 53765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53766 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53767 | GIM_CheckHasNoUse, /*MI*/0, |
| 53768 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53769 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 53770 | // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>> => (GLOBAL_ATOMIC_SWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 53771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR), |
| 53772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 53773 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 53775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53778 | GIR_RootConstrainSelectedInstOperands, |
| 53779 | // GIR_Coverage, 3699, |
| 53780 | GIR_EraseRootFromParent_Done, |
| 53781 | // Label 2915: @173104 |
| 53782 | GIM_Try, /*On fail goto*//*Label 2916*/ GIMT_Encode4(173165), // Rule ID 3701 // |
| 53783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53784 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 53788 | // (atomic_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>> => (GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 53789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_SADDR_RTN), |
| 53790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 53792 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 53794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 53795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53796 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53797 | GIR_RootConstrainSelectedInstOperands, |
| 53798 | // GIR_Coverage, 3701, |
| 53799 | GIR_EraseRootFromParent_Done, |
| 53800 | // Label 2916: @173165 |
| 53801 | GIM_Try, /*On fail goto*//*Label 2917*/ GIMT_Encode4(173217), // Rule ID 3698 // |
| 53802 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53803 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53804 | GIM_CheckHasNoUse, /*MI*/0, |
| 53805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 53807 | // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>> => (GLOBAL_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2), |
| 53809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53810 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53813 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53814 | GIR_RootConstrainSelectedInstOperands, |
| 53815 | // GIR_Coverage, 3698, |
| 53816 | GIR_EraseRootFromParent_Done, |
| 53817 | // Label 2917: @173217 |
| 53818 | GIM_Try, /*On fail goto*//*Label 2918*/ GIMT_Encode4(173273), // Rule ID 3700 // |
| 53819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 53820 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53822 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 53824 | // (atomic_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>> => (GLOBAL_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SWAP_X2_RTN), |
| 53826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53828 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53832 | GIR_RootConstrainSelectedInstOperands, |
| 53833 | // GIR_Coverage, 3700, |
| 53834 | GIR_EraseRootFromParent_Done, |
| 53835 | // Label 2918: @173273 |
| 53836 | GIM_Try, /*On fail goto*//*Label 2919*/ GIMT_Encode4(173326), // Rule ID 3333 // |
| 53837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53838 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53839 | GIM_CheckHasNoUse, /*MI*/0, |
| 53840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53842 | // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_noret_i64>> => (FLAT_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2), |
| 53844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53845 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53849 | GIR_RootConstrainSelectedInstOperands, |
| 53850 | // GIR_Coverage, 3333, |
| 53851 | GIR_EraseRootFromParent_Done, |
| 53852 | // Label 2919: @173326 |
| 53853 | GIM_Try, /*On fail goto*//*Label 2920*/ GIMT_Encode4(173378), // Rule ID 3393 // |
| 53854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53855 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53856 | GIM_CheckHasNoUse, /*MI*/0, |
| 53857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53859 | // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_noret_i64>> => (FLAT_ATOMIC_SWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2), |
| 53861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53862 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53865 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53866 | GIR_RootConstrainSelectedInstOperands, |
| 53867 | // GIR_Coverage, 3393, |
| 53868 | GIR_EraseRootFromParent_Done, |
| 53869 | // Label 2920: @173378 |
| 53870 | GIM_Try, /*On fail goto*//*Label 2921*/ GIMT_Encode4(173435), // Rule ID 3332 // |
| 53871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53872 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53874 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53876 | // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_flat_i64>> => (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN), |
| 53878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53880 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53883 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53884 | GIR_RootConstrainSelectedInstOperands, |
| 53885 | // GIR_Coverage, 3332, |
| 53886 | GIR_EraseRootFromParent_Done, |
| 53887 | // Label 2921: @173435 |
| 53888 | GIM_Try, /*On fail goto*//*Label 2922*/ GIMT_Encode4(173491), // Rule ID 3392 // |
| 53889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 53890 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 53892 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 53894 | // (atomic_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_swap_global_i64>> => (FLAT_ATOMIC_SWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 53895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SWAP_X2_RTN), |
| 53896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 53897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 53898 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 53899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 53900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53902 | GIR_RootConstrainSelectedInstOperands, |
| 53903 | // GIR_Coverage, 3392, |
| 53904 | GIR_EraseRootFromParent_Done, |
| 53905 | // Label 2922: @173491 |
| 53906 | GIM_Reject, |
| 53907 | // Label 2903: @173492 |
| 53908 | GIM_Reject, |
| 53909 | // Label 2882: @173493 |
| 53910 | GIM_Reject, |
| 53911 | // Label 19: @173494 |
| 53912 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2925*/ GIMT_Encode4(176005), |
| 53913 | /*GILLT_s32*//*Label 2923*/ GIMT_Encode4(173513), |
| 53914 | /*GILLT_s64*//*Label 2924*/ GIMT_Encode4(174759), |
| 53915 | // Label 2923: @173513 |
| 53916 | GIM_Try, /*On fail goto*//*Label 2926*/ GIMT_Encode4(174758), |
| 53917 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 53918 | GIM_Try, /*On fail goto*//*Label 2927*/ GIMT_Encode4(173583), // Rule ID 5260 // |
| 53919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53920 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53921 | GIM_CheckHasNoUse, /*MI*/0, |
| 53922 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53923 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53924 | // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>> => (BUFFER_ATOMIC_ADD_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64), |
| 53926 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53932 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53933 | GIR_RootConstrainSelectedInstOperands, |
| 53934 | // GIR_Coverage, 5260, |
| 53935 | GIR_EraseRootFromParent_Done, |
| 53936 | // Label 2927: @173583 |
| 53937 | GIM_Try, /*On fail goto*//*Label 2928*/ GIMT_Encode4(173642), // Rule ID 5264 // |
| 53938 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53939 | GIM_CheckHasNoUse, /*MI*/0, |
| 53940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53941 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53942 | // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>> => (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64), |
| 53944 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 53950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53951 | GIR_RootConstrainSelectedInstOperands, |
| 53952 | // GIR_Coverage, 5264, |
| 53953 | GIR_EraseRootFromParent_Done, |
| 53954 | // Label 2928: @173642 |
| 53955 | GIM_Try, /*On fail goto*//*Label 2929*/ GIMT_Encode4(173708), // Rule ID 5258 // |
| 53956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53957 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53959 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53961 | // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>> => (BUFFER_ATOMIC_ADD_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_ADDR64_RTN), |
| 53963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53964 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53971 | GIR_RootConstrainSelectedInstOperands, |
| 53972 | // GIR_Coverage, 5258, |
| 53973 | GIR_EraseRootFromParent_Done, |
| 53974 | // Label 2929: @173708 |
| 53975 | GIM_Try, /*On fail goto*//*Label 2930*/ GIMT_Encode4(173771), // Rule ID 5262 // |
| 53976 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 53978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 53980 | // (atomic_load_add:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>> => (BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 53981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_ADDR64_RTN), |
| 53982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 53983 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 53984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 53985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 53986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 53987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 53988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 53989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 53990 | GIR_RootConstrainSelectedInstOperands, |
| 53991 | // GIR_Coverage, 5262, |
| 53992 | GIR_EraseRootFromParent_Done, |
| 53993 | // Label 2930: @173771 |
| 53994 | GIM_Try, /*On fail goto*//*Label 2931*/ GIMT_Encode4(173828), // Rule ID 5259 // |
| 53995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 53996 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 53997 | GIM_CheckHasNoUse, /*MI*/0, |
| 53998 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 53999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54000 | // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>> => (BUFFER_ATOMIC_ADD_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET), |
| 54002 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54007 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54008 | GIR_RootConstrainSelectedInstOperands, |
| 54009 | // GIR_Coverage, 5259, |
| 54010 | GIR_EraseRootFromParent_Done, |
| 54011 | // Label 2931: @173828 |
| 54012 | GIM_Try, /*On fail goto*//*Label 2932*/ GIMT_Encode4(173882), // Rule ID 5263 // |
| 54013 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54014 | GIM_CheckHasNoUse, /*MI*/0, |
| 54015 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54016 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54017 | // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i32>> => (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET), |
| 54019 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54024 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54025 | GIR_RootConstrainSelectedInstOperands, |
| 54026 | // GIR_Coverage, 5263, |
| 54027 | GIR_EraseRootFromParent_Done, |
| 54028 | // Label 2932: @173882 |
| 54029 | GIM_Try, /*On fail goto*//*Label 2933*/ GIMT_Encode4(173943), // Rule ID 5257 // |
| 54030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54031 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54033 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54034 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54035 | // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>> => (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN), |
| 54037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54038 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54044 | GIR_RootConstrainSelectedInstOperands, |
| 54045 | // GIR_Coverage, 5257, |
| 54046 | GIR_EraseRootFromParent_Done, |
| 54047 | // Label 2933: @173943 |
| 54048 | GIM_Try, /*On fail goto*//*Label 2934*/ GIMT_Encode4(174001), // Rule ID 5261 // |
| 54049 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54051 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54053 | // (atomic_load_add:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i32>> => (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN), |
| 54055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54056 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54061 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54062 | GIR_RootConstrainSelectedInstOperands, |
| 54063 | // GIR_Coverage, 5261, |
| 54064 | GIR_EraseRootFromParent_Done, |
| 54065 | // Label 2934: @174001 |
| 54066 | GIM_Try, /*On fail goto*//*Label 2935*/ GIMT_Encode4(174051), // Rule ID 7763 // |
| 54067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54068 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54069 | GIM_CheckHasNoUse, /*MI*/0, |
| 54070 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54072 | // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i32>> => (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32), |
| 54074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54075 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54079 | GIR_RootConstrainSelectedInstOperands, |
| 54080 | // GIR_Coverage, 7763, |
| 54081 | GIR_EraseRootFromParent_Done, |
| 54082 | // Label 2935: @174051 |
| 54083 | GIM_Try, /*On fail goto*//*Label 2936*/ GIMT_Encode4(174101), // Rule ID 7765 // |
| 54084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54085 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54086 | GIM_CheckHasNoUse, /*MI*/0, |
| 54087 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54088 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54089 | // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_noret_i32>> => (DS_ADD_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32_gfx9), |
| 54091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54092 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54095 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54096 | GIR_RootConstrainSelectedInstOperands, |
| 54097 | // GIR_Coverage, 7765, |
| 54098 | GIR_EraseRootFromParent_Done, |
| 54099 | // Label 2936: @174101 |
| 54100 | GIM_Try, /*On fail goto*//*Label 2937*/ GIMT_Encode4(174151), // Rule ID 7767 // |
| 54101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54102 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54103 | GIM_CheckHasNoUse, /*MI*/0, |
| 54104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54106 | // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i32>> => (DS_ADD_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U32), |
| 54108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54109 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54113 | GIR_RootConstrainSelectedInstOperands, |
| 54114 | // GIR_Coverage, 7767, |
| 54115 | GIR_EraseRootFromParent_Done, |
| 54116 | // Label 2937: @174151 |
| 54117 | GIM_Try, /*On fail goto*//*Label 2938*/ GIMT_Encode4(174205), // Rule ID 7762 // |
| 54118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54119 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54121 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54122 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54123 | // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_m0_i32>> => (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32), |
| 54125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54127 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54131 | GIR_RootConstrainSelectedInstOperands, |
| 54132 | // GIR_Coverage, 7762, |
| 54133 | GIR_EraseRootFromParent_Done, |
| 54134 | // Label 2938: @174205 |
| 54135 | GIM_Try, /*On fail goto*//*Label 2939*/ GIMT_Encode4(174259), // Rule ID 7764 // |
| 54136 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54137 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54139 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54140 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54141 | // (atomic_load_add:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_local_i32>> => (DS_ADD_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32_gfx9), |
| 54143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54145 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54148 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54149 | GIR_RootConstrainSelectedInstOperands, |
| 54150 | // GIR_Coverage, 7764, |
| 54151 | GIR_EraseRootFromParent_Done, |
| 54152 | // Label 2939: @174259 |
| 54153 | GIM_Try, /*On fail goto*//*Label 2940*/ GIMT_Encode4(174313), // Rule ID 7766 // |
| 54154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54155 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54157 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54159 | // (atomic_load_add_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_add_region_m0_i32>> => (DS_ADD_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U32), |
| 54161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54163 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54166 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54167 | GIR_RootConstrainSelectedInstOperands, |
| 54168 | // GIR_Coverage, 7766, |
| 54169 | GIR_EraseRootFromParent_Done, |
| 54170 | // Label 2940: @174313 |
| 54171 | GIM_Try, /*On fail goto*//*Label 2941*/ GIMT_Encode4(174370), // Rule ID 3198 // |
| 54172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54173 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54174 | GIM_CheckHasNoUse, /*MI*/0, |
| 54175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 54177 | // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>> => (GLOBAL_ATOMIC_ADD_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 54178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR), |
| 54179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 54180 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 54182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54184 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54185 | GIR_RootConstrainSelectedInstOperands, |
| 54186 | // GIR_Coverage, 3198, |
| 54187 | GIR_EraseRootFromParent_Done, |
| 54188 | // Label 2941: @174370 |
| 54189 | GIM_Try, /*On fail goto*//*Label 2942*/ GIMT_Encode4(174431), // Rule ID 3200 // |
| 54190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54191 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54193 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 54195 | // (atomic_load_add:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>> => (GLOBAL_ATOMIC_ADD_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 54196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_SADDR_RTN), |
| 54197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 54199 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 54201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54203 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54204 | GIR_RootConstrainSelectedInstOperands, |
| 54205 | // GIR_Coverage, 3200, |
| 54206 | GIR_EraseRootFromParent_Done, |
| 54207 | // Label 2942: @174431 |
| 54208 | GIM_Try, /*On fail goto*//*Label 2943*/ GIMT_Encode4(174483), // Rule ID 3197 // |
| 54209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54210 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54211 | GIM_CheckHasNoUse, /*MI*/0, |
| 54212 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54213 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 54214 | // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>> => (GLOBAL_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD), |
| 54216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54217 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54221 | GIR_RootConstrainSelectedInstOperands, |
| 54222 | // GIR_Coverage, 3197, |
| 54223 | GIR_EraseRootFromParent_Done, |
| 54224 | // Label 2943: @174483 |
| 54225 | GIM_Try, /*On fail goto*//*Label 2944*/ GIMT_Encode4(174539), // Rule ID 3199 // |
| 54226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54227 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54228 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54229 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54230 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 54231 | // (atomic_load_add:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>> => (GLOBAL_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_RTN), |
| 54233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54235 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54239 | GIR_RootConstrainSelectedInstOperands, |
| 54240 | // GIR_Coverage, 3199, |
| 54241 | GIR_EraseRootFromParent_Done, |
| 54242 | // Label 2944: @174539 |
| 54243 | GIM_Try, /*On fail goto*//*Label 2945*/ GIMT_Encode4(174592), // Rule ID 3189 // |
| 54244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54246 | GIM_CheckHasNoUse, /*MI*/0, |
| 54247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54249 | // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i32>> => (FLAT_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD), |
| 54251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54252 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54255 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54256 | GIR_RootConstrainSelectedInstOperands, |
| 54257 | // GIR_Coverage, 3189, |
| 54258 | GIR_EraseRootFromParent_Done, |
| 54259 | // Label 2945: @174592 |
| 54260 | GIM_Try, /*On fail goto*//*Label 2946*/ GIMT_Encode4(174644), // Rule ID 3347 // |
| 54261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54263 | GIM_CheckHasNoUse, /*MI*/0, |
| 54264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54266 | // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_noret_i32>> => (FLAT_ATOMIC_ADD VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD), |
| 54268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54269 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54273 | GIR_RootConstrainSelectedInstOperands, |
| 54274 | // GIR_Coverage, 3347, |
| 54275 | GIR_EraseRootFromParent_Done, |
| 54276 | // Label 2946: @174644 |
| 54277 | GIM_Try, /*On fail goto*//*Label 2947*/ GIMT_Encode4(174701), // Rule ID 3190 // |
| 54278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54279 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54281 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54283 | // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_flat_i32>> => (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN), |
| 54285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54287 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54291 | GIR_RootConstrainSelectedInstOperands, |
| 54292 | // GIR_Coverage, 3190, |
| 54293 | GIR_EraseRootFromParent_Done, |
| 54294 | // Label 2947: @174701 |
| 54295 | GIM_Try, /*On fail goto*//*Label 2948*/ GIMT_Encode4(174757), // Rule ID 3346 // |
| 54296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54297 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54299 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54301 | // (atomic_load_add:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_add_global_i32>> => (FLAT_ATOMIC_ADD_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 54302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_RTN), |
| 54303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54305 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54309 | GIR_RootConstrainSelectedInstOperands, |
| 54310 | // GIR_Coverage, 3346, |
| 54311 | GIR_EraseRootFromParent_Done, |
| 54312 | // Label 2948: @174757 |
| 54313 | GIM_Reject, |
| 54314 | // Label 2926: @174758 |
| 54315 | GIM_Reject, |
| 54316 | // Label 2924: @174759 |
| 54317 | GIM_Try, /*On fail goto*//*Label 2949*/ GIMT_Encode4(176004), |
| 54318 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 54319 | GIM_Try, /*On fail goto*//*Label 2950*/ GIMT_Encode4(174829), // Rule ID 5356 // |
| 54320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54321 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54322 | GIM_CheckHasNoUse, /*MI*/0, |
| 54323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54325 | // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>> => (BUFFER_ATOMIC_ADD_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64), |
| 54327 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54334 | GIR_RootConstrainSelectedInstOperands, |
| 54335 | // GIR_Coverage, 5356, |
| 54336 | GIR_EraseRootFromParent_Done, |
| 54337 | // Label 2950: @174829 |
| 54338 | GIM_Try, /*On fail goto*//*Label 2951*/ GIMT_Encode4(174888), // Rule ID 5360 // |
| 54339 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54340 | GIM_CheckHasNoUse, /*MI*/0, |
| 54341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54343 | // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64), |
| 54345 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54351 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54352 | GIR_RootConstrainSelectedInstOperands, |
| 54353 | // GIR_Coverage, 5360, |
| 54354 | GIR_EraseRootFromParent_Done, |
| 54355 | // Label 2951: @174888 |
| 54356 | GIM_Try, /*On fail goto*//*Label 2952*/ GIMT_Encode4(174954), // Rule ID 5354 // |
| 54357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54358 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54360 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54362 | // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>> => (BUFFER_ATOMIC_ADD_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_ADDR64_RTN), |
| 54364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54365 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54372 | GIR_RootConstrainSelectedInstOperands, |
| 54373 | // GIR_Coverage, 5354, |
| 54374 | GIR_EraseRootFromParent_Done, |
| 54375 | // Label 2952: @174954 |
| 54376 | GIM_Try, /*On fail goto*//*Label 2953*/ GIMT_Encode4(175017), // Rule ID 5358 // |
| 54377 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54379 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54381 | // (atomic_load_add:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_ADDR64_RTN), |
| 54383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54384 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54390 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54391 | GIR_RootConstrainSelectedInstOperands, |
| 54392 | // GIR_Coverage, 5358, |
| 54393 | GIR_EraseRootFromParent_Done, |
| 54394 | // Label 2953: @175017 |
| 54395 | GIM_Try, /*On fail goto*//*Label 2954*/ GIMT_Encode4(175074), // Rule ID 5355 // |
| 54396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54397 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54398 | GIM_CheckHasNoUse, /*MI*/0, |
| 54399 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54401 | // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>> => (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET), |
| 54403 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54409 | GIR_RootConstrainSelectedInstOperands, |
| 54410 | // GIR_Coverage, 5355, |
| 54411 | GIR_EraseRootFromParent_Done, |
| 54412 | // Label 2954: @175074 |
| 54413 | GIM_Try, /*On fail goto*//*Label 2955*/ GIMT_Encode4(175128), // Rule ID 5359 // |
| 54414 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54415 | GIM_CheckHasNoUse, /*MI*/0, |
| 54416 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54417 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54418 | // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_noret_i64>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET), |
| 54420 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54426 | GIR_RootConstrainSelectedInstOperands, |
| 54427 | // GIR_Coverage, 5359, |
| 54428 | GIR_EraseRootFromParent_Done, |
| 54429 | // Label 2955: @175128 |
| 54430 | GIM_Try, /*On fail goto*//*Label 2956*/ GIMT_Encode4(175189), // Rule ID 5353 // |
| 54431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54432 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54434 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54436 | // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>> => (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN), |
| 54438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54439 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54445 | GIR_RootConstrainSelectedInstOperands, |
| 54446 | // GIR_Coverage, 5353, |
| 54447 | GIR_EraseRootFromParent_Done, |
| 54448 | // Label 2956: @175189 |
| 54449 | GIM_Try, /*On fail goto*//*Label 2957*/ GIMT_Encode4(175247), // Rule ID 5357 // |
| 54450 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54452 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54453 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54454 | // (atomic_load_add:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_add_global_i64>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN), |
| 54456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54457 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54462 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54463 | GIR_RootConstrainSelectedInstOperands, |
| 54464 | // GIR_Coverage, 5357, |
| 54465 | GIR_EraseRootFromParent_Done, |
| 54466 | // Label 2957: @175247 |
| 54467 | GIM_Try, /*On fail goto*//*Label 2958*/ GIMT_Encode4(175297), // Rule ID 7872 // |
| 54468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54469 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54470 | GIM_CheckHasNoUse, /*MI*/0, |
| 54471 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54473 | // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_noret_i64>> => (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64), |
| 54475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54476 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54479 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54480 | GIR_RootConstrainSelectedInstOperands, |
| 54481 | // GIR_Coverage, 7872, |
| 54482 | GIR_EraseRootFromParent_Done, |
| 54483 | // Label 2958: @175297 |
| 54484 | GIM_Try, /*On fail goto*//*Label 2959*/ GIMT_Encode4(175347), // Rule ID 7874 // |
| 54485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54486 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54487 | GIM_CheckHasNoUse, /*MI*/0, |
| 54488 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54490 | // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_noret_i64>> => (DS_ADD_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64_gfx9), |
| 54492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54493 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54496 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54497 | GIR_RootConstrainSelectedInstOperands, |
| 54498 | // GIR_Coverage, 7874, |
| 54499 | GIR_EraseRootFromParent_Done, |
| 54500 | // Label 2959: @175347 |
| 54501 | GIM_Try, /*On fail goto*//*Label 2960*/ GIMT_Encode4(175397), // Rule ID 7876 // |
| 54502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54503 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54504 | GIM_CheckHasNoUse, /*MI*/0, |
| 54505 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54507 | // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_noret_i64>> => (DS_ADD_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_U64), |
| 54509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54510 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54514 | GIR_RootConstrainSelectedInstOperands, |
| 54515 | // GIR_Coverage, 7876, |
| 54516 | GIR_EraseRootFromParent_Done, |
| 54517 | // Label 2960: @175397 |
| 54518 | GIM_Try, /*On fail goto*//*Label 2961*/ GIMT_Encode4(175451), // Rule ID 7871 // |
| 54519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54520 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54522 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54523 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54524 | // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_m0_i64>> => (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64), |
| 54526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54528 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54531 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54532 | GIR_RootConstrainSelectedInstOperands, |
| 54533 | // GIR_Coverage, 7871, |
| 54534 | GIR_EraseRootFromParent_Done, |
| 54535 | // Label 2961: @175451 |
| 54536 | GIM_Try, /*On fail goto*//*Label 2962*/ GIMT_Encode4(175505), // Rule ID 7873 // |
| 54537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54538 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54540 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54542 | // (atomic_load_add:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_local_i64>> => (DS_ADD_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64_gfx9), |
| 54544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54546 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54550 | GIR_RootConstrainSelectedInstOperands, |
| 54551 | // GIR_Coverage, 7873, |
| 54552 | GIR_EraseRootFromParent_Done, |
| 54553 | // Label 2962: @175505 |
| 54554 | GIM_Try, /*On fail goto*//*Label 2963*/ GIMT_Encode4(175559), // Rule ID 7875 // |
| 54555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54556 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54558 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54560 | // (atomic_load_add_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_add_region_m0_i64>> => (DS_ADD_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_U64), |
| 54562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54564 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54567 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54568 | GIR_RootConstrainSelectedInstOperands, |
| 54569 | // GIR_Coverage, 7875, |
| 54570 | GIR_EraseRootFromParent_Done, |
| 54571 | // Label 2963: @175559 |
| 54572 | GIM_Try, /*On fail goto*//*Label 2964*/ GIMT_Encode4(175616), // Rule ID 3659 // |
| 54573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54574 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54575 | GIM_CheckHasNoUse, /*MI*/0, |
| 54576 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54577 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 54578 | // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>> => (GLOBAL_ATOMIC_ADD_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 54579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR), |
| 54580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 54581 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 54583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54585 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54586 | GIR_RootConstrainSelectedInstOperands, |
| 54587 | // GIR_Coverage, 3659, |
| 54588 | GIR_EraseRootFromParent_Done, |
| 54589 | // Label 2964: @175616 |
| 54590 | GIM_Try, /*On fail goto*//*Label 2965*/ GIMT_Encode4(175677), // Rule ID 3661 // |
| 54591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54592 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 54596 | // (atomic_load_add:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>> => (GLOBAL_ATOMIC_ADD_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 54597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_SADDR_RTN), |
| 54598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 54600 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 54602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54603 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54605 | GIR_RootConstrainSelectedInstOperands, |
| 54606 | // GIR_Coverage, 3661, |
| 54607 | GIR_EraseRootFromParent_Done, |
| 54608 | // Label 2965: @175677 |
| 54609 | GIM_Try, /*On fail goto*//*Label 2966*/ GIMT_Encode4(175729), // Rule ID 3658 // |
| 54610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54611 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54612 | GIM_CheckHasNoUse, /*MI*/0, |
| 54613 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 54615 | // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>> => (GLOBAL_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2), |
| 54617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54618 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54621 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54622 | GIR_RootConstrainSelectedInstOperands, |
| 54623 | // GIR_Coverage, 3658, |
| 54624 | GIR_EraseRootFromParent_Done, |
| 54625 | // Label 2966: @175729 |
| 54626 | GIM_Try, /*On fail goto*//*Label 2967*/ GIMT_Encode4(175785), // Rule ID 3660 // |
| 54627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54628 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54630 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 54632 | // (atomic_load_add:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>> => (GLOBAL_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_X2_RTN), |
| 54634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54636 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54640 | GIR_RootConstrainSelectedInstOperands, |
| 54641 | // GIR_Coverage, 3660, |
| 54642 | GIR_EraseRootFromParent_Done, |
| 54643 | // Label 2967: @175785 |
| 54644 | GIM_Try, /*On fail goto*//*Label 2968*/ GIMT_Encode4(175838), // Rule ID 3313 // |
| 54645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54646 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54647 | GIM_CheckHasNoUse, /*MI*/0, |
| 54648 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54650 | // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_noret_i64>> => (FLAT_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2), |
| 54652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54653 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54656 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54657 | GIR_RootConstrainSelectedInstOperands, |
| 54658 | // GIR_Coverage, 3313, |
| 54659 | GIR_EraseRootFromParent_Done, |
| 54660 | // Label 2968: @175838 |
| 54661 | GIM_Try, /*On fail goto*//*Label 2969*/ GIMT_Encode4(175890), // Rule ID 3373 // |
| 54662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54663 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54664 | GIM_CheckHasNoUse, /*MI*/0, |
| 54665 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54667 | // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_noret_i64>> => (FLAT_ATOMIC_ADD_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2), |
| 54669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54670 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54673 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54674 | GIR_RootConstrainSelectedInstOperands, |
| 54675 | // GIR_Coverage, 3373, |
| 54676 | GIR_EraseRootFromParent_Done, |
| 54677 | // Label 2969: @175890 |
| 54678 | GIM_Try, /*On fail goto*//*Label 2970*/ GIMT_Encode4(175947), // Rule ID 3312 // |
| 54679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54680 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54681 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54682 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54683 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54684 | // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_flat_i64>> => (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN), |
| 54686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54688 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54692 | GIR_RootConstrainSelectedInstOperands, |
| 54693 | // GIR_Coverage, 3312, |
| 54694 | GIR_EraseRootFromParent_Done, |
| 54695 | // Label 2970: @175947 |
| 54696 | GIM_Try, /*On fail goto*//*Label 2971*/ GIMT_Encode4(176003), // Rule ID 3372 // |
| 54697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 54698 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 54700 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54701 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 54702 | // (atomic_load_add:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_add_global_i64>> => (FLAT_ATOMIC_ADD_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 54703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_X2_RTN), |
| 54704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 54706 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54709 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54710 | GIR_RootConstrainSelectedInstOperands, |
| 54711 | // GIR_Coverage, 3372, |
| 54712 | GIR_EraseRootFromParent_Done, |
| 54713 | // Label 2971: @176003 |
| 54714 | GIM_Reject, |
| 54715 | // Label 2949: @176004 |
| 54716 | GIM_Reject, |
| 54717 | // Label 2925: @176005 |
| 54718 | GIM_Reject, |
| 54719 | // Label 20: @176006 |
| 54720 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 2974*/ GIMT_Encode4(178517), |
| 54721 | /*GILLT_s32*//*Label 2972*/ GIMT_Encode4(176025), |
| 54722 | /*GILLT_s64*//*Label 2973*/ GIMT_Encode4(177271), |
| 54723 | // Label 2972: @176025 |
| 54724 | GIM_Try, /*On fail goto*//*Label 2975*/ GIMT_Encode4(177270), |
| 54725 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 54726 | GIM_Try, /*On fail goto*//*Label 2976*/ GIMT_Encode4(176095), // Rule ID 5268 // |
| 54727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54728 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54729 | GIM_CheckHasNoUse, /*MI*/0, |
| 54730 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54732 | // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (BUFFER_ATOMIC_SUB_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64), |
| 54734 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54741 | GIR_RootConstrainSelectedInstOperands, |
| 54742 | // GIR_Coverage, 5268, |
| 54743 | GIR_EraseRootFromParent_Done, |
| 54744 | // Label 2976: @176095 |
| 54745 | GIM_Try, /*On fail goto*//*Label 2977*/ GIMT_Encode4(176154), // Rule ID 5272 // |
| 54746 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54747 | GIM_CheckHasNoUse, /*MI*/0, |
| 54748 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54750 | // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64), |
| 54752 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54759 | GIR_RootConstrainSelectedInstOperands, |
| 54760 | // GIR_Coverage, 5272, |
| 54761 | GIR_EraseRootFromParent_Done, |
| 54762 | // Label 2977: @176154 |
| 54763 | GIM_Try, /*On fail goto*//*Label 2978*/ GIMT_Encode4(176220), // Rule ID 5266 // |
| 54764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54765 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54767 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54769 | // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>> => (BUFFER_ATOMIC_SUB_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_ADDR64_RTN), |
| 54771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54772 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54778 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54779 | GIR_RootConstrainSelectedInstOperands, |
| 54780 | // GIR_Coverage, 5266, |
| 54781 | GIR_EraseRootFromParent_Done, |
| 54782 | // Label 2978: @176220 |
| 54783 | GIM_Try, /*On fail goto*//*Label 2979*/ GIMT_Encode4(176283), // Rule ID 5270 // |
| 54784 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 54788 | // (atomic_load_sub:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>> => (BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_ADDR64_RTN), |
| 54790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54791 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 54793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 54795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 54796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54798 | GIR_RootConstrainSelectedInstOperands, |
| 54799 | // GIR_Coverage, 5270, |
| 54800 | GIR_EraseRootFromParent_Done, |
| 54801 | // Label 2979: @176283 |
| 54802 | GIM_Try, /*On fail goto*//*Label 2980*/ GIMT_Encode4(176340), // Rule ID 5267 // |
| 54803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54804 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54805 | GIM_CheckHasNoUse, /*MI*/0, |
| 54806 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54808 | // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (BUFFER_ATOMIC_SUB_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET), |
| 54810 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54815 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54816 | GIR_RootConstrainSelectedInstOperands, |
| 54817 | // GIR_Coverage, 5267, |
| 54818 | GIR_EraseRootFromParent_Done, |
| 54819 | // Label 2980: @176340 |
| 54820 | GIM_Try, /*On fail goto*//*Label 2981*/ GIMT_Encode4(176394), // Rule ID 5271 // |
| 54821 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54822 | GIM_CheckHasNoUse, /*MI*/0, |
| 54823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54825 | // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET), |
| 54827 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54832 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54833 | GIR_RootConstrainSelectedInstOperands, |
| 54834 | // GIR_Coverage, 5271, |
| 54835 | GIR_EraseRootFromParent_Done, |
| 54836 | // Label 2981: @176394 |
| 54837 | GIM_Try, /*On fail goto*//*Label 2982*/ GIMT_Encode4(176455), // Rule ID 5265 // |
| 54838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 54839 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54841 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54842 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54843 | // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>> => (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN), |
| 54845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54846 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54852 | GIR_RootConstrainSelectedInstOperands, |
| 54853 | // GIR_Coverage, 5265, |
| 54854 | GIR_EraseRootFromParent_Done, |
| 54855 | // Label 2982: @176455 |
| 54856 | GIM_Try, /*On fail goto*//*Label 2983*/ GIMT_Encode4(176513), // Rule ID 5269 // |
| 54857 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54859 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 54861 | // (atomic_load_sub:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i32>> => (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 54862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN), |
| 54863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 54864 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 54865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 54866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 54867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54869 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54870 | GIR_RootConstrainSelectedInstOperands, |
| 54871 | // GIR_Coverage, 5269, |
| 54872 | GIR_EraseRootFromParent_Done, |
| 54873 | // Label 2983: @176513 |
| 54874 | GIM_Try, /*On fail goto*//*Label 2984*/ GIMT_Encode4(176563), // Rule ID 7779 // |
| 54875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54876 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54877 | GIM_CheckHasNoUse, /*MI*/0, |
| 54878 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54879 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54880 | // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i32>> => (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32), |
| 54882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54883 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54886 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54887 | GIR_RootConstrainSelectedInstOperands, |
| 54888 | // GIR_Coverage, 7779, |
| 54889 | GIR_EraseRootFromParent_Done, |
| 54890 | // Label 2984: @176563 |
| 54891 | GIM_Try, /*On fail goto*//*Label 2985*/ GIMT_Encode4(176613), // Rule ID 7781 // |
| 54892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54893 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54894 | GIM_CheckHasNoUse, /*MI*/0, |
| 54895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54897 | // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i32>> => (DS_SUB_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32_gfx9), |
| 54899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54900 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54903 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54904 | GIR_RootConstrainSelectedInstOperands, |
| 54905 | // GIR_Coverage, 7781, |
| 54906 | GIR_EraseRootFromParent_Done, |
| 54907 | // Label 2985: @176613 |
| 54908 | GIM_Try, /*On fail goto*//*Label 2986*/ GIMT_Encode4(176663), // Rule ID 7783 // |
| 54909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54910 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54911 | GIM_CheckHasNoUse, /*MI*/0, |
| 54912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54914 | // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i32>> => (DS_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U32), |
| 54916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54917 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54921 | GIR_RootConstrainSelectedInstOperands, |
| 54922 | // GIR_Coverage, 7783, |
| 54923 | GIR_EraseRootFromParent_Done, |
| 54924 | // Label 2986: @176663 |
| 54925 | GIM_Try, /*On fail goto*//*Label 2987*/ GIMT_Encode4(176717), // Rule ID 7778 // |
| 54926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 54927 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54929 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54931 | // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i32>> => (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32), |
| 54933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54935 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54939 | GIR_RootConstrainSelectedInstOperands, |
| 54940 | // GIR_Coverage, 7778, |
| 54941 | GIR_EraseRootFromParent_Done, |
| 54942 | // Label 2987: @176717 |
| 54943 | GIM_Try, /*On fail goto*//*Label 2988*/ GIMT_Encode4(176771), // Rule ID 7780 // |
| 54944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 54945 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 54946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54947 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54949 | // (atomic_load_sub:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_local_i32>> => (DS_SUB_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 54950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32_gfx9), |
| 54951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54953 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54956 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54957 | GIR_RootConstrainSelectedInstOperands, |
| 54958 | // GIR_Coverage, 7780, |
| 54959 | GIR_EraseRootFromParent_Done, |
| 54960 | // Label 2988: @176771 |
| 54961 | GIM_Try, /*On fail goto*//*Label 2989*/ GIMT_Encode4(176825), // Rule ID 7782 // |
| 54962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 54963 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 54964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 54965 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 54967 | // (atomic_load_sub_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i32>> => (DS_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 54968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U32), |
| 54969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 54970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 54971 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 54972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 54973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 54974 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54975 | GIR_RootConstrainSelectedInstOperands, |
| 54976 | // GIR_Coverage, 7782, |
| 54977 | GIR_EraseRootFromParent_Done, |
| 54978 | // Label 2989: @176825 |
| 54979 | GIM_Try, /*On fail goto*//*Label 2990*/ GIMT_Encode4(176882), // Rule ID 3607 // |
| 54980 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54981 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 54982 | GIM_CheckHasNoUse, /*MI*/0, |
| 54983 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 54984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 54985 | // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (GLOBAL_ATOMIC_SUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 54986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR), |
| 54987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 54988 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 54989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 54990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 54991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 54992 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 54993 | GIR_RootConstrainSelectedInstOperands, |
| 54994 | // GIR_Coverage, 3607, |
| 54995 | GIR_EraseRootFromParent_Done, |
| 54996 | // Label 2990: @176882 |
| 54997 | GIM_Try, /*On fail goto*//*Label 2991*/ GIMT_Encode4(176943), // Rule ID 3609 // |
| 54998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 54999 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55001 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 55003 | // (atomic_load_sub:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>> => (GLOBAL_ATOMIC_SUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 55004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_SADDR_RTN), |
| 55005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 55007 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 55009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55011 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55012 | GIR_RootConstrainSelectedInstOperands, |
| 55013 | // GIR_Coverage, 3609, |
| 55014 | GIR_EraseRootFromParent_Done, |
| 55015 | // Label 2991: @176943 |
| 55016 | GIM_Try, /*On fail goto*//*Label 2992*/ GIMT_Encode4(176995), // Rule ID 3606 // |
| 55017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55018 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55019 | GIM_CheckHasNoUse, /*MI*/0, |
| 55020 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55021 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55022 | // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (GLOBAL_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB), |
| 55024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55025 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55029 | GIR_RootConstrainSelectedInstOperands, |
| 55030 | // GIR_Coverage, 3606, |
| 55031 | GIR_EraseRootFromParent_Done, |
| 55032 | // Label 2992: @176995 |
| 55033 | GIM_Try, /*On fail goto*//*Label 2993*/ GIMT_Encode4(177051), // Rule ID 3608 // |
| 55034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55035 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55039 | // (atomic_load_sub:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>> => (GLOBAL_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_RTN), |
| 55041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55043 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55046 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55047 | GIR_RootConstrainSelectedInstOperands, |
| 55048 | // GIR_Coverage, 3608, |
| 55049 | GIR_EraseRootFromParent_Done, |
| 55050 | // Label 2993: @177051 |
| 55051 | GIM_Try, /*On fail goto*//*Label 2994*/ GIMT_Encode4(177104), // Rule ID 3289 // |
| 55052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55053 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55054 | GIM_CheckHasNoUse, /*MI*/0, |
| 55055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55057 | // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i32>> => (FLAT_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB), |
| 55059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55060 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55064 | GIR_RootConstrainSelectedInstOperands, |
| 55065 | // GIR_Coverage, 3289, |
| 55066 | GIR_EraseRootFromParent_Done, |
| 55067 | // Label 2994: @177104 |
| 55068 | GIM_Try, /*On fail goto*//*Label 2995*/ GIMT_Encode4(177156), // Rule ID 3349 // |
| 55069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55070 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55071 | GIM_CheckHasNoUse, /*MI*/0, |
| 55072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55074 | // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i32>> => (FLAT_ATOMIC_SUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB), |
| 55076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55077 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55081 | GIR_RootConstrainSelectedInstOperands, |
| 55082 | // GIR_Coverage, 3349, |
| 55083 | GIR_EraseRootFromParent_Done, |
| 55084 | // Label 2995: @177156 |
| 55085 | GIM_Try, /*On fail goto*//*Label 2996*/ GIMT_Encode4(177213), // Rule ID 3288 // |
| 55086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55087 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55091 | // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_flat_i32>> => (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN), |
| 55093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55095 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55099 | GIR_RootConstrainSelectedInstOperands, |
| 55100 | // GIR_Coverage, 3288, |
| 55101 | GIR_EraseRootFromParent_Done, |
| 55102 | // Label 2996: @177213 |
| 55103 | GIM_Try, /*On fail goto*//*Label 2997*/ GIMT_Encode4(177269), // Rule ID 3348 // |
| 55104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55109 | // (atomic_load_sub:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_sub_global_i32>> => (FLAT_ATOMIC_SUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_RTN), |
| 55111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55113 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55117 | GIR_RootConstrainSelectedInstOperands, |
| 55118 | // GIR_Coverage, 3348, |
| 55119 | GIR_EraseRootFromParent_Done, |
| 55120 | // Label 2997: @177269 |
| 55121 | GIM_Reject, |
| 55122 | // Label 2975: @177270 |
| 55123 | GIM_Reject, |
| 55124 | // Label 2973: @177271 |
| 55125 | GIM_Try, /*On fail goto*//*Label 2998*/ GIMT_Encode4(178516), |
| 55126 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55127 | GIM_Try, /*On fail goto*//*Label 2999*/ GIMT_Encode4(177341), // Rule ID 5364 // |
| 55128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55129 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55130 | GIM_CheckHasNoUse, /*MI*/0, |
| 55131 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55132 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55133 | // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (BUFFER_ATOMIC_SUB_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64), |
| 55135 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55141 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55142 | GIR_RootConstrainSelectedInstOperands, |
| 55143 | // GIR_Coverage, 5364, |
| 55144 | GIR_EraseRootFromParent_Done, |
| 55145 | // Label 2999: @177341 |
| 55146 | GIM_Try, /*On fail goto*//*Label 3000*/ GIMT_Encode4(177400), // Rule ID 5368 // |
| 55147 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55148 | GIM_CheckHasNoUse, /*MI*/0, |
| 55149 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55150 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55151 | // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64), |
| 55153 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55159 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55160 | GIR_RootConstrainSelectedInstOperands, |
| 55161 | // GIR_Coverage, 5368, |
| 55162 | GIR_EraseRootFromParent_Done, |
| 55163 | // Label 3000: @177400 |
| 55164 | GIM_Try, /*On fail goto*//*Label 3001*/ GIMT_Encode4(177466), // Rule ID 5362 // |
| 55165 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55166 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55168 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55169 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55170 | // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>> => (BUFFER_ATOMIC_SUB_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_ADDR64_RTN), |
| 55172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55173 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55179 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55180 | GIR_RootConstrainSelectedInstOperands, |
| 55181 | // GIR_Coverage, 5362, |
| 55182 | GIR_EraseRootFromParent_Done, |
| 55183 | // Label 3001: @177466 |
| 55184 | GIM_Try, /*On fail goto*//*Label 3002*/ GIMT_Encode4(177529), // Rule ID 5366 // |
| 55185 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55187 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55188 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55189 | // (atomic_load_sub:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_ADDR64_RTN), |
| 55191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55192 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55198 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55199 | GIR_RootConstrainSelectedInstOperands, |
| 55200 | // GIR_Coverage, 5366, |
| 55201 | GIR_EraseRootFromParent_Done, |
| 55202 | // Label 3002: @177529 |
| 55203 | GIM_Try, /*On fail goto*//*Label 3003*/ GIMT_Encode4(177586), // Rule ID 5363 // |
| 55204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55205 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55206 | GIM_CheckHasNoUse, /*MI*/0, |
| 55207 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55208 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55209 | // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET), |
| 55211 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55217 | GIR_RootConstrainSelectedInstOperands, |
| 55218 | // GIR_Coverage, 5363, |
| 55219 | GIR_EraseRootFromParent_Done, |
| 55220 | // Label 3003: @177586 |
| 55221 | GIM_Try, /*On fail goto*//*Label 3004*/ GIMT_Encode4(177640), // Rule ID 5367 // |
| 55222 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55223 | GIM_CheckHasNoUse, /*MI*/0, |
| 55224 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55225 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55226 | // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET), |
| 55228 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55233 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55234 | GIR_RootConstrainSelectedInstOperands, |
| 55235 | // GIR_Coverage, 5367, |
| 55236 | GIR_EraseRootFromParent_Done, |
| 55237 | // Label 3004: @177640 |
| 55238 | GIM_Try, /*On fail goto*//*Label 3005*/ GIMT_Encode4(177701), // Rule ID 5361 // |
| 55239 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55240 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55242 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55244 | // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>> => (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN), |
| 55246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55247 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55253 | GIR_RootConstrainSelectedInstOperands, |
| 55254 | // GIR_Coverage, 5361, |
| 55255 | GIR_EraseRootFromParent_Done, |
| 55256 | // Label 3005: @177701 |
| 55257 | GIM_Try, /*On fail goto*//*Label 3006*/ GIMT_Encode4(177759), // Rule ID 5365 // |
| 55258 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55260 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55262 | // (atomic_load_sub:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_sub_global_i64>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN), |
| 55264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55265 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55270 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55271 | GIR_RootConstrainSelectedInstOperands, |
| 55272 | // GIR_Coverage, 5365, |
| 55273 | GIR_EraseRootFromParent_Done, |
| 55274 | // Label 3006: @177759 |
| 55275 | GIM_Try, /*On fail goto*//*Label 3007*/ GIMT_Encode4(177809), // Rule ID 7878 // |
| 55276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 55277 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55278 | GIM_CheckHasNoUse, /*MI*/0, |
| 55279 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55281 | // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_noret_i64>> => (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64), |
| 55283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55284 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55287 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55288 | GIR_RootConstrainSelectedInstOperands, |
| 55289 | // GIR_Coverage, 7878, |
| 55290 | GIR_EraseRootFromParent_Done, |
| 55291 | // Label 3007: @177809 |
| 55292 | GIM_Try, /*On fail goto*//*Label 3008*/ GIMT_Encode4(177859), // Rule ID 7880 // |
| 55293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 55294 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55295 | GIM_CheckHasNoUse, /*MI*/0, |
| 55296 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55297 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55298 | // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_noret_i64>> => (DS_SUB_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64_gfx9), |
| 55300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55301 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55304 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55305 | GIR_RootConstrainSelectedInstOperands, |
| 55306 | // GIR_Coverage, 7880, |
| 55307 | GIR_EraseRootFromParent_Done, |
| 55308 | // Label 3008: @177859 |
| 55309 | GIM_Try, /*On fail goto*//*Label 3009*/ GIMT_Encode4(177909), // Rule ID 7882 // |
| 55310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 55311 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 55312 | GIM_CheckHasNoUse, /*MI*/0, |
| 55313 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55315 | // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_noret_i64>> => (DS_SUB_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 55316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_U64), |
| 55317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55318 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55321 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55322 | GIR_RootConstrainSelectedInstOperands, |
| 55323 | // GIR_Coverage, 7882, |
| 55324 | GIR_EraseRootFromParent_Done, |
| 55325 | // Label 3009: @177909 |
| 55326 | GIM_Try, /*On fail goto*//*Label 3010*/ GIMT_Encode4(177963), // Rule ID 7877 // |
| 55327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 55328 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55330 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55331 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55332 | // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_m0_i64>> => (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64), |
| 55334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55336 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55339 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55340 | GIR_RootConstrainSelectedInstOperands, |
| 55341 | // GIR_Coverage, 7877, |
| 55342 | GIR_EraseRootFromParent_Done, |
| 55343 | // Label 3010: @177963 |
| 55344 | GIM_Try, /*On fail goto*//*Label 3011*/ GIMT_Encode4(178017), // Rule ID 7879 // |
| 55345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 55346 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55348 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55350 | // (atomic_load_sub:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_local_i64>> => (DS_SUB_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64_gfx9), |
| 55352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55354 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55357 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55358 | GIR_RootConstrainSelectedInstOperands, |
| 55359 | // GIR_Coverage, 7879, |
| 55360 | GIR_EraseRootFromParent_Done, |
| 55361 | // Label 3011: @178017 |
| 55362 | GIM_Try, /*On fail goto*//*Label 3012*/ GIMT_Encode4(178071), // Rule ID 7881 // |
| 55363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 55364 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 55365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55366 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55367 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55368 | // (atomic_load_sub_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_sub_region_m0_i64>> => (DS_SUB_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 55369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_RTN_U64), |
| 55370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55372 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55376 | GIR_RootConstrainSelectedInstOperands, |
| 55377 | // GIR_Coverage, 7881, |
| 55378 | GIR_EraseRootFromParent_Done, |
| 55379 | // Label 3012: @178071 |
| 55380 | GIM_Try, /*On fail goto*//*Label 3013*/ GIMT_Encode4(178128), // Rule ID 3663 // |
| 55381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55382 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55383 | GIM_CheckHasNoUse, /*MI*/0, |
| 55384 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 55386 | // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (GLOBAL_ATOMIC_SUB_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 55387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR), |
| 55388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 55389 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 55391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55394 | GIR_RootConstrainSelectedInstOperands, |
| 55395 | // GIR_Coverage, 3663, |
| 55396 | GIR_EraseRootFromParent_Done, |
| 55397 | // Label 3013: @178128 |
| 55398 | GIM_Try, /*On fail goto*//*Label 3014*/ GIMT_Encode4(178189), // Rule ID 3665 // |
| 55399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55400 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55402 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55403 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 55404 | // (atomic_load_sub:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>> => (GLOBAL_ATOMIC_SUB_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 55405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_SADDR_RTN), |
| 55406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 55408 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 55410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55412 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55413 | GIR_RootConstrainSelectedInstOperands, |
| 55414 | // GIR_Coverage, 3665, |
| 55415 | GIR_EraseRootFromParent_Done, |
| 55416 | // Label 3014: @178189 |
| 55417 | GIM_Try, /*On fail goto*//*Label 3015*/ GIMT_Encode4(178241), // Rule ID 3662 // |
| 55418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55419 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55420 | GIM_CheckHasNoUse, /*MI*/0, |
| 55421 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55423 | // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (GLOBAL_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2), |
| 55425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55426 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55429 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55430 | GIR_RootConstrainSelectedInstOperands, |
| 55431 | // GIR_Coverage, 3662, |
| 55432 | GIR_EraseRootFromParent_Done, |
| 55433 | // Label 3015: @178241 |
| 55434 | GIM_Try, /*On fail goto*//*Label 3016*/ GIMT_Encode4(178297), // Rule ID 3664 // |
| 55435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55436 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55438 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55440 | // (atomic_load_sub:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>> => (GLOBAL_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SUB_X2_RTN), |
| 55442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55444 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55448 | GIR_RootConstrainSelectedInstOperands, |
| 55449 | // GIR_Coverage, 3664, |
| 55450 | GIR_EraseRootFromParent_Done, |
| 55451 | // Label 3016: @178297 |
| 55452 | GIM_Try, /*On fail goto*//*Label 3017*/ GIMT_Encode4(178350), // Rule ID 3315 // |
| 55453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55454 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55455 | GIM_CheckHasNoUse, /*MI*/0, |
| 55456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55457 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55458 | // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_noret_i64>> => (FLAT_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2), |
| 55460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55461 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55465 | GIR_RootConstrainSelectedInstOperands, |
| 55466 | // GIR_Coverage, 3315, |
| 55467 | GIR_EraseRootFromParent_Done, |
| 55468 | // Label 3017: @178350 |
| 55469 | GIM_Try, /*On fail goto*//*Label 3018*/ GIMT_Encode4(178402), // Rule ID 3375 // |
| 55470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55471 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55472 | GIM_CheckHasNoUse, /*MI*/0, |
| 55473 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55475 | // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_noret_i64>> => (FLAT_ATOMIC_SUB_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2), |
| 55477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55478 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55482 | GIR_RootConstrainSelectedInstOperands, |
| 55483 | // GIR_Coverage, 3375, |
| 55484 | GIR_EraseRootFromParent_Done, |
| 55485 | // Label 3018: @178402 |
| 55486 | GIM_Try, /*On fail goto*//*Label 3019*/ GIMT_Encode4(178459), // Rule ID 3314 // |
| 55487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55488 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55490 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55492 | // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_flat_i64>> => (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN), |
| 55494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55496 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55499 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55500 | GIR_RootConstrainSelectedInstOperands, |
| 55501 | // GIR_Coverage, 3314, |
| 55502 | GIR_EraseRootFromParent_Done, |
| 55503 | // Label 3019: @178459 |
| 55504 | GIM_Try, /*On fail goto*//*Label 3020*/ GIMT_Encode4(178515), // Rule ID 3374 // |
| 55505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55506 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55508 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55510 | // (atomic_load_sub:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_sub_global_i64>> => (FLAT_ATOMIC_SUB_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 55511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SUB_X2_RTN), |
| 55512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55514 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55517 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55518 | GIR_RootConstrainSelectedInstOperands, |
| 55519 | // GIR_Coverage, 3374, |
| 55520 | GIR_EraseRootFromParent_Done, |
| 55521 | // Label 3020: @178515 |
| 55522 | GIM_Reject, |
| 55523 | // Label 2998: @178516 |
| 55524 | GIM_Reject, |
| 55525 | // Label 2974: @178517 |
| 55526 | GIM_Reject, |
| 55527 | // Label 21: @178518 |
| 55528 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3023*/ GIMT_Encode4(181029), |
| 55529 | /*GILLT_s32*//*Label 3021*/ GIMT_Encode4(178537), |
| 55530 | /*GILLT_s64*//*Label 3022*/ GIMT_Encode4(179783), |
| 55531 | // Label 3021: @178537 |
| 55532 | GIM_Try, /*On fail goto*//*Label 3024*/ GIMT_Encode4(179782), |
| 55533 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 55534 | GIM_Try, /*On fail goto*//*Label 3025*/ GIMT_Encode4(178607), // Rule ID 5308 // |
| 55535 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55536 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55537 | GIM_CheckHasNoUse, /*MI*/0, |
| 55538 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55540 | // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>> => (BUFFER_ATOMIC_AND_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64), |
| 55542 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55549 | GIR_RootConstrainSelectedInstOperands, |
| 55550 | // GIR_Coverage, 5308, |
| 55551 | GIR_EraseRootFromParent_Done, |
| 55552 | // Label 3025: @178607 |
| 55553 | GIM_Try, /*On fail goto*//*Label 3026*/ GIMT_Encode4(178666), // Rule ID 5312 // |
| 55554 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55555 | GIM_CheckHasNoUse, /*MI*/0, |
| 55556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55557 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55558 | // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>> => (BUFFER_ATOMIC_AND_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64), |
| 55560 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55566 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55567 | GIR_RootConstrainSelectedInstOperands, |
| 55568 | // GIR_Coverage, 5312, |
| 55569 | GIR_EraseRootFromParent_Done, |
| 55570 | // Label 3026: @178666 |
| 55571 | GIM_Try, /*On fail goto*//*Label 3027*/ GIMT_Encode4(178732), // Rule ID 5306 // |
| 55572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55573 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55574 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55575 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55576 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55577 | // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>> => (BUFFER_ATOMIC_AND_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_ADDR64_RTN), |
| 55579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55580 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55587 | GIR_RootConstrainSelectedInstOperands, |
| 55588 | // GIR_Coverage, 5306, |
| 55589 | GIR_EraseRootFromParent_Done, |
| 55590 | // Label 3027: @178732 |
| 55591 | GIM_Try, /*On fail goto*//*Label 3028*/ GIMT_Encode4(178795), // Rule ID 5310 // |
| 55592 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55596 | // (atomic_load_and:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>> => (BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_ADDR64_RTN), |
| 55598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55599 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55605 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55606 | GIR_RootConstrainSelectedInstOperands, |
| 55607 | // GIR_Coverage, 5310, |
| 55608 | GIR_EraseRootFromParent_Done, |
| 55609 | // Label 3028: @178795 |
| 55610 | GIM_Try, /*On fail goto*//*Label 3029*/ GIMT_Encode4(178852), // Rule ID 5307 // |
| 55611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55612 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55613 | GIM_CheckHasNoUse, /*MI*/0, |
| 55614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55616 | // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>> => (BUFFER_ATOMIC_AND_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET), |
| 55618 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55623 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55624 | GIR_RootConstrainSelectedInstOperands, |
| 55625 | // GIR_Coverage, 5307, |
| 55626 | GIR_EraseRootFromParent_Done, |
| 55627 | // Label 3029: @178852 |
| 55628 | GIM_Try, /*On fail goto*//*Label 3030*/ GIMT_Encode4(178906), // Rule ID 5311 // |
| 55629 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55630 | GIM_CheckHasNoUse, /*MI*/0, |
| 55631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55633 | // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i32>> => (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET), |
| 55635 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55641 | GIR_RootConstrainSelectedInstOperands, |
| 55642 | // GIR_Coverage, 5311, |
| 55643 | GIR_EraseRootFromParent_Done, |
| 55644 | // Label 3030: @178906 |
| 55645 | GIM_Try, /*On fail goto*//*Label 3031*/ GIMT_Encode4(178967), // Rule ID 5305 // |
| 55646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55647 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55649 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55651 | // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>> => (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN), |
| 55653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55654 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55659 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55660 | GIR_RootConstrainSelectedInstOperands, |
| 55661 | // GIR_Coverage, 5305, |
| 55662 | GIR_EraseRootFromParent_Done, |
| 55663 | // Label 3031: @178967 |
| 55664 | GIM_Try, /*On fail goto*//*Label 3032*/ GIMT_Encode4(179025), // Rule ID 5309 // |
| 55665 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55667 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 55669 | // (atomic_load_and:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i32>> => (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN), |
| 55671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55672 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 55675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55677 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55678 | GIR_RootConstrainSelectedInstOperands, |
| 55679 | // GIR_Coverage, 5309, |
| 55680 | GIR_EraseRootFromParent_Done, |
| 55681 | // Label 3032: @179025 |
| 55682 | GIM_Try, /*On fail goto*//*Label 3033*/ GIMT_Encode4(179075), // Rule ID 7797 // |
| 55683 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 55684 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55685 | GIM_CheckHasNoUse, /*MI*/0, |
| 55686 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55688 | // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i32>> => (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32), |
| 55690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55691 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55695 | GIR_RootConstrainSelectedInstOperands, |
| 55696 | // GIR_Coverage, 7797, |
| 55697 | GIR_EraseRootFromParent_Done, |
| 55698 | // Label 3033: @179075 |
| 55699 | GIM_Try, /*On fail goto*//*Label 3034*/ GIMT_Encode4(179125), // Rule ID 7799 // |
| 55700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 55701 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55702 | GIM_CheckHasNoUse, /*MI*/0, |
| 55703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55705 | // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_noret_i32>> => (DS_AND_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32_gfx9), |
| 55707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55708 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55712 | GIR_RootConstrainSelectedInstOperands, |
| 55713 | // GIR_Coverage, 7799, |
| 55714 | GIR_EraseRootFromParent_Done, |
| 55715 | // Label 3034: @179125 |
| 55716 | GIM_Try, /*On fail goto*//*Label 3035*/ GIMT_Encode4(179175), // Rule ID 7801 // |
| 55717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 55718 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 55719 | GIM_CheckHasNoUse, /*MI*/0, |
| 55720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55721 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55722 | // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i32>> => (DS_AND_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 55723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B32), |
| 55724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55725 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55729 | GIR_RootConstrainSelectedInstOperands, |
| 55730 | // GIR_Coverage, 7801, |
| 55731 | GIR_EraseRootFromParent_Done, |
| 55732 | // Label 3035: @179175 |
| 55733 | GIM_Try, /*On fail goto*//*Label 3036*/ GIMT_Encode4(179229), // Rule ID 7796 // |
| 55734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 55735 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55737 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55739 | // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_m0_i32>> => (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32), |
| 55741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55743 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55746 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55747 | GIR_RootConstrainSelectedInstOperands, |
| 55748 | // GIR_Coverage, 7796, |
| 55749 | GIR_EraseRootFromParent_Done, |
| 55750 | // Label 3036: @179229 |
| 55751 | GIM_Try, /*On fail goto*//*Label 3037*/ GIMT_Encode4(179283), // Rule ID 7798 // |
| 55752 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 55753 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 55754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55755 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55756 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55757 | // (atomic_load_and:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_local_i32>> => (DS_AND_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 55758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32_gfx9), |
| 55759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55761 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55765 | GIR_RootConstrainSelectedInstOperands, |
| 55766 | // GIR_Coverage, 7798, |
| 55767 | GIR_EraseRootFromParent_Done, |
| 55768 | // Label 3037: @179283 |
| 55769 | GIM_Try, /*On fail goto*//*Label 3038*/ GIMT_Encode4(179337), // Rule ID 7800 // |
| 55770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 55771 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 55772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 55775 | // (atomic_load_and_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_and_region_m0_i32>> => (DS_AND_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 55776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B32), |
| 55777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 55779 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 55780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55783 | GIR_RootConstrainSelectedInstOperands, |
| 55784 | // GIR_Coverage, 7800, |
| 55785 | GIR_EraseRootFromParent_Done, |
| 55786 | // Label 3038: @179337 |
| 55787 | GIM_Try, /*On fail goto*//*Label 3039*/ GIMT_Encode4(179394), // Rule ID 3619 // |
| 55788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55790 | GIM_CheckHasNoUse, /*MI*/0, |
| 55791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 55793 | // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>> => (GLOBAL_ATOMIC_AND_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 55794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR), |
| 55795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 55796 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 55798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55801 | GIR_RootConstrainSelectedInstOperands, |
| 55802 | // GIR_Coverage, 3619, |
| 55803 | GIR_EraseRootFromParent_Done, |
| 55804 | // Label 3039: @179394 |
| 55805 | GIM_Try, /*On fail goto*//*Label 3040*/ GIMT_Encode4(179455), // Rule ID 3621 // |
| 55806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55807 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55809 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 55811 | // (atomic_load_and:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>> => (GLOBAL_ATOMIC_AND_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 55812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_SADDR_RTN), |
| 55813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 55815 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 55817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 55818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55820 | GIR_RootConstrainSelectedInstOperands, |
| 55821 | // GIR_Coverage, 3621, |
| 55822 | GIR_EraseRootFromParent_Done, |
| 55823 | // Label 3040: @179455 |
| 55824 | GIM_Try, /*On fail goto*//*Label 3041*/ GIMT_Encode4(179507), // Rule ID 3618 // |
| 55825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55826 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55827 | GIM_CheckHasNoUse, /*MI*/0, |
| 55828 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55829 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55830 | // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>> => (GLOBAL_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND), |
| 55832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55833 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55837 | GIR_RootConstrainSelectedInstOperands, |
| 55838 | // GIR_Coverage, 3618, |
| 55839 | GIR_EraseRootFromParent_Done, |
| 55840 | // Label 3041: @179507 |
| 55841 | GIM_Try, /*On fail goto*//*Label 3042*/ GIMT_Encode4(179563), // Rule ID 3620 // |
| 55842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 55843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 55847 | // (atomic_load_and:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>> => (GLOBAL_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_RTN), |
| 55849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55851 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55855 | GIR_RootConstrainSelectedInstOperands, |
| 55856 | // GIR_Coverage, 3620, |
| 55857 | GIR_EraseRootFromParent_Done, |
| 55858 | // Label 3042: @179563 |
| 55859 | GIM_Try, /*On fail goto*//*Label 3043*/ GIMT_Encode4(179616), // Rule ID 3295 // |
| 55860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55861 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55862 | GIM_CheckHasNoUse, /*MI*/0, |
| 55863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55865 | // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i32>> => (FLAT_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND), |
| 55867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55868 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55871 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55872 | GIR_RootConstrainSelectedInstOperands, |
| 55873 | // GIR_Coverage, 3295, |
| 55874 | GIR_EraseRootFromParent_Done, |
| 55875 | // Label 3043: @179616 |
| 55876 | GIM_Try, /*On fail goto*//*Label 3044*/ GIMT_Encode4(179668), // Rule ID 3355 // |
| 55877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55878 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55879 | GIM_CheckHasNoUse, /*MI*/0, |
| 55880 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55882 | // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_noret_i32>> => (FLAT_ATOMIC_AND VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND), |
| 55884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55885 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55889 | GIR_RootConstrainSelectedInstOperands, |
| 55890 | // GIR_Coverage, 3355, |
| 55891 | GIR_EraseRootFromParent_Done, |
| 55892 | // Label 3044: @179668 |
| 55893 | GIM_Try, /*On fail goto*//*Label 3045*/ GIMT_Encode4(179725), // Rule ID 3294 // |
| 55894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55895 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55896 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55899 | // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_flat_i32>> => (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN), |
| 55901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55903 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55907 | GIR_RootConstrainSelectedInstOperands, |
| 55908 | // GIR_Coverage, 3294, |
| 55909 | GIR_EraseRootFromParent_Done, |
| 55910 | // Label 3045: @179725 |
| 55911 | GIM_Try, /*On fail goto*//*Label 3046*/ GIMT_Encode4(179781), // Rule ID 3354 // |
| 55912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 55913 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 55915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55916 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 55917 | // (atomic_load_and:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_and_global_i32>> => (FLAT_ATOMIC_AND_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 55918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_RTN), |
| 55919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 55920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 55921 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 55922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 55923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55924 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55925 | GIR_RootConstrainSelectedInstOperands, |
| 55926 | // GIR_Coverage, 3354, |
| 55927 | GIR_EraseRootFromParent_Done, |
| 55928 | // Label 3046: @179781 |
| 55929 | GIM_Reject, |
| 55930 | // Label 3024: @179782 |
| 55931 | GIM_Reject, |
| 55932 | // Label 3022: @179783 |
| 55933 | GIM_Try, /*On fail goto*//*Label 3047*/ GIMT_Encode4(181028), |
| 55934 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 55935 | GIM_Try, /*On fail goto*//*Label 3048*/ GIMT_Encode4(179853), // Rule ID 5404 // |
| 55936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55937 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55938 | GIM_CheckHasNoUse, /*MI*/0, |
| 55939 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55941 | // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>> => (BUFFER_ATOMIC_AND_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64), |
| 55943 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55950 | GIR_RootConstrainSelectedInstOperands, |
| 55951 | // GIR_Coverage, 5404, |
| 55952 | GIR_EraseRootFromParent_Done, |
| 55953 | // Label 3048: @179853 |
| 55954 | GIM_Try, /*On fail goto*//*Label 3049*/ GIMT_Encode4(179912), // Rule ID 5408 // |
| 55955 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55956 | GIM_CheckHasNoUse, /*MI*/0, |
| 55957 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55958 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55959 | // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64), |
| 55961 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 55967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55968 | GIR_RootConstrainSelectedInstOperands, |
| 55969 | // GIR_Coverage, 5408, |
| 55970 | GIR_EraseRootFromParent_Done, |
| 55971 | // Label 3049: @179912 |
| 55972 | GIM_Try, /*On fail goto*//*Label 3050*/ GIMT_Encode4(179978), // Rule ID 5402 // |
| 55973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 55974 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55976 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55977 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55978 | // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>> => (BUFFER_ATOMIC_AND_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_ADDR64_RTN), |
| 55980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 55981 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 55982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 55983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 55984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 55985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 55986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 55987 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 55988 | GIR_RootConstrainSelectedInstOperands, |
| 55989 | // GIR_Coverage, 5402, |
| 55990 | GIR_EraseRootFromParent_Done, |
| 55991 | // Label 3050: @179978 |
| 55992 | GIM_Try, /*On fail goto*//*Label 3051*/ GIMT_Encode4(180041), // Rule ID 5406 // |
| 55993 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 55994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 55995 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 55996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 55997 | // (atomic_load_and:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 55998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_ADDR64_RTN), |
| 55999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56000 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56006 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56007 | GIR_RootConstrainSelectedInstOperands, |
| 56008 | // GIR_Coverage, 5406, |
| 56009 | GIR_EraseRootFromParent_Done, |
| 56010 | // Label 3051: @180041 |
| 56011 | GIM_Try, /*On fail goto*//*Label 3052*/ GIMT_Encode4(180098), // Rule ID 5403 // |
| 56012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56013 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56014 | GIM_CheckHasNoUse, /*MI*/0, |
| 56015 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56016 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56017 | // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>> => (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET), |
| 56019 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56024 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56025 | GIR_RootConstrainSelectedInstOperands, |
| 56026 | // GIR_Coverage, 5403, |
| 56027 | GIR_EraseRootFromParent_Done, |
| 56028 | // Label 3052: @180098 |
| 56029 | GIM_Try, /*On fail goto*//*Label 3053*/ GIMT_Encode4(180152), // Rule ID 5407 // |
| 56030 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56031 | GIM_CheckHasNoUse, /*MI*/0, |
| 56032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56034 | // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_noret_i64>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET), |
| 56036 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56041 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56042 | GIR_RootConstrainSelectedInstOperands, |
| 56043 | // GIR_Coverage, 5407, |
| 56044 | GIR_EraseRootFromParent_Done, |
| 56045 | // Label 3053: @180152 |
| 56046 | GIM_Try, /*On fail goto*//*Label 3054*/ GIMT_Encode4(180213), // Rule ID 5401 // |
| 56047 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56048 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56052 | // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>> => (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN), |
| 56054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56055 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56060 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56061 | GIR_RootConstrainSelectedInstOperands, |
| 56062 | // GIR_Coverage, 5401, |
| 56063 | GIR_EraseRootFromParent_Done, |
| 56064 | // Label 3054: @180213 |
| 56065 | GIM_Try, /*On fail goto*//*Label 3055*/ GIMT_Encode4(180271), // Rule ID 5405 // |
| 56066 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56068 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56070 | // (atomic_load_and:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_and_global_i64>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN), |
| 56072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56073 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56079 | GIR_RootConstrainSelectedInstOperands, |
| 56080 | // GIR_Coverage, 5405, |
| 56081 | GIR_EraseRootFromParent_Done, |
| 56082 | // Label 3055: @180271 |
| 56083 | GIM_Try, /*On fail goto*//*Label 3056*/ GIMT_Encode4(180321), // Rule ID 7896 // |
| 56084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56085 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56086 | GIM_CheckHasNoUse, /*MI*/0, |
| 56087 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56088 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56089 | // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_noret_i64>> => (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64), |
| 56091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56092 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56095 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56096 | GIR_RootConstrainSelectedInstOperands, |
| 56097 | // GIR_Coverage, 7896, |
| 56098 | GIR_EraseRootFromParent_Done, |
| 56099 | // Label 3056: @180321 |
| 56100 | GIM_Try, /*On fail goto*//*Label 3057*/ GIMT_Encode4(180371), // Rule ID 7898 // |
| 56101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56102 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56103 | GIM_CheckHasNoUse, /*MI*/0, |
| 56104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56106 | // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_noret_i64>> => (DS_AND_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64_gfx9), |
| 56108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56109 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56113 | GIR_RootConstrainSelectedInstOperands, |
| 56114 | // GIR_Coverage, 7898, |
| 56115 | GIR_EraseRootFromParent_Done, |
| 56116 | // Label 3057: @180371 |
| 56117 | GIM_Try, /*On fail goto*//*Label 3058*/ GIMT_Encode4(180421), // Rule ID 7900 // |
| 56118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56119 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56120 | GIM_CheckHasNoUse, /*MI*/0, |
| 56121 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56122 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56123 | // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_noret_i64>> => (DS_AND_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_B64), |
| 56125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56126 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56129 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56130 | GIR_RootConstrainSelectedInstOperands, |
| 56131 | // GIR_Coverage, 7900, |
| 56132 | GIR_EraseRootFromParent_Done, |
| 56133 | // Label 3058: @180421 |
| 56134 | GIM_Try, /*On fail goto*//*Label 3059*/ GIMT_Encode4(180475), // Rule ID 7895 // |
| 56135 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56136 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56138 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56139 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56140 | // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_m0_i64>> => (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64), |
| 56142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56144 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56148 | GIR_RootConstrainSelectedInstOperands, |
| 56149 | // GIR_Coverage, 7895, |
| 56150 | GIR_EraseRootFromParent_Done, |
| 56151 | // Label 3059: @180475 |
| 56152 | GIM_Try, /*On fail goto*//*Label 3060*/ GIMT_Encode4(180529), // Rule ID 7897 // |
| 56153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56154 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56156 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56158 | // (atomic_load_and:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_local_i64>> => (DS_AND_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64_gfx9), |
| 56160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56162 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56166 | GIR_RootConstrainSelectedInstOperands, |
| 56167 | // GIR_Coverage, 7897, |
| 56168 | GIR_EraseRootFromParent_Done, |
| 56169 | // Label 3060: @180529 |
| 56170 | GIM_Try, /*On fail goto*//*Label 3061*/ GIMT_Encode4(180583), // Rule ID 7899 // |
| 56171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56172 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56176 | // (atomic_load_and_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_and_region_m0_i64>> => (DS_AND_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_AND_RTN_B64), |
| 56178 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56180 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56184 | GIR_RootConstrainSelectedInstOperands, |
| 56185 | // GIR_Coverage, 7899, |
| 56186 | GIR_EraseRootFromParent_Done, |
| 56187 | // Label 3061: @180583 |
| 56188 | GIM_Try, /*On fail goto*//*Label 3062*/ GIMT_Encode4(180640), // Rule ID 3675 // |
| 56189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56190 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56191 | GIM_CheckHasNoUse, /*MI*/0, |
| 56192 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56193 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 56194 | // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>> => (GLOBAL_ATOMIC_AND_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 56195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR), |
| 56196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 56197 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 56199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56201 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56202 | GIR_RootConstrainSelectedInstOperands, |
| 56203 | // GIR_Coverage, 3675, |
| 56204 | GIR_EraseRootFromParent_Done, |
| 56205 | // Label 3062: @180640 |
| 56206 | GIM_Try, /*On fail goto*//*Label 3063*/ GIMT_Encode4(180701), // Rule ID 3677 // |
| 56207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56208 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 56212 | // (atomic_load_and:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>> => (GLOBAL_ATOMIC_AND_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 56213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_SADDR_RTN), |
| 56214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 56216 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 56218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56221 | GIR_RootConstrainSelectedInstOperands, |
| 56222 | // GIR_Coverage, 3677, |
| 56223 | GIR_EraseRootFromParent_Done, |
| 56224 | // Label 3063: @180701 |
| 56225 | GIM_Try, /*On fail goto*//*Label 3064*/ GIMT_Encode4(180753), // Rule ID 3674 // |
| 56226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56227 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56228 | GIM_CheckHasNoUse, /*MI*/0, |
| 56229 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56230 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 56231 | // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>> => (GLOBAL_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2), |
| 56233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56234 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56237 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56238 | GIR_RootConstrainSelectedInstOperands, |
| 56239 | // GIR_Coverage, 3674, |
| 56240 | GIR_EraseRootFromParent_Done, |
| 56241 | // Label 3064: @180753 |
| 56242 | GIM_Try, /*On fail goto*//*Label 3065*/ GIMT_Encode4(180809), // Rule ID 3676 // |
| 56243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56244 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56246 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 56248 | // (atomic_load_and:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>> => (GLOBAL_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_AND_X2_RTN), |
| 56250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56252 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56255 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56256 | GIR_RootConstrainSelectedInstOperands, |
| 56257 | // GIR_Coverage, 3676, |
| 56258 | GIR_EraseRootFromParent_Done, |
| 56259 | // Label 3065: @180809 |
| 56260 | GIM_Try, /*On fail goto*//*Label 3066*/ GIMT_Encode4(180862), // Rule ID 3321 // |
| 56261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56263 | GIM_CheckHasNoUse, /*MI*/0, |
| 56264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56266 | // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_noret_i64>> => (FLAT_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2), |
| 56268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56269 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56273 | GIR_RootConstrainSelectedInstOperands, |
| 56274 | // GIR_Coverage, 3321, |
| 56275 | GIR_EraseRootFromParent_Done, |
| 56276 | // Label 3066: @180862 |
| 56277 | GIM_Try, /*On fail goto*//*Label 3067*/ GIMT_Encode4(180914), // Rule ID 3381 // |
| 56278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56279 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56280 | GIM_CheckHasNoUse, /*MI*/0, |
| 56281 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56283 | // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_noret_i64>> => (FLAT_ATOMIC_AND_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2), |
| 56285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56286 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56290 | GIR_RootConstrainSelectedInstOperands, |
| 56291 | // GIR_Coverage, 3381, |
| 56292 | GIR_EraseRootFromParent_Done, |
| 56293 | // Label 3067: @180914 |
| 56294 | GIM_Try, /*On fail goto*//*Label 3068*/ GIMT_Encode4(180971), // Rule ID 3320 // |
| 56295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56296 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56298 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56300 | // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_flat_i64>> => (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN), |
| 56302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56304 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56308 | GIR_RootConstrainSelectedInstOperands, |
| 56309 | // GIR_Coverage, 3320, |
| 56310 | GIR_EraseRootFromParent_Done, |
| 56311 | // Label 3068: @180971 |
| 56312 | GIM_Try, /*On fail goto*//*Label 3069*/ GIMT_Encode4(181027), // Rule ID 3380 // |
| 56313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56314 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56315 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56316 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56318 | // (atomic_load_and:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_and_global_i64>> => (FLAT_ATOMIC_AND_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 56319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_AND_X2_RTN), |
| 56320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56322 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56325 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56326 | GIR_RootConstrainSelectedInstOperands, |
| 56327 | // GIR_Coverage, 3380, |
| 56328 | GIR_EraseRootFromParent_Done, |
| 56329 | // Label 3069: @181027 |
| 56330 | GIM_Reject, |
| 56331 | // Label 3047: @181028 |
| 56332 | GIM_Reject, |
| 56333 | // Label 3023: @181029 |
| 56334 | GIM_Reject, |
| 56335 | // Label 22: @181030 |
| 56336 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3072*/ GIMT_Encode4(183541), |
| 56337 | /*GILLT_s32*//*Label 3070*/ GIMT_Encode4(181049), |
| 56338 | /*GILLT_s64*//*Label 3071*/ GIMT_Encode4(182295), |
| 56339 | // Label 3070: @181049 |
| 56340 | GIM_Try, /*On fail goto*//*Label 3073*/ GIMT_Encode4(182294), |
| 56341 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 56342 | GIM_Try, /*On fail goto*//*Label 3074*/ GIMT_Encode4(181119), // Rule ID 5316 // |
| 56343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56344 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56345 | GIM_CheckHasNoUse, /*MI*/0, |
| 56346 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56347 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56348 | // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>> => (BUFFER_ATOMIC_OR_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56349 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64), |
| 56350 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56356 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56357 | GIR_RootConstrainSelectedInstOperands, |
| 56358 | // GIR_Coverage, 5316, |
| 56359 | GIR_EraseRootFromParent_Done, |
| 56360 | // Label 3074: @181119 |
| 56361 | GIM_Try, /*On fail goto*//*Label 3075*/ GIMT_Encode4(181178), // Rule ID 5320 // |
| 56362 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56363 | GIM_CheckHasNoUse, /*MI*/0, |
| 56364 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56366 | // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>> => (BUFFER_ATOMIC_OR_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64), |
| 56368 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56374 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56375 | GIR_RootConstrainSelectedInstOperands, |
| 56376 | // GIR_Coverage, 5320, |
| 56377 | GIR_EraseRootFromParent_Done, |
| 56378 | // Label 3075: @181178 |
| 56379 | GIM_Try, /*On fail goto*//*Label 3076*/ GIMT_Encode4(181244), // Rule ID 5314 // |
| 56380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56381 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56383 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56385 | // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>> => (BUFFER_ATOMIC_OR_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_ADDR64_RTN), |
| 56387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56388 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56395 | GIR_RootConstrainSelectedInstOperands, |
| 56396 | // GIR_Coverage, 5314, |
| 56397 | GIR_EraseRootFromParent_Done, |
| 56398 | // Label 3076: @181244 |
| 56399 | GIM_Try, /*On fail goto*//*Label 3077*/ GIMT_Encode4(181307), // Rule ID 5318 // |
| 56400 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56401 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56402 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56403 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56404 | // (atomic_load_or:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>> => (BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_ADDR64_RTN), |
| 56406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56407 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56414 | GIR_RootConstrainSelectedInstOperands, |
| 56415 | // GIR_Coverage, 5318, |
| 56416 | GIR_EraseRootFromParent_Done, |
| 56417 | // Label 3077: @181307 |
| 56418 | GIM_Try, /*On fail goto*//*Label 3078*/ GIMT_Encode4(181364), // Rule ID 5315 // |
| 56419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56420 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56421 | GIM_CheckHasNoUse, /*MI*/0, |
| 56422 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56424 | // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>> => (BUFFER_ATOMIC_OR_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET), |
| 56426 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56431 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56432 | GIR_RootConstrainSelectedInstOperands, |
| 56433 | // GIR_Coverage, 5315, |
| 56434 | GIR_EraseRootFromParent_Done, |
| 56435 | // Label 3078: @181364 |
| 56436 | GIM_Try, /*On fail goto*//*Label 3079*/ GIMT_Encode4(181418), // Rule ID 5319 // |
| 56437 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56438 | GIM_CheckHasNoUse, /*MI*/0, |
| 56439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56441 | // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i32>> => (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET), |
| 56443 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56449 | GIR_RootConstrainSelectedInstOperands, |
| 56450 | // GIR_Coverage, 5319, |
| 56451 | GIR_EraseRootFromParent_Done, |
| 56452 | // Label 3079: @181418 |
| 56453 | GIM_Try, /*On fail goto*//*Label 3080*/ GIMT_Encode4(181479), // Rule ID 5313 // |
| 56454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56455 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56459 | // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>> => (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN), |
| 56461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56462 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56467 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56468 | GIR_RootConstrainSelectedInstOperands, |
| 56469 | // GIR_Coverage, 5313, |
| 56470 | GIR_EraseRootFromParent_Done, |
| 56471 | // Label 3080: @181479 |
| 56472 | GIM_Try, /*On fail goto*//*Label 3081*/ GIMT_Encode4(181537), // Rule ID 5317 // |
| 56473 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56477 | // (atomic_load_or:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i32>> => (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN), |
| 56479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56480 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56486 | GIR_RootConstrainSelectedInstOperands, |
| 56487 | // GIR_Coverage, 5317, |
| 56488 | GIR_EraseRootFromParent_Done, |
| 56489 | // Label 3081: @181537 |
| 56490 | GIM_Try, /*On fail goto*//*Label 3082*/ GIMT_Encode4(181587), // Rule ID 7803 // |
| 56491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56492 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56493 | GIM_CheckHasNoUse, /*MI*/0, |
| 56494 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56495 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56496 | // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i32>> => (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32), |
| 56498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56499 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56502 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56503 | GIR_RootConstrainSelectedInstOperands, |
| 56504 | // GIR_Coverage, 7803, |
| 56505 | GIR_EraseRootFromParent_Done, |
| 56506 | // Label 3082: @181587 |
| 56507 | GIM_Try, /*On fail goto*//*Label 3083*/ GIMT_Encode4(181637), // Rule ID 7805 // |
| 56508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56509 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56510 | GIM_CheckHasNoUse, /*MI*/0, |
| 56511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56513 | // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_noret_i32>> => (DS_OR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32_gfx9), |
| 56515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56516 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56519 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56520 | GIR_RootConstrainSelectedInstOperands, |
| 56521 | // GIR_Coverage, 7805, |
| 56522 | GIR_EraseRootFromParent_Done, |
| 56523 | // Label 3083: @181637 |
| 56524 | GIM_Try, /*On fail goto*//*Label 3084*/ GIMT_Encode4(181687), // Rule ID 7807 // |
| 56525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56526 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56527 | GIM_CheckHasNoUse, /*MI*/0, |
| 56528 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56529 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56530 | // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i32>> => (DS_OR_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B32), |
| 56532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56533 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56536 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56537 | GIR_RootConstrainSelectedInstOperands, |
| 56538 | // GIR_Coverage, 7807, |
| 56539 | GIR_EraseRootFromParent_Done, |
| 56540 | // Label 3084: @181687 |
| 56541 | GIM_Try, /*On fail goto*//*Label 3085*/ GIMT_Encode4(181741), // Rule ID 7802 // |
| 56542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56543 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56545 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56547 | // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_m0_i32>> => (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32), |
| 56549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56551 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56553 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56555 | GIR_RootConstrainSelectedInstOperands, |
| 56556 | // GIR_Coverage, 7802, |
| 56557 | GIR_EraseRootFromParent_Done, |
| 56558 | // Label 3085: @181741 |
| 56559 | GIM_Try, /*On fail goto*//*Label 3086*/ GIMT_Encode4(181795), // Rule ID 7804 // |
| 56560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56561 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56563 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56564 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56565 | // (atomic_load_or:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_local_i32>> => (DS_OR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32_gfx9), |
| 56567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56569 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56573 | GIR_RootConstrainSelectedInstOperands, |
| 56574 | // GIR_Coverage, 7804, |
| 56575 | GIR_EraseRootFromParent_Done, |
| 56576 | // Label 3086: @181795 |
| 56577 | GIM_Try, /*On fail goto*//*Label 3087*/ GIMT_Encode4(181849), // Rule ID 7806 // |
| 56578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56579 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56581 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56583 | // (atomic_load_or_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_or_region_m0_i32>> => (DS_OR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B32), |
| 56585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56587 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56590 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56591 | GIR_RootConstrainSelectedInstOperands, |
| 56592 | // GIR_Coverage, 7806, |
| 56593 | GIR_EraseRootFromParent_Done, |
| 56594 | // Label 3087: @181849 |
| 56595 | GIM_Try, /*On fail goto*//*Label 3088*/ GIMT_Encode4(181906), // Rule ID 3639 // |
| 56596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56597 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56598 | GIM_CheckHasNoUse, /*MI*/0, |
| 56599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 56601 | // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>> => (GLOBAL_ATOMIC_OR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 56602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR), |
| 56603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 56604 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 56606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56609 | GIR_RootConstrainSelectedInstOperands, |
| 56610 | // GIR_Coverage, 3639, |
| 56611 | GIR_EraseRootFromParent_Done, |
| 56612 | // Label 3088: @181906 |
| 56613 | GIM_Try, /*On fail goto*//*Label 3089*/ GIMT_Encode4(181967), // Rule ID 3641 // |
| 56614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56615 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 56619 | // (atomic_load_or:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>> => (GLOBAL_ATOMIC_OR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 56620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_SADDR_RTN), |
| 56621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 56623 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 56625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56628 | GIR_RootConstrainSelectedInstOperands, |
| 56629 | // GIR_Coverage, 3641, |
| 56630 | GIR_EraseRootFromParent_Done, |
| 56631 | // Label 3089: @181967 |
| 56632 | GIM_Try, /*On fail goto*//*Label 3090*/ GIMT_Encode4(182019), // Rule ID 3638 // |
| 56633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56634 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56635 | GIM_CheckHasNoUse, /*MI*/0, |
| 56636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 56638 | // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>> => (GLOBAL_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR), |
| 56640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56641 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56645 | GIR_RootConstrainSelectedInstOperands, |
| 56646 | // GIR_Coverage, 3638, |
| 56647 | GIR_EraseRootFromParent_Done, |
| 56648 | // Label 3090: @182019 |
| 56649 | GIM_Try, /*On fail goto*//*Label 3091*/ GIMT_Encode4(182075), // Rule ID 3640 // |
| 56650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56651 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56654 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 56655 | // (atomic_load_or:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>> => (GLOBAL_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_RTN), |
| 56657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56659 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56662 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56663 | GIR_RootConstrainSelectedInstOperands, |
| 56664 | // GIR_Coverage, 3640, |
| 56665 | GIR_EraseRootFromParent_Done, |
| 56666 | // Label 3091: @182075 |
| 56667 | GIM_Try, /*On fail goto*//*Label 3092*/ GIMT_Encode4(182128), // Rule ID 3305 // |
| 56668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56669 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56670 | GIM_CheckHasNoUse, /*MI*/0, |
| 56671 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56673 | // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i32>> => (FLAT_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR), |
| 56675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56676 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56679 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56680 | GIR_RootConstrainSelectedInstOperands, |
| 56681 | // GIR_Coverage, 3305, |
| 56682 | GIR_EraseRootFromParent_Done, |
| 56683 | // Label 3092: @182128 |
| 56684 | GIM_Try, /*On fail goto*//*Label 3093*/ GIMT_Encode4(182180), // Rule ID 3365 // |
| 56685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56686 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56687 | GIM_CheckHasNoUse, /*MI*/0, |
| 56688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56690 | // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_noret_i32>> => (FLAT_ATOMIC_OR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR), |
| 56692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56693 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56696 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56697 | GIR_RootConstrainSelectedInstOperands, |
| 56698 | // GIR_Coverage, 3365, |
| 56699 | GIR_EraseRootFromParent_Done, |
| 56700 | // Label 3093: @182180 |
| 56701 | GIM_Try, /*On fail goto*//*Label 3094*/ GIMT_Encode4(182237), // Rule ID 3304 // |
| 56702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56703 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56705 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56706 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56707 | // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_flat_i32>> => (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN), |
| 56709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56711 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56714 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56715 | GIR_RootConstrainSelectedInstOperands, |
| 56716 | // GIR_Coverage, 3304, |
| 56717 | GIR_EraseRootFromParent_Done, |
| 56718 | // Label 3094: @182237 |
| 56719 | GIM_Try, /*On fail goto*//*Label 3095*/ GIMT_Encode4(182293), // Rule ID 3364 // |
| 56720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 56721 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 56723 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56724 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 56725 | // (atomic_load_or:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_or_global_i32>> => (FLAT_ATOMIC_OR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 56726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_RTN), |
| 56727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 56729 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 56730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56732 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56733 | GIR_RootConstrainSelectedInstOperands, |
| 56734 | // GIR_Coverage, 3364, |
| 56735 | GIR_EraseRootFromParent_Done, |
| 56736 | // Label 3095: @182293 |
| 56737 | GIM_Reject, |
| 56738 | // Label 3073: @182294 |
| 56739 | GIM_Reject, |
| 56740 | // Label 3071: @182295 |
| 56741 | GIM_Try, /*On fail goto*//*Label 3096*/ GIMT_Encode4(183540), |
| 56742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 56743 | GIM_Try, /*On fail goto*//*Label 3097*/ GIMT_Encode4(182365), // Rule ID 5412 // |
| 56744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56745 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56746 | GIM_CheckHasNoUse, /*MI*/0, |
| 56747 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56749 | // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>> => (BUFFER_ATOMIC_OR_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64), |
| 56751 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56758 | GIR_RootConstrainSelectedInstOperands, |
| 56759 | // GIR_Coverage, 5412, |
| 56760 | GIR_EraseRootFromParent_Done, |
| 56761 | // Label 3097: @182365 |
| 56762 | GIM_Try, /*On fail goto*//*Label 3098*/ GIMT_Encode4(182424), // Rule ID 5416 // |
| 56763 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56764 | GIM_CheckHasNoUse, /*MI*/0, |
| 56765 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56767 | // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64), |
| 56769 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56776 | GIR_RootConstrainSelectedInstOperands, |
| 56777 | // GIR_Coverage, 5416, |
| 56778 | GIR_EraseRootFromParent_Done, |
| 56779 | // Label 3098: @182424 |
| 56780 | GIM_Try, /*On fail goto*//*Label 3099*/ GIMT_Encode4(182490), // Rule ID 5410 // |
| 56781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56782 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56783 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56784 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56785 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56786 | // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>> => (BUFFER_ATOMIC_OR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_ADDR64_RTN), |
| 56788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56789 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56796 | GIR_RootConstrainSelectedInstOperands, |
| 56797 | // GIR_Coverage, 5410, |
| 56798 | GIR_EraseRootFromParent_Done, |
| 56799 | // Label 3099: @182490 |
| 56800 | GIM_Try, /*On fail goto*//*Label 3100*/ GIMT_Encode4(182553), // Rule ID 5414 // |
| 56801 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56803 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56804 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 56805 | // (atomic_load_or:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_ADDR64_RTN), |
| 56807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56808 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 56810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 56812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 56813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56815 | GIR_RootConstrainSelectedInstOperands, |
| 56816 | // GIR_Coverage, 5414, |
| 56817 | GIR_EraseRootFromParent_Done, |
| 56818 | // Label 3100: @182553 |
| 56819 | GIM_Try, /*On fail goto*//*Label 3101*/ GIMT_Encode4(182610), // Rule ID 5411 // |
| 56820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56821 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56822 | GIM_CheckHasNoUse, /*MI*/0, |
| 56823 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56825 | // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>> => (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET), |
| 56827 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56832 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56833 | GIR_RootConstrainSelectedInstOperands, |
| 56834 | // GIR_Coverage, 5411, |
| 56835 | GIR_EraseRootFromParent_Done, |
| 56836 | // Label 3101: @182610 |
| 56837 | GIM_Try, /*On fail goto*//*Label 3102*/ GIMT_Encode4(182664), // Rule ID 5415 // |
| 56838 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56839 | GIM_CheckHasNoUse, /*MI*/0, |
| 56840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56842 | // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_noret_i64>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET), |
| 56844 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56849 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56850 | GIR_RootConstrainSelectedInstOperands, |
| 56851 | // GIR_Coverage, 5415, |
| 56852 | GIR_EraseRootFromParent_Done, |
| 56853 | // Label 3102: @182664 |
| 56854 | GIM_Try, /*On fail goto*//*Label 3103*/ GIMT_Encode4(182725), // Rule ID 5409 // |
| 56855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 56856 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56860 | // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>> => (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN), |
| 56862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56863 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56868 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56869 | GIR_RootConstrainSelectedInstOperands, |
| 56870 | // GIR_Coverage, 5409, |
| 56871 | GIR_EraseRootFromParent_Done, |
| 56872 | // Label 3103: @182725 |
| 56873 | GIM_Try, /*On fail goto*//*Label 3104*/ GIMT_Encode4(182783), // Rule ID 5413 // |
| 56874 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56876 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 56878 | // (atomic_load_or:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_or_global_i64>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 56879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN), |
| 56880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 56881 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 56882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 56883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 56884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 56885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56886 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56887 | GIR_RootConstrainSelectedInstOperands, |
| 56888 | // GIR_Coverage, 5413, |
| 56889 | GIR_EraseRootFromParent_Done, |
| 56890 | // Label 3104: @182783 |
| 56891 | GIM_Try, /*On fail goto*//*Label 3105*/ GIMT_Encode4(182833), // Rule ID 7902 // |
| 56892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56893 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56894 | GIM_CheckHasNoUse, /*MI*/0, |
| 56895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56897 | // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_noret_i64>> => (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64), |
| 56899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56900 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56903 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56904 | GIR_RootConstrainSelectedInstOperands, |
| 56905 | // GIR_Coverage, 7902, |
| 56906 | GIR_EraseRootFromParent_Done, |
| 56907 | // Label 3105: @182833 |
| 56908 | GIM_Try, /*On fail goto*//*Label 3106*/ GIMT_Encode4(182883), // Rule ID 7904 // |
| 56909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56910 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56911 | GIM_CheckHasNoUse, /*MI*/0, |
| 56912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56914 | // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_noret_i64>> => (DS_OR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64_gfx9), |
| 56916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56917 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56919 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56921 | GIR_RootConstrainSelectedInstOperands, |
| 56922 | // GIR_Coverage, 7904, |
| 56923 | GIR_EraseRootFromParent_Done, |
| 56924 | // Label 3106: @182883 |
| 56925 | GIM_Try, /*On fail goto*//*Label 3107*/ GIMT_Encode4(182933), // Rule ID 7906 // |
| 56926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56927 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56928 | GIM_CheckHasNoUse, /*MI*/0, |
| 56929 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56931 | // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_noret_i64>> => (DS_OR_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_B64), |
| 56933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56934 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56938 | GIR_RootConstrainSelectedInstOperands, |
| 56939 | // GIR_Coverage, 7906, |
| 56940 | GIR_EraseRootFromParent_Done, |
| 56941 | // Label 3107: @182933 |
| 56942 | GIM_Try, /*On fail goto*//*Label 3108*/ GIMT_Encode4(182987), // Rule ID 7901 // |
| 56943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 56944 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56946 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56948 | // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_m0_i64>> => (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64), |
| 56950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56952 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56955 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56956 | GIR_RootConstrainSelectedInstOperands, |
| 56957 | // GIR_Coverage, 7901, |
| 56958 | GIR_EraseRootFromParent_Done, |
| 56959 | // Label 3108: @182987 |
| 56960 | GIM_Try, /*On fail goto*//*Label 3109*/ GIMT_Encode4(183041), // Rule ID 7903 // |
| 56961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 56962 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 56963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56964 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56965 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56966 | // (atomic_load_or:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_local_i64>> => (DS_OR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 56967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64_gfx9), |
| 56968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56970 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 56973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56974 | GIR_RootConstrainSelectedInstOperands, |
| 56975 | // GIR_Coverage, 7903, |
| 56976 | GIR_EraseRootFromParent_Done, |
| 56977 | // Label 3109: @183041 |
| 56978 | GIM_Try, /*On fail goto*//*Label 3110*/ GIMT_Encode4(183095), // Rule ID 7905 // |
| 56979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 56980 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 56981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 56982 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 56983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 56984 | // (atomic_load_or_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_or_region_m0_i64>> => (DS_OR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 56985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_OR_RTN_B64), |
| 56986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 56987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 56988 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 56989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 56990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 56991 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 56992 | GIR_RootConstrainSelectedInstOperands, |
| 56993 | // GIR_Coverage, 7905, |
| 56994 | GIR_EraseRootFromParent_Done, |
| 56995 | // Label 3110: @183095 |
| 56996 | GIM_Try, /*On fail goto*//*Label 3111*/ GIMT_Encode4(183152), // Rule ID 3695 // |
| 56997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 56998 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 56999 | GIM_CheckHasNoUse, /*MI*/0, |
| 57000 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57001 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57002 | // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>> => (GLOBAL_ATOMIC_OR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR), |
| 57004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57005 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57009 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57010 | GIR_RootConstrainSelectedInstOperands, |
| 57011 | // GIR_Coverage, 3695, |
| 57012 | GIR_EraseRootFromParent_Done, |
| 57013 | // Label 3111: @183152 |
| 57014 | GIM_Try, /*On fail goto*//*Label 3112*/ GIMT_Encode4(183213), // Rule ID 3697 // |
| 57015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57016 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57018 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57020 | // (atomic_load_or:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>> => (GLOBAL_ATOMIC_OR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_SADDR_RTN), |
| 57022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57024 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57029 | GIR_RootConstrainSelectedInstOperands, |
| 57030 | // GIR_Coverage, 3697, |
| 57031 | GIR_EraseRootFromParent_Done, |
| 57032 | // Label 3112: @183213 |
| 57033 | GIM_Try, /*On fail goto*//*Label 3113*/ GIMT_Encode4(183265), // Rule ID 3694 // |
| 57034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57035 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57036 | GIM_CheckHasNoUse, /*MI*/0, |
| 57037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57039 | // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>> => (GLOBAL_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2), |
| 57041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57042 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57046 | GIR_RootConstrainSelectedInstOperands, |
| 57047 | // GIR_Coverage, 3694, |
| 57048 | GIR_EraseRootFromParent_Done, |
| 57049 | // Label 3113: @183265 |
| 57050 | GIM_Try, /*On fail goto*//*Label 3114*/ GIMT_Encode4(183321), // Rule ID 3696 // |
| 57051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57052 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57054 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57055 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57056 | // (atomic_load_or:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>> => (GLOBAL_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_OR_X2_RTN), |
| 57058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57060 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57064 | GIR_RootConstrainSelectedInstOperands, |
| 57065 | // GIR_Coverage, 3696, |
| 57066 | GIR_EraseRootFromParent_Done, |
| 57067 | // Label 3114: @183321 |
| 57068 | GIM_Try, /*On fail goto*//*Label 3115*/ GIMT_Encode4(183374), // Rule ID 3331 // |
| 57069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57070 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57071 | GIM_CheckHasNoUse, /*MI*/0, |
| 57072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57074 | // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_noret_i64>> => (FLAT_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2), |
| 57076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57077 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57081 | GIR_RootConstrainSelectedInstOperands, |
| 57082 | // GIR_Coverage, 3331, |
| 57083 | GIR_EraseRootFromParent_Done, |
| 57084 | // Label 3115: @183374 |
| 57085 | GIM_Try, /*On fail goto*//*Label 3116*/ GIMT_Encode4(183426), // Rule ID 3391 // |
| 57086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57087 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57088 | GIM_CheckHasNoUse, /*MI*/0, |
| 57089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57091 | // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_noret_i64>> => (FLAT_ATOMIC_OR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2), |
| 57093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57094 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57097 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57098 | GIR_RootConstrainSelectedInstOperands, |
| 57099 | // GIR_Coverage, 3391, |
| 57100 | GIR_EraseRootFromParent_Done, |
| 57101 | // Label 3116: @183426 |
| 57102 | GIM_Try, /*On fail goto*//*Label 3117*/ GIMT_Encode4(183483), // Rule ID 3330 // |
| 57103 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57104 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57105 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57106 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57107 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57108 | // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_flat_i64>> => (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN), |
| 57110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57112 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57115 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57116 | GIR_RootConstrainSelectedInstOperands, |
| 57117 | // GIR_Coverage, 3330, |
| 57118 | GIR_EraseRootFromParent_Done, |
| 57119 | // Label 3117: @183483 |
| 57120 | GIM_Try, /*On fail goto*//*Label 3118*/ GIMT_Encode4(183539), // Rule ID 3390 // |
| 57121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57122 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57126 | // (atomic_load_or:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_or_global_i64>> => (FLAT_ATOMIC_OR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_OR_X2_RTN), |
| 57128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57130 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57134 | GIR_RootConstrainSelectedInstOperands, |
| 57135 | // GIR_Coverage, 3390, |
| 57136 | GIR_EraseRootFromParent_Done, |
| 57137 | // Label 3118: @183539 |
| 57138 | GIM_Reject, |
| 57139 | // Label 3096: @183540 |
| 57140 | GIM_Reject, |
| 57141 | // Label 3072: @183541 |
| 57142 | GIM_Reject, |
| 57143 | // Label 23: @183542 |
| 57144 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3121*/ GIMT_Encode4(186053), |
| 57145 | /*GILLT_s32*//*Label 3119*/ GIMT_Encode4(183561), |
| 57146 | /*GILLT_s64*//*Label 3120*/ GIMT_Encode4(184807), |
| 57147 | // Label 3119: @183561 |
| 57148 | GIM_Try, /*On fail goto*//*Label 3122*/ GIMT_Encode4(184806), |
| 57149 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 57150 | GIM_Try, /*On fail goto*//*Label 3123*/ GIMT_Encode4(183631), // Rule ID 5324 // |
| 57151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57152 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57153 | GIM_CheckHasNoUse, /*MI*/0, |
| 57154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57155 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57156 | // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (BUFFER_ATOMIC_XOR_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64), |
| 57158 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57165 | GIR_RootConstrainSelectedInstOperands, |
| 57166 | // GIR_Coverage, 5324, |
| 57167 | GIR_EraseRootFromParent_Done, |
| 57168 | // Label 3123: @183631 |
| 57169 | GIM_Try, /*On fail goto*//*Label 3124*/ GIMT_Encode4(183690), // Rule ID 5328 // |
| 57170 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57171 | GIM_CheckHasNoUse, /*MI*/0, |
| 57172 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57174 | // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64), |
| 57176 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57183 | GIR_RootConstrainSelectedInstOperands, |
| 57184 | // GIR_Coverage, 5328, |
| 57185 | GIR_EraseRootFromParent_Done, |
| 57186 | // Label 3124: @183690 |
| 57187 | GIM_Try, /*On fail goto*//*Label 3125*/ GIMT_Encode4(183756), // Rule ID 5322 // |
| 57188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57189 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57191 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57193 | // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>> => (BUFFER_ATOMIC_XOR_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_ADDR64_RTN), |
| 57195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57196 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57202 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57203 | GIR_RootConstrainSelectedInstOperands, |
| 57204 | // GIR_Coverage, 5322, |
| 57205 | GIR_EraseRootFromParent_Done, |
| 57206 | // Label 3125: @183756 |
| 57207 | GIM_Try, /*On fail goto*//*Label 3126*/ GIMT_Encode4(183819), // Rule ID 5326 // |
| 57208 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57210 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57212 | // (atomic_load_xor:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>> => (BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_ADDR64_RTN), |
| 57214 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57215 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57221 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57222 | GIR_RootConstrainSelectedInstOperands, |
| 57223 | // GIR_Coverage, 5326, |
| 57224 | GIR_EraseRootFromParent_Done, |
| 57225 | // Label 3126: @183819 |
| 57226 | GIM_Try, /*On fail goto*//*Label 3127*/ GIMT_Encode4(183876), // Rule ID 5323 // |
| 57227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57228 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57229 | GIM_CheckHasNoUse, /*MI*/0, |
| 57230 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57231 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57232 | // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (BUFFER_ATOMIC_XOR_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET), |
| 57234 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57239 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57240 | GIR_RootConstrainSelectedInstOperands, |
| 57241 | // GIR_Coverage, 5323, |
| 57242 | GIR_EraseRootFromParent_Done, |
| 57243 | // Label 3127: @183876 |
| 57244 | GIM_Try, /*On fail goto*//*Label 3128*/ GIMT_Encode4(183930), // Rule ID 5327 // |
| 57245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57246 | GIM_CheckHasNoUse, /*MI*/0, |
| 57247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57249 | // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET), |
| 57251 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57257 | GIR_RootConstrainSelectedInstOperands, |
| 57258 | // GIR_Coverage, 5327, |
| 57259 | GIR_EraseRootFromParent_Done, |
| 57260 | // Label 3128: @183930 |
| 57261 | GIM_Try, /*On fail goto*//*Label 3129*/ GIMT_Encode4(183991), // Rule ID 5321 // |
| 57262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57263 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57265 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57266 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57267 | // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>> => (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN), |
| 57269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57270 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57276 | GIR_RootConstrainSelectedInstOperands, |
| 57277 | // GIR_Coverage, 5321, |
| 57278 | GIR_EraseRootFromParent_Done, |
| 57279 | // Label 3129: @183991 |
| 57280 | GIM_Try, /*On fail goto*//*Label 3130*/ GIMT_Encode4(184049), // Rule ID 5325 // |
| 57281 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57284 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57285 | // (atomic_load_xor:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i32>> => (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN), |
| 57287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57288 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57293 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57294 | GIR_RootConstrainSelectedInstOperands, |
| 57295 | // GIR_Coverage, 5325, |
| 57296 | GIR_EraseRootFromParent_Done, |
| 57297 | // Label 3130: @184049 |
| 57298 | GIM_Try, /*On fail goto*//*Label 3131*/ GIMT_Encode4(184099), // Rule ID 7809 // |
| 57299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 57300 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57301 | GIM_CheckHasNoUse, /*MI*/0, |
| 57302 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57303 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57304 | // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i32>> => (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32), |
| 57306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57307 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57310 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57311 | GIR_RootConstrainSelectedInstOperands, |
| 57312 | // GIR_Coverage, 7809, |
| 57313 | GIR_EraseRootFromParent_Done, |
| 57314 | // Label 3131: @184099 |
| 57315 | GIM_Try, /*On fail goto*//*Label 3132*/ GIMT_Encode4(184149), // Rule ID 7811 // |
| 57316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 57317 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57318 | GIM_CheckHasNoUse, /*MI*/0, |
| 57319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57321 | // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i32>> => (DS_XOR_B32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32_gfx9), |
| 57323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57324 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57328 | GIR_RootConstrainSelectedInstOperands, |
| 57329 | // GIR_Coverage, 7811, |
| 57330 | GIR_EraseRootFromParent_Done, |
| 57331 | // Label 3132: @184149 |
| 57332 | GIM_Try, /*On fail goto*//*Label 3133*/ GIMT_Encode4(184199), // Rule ID 7813 // |
| 57333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 57334 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 57335 | GIM_CheckHasNoUse, /*MI*/0, |
| 57336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57338 | // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i32>> => (DS_XOR_B32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 57339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B32), |
| 57340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57341 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57345 | GIR_RootConstrainSelectedInstOperands, |
| 57346 | // GIR_Coverage, 7813, |
| 57347 | GIR_EraseRootFromParent_Done, |
| 57348 | // Label 3133: @184199 |
| 57349 | GIM_Try, /*On fail goto*//*Label 3134*/ GIMT_Encode4(184253), // Rule ID 7808 // |
| 57350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 57351 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57353 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57355 | // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i32>> => (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32), |
| 57357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57359 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57362 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57363 | GIR_RootConstrainSelectedInstOperands, |
| 57364 | // GIR_Coverage, 7808, |
| 57365 | GIR_EraseRootFromParent_Done, |
| 57366 | // Label 3134: @184253 |
| 57367 | GIM_Try, /*On fail goto*//*Label 3135*/ GIMT_Encode4(184307), // Rule ID 7810 // |
| 57368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 57369 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57371 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57373 | // (atomic_load_xor:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_local_i32>> => (DS_XOR_RTN_B32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32_gfx9), |
| 57375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57377 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57381 | GIR_RootConstrainSelectedInstOperands, |
| 57382 | // GIR_Coverage, 7810, |
| 57383 | GIR_EraseRootFromParent_Done, |
| 57384 | // Label 3135: @184307 |
| 57385 | GIM_Try, /*On fail goto*//*Label 3136*/ GIMT_Encode4(184361), // Rule ID 7812 // |
| 57386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 57387 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 57388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57389 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57390 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57391 | // (atomic_load_xor_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i32>> => (DS_XOR_RTN_B32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 57392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B32), |
| 57393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57395 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57399 | GIR_RootConstrainSelectedInstOperands, |
| 57400 | // GIR_Coverage, 7812, |
| 57401 | GIR_EraseRootFromParent_Done, |
| 57402 | // Label 3136: @184361 |
| 57403 | GIM_Try, /*On fail goto*//*Label 3137*/ GIMT_Encode4(184418), // Rule ID 3651 // |
| 57404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57405 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57406 | GIM_CheckHasNoUse, /*MI*/0, |
| 57407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57409 | // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (GLOBAL_ATOMIC_XOR_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR), |
| 57411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57412 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57417 | GIR_RootConstrainSelectedInstOperands, |
| 57418 | // GIR_Coverage, 3651, |
| 57419 | GIR_EraseRootFromParent_Done, |
| 57420 | // Label 3137: @184418 |
| 57421 | GIM_Try, /*On fail goto*//*Label 3138*/ GIMT_Encode4(184479), // Rule ID 3653 // |
| 57422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57423 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57425 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57427 | // (atomic_load_xor:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>> => (GLOBAL_ATOMIC_XOR_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_SADDR_RTN), |
| 57429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57431 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57435 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57436 | GIR_RootConstrainSelectedInstOperands, |
| 57437 | // GIR_Coverage, 3653, |
| 57438 | GIR_EraseRootFromParent_Done, |
| 57439 | // Label 3138: @184479 |
| 57440 | GIM_Try, /*On fail goto*//*Label 3139*/ GIMT_Encode4(184531), // Rule ID 3650 // |
| 57441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57442 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57443 | GIM_CheckHasNoUse, /*MI*/0, |
| 57444 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57446 | // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (GLOBAL_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR), |
| 57448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57449 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57453 | GIR_RootConstrainSelectedInstOperands, |
| 57454 | // GIR_Coverage, 3650, |
| 57455 | GIR_EraseRootFromParent_Done, |
| 57456 | // Label 3139: @184531 |
| 57457 | GIM_Try, /*On fail goto*//*Label 3140*/ GIMT_Encode4(184587), // Rule ID 3652 // |
| 57458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57459 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57463 | // (atomic_load_xor:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>> => (GLOBAL_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_RTN), |
| 57465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57467 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57471 | GIR_RootConstrainSelectedInstOperands, |
| 57472 | // GIR_Coverage, 3652, |
| 57473 | GIR_EraseRootFromParent_Done, |
| 57474 | // Label 3140: @184587 |
| 57475 | GIM_Try, /*On fail goto*//*Label 3141*/ GIMT_Encode4(184640), // Rule ID 3311 // |
| 57476 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57477 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57478 | GIM_CheckHasNoUse, /*MI*/0, |
| 57479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57480 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57481 | // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i32>> => (FLAT_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR), |
| 57483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57484 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57488 | GIR_RootConstrainSelectedInstOperands, |
| 57489 | // GIR_Coverage, 3311, |
| 57490 | GIR_EraseRootFromParent_Done, |
| 57491 | // Label 3141: @184640 |
| 57492 | GIM_Try, /*On fail goto*//*Label 3142*/ GIMT_Encode4(184692), // Rule ID 3371 // |
| 57493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57495 | GIM_CheckHasNoUse, /*MI*/0, |
| 57496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57498 | // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i32>> => (FLAT_ATOMIC_XOR VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR), |
| 57500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57501 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57505 | GIR_RootConstrainSelectedInstOperands, |
| 57506 | // GIR_Coverage, 3371, |
| 57507 | GIR_EraseRootFromParent_Done, |
| 57508 | // Label 3142: @184692 |
| 57509 | GIM_Try, /*On fail goto*//*Label 3143*/ GIMT_Encode4(184749), // Rule ID 3310 // |
| 57510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57511 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57513 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57515 | // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_flat_i32>> => (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN), |
| 57517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57519 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57523 | GIR_RootConstrainSelectedInstOperands, |
| 57524 | // GIR_Coverage, 3310, |
| 57525 | GIR_EraseRootFromParent_Done, |
| 57526 | // Label 3143: @184749 |
| 57527 | GIM_Try, /*On fail goto*//*Label 3144*/ GIMT_Encode4(184805), // Rule ID 3370 // |
| 57528 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57529 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57531 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57532 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57533 | // (atomic_load_xor:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_xor_global_i32>> => (FLAT_ATOMIC_XOR_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 57534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_RTN), |
| 57535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57537 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57541 | GIR_RootConstrainSelectedInstOperands, |
| 57542 | // GIR_Coverage, 3370, |
| 57543 | GIR_EraseRootFromParent_Done, |
| 57544 | // Label 3144: @184805 |
| 57545 | GIM_Reject, |
| 57546 | // Label 3122: @184806 |
| 57547 | GIM_Reject, |
| 57548 | // Label 3120: @184807 |
| 57549 | GIM_Try, /*On fail goto*//*Label 3145*/ GIMT_Encode4(186052), |
| 57550 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 57551 | GIM_Try, /*On fail goto*//*Label 3146*/ GIMT_Encode4(184877), // Rule ID 5420 // |
| 57552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57553 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57554 | GIM_CheckHasNoUse, /*MI*/0, |
| 57555 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57556 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57557 | // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (BUFFER_ATOMIC_XOR_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57558 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64), |
| 57559 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57565 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57566 | GIR_RootConstrainSelectedInstOperands, |
| 57567 | // GIR_Coverage, 5420, |
| 57568 | GIR_EraseRootFromParent_Done, |
| 57569 | // Label 3146: @184877 |
| 57570 | GIM_Try, /*On fail goto*//*Label 3147*/ GIMT_Encode4(184936), // Rule ID 5424 // |
| 57571 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57572 | GIM_CheckHasNoUse, /*MI*/0, |
| 57573 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57575 | // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64), |
| 57577 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57583 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57584 | GIR_RootConstrainSelectedInstOperands, |
| 57585 | // GIR_Coverage, 5424, |
| 57586 | GIR_EraseRootFromParent_Done, |
| 57587 | // Label 3147: @184936 |
| 57588 | GIM_Try, /*On fail goto*//*Label 3148*/ GIMT_Encode4(185002), // Rule ID 5418 // |
| 57589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57590 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57592 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57593 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57594 | // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>> => (BUFFER_ATOMIC_XOR_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_ADDR64_RTN), |
| 57596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57597 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57604 | GIR_RootConstrainSelectedInstOperands, |
| 57605 | // GIR_Coverage, 5418, |
| 57606 | GIR_EraseRootFromParent_Done, |
| 57607 | // Label 3148: @185002 |
| 57608 | GIM_Try, /*On fail goto*//*Label 3149*/ GIMT_Encode4(185065), // Rule ID 5422 // |
| 57609 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57611 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57612 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57613 | // (atomic_load_xor:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_ADDR64_RTN), |
| 57615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57616 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57623 | GIR_RootConstrainSelectedInstOperands, |
| 57624 | // GIR_Coverage, 5422, |
| 57625 | GIR_EraseRootFromParent_Done, |
| 57626 | // Label 3149: @185065 |
| 57627 | GIM_Try, /*On fail goto*//*Label 3150*/ GIMT_Encode4(185122), // Rule ID 5419 // |
| 57628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57629 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57630 | GIM_CheckHasNoUse, /*MI*/0, |
| 57631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57633 | // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET), |
| 57635 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57641 | GIR_RootConstrainSelectedInstOperands, |
| 57642 | // GIR_Coverage, 5419, |
| 57643 | GIR_EraseRootFromParent_Done, |
| 57644 | // Label 3150: @185122 |
| 57645 | GIM_Try, /*On fail goto*//*Label 3151*/ GIMT_Encode4(185176), // Rule ID 5423 // |
| 57646 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57647 | GIM_CheckHasNoUse, /*MI*/0, |
| 57648 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57650 | // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET), |
| 57652 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57657 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57658 | GIR_RootConstrainSelectedInstOperands, |
| 57659 | // GIR_Coverage, 5423, |
| 57660 | GIR_EraseRootFromParent_Done, |
| 57661 | // Label 3151: @185176 |
| 57662 | GIM_Try, /*On fail goto*//*Label 3152*/ GIMT_Encode4(185237), // Rule ID 5417 // |
| 57663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57664 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57666 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57667 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57668 | // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>> => (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN), |
| 57670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57671 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57676 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57677 | GIR_RootConstrainSelectedInstOperands, |
| 57678 | // GIR_Coverage, 5417, |
| 57679 | GIR_EraseRootFromParent_Done, |
| 57680 | // Label 3152: @185237 |
| 57681 | GIM_Try, /*On fail goto*//*Label 3153*/ GIMT_Encode4(185295), // Rule ID 5421 // |
| 57682 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 57686 | // (atomic_load_xor:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_xor_global_i64>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN), |
| 57688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 57689 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 57692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57695 | GIR_RootConstrainSelectedInstOperands, |
| 57696 | // GIR_Coverage, 5421, |
| 57697 | GIR_EraseRootFromParent_Done, |
| 57698 | // Label 3153: @185295 |
| 57699 | GIM_Try, /*On fail goto*//*Label 3154*/ GIMT_Encode4(185345), // Rule ID 7908 // |
| 57700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 57701 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57702 | GIM_CheckHasNoUse, /*MI*/0, |
| 57703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57705 | // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_noret_i64>> => (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64), |
| 57707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57708 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57710 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57712 | GIR_RootConstrainSelectedInstOperands, |
| 57713 | // GIR_Coverage, 7908, |
| 57714 | GIR_EraseRootFromParent_Done, |
| 57715 | // Label 3154: @185345 |
| 57716 | GIM_Try, /*On fail goto*//*Label 3155*/ GIMT_Encode4(185395), // Rule ID 7910 // |
| 57717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 57718 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57719 | GIM_CheckHasNoUse, /*MI*/0, |
| 57720 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57721 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57722 | // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_noret_i64>> => (DS_XOR_B64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64_gfx9), |
| 57724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57725 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57729 | GIR_RootConstrainSelectedInstOperands, |
| 57730 | // GIR_Coverage, 7910, |
| 57731 | GIR_EraseRootFromParent_Done, |
| 57732 | // Label 3155: @185395 |
| 57733 | GIM_Try, /*On fail goto*//*Label 3156*/ GIMT_Encode4(185445), // Rule ID 7912 // |
| 57734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 57735 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 57736 | GIM_CheckHasNoUse, /*MI*/0, |
| 57737 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57739 | // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_noret_i64>> => (DS_XOR_B64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 57740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_B64), |
| 57741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57742 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57745 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57746 | GIR_RootConstrainSelectedInstOperands, |
| 57747 | // GIR_Coverage, 7912, |
| 57748 | GIR_EraseRootFromParent_Done, |
| 57749 | // Label 3156: @185445 |
| 57750 | GIM_Try, /*On fail goto*//*Label 3157*/ GIMT_Encode4(185499), // Rule ID 7907 // |
| 57751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 57752 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57753 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57754 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57755 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57756 | // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_m0_i64>> => (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64), |
| 57758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57760 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57764 | GIR_RootConstrainSelectedInstOperands, |
| 57765 | // GIR_Coverage, 7907, |
| 57766 | GIR_EraseRootFromParent_Done, |
| 57767 | // Label 3157: @185499 |
| 57768 | GIM_Try, /*On fail goto*//*Label 3158*/ GIMT_Encode4(185553), // Rule ID 7909 // |
| 57769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 57770 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 57771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57774 | // (atomic_load_xor:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_local_i64>> => (DS_XOR_RTN_B64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 57775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64_gfx9), |
| 57776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57778 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57781 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57782 | GIR_RootConstrainSelectedInstOperands, |
| 57783 | // GIR_Coverage, 7909, |
| 57784 | GIR_EraseRootFromParent_Done, |
| 57785 | // Label 3158: @185553 |
| 57786 | GIM_Try, /*On fail goto*//*Label 3159*/ GIMT_Encode4(185607), // Rule ID 7911 // |
| 57787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 57788 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 57789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57790 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 57792 | // (atomic_load_xor_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_xor_region_m0_i64>> => (DS_XOR_RTN_B64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 57793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_XOR_RTN_B64), |
| 57794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 57796 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 57797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57800 | GIR_RootConstrainSelectedInstOperands, |
| 57801 | // GIR_Coverage, 7911, |
| 57802 | GIR_EraseRootFromParent_Done, |
| 57803 | // Label 3159: @185607 |
| 57804 | GIM_Try, /*On fail goto*//*Label 3160*/ GIMT_Encode4(185664), // Rule ID 3707 // |
| 57805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57806 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57807 | GIM_CheckHasNoUse, /*MI*/0, |
| 57808 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57810 | // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (GLOBAL_ATOMIC_XOR_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR), |
| 57812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57813 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57818 | GIR_RootConstrainSelectedInstOperands, |
| 57819 | // GIR_Coverage, 3707, |
| 57820 | GIR_EraseRootFromParent_Done, |
| 57821 | // Label 3160: @185664 |
| 57822 | GIM_Try, /*On fail goto*//*Label 3161*/ GIMT_Encode4(185725), // Rule ID 3709 // |
| 57823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57824 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 57828 | // (atomic_load_xor:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>> => (GLOBAL_ATOMIC_XOR_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 57829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_SADDR_RTN), |
| 57830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 57832 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 57834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 57835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57837 | GIR_RootConstrainSelectedInstOperands, |
| 57838 | // GIR_Coverage, 3709, |
| 57839 | GIR_EraseRootFromParent_Done, |
| 57840 | // Label 3161: @185725 |
| 57841 | GIM_Try, /*On fail goto*//*Label 3162*/ GIMT_Encode4(185777), // Rule ID 3706 // |
| 57842 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57843 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57844 | GIM_CheckHasNoUse, /*MI*/0, |
| 57845 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57847 | // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (GLOBAL_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2), |
| 57849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57850 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57854 | GIR_RootConstrainSelectedInstOperands, |
| 57855 | // GIR_Coverage, 3706, |
| 57856 | GIR_EraseRootFromParent_Done, |
| 57857 | // Label 3162: @185777 |
| 57858 | GIM_Try, /*On fail goto*//*Label 3163*/ GIMT_Encode4(185833), // Rule ID 3708 // |
| 57859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 57860 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57862 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57863 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 57864 | // (atomic_load_xor:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>> => (GLOBAL_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_XOR_X2_RTN), |
| 57866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57868 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57871 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57872 | GIR_RootConstrainSelectedInstOperands, |
| 57873 | // GIR_Coverage, 3708, |
| 57874 | GIR_EraseRootFromParent_Done, |
| 57875 | // Label 3163: @185833 |
| 57876 | GIM_Try, /*On fail goto*//*Label 3164*/ GIMT_Encode4(185886), // Rule ID 3337 // |
| 57877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57878 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57879 | GIM_CheckHasNoUse, /*MI*/0, |
| 57880 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57882 | // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_noret_i64>> => (FLAT_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2), |
| 57884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57885 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57889 | GIR_RootConstrainSelectedInstOperands, |
| 57890 | // GIR_Coverage, 3337, |
| 57891 | GIR_EraseRootFromParent_Done, |
| 57892 | // Label 3164: @185886 |
| 57893 | GIM_Try, /*On fail goto*//*Label 3165*/ GIMT_Encode4(185938), // Rule ID 3397 // |
| 57894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57895 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57896 | GIM_CheckHasNoUse, /*MI*/0, |
| 57897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57899 | // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_noret_i64>> => (FLAT_ATOMIC_XOR_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2), |
| 57901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57902 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57905 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57906 | GIR_RootConstrainSelectedInstOperands, |
| 57907 | // GIR_Coverage, 3397, |
| 57908 | GIR_EraseRootFromParent_Done, |
| 57909 | // Label 3165: @185938 |
| 57910 | GIM_Try, /*On fail goto*//*Label 3166*/ GIMT_Encode4(185995), // Rule ID 3336 // |
| 57911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57912 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57914 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57916 | // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_flat_i64>> => (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN), |
| 57918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57920 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57924 | GIR_RootConstrainSelectedInstOperands, |
| 57925 | // GIR_Coverage, 3336, |
| 57926 | GIR_EraseRootFromParent_Done, |
| 57927 | // Label 3166: @185995 |
| 57928 | GIM_Try, /*On fail goto*//*Label 3167*/ GIMT_Encode4(186051), // Rule ID 3396 // |
| 57929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 57930 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 57932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 57934 | // (atomic_load_xor:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_xor_global_i64>> => (FLAT_ATOMIC_XOR_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 57935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_XOR_X2_RTN), |
| 57936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 57937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 57938 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 57939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 57940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 57941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57942 | GIR_RootConstrainSelectedInstOperands, |
| 57943 | // GIR_Coverage, 3396, |
| 57944 | GIR_EraseRootFromParent_Done, |
| 57945 | // Label 3167: @186051 |
| 57946 | GIM_Reject, |
| 57947 | // Label 3145: @186052 |
| 57948 | GIM_Reject, |
| 57949 | // Label 3121: @186053 |
| 57950 | GIM_Reject, |
| 57951 | // Label 24: @186054 |
| 57952 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3170*/ GIMT_Encode4(188565), |
| 57953 | /*GILLT_s32*//*Label 3168*/ GIMT_Encode4(186073), |
| 57954 | /*GILLT_s64*//*Label 3169*/ GIMT_Encode4(187319), |
| 57955 | // Label 3168: @186073 |
| 57956 | GIM_Try, /*On fail goto*//*Label 3171*/ GIMT_Encode4(187318), |
| 57957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 57958 | GIM_Try, /*On fail goto*//*Label 3172*/ GIMT_Encode4(186143), // Rule ID 5292 // |
| 57959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57960 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57961 | GIM_CheckHasNoUse, /*MI*/0, |
| 57962 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57964 | // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>> => (BUFFER_ATOMIC_SMAX_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64), |
| 57966 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57971 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57972 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57973 | GIR_RootConstrainSelectedInstOperands, |
| 57974 | // GIR_Coverage, 5292, |
| 57975 | GIR_EraseRootFromParent_Done, |
| 57976 | // Label 3172: @186143 |
| 57977 | GIM_Try, /*On fail goto*//*Label 3173*/ GIMT_Encode4(186202), // Rule ID 5296 // |
| 57978 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57979 | GIM_CheckHasNoUse, /*MI*/0, |
| 57980 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 57981 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 57982 | // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>> => (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 57983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64), |
| 57984 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 57985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 57986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 57987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 57988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 57989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 57990 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 57991 | GIR_RootConstrainSelectedInstOperands, |
| 57992 | // GIR_Coverage, 5296, |
| 57993 | GIR_EraseRootFromParent_Done, |
| 57994 | // Label 3173: @186202 |
| 57995 | GIM_Try, /*On fail goto*//*Label 3174*/ GIMT_Encode4(186268), // Rule ID 5290 // |
| 57996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 57997 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 57998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 57999 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58000 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58001 | // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>> => (BUFFER_ATOMIC_SMAX_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_ADDR64_RTN), |
| 58003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58004 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58011 | GIR_RootConstrainSelectedInstOperands, |
| 58012 | // GIR_Coverage, 5290, |
| 58013 | GIR_EraseRootFromParent_Done, |
| 58014 | // Label 3174: @186268 |
| 58015 | GIM_Try, /*On fail goto*//*Label 3175*/ GIMT_Encode4(186331), // Rule ID 5294 // |
| 58016 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58018 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58020 | // (atomic_load_max:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>> => (BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_ADDR64_RTN), |
| 58022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58023 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58030 | GIR_RootConstrainSelectedInstOperands, |
| 58031 | // GIR_Coverage, 5294, |
| 58032 | GIR_EraseRootFromParent_Done, |
| 58033 | // Label 3175: @186331 |
| 58034 | GIM_Try, /*On fail goto*//*Label 3176*/ GIMT_Encode4(186388), // Rule ID 5291 // |
| 58035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58036 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58037 | GIM_CheckHasNoUse, /*MI*/0, |
| 58038 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58040 | // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>> => (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET), |
| 58042 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58048 | GIR_RootConstrainSelectedInstOperands, |
| 58049 | // GIR_Coverage, 5291, |
| 58050 | GIR_EraseRootFromParent_Done, |
| 58051 | // Label 3176: @186388 |
| 58052 | GIM_Try, /*On fail goto*//*Label 3177*/ GIMT_Encode4(186442), // Rule ID 5295 // |
| 58053 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58054 | GIM_CheckHasNoUse, /*MI*/0, |
| 58055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58057 | // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i32>> => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET), |
| 58059 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58065 | GIR_RootConstrainSelectedInstOperands, |
| 58066 | // GIR_Coverage, 5295, |
| 58067 | GIR_EraseRootFromParent_Done, |
| 58068 | // Label 3177: @186442 |
| 58069 | GIM_Try, /*On fail goto*//*Label 3178*/ GIMT_Encode4(186503), // Rule ID 5289 // |
| 58070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58071 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58073 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58074 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58075 | // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>> => (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN), |
| 58077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58078 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58084 | GIR_RootConstrainSelectedInstOperands, |
| 58085 | // GIR_Coverage, 5289, |
| 58086 | GIR_EraseRootFromParent_Done, |
| 58087 | // Label 3178: @186503 |
| 58088 | GIM_Try, /*On fail goto*//*Label 3179*/ GIMT_Encode4(186561), // Rule ID 5293 // |
| 58089 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58093 | // (atomic_load_max:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i32>> => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN), |
| 58095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58096 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58102 | GIR_RootConstrainSelectedInstOperands, |
| 58103 | // GIR_Coverage, 5293, |
| 58104 | GIR_EraseRootFromParent_Done, |
| 58105 | // Label 3179: @186561 |
| 58106 | GIM_Try, /*On fail goto*//*Label 3180*/ GIMT_Encode4(186611), // Rule ID 7821 // |
| 58107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58108 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58109 | GIM_CheckHasNoUse, /*MI*/0, |
| 58110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58112 | // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i32>> => (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32), |
| 58114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58115 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58119 | GIR_RootConstrainSelectedInstOperands, |
| 58120 | // GIR_Coverage, 7821, |
| 58121 | GIR_EraseRootFromParent_Done, |
| 58122 | // Label 3180: @186611 |
| 58123 | GIM_Try, /*On fail goto*//*Label 3181*/ GIMT_Encode4(186661), // Rule ID 7823 // |
| 58124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58125 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58126 | GIM_CheckHasNoUse, /*MI*/0, |
| 58127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58128 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58129 | // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_noret_i32>> => (DS_MAX_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32_gfx9), |
| 58131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58132 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58136 | GIR_RootConstrainSelectedInstOperands, |
| 58137 | // GIR_Coverage, 7823, |
| 58138 | GIR_EraseRootFromParent_Done, |
| 58139 | // Label 3181: @186661 |
| 58140 | GIM_Try, /*On fail goto*//*Label 3182*/ GIMT_Encode4(186711), // Rule ID 7825 // |
| 58141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 58142 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 58143 | GIM_CheckHasNoUse, /*MI*/0, |
| 58144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58146 | // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i32>> => (DS_MAX_I32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 58147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I32), |
| 58148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58149 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58153 | GIR_RootConstrainSelectedInstOperands, |
| 58154 | // GIR_Coverage, 7825, |
| 58155 | GIR_EraseRootFromParent_Done, |
| 58156 | // Label 3182: @186711 |
| 58157 | GIM_Try, /*On fail goto*//*Label 3183*/ GIMT_Encode4(186765), // Rule ID 7820 // |
| 58158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58159 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58163 | // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_m0_i32>> => (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32), |
| 58165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58167 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58170 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58171 | GIR_RootConstrainSelectedInstOperands, |
| 58172 | // GIR_Coverage, 7820, |
| 58173 | GIR_EraseRootFromParent_Done, |
| 58174 | // Label 3183: @186765 |
| 58175 | GIM_Try, /*On fail goto*//*Label 3184*/ GIMT_Encode4(186819), // Rule ID 7822 // |
| 58176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58177 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58179 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58181 | // (atomic_load_max:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_local_i32>> => (DS_MAX_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32_gfx9), |
| 58183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58185 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58188 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58189 | GIR_RootConstrainSelectedInstOperands, |
| 58190 | // GIR_Coverage, 7822, |
| 58191 | GIR_EraseRootFromParent_Done, |
| 58192 | // Label 3184: @186819 |
| 58193 | GIM_Try, /*On fail goto*//*Label 3185*/ GIMT_Encode4(186873), // Rule ID 7824 // |
| 58194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 58195 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 58196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58197 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58199 | // (atomic_load_max_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_max_region_m0_i32>> => (DS_MAX_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 58200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I32), |
| 58201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58203 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58207 | GIR_RootConstrainSelectedInstOperands, |
| 58208 | // GIR_Coverage, 7824, |
| 58209 | GIR_EraseRootFromParent_Done, |
| 58210 | // Label 3185: @186873 |
| 58211 | GIM_Try, /*On fail goto*//*Label 3186*/ GIMT_Encode4(186930), // Rule ID 3623 // |
| 58212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58213 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58214 | GIM_CheckHasNoUse, /*MI*/0, |
| 58215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 58217 | // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>> => (GLOBAL_ATOMIC_SMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 58218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR), |
| 58219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 58220 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 58222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58224 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58225 | GIR_RootConstrainSelectedInstOperands, |
| 58226 | // GIR_Coverage, 3623, |
| 58227 | GIR_EraseRootFromParent_Done, |
| 58228 | // Label 3186: @186930 |
| 58229 | GIM_Try, /*On fail goto*//*Label 3187*/ GIMT_Encode4(186991), // Rule ID 3625 // |
| 58230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58231 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 58235 | // (atomic_load_max:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>> => (GLOBAL_ATOMIC_SMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 58236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_SADDR_RTN), |
| 58237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 58239 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 58241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58243 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58244 | GIR_RootConstrainSelectedInstOperands, |
| 58245 | // GIR_Coverage, 3625, |
| 58246 | GIR_EraseRootFromParent_Done, |
| 58247 | // Label 3187: @186991 |
| 58248 | GIM_Try, /*On fail goto*//*Label 3188*/ GIMT_Encode4(187043), // Rule ID 3622 // |
| 58249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58250 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58251 | GIM_CheckHasNoUse, /*MI*/0, |
| 58252 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58253 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 58254 | // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>> => (GLOBAL_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX), |
| 58256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58257 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58261 | GIR_RootConstrainSelectedInstOperands, |
| 58262 | // GIR_Coverage, 3622, |
| 58263 | GIR_EraseRootFromParent_Done, |
| 58264 | // Label 3188: @187043 |
| 58265 | GIM_Try, /*On fail goto*//*Label 3189*/ GIMT_Encode4(187099), // Rule ID 3624 // |
| 58266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58267 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58269 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 58271 | // (atomic_load_max:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>> => (GLOBAL_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_RTN), |
| 58273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58275 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58279 | GIR_RootConstrainSelectedInstOperands, |
| 58280 | // GIR_Coverage, 3624, |
| 58281 | GIR_EraseRootFromParent_Done, |
| 58282 | // Label 3189: @187099 |
| 58283 | GIM_Try, /*On fail goto*//*Label 3190*/ GIMT_Encode4(187152), // Rule ID 3297 // |
| 58284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58285 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58286 | GIM_CheckHasNoUse, /*MI*/0, |
| 58287 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58289 | // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i32>> => (FLAT_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX), |
| 58291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58292 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58296 | GIR_RootConstrainSelectedInstOperands, |
| 58297 | // GIR_Coverage, 3297, |
| 58298 | GIR_EraseRootFromParent_Done, |
| 58299 | // Label 3190: @187152 |
| 58300 | GIM_Try, /*On fail goto*//*Label 3191*/ GIMT_Encode4(187204), // Rule ID 3357 // |
| 58301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58302 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58303 | GIM_CheckHasNoUse, /*MI*/0, |
| 58304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58306 | // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_noret_i32>> => (FLAT_ATOMIC_SMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX), |
| 58308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58309 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58313 | GIR_RootConstrainSelectedInstOperands, |
| 58314 | // GIR_Coverage, 3357, |
| 58315 | GIR_EraseRootFromParent_Done, |
| 58316 | // Label 3191: @187204 |
| 58317 | GIM_Try, /*On fail goto*//*Label 3192*/ GIMT_Encode4(187261), // Rule ID 3296 // |
| 58318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58323 | // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_flat_i32>> => (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN), |
| 58325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58327 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58330 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58331 | GIR_RootConstrainSelectedInstOperands, |
| 58332 | // GIR_Coverage, 3296, |
| 58333 | GIR_EraseRootFromParent_Done, |
| 58334 | // Label 3192: @187261 |
| 58335 | GIM_Try, /*On fail goto*//*Label 3193*/ GIMT_Encode4(187317), // Rule ID 3356 // |
| 58336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58337 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58339 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58341 | // (atomic_load_max:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_max_global_i32>> => (FLAT_ATOMIC_SMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 58342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_RTN), |
| 58343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58345 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58349 | GIR_RootConstrainSelectedInstOperands, |
| 58350 | // GIR_Coverage, 3356, |
| 58351 | GIR_EraseRootFromParent_Done, |
| 58352 | // Label 3193: @187317 |
| 58353 | GIM_Reject, |
| 58354 | // Label 3171: @187318 |
| 58355 | GIM_Reject, |
| 58356 | // Label 3169: @187319 |
| 58357 | GIM_Try, /*On fail goto*//*Label 3194*/ GIMT_Encode4(188564), |
| 58358 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 58359 | GIM_Try, /*On fail goto*//*Label 3195*/ GIMT_Encode4(187389), // Rule ID 5388 // |
| 58360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58361 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58362 | GIM_CheckHasNoUse, /*MI*/0, |
| 58363 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58365 | // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>> => (BUFFER_ATOMIC_SMAX_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64), |
| 58367 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58374 | GIR_RootConstrainSelectedInstOperands, |
| 58375 | // GIR_Coverage, 5388, |
| 58376 | GIR_EraseRootFromParent_Done, |
| 58377 | // Label 3195: @187389 |
| 58378 | GIM_Try, /*On fail goto*//*Label 3196*/ GIMT_Encode4(187448), // Rule ID 5392 // |
| 58379 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58380 | GIM_CheckHasNoUse, /*MI*/0, |
| 58381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58383 | // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64), |
| 58385 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58391 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58392 | GIR_RootConstrainSelectedInstOperands, |
| 58393 | // GIR_Coverage, 5392, |
| 58394 | GIR_EraseRootFromParent_Done, |
| 58395 | // Label 3196: @187448 |
| 58396 | GIM_Try, /*On fail goto*//*Label 3197*/ GIMT_Encode4(187514), // Rule ID 5386 // |
| 58397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58398 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58402 | // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>> => (BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_ADDR64_RTN), |
| 58404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58405 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58411 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58412 | GIR_RootConstrainSelectedInstOperands, |
| 58413 | // GIR_Coverage, 5386, |
| 58414 | GIR_EraseRootFromParent_Done, |
| 58415 | // Label 3197: @187514 |
| 58416 | GIM_Try, /*On fail goto*//*Label 3198*/ GIMT_Encode4(187577), // Rule ID 5390 // |
| 58417 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58419 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58421 | // (atomic_load_max:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_ADDR64_RTN), |
| 58423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58424 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58430 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58431 | GIR_RootConstrainSelectedInstOperands, |
| 58432 | // GIR_Coverage, 5390, |
| 58433 | GIR_EraseRootFromParent_Done, |
| 58434 | // Label 3198: @187577 |
| 58435 | GIM_Try, /*On fail goto*//*Label 3199*/ GIMT_Encode4(187634), // Rule ID 5387 // |
| 58436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58437 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58438 | GIM_CheckHasNoUse, /*MI*/0, |
| 58439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58441 | // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>> => (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET), |
| 58443 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58449 | GIR_RootConstrainSelectedInstOperands, |
| 58450 | // GIR_Coverage, 5387, |
| 58451 | GIR_EraseRootFromParent_Done, |
| 58452 | // Label 3199: @187634 |
| 58453 | GIM_Try, /*On fail goto*//*Label 3200*/ GIMT_Encode4(187688), // Rule ID 5391 // |
| 58454 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58455 | GIM_CheckHasNoUse, /*MI*/0, |
| 58456 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58457 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58458 | // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_noret_i64>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET), |
| 58460 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58466 | GIR_RootConstrainSelectedInstOperands, |
| 58467 | // GIR_Coverage, 5391, |
| 58468 | GIR_EraseRootFromParent_Done, |
| 58469 | // Label 3200: @187688 |
| 58470 | GIM_Try, /*On fail goto*//*Label 3201*/ GIMT_Encode4(187749), // Rule ID 5385 // |
| 58471 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58472 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58474 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58476 | // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>> => (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN), |
| 58478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58479 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58485 | GIR_RootConstrainSelectedInstOperands, |
| 58486 | // GIR_Coverage, 5385, |
| 58487 | GIR_EraseRootFromParent_Done, |
| 58488 | // Label 3201: @187749 |
| 58489 | GIM_Try, /*On fail goto*//*Label 3202*/ GIMT_Encode4(187807), // Rule ID 5389 // |
| 58490 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58492 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58493 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58494 | // (atomic_load_max:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_max_global_i64>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN), |
| 58496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58497 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58502 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58503 | GIR_RootConstrainSelectedInstOperands, |
| 58504 | // GIR_Coverage, 5389, |
| 58505 | GIR_EraseRootFromParent_Done, |
| 58506 | // Label 3202: @187807 |
| 58507 | GIM_Try, /*On fail goto*//*Label 3203*/ GIMT_Encode4(187857), // Rule ID 7920 // |
| 58508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58509 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58510 | GIM_CheckHasNoUse, /*MI*/0, |
| 58511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58513 | // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_noret_i64>> => (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64), |
| 58515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58516 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58519 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58520 | GIR_RootConstrainSelectedInstOperands, |
| 58521 | // GIR_Coverage, 7920, |
| 58522 | GIR_EraseRootFromParent_Done, |
| 58523 | // Label 3203: @187857 |
| 58524 | GIM_Try, /*On fail goto*//*Label 3204*/ GIMT_Encode4(187907), // Rule ID 7922 // |
| 58525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58526 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58527 | GIM_CheckHasNoUse, /*MI*/0, |
| 58528 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58529 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58530 | // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_noret_i64>> => (DS_MAX_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64_gfx9), |
| 58532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58533 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58536 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58537 | GIR_RootConstrainSelectedInstOperands, |
| 58538 | // GIR_Coverage, 7922, |
| 58539 | GIR_EraseRootFromParent_Done, |
| 58540 | // Label 3204: @187907 |
| 58541 | GIM_Try, /*On fail goto*//*Label 3205*/ GIMT_Encode4(187957), // Rule ID 7924 // |
| 58542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 58543 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 58544 | GIM_CheckHasNoUse, /*MI*/0, |
| 58545 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58547 | // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_noret_i64>> => (DS_MAX_I64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 58548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_I64), |
| 58549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58550 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58554 | GIR_RootConstrainSelectedInstOperands, |
| 58555 | // GIR_Coverage, 7924, |
| 58556 | GIR_EraseRootFromParent_Done, |
| 58557 | // Label 3205: @187957 |
| 58558 | GIM_Try, /*On fail goto*//*Label 3206*/ GIMT_Encode4(188011), // Rule ID 7919 // |
| 58559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58560 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58562 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58564 | // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_m0_i64>> => (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64), |
| 58566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58568 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58572 | GIR_RootConstrainSelectedInstOperands, |
| 58573 | // GIR_Coverage, 7919, |
| 58574 | GIR_EraseRootFromParent_Done, |
| 58575 | // Label 3206: @188011 |
| 58576 | GIM_Try, /*On fail goto*//*Label 3207*/ GIMT_Encode4(188065), // Rule ID 7921 // |
| 58577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58578 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58582 | // (atomic_load_max:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_local_i64>> => (DS_MAX_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64_gfx9), |
| 58584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58586 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58590 | GIR_RootConstrainSelectedInstOperands, |
| 58591 | // GIR_Coverage, 7921, |
| 58592 | GIR_EraseRootFromParent_Done, |
| 58593 | // Label 3207: @188065 |
| 58594 | GIM_Try, /*On fail goto*//*Label 3208*/ GIMT_Encode4(188119), // Rule ID 7923 // |
| 58595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 58596 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 58597 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58598 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58600 | // (atomic_load_max_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_max_region_m0_i64>> => (DS_MAX_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 58601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_I64), |
| 58602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58604 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58608 | GIR_RootConstrainSelectedInstOperands, |
| 58609 | // GIR_Coverage, 7923, |
| 58610 | GIR_EraseRootFromParent_Done, |
| 58611 | // Label 3208: @188119 |
| 58612 | GIM_Try, /*On fail goto*//*Label 3209*/ GIMT_Encode4(188176), // Rule ID 3679 // |
| 58613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58614 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58615 | GIM_CheckHasNoUse, /*MI*/0, |
| 58616 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 58618 | // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>> => (GLOBAL_ATOMIC_SMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 58619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR), |
| 58620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 58621 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 58623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58625 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58626 | GIR_RootConstrainSelectedInstOperands, |
| 58627 | // GIR_Coverage, 3679, |
| 58628 | GIR_EraseRootFromParent_Done, |
| 58629 | // Label 3209: @188176 |
| 58630 | GIM_Try, /*On fail goto*//*Label 3210*/ GIMT_Encode4(188237), // Rule ID 3681 // |
| 58631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58632 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 58636 | // (atomic_load_max:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>> => (GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 58637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_SADDR_RTN), |
| 58638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 58640 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 58642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58645 | GIR_RootConstrainSelectedInstOperands, |
| 58646 | // GIR_Coverage, 3681, |
| 58647 | GIR_EraseRootFromParent_Done, |
| 58648 | // Label 3210: @188237 |
| 58649 | GIM_Try, /*On fail goto*//*Label 3211*/ GIMT_Encode4(188289), // Rule ID 3678 // |
| 58650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58651 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58652 | GIM_CheckHasNoUse, /*MI*/0, |
| 58653 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58654 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 58655 | // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>> => (GLOBAL_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2), |
| 58657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58658 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58662 | GIR_RootConstrainSelectedInstOperands, |
| 58663 | // GIR_Coverage, 3678, |
| 58664 | GIR_EraseRootFromParent_Done, |
| 58665 | // Label 3211: @188289 |
| 58666 | GIM_Try, /*On fail goto*//*Label 3212*/ GIMT_Encode4(188345), // Rule ID 3680 // |
| 58667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 58668 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58669 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58670 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58671 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 58672 | // (atomic_load_max:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>> => (GLOBAL_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMAX_X2_RTN), |
| 58674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58676 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58679 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58680 | GIR_RootConstrainSelectedInstOperands, |
| 58681 | // GIR_Coverage, 3680, |
| 58682 | GIR_EraseRootFromParent_Done, |
| 58683 | // Label 3212: @188345 |
| 58684 | GIM_Try, /*On fail goto*//*Label 3213*/ GIMT_Encode4(188398), // Rule ID 3323 // |
| 58685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58686 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58687 | GIM_CheckHasNoUse, /*MI*/0, |
| 58688 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58690 | // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_noret_i64>> => (FLAT_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2), |
| 58692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58693 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58696 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58697 | GIR_RootConstrainSelectedInstOperands, |
| 58698 | // GIR_Coverage, 3323, |
| 58699 | GIR_EraseRootFromParent_Done, |
| 58700 | // Label 3213: @188398 |
| 58701 | GIM_Try, /*On fail goto*//*Label 3214*/ GIMT_Encode4(188450), // Rule ID 3383 // |
| 58702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58703 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58704 | GIM_CheckHasNoUse, /*MI*/0, |
| 58705 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58706 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58707 | // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_noret_i64>> => (FLAT_ATOMIC_SMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2), |
| 58709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58710 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58714 | GIR_RootConstrainSelectedInstOperands, |
| 58715 | // GIR_Coverage, 3383, |
| 58716 | GIR_EraseRootFromParent_Done, |
| 58717 | // Label 3214: @188450 |
| 58718 | GIM_Try, /*On fail goto*//*Label 3215*/ GIMT_Encode4(188507), // Rule ID 3322 // |
| 58719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58720 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58724 | // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_flat_i64>> => (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN), |
| 58726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58728 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58731 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58732 | GIR_RootConstrainSelectedInstOperands, |
| 58733 | // GIR_Coverage, 3322, |
| 58734 | GIR_EraseRootFromParent_Done, |
| 58735 | // Label 3215: @188507 |
| 58736 | GIM_Try, /*On fail goto*//*Label 3216*/ GIMT_Encode4(188563), // Rule ID 3382 // |
| 58737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 58738 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 58740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 58742 | // (atomic_load_max:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_max_global_i64>> => (FLAT_ATOMIC_SMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 58743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMAX_X2_RTN), |
| 58744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 58746 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 58747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58749 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58750 | GIR_RootConstrainSelectedInstOperands, |
| 58751 | // GIR_Coverage, 3382, |
| 58752 | GIR_EraseRootFromParent_Done, |
| 58753 | // Label 3216: @188563 |
| 58754 | GIM_Reject, |
| 58755 | // Label 3194: @188564 |
| 58756 | GIM_Reject, |
| 58757 | // Label 3170: @188565 |
| 58758 | GIM_Reject, |
| 58759 | // Label 25: @188566 |
| 58760 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3219*/ GIMT_Encode4(191077), |
| 58761 | /*GILLT_s32*//*Label 3217*/ GIMT_Encode4(188585), |
| 58762 | /*GILLT_s64*//*Label 3218*/ GIMT_Encode4(189831), |
| 58763 | // Label 3217: @188585 |
| 58764 | GIM_Try, /*On fail goto*//*Label 3220*/ GIMT_Encode4(189830), |
| 58765 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 58766 | GIM_Try, /*On fail goto*//*Label 3221*/ GIMT_Encode4(188655), // Rule ID 5276 // |
| 58767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58768 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58769 | GIM_CheckHasNoUse, /*MI*/0, |
| 58770 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58772 | // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>> => (BUFFER_ATOMIC_SMIN_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64), |
| 58774 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58781 | GIR_RootConstrainSelectedInstOperands, |
| 58782 | // GIR_Coverage, 5276, |
| 58783 | GIR_EraseRootFromParent_Done, |
| 58784 | // Label 3221: @188655 |
| 58785 | GIM_Try, /*On fail goto*//*Label 3222*/ GIMT_Encode4(188714), // Rule ID 5280 // |
| 58786 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58787 | GIM_CheckHasNoUse, /*MI*/0, |
| 58788 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58790 | // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>> => (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64), |
| 58792 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58798 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58799 | GIR_RootConstrainSelectedInstOperands, |
| 58800 | // GIR_Coverage, 5280, |
| 58801 | GIR_EraseRootFromParent_Done, |
| 58802 | // Label 3222: @188714 |
| 58803 | GIM_Try, /*On fail goto*//*Label 3223*/ GIMT_Encode4(188780), // Rule ID 5274 // |
| 58804 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58805 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58807 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58809 | // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>> => (BUFFER_ATOMIC_SMIN_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_ADDR64_RTN), |
| 58811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58812 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58819 | GIR_RootConstrainSelectedInstOperands, |
| 58820 | // GIR_Coverage, 5274, |
| 58821 | GIR_EraseRootFromParent_Done, |
| 58822 | // Label 3223: @188780 |
| 58823 | GIM_Try, /*On fail goto*//*Label 3224*/ GIMT_Encode4(188843), // Rule ID 5278 // |
| 58824 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58826 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 58828 | // (atomic_load_min:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>> => (BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_ADDR64_RTN), |
| 58830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58831 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 58833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 58835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 58836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58838 | GIR_RootConstrainSelectedInstOperands, |
| 58839 | // GIR_Coverage, 5278, |
| 58840 | GIR_EraseRootFromParent_Done, |
| 58841 | // Label 3224: @188843 |
| 58842 | GIM_Try, /*On fail goto*//*Label 3225*/ GIMT_Encode4(188900), // Rule ID 5275 // |
| 58843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58844 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58845 | GIM_CheckHasNoUse, /*MI*/0, |
| 58846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58848 | // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>> => (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET), |
| 58850 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58855 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58856 | GIR_RootConstrainSelectedInstOperands, |
| 58857 | // GIR_Coverage, 5275, |
| 58858 | GIR_EraseRootFromParent_Done, |
| 58859 | // Label 3225: @188900 |
| 58860 | GIM_Try, /*On fail goto*//*Label 3226*/ GIMT_Encode4(188954), // Rule ID 5279 // |
| 58861 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58862 | GIM_CheckHasNoUse, /*MI*/0, |
| 58863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58865 | // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i32>> => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET), |
| 58867 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58873 | GIR_RootConstrainSelectedInstOperands, |
| 58874 | // GIR_Coverage, 5279, |
| 58875 | GIR_EraseRootFromParent_Done, |
| 58876 | // Label 3226: @188954 |
| 58877 | GIM_Try, /*On fail goto*//*Label 3227*/ GIMT_Encode4(189015), // Rule ID 5273 // |
| 58878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 58879 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58881 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58883 | // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>> => (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN), |
| 58885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58886 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58892 | GIR_RootConstrainSelectedInstOperands, |
| 58893 | // GIR_Coverage, 5273, |
| 58894 | GIR_EraseRootFromParent_Done, |
| 58895 | // Label 3227: @189015 |
| 58896 | GIM_Try, /*On fail goto*//*Label 3228*/ GIMT_Encode4(189073), // Rule ID 5277 // |
| 58897 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 58898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58899 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 58901 | // (atomic_load_min:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i32>> => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 58902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN), |
| 58903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 58904 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 58905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 58906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 58907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 58908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58909 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58910 | GIR_RootConstrainSelectedInstOperands, |
| 58911 | // GIR_Coverage, 5277, |
| 58912 | GIR_EraseRootFromParent_Done, |
| 58913 | // Label 3228: @189073 |
| 58914 | GIM_Try, /*On fail goto*//*Label 3229*/ GIMT_Encode4(189123), // Rule ID 7815 // |
| 58915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58916 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58917 | GIM_CheckHasNoUse, /*MI*/0, |
| 58918 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58920 | // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i32>> => (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32), |
| 58922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58923 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58927 | GIR_RootConstrainSelectedInstOperands, |
| 58928 | // GIR_Coverage, 7815, |
| 58929 | GIR_EraseRootFromParent_Done, |
| 58930 | // Label 3229: @189123 |
| 58931 | GIM_Try, /*On fail goto*//*Label 3230*/ GIMT_Encode4(189173), // Rule ID 7817 // |
| 58932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58933 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58934 | GIM_CheckHasNoUse, /*MI*/0, |
| 58935 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58937 | // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_noret_i32>> => (DS_MIN_I32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32_gfx9), |
| 58939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58940 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58944 | GIR_RootConstrainSelectedInstOperands, |
| 58945 | // GIR_Coverage, 7817, |
| 58946 | GIR_EraseRootFromParent_Done, |
| 58947 | // Label 3230: @189173 |
| 58948 | GIM_Try, /*On fail goto*//*Label 3231*/ GIMT_Encode4(189223), // Rule ID 7819 // |
| 58949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 58950 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 58951 | GIM_CheckHasNoUse, /*MI*/0, |
| 58952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58954 | // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i32>> => (DS_MIN_I32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 58955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I32), |
| 58956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58957 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 58960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58961 | GIR_RootConstrainSelectedInstOperands, |
| 58962 | // GIR_Coverage, 7819, |
| 58963 | GIR_EraseRootFromParent_Done, |
| 58964 | // Label 3231: @189223 |
| 58965 | GIM_Try, /*On fail goto*//*Label 3232*/ GIMT_Encode4(189277), // Rule ID 7814 // |
| 58966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 58967 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58971 | // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_m0_i32>> => (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32), |
| 58973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58975 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58978 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58979 | GIR_RootConstrainSelectedInstOperands, |
| 58980 | // GIR_Coverage, 7814, |
| 58981 | GIR_EraseRootFromParent_Done, |
| 58982 | // Label 3232: @189277 |
| 58983 | GIM_Try, /*On fail goto*//*Label 3233*/ GIMT_Encode4(189331), // Rule ID 7816 // |
| 58984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 58985 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 58986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 58987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 58988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 58989 | // (atomic_load_min:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_local_i32>> => (DS_MIN_RTN_I32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 58990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32_gfx9), |
| 58991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 58992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 58993 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 58994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 58995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 58996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 58997 | GIR_RootConstrainSelectedInstOperands, |
| 58998 | // GIR_Coverage, 7816, |
| 58999 | GIR_EraseRootFromParent_Done, |
| 59000 | // Label 3233: @189331 |
| 59001 | GIM_Try, /*On fail goto*//*Label 3234*/ GIMT_Encode4(189385), // Rule ID 7818 // |
| 59002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 59003 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 59004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59005 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59007 | // (atomic_load_min_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_min_region_m0_i32>> => (DS_MIN_RTN_I32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 59008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I32), |
| 59009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59011 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59014 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59015 | GIR_RootConstrainSelectedInstOperands, |
| 59016 | // GIR_Coverage, 7818, |
| 59017 | GIR_EraseRootFromParent_Done, |
| 59018 | // Label 3234: @189385 |
| 59019 | GIM_Try, /*On fail goto*//*Label 3235*/ GIMT_Encode4(189442), // Rule ID 3631 // |
| 59020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59021 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59022 | GIM_CheckHasNoUse, /*MI*/0, |
| 59023 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59024 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59025 | // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>> => (GLOBAL_ATOMIC_SMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR), |
| 59027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59028 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59033 | GIR_RootConstrainSelectedInstOperands, |
| 59034 | // GIR_Coverage, 3631, |
| 59035 | GIR_EraseRootFromParent_Done, |
| 59036 | // Label 3235: @189442 |
| 59037 | GIM_Try, /*On fail goto*//*Label 3236*/ GIMT_Encode4(189503), // Rule ID 3633 // |
| 59038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59039 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59041 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59043 | // (atomic_load_min:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>> => (GLOBAL_ATOMIC_SMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_SADDR_RTN), |
| 59045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59047 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59052 | GIR_RootConstrainSelectedInstOperands, |
| 59053 | // GIR_Coverage, 3633, |
| 59054 | GIR_EraseRootFromParent_Done, |
| 59055 | // Label 3236: @189503 |
| 59056 | GIM_Try, /*On fail goto*//*Label 3237*/ GIMT_Encode4(189555), // Rule ID 3630 // |
| 59057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59058 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59059 | GIM_CheckHasNoUse, /*MI*/0, |
| 59060 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59061 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59062 | // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>> => (GLOBAL_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN), |
| 59064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59065 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59068 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59069 | GIR_RootConstrainSelectedInstOperands, |
| 59070 | // GIR_Coverage, 3630, |
| 59071 | GIR_EraseRootFromParent_Done, |
| 59072 | // Label 3237: @189555 |
| 59073 | GIM_Try, /*On fail goto*//*Label 3238*/ GIMT_Encode4(189611), // Rule ID 3632 // |
| 59074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59075 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59077 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59079 | // (atomic_load_min:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>> => (GLOBAL_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_RTN), |
| 59081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59083 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59085 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59086 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59087 | GIR_RootConstrainSelectedInstOperands, |
| 59088 | // GIR_Coverage, 3632, |
| 59089 | GIR_EraseRootFromParent_Done, |
| 59090 | // Label 3238: @189611 |
| 59091 | GIM_Try, /*On fail goto*//*Label 3239*/ GIMT_Encode4(189664), // Rule ID 3301 // |
| 59092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59093 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59094 | GIM_CheckHasNoUse, /*MI*/0, |
| 59095 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59096 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59097 | // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i32>> => (FLAT_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN), |
| 59099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59100 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59103 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59104 | GIR_RootConstrainSelectedInstOperands, |
| 59105 | // GIR_Coverage, 3301, |
| 59106 | GIR_EraseRootFromParent_Done, |
| 59107 | // Label 3239: @189664 |
| 59108 | GIM_Try, /*On fail goto*//*Label 3240*/ GIMT_Encode4(189716), // Rule ID 3361 // |
| 59109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59110 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59111 | GIM_CheckHasNoUse, /*MI*/0, |
| 59112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59114 | // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_noret_i32>> => (FLAT_ATOMIC_SMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN), |
| 59116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59117 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59121 | GIR_RootConstrainSelectedInstOperands, |
| 59122 | // GIR_Coverage, 3361, |
| 59123 | GIR_EraseRootFromParent_Done, |
| 59124 | // Label 3240: @189716 |
| 59125 | GIM_Try, /*On fail goto*//*Label 3241*/ GIMT_Encode4(189773), // Rule ID 3300 // |
| 59126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59127 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59131 | // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_flat_i32>> => (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN), |
| 59133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59135 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59139 | GIR_RootConstrainSelectedInstOperands, |
| 59140 | // GIR_Coverage, 3300, |
| 59141 | GIR_EraseRootFromParent_Done, |
| 59142 | // Label 3241: @189773 |
| 59143 | GIM_Try, /*On fail goto*//*Label 3242*/ GIMT_Encode4(189829), // Rule ID 3360 // |
| 59144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59145 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59147 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59149 | // (atomic_load_min:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_min_global_i32>> => (FLAT_ATOMIC_SMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_RTN), |
| 59151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59153 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59156 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59157 | GIR_RootConstrainSelectedInstOperands, |
| 59158 | // GIR_Coverage, 3360, |
| 59159 | GIR_EraseRootFromParent_Done, |
| 59160 | // Label 3242: @189829 |
| 59161 | GIM_Reject, |
| 59162 | // Label 3220: @189830 |
| 59163 | GIM_Reject, |
| 59164 | // Label 3218: @189831 |
| 59165 | GIM_Try, /*On fail goto*//*Label 3243*/ GIMT_Encode4(191076), |
| 59166 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 59167 | GIM_Try, /*On fail goto*//*Label 3244*/ GIMT_Encode4(189901), // Rule ID 5372 // |
| 59168 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59169 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59170 | GIM_CheckHasNoUse, /*MI*/0, |
| 59171 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59173 | // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>> => (BUFFER_ATOMIC_SMIN_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64), |
| 59175 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59181 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59182 | GIR_RootConstrainSelectedInstOperands, |
| 59183 | // GIR_Coverage, 5372, |
| 59184 | GIR_EraseRootFromParent_Done, |
| 59185 | // Label 3244: @189901 |
| 59186 | GIM_Try, /*On fail goto*//*Label 3245*/ GIMT_Encode4(189960), // Rule ID 5376 // |
| 59187 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59188 | GIM_CheckHasNoUse, /*MI*/0, |
| 59189 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59190 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59191 | // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59192 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64), |
| 59193 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59199 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59200 | GIR_RootConstrainSelectedInstOperands, |
| 59201 | // GIR_Coverage, 5376, |
| 59202 | GIR_EraseRootFromParent_Done, |
| 59203 | // Label 3245: @189960 |
| 59204 | GIM_Try, /*On fail goto*//*Label 3246*/ GIMT_Encode4(190026), // Rule ID 5370 // |
| 59205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59206 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59208 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59210 | // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>> => (BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_ADDR64_RTN), |
| 59212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59213 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59220 | GIR_RootConstrainSelectedInstOperands, |
| 59221 | // GIR_Coverage, 5370, |
| 59222 | GIR_EraseRootFromParent_Done, |
| 59223 | // Label 3246: @190026 |
| 59224 | GIM_Try, /*On fail goto*//*Label 3247*/ GIMT_Encode4(190089), // Rule ID 5374 // |
| 59225 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59229 | // (atomic_load_min:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_ADDR64_RTN), |
| 59231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59232 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59239 | GIR_RootConstrainSelectedInstOperands, |
| 59240 | // GIR_Coverage, 5374, |
| 59241 | GIR_EraseRootFromParent_Done, |
| 59242 | // Label 3247: @190089 |
| 59243 | GIM_Try, /*On fail goto*//*Label 3248*/ GIMT_Encode4(190146), // Rule ID 5371 // |
| 59244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59246 | GIM_CheckHasNoUse, /*MI*/0, |
| 59247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59249 | // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>> => (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET), |
| 59251 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59257 | GIR_RootConstrainSelectedInstOperands, |
| 59258 | // GIR_Coverage, 5371, |
| 59259 | GIR_EraseRootFromParent_Done, |
| 59260 | // Label 3248: @190146 |
| 59261 | GIM_Try, /*On fail goto*//*Label 3249*/ GIMT_Encode4(190200), // Rule ID 5375 // |
| 59262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59263 | GIM_CheckHasNoUse, /*MI*/0, |
| 59264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59266 | // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_noret_i64>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET), |
| 59268 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59274 | GIR_RootConstrainSelectedInstOperands, |
| 59275 | // GIR_Coverage, 5375, |
| 59276 | GIR_EraseRootFromParent_Done, |
| 59277 | // Label 3249: @190200 |
| 59278 | GIM_Try, /*On fail goto*//*Label 3250*/ GIMT_Encode4(190261), // Rule ID 5369 // |
| 59279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59280 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59284 | // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>> => (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN), |
| 59286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59287 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59292 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59293 | GIR_RootConstrainSelectedInstOperands, |
| 59294 | // GIR_Coverage, 5369, |
| 59295 | GIR_EraseRootFromParent_Done, |
| 59296 | // Label 3250: @190261 |
| 59297 | GIM_Try, /*On fail goto*//*Label 3251*/ GIMT_Encode4(190319), // Rule ID 5373 // |
| 59298 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59302 | // (atomic_load_min:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_min_global_i64>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN), |
| 59304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59305 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59310 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59311 | GIR_RootConstrainSelectedInstOperands, |
| 59312 | // GIR_Coverage, 5373, |
| 59313 | GIR_EraseRootFromParent_Done, |
| 59314 | // Label 3251: @190319 |
| 59315 | GIM_Try, /*On fail goto*//*Label 3252*/ GIMT_Encode4(190369), // Rule ID 7914 // |
| 59316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 59317 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59318 | GIM_CheckHasNoUse, /*MI*/0, |
| 59319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59321 | // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_noret_i64>> => (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64), |
| 59323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59324 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59327 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59328 | GIR_RootConstrainSelectedInstOperands, |
| 59329 | // GIR_Coverage, 7914, |
| 59330 | GIR_EraseRootFromParent_Done, |
| 59331 | // Label 3252: @190369 |
| 59332 | GIM_Try, /*On fail goto*//*Label 3253*/ GIMT_Encode4(190419), // Rule ID 7916 // |
| 59333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 59334 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59335 | GIM_CheckHasNoUse, /*MI*/0, |
| 59336 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59338 | // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_noret_i64>> => (DS_MIN_I64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64_gfx9), |
| 59340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59341 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59345 | GIR_RootConstrainSelectedInstOperands, |
| 59346 | // GIR_Coverage, 7916, |
| 59347 | GIR_EraseRootFromParent_Done, |
| 59348 | // Label 3253: @190419 |
| 59349 | GIM_Try, /*On fail goto*//*Label 3254*/ GIMT_Encode4(190469), // Rule ID 7918 // |
| 59350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 59351 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 59352 | GIM_CheckHasNoUse, /*MI*/0, |
| 59353 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59355 | // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_noret_i64>> => (DS_MIN_I64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 59356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_I64), |
| 59357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59358 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59362 | GIR_RootConstrainSelectedInstOperands, |
| 59363 | // GIR_Coverage, 7918, |
| 59364 | GIR_EraseRootFromParent_Done, |
| 59365 | // Label 3254: @190469 |
| 59366 | GIM_Try, /*On fail goto*//*Label 3255*/ GIMT_Encode4(190523), // Rule ID 7913 // |
| 59367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 59368 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59370 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59372 | // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_m0_i64>> => (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59373 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64), |
| 59374 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59376 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59379 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59380 | GIR_RootConstrainSelectedInstOperands, |
| 59381 | // GIR_Coverage, 7913, |
| 59382 | GIR_EraseRootFromParent_Done, |
| 59383 | // Label 3255: @190523 |
| 59384 | GIM_Try, /*On fail goto*//*Label 3256*/ GIMT_Encode4(190577), // Rule ID 7915 // |
| 59385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 59386 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59387 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59388 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59390 | // (atomic_load_min:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_local_i64>> => (DS_MIN_RTN_I64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64_gfx9), |
| 59392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59394 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59398 | GIR_RootConstrainSelectedInstOperands, |
| 59399 | // GIR_Coverage, 7915, |
| 59400 | GIR_EraseRootFromParent_Done, |
| 59401 | // Label 3256: @190577 |
| 59402 | GIM_Try, /*On fail goto*//*Label 3257*/ GIMT_Encode4(190631), // Rule ID 7917 // |
| 59403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 59404 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 59405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59406 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59408 | // (atomic_load_min_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_min_region_m0_i64>> => (DS_MIN_RTN_I64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 59409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_I64), |
| 59410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59412 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59415 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59416 | GIR_RootConstrainSelectedInstOperands, |
| 59417 | // GIR_Coverage, 7917, |
| 59418 | GIR_EraseRootFromParent_Done, |
| 59419 | // Label 3257: @190631 |
| 59420 | GIM_Try, /*On fail goto*//*Label 3258*/ GIMT_Encode4(190688), // Rule ID 3687 // |
| 59421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59422 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59423 | GIM_CheckHasNoUse, /*MI*/0, |
| 59424 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59426 | // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>> => (GLOBAL_ATOMIC_SMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR), |
| 59428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59429 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59433 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59434 | GIR_RootConstrainSelectedInstOperands, |
| 59435 | // GIR_Coverage, 3687, |
| 59436 | GIR_EraseRootFromParent_Done, |
| 59437 | // Label 3258: @190688 |
| 59438 | GIM_Try, /*On fail goto*//*Label 3259*/ GIMT_Encode4(190749), // Rule ID 3689 // |
| 59439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59440 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59443 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59444 | // (atomic_load_min:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>> => (GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_SADDR_RTN), |
| 59446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59448 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59453 | GIR_RootConstrainSelectedInstOperands, |
| 59454 | // GIR_Coverage, 3689, |
| 59455 | GIR_EraseRootFromParent_Done, |
| 59456 | // Label 3259: @190749 |
| 59457 | GIM_Try, /*On fail goto*//*Label 3260*/ GIMT_Encode4(190801), // Rule ID 3686 // |
| 59458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59459 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59460 | GIM_CheckHasNoUse, /*MI*/0, |
| 59461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59463 | // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>> => (GLOBAL_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2), |
| 59465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59466 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59470 | GIR_RootConstrainSelectedInstOperands, |
| 59471 | // GIR_Coverage, 3686, |
| 59472 | GIR_EraseRootFromParent_Done, |
| 59473 | // Label 3260: @190801 |
| 59474 | GIM_Try, /*On fail goto*//*Label 3261*/ GIMT_Encode4(190857), // Rule ID 3688 // |
| 59475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59476 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59478 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59479 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59480 | // (atomic_load_min:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>> => (GLOBAL_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_SMIN_X2_RTN), |
| 59482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59484 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59488 | GIR_RootConstrainSelectedInstOperands, |
| 59489 | // GIR_Coverage, 3688, |
| 59490 | GIR_EraseRootFromParent_Done, |
| 59491 | // Label 3261: @190857 |
| 59492 | GIM_Try, /*On fail goto*//*Label 3262*/ GIMT_Encode4(190910), // Rule ID 3327 // |
| 59493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59494 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59495 | GIM_CheckHasNoUse, /*MI*/0, |
| 59496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59498 | // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_noret_i64>> => (FLAT_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2), |
| 59500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59501 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59505 | GIR_RootConstrainSelectedInstOperands, |
| 59506 | // GIR_Coverage, 3327, |
| 59507 | GIR_EraseRootFromParent_Done, |
| 59508 | // Label 3262: @190910 |
| 59509 | GIM_Try, /*On fail goto*//*Label 3263*/ GIMT_Encode4(190962), // Rule ID 3387 // |
| 59510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59511 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59512 | GIM_CheckHasNoUse, /*MI*/0, |
| 59513 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59515 | // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_noret_i64>> => (FLAT_ATOMIC_SMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2), |
| 59517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59518 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59522 | GIR_RootConstrainSelectedInstOperands, |
| 59523 | // GIR_Coverage, 3387, |
| 59524 | GIR_EraseRootFromParent_Done, |
| 59525 | // Label 3263: @190962 |
| 59526 | GIM_Try, /*On fail goto*//*Label 3264*/ GIMT_Encode4(191019), // Rule ID 3326 // |
| 59527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59528 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59532 | // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_flat_i64>> => (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN), |
| 59534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59536 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59539 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59540 | GIR_RootConstrainSelectedInstOperands, |
| 59541 | // GIR_Coverage, 3326, |
| 59542 | GIR_EraseRootFromParent_Done, |
| 59543 | // Label 3264: @191019 |
| 59544 | GIM_Try, /*On fail goto*//*Label 3265*/ GIMT_Encode4(191075), // Rule ID 3386 // |
| 59545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59546 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 59548 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59550 | // (atomic_load_min:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_min_global_i64>> => (FLAT_ATOMIC_SMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 59551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_SMIN_X2_RTN), |
| 59552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59554 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59557 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59558 | GIR_RootConstrainSelectedInstOperands, |
| 59559 | // GIR_Coverage, 3386, |
| 59560 | GIR_EraseRootFromParent_Done, |
| 59561 | // Label 3265: @191075 |
| 59562 | GIM_Reject, |
| 59563 | // Label 3243: @191076 |
| 59564 | GIM_Reject, |
| 59565 | // Label 3219: @191077 |
| 59566 | GIM_Reject, |
| 59567 | // Label 26: @191078 |
| 59568 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3268*/ GIMT_Encode4(193589), |
| 59569 | /*GILLT_s32*//*Label 3266*/ GIMT_Encode4(191097), |
| 59570 | /*GILLT_s64*//*Label 3267*/ GIMT_Encode4(192343), |
| 59571 | // Label 3266: @191097 |
| 59572 | GIM_Try, /*On fail goto*//*Label 3269*/ GIMT_Encode4(192342), |
| 59573 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 59574 | GIM_Try, /*On fail goto*//*Label 3270*/ GIMT_Encode4(191167), // Rule ID 5300 // |
| 59575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59576 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59577 | GIM_CheckHasNoUse, /*MI*/0, |
| 59578 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59580 | // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (BUFFER_ATOMIC_UMAX_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64), |
| 59582 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59588 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59589 | GIR_RootConstrainSelectedInstOperands, |
| 59590 | // GIR_Coverage, 5300, |
| 59591 | GIR_EraseRootFromParent_Done, |
| 59592 | // Label 3270: @191167 |
| 59593 | GIM_Try, /*On fail goto*//*Label 3271*/ GIMT_Encode4(191226), // Rule ID 5304 // |
| 59594 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59595 | GIM_CheckHasNoUse, /*MI*/0, |
| 59596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59598 | // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64), |
| 59600 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59607 | GIR_RootConstrainSelectedInstOperands, |
| 59608 | // GIR_Coverage, 5304, |
| 59609 | GIR_EraseRootFromParent_Done, |
| 59610 | // Label 3271: @191226 |
| 59611 | GIM_Try, /*On fail goto*//*Label 3272*/ GIMT_Encode4(191292), // Rule ID 5298 // |
| 59612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59613 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59617 | // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>> => (BUFFER_ATOMIC_UMAX_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_ADDR64_RTN), |
| 59619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59620 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59627 | GIR_RootConstrainSelectedInstOperands, |
| 59628 | // GIR_Coverage, 5298, |
| 59629 | GIR_EraseRootFromParent_Done, |
| 59630 | // Label 3272: @191292 |
| 59631 | GIM_Try, /*On fail goto*//*Label 3273*/ GIMT_Encode4(191355), // Rule ID 5302 // |
| 59632 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59634 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59636 | // (atomic_load_umax:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>> => (BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_ADDR64_RTN), |
| 59638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59639 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59646 | GIR_RootConstrainSelectedInstOperands, |
| 59647 | // GIR_Coverage, 5302, |
| 59648 | GIR_EraseRootFromParent_Done, |
| 59649 | // Label 3273: @191355 |
| 59650 | GIM_Try, /*On fail goto*//*Label 3274*/ GIMT_Encode4(191412), // Rule ID 5299 // |
| 59651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59652 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59653 | GIM_CheckHasNoUse, /*MI*/0, |
| 59654 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59656 | // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET), |
| 59658 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59663 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59664 | GIR_RootConstrainSelectedInstOperands, |
| 59665 | // GIR_Coverage, 5299, |
| 59666 | GIR_EraseRootFromParent_Done, |
| 59667 | // Label 3274: @191412 |
| 59668 | GIM_Try, /*On fail goto*//*Label 3275*/ GIMT_Encode4(191466), // Rule ID 5303 // |
| 59669 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59670 | GIM_CheckHasNoUse, /*MI*/0, |
| 59671 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59673 | // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET), |
| 59675 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59680 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59681 | GIR_RootConstrainSelectedInstOperands, |
| 59682 | // GIR_Coverage, 5303, |
| 59683 | GIR_EraseRootFromParent_Done, |
| 59684 | // Label 3275: @191466 |
| 59685 | GIM_Try, /*On fail goto*//*Label 3276*/ GIMT_Encode4(191527), // Rule ID 5297 // |
| 59686 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59687 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59689 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59690 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59691 | // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>> => (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN), |
| 59693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59694 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59699 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59700 | GIR_RootConstrainSelectedInstOperands, |
| 59701 | // GIR_Coverage, 5297, |
| 59702 | GIR_EraseRootFromParent_Done, |
| 59703 | // Label 3276: @191527 |
| 59704 | GIM_Try, /*On fail goto*//*Label 3277*/ GIMT_Encode4(191585), // Rule ID 5301 // |
| 59705 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59707 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 59709 | // (atomic_load_umax:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i32>> => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN), |
| 59711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 59712 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 59715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59717 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59718 | GIR_RootConstrainSelectedInstOperands, |
| 59719 | // GIR_Coverage, 5301, |
| 59720 | GIR_EraseRootFromParent_Done, |
| 59721 | // Label 3277: @191585 |
| 59722 | GIM_Try, /*On fail goto*//*Label 3278*/ GIMT_Encode4(191635), // Rule ID 7833 // |
| 59723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 59724 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59725 | GIM_CheckHasNoUse, /*MI*/0, |
| 59726 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59727 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59728 | // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i32>> => (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32), |
| 59730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59731 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59734 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59735 | GIR_RootConstrainSelectedInstOperands, |
| 59736 | // GIR_Coverage, 7833, |
| 59737 | GIR_EraseRootFromParent_Done, |
| 59738 | // Label 3278: @191635 |
| 59739 | GIM_Try, /*On fail goto*//*Label 3279*/ GIMT_Encode4(191685), // Rule ID 7835 // |
| 59740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 59741 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59742 | GIM_CheckHasNoUse, /*MI*/0, |
| 59743 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59745 | // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i32>> => (DS_MAX_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32_gfx9), |
| 59747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59748 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59751 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59752 | GIR_RootConstrainSelectedInstOperands, |
| 59753 | // GIR_Coverage, 7835, |
| 59754 | GIR_EraseRootFromParent_Done, |
| 59755 | // Label 3279: @191685 |
| 59756 | GIM_Try, /*On fail goto*//*Label 3280*/ GIMT_Encode4(191735), // Rule ID 7837 // |
| 59757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 59758 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 59759 | GIM_CheckHasNoUse, /*MI*/0, |
| 59760 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59761 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59762 | // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i32>> => (DS_MAX_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 59763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U32), |
| 59764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59765 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59769 | GIR_RootConstrainSelectedInstOperands, |
| 59770 | // GIR_Coverage, 7837, |
| 59771 | GIR_EraseRootFromParent_Done, |
| 59772 | // Label 3280: @191735 |
| 59773 | GIM_Try, /*On fail goto*//*Label 3281*/ GIMT_Encode4(191789), // Rule ID 7832 // |
| 59774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 59775 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59776 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59777 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59778 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59779 | // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i32>> => (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32), |
| 59781 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59783 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59786 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59787 | GIR_RootConstrainSelectedInstOperands, |
| 59788 | // GIR_Coverage, 7832, |
| 59789 | GIR_EraseRootFromParent_Done, |
| 59790 | // Label 3281: @191789 |
| 59791 | GIM_Try, /*On fail goto*//*Label 3282*/ GIMT_Encode4(191843), // Rule ID 7834 // |
| 59792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 59793 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 59794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59797 | // (atomic_load_umax:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_local_i32>> => (DS_MAX_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 59798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32_gfx9), |
| 59799 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59801 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59804 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59805 | GIR_RootConstrainSelectedInstOperands, |
| 59806 | // GIR_Coverage, 7834, |
| 59807 | GIR_EraseRootFromParent_Done, |
| 59808 | // Label 3282: @191843 |
| 59809 | GIM_Try, /*On fail goto*//*Label 3283*/ GIMT_Encode4(191897), // Rule ID 7836 // |
| 59810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 59811 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 59812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59813 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 59815 | // (atomic_load_umax_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i32>> => (DS_MAX_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 59816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U32), |
| 59817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 59819 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 59820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59823 | GIR_RootConstrainSelectedInstOperands, |
| 59824 | // GIR_Coverage, 7836, |
| 59825 | GIR_EraseRootFromParent_Done, |
| 59826 | // Label 3283: @191897 |
| 59827 | GIM_Try, /*On fail goto*//*Label 3284*/ GIMT_Encode4(191954), // Rule ID 3627 // |
| 59828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59829 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59830 | GIM_CheckHasNoUse, /*MI*/0, |
| 59831 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59833 | // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (GLOBAL_ATOMIC_UMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR), |
| 59835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59836 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59841 | GIR_RootConstrainSelectedInstOperands, |
| 59842 | // GIR_Coverage, 3627, |
| 59843 | GIR_EraseRootFromParent_Done, |
| 59844 | // Label 3284: @191954 |
| 59845 | GIM_Try, /*On fail goto*//*Label 3285*/ GIMT_Encode4(192015), // Rule ID 3629 // |
| 59846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59847 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59849 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59850 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 59851 | // (atomic_load_umax:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>> => (GLOBAL_ATOMIC_UMAX_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 59852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_SADDR_RTN), |
| 59853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 59855 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 59857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 59858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59859 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59860 | GIR_RootConstrainSelectedInstOperands, |
| 59861 | // GIR_Coverage, 3629, |
| 59862 | GIR_EraseRootFromParent_Done, |
| 59863 | // Label 3285: @192015 |
| 59864 | GIM_Try, /*On fail goto*//*Label 3286*/ GIMT_Encode4(192067), // Rule ID 3626 // |
| 59865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59866 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59867 | GIM_CheckHasNoUse, /*MI*/0, |
| 59868 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59870 | // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (GLOBAL_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX), |
| 59872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59873 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59877 | GIR_RootConstrainSelectedInstOperands, |
| 59878 | // GIR_Coverage, 3626, |
| 59879 | GIR_EraseRootFromParent_Done, |
| 59880 | // Label 3286: @192067 |
| 59881 | GIM_Try, /*On fail goto*//*Label 3287*/ GIMT_Encode4(192123), // Rule ID 3628 // |
| 59882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 59883 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59884 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59885 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 59887 | // (atomic_load_umax:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>> => (GLOBAL_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_RTN), |
| 59889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59891 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59895 | GIR_RootConstrainSelectedInstOperands, |
| 59896 | // GIR_Coverage, 3628, |
| 59897 | GIR_EraseRootFromParent_Done, |
| 59898 | // Label 3287: @192123 |
| 59899 | GIM_Try, /*On fail goto*//*Label 3288*/ GIMT_Encode4(192176), // Rule ID 3299 // |
| 59900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59901 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59902 | GIM_CheckHasNoUse, /*MI*/0, |
| 59903 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59905 | // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i32>> => (FLAT_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX), |
| 59907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59908 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59912 | GIR_RootConstrainSelectedInstOperands, |
| 59913 | // GIR_Coverage, 3299, |
| 59914 | GIR_EraseRootFromParent_Done, |
| 59915 | // Label 3288: @192176 |
| 59916 | GIM_Try, /*On fail goto*//*Label 3289*/ GIMT_Encode4(192228), // Rule ID 3359 // |
| 59917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59918 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59919 | GIM_CheckHasNoUse, /*MI*/0, |
| 59920 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59921 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59922 | // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i32>> => (FLAT_ATOMIC_UMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX), |
| 59924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59925 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59929 | GIR_RootConstrainSelectedInstOperands, |
| 59930 | // GIR_Coverage, 3359, |
| 59931 | GIR_EraseRootFromParent_Done, |
| 59932 | // Label 3289: @192228 |
| 59933 | GIM_Try, /*On fail goto*//*Label 3290*/ GIMT_Encode4(192285), // Rule ID 3298 // |
| 59934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59935 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59939 | // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_flat_i32>> => (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN), |
| 59941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59943 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59947 | GIR_RootConstrainSelectedInstOperands, |
| 59948 | // GIR_Coverage, 3298, |
| 59949 | GIR_EraseRootFromParent_Done, |
| 59950 | // Label 3290: @192285 |
| 59951 | GIM_Try, /*On fail goto*//*Label 3291*/ GIMT_Encode4(192341), // Rule ID 3358 // |
| 59952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 59953 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 59955 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 59957 | // (atomic_load_umax:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umax_global_i32>> => (FLAT_ATOMIC_UMAX_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 59958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_RTN), |
| 59959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 59960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 59961 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 59962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 59963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 59964 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59965 | GIR_RootConstrainSelectedInstOperands, |
| 59966 | // GIR_Coverage, 3358, |
| 59967 | GIR_EraseRootFromParent_Done, |
| 59968 | // Label 3291: @192341 |
| 59969 | GIM_Reject, |
| 59970 | // Label 3269: @192342 |
| 59971 | GIM_Reject, |
| 59972 | // Label 3267: @192343 |
| 59973 | GIM_Try, /*On fail goto*//*Label 3292*/ GIMT_Encode4(193588), |
| 59974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 59975 | GIM_Try, /*On fail goto*//*Label 3293*/ GIMT_Encode4(192413), // Rule ID 5396 // |
| 59976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 59977 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59978 | GIM_CheckHasNoUse, /*MI*/0, |
| 59979 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59980 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59981 | // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (BUFFER_ATOMIC_UMAX_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 59982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64), |
| 59983 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 59984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 59985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 59986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 59987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 59988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 59989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 59990 | GIR_RootConstrainSelectedInstOperands, |
| 59991 | // GIR_Coverage, 5396, |
| 59992 | GIR_EraseRootFromParent_Done, |
| 59993 | // Label 3293: @192413 |
| 59994 | GIM_Try, /*On fail goto*//*Label 3294*/ GIMT_Encode4(192472), // Rule ID 5400 // |
| 59995 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 59996 | GIM_CheckHasNoUse, /*MI*/0, |
| 59997 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 59998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 59999 | // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64), |
| 60001 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60007 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60008 | GIR_RootConstrainSelectedInstOperands, |
| 60009 | // GIR_Coverage, 5400, |
| 60010 | GIR_EraseRootFromParent_Done, |
| 60011 | // Label 3294: @192472 |
| 60012 | GIM_Try, /*On fail goto*//*Label 3295*/ GIMT_Encode4(192538), // Rule ID 5394 // |
| 60013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60014 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60016 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60017 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60018 | // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>> => (BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_ADDR64_RTN), |
| 60020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60021 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60027 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60028 | GIR_RootConstrainSelectedInstOperands, |
| 60029 | // GIR_Coverage, 5394, |
| 60030 | GIR_EraseRootFromParent_Done, |
| 60031 | // Label 3295: @192538 |
| 60032 | GIM_Try, /*On fail goto*//*Label 3296*/ GIMT_Encode4(192601), // Rule ID 5398 // |
| 60033 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60035 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60036 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60037 | // (atomic_load_umax:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_ADDR64_RTN), |
| 60039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60040 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60046 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60047 | GIR_RootConstrainSelectedInstOperands, |
| 60048 | // GIR_Coverage, 5398, |
| 60049 | GIR_EraseRootFromParent_Done, |
| 60050 | // Label 3296: @192601 |
| 60051 | GIM_Try, /*On fail goto*//*Label 3297*/ GIMT_Encode4(192658), // Rule ID 5395 // |
| 60052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60053 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60054 | GIM_CheckHasNoUse, /*MI*/0, |
| 60055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60057 | // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET), |
| 60059 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60065 | GIR_RootConstrainSelectedInstOperands, |
| 60066 | // GIR_Coverage, 5395, |
| 60067 | GIR_EraseRootFromParent_Done, |
| 60068 | // Label 3297: @192658 |
| 60069 | GIM_Try, /*On fail goto*//*Label 3298*/ GIMT_Encode4(192712), // Rule ID 5399 // |
| 60070 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60071 | GIM_CheckHasNoUse, /*MI*/0, |
| 60072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60074 | // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET), |
| 60076 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60081 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60082 | GIR_RootConstrainSelectedInstOperands, |
| 60083 | // GIR_Coverage, 5399, |
| 60084 | GIR_EraseRootFromParent_Done, |
| 60085 | // Label 3298: @192712 |
| 60086 | GIM_Try, /*On fail goto*//*Label 3299*/ GIMT_Encode4(192773), // Rule ID 5393 // |
| 60087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60088 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60090 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60092 | // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>> => (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN), |
| 60094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60095 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60100 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60101 | GIR_RootConstrainSelectedInstOperands, |
| 60102 | // GIR_Coverage, 5393, |
| 60103 | GIR_EraseRootFromParent_Done, |
| 60104 | // Label 3299: @192773 |
| 60105 | GIM_Try, /*On fail goto*//*Label 3300*/ GIMT_Encode4(192831), // Rule ID 5397 // |
| 60106 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60108 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60110 | // (atomic_load_umax:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umax_global_i64>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN), |
| 60112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60113 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60119 | GIR_RootConstrainSelectedInstOperands, |
| 60120 | // GIR_Coverage, 5397, |
| 60121 | GIR_EraseRootFromParent_Done, |
| 60122 | // Label 3300: @192831 |
| 60123 | GIM_Try, /*On fail goto*//*Label 3301*/ GIMT_Encode4(192881), // Rule ID 7932 // |
| 60124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60125 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60126 | GIM_CheckHasNoUse, /*MI*/0, |
| 60127 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60128 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60129 | // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_noret_i64>> => (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64), |
| 60131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60132 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60136 | GIR_RootConstrainSelectedInstOperands, |
| 60137 | // GIR_Coverage, 7932, |
| 60138 | GIR_EraseRootFromParent_Done, |
| 60139 | // Label 3301: @192881 |
| 60140 | GIM_Try, /*On fail goto*//*Label 3302*/ GIMT_Encode4(192931), // Rule ID 7934 // |
| 60141 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 60142 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60143 | GIM_CheckHasNoUse, /*MI*/0, |
| 60144 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60146 | // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_noret_i64>> => (DS_MAX_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64_gfx9), |
| 60148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60149 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60153 | GIR_RootConstrainSelectedInstOperands, |
| 60154 | // GIR_Coverage, 7934, |
| 60155 | GIR_EraseRootFromParent_Done, |
| 60156 | // Label 3302: @192931 |
| 60157 | GIM_Try, /*On fail goto*//*Label 3303*/ GIMT_Encode4(192981), // Rule ID 7936 // |
| 60158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 60159 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 60160 | GIM_CheckHasNoUse, /*MI*/0, |
| 60161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60163 | // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_noret_i64>> => (DS_MAX_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 60164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_U64), |
| 60165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60166 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60170 | GIR_RootConstrainSelectedInstOperands, |
| 60171 | // GIR_Coverage, 7936, |
| 60172 | GIR_EraseRootFromParent_Done, |
| 60173 | // Label 3303: @192981 |
| 60174 | GIM_Try, /*On fail goto*//*Label 3304*/ GIMT_Encode4(193035), // Rule ID 7931 // |
| 60175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60176 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60178 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60180 | // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_m0_i64>> => (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64), |
| 60182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60184 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60187 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60188 | GIR_RootConstrainSelectedInstOperands, |
| 60189 | // GIR_Coverage, 7931, |
| 60190 | GIR_EraseRootFromParent_Done, |
| 60191 | // Label 3304: @193035 |
| 60192 | GIM_Try, /*On fail goto*//*Label 3305*/ GIMT_Encode4(193089), // Rule ID 7933 // |
| 60193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 60194 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60197 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60198 | // (atomic_load_umax:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_local_i64>> => (DS_MAX_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64_gfx9), |
| 60200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60202 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60206 | GIR_RootConstrainSelectedInstOperands, |
| 60207 | // GIR_Coverage, 7933, |
| 60208 | GIR_EraseRootFromParent_Done, |
| 60209 | // Label 3305: @193089 |
| 60210 | GIM_Try, /*On fail goto*//*Label 3306*/ GIMT_Encode4(193143), // Rule ID 7935 // |
| 60211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 60212 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 60213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60214 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60216 | // (atomic_load_umax_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umax_region_m0_i64>> => (DS_MAX_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 60217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_U64), |
| 60218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60220 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60223 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60224 | GIR_RootConstrainSelectedInstOperands, |
| 60225 | // GIR_Coverage, 7935, |
| 60226 | GIR_EraseRootFromParent_Done, |
| 60227 | // Label 3306: @193143 |
| 60228 | GIM_Try, /*On fail goto*//*Label 3307*/ GIMT_Encode4(193200), // Rule ID 3683 // |
| 60229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60230 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60231 | GIM_CheckHasNoUse, /*MI*/0, |
| 60232 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 60234 | // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (GLOBAL_ATOMIC_UMAX_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 60235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR), |
| 60236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 60237 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 60239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60241 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60242 | GIR_RootConstrainSelectedInstOperands, |
| 60243 | // GIR_Coverage, 3683, |
| 60244 | GIR_EraseRootFromParent_Done, |
| 60245 | // Label 3307: @193200 |
| 60246 | GIM_Try, /*On fail goto*//*Label 3308*/ GIMT_Encode4(193261), // Rule ID 3685 // |
| 60247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60248 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60250 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60251 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 60252 | // (atomic_load_umax:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>> => (GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 60253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_SADDR_RTN), |
| 60254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 60256 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 60258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60261 | GIR_RootConstrainSelectedInstOperands, |
| 60262 | // GIR_Coverage, 3685, |
| 60263 | GIR_EraseRootFromParent_Done, |
| 60264 | // Label 3308: @193261 |
| 60265 | GIM_Try, /*On fail goto*//*Label 3309*/ GIMT_Encode4(193313), // Rule ID 3682 // |
| 60266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60267 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60268 | GIM_CheckHasNoUse, /*MI*/0, |
| 60269 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 60271 | // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (GLOBAL_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2), |
| 60273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60274 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60278 | GIR_RootConstrainSelectedInstOperands, |
| 60279 | // GIR_Coverage, 3682, |
| 60280 | GIR_EraseRootFromParent_Done, |
| 60281 | // Label 3309: @193313 |
| 60282 | GIM_Try, /*On fail goto*//*Label 3310*/ GIMT_Encode4(193369), // Rule ID 3684 // |
| 60283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60284 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60286 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 60288 | // (atomic_load_umax:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>> => (GLOBAL_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMAX_X2_RTN), |
| 60290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60292 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60296 | GIR_RootConstrainSelectedInstOperands, |
| 60297 | // GIR_Coverage, 3684, |
| 60298 | GIR_EraseRootFromParent_Done, |
| 60299 | // Label 3310: @193369 |
| 60300 | GIM_Try, /*On fail goto*//*Label 3311*/ GIMT_Encode4(193422), // Rule ID 3325 // |
| 60301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60302 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60303 | GIM_CheckHasNoUse, /*MI*/0, |
| 60304 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60306 | // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_noret_i64>> => (FLAT_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2), |
| 60308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60309 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60313 | GIR_RootConstrainSelectedInstOperands, |
| 60314 | // GIR_Coverage, 3325, |
| 60315 | GIR_EraseRootFromParent_Done, |
| 60316 | // Label 3311: @193422 |
| 60317 | GIM_Try, /*On fail goto*//*Label 3312*/ GIMT_Encode4(193474), // Rule ID 3385 // |
| 60318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60320 | GIM_CheckHasNoUse, /*MI*/0, |
| 60321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60323 | // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_noret_i64>> => (FLAT_ATOMIC_UMAX_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2), |
| 60325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60326 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60330 | GIR_RootConstrainSelectedInstOperands, |
| 60331 | // GIR_Coverage, 3385, |
| 60332 | GIR_EraseRootFromParent_Done, |
| 60333 | // Label 3312: @193474 |
| 60334 | GIM_Try, /*On fail goto*//*Label 3313*/ GIMT_Encode4(193531), // Rule ID 3324 // |
| 60335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60336 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60338 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60340 | // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_flat_i64>> => (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN), |
| 60342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60344 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60348 | GIR_RootConstrainSelectedInstOperands, |
| 60349 | // GIR_Coverage, 3324, |
| 60350 | GIR_EraseRootFromParent_Done, |
| 60351 | // Label 3313: @193531 |
| 60352 | GIM_Try, /*On fail goto*//*Label 3314*/ GIMT_Encode4(193587), // Rule ID 3384 // |
| 60353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60354 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60356 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60357 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60358 | // (atomic_load_umax:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umax_global_i64>> => (FLAT_ATOMIC_UMAX_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 60359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMAX_X2_RTN), |
| 60360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60362 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60365 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60366 | GIR_RootConstrainSelectedInstOperands, |
| 60367 | // GIR_Coverage, 3384, |
| 60368 | GIR_EraseRootFromParent_Done, |
| 60369 | // Label 3314: @193587 |
| 60370 | GIM_Reject, |
| 60371 | // Label 3292: @193588 |
| 60372 | GIM_Reject, |
| 60373 | // Label 3268: @193589 |
| 60374 | GIM_Reject, |
| 60375 | // Label 27: @193590 |
| 60376 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3317*/ GIMT_Encode4(196101), |
| 60377 | /*GILLT_s32*//*Label 3315*/ GIMT_Encode4(193609), |
| 60378 | /*GILLT_s64*//*Label 3316*/ GIMT_Encode4(194855), |
| 60379 | // Label 3315: @193609 |
| 60380 | GIM_Try, /*On fail goto*//*Label 3318*/ GIMT_Encode4(194854), |
| 60381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 60382 | GIM_Try, /*On fail goto*//*Label 3319*/ GIMT_Encode4(193679), // Rule ID 5284 // |
| 60383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60384 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60385 | GIM_CheckHasNoUse, /*MI*/0, |
| 60386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60388 | // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (BUFFER_ATOMIC_UMIN_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64), |
| 60390 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60397 | GIR_RootConstrainSelectedInstOperands, |
| 60398 | // GIR_Coverage, 5284, |
| 60399 | GIR_EraseRootFromParent_Done, |
| 60400 | // Label 3319: @193679 |
| 60401 | GIM_Try, /*On fail goto*//*Label 3320*/ GIMT_Encode4(193738), // Rule ID 5288 // |
| 60402 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60403 | GIM_CheckHasNoUse, /*MI*/0, |
| 60404 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60405 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60406 | // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64), |
| 60408 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60415 | GIR_RootConstrainSelectedInstOperands, |
| 60416 | // GIR_Coverage, 5288, |
| 60417 | GIR_EraseRootFromParent_Done, |
| 60418 | // Label 3320: @193738 |
| 60419 | GIM_Try, /*On fail goto*//*Label 3321*/ GIMT_Encode4(193804), // Rule ID 5282 // |
| 60420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60421 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60423 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60424 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60425 | // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>> => (BUFFER_ATOMIC_UMIN_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_ADDR64_RTN), |
| 60427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60428 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60435 | GIR_RootConstrainSelectedInstOperands, |
| 60436 | // GIR_Coverage, 5282, |
| 60437 | GIR_EraseRootFromParent_Done, |
| 60438 | // Label 3321: @193804 |
| 60439 | GIM_Try, /*On fail goto*//*Label 3322*/ GIMT_Encode4(193867), // Rule ID 5286 // |
| 60440 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60442 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60443 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60444 | // (atomic_load_umin:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>> => (BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_ADDR64_RTN), |
| 60446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60447 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60453 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60454 | GIR_RootConstrainSelectedInstOperands, |
| 60455 | // GIR_Coverage, 5286, |
| 60456 | GIR_EraseRootFromParent_Done, |
| 60457 | // Label 3322: @193867 |
| 60458 | GIM_Try, /*On fail goto*//*Label 3323*/ GIMT_Encode4(193924), // Rule ID 5283 // |
| 60459 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60460 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60461 | GIM_CheckHasNoUse, /*MI*/0, |
| 60462 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60464 | // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET), |
| 60466 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60471 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60472 | GIR_RootConstrainSelectedInstOperands, |
| 60473 | // GIR_Coverage, 5283, |
| 60474 | GIR_EraseRootFromParent_Done, |
| 60475 | // Label 3323: @193924 |
| 60476 | GIM_Try, /*On fail goto*//*Label 3324*/ GIMT_Encode4(193978), // Rule ID 5287 // |
| 60477 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60478 | GIM_CheckHasNoUse, /*MI*/0, |
| 60479 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60480 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60481 | // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET), |
| 60483 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60489 | GIR_RootConstrainSelectedInstOperands, |
| 60490 | // GIR_Coverage, 5287, |
| 60491 | GIR_EraseRootFromParent_Done, |
| 60492 | // Label 3324: @193978 |
| 60493 | GIM_Try, /*On fail goto*//*Label 3325*/ GIMT_Encode4(194039), // Rule ID 5281 // |
| 60494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60495 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60499 | // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>> => (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN), |
| 60501 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60502 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60508 | GIR_RootConstrainSelectedInstOperands, |
| 60509 | // GIR_Coverage, 5281, |
| 60510 | GIR_EraseRootFromParent_Done, |
| 60511 | // Label 3325: @194039 |
| 60512 | GIM_Try, /*On fail goto*//*Label 3326*/ GIMT_Encode4(194097), // Rule ID 5285 // |
| 60513 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60517 | // (atomic_load_umin:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i32>> => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN), |
| 60519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60520 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60525 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60526 | GIR_RootConstrainSelectedInstOperands, |
| 60527 | // GIR_Coverage, 5285, |
| 60528 | GIR_EraseRootFromParent_Done, |
| 60529 | // Label 3326: @194097 |
| 60530 | GIM_Try, /*On fail goto*//*Label 3327*/ GIMT_Encode4(194147), // Rule ID 7827 // |
| 60531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60532 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60533 | GIM_CheckHasNoUse, /*MI*/0, |
| 60534 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60536 | // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i32>> => (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32), |
| 60538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60539 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60543 | GIR_RootConstrainSelectedInstOperands, |
| 60544 | // GIR_Coverage, 7827, |
| 60545 | GIR_EraseRootFromParent_Done, |
| 60546 | // Label 3327: @194147 |
| 60547 | GIM_Try, /*On fail goto*//*Label 3328*/ GIMT_Encode4(194197), // Rule ID 7829 // |
| 60548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 60549 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60550 | GIM_CheckHasNoUse, /*MI*/0, |
| 60551 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60552 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60553 | // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i32>> => (DS_MIN_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32_gfx9), |
| 60555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60556 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60559 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60560 | GIR_RootConstrainSelectedInstOperands, |
| 60561 | // GIR_Coverage, 7829, |
| 60562 | GIR_EraseRootFromParent_Done, |
| 60563 | // Label 3328: @194197 |
| 60564 | GIM_Try, /*On fail goto*//*Label 3329*/ GIMT_Encode4(194247), // Rule ID 7831 // |
| 60565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 60566 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 60567 | GIM_CheckHasNoUse, /*MI*/0, |
| 60568 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60569 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60570 | // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i32>> => (DS_MIN_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 60571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U32), |
| 60572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60573 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60577 | GIR_RootConstrainSelectedInstOperands, |
| 60578 | // GIR_Coverage, 7831, |
| 60579 | GIR_EraseRootFromParent_Done, |
| 60580 | // Label 3329: @194247 |
| 60581 | GIM_Try, /*On fail goto*//*Label 3330*/ GIMT_Encode4(194301), // Rule ID 7826 // |
| 60582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60583 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60585 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60587 | // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i32>> => (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32), |
| 60589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60591 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60594 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60595 | GIR_RootConstrainSelectedInstOperands, |
| 60596 | // GIR_Coverage, 7826, |
| 60597 | GIR_EraseRootFromParent_Done, |
| 60598 | // Label 3330: @194301 |
| 60599 | GIM_Try, /*On fail goto*//*Label 3331*/ GIMT_Encode4(194355), // Rule ID 7828 // |
| 60600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 60601 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60603 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60605 | // (atomic_load_umin:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_local_i32>> => (DS_MIN_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32_gfx9), |
| 60607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60609 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60612 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60613 | GIR_RootConstrainSelectedInstOperands, |
| 60614 | // GIR_Coverage, 7828, |
| 60615 | GIR_EraseRootFromParent_Done, |
| 60616 | // Label 3331: @194355 |
| 60617 | GIM_Try, /*On fail goto*//*Label 3332*/ GIMT_Encode4(194409), // Rule ID 7830 // |
| 60618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 60619 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 60620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60621 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60623 | // (atomic_load_umin_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i32>> => (DS_MIN_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 60624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U32), |
| 60625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60627 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60630 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60631 | GIR_RootConstrainSelectedInstOperands, |
| 60632 | // GIR_Coverage, 7830, |
| 60633 | GIR_EraseRootFromParent_Done, |
| 60634 | // Label 3332: @194409 |
| 60635 | GIM_Try, /*On fail goto*//*Label 3333*/ GIMT_Encode4(194466), // Rule ID 3635 // |
| 60636 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60637 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60638 | GIM_CheckHasNoUse, /*MI*/0, |
| 60639 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60640 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 60641 | // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (GLOBAL_ATOMIC_UMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 60642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR), |
| 60643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 60644 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 60646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60648 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60649 | GIR_RootConstrainSelectedInstOperands, |
| 60650 | // GIR_Coverage, 3635, |
| 60651 | GIR_EraseRootFromParent_Done, |
| 60652 | // Label 3333: @194466 |
| 60653 | GIM_Try, /*On fail goto*//*Label 3334*/ GIMT_Encode4(194527), // Rule ID 3637 // |
| 60654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60655 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 60659 | // (atomic_load_umin:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>> => (GLOBAL_ATOMIC_UMIN_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 60660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_SADDR_RTN), |
| 60661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 60663 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 60665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60667 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60668 | GIR_RootConstrainSelectedInstOperands, |
| 60669 | // GIR_Coverage, 3637, |
| 60670 | GIR_EraseRootFromParent_Done, |
| 60671 | // Label 3334: @194527 |
| 60672 | GIM_Try, /*On fail goto*//*Label 3335*/ GIMT_Encode4(194579), // Rule ID 3634 // |
| 60673 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60674 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60675 | GIM_CheckHasNoUse, /*MI*/0, |
| 60676 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60677 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 60678 | // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (GLOBAL_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN), |
| 60680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60681 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60684 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60685 | GIR_RootConstrainSelectedInstOperands, |
| 60686 | // GIR_Coverage, 3634, |
| 60687 | GIR_EraseRootFromParent_Done, |
| 60688 | // Label 3335: @194579 |
| 60689 | GIM_Try, /*On fail goto*//*Label 3336*/ GIMT_Encode4(194635), // Rule ID 3636 // |
| 60690 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 60691 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60693 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 60695 | // (atomic_load_umin:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>> => (GLOBAL_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_RTN), |
| 60697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60699 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60703 | GIR_RootConstrainSelectedInstOperands, |
| 60704 | // GIR_Coverage, 3636, |
| 60705 | GIR_EraseRootFromParent_Done, |
| 60706 | // Label 3336: @194635 |
| 60707 | GIM_Try, /*On fail goto*//*Label 3337*/ GIMT_Encode4(194688), // Rule ID 3303 // |
| 60708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60709 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60710 | GIM_CheckHasNoUse, /*MI*/0, |
| 60711 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60713 | // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i32>> => (FLAT_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN), |
| 60715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60716 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60718 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60719 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60720 | GIR_RootConstrainSelectedInstOperands, |
| 60721 | // GIR_Coverage, 3303, |
| 60722 | GIR_EraseRootFromParent_Done, |
| 60723 | // Label 3337: @194688 |
| 60724 | GIM_Try, /*On fail goto*//*Label 3338*/ GIMT_Encode4(194740), // Rule ID 3363 // |
| 60725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60726 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60727 | GIM_CheckHasNoUse, /*MI*/0, |
| 60728 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60729 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60730 | // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i32>> => (FLAT_ATOMIC_UMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN), |
| 60732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60733 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60737 | GIR_RootConstrainSelectedInstOperands, |
| 60738 | // GIR_Coverage, 3363, |
| 60739 | GIR_EraseRootFromParent_Done, |
| 60740 | // Label 3338: @194740 |
| 60741 | GIM_Try, /*On fail goto*//*Label 3339*/ GIMT_Encode4(194797), // Rule ID 3302 // |
| 60742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60743 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60745 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60746 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60747 | // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_flat_i32>> => (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN), |
| 60749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60751 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60754 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60755 | GIR_RootConstrainSelectedInstOperands, |
| 60756 | // GIR_Coverage, 3302, |
| 60757 | GIR_EraseRootFromParent_Done, |
| 60758 | // Label 3339: @194797 |
| 60759 | GIM_Try, /*On fail goto*//*Label 3340*/ GIMT_Encode4(194853), // Rule ID 3362 // |
| 60760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 60761 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 60763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 60765 | // (atomic_load_umin:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_umin_global_i32>> => (FLAT_ATOMIC_UMIN_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 60766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_RTN), |
| 60767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 60769 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 60770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60772 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60773 | GIR_RootConstrainSelectedInstOperands, |
| 60774 | // GIR_Coverage, 3362, |
| 60775 | GIR_EraseRootFromParent_Done, |
| 60776 | // Label 3340: @194853 |
| 60777 | GIM_Reject, |
| 60778 | // Label 3318: @194854 |
| 60779 | GIM_Reject, |
| 60780 | // Label 3316: @194855 |
| 60781 | GIM_Try, /*On fail goto*//*Label 3341*/ GIMT_Encode4(196100), |
| 60782 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 60783 | GIM_Try, /*On fail goto*//*Label 3342*/ GIMT_Encode4(194925), // Rule ID 5380 // |
| 60784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60785 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60786 | GIM_CheckHasNoUse, /*MI*/0, |
| 60787 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60789 | // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (BUFFER_ATOMIC_UMIN_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64), |
| 60791 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60798 | GIR_RootConstrainSelectedInstOperands, |
| 60799 | // GIR_Coverage, 5380, |
| 60800 | GIR_EraseRootFromParent_Done, |
| 60801 | // Label 3342: @194925 |
| 60802 | GIM_Try, /*On fail goto*//*Label 3343*/ GIMT_Encode4(194984), // Rule ID 5384 // |
| 60803 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60804 | GIM_CheckHasNoUse, /*MI*/0, |
| 60805 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60807 | // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64), |
| 60809 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60815 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60816 | GIR_RootConstrainSelectedInstOperands, |
| 60817 | // GIR_Coverage, 5384, |
| 60818 | GIR_EraseRootFromParent_Done, |
| 60819 | // Label 3343: @194984 |
| 60820 | GIM_Try, /*On fail goto*//*Label 3344*/ GIMT_Encode4(195050), // Rule ID 5378 // |
| 60821 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60822 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60824 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60825 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60826 | // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>> => (BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_ADDR64_RTN), |
| 60828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60829 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60835 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60836 | GIR_RootConstrainSelectedInstOperands, |
| 60837 | // GIR_Coverage, 5378, |
| 60838 | GIR_EraseRootFromParent_Done, |
| 60839 | // Label 3344: @195050 |
| 60840 | GIM_Try, /*On fail goto*//*Label 3345*/ GIMT_Encode4(195113), // Rule ID 5382 // |
| 60841 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60843 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 60845 | // (atomic_load_umin:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_ADDR64_RTN), |
| 60847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60848 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 60850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 60852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 60853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60855 | GIR_RootConstrainSelectedInstOperands, |
| 60856 | // GIR_Coverage, 5382, |
| 60857 | GIR_EraseRootFromParent_Done, |
| 60858 | // Label 3345: @195113 |
| 60859 | GIM_Try, /*On fail goto*//*Label 3346*/ GIMT_Encode4(195170), // Rule ID 5379 // |
| 60860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60861 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60862 | GIM_CheckHasNoUse, /*MI*/0, |
| 60863 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60865 | // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET), |
| 60867 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60873 | GIR_RootConstrainSelectedInstOperands, |
| 60874 | // GIR_Coverage, 5379, |
| 60875 | GIR_EraseRootFromParent_Done, |
| 60876 | // Label 3346: @195170 |
| 60877 | GIM_Try, /*On fail goto*//*Label 3347*/ GIMT_Encode4(195224), // Rule ID 5383 // |
| 60878 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60879 | GIM_CheckHasNoUse, /*MI*/0, |
| 60880 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60882 | // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET), |
| 60884 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60889 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60890 | GIR_RootConstrainSelectedInstOperands, |
| 60891 | // GIR_Coverage, 5383, |
| 60892 | GIR_EraseRootFromParent_Done, |
| 60893 | // Label 3347: @195224 |
| 60894 | GIM_Try, /*On fail goto*//*Label 3348*/ GIMT_Encode4(195285), // Rule ID 5377 // |
| 60895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 60896 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60898 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60900 | // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>> => (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN), |
| 60902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60903 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60907 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60908 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60909 | GIR_RootConstrainSelectedInstOperands, |
| 60910 | // GIR_Coverage, 5377, |
| 60911 | GIR_EraseRootFromParent_Done, |
| 60912 | // Label 3348: @195285 |
| 60913 | GIM_Try, /*On fail goto*//*Label 3349*/ GIMT_Encode4(195343), // Rule ID 5381 // |
| 60914 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 60915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60916 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 60918 | // (atomic_load_umin:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_umin_global_i64>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 60919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN), |
| 60920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 60921 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 60922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 60923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 60924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 60925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60927 | GIR_RootConstrainSelectedInstOperands, |
| 60928 | // GIR_Coverage, 5381, |
| 60929 | GIR_EraseRootFromParent_Done, |
| 60930 | // Label 3349: @195343 |
| 60931 | GIM_Try, /*On fail goto*//*Label 3350*/ GIMT_Encode4(195393), // Rule ID 7926 // |
| 60932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60933 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60934 | GIM_CheckHasNoUse, /*MI*/0, |
| 60935 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60937 | // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_noret_i64>> => (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64), |
| 60939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60940 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60944 | GIR_RootConstrainSelectedInstOperands, |
| 60945 | // GIR_Coverage, 7926, |
| 60946 | GIR_EraseRootFromParent_Done, |
| 60947 | // Label 3350: @195393 |
| 60948 | GIM_Try, /*On fail goto*//*Label 3351*/ GIMT_Encode4(195443), // Rule ID 7928 // |
| 60949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 60950 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60951 | GIM_CheckHasNoUse, /*MI*/0, |
| 60952 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60954 | // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_noret_i64>> => (DS_MIN_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64_gfx9), |
| 60956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60957 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60961 | GIR_RootConstrainSelectedInstOperands, |
| 60962 | // GIR_Coverage, 7928, |
| 60963 | GIR_EraseRootFromParent_Done, |
| 60964 | // Label 3351: @195443 |
| 60965 | GIM_Try, /*On fail goto*//*Label 3352*/ GIMT_Encode4(195493), // Rule ID 7930 // |
| 60966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 60967 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 60968 | GIM_CheckHasNoUse, /*MI*/0, |
| 60969 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60971 | // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_noret_i64>> => (DS_MIN_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 60972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_U64), |
| 60973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60974 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 60977 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60978 | GIR_RootConstrainSelectedInstOperands, |
| 60979 | // GIR_Coverage, 7930, |
| 60980 | GIR_EraseRootFromParent_Done, |
| 60981 | // Label 3352: @195493 |
| 60982 | GIM_Try, /*On fail goto*//*Label 3353*/ GIMT_Encode4(195547), // Rule ID 7925 // |
| 60983 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 60984 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 60985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 60986 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 60987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 60988 | // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_m0_i64>> => (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 60989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64), |
| 60990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 60991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 60992 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 60993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 60994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 60995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 60996 | GIR_RootConstrainSelectedInstOperands, |
| 60997 | // GIR_Coverage, 7925, |
| 60998 | GIR_EraseRootFromParent_Done, |
| 60999 | // Label 3353: @195547 |
| 61000 | GIM_Try, /*On fail goto*//*Label 3354*/ GIMT_Encode4(195601), // Rule ID 7927 // |
| 61001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 61002 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61006 | // (atomic_load_umin:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_local_i64>> => (DS_MIN_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64_gfx9), |
| 61008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61010 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61013 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61014 | GIR_RootConstrainSelectedInstOperands, |
| 61015 | // GIR_Coverage, 7927, |
| 61016 | GIR_EraseRootFromParent_Done, |
| 61017 | // Label 3354: @195601 |
| 61018 | GIM_Try, /*On fail goto*//*Label 3355*/ GIMT_Encode4(195655), // Rule ID 7929 // |
| 61019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 61020 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61021 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61022 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61023 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61024 | // (atomic_load_umin_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_umin_region_m0_i64>> => (DS_MIN_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_U64), |
| 61026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61028 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61032 | GIR_RootConstrainSelectedInstOperands, |
| 61033 | // GIR_Coverage, 7929, |
| 61034 | GIR_EraseRootFromParent_Done, |
| 61035 | // Label 3355: @195655 |
| 61036 | GIM_Try, /*On fail goto*//*Label 3356*/ GIMT_Encode4(195712), // Rule ID 3691 // |
| 61037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61038 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61039 | GIM_CheckHasNoUse, /*MI*/0, |
| 61040 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61042 | // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (GLOBAL_ATOMIC_UMIN_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR), |
| 61044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61045 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61049 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61050 | GIR_RootConstrainSelectedInstOperands, |
| 61051 | // GIR_Coverage, 3691, |
| 61052 | GIR_EraseRootFromParent_Done, |
| 61053 | // Label 3356: @195712 |
| 61054 | GIM_Try, /*On fail goto*//*Label 3357*/ GIMT_Encode4(195773), // Rule ID 3693 // |
| 61055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61056 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61058 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61060 | // (atomic_load_umin:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>> => (GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_SADDR_RTN), |
| 61062 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61064 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61068 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61069 | GIR_RootConstrainSelectedInstOperands, |
| 61070 | // GIR_Coverage, 3693, |
| 61071 | GIR_EraseRootFromParent_Done, |
| 61072 | // Label 3357: @195773 |
| 61073 | GIM_Try, /*On fail goto*//*Label 3358*/ GIMT_Encode4(195825), // Rule ID 3690 // |
| 61074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61075 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61076 | GIM_CheckHasNoUse, /*MI*/0, |
| 61077 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61079 | // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (GLOBAL_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2), |
| 61081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61082 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61085 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61086 | GIR_RootConstrainSelectedInstOperands, |
| 61087 | // GIR_Coverage, 3690, |
| 61088 | GIR_EraseRootFromParent_Done, |
| 61089 | // Label 3358: @195825 |
| 61090 | GIM_Try, /*On fail goto*//*Label 3359*/ GIMT_Encode4(195881), // Rule ID 3692 // |
| 61091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61092 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61093 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61094 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61095 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61096 | // (atomic_load_umin:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>> => (GLOBAL_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_UMIN_X2_RTN), |
| 61098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61100 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61103 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61104 | GIR_RootConstrainSelectedInstOperands, |
| 61105 | // GIR_Coverage, 3692, |
| 61106 | GIR_EraseRootFromParent_Done, |
| 61107 | // Label 3359: @195881 |
| 61108 | GIM_Try, /*On fail goto*//*Label 3360*/ GIMT_Encode4(195934), // Rule ID 3329 // |
| 61109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 61110 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61111 | GIM_CheckHasNoUse, /*MI*/0, |
| 61112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61114 | // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_noret_i64>> => (FLAT_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2), |
| 61116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61117 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61121 | GIR_RootConstrainSelectedInstOperands, |
| 61122 | // GIR_Coverage, 3329, |
| 61123 | GIR_EraseRootFromParent_Done, |
| 61124 | // Label 3360: @195934 |
| 61125 | GIM_Try, /*On fail goto*//*Label 3361*/ GIMT_Encode4(195986), // Rule ID 3389 // |
| 61126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 61127 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61128 | GIM_CheckHasNoUse, /*MI*/0, |
| 61129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61131 | // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_noret_i64>> => (FLAT_ATOMIC_UMIN_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2), |
| 61133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61134 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61138 | GIR_RootConstrainSelectedInstOperands, |
| 61139 | // GIR_Coverage, 3389, |
| 61140 | GIR_EraseRootFromParent_Done, |
| 61141 | // Label 3361: @195986 |
| 61142 | GIM_Try, /*On fail goto*//*Label 3362*/ GIMT_Encode4(196043), // Rule ID 3328 // |
| 61143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 61144 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61148 | // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_flat_i64>> => (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN), |
| 61150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61152 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61155 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61156 | GIR_RootConstrainSelectedInstOperands, |
| 61157 | // GIR_Coverage, 3328, |
| 61158 | GIR_EraseRootFromParent_Done, |
| 61159 | // Label 3362: @196043 |
| 61160 | GIM_Try, /*On fail goto*//*Label 3363*/ GIMT_Encode4(196099), // Rule ID 3388 // |
| 61161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 61162 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61163 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61164 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61165 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61166 | // (atomic_load_umin:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_umin_global_i64>> => (FLAT_ATOMIC_UMIN_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 61167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_UMIN_X2_RTN), |
| 61168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61170 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61173 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61174 | GIR_RootConstrainSelectedInstOperands, |
| 61175 | // GIR_Coverage, 3388, |
| 61176 | GIR_EraseRootFromParent_Done, |
| 61177 | // Label 3363: @196099 |
| 61178 | GIM_Reject, |
| 61179 | // Label 3341: @196100 |
| 61180 | GIM_Reject, |
| 61181 | // Label 3317: @196101 |
| 61182 | GIM_Reject, |
| 61183 | // Label 28: @196102 |
| 61184 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 3367*/ GIMT_Encode4(198960), |
| 61185 | /*GILLT_s32*//*Label 3364*/ GIMT_Encode4(196125), |
| 61186 | /*GILLT_s64*//*Label 3365*/ GIMT_Encode4(196783), |
| 61187 | /*GILLT_v2s16*//*Label 3366*/ GIMT_Encode4(197233), |
| 61188 | // Label 3364: @196125 |
| 61189 | GIM_Try, /*On fail goto*//*Label 3368*/ GIMT_Encode4(196782), |
| 61190 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 61191 | GIM_Try, /*On fail goto*//*Label 3369*/ GIMT_Encode4(196183), // Rule ID 7863 // |
| 61192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init), |
| 61193 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61194 | GIM_CheckHasNoUse, /*MI*/0, |
| 61195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61197 | // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_f32>> => (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32), |
| 61199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61200 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61203 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61204 | GIR_RootConstrainSelectedInstOperands, |
| 61205 | // GIR_Coverage, 7863, |
| 61206 | GIR_EraseRootFromParent_Done, |
| 61207 | // Label 3369: @196183 |
| 61208 | GIM_Try, /*On fail goto*//*Label 3370*/ GIMT_Encode4(196233), // Rule ID 7865 // |
| 61209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init), |
| 61210 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61211 | GIM_CheckHasNoUse, /*MI*/0, |
| 61212 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61213 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61214 | // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f32>> => (DS_ADD_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32_gfx9), |
| 61216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61217 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61221 | GIR_RootConstrainSelectedInstOperands, |
| 61222 | // GIR_Coverage, 7865, |
| 61223 | GIR_EraseRootFromParent_Done, |
| 61224 | // Label 3370: @196233 |
| 61225 | GIM_Try, /*On fail goto*//*Label 3371*/ GIMT_Encode4(196283), // Rule ID 7867 // |
| 61226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32), |
| 61227 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61228 | GIM_CheckHasNoUse, /*MI*/0, |
| 61229 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61230 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61231 | // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_f32>> => (DS_ADD_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F32), |
| 61233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61234 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61237 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61238 | GIR_RootConstrainSelectedInstOperands, |
| 61239 | // GIR_Coverage, 7867, |
| 61240 | GIR_EraseRootFromParent_Done, |
| 61241 | // Label 3371: @196283 |
| 61242 | GIM_Try, /*On fail goto*//*Label 3372*/ GIMT_Encode4(196337), // Rule ID 7862 // |
| 61243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_LDSRequiresM0Init), |
| 61244 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61246 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61248 | // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_f32>> => (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32), |
| 61250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61252 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61255 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61256 | GIR_RootConstrainSelectedInstOperands, |
| 61257 | // GIR_Coverage, 7862, |
| 61258 | GIR_EraseRootFromParent_Done, |
| 61259 | // Label 3372: @196337 |
| 61260 | GIM_Try, /*On fail goto*//*Label 3373*/ GIMT_Encode4(196391), // Rule ID 7864 // |
| 61261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLDSFPAtomicAddF32_NotLDSRequiresM0Init), |
| 61262 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61264 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61266 | // (atomic_load_fadd:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_local_f32>> => (DS_ADD_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32_gfx9), |
| 61268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61270 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61274 | GIR_RootConstrainSelectedInstOperands, |
| 61275 | // GIR_Coverage, 7864, |
| 61276 | GIR_EraseRootFromParent_Done, |
| 61277 | // Label 3373: @196391 |
| 61278 | GIM_Try, /*On fail goto*//*Label 3374*/ GIMT_Encode4(196445), // Rule ID 7866 // |
| 61279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS_HasLDSFPAtomicAddF32), |
| 61280 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61284 | // (atomic_load_fadd_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_f32>> => (DS_ADD_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F32), |
| 61286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61288 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61291 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61292 | GIR_RootConstrainSelectedInstOperands, |
| 61293 | // GIR_Coverage, 7866, |
| 61294 | GIR_EraseRootFromParent_Done, |
| 61295 | // Label 3374: @196445 |
| 61296 | GIM_Try, /*On fail goto*//*Label 3375*/ GIMT_Encode4(196502), // Rule ID 3769 // |
| 61297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 61298 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61299 | GIM_CheckHasNoUse, /*MI*/0, |
| 61300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61302 | // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>> => (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR), |
| 61304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61305 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61310 | GIR_RootConstrainSelectedInstOperands, |
| 61311 | // GIR_Coverage, 3769, |
| 61312 | GIR_EraseRootFromParent_Done, |
| 61313 | // Label 3375: @196502 |
| 61314 | GIM_Try, /*On fail goto*//*Label 3376*/ GIMT_Encode4(196563), // Rule ID 3781 // |
| 61315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 61316 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61318 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61320 | // (atomic_load_fadd:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>> => (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN), |
| 61322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61324 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61328 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61329 | GIR_RootConstrainSelectedInstOperands, |
| 61330 | // GIR_Coverage, 3781, |
| 61331 | GIR_EraseRootFromParent_Done, |
| 61332 | // Label 3376: @196563 |
| 61333 | GIM_Try, /*On fail goto*//*Label 3377*/ GIMT_Encode4(196615), // Rule ID 3768 // |
| 61334 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 61335 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61336 | GIM_CheckHasNoUse, /*MI*/0, |
| 61337 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61339 | // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f32>> => (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 61340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32), |
| 61341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61342 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61345 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61346 | GIR_RootConstrainSelectedInstOperands, |
| 61347 | // GIR_Coverage, 3768, |
| 61348 | GIR_EraseRootFromParent_Done, |
| 61349 | // Label 3377: @196615 |
| 61350 | GIM_Try, /*On fail goto*//*Label 3378*/ GIMT_Encode4(196671), // Rule ID 3780 // |
| 61351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 61352 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61354 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61355 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61356 | // (atomic_load_fadd:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_global_f32>> => (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 61357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN), |
| 61358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61360 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61363 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61364 | GIR_RootConstrainSelectedInstOperands, |
| 61365 | // GIR_Coverage, 3780, |
| 61366 | GIR_EraseRootFromParent_Done, |
| 61367 | // Label 3378: @196671 |
| 61368 | GIM_Try, /*On fail goto*//*Label 3379*/ GIMT_Encode4(196724), // Rule ID 3831 // |
| 61369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst), |
| 61370 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61371 | GIM_CheckHasNoUse, /*MI*/0, |
| 61372 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61374 | // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f32>> => (FLAT_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 61375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32), |
| 61376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61377 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61381 | GIR_RootConstrainSelectedInstOperands, |
| 61382 | // GIR_Coverage, 3831, |
| 61383 | GIR_EraseRootFromParent_Done, |
| 61384 | // Label 3379: @196724 |
| 61385 | GIM_Try, /*On fail goto*//*Label 3380*/ GIMT_Encode4(196781), // Rule ID 3830 // |
| 61386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst), |
| 61387 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61389 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61390 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61391 | // (atomic_load_fadd:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fadd_flat_f32>> => (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 61392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN), |
| 61393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61395 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61399 | GIR_RootConstrainSelectedInstOperands, |
| 61400 | // GIR_Coverage, 3830, |
| 61401 | GIR_EraseRootFromParent_Done, |
| 61402 | // Label 3380: @196781 |
| 61403 | GIM_Reject, |
| 61404 | // Label 3368: @196782 |
| 61405 | GIM_Reject, |
| 61406 | // Label 3365: @196783 |
| 61407 | GIM_Try, /*On fail goto*//*Label 3381*/ GIMT_Encode4(197232), |
| 61408 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 61409 | GIM_Try, /*On fail goto*//*Label 3382*/ GIMT_Encode4(196841), // Rule ID 7960 // |
| 61410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64), |
| 61411 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61412 | GIM_CheckHasNoUse, /*MI*/0, |
| 61413 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61415 | // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_f64>> => (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64), |
| 61417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61418 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61422 | GIR_RootConstrainSelectedInstOperands, |
| 61423 | // GIR_Coverage, 7960, |
| 61424 | GIR_EraseRootFromParent_Done, |
| 61425 | // Label 3382: @196841 |
| 61426 | GIM_Try, /*On fail goto*//*Label 3383*/ GIMT_Encode4(196895), // Rule ID 7959 // |
| 61427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64), |
| 61428 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61430 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61432 | // (atomic_load_fadd:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fadd_local_f64>> => (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64), |
| 61434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61436 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61440 | GIR_RootConstrainSelectedInstOperands, |
| 61441 | // GIR_Coverage, 7959, |
| 61442 | GIR_EraseRootFromParent_Done, |
| 61443 | // Label 3383: @196895 |
| 61444 | GIM_Try, /*On fail goto*//*Label 3384*/ GIMT_Encode4(196952), // Rule ID 3815 // |
| 61445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61446 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61447 | GIM_CheckHasNoUse, /*MI*/0, |
| 61448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61450 | // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>> => (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR), |
| 61452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61453 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61458 | GIR_RootConstrainSelectedInstOperands, |
| 61459 | // GIR_Coverage, 3815, |
| 61460 | GIR_EraseRootFromParent_Done, |
| 61461 | // Label 3384: @196952 |
| 61462 | GIM_Try, /*On fail goto*//*Label 3385*/ GIMT_Encode4(197013), // Rule ID 3817 // |
| 61463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61464 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61466 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61468 | // (atomic_load_fadd:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>> => (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN), |
| 61470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61472 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61476 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61477 | GIR_RootConstrainSelectedInstOperands, |
| 61478 | // GIR_Coverage, 3817, |
| 61479 | GIR_EraseRootFromParent_Done, |
| 61480 | // Label 3385: @197013 |
| 61481 | GIM_Try, /*On fail goto*//*Label 3386*/ GIMT_Encode4(197065), // Rule ID 3814 // |
| 61482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61483 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61484 | GIM_CheckHasNoUse, /*MI*/0, |
| 61485 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61486 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61487 | // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_f64>> => (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 61488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64), |
| 61489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61490 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61493 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61494 | GIR_RootConstrainSelectedInstOperands, |
| 61495 | // GIR_Coverage, 3814, |
| 61496 | GIR_EraseRootFromParent_Done, |
| 61497 | // Label 3386: @197065 |
| 61498 | GIM_Try, /*On fail goto*//*Label 3387*/ GIMT_Encode4(197121), // Rule ID 3816 // |
| 61499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61500 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61501 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61502 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61504 | // (atomic_load_fadd:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_global_f64>> => (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 61505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN), |
| 61506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61508 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61511 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61512 | GIR_RootConstrainSelectedInstOperands, |
| 61513 | // GIR_Coverage, 3816, |
| 61514 | GIR_EraseRootFromParent_Done, |
| 61515 | // Label 3387: @197121 |
| 61516 | GIM_Try, /*On fail goto*//*Label 3388*/ GIMT_Encode4(197174), // Rule ID 3827 // |
| 61517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61518 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61519 | GIM_CheckHasNoUse, /*MI*/0, |
| 61520 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61522 | // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_f64>> => (FLAT_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 61523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64), |
| 61524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61525 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61529 | GIR_RootConstrainSelectedInstOperands, |
| 61530 | // GIR_Coverage, 3827, |
| 61531 | GIR_EraseRootFromParent_Done, |
| 61532 | // Label 3388: @197174 |
| 61533 | GIM_Try, /*On fail goto*//*Label 3389*/ GIMT_Encode4(197231), // Rule ID 3826 // |
| 61534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 61535 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 61537 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 61539 | // (atomic_load_fadd:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fadd_flat_f64>> => (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 61540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN), |
| 61541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61543 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61547 | GIR_RootConstrainSelectedInstOperands, |
| 61548 | // GIR_Coverage, 3826, |
| 61549 | GIR_EraseRootFromParent_Done, |
| 61550 | // Label 3389: @197231 |
| 61551 | GIM_Reject, |
| 61552 | // Label 3381: @197232 |
| 61553 | GIM_Reject, |
| 61554 | // Label 3366: @197233 |
| 61555 | GIM_Try, /*On fail goto*//*Label 3390*/ GIMT_Encode4(198959), |
| 61556 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 61557 | GIM_Try, /*On fail goto*//*Label 3391*/ GIMT_Encode4(197291), // Rule ID 7851 // |
| 61558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61559 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61560 | GIM_CheckHasNoUse, /*MI*/0, |
| 61561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61563 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_v2f16>> => (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16), |
| 61565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61566 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61570 | GIR_RootConstrainSelectedInstOperands, |
| 61571 | // GIR_Coverage, 7851, |
| 61572 | GIR_EraseRootFromParent_Done, |
| 61573 | // Label 3391: @197291 |
| 61574 | GIM_Try, /*On fail goto*//*Label 3392*/ GIMT_Encode4(197341), // Rule ID 7853 // |
| 61575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61576 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61577 | GIM_CheckHasNoUse, /*MI*/0, |
| 61578 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61580 | // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>> => (DS_PK_ADD_F16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16_gfx9), |
| 61582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61583 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61587 | GIR_RootConstrainSelectedInstOperands, |
| 61588 | // GIR_Coverage, 7853, |
| 61589 | GIR_EraseRootFromParent_Done, |
| 61590 | // Label 3392: @197341 |
| 61591 | GIM_Try, /*On fail goto*//*Label 3393*/ GIMT_Encode4(197391), // Rule ID 7855 // |
| 61592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61593 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61594 | GIM_CheckHasNoUse, /*MI*/0, |
| 61595 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61597 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_v2f16>> => (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16), |
| 61599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61600 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61604 | GIR_RootConstrainSelectedInstOperands, |
| 61605 | // GIR_Coverage, 7855, |
| 61606 | GIR_EraseRootFromParent_Done, |
| 61607 | // Label 3393: @197391 |
| 61608 | GIM_Try, /*On fail goto*//*Label 3394*/ GIMT_Encode4(197441), // Rule ID 7857 // |
| 61609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61610 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61611 | GIM_CheckHasNoUse, /*MI*/0, |
| 61612 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61614 | // (atomic_load_fadd_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_v2bf16>> => (DS_PK_ADD_BF16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_BF16), |
| 61616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61617 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61620 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61621 | GIR_RootConstrainSelectedInstOperands, |
| 61622 | // GIR_Coverage, 7857, |
| 61623 | GIR_EraseRootFromParent_Done, |
| 61624 | // Label 3394: @197441 |
| 61625 | GIM_Try, /*On fail goto*//*Label 3395*/ GIMT_Encode4(197491), // Rule ID 7859 // |
| 61626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61627 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61628 | GIM_CheckHasNoUse, /*MI*/0, |
| 61629 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61631 | // (atomic_load_fadd:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2bf16>> => (DS_PK_ADD_BF16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_BF16_gfx9), |
| 61633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61634 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61637 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61638 | GIR_RootConstrainSelectedInstOperands, |
| 61639 | // GIR_Coverage, 7859, |
| 61640 | GIR_EraseRootFromParent_Done, |
| 61641 | // Label 3395: @197491 |
| 61642 | GIM_Try, /*On fail goto*//*Label 3396*/ GIMT_Encode4(197541), // Rule ID 7861 // |
| 61643 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61644 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61645 | GIM_CheckHasNoUse, /*MI*/0, |
| 61646 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61647 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61648 | // (atomic_load_fadd_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_v2bf16>> => (DS_PK_ADD_BF16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_BF16), |
| 61650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61651 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61653 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61654 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61655 | GIR_RootConstrainSelectedInstOperands, |
| 61656 | // GIR_Coverage, 7861, |
| 61657 | GIR_EraseRootFromParent_Done, |
| 61658 | // Label 3396: @197541 |
| 61659 | GIM_Try, /*On fail goto*//*Label 3397*/ GIMT_Encode4(197591), // Rule ID 7964 // |
| 61660 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61661 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61662 | GIM_CheckHasNoUse, /*MI*/0, |
| 61663 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61665 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_noret_v2f16>> => (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16), |
| 61667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61668 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61671 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61672 | GIR_RootConstrainSelectedInstOperands, |
| 61673 | // GIR_Coverage, 7964, |
| 61674 | GIR_EraseRootFromParent_Done, |
| 61675 | // Label 3397: @197591 |
| 61676 | GIM_Try, /*On fail goto*//*Label 3398*/ GIMT_Encode4(197641), // Rule ID 7966 // |
| 61677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61678 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61679 | GIM_CheckHasNoUse, /*MI*/0, |
| 61680 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61681 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61682 | // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_noret_v2f16>> => (DS_PK_ADD_F16_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16_gfx9), |
| 61684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61685 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61689 | GIR_RootConstrainSelectedInstOperands, |
| 61690 | // GIR_Coverage, 7966, |
| 61691 | GIR_EraseRootFromParent_Done, |
| 61692 | // Label 3398: @197641 |
| 61693 | GIM_Try, /*On fail goto*//*Label 3399*/ GIMT_Encode4(197691), // Rule ID 7968 // |
| 61694 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61695 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61696 | GIM_CheckHasNoUse, /*MI*/0, |
| 61697 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61698 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61699 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_noret_v2f16>> => (DS_PK_ADD_F16 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_F16), |
| 61701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61702 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61706 | GIR_RootConstrainSelectedInstOperands, |
| 61707 | // GIR_Coverage, 7968, |
| 61708 | GIR_EraseRootFromParent_Done, |
| 61709 | // Label 3399: @197691 |
| 61710 | GIM_Try, /*On fail goto*//*Label 3400*/ GIMT_Encode4(197745), // Rule ID 7850 // |
| 61711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61712 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61714 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61716 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_v2f16>> => (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16), |
| 61718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61720 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61724 | GIR_RootConstrainSelectedInstOperands, |
| 61725 | // GIR_Coverage, 7850, |
| 61726 | GIR_EraseRootFromParent_Done, |
| 61727 | // Label 3400: @197745 |
| 61728 | GIM_Try, /*On fail goto*//*Label 3401*/ GIMT_Encode4(197799), // Rule ID 7852 // |
| 61729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61730 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61732 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61734 | // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_v2f16>> => (DS_PK_ADD_RTN_F16_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16_gfx9), |
| 61736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61738 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61742 | GIR_RootConstrainSelectedInstOperands, |
| 61743 | // GIR_Coverage, 7852, |
| 61744 | GIR_EraseRootFromParent_Done, |
| 61745 | // Label 3401: @197799 |
| 61746 | GIM_Try, /*On fail goto*//*Label 3402*/ GIMT_Encode4(197853), // Rule ID 7854 // |
| 61747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61748 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61750 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61752 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_v2f16>> => (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16), |
| 61754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61756 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61760 | GIR_RootConstrainSelectedInstOperands, |
| 61761 | // GIR_Coverage, 7854, |
| 61762 | GIR_EraseRootFromParent_Done, |
| 61763 | // Label 3402: @197853 |
| 61764 | GIM_Try, /*On fail goto*//*Label 3403*/ GIMT_Encode4(197907), // Rule ID 7856 // |
| 61765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61766 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61768 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61769 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61770 | // (atomic_load_fadd_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_v2bf16>> => (DS_PK_ADD_RTN_BF16:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_BF16), |
| 61772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61774 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61778 | GIR_RootConstrainSelectedInstOperands, |
| 61779 | // GIR_Coverage, 7856, |
| 61780 | GIR_EraseRootFromParent_Done, |
| 61781 | // Label 3403: @197907 |
| 61782 | GIM_Try, /*On fail goto*//*Label 3404*/ GIMT_Encode4(197961), // Rule ID 7858 // |
| 61783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61784 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61786 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61788 | // (atomic_load_fadd:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_local_v2bf16>> => (DS_PK_ADD_RTN_BF16_gfx9:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_BF16_gfx9), |
| 61790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61792 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61796 | GIR_RootConstrainSelectedInstOperands, |
| 61797 | // GIR_Coverage, 7858, |
| 61798 | GIR_EraseRootFromParent_Done, |
| 61799 | // Label 3404: @197961 |
| 61800 | GIM_Try, /*On fail goto*//*Label 3405*/ GIMT_Encode4(198015), // Rule ID 7860 // |
| 61801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61802 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61804 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61805 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61806 | // (atomic_load_fadd_glue:{ *:[v2bf16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_v2bf16>> => (DS_PK_ADD_RTN_BF16:{ *:[v2bf16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2bf16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_BF16), |
| 61808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61810 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61813 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61814 | GIR_RootConstrainSelectedInstOperands, |
| 61815 | // GIR_Coverage, 7860, |
| 61816 | GIR_EraseRootFromParent_Done, |
| 61817 | // Label 3405: @198015 |
| 61818 | GIM_Try, /*On fail goto*//*Label 3406*/ GIMT_Encode4(198069), // Rule ID 7963 // |
| 61819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_LDSRequiresM0Init), |
| 61820 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61822 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61824 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_m0_v2f16>> => (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16), |
| 61826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61828 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61832 | GIR_RootConstrainSelectedInstOperands, |
| 61833 | // GIR_Coverage, 7963, |
| 61834 | GIR_EraseRootFromParent_Done, |
| 61835 | // Label 3406: @198069 |
| 61836 | GIM_Try, /*On fail goto*//*Label 3407*/ GIMT_Encode4(198123), // Rule ID 7965 // |
| 61837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_NotLDSRequiresM0Init), |
| 61838 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 61839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61840 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61842 | // (atomic_load_fadd:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_local_v2f16>> => (DS_PK_ADD_RTN_F16_gfx9:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 61843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16_gfx9), |
| 61844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61846 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61849 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61850 | GIR_RootConstrainSelectedInstOperands, |
| 61851 | // GIR_Coverage, 7965, |
| 61852 | GIR_EraseRootFromParent_Done, |
| 61853 | // Label 3407: @198123 |
| 61854 | GIM_Try, /*On fail goto*//*Label 3408*/ GIMT_Encode4(198177), // Rule ID 7967 // |
| 61855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicDsPkAdd16Insts_HasGDS), |
| 61856 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 61857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61858 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 61860 | // (atomic_load_fadd_glue:{ *:[v2f16] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$value)<<P:Predicate_atomic_load_fadd_region_m0_v2f16>> => (DS_PK_ADD_RTN_F16:{ *:[v2f16] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[v2f16] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 61861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PK_ADD_RTN_F16), |
| 61862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 61864 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 61865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61868 | GIR_RootConstrainSelectedInstOperands, |
| 61869 | // GIR_Coverage, 7967, |
| 61870 | GIR_EraseRootFromParent_Done, |
| 61871 | // Label 3408: @198177 |
| 61872 | GIM_Try, /*On fail goto*//*Label 3409*/ GIMT_Encode4(198234), // Rule ID 3775 // |
| 61873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 61874 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61875 | GIM_CheckHasNoUse, /*MI*/0, |
| 61876 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61878 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR), |
| 61880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61881 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61885 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61886 | GIR_RootConstrainSelectedInstOperands, |
| 61887 | // GIR_Coverage, 3775, |
| 61888 | GIR_EraseRootFromParent_Done, |
| 61889 | // Label 3409: @198234 |
| 61890 | GIM_Try, /*On fail goto*//*Label 3410*/ GIMT_Encode4(198291), // Rule ID 3791 // |
| 61891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 61892 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61893 | GIM_CheckHasNoUse, /*MI*/0, |
| 61894 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61895 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61896 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR), |
| 61898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61899 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61903 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61904 | GIR_RootConstrainSelectedInstOperands, |
| 61905 | // GIR_Coverage, 3791, |
| 61906 | GIR_EraseRootFromParent_Done, |
| 61907 | // Label 3410: @198291 |
| 61908 | GIM_Try, /*On fail goto*//*Label 3411*/ GIMT_Encode4(198348), // Rule ID 3847 // |
| 61909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61910 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61911 | GIM_CheckHasNoUse, /*MI*/0, |
| 61912 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61914 | // (atomic_load_fadd:{ *:[v2bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2bf16>> => (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR), |
| 61916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61917 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61922 | GIR_RootConstrainSelectedInstOperands, |
| 61923 | // GIR_Coverage, 3847, |
| 61924 | GIR_EraseRootFromParent_Done, |
| 61925 | // Label 3411: @198348 |
| 61926 | GIM_Try, /*On fail goto*//*Label 3412*/ GIMT_Encode4(198409), // Rule ID 3793 // |
| 61927 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 61928 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61932 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN), |
| 61934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61936 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61940 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61941 | GIR_RootConstrainSelectedInstOperands, |
| 61942 | // GIR_Coverage, 3793, |
| 61943 | GIR_EraseRootFromParent_Done, |
| 61944 | // Label 3412: @198409 |
| 61945 | GIM_Try, /*On fail goto*//*Label 3413*/ GIMT_Encode4(198470), // Rule ID 3849 // |
| 61946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 61947 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 61949 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61950 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 61951 | // (atomic_load_fadd:{ *:[v2bf16] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2bf16>> => (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN:{ *:[v2bf16] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 61952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN), |
| 61953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 61954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 61955 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 61957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 61958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 61959 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61960 | GIR_RootConstrainSelectedInstOperands, |
| 61961 | // GIR_Coverage, 3849, |
| 61962 | GIR_EraseRootFromParent_Done, |
| 61963 | // Label 3413: @198470 |
| 61964 | GIM_Try, /*On fail goto*//*Label 3414*/ GIMT_Encode4(198522), // Rule ID 3774 // |
| 61965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 61966 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61967 | GIM_CheckHasNoUse, /*MI*/0, |
| 61968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61970 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 61971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16), |
| 61972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61973 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61977 | GIR_RootConstrainSelectedInstOperands, |
| 61978 | // GIR_Coverage, 3774, |
| 61979 | GIR_EraseRootFromParent_Done, |
| 61980 | // Label 3414: @198522 |
| 61981 | GIM_Try, /*On fail goto*//*Label 3415*/ GIMT_Encode4(198574), // Rule ID 3790 // |
| 61982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 61983 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 61984 | GIM_CheckHasNoUse, /*MI*/0, |
| 61985 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 61986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 61987 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 61988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16), |
| 61989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 61990 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 61991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 61992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 61993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 61994 | GIR_RootConstrainSelectedInstOperands, |
| 61995 | // GIR_Coverage, 3790, |
| 61996 | GIR_EraseRootFromParent_Done, |
| 61997 | // Label 3415: @198574 |
| 61998 | GIM_Try, /*On fail goto*//*Label 3416*/ GIMT_Encode4(198626), // Rule ID 3846 // |
| 61999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 62000 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62001 | GIM_CheckHasNoUse, /*MI*/0, |
| 62002 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62003 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62004 | // (atomic_load_fadd:{ *:[v2bf16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_global_noret_v2bf16>> => (GLOBAL_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 62005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16), |
| 62006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62007 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62011 | GIR_RootConstrainSelectedInstOperands, |
| 62012 | // GIR_Coverage, 3846, |
| 62013 | GIR_EraseRootFromParent_Done, |
| 62014 | // Label 3416: @198626 |
| 62015 | GIM_Try, /*On fail goto*//*Label 3417*/ GIMT_Encode4(198682), // Rule ID 3792 // |
| 62016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 62017 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62019 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62021 | // (atomic_load_fadd:{ *:[v2f16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2f16>> => (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 62022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN), |
| 62023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62025 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62029 | GIR_RootConstrainSelectedInstOperands, |
| 62030 | // GIR_Coverage, 3792, |
| 62031 | GIR_EraseRootFromParent_Done, |
| 62032 | // Label 3417: @198682 |
| 62033 | GIM_Try, /*On fail goto*//*Label 3418*/ GIMT_Encode4(198738), // Rule ID 3848 // |
| 62034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 62035 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62037 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62039 | // (atomic_load_fadd:{ *:[v2bf16] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_global_v2bf16>> => (GLOBAL_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2bf16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 62040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN), |
| 62041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62043 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62046 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62047 | GIR_RootConstrainSelectedInstOperands, |
| 62048 | // GIR_Coverage, 3848, |
| 62049 | GIR_EraseRootFromParent_Done, |
| 62050 | // Label 3418: @198738 |
| 62051 | GIM_Try, /*On fail goto*//*Label 3419*/ GIMT_Encode4(198791), // Rule ID 3839 // |
| 62052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 62053 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62054 | GIM_CheckHasNoUse, /*MI*/0, |
| 62055 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62057 | // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2f16>> => (FLAT_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 62058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16), |
| 62059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62060 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62064 | GIR_RootConstrainSelectedInstOperands, |
| 62065 | // GIR_Coverage, 3839, |
| 62066 | GIR_EraseRootFromParent_Done, |
| 62067 | // Label 3419: @198791 |
| 62068 | GIM_Try, /*On fail goto*//*Label 3420*/ GIMT_Encode4(198844), // Rule ID 3841 // |
| 62069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 62070 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62071 | GIM_CheckHasNoUse, /*MI*/0, |
| 62072 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62073 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62074 | // (atomic_load_fadd:{ *:[v2bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_flat_noret_v2bf16>> => (FLAT_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 62075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16), |
| 62076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62077 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62081 | GIR_RootConstrainSelectedInstOperands, |
| 62082 | // GIR_Coverage, 3841, |
| 62083 | GIR_EraseRootFromParent_Done, |
| 62084 | // Label 3420: @198844 |
| 62085 | GIM_Try, /*On fail goto*//*Label 3421*/ GIMT_Encode4(198901), // Rule ID 3838 // |
| 62086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 62087 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62089 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62091 | // (atomic_load_fadd:{ *:[v2f16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2f16>> => (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 62092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN), |
| 62093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62095 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62099 | GIR_RootConstrainSelectedInstOperands, |
| 62100 | // GIR_Coverage, 3838, |
| 62101 | GIR_EraseRootFromParent_Done, |
| 62102 | // Label 3421: @198901 |
| 62103 | GIM_Try, /*On fail goto*//*Label 3422*/ GIMT_Encode4(198958), // Rule ID 3840 // |
| 62104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 62105 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62107 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62109 | // (atomic_load_fadd:{ *:[v2bf16] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2bf16:{ *:[v2bf16] }:$data)<<P:Predicate_atomic_load_fadd_flat_v2bf16>> => (FLAT_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2bf16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2bf16] }:$data, ?:{ *:[i32] }:$offset) |
| 62110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN), |
| 62111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62113 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62116 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62117 | GIR_RootConstrainSelectedInstOperands, |
| 62118 | // GIR_Coverage, 3840, |
| 62119 | GIR_EraseRootFromParent_Done, |
| 62120 | // Label 3422: @198958 |
| 62121 | GIM_Reject, |
| 62122 | // Label 3390: @198959 |
| 62123 | GIM_Reject, |
| 62124 | // Label 3367: @198960 |
| 62125 | GIM_Reject, |
| 62126 | // Label 29: @198961 |
| 62127 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3425*/ GIMT_Encode4(201606), |
| 62128 | /*GILLT_s32*//*Label 3423*/ GIMT_Encode4(198980), |
| 62129 | /*GILLT_s64*//*Label 3424*/ GIMT_Encode4(200348), |
| 62130 | // Label 3423: @198980 |
| 62131 | GIM_Try, /*On fail goto*//*Label 3426*/ GIMT_Encode4(200347), |
| 62132 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 62133 | GIM_Try, /*On fail goto*//*Label 3427*/ GIMT_Encode4(199050), // Rule ID 5452 // |
| 62134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62135 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62136 | GIM_CheckHasNoUse, /*MI*/0, |
| 62137 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62139 | // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (BUFFER_ATOMIC_FMAX_ADDR64 anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64), |
| 62141 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62148 | GIR_RootConstrainSelectedInstOperands, |
| 62149 | // GIR_Coverage, 5452, |
| 62150 | GIR_EraseRootFromParent_Done, |
| 62151 | // Label 3427: @199050 |
| 62152 | GIM_Try, /*On fail goto*//*Label 3428*/ GIMT_Encode4(199112), // Rule ID 5456 // |
| 62153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62154 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62155 | GIM_CheckHasNoUse, /*MI*/0, |
| 62156 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62158 | // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64 anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64), |
| 62160 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62166 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62167 | GIR_RootConstrainSelectedInstOperands, |
| 62168 | // GIR_Coverage, 5456, |
| 62169 | GIR_EraseRootFromParent_Done, |
| 62170 | // Label 3428: @199112 |
| 62171 | GIM_Try, /*On fail goto*//*Label 3429*/ GIMT_Encode4(199178), // Rule ID 5450 // |
| 62172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62173 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62177 | // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>> => (BUFFER_ATOMIC_FMAX_ADDR64_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_ADDR64_RTN), |
| 62179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62180 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62186 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62187 | GIR_RootConstrainSelectedInstOperands, |
| 62188 | // GIR_Coverage, 5450, |
| 62189 | GIR_EraseRootFromParent_Done, |
| 62190 | // Label 3429: @199178 |
| 62191 | GIM_Try, /*On fail goto*//*Label 3430*/ GIMT_Encode4(199244), // Rule ID 5454 // |
| 62192 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62193 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62194 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62195 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62197 | // (atomic_load_fmax:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>> => (BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_ADDR64_RTN), |
| 62199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62200 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62207 | GIR_RootConstrainSelectedInstOperands, |
| 62208 | // GIR_Coverage, 5454, |
| 62209 | GIR_EraseRootFromParent_Done, |
| 62210 | // Label 3430: @199244 |
| 62211 | GIM_Try, /*On fail goto*//*Label 3431*/ GIMT_Encode4(199301), // Rule ID 5451 // |
| 62212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62213 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62214 | GIM_CheckHasNoUse, /*MI*/0, |
| 62215 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62217 | // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET), |
| 62219 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62224 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62225 | GIR_RootConstrainSelectedInstOperands, |
| 62226 | // GIR_Coverage, 5451, |
| 62227 | GIR_EraseRootFromParent_Done, |
| 62228 | // Label 3431: @199301 |
| 62229 | GIM_Try, /*On fail goto*//*Label 3432*/ GIMT_Encode4(199358), // Rule ID 5455 // |
| 62230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62231 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62232 | GIM_CheckHasNoUse, /*MI*/0, |
| 62233 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62235 | // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET), |
| 62237 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62242 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62243 | GIR_RootConstrainSelectedInstOperands, |
| 62244 | // GIR_Coverage, 5455, |
| 62245 | GIR_EraseRootFromParent_Done, |
| 62246 | // Label 3432: @199358 |
| 62247 | GIM_Try, /*On fail goto*//*Label 3433*/ GIMT_Encode4(199419), // Rule ID 5449 // |
| 62248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62249 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62251 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62253 | // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>> => (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN), |
| 62255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62256 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62261 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62262 | GIR_RootConstrainSelectedInstOperands, |
| 62263 | // GIR_Coverage, 5449, |
| 62264 | GIR_EraseRootFromParent_Done, |
| 62265 | // Label 3433: @199419 |
| 62266 | GIM_Try, /*On fail goto*//*Label 3434*/ GIMT_Encode4(199480), // Rule ID 5453 // |
| 62267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62268 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62270 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62271 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62272 | // (atomic_load_fmax:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f32>> => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN), |
| 62274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62275 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62281 | GIR_RootConstrainSelectedInstOperands, |
| 62282 | // GIR_Coverage, 5453, |
| 62283 | GIR_EraseRootFromParent_Done, |
| 62284 | // Label 3434: @199480 |
| 62285 | GIM_Try, /*On fail goto*//*Label 3435*/ GIMT_Encode4(199530), // Rule ID 7845 // |
| 62286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 62287 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62288 | GIM_CheckHasNoUse, /*MI*/0, |
| 62289 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62290 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62291 | // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f32>> => (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32), |
| 62293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62294 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62298 | GIR_RootConstrainSelectedInstOperands, |
| 62299 | // GIR_Coverage, 7845, |
| 62300 | GIR_EraseRootFromParent_Done, |
| 62301 | // Label 3435: @199530 |
| 62302 | GIM_Try, /*On fail goto*//*Label 3436*/ GIMT_Encode4(199580), // Rule ID 7847 // |
| 62303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 62304 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62305 | GIM_CheckHasNoUse, /*MI*/0, |
| 62306 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62308 | // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f32>> => (DS_MAX_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32_gfx9), |
| 62310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62311 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62315 | GIR_RootConstrainSelectedInstOperands, |
| 62316 | // GIR_Coverage, 7847, |
| 62317 | GIR_EraseRootFromParent_Done, |
| 62318 | // Label 3436: @199580 |
| 62319 | GIM_Try, /*On fail goto*//*Label 3437*/ GIMT_Encode4(199630), // Rule ID 7849 // |
| 62320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 62321 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 62322 | GIM_CheckHasNoUse, /*MI*/0, |
| 62323 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62325 | // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f32>> => (DS_MAX_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 62326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F32), |
| 62327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62328 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62331 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62332 | GIR_RootConstrainSelectedInstOperands, |
| 62333 | // GIR_Coverage, 7849, |
| 62334 | GIR_EraseRootFromParent_Done, |
| 62335 | // Label 3437: @199630 |
| 62336 | GIM_Try, /*On fail goto*//*Label 3438*/ GIMT_Encode4(199684), // Rule ID 7844 // |
| 62337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 62338 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62340 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62342 | // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f32>> => (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32), |
| 62344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62346 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62350 | GIR_RootConstrainSelectedInstOperands, |
| 62351 | // GIR_Coverage, 7844, |
| 62352 | GIR_EraseRootFromParent_Done, |
| 62353 | // Label 3438: @199684 |
| 62354 | GIM_Try, /*On fail goto*//*Label 3439*/ GIMT_Encode4(199738), // Rule ID 7846 // |
| 62355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 62356 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62358 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62360 | // (atomic_load_fmax:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_local_f32>> => (DS_MAX_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32_gfx9), |
| 62362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62364 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62368 | GIR_RootConstrainSelectedInstOperands, |
| 62369 | // GIR_Coverage, 7846, |
| 62370 | GIR_EraseRootFromParent_Done, |
| 62371 | // Label 3439: @199738 |
| 62372 | GIM_Try, /*On fail goto*//*Label 3440*/ GIMT_Encode4(199792), // Rule ID 7848 // |
| 62373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 62374 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 62375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62376 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62378 | // (atomic_load_fmax_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f32>> => (DS_MAX_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 62379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F32), |
| 62380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62382 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62385 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62386 | GIR_RootConstrainSelectedInstOperands, |
| 62387 | // GIR_Coverage, 7848, |
| 62388 | GIR_EraseRootFromParent_Done, |
| 62389 | // Label 3440: @199792 |
| 62390 | GIM_Try, /*On fail goto*//*Label 3441*/ GIMT_Encode4(199849), // Rule ID 3737 // |
| 62391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 62392 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62393 | GIM_CheckHasNoUse, /*MI*/0, |
| 62394 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62395 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 62396 | // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 62397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR), |
| 62398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 62399 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 62401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62403 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62404 | GIR_RootConstrainSelectedInstOperands, |
| 62405 | // GIR_Coverage, 3737, |
| 62406 | GIR_EraseRootFromParent_Done, |
| 62407 | // Label 3441: @199849 |
| 62408 | GIM_Try, /*On fail goto*//*Label 3442*/ GIMT_Encode4(199910), // Rule ID 3739 // |
| 62409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 62410 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62412 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 62414 | // (atomic_load_fmax:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>> => (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 62415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN), |
| 62416 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 62418 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 62420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62422 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62423 | GIR_RootConstrainSelectedInstOperands, |
| 62424 | // GIR_Coverage, 3739, |
| 62425 | GIR_EraseRootFromParent_Done, |
| 62426 | // Label 3442: @199910 |
| 62427 | GIM_Try, /*On fail goto*//*Label 3443*/ GIMT_Encode4(199962), // Rule ID 3736 // |
| 62428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 62429 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62430 | GIM_CheckHasNoUse, /*MI*/0, |
| 62431 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62433 | // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX), |
| 62435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62436 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62440 | GIR_RootConstrainSelectedInstOperands, |
| 62441 | // GIR_Coverage, 3736, |
| 62442 | GIR_EraseRootFromParent_Done, |
| 62443 | // Label 3443: @199962 |
| 62444 | GIM_Try, /*On fail goto*//*Label 3444*/ GIMT_Encode4(200018), // Rule ID 3738 // |
| 62445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 62446 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62448 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62450 | // (atomic_load_fmax:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>> => (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN), |
| 62452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62454 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62458 | GIR_RootConstrainSelectedInstOperands, |
| 62459 | // GIR_Coverage, 3738, |
| 62460 | GIR_EraseRootFromParent_Done, |
| 62461 | // Label 3444: @200018 |
| 62462 | GIM_Try, /*On fail goto*//*Label 3445*/ GIMT_Encode4(200071), // Rule ID 3341 // |
| 62463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 62464 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62465 | GIM_CheckHasNoUse, /*MI*/0, |
| 62466 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62468 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>> => (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX), |
| 62470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62471 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62474 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62475 | GIR_RootConstrainSelectedInstOperands, |
| 62476 | // GIR_Coverage, 3341, |
| 62477 | GIR_EraseRootFromParent_Done, |
| 62478 | // Label 3445: @200071 |
| 62479 | GIM_Try, /*On fail goto*//*Label 3446*/ GIMT_Encode4(200123), // Rule ID 3401 // |
| 62480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 62481 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62482 | GIM_CheckHasNoUse, /*MI*/0, |
| 62483 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62485 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f32>> => (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX), |
| 62487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62488 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62491 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62492 | GIR_RootConstrainSelectedInstOperands, |
| 62493 | // GIR_Coverage, 3401, |
| 62494 | GIR_EraseRootFromParent_Done, |
| 62495 | // Label 3446: @200123 |
| 62496 | GIM_Try, /*On fail goto*//*Label 3447*/ GIMT_Encode4(200176), // Rule ID 3751 // |
| 62497 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 62498 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62499 | GIM_CheckHasNoUse, /*MI*/0, |
| 62500 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62501 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62502 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f32>> => (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX), |
| 62504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62505 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62508 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62509 | GIR_RootConstrainSelectedInstOperands, |
| 62510 | // GIR_Coverage, 3751, |
| 62511 | GIR_EraseRootFromParent_Done, |
| 62512 | // Label 3447: @200176 |
| 62513 | GIM_Try, /*On fail goto*//*Label 3448*/ GIMT_Encode4(200233), // Rule ID 3340 // |
| 62514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 62515 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62517 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62519 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>> => (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN), |
| 62521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62523 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62526 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62527 | GIR_RootConstrainSelectedInstOperands, |
| 62528 | // GIR_Coverage, 3340, |
| 62529 | GIR_EraseRootFromParent_Done, |
| 62530 | // Label 3448: @200233 |
| 62531 | GIM_Try, /*On fail goto*//*Label 3449*/ GIMT_Encode4(200289), // Rule ID 3400 // |
| 62532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 62533 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62535 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62536 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62537 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_global_f32>> => (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN), |
| 62539 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62541 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62544 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62545 | GIR_RootConstrainSelectedInstOperands, |
| 62546 | // GIR_Coverage, 3400, |
| 62547 | GIR_EraseRootFromParent_Done, |
| 62548 | // Label 3449: @200289 |
| 62549 | GIM_Try, /*On fail goto*//*Label 3450*/ GIMT_Encode4(200346), // Rule ID 3750 // |
| 62550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 62551 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 62553 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62554 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62555 | // (atomic_load_fmax:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmax_flat_f32>> => (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 62556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN), |
| 62557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62559 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62562 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62563 | GIR_RootConstrainSelectedInstOperands, |
| 62564 | // GIR_Coverage, 3750, |
| 62565 | GIR_EraseRootFromParent_Done, |
| 62566 | // Label 3450: @200346 |
| 62567 | GIM_Reject, |
| 62568 | // Label 3426: @200347 |
| 62569 | GIM_Reject, |
| 62570 | // Label 3424: @200348 |
| 62571 | GIM_Try, /*On fail goto*//*Label 3451*/ GIMT_Encode4(201605), |
| 62572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 62573 | GIM_Try, /*On fail goto*//*Label 3452*/ GIMT_Encode4(200418), // Rule ID 5468 // |
| 62574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62575 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62576 | GIM_CheckHasNoUse, /*MI*/0, |
| 62577 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62578 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62579 | // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (BUFFER_ATOMIC_MAX_F64_ADDR64 anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64), |
| 62581 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62587 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62588 | GIR_RootConstrainSelectedInstOperands, |
| 62589 | // GIR_Coverage, 5468, |
| 62590 | GIR_EraseRootFromParent_Done, |
| 62591 | // Label 3452: @200418 |
| 62592 | GIM_Try, /*On fail goto*//*Label 3453*/ GIMT_Encode4(200480), // Rule ID 5472 // |
| 62593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62594 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62595 | GIM_CheckHasNoUse, /*MI*/0, |
| 62596 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62598 | // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64 anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64), |
| 62600 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62607 | GIR_RootConstrainSelectedInstOperands, |
| 62608 | // GIR_Coverage, 5472, |
| 62609 | GIR_EraseRootFromParent_Done, |
| 62610 | // Label 3453: @200480 |
| 62611 | GIM_Try, /*On fail goto*//*Label 3454*/ GIMT_Encode4(200546), // Rule ID 5466 // |
| 62612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62613 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62617 | // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>> => (BUFFER_ATOMIC_MAX_F64_ADDR64_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_ADDR64_RTN), |
| 62619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62620 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62627 | GIR_RootConstrainSelectedInstOperands, |
| 62628 | // GIR_Coverage, 5466, |
| 62629 | GIR_EraseRootFromParent_Done, |
| 62630 | // Label 3454: @200546 |
| 62631 | GIM_Try, /*On fail goto*//*Label 3455*/ GIMT_Encode4(200612), // Rule ID 5470 // |
| 62632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62633 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62635 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62637 | // (atomic_load_fmax:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_ADDR64_RTN), |
| 62639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62640 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62646 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62647 | GIR_RootConstrainSelectedInstOperands, |
| 62648 | // GIR_Coverage, 5470, |
| 62649 | GIR_EraseRootFromParent_Done, |
| 62650 | // Label 3455: @200612 |
| 62651 | GIM_Try, /*On fail goto*//*Label 3456*/ GIMT_Encode4(200669), // Rule ID 5467 // |
| 62652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62653 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62654 | GIM_CheckHasNoUse, /*MI*/0, |
| 62655 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62657 | // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET), |
| 62659 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62665 | GIR_RootConstrainSelectedInstOperands, |
| 62666 | // GIR_Coverage, 5467, |
| 62667 | GIR_EraseRootFromParent_Done, |
| 62668 | // Label 3456: @200669 |
| 62669 | GIM_Try, /*On fail goto*//*Label 3457*/ GIMT_Encode4(200726), // Rule ID 5471 // |
| 62670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62671 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62672 | GIM_CheckHasNoUse, /*MI*/0, |
| 62673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62674 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62675 | // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET), |
| 62677 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62683 | GIR_RootConstrainSelectedInstOperands, |
| 62684 | // GIR_Coverage, 5471, |
| 62685 | GIR_EraseRootFromParent_Done, |
| 62686 | // Label 3457: @200726 |
| 62687 | GIM_Try, /*On fail goto*//*Label 3458*/ GIMT_Encode4(200787), // Rule ID 5465 // |
| 62688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62689 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62691 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62693 | // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>> => (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN), |
| 62695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62696 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62701 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62702 | GIR_RootConstrainSelectedInstOperands, |
| 62703 | // GIR_Coverage, 5465, |
| 62704 | GIR_EraseRootFromParent_Done, |
| 62705 | // Label 3458: @200787 |
| 62706 | GIM_Try, /*On fail goto*//*Label 3459*/ GIMT_Encode4(200848), // Rule ID 5469 // |
| 62707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 62708 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62710 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62711 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 62712 | // (atomic_load_fmax:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmax_global_f64>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN), |
| 62714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 62715 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 62718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62720 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62721 | GIR_RootConstrainSelectedInstOperands, |
| 62722 | // GIR_Coverage, 5469, |
| 62723 | GIR_EraseRootFromParent_Done, |
| 62724 | // Label 3459: @200848 |
| 62725 | GIM_Try, /*On fail goto*//*Label 3460*/ GIMT_Encode4(200898), // Rule ID 7944 // |
| 62726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 62727 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62728 | GIM_CheckHasNoUse, /*MI*/0, |
| 62729 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62730 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62731 | // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_noret_f64>> => (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64), |
| 62733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62734 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62737 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62738 | GIR_RootConstrainSelectedInstOperands, |
| 62739 | // GIR_Coverage, 7944, |
| 62740 | GIR_EraseRootFromParent_Done, |
| 62741 | // Label 3460: @200898 |
| 62742 | GIM_Try, /*On fail goto*//*Label 3461*/ GIMT_Encode4(200948), // Rule ID 7946 // |
| 62743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 62744 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62745 | GIM_CheckHasNoUse, /*MI*/0, |
| 62746 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62748 | // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_noret_f64>> => (DS_MAX_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64_gfx9), |
| 62750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62751 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62754 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62755 | GIR_RootConstrainSelectedInstOperands, |
| 62756 | // GIR_Coverage, 7946, |
| 62757 | GIR_EraseRootFromParent_Done, |
| 62758 | // Label 3461: @200948 |
| 62759 | GIM_Try, /*On fail goto*//*Label 3462*/ GIMT_Encode4(200998), // Rule ID 7948 // |
| 62760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 62761 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 62762 | GIM_CheckHasNoUse, /*MI*/0, |
| 62763 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62765 | // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_noret_f64>> => (DS_MAX_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 62766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_F64), |
| 62767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62768 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62771 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62772 | GIR_RootConstrainSelectedInstOperands, |
| 62773 | // GIR_Coverage, 7948, |
| 62774 | GIR_EraseRootFromParent_Done, |
| 62775 | // Label 3462: @200998 |
| 62776 | GIM_Try, /*On fail goto*//*Label 3463*/ GIMT_Encode4(201052), // Rule ID 7943 // |
| 62777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 62778 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62780 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62781 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62782 | // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_m0_f64>> => (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64), |
| 62784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62786 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62789 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62790 | GIR_RootConstrainSelectedInstOperands, |
| 62791 | // GIR_Coverage, 7943, |
| 62792 | GIR_EraseRootFromParent_Done, |
| 62793 | // Label 3463: @201052 |
| 62794 | GIM_Try, /*On fail goto*//*Label 3464*/ GIMT_Encode4(201106), // Rule ID 7945 // |
| 62795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 62796 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 62797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62798 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62800 | // (atomic_load_fmax:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_local_f64>> => (DS_MAX_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 62801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64_gfx9), |
| 62802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62804 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62806 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62807 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62808 | GIR_RootConstrainSelectedInstOperands, |
| 62809 | // GIR_Coverage, 7945, |
| 62810 | GIR_EraseRootFromParent_Done, |
| 62811 | // Label 3464: @201106 |
| 62812 | GIM_Try, /*On fail goto*//*Label 3465*/ GIMT_Encode4(201160), // Rule ID 7947 // |
| 62813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 62814 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 62815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62816 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62817 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 62818 | // (atomic_load_fmax_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmax_region_m0_f64>> => (DS_MAX_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 62819 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MAX_RTN_F64), |
| 62820 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 62822 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 62823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62825 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62826 | GIR_RootConstrainSelectedInstOperands, |
| 62827 | // GIR_Coverage, 7947, |
| 62828 | GIR_EraseRootFromParent_Done, |
| 62829 | // Label 3465: @201160 |
| 62830 | GIM_Try, /*On fail goto*//*Label 3466*/ GIMT_Encode4(201217), // Rule ID 3799 // |
| 62831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 62832 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62833 | GIM_CheckHasNoUse, /*MI*/0, |
| 62834 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62835 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 62836 | // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 62837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR), |
| 62838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 62839 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 62841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62843 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62844 | GIR_RootConstrainSelectedInstOperands, |
| 62845 | // GIR_Coverage, 3799, |
| 62846 | GIR_EraseRootFromParent_Done, |
| 62847 | // Label 3466: @201217 |
| 62848 | GIM_Try, /*On fail goto*//*Label 3467*/ GIMT_Encode4(201278), // Rule ID 3801 // |
| 62849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 62850 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62852 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 62854 | // (atomic_load_fmax:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>> => (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 62855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN), |
| 62856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 62858 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 62860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 62861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62862 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62863 | GIR_RootConstrainSelectedInstOperands, |
| 62864 | // GIR_Coverage, 3801, |
| 62865 | GIR_EraseRootFromParent_Done, |
| 62866 | // Label 3467: @201278 |
| 62867 | GIM_Try, /*On fail goto*//*Label 3468*/ GIMT_Encode4(201330), // Rule ID 3798 // |
| 62868 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 62869 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62870 | GIM_CheckHasNoUse, /*MI*/0, |
| 62871 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62873 | // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (GLOBAL_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64), |
| 62875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62876 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62880 | GIR_RootConstrainSelectedInstOperands, |
| 62881 | // GIR_Coverage, 3798, |
| 62882 | GIR_EraseRootFromParent_Done, |
| 62883 | // Label 3468: @201330 |
| 62884 | GIM_Try, /*On fail goto*//*Label 3469*/ GIMT_Encode4(201386), // Rule ID 3800 // |
| 62885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 62886 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62888 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 62890 | // (atomic_load_fmax:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>> => (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN), |
| 62892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62894 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62898 | GIR_RootConstrainSelectedInstOperands, |
| 62899 | // GIR_Coverage, 3800, |
| 62900 | GIR_EraseRootFromParent_Done, |
| 62901 | // Label 3469: @201386 |
| 62902 | GIM_Try, /*On fail goto*//*Label 3470*/ GIMT_Encode4(201439), // Rule ID 3345 // |
| 62903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 62904 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62905 | GIM_CheckHasNoUse, /*MI*/0, |
| 62906 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62908 | // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_noret_f64>> => (FLAT_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64), |
| 62910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62911 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62915 | GIR_RootConstrainSelectedInstOperands, |
| 62916 | // GIR_Coverage, 3345, |
| 62917 | GIR_EraseRootFromParent_Done, |
| 62918 | // Label 3470: @201439 |
| 62919 | GIM_Try, /*On fail goto*//*Label 3471*/ GIMT_Encode4(201491), // Rule ID 3405 // |
| 62920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 62921 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62922 | GIM_CheckHasNoUse, /*MI*/0, |
| 62923 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62924 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62925 | // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_noret_f64>> => (FLAT_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64), |
| 62927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62928 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62931 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62932 | GIR_RootConstrainSelectedInstOperands, |
| 62933 | // GIR_Coverage, 3405, |
| 62934 | GIR_EraseRootFromParent_Done, |
| 62935 | // Label 3471: @201491 |
| 62936 | GIM_Try, /*On fail goto*//*Label 3472*/ GIMT_Encode4(201548), // Rule ID 3344 // |
| 62937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 62938 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62940 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62941 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62942 | // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_flat_f64>> => (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN), |
| 62944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62946 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62950 | GIR_RootConstrainSelectedInstOperands, |
| 62951 | // GIR_Coverage, 3344, |
| 62952 | GIR_EraseRootFromParent_Done, |
| 62953 | // Label 3472: @201548 |
| 62954 | GIM_Try, /*On fail goto*//*Label 3473*/ GIMT_Encode4(201604), // Rule ID 3404 // |
| 62955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 62956 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 62958 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62959 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 62960 | // (atomic_load_fmax:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmax_global_f64>> => (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 62961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN), |
| 62962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 62963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 62964 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 62965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 62966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 62967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62968 | GIR_RootConstrainSelectedInstOperands, |
| 62969 | // GIR_Coverage, 3404, |
| 62970 | GIR_EraseRootFromParent_Done, |
| 62971 | // Label 3473: @201604 |
| 62972 | GIM_Reject, |
| 62973 | // Label 3451: @201605 |
| 62974 | GIM_Reject, |
| 62975 | // Label 3425: @201606 |
| 62976 | GIM_Reject, |
| 62977 | // Label 30: @201607 |
| 62978 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3476*/ GIMT_Encode4(204252), |
| 62979 | /*GILLT_s32*//*Label 3474*/ GIMT_Encode4(201626), |
| 62980 | /*GILLT_s64*//*Label 3475*/ GIMT_Encode4(202994), |
| 62981 | // Label 3474: @201626 |
| 62982 | GIM_Try, /*On fail goto*//*Label 3477*/ GIMT_Encode4(202993), |
| 62983 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 62984 | GIM_Try, /*On fail goto*//*Label 3478*/ GIMT_Encode4(201696), // Rule ID 5444 // |
| 62985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 62986 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 62987 | GIM_CheckHasNoUse, /*MI*/0, |
| 62988 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 62989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 62990 | // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (BUFFER_ATOMIC_FMIN_ADDR64 anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 62991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64), |
| 62992 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 62993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 62994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 62995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 62996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 62997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 62998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 62999 | GIR_RootConstrainSelectedInstOperands, |
| 63000 | // GIR_Coverage, 5444, |
| 63001 | GIR_EraseRootFromParent_Done, |
| 63002 | // Label 3478: @201696 |
| 63003 | GIM_Try, /*On fail goto*//*Label 3479*/ GIMT_Encode4(201758), // Rule ID 5448 // |
| 63004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63006 | GIM_CheckHasNoUse, /*MI*/0, |
| 63007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63009 | // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64 anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64), |
| 63011 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63018 | GIR_RootConstrainSelectedInstOperands, |
| 63019 | // GIR_Coverage, 5448, |
| 63020 | GIR_EraseRootFromParent_Done, |
| 63021 | // Label 3479: @201758 |
| 63022 | GIM_Try, /*On fail goto*//*Label 3480*/ GIMT_Encode4(201824), // Rule ID 5442 // |
| 63023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63024 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63028 | // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>> => (BUFFER_ATOMIC_FMIN_ADDR64_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_ADDR64_RTN), |
| 63030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63031 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63037 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63038 | GIR_RootConstrainSelectedInstOperands, |
| 63039 | // GIR_Coverage, 5442, |
| 63040 | GIR_EraseRootFromParent_Done, |
| 63041 | // Label 3480: @201824 |
| 63042 | GIM_Try, /*On fail goto*//*Label 3481*/ GIMT_Encode4(201890), // Rule ID 5446 // |
| 63043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63044 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63046 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63047 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63048 | // (atomic_load_fmin:{ *:[f32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>> => (BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63049 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_ADDR64_RTN), |
| 63050 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63051 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63058 | GIR_RootConstrainSelectedInstOperands, |
| 63059 | // GIR_Coverage, 5446, |
| 63060 | GIR_EraseRootFromParent_Done, |
| 63061 | // Label 3481: @201890 |
| 63062 | GIM_Try, /*On fail goto*//*Label 3482*/ GIMT_Encode4(201947), // Rule ID 5443 // |
| 63063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63064 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63065 | GIM_CheckHasNoUse, /*MI*/0, |
| 63066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63068 | // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET), |
| 63070 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63075 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63076 | GIR_RootConstrainSelectedInstOperands, |
| 63077 | // GIR_Coverage, 5443, |
| 63078 | GIR_EraseRootFromParent_Done, |
| 63079 | // Label 3482: @201947 |
| 63080 | GIM_Try, /*On fail goto*//*Label 3483*/ GIMT_Encode4(202004), // Rule ID 5447 // |
| 63081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63082 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63083 | GIM_CheckHasNoUse, /*MI*/0, |
| 63084 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63086 | // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET), |
| 63088 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63094 | GIR_RootConstrainSelectedInstOperands, |
| 63095 | // GIR_Coverage, 5447, |
| 63096 | GIR_EraseRootFromParent_Done, |
| 63097 | // Label 3483: @202004 |
| 63098 | GIM_Try, /*On fail goto*//*Label 3484*/ GIMT_Encode4(202065), // Rule ID 5441 // |
| 63099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63100 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63102 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63103 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63104 | // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>> => (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN), |
| 63106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63107 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63113 | GIR_RootConstrainSelectedInstOperands, |
| 63114 | // GIR_Coverage, 5441, |
| 63115 | GIR_EraseRootFromParent_Done, |
| 63116 | // Label 3484: @202065 |
| 63117 | GIM_Try, /*On fail goto*//*Label 3485*/ GIMT_Encode4(202126), // Rule ID 5445 // |
| 63118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 63119 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63121 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63122 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63123 | // (atomic_load_fmin:{ *:[f32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f32>> => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN), |
| 63125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63126 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63132 | GIR_RootConstrainSelectedInstOperands, |
| 63133 | // GIR_Coverage, 5445, |
| 63134 | GIR_EraseRootFromParent_Done, |
| 63135 | // Label 3485: @202126 |
| 63136 | GIM_Try, /*On fail goto*//*Label 3486*/ GIMT_Encode4(202176), // Rule ID 7839 // |
| 63137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 63138 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63139 | GIM_CheckHasNoUse, /*MI*/0, |
| 63140 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63142 | // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f32>> => (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32), |
| 63144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63145 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63148 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63149 | GIR_RootConstrainSelectedInstOperands, |
| 63150 | // GIR_Coverage, 7839, |
| 63151 | GIR_EraseRootFromParent_Done, |
| 63152 | // Label 3486: @202176 |
| 63153 | GIM_Try, /*On fail goto*//*Label 3487*/ GIMT_Encode4(202226), // Rule ID 7841 // |
| 63154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 63155 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63156 | GIM_CheckHasNoUse, /*MI*/0, |
| 63157 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63159 | // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f32>> => (DS_MIN_F32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32_gfx9), |
| 63161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63162 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63166 | GIR_RootConstrainSelectedInstOperands, |
| 63167 | // GIR_Coverage, 7841, |
| 63168 | GIR_EraseRootFromParent_Done, |
| 63169 | // Label 3487: @202226 |
| 63170 | GIM_Try, /*On fail goto*//*Label 3488*/ GIMT_Encode4(202276), // Rule ID 7843 // |
| 63171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 63172 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 63173 | GIM_CheckHasNoUse, /*MI*/0, |
| 63174 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63176 | // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f32>> => (DS_MIN_F32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 63177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F32), |
| 63178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63179 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63183 | GIR_RootConstrainSelectedInstOperands, |
| 63184 | // GIR_Coverage, 7843, |
| 63185 | GIR_EraseRootFromParent_Done, |
| 63186 | // Label 3488: @202276 |
| 63187 | GIM_Try, /*On fail goto*//*Label 3489*/ GIMT_Encode4(202330), // Rule ID 7838 // |
| 63188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 63189 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63191 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63193 | // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f32>> => (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32), |
| 63195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63197 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63200 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63201 | GIR_RootConstrainSelectedInstOperands, |
| 63202 | // GIR_Coverage, 7838, |
| 63203 | GIR_EraseRootFromParent_Done, |
| 63204 | // Label 3489: @202330 |
| 63205 | GIM_Try, /*On fail goto*//*Label 3490*/ GIMT_Encode4(202384), // Rule ID 7840 // |
| 63206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 63207 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63209 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63211 | // (atomic_load_fmin:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_local_f32>> => (DS_MIN_RTN_F32_gfx9:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32_gfx9), |
| 63213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63215 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63218 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63219 | GIR_RootConstrainSelectedInstOperands, |
| 63220 | // GIR_Coverage, 7840, |
| 63221 | GIR_EraseRootFromParent_Done, |
| 63222 | // Label 3490: @202384 |
| 63223 | GIM_Try, /*On fail goto*//*Label 3491*/ GIMT_Encode4(202438), // Rule ID 7842 // |
| 63224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 63225 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 63226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63227 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63229 | // (atomic_load_fmin_glue:{ *:[f32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f32>> => (DS_MIN_RTN_F32:{ *:[f32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[f32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 63230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F32), |
| 63231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63233 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63236 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63237 | GIR_RootConstrainSelectedInstOperands, |
| 63238 | // GIR_Coverage, 7842, |
| 63239 | GIR_EraseRootFromParent_Done, |
| 63240 | // Label 3491: @202438 |
| 63241 | GIM_Try, /*On fail goto*//*Label 3492*/ GIMT_Encode4(202495), // Rule ID 3733 // |
| 63242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 63243 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63244 | GIM_CheckHasNoUse, /*MI*/0, |
| 63245 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 63247 | // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 63248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR), |
| 63249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 63250 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 63252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63255 | GIR_RootConstrainSelectedInstOperands, |
| 63256 | // GIR_Coverage, 3733, |
| 63257 | GIR_EraseRootFromParent_Done, |
| 63258 | // Label 3492: @202495 |
| 63259 | GIM_Try, /*On fail goto*//*Label 3493*/ GIMT_Encode4(202556), // Rule ID 3735 // |
| 63260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 63261 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63263 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 63265 | // (atomic_load_fmin:{ *:[f32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>> => (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 63266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN), |
| 63267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 63269 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 63271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63274 | GIR_RootConstrainSelectedInstOperands, |
| 63275 | // GIR_Coverage, 3735, |
| 63276 | GIR_EraseRootFromParent_Done, |
| 63277 | // Label 3493: @202556 |
| 63278 | GIM_Try, /*On fail goto*//*Label 3494*/ GIMT_Encode4(202608), // Rule ID 3732 // |
| 63279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 63280 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63281 | GIM_CheckHasNoUse, /*MI*/0, |
| 63282 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 63284 | // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN), |
| 63286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63287 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63291 | GIR_RootConstrainSelectedInstOperands, |
| 63292 | // GIR_Coverage, 3732, |
| 63293 | GIR_EraseRootFromParent_Done, |
| 63294 | // Label 3494: @202608 |
| 63295 | GIM_Try, /*On fail goto*//*Label 3495*/ GIMT_Encode4(202664), // Rule ID 3734 // |
| 63296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 63297 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63299 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 63301 | // (atomic_load_fmin:{ *:[f32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>> => (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN), |
| 63303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63305 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63309 | GIR_RootConstrainSelectedInstOperands, |
| 63310 | // GIR_Coverage, 3734, |
| 63311 | GIR_EraseRootFromParent_Done, |
| 63312 | // Label 3495: @202664 |
| 63313 | GIM_Try, /*On fail goto*//*Label 3496*/ GIMT_Encode4(202717), // Rule ID 3339 // |
| 63314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 63315 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63316 | GIM_CheckHasNoUse, /*MI*/0, |
| 63317 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63319 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>> => (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN), |
| 63321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63322 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63325 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63326 | GIR_RootConstrainSelectedInstOperands, |
| 63327 | // GIR_Coverage, 3339, |
| 63328 | GIR_EraseRootFromParent_Done, |
| 63329 | // Label 3496: @202717 |
| 63330 | GIM_Try, /*On fail goto*//*Label 3497*/ GIMT_Encode4(202769), // Rule ID 3399 // |
| 63331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 63332 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63333 | GIM_CheckHasNoUse, /*MI*/0, |
| 63334 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63336 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f32>> => (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN), |
| 63338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63339 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63342 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63343 | GIR_RootConstrainSelectedInstOperands, |
| 63344 | // GIR_Coverage, 3399, |
| 63345 | GIR_EraseRootFromParent_Done, |
| 63346 | // Label 3497: @202769 |
| 63347 | GIM_Try, /*On fail goto*//*Label 3498*/ GIMT_Encode4(202822), // Rule ID 3749 // |
| 63348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 63349 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63350 | GIM_CheckHasNoUse, /*MI*/0, |
| 63351 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63352 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63353 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f32>> => (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN), |
| 63355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63356 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63359 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63360 | GIR_RootConstrainSelectedInstOperands, |
| 63361 | // GIR_Coverage, 3749, |
| 63362 | GIR_EraseRootFromParent_Done, |
| 63363 | // Label 3498: @202822 |
| 63364 | GIM_Try, /*On fail goto*//*Label 3499*/ GIMT_Encode4(202879), // Rule ID 3338 // |
| 63365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 63366 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63368 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63370 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>> => (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN), |
| 63372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63374 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63378 | GIR_RootConstrainSelectedInstOperands, |
| 63379 | // GIR_Coverage, 3338, |
| 63380 | GIR_EraseRootFromParent_Done, |
| 63381 | // Label 3499: @202879 |
| 63382 | GIM_Try, /*On fail goto*//*Label 3500*/ GIMT_Encode4(202935), // Rule ID 3398 // |
| 63383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatAddressSpace), |
| 63384 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63386 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63388 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_global_f32>> => (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN), |
| 63390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63392 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63395 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63396 | GIR_RootConstrainSelectedInstOperands, |
| 63397 | // GIR_Coverage, 3398, |
| 63398 | GIR_EraseRootFromParent_Done, |
| 63399 | // Label 3500: @202935 |
| 63400 | GIM_Try, /*On fail goto*//*Label 3501*/ GIMT_Encode4(202992), // Rule ID 3748 // |
| 63401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 63402 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63404 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63405 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63406 | // (atomic_load_fmin:{ *:[f32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_atomic_load_fmin_flat_f32>> => (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 63407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN), |
| 63408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63410 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63414 | GIR_RootConstrainSelectedInstOperands, |
| 63415 | // GIR_Coverage, 3748, |
| 63416 | GIR_EraseRootFromParent_Done, |
| 63417 | // Label 3501: @202992 |
| 63418 | GIM_Reject, |
| 63419 | // Label 3477: @202993 |
| 63420 | GIM_Reject, |
| 63421 | // Label 3475: @202994 |
| 63422 | GIM_Try, /*On fail goto*//*Label 3502*/ GIMT_Encode4(204251), |
| 63423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 63424 | GIM_Try, /*On fail goto*//*Label 3503*/ GIMT_Encode4(203064), // Rule ID 5460 // |
| 63425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63426 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63427 | GIM_CheckHasNoUse, /*MI*/0, |
| 63428 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63429 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63430 | // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (BUFFER_ATOMIC_MIN_F64_ADDR64 anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64), |
| 63432 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63438 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63439 | GIR_RootConstrainSelectedInstOperands, |
| 63440 | // GIR_Coverage, 5460, |
| 63441 | GIR_EraseRootFromParent_Done, |
| 63442 | // Label 3503: @203064 |
| 63443 | GIM_Try, /*On fail goto*//*Label 3504*/ GIMT_Encode4(203126), // Rule ID 5464 // |
| 63444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63445 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63446 | GIM_CheckHasNoUse, /*MI*/0, |
| 63447 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63449 | // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64 anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64), |
| 63451 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63458 | GIR_RootConstrainSelectedInstOperands, |
| 63459 | // GIR_Coverage, 5464, |
| 63460 | GIR_EraseRootFromParent_Done, |
| 63461 | // Label 3504: @203126 |
| 63462 | GIM_Try, /*On fail goto*//*Label 3505*/ GIMT_Encode4(203192), // Rule ID 5458 // |
| 63463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63464 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63465 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63466 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63468 | // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>> => (BUFFER_ATOMIC_MIN_F64_ADDR64_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_ADDR64_RTN), |
| 63470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63471 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63477 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63478 | GIR_RootConstrainSelectedInstOperands, |
| 63479 | // GIR_Coverage, 5458, |
| 63480 | GIR_EraseRootFromParent_Done, |
| 63481 | // Label 3505: @203192 |
| 63482 | GIM_Try, /*On fail goto*//*Label 3506*/ GIMT_Encode4(203258), // Rule ID 5462 // |
| 63483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63484 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63486 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63488 | // (atomic_load_fmin:{ *:[f64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_ADDR64_RTN), |
| 63490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63491 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63497 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63498 | GIR_RootConstrainSelectedInstOperands, |
| 63499 | // GIR_Coverage, 5462, |
| 63500 | GIR_EraseRootFromParent_Done, |
| 63501 | // Label 3506: @203258 |
| 63502 | GIM_Try, /*On fail goto*//*Label 3507*/ GIMT_Encode4(203315), // Rule ID 5459 // |
| 63503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63504 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63505 | GIM_CheckHasNoUse, /*MI*/0, |
| 63506 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63507 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63508 | // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET), |
| 63510 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63515 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63516 | GIR_RootConstrainSelectedInstOperands, |
| 63517 | // GIR_Coverage, 5459, |
| 63518 | GIR_EraseRootFromParent_Done, |
| 63519 | // Label 3507: @203315 |
| 63520 | GIM_Try, /*On fail goto*//*Label 3508*/ GIMT_Encode4(203372), // Rule ID 5463 // |
| 63521 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63522 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63523 | GIM_CheckHasNoUse, /*MI*/0, |
| 63524 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63526 | // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET), |
| 63528 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63533 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63534 | GIR_RootConstrainSelectedInstOperands, |
| 63535 | // GIR_Coverage, 5463, |
| 63536 | GIR_EraseRootFromParent_Done, |
| 63537 | // Label 3508: @203372 |
| 63538 | GIM_Try, /*On fail goto*//*Label 3509*/ GIMT_Encode4(203433), // Rule ID 5457 // |
| 63539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63540 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63542 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63543 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63544 | // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>> => (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN), |
| 63546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63547 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63552 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63553 | GIR_RootConstrainSelectedInstOperands, |
| 63554 | // GIR_Coverage, 5457, |
| 63555 | GIR_EraseRootFromParent_Done, |
| 63556 | // Label 3509: @203433 |
| 63557 | GIM_Try, /*On fail goto*//*Label 3510*/ GIMT_Encode4(203494), // Rule ID 5461 // |
| 63558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 63559 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63561 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63563 | // (atomic_load_fmin:{ *:[f64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$vdata_in)<<P:Predicate_atomic_load_fmin_global_f64>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN), |
| 63565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63566 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63572 | GIR_RootConstrainSelectedInstOperands, |
| 63573 | // GIR_Coverage, 5461, |
| 63574 | GIR_EraseRootFromParent_Done, |
| 63575 | // Label 3510: @203494 |
| 63576 | GIM_Try, /*On fail goto*//*Label 3511*/ GIMT_Encode4(203544), // Rule ID 7938 // |
| 63577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 63578 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63579 | GIM_CheckHasNoUse, /*MI*/0, |
| 63580 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63582 | // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_noret_f64>> => (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64), |
| 63584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63585 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63588 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63589 | GIR_RootConstrainSelectedInstOperands, |
| 63590 | // GIR_Coverage, 7938, |
| 63591 | GIR_EraseRootFromParent_Done, |
| 63592 | // Label 3511: @203544 |
| 63593 | GIM_Try, /*On fail goto*//*Label 3512*/ GIMT_Encode4(203594), // Rule ID 7940 // |
| 63594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 63595 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63596 | GIM_CheckHasNoUse, /*MI*/0, |
| 63597 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63599 | // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_noret_f64>> => (DS_MIN_F64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64_gfx9), |
| 63601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63602 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63605 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63606 | GIR_RootConstrainSelectedInstOperands, |
| 63607 | // GIR_Coverage, 7940, |
| 63608 | GIR_EraseRootFromParent_Done, |
| 63609 | // Label 3512: @203594 |
| 63610 | GIM_Try, /*On fail goto*//*Label 3513*/ GIMT_Encode4(203644), // Rule ID 7942 // |
| 63611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 63612 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 63613 | GIM_CheckHasNoUse, /*MI*/0, |
| 63614 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63616 | // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_noret_f64>> => (DS_MIN_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 63617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_F64), |
| 63618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63619 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63623 | GIR_RootConstrainSelectedInstOperands, |
| 63624 | // GIR_Coverage, 7942, |
| 63625 | GIR_EraseRootFromParent_Done, |
| 63626 | // Label 3513: @203644 |
| 63627 | GIM_Try, /*On fail goto*//*Label 3514*/ GIMT_Encode4(203698), // Rule ID 7937 // |
| 63628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 63629 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63633 | // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_m0_f64>> => (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64), |
| 63635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63637 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63641 | GIR_RootConstrainSelectedInstOperands, |
| 63642 | // GIR_Coverage, 7937, |
| 63643 | GIR_EraseRootFromParent_Done, |
| 63644 | // Label 3514: @203698 |
| 63645 | GIM_Try, /*On fail goto*//*Label 3515*/ GIMT_Encode4(203752), // Rule ID 7939 // |
| 63646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 63647 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63649 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63651 | // (atomic_load_fmin:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_local_f64>> => (DS_MIN_RTN_F64_gfx9:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64_gfx9), |
| 63653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63655 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63659 | GIR_RootConstrainSelectedInstOperands, |
| 63660 | // GIR_Coverage, 7939, |
| 63661 | GIR_EraseRootFromParent_Done, |
| 63662 | // Label 3515: @203752 |
| 63663 | GIM_Try, /*On fail goto*//*Label 3516*/ GIMT_Encode4(203806), // Rule ID 7941 // |
| 63664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 63665 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 63666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63667 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63669 | // (atomic_load_fmin_glue:{ *:[f64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_atomic_load_fmin_region_m0_f64>> => (DS_MIN_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 63670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_MIN_RTN_F64), |
| 63671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63673 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63676 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63677 | GIR_RootConstrainSelectedInstOperands, |
| 63678 | // GIR_Coverage, 7941, |
| 63679 | GIR_EraseRootFromParent_Done, |
| 63680 | // Label 3516: @203806 |
| 63681 | GIM_Try, /*On fail goto*//*Label 3517*/ GIMT_Encode4(203863), // Rule ID 3795 // |
| 63682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 63683 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63684 | GIM_CheckHasNoUse, /*MI*/0, |
| 63685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 63687 | // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 63688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR), |
| 63689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 63690 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 63692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63695 | GIR_RootConstrainSelectedInstOperands, |
| 63696 | // GIR_Coverage, 3795, |
| 63697 | GIR_EraseRootFromParent_Done, |
| 63698 | // Label 3517: @203863 |
| 63699 | GIM_Try, /*On fail goto*//*Label 3518*/ GIMT_Encode4(203924), // Rule ID 3797 // |
| 63700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 63701 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 63705 | // (atomic_load_fmin:{ *:[f64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>> => (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 63706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN), |
| 63707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 63709 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 63711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63714 | GIR_RootConstrainSelectedInstOperands, |
| 63715 | // GIR_Coverage, 3797, |
| 63716 | GIR_EraseRootFromParent_Done, |
| 63717 | // Label 3518: @203924 |
| 63718 | GIM_Try, /*On fail goto*//*Label 3519*/ GIMT_Encode4(203976), // Rule ID 3794 // |
| 63719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 63720 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63721 | GIM_CheckHasNoUse, /*MI*/0, |
| 63722 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 63724 | // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (GLOBAL_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64), |
| 63726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63727 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63730 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63731 | GIR_RootConstrainSelectedInstOperands, |
| 63732 | // GIR_Coverage, 3794, |
| 63733 | GIR_EraseRootFromParent_Done, |
| 63734 | // Label 3519: @203976 |
| 63735 | GIM_Try, /*On fail goto*//*Label 3520*/ GIMT_Encode4(204032), // Rule ID 3796 // |
| 63736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 63737 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63739 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 63741 | // (atomic_load_fmin:{ *:[f64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>> => (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN), |
| 63743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63745 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63749 | GIR_RootConstrainSelectedInstOperands, |
| 63750 | // GIR_Coverage, 3796, |
| 63751 | GIR_EraseRootFromParent_Done, |
| 63752 | // Label 3520: @204032 |
| 63753 | GIM_Try, /*On fail goto*//*Label 3521*/ GIMT_Encode4(204085), // Rule ID 3343 // |
| 63754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 63755 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63756 | GIM_CheckHasNoUse, /*MI*/0, |
| 63757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63759 | // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_noret_f64>> => (FLAT_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64), |
| 63761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63762 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63765 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63766 | GIR_RootConstrainSelectedInstOperands, |
| 63767 | // GIR_Coverage, 3343, |
| 63768 | GIR_EraseRootFromParent_Done, |
| 63769 | // Label 3521: @204085 |
| 63770 | GIM_Try, /*On fail goto*//*Label 3522*/ GIMT_Encode4(204137), // Rule ID 3403 // |
| 63771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 63772 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63773 | GIM_CheckHasNoUse, /*MI*/0, |
| 63774 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63776 | // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_noret_f64>> => (FLAT_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64), |
| 63778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63779 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63783 | GIR_RootConstrainSelectedInstOperands, |
| 63784 | // GIR_Coverage, 3403, |
| 63785 | GIR_EraseRootFromParent_Done, |
| 63786 | // Label 3522: @204137 |
| 63787 | GIM_Try, /*On fail goto*//*Label 3523*/ GIMT_Encode4(204194), // Rule ID 3342 // |
| 63788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 63789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63793 | // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_flat_f64>> => (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN), |
| 63795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63797 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63801 | GIR_RootConstrainSelectedInstOperands, |
| 63802 | // GIR_Coverage, 3342, |
| 63803 | GIR_EraseRootFromParent_Done, |
| 63804 | // Label 3523: @204194 |
| 63805 | GIM_Try, /*On fail goto*//*Label 3524*/ GIMT_Encode4(204250), // Rule ID 3402 // |
| 63806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatAddressSpace), |
| 63807 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 63809 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 63811 | // (atomic_load_fmin:{ *:[f64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_atomic_load_fmin_global_f64>> => (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 63812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN), |
| 63813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 63814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 63815 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 63816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63819 | GIR_RootConstrainSelectedInstOperands, |
| 63820 | // GIR_Coverage, 3402, |
| 63821 | GIR_EraseRootFromParent_Done, |
| 63822 | // Label 3524: @204250 |
| 63823 | GIM_Reject, |
| 63824 | // Label 3502: @204251 |
| 63825 | GIM_Reject, |
| 63826 | // Label 3476: @204252 |
| 63827 | GIM_Reject, |
| 63828 | // Label 31: @204253 |
| 63829 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3527*/ GIMT_Encode4(206764), |
| 63830 | /*GILLT_s32*//*Label 3525*/ GIMT_Encode4(204272), |
| 63831 | /*GILLT_s64*//*Label 3526*/ GIMT_Encode4(205518), |
| 63832 | // Label 3525: @204272 |
| 63833 | GIM_Try, /*On fail goto*//*Label 3528*/ GIMT_Encode4(205517), |
| 63834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 63835 | GIM_Try, /*On fail goto*//*Label 3529*/ GIMT_Encode4(204342), // Rule ID 5332 // |
| 63836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 63837 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63838 | GIM_CheckHasNoUse, /*MI*/0, |
| 63839 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63841 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (BUFFER_ATOMIC_INC_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64), |
| 63843 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63849 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63850 | GIR_RootConstrainSelectedInstOperands, |
| 63851 | // GIR_Coverage, 5332, |
| 63852 | GIR_EraseRootFromParent_Done, |
| 63853 | // Label 3529: @204342 |
| 63854 | GIM_Try, /*On fail goto*//*Label 3530*/ GIMT_Encode4(204401), // Rule ID 5336 // |
| 63855 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63856 | GIM_CheckHasNoUse, /*MI*/0, |
| 63857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63859 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (BUFFER_ATOMIC_INC_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64), |
| 63861 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63868 | GIR_RootConstrainSelectedInstOperands, |
| 63869 | // GIR_Coverage, 5336, |
| 63870 | GIR_EraseRootFromParent_Done, |
| 63871 | // Label 3530: @204401 |
| 63872 | GIM_Try, /*On fail goto*//*Label 3531*/ GIMT_Encode4(204467), // Rule ID 5330 // |
| 63873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 63874 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63876 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63878 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (BUFFER_ATOMIC_INC_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_ADDR64_RTN), |
| 63880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63881 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63887 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63888 | GIR_RootConstrainSelectedInstOperands, |
| 63889 | // GIR_Coverage, 5330, |
| 63890 | GIR_EraseRootFromParent_Done, |
| 63891 | // Label 3531: @204467 |
| 63892 | GIM_Try, /*On fail goto*//*Label 3532*/ GIMT_Encode4(204530), // Rule ID 5334 // |
| 63893 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63895 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 63897 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_ADDR64_RTN), |
| 63899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63900 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 63902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 63904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 63905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63907 | GIR_RootConstrainSelectedInstOperands, |
| 63908 | // GIR_Coverage, 5334, |
| 63909 | GIR_EraseRootFromParent_Done, |
| 63910 | // Label 3532: @204530 |
| 63911 | GIM_Try, /*On fail goto*//*Label 3533*/ GIMT_Encode4(204587), // Rule ID 5331 // |
| 63912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 63913 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63914 | GIM_CheckHasNoUse, /*MI*/0, |
| 63915 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63916 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63917 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (BUFFER_ATOMIC_INC_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET), |
| 63919 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63924 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63925 | GIR_RootConstrainSelectedInstOperands, |
| 63926 | // GIR_Coverage, 5331, |
| 63927 | GIR_EraseRootFromParent_Done, |
| 63928 | // Label 3533: @204587 |
| 63929 | GIM_Try, /*On fail goto*//*Label 3534*/ GIMT_Encode4(204641), // Rule ID 5335 // |
| 63930 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63931 | GIM_CheckHasNoUse, /*MI*/0, |
| 63932 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63934 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET), |
| 63936 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63942 | GIR_RootConstrainSelectedInstOperands, |
| 63943 | // GIR_Coverage, 5335, |
| 63944 | GIR_EraseRootFromParent_Done, |
| 63945 | // Label 3534: @204641 |
| 63946 | GIM_Try, /*On fail goto*//*Label 3535*/ GIMT_Encode4(204702), // Rule ID 5329 // |
| 63947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 63948 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63950 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63952 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN), |
| 63954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63955 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63960 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63961 | GIR_RootConstrainSelectedInstOperands, |
| 63962 | // GIR_Coverage, 5329, |
| 63963 | GIR_EraseRootFromParent_Done, |
| 63964 | // Label 3535: @204702 |
| 63965 | GIM_Try, /*On fail goto*//*Label 3536*/ GIMT_Encode4(204760), // Rule ID 5333 // |
| 63966 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 63967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 63968 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 63970 | // (atomic_load_uinc_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 63971 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN), |
| 63972 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 63973 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 63974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 63975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 63976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 63977 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 63978 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63979 | GIR_RootConstrainSelectedInstOperands, |
| 63980 | // GIR_Coverage, 5333, |
| 63981 | GIR_EraseRootFromParent_Done, |
| 63982 | // Label 3536: @204760 |
| 63983 | GIM_Try, /*On fail goto*//*Label 3537*/ GIMT_Encode4(204810), // Rule ID 7785 // |
| 63984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 63985 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 63986 | GIM_CheckHasNoUse, /*MI*/0, |
| 63987 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 63988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 63989 | // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i32>> => (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 63990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32), |
| 63991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 63992 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 63993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 63994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 63995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 63996 | GIR_RootConstrainSelectedInstOperands, |
| 63997 | // GIR_Coverage, 7785, |
| 63998 | GIR_EraseRootFromParent_Done, |
| 63999 | // Label 3537: @204810 |
| 64000 | GIM_Try, /*On fail goto*//*Label 3538*/ GIMT_Encode4(204860), // Rule ID 7787 // |
| 64001 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64002 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64003 | GIM_CheckHasNoUse, /*MI*/0, |
| 64004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64006 | // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i32>> => (DS_INC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32_gfx9), |
| 64008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64009 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64012 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64013 | GIR_RootConstrainSelectedInstOperands, |
| 64014 | // GIR_Coverage, 7787, |
| 64015 | GIR_EraseRootFromParent_Done, |
| 64016 | // Label 3538: @204860 |
| 64017 | GIM_Try, /*On fail goto*//*Label 3539*/ GIMT_Encode4(204910), // Rule ID 7789 // |
| 64018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64019 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64020 | GIM_CheckHasNoUse, /*MI*/0, |
| 64021 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64023 | // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i32>> => (DS_INC_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U32), |
| 64025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64026 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64030 | GIR_RootConstrainSelectedInstOperands, |
| 64031 | // GIR_Coverage, 7789, |
| 64032 | GIR_EraseRootFromParent_Done, |
| 64033 | // Label 3539: @204910 |
| 64034 | GIM_Try, /*On fail goto*//*Label 3540*/ GIMT_Encode4(204964), // Rule ID 7784 // |
| 64035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 64036 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64038 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64040 | // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i32>> => (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32), |
| 64042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64044 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64048 | GIR_RootConstrainSelectedInstOperands, |
| 64049 | // GIR_Coverage, 7784, |
| 64050 | GIR_EraseRootFromParent_Done, |
| 64051 | // Label 3540: @204964 |
| 64052 | GIM_Try, /*On fail goto*//*Label 3541*/ GIMT_Encode4(205018), // Rule ID 7786 // |
| 64053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64054 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64056 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64058 | // (atomic_load_uinc_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i32>> => (DS_INC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32_gfx9), |
| 64060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64062 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64066 | GIR_RootConstrainSelectedInstOperands, |
| 64067 | // GIR_Coverage, 7786, |
| 64068 | GIR_EraseRootFromParent_Done, |
| 64069 | // Label 3541: @205018 |
| 64070 | GIM_Try, /*On fail goto*//*Label 3542*/ GIMT_Encode4(205072), // Rule ID 7788 // |
| 64071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64072 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64074 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64075 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64076 | // (atomic_load_uinc_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i32>> => (DS_INC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U32), |
| 64078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64080 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64083 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64084 | GIR_RootConstrainSelectedInstOperands, |
| 64085 | // GIR_Coverage, 7788, |
| 64086 | GIR_EraseRootFromParent_Done, |
| 64087 | // Label 3542: @205072 |
| 64088 | GIM_Try, /*On fail goto*//*Label 3543*/ GIMT_Encode4(205129), // Rule ID 3611 // |
| 64089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64090 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64091 | GIM_CheckHasNoUse, /*MI*/0, |
| 64092 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64093 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64094 | // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (GLOBAL_ATOMIC_INC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR), |
| 64096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64097 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64102 | GIR_RootConstrainSelectedInstOperands, |
| 64103 | // GIR_Coverage, 3611, |
| 64104 | GIR_EraseRootFromParent_Done, |
| 64105 | // Label 3543: @205129 |
| 64106 | GIM_Try, /*On fail goto*//*Label 3544*/ GIMT_Encode4(205190), // Rule ID 3613 // |
| 64107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64108 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64110 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64112 | // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (GLOBAL_ATOMIC_INC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_SADDR_RTN), |
| 64114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64116 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64121 | GIR_RootConstrainSelectedInstOperands, |
| 64122 | // GIR_Coverage, 3613, |
| 64123 | GIR_EraseRootFromParent_Done, |
| 64124 | // Label 3544: @205190 |
| 64125 | GIM_Try, /*On fail goto*//*Label 3545*/ GIMT_Encode4(205242), // Rule ID 3610 // |
| 64126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64127 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64128 | GIM_CheckHasNoUse, /*MI*/0, |
| 64129 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64131 | // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (GLOBAL_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC), |
| 64133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64134 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64138 | GIR_RootConstrainSelectedInstOperands, |
| 64139 | // GIR_Coverage, 3610, |
| 64140 | GIR_EraseRootFromParent_Done, |
| 64141 | // Label 3545: @205242 |
| 64142 | GIM_Try, /*On fail goto*//*Label 3546*/ GIMT_Encode4(205298), // Rule ID 3612 // |
| 64143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64144 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64146 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64148 | // (atomic_load_uinc_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (GLOBAL_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_RTN), |
| 64150 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64152 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64155 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64156 | GIR_RootConstrainSelectedInstOperands, |
| 64157 | // GIR_Coverage, 3612, |
| 64158 | GIR_EraseRootFromParent_Done, |
| 64159 | // Label 3546: @205298 |
| 64160 | GIM_Try, /*On fail goto*//*Label 3547*/ GIMT_Encode4(205351), // Rule ID 3291 // |
| 64161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64162 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64163 | GIM_CheckHasNoUse, /*MI*/0, |
| 64164 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64165 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64166 | // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i32>> => (FLAT_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC), |
| 64168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64169 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64173 | GIR_RootConstrainSelectedInstOperands, |
| 64174 | // GIR_Coverage, 3291, |
| 64175 | GIR_EraseRootFromParent_Done, |
| 64176 | // Label 3547: @205351 |
| 64177 | GIM_Try, /*On fail goto*//*Label 3548*/ GIMT_Encode4(205403), // Rule ID 3351 // |
| 64178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64179 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64180 | GIM_CheckHasNoUse, /*MI*/0, |
| 64181 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64183 | // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i32>> => (FLAT_ATOMIC_INC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC), |
| 64185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64186 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64189 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64190 | GIR_RootConstrainSelectedInstOperands, |
| 64191 | // GIR_Coverage, 3351, |
| 64192 | GIR_EraseRootFromParent_Done, |
| 64193 | // Label 3548: @205403 |
| 64194 | GIM_Try, /*On fail goto*//*Label 3549*/ GIMT_Encode4(205460), // Rule ID 3290 // |
| 64195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64196 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64198 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64200 | // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i32>> => (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN), |
| 64202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64204 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64207 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64208 | GIR_RootConstrainSelectedInstOperands, |
| 64209 | // GIR_Coverage, 3290, |
| 64210 | GIR_EraseRootFromParent_Done, |
| 64211 | // Label 3549: @205460 |
| 64212 | GIM_Try, /*On fail goto*//*Label 3550*/ GIMT_Encode4(205516), // Rule ID 3350 // |
| 64213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64214 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64216 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64218 | // (atomic_load_uinc_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i32>> => (FLAT_ATOMIC_INC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_RTN), |
| 64220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64222 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64225 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64226 | GIR_RootConstrainSelectedInstOperands, |
| 64227 | // GIR_Coverage, 3350, |
| 64228 | GIR_EraseRootFromParent_Done, |
| 64229 | // Label 3550: @205516 |
| 64230 | GIM_Reject, |
| 64231 | // Label 3528: @205517 |
| 64232 | GIM_Reject, |
| 64233 | // Label 3526: @205518 |
| 64234 | GIM_Try, /*On fail goto*//*Label 3551*/ GIMT_Encode4(206763), |
| 64235 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 64236 | GIM_Try, /*On fail goto*//*Label 3552*/ GIMT_Encode4(205588), // Rule ID 5428 // |
| 64237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64238 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64239 | GIM_CheckHasNoUse, /*MI*/0, |
| 64240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64242 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (BUFFER_ATOMIC_INC_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64), |
| 64244 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64249 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64250 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64251 | GIR_RootConstrainSelectedInstOperands, |
| 64252 | // GIR_Coverage, 5428, |
| 64253 | GIR_EraseRootFromParent_Done, |
| 64254 | // Label 3552: @205588 |
| 64255 | GIM_Try, /*On fail goto*//*Label 3553*/ GIMT_Encode4(205647), // Rule ID 5432 // |
| 64256 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64257 | GIM_CheckHasNoUse, /*MI*/0, |
| 64258 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64259 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64260 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64), |
| 64262 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64268 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64269 | GIR_RootConstrainSelectedInstOperands, |
| 64270 | // GIR_Coverage, 5432, |
| 64271 | GIR_EraseRootFromParent_Done, |
| 64272 | // Label 3553: @205647 |
| 64273 | GIM_Try, /*On fail goto*//*Label 3554*/ GIMT_Encode4(205713), // Rule ID 5426 // |
| 64274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64275 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64277 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64279 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (BUFFER_ATOMIC_INC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_ADDR64_RTN), |
| 64281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64282 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64289 | GIR_RootConstrainSelectedInstOperands, |
| 64290 | // GIR_Coverage, 5426, |
| 64291 | GIR_EraseRootFromParent_Done, |
| 64292 | // Label 3554: @205713 |
| 64293 | GIM_Try, /*On fail goto*//*Label 3555*/ GIMT_Encode4(205776), // Rule ID 5430 // |
| 64294 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64296 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64297 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64298 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_ADDR64_RTN), |
| 64300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64301 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64308 | GIR_RootConstrainSelectedInstOperands, |
| 64309 | // GIR_Coverage, 5430, |
| 64310 | GIR_EraseRootFromParent_Done, |
| 64311 | // Label 3555: @205776 |
| 64312 | GIM_Try, /*On fail goto*//*Label 3556*/ GIMT_Encode4(205833), // Rule ID 5427 // |
| 64313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64314 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64315 | GIM_CheckHasNoUse, /*MI*/0, |
| 64316 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64318 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET), |
| 64320 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64325 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64326 | GIR_RootConstrainSelectedInstOperands, |
| 64327 | // GIR_Coverage, 5427, |
| 64328 | GIR_EraseRootFromParent_Done, |
| 64329 | // Label 3556: @205833 |
| 64330 | GIM_Try, /*On fail goto*//*Label 3557*/ GIMT_Encode4(205887), // Rule ID 5431 // |
| 64331 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64332 | GIM_CheckHasNoUse, /*MI*/0, |
| 64333 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64335 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET), |
| 64337 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64342 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64343 | GIR_RootConstrainSelectedInstOperands, |
| 64344 | // GIR_Coverage, 5431, |
| 64345 | GIR_EraseRootFromParent_Done, |
| 64346 | // Label 3557: @205887 |
| 64347 | GIM_Try, /*On fail goto*//*Label 3558*/ GIMT_Encode4(205948), // Rule ID 5425 // |
| 64348 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64349 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64351 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64352 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64353 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN), |
| 64355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64356 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64362 | GIR_RootConstrainSelectedInstOperands, |
| 64363 | // GIR_Coverage, 5425, |
| 64364 | GIR_EraseRootFromParent_Done, |
| 64365 | // Label 3558: @205948 |
| 64366 | GIM_Try, /*On fail goto*//*Label 3559*/ GIMT_Encode4(206006), // Rule ID 5429 // |
| 64367 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64369 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64370 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64371 | // (atomic_load_uinc_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN), |
| 64373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64374 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64379 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64380 | GIR_RootConstrainSelectedInstOperands, |
| 64381 | // GIR_Coverage, 5429, |
| 64382 | GIR_EraseRootFromParent_Done, |
| 64383 | // Label 3559: @206006 |
| 64384 | GIM_Try, /*On fail goto*//*Label 3560*/ GIMT_Encode4(206056), // Rule ID 7884 // |
| 64385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 64386 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64387 | GIM_CheckHasNoUse, /*MI*/0, |
| 64388 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64390 | // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_noret_i64>> => (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64), |
| 64392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64393 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64397 | GIR_RootConstrainSelectedInstOperands, |
| 64398 | // GIR_Coverage, 7884, |
| 64399 | GIR_EraseRootFromParent_Done, |
| 64400 | // Label 3560: @206056 |
| 64401 | GIM_Try, /*On fail goto*//*Label 3561*/ GIMT_Encode4(206106), // Rule ID 7886 // |
| 64402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64403 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64404 | GIM_CheckHasNoUse, /*MI*/0, |
| 64405 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64407 | // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_noret_i64>> => (DS_INC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64_gfx9), |
| 64409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64410 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64414 | GIR_RootConstrainSelectedInstOperands, |
| 64415 | // GIR_Coverage, 7886, |
| 64416 | GIR_EraseRootFromParent_Done, |
| 64417 | // Label 3561: @206106 |
| 64418 | GIM_Try, /*On fail goto*//*Label 3562*/ GIMT_Encode4(206156), // Rule ID 7888 // |
| 64419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64420 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64421 | GIM_CheckHasNoUse, /*MI*/0, |
| 64422 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64424 | // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_noret_i64>> => (DS_INC_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_U64), |
| 64426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64427 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64430 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64431 | GIR_RootConstrainSelectedInstOperands, |
| 64432 | // GIR_Coverage, 7888, |
| 64433 | GIR_EraseRootFromParent_Done, |
| 64434 | // Label 3562: @206156 |
| 64435 | GIM_Try, /*On fail goto*//*Label 3563*/ GIMT_Encode4(206210), // Rule ID 7883 // |
| 64436 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 64437 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64441 | // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_m0_i64>> => (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64), |
| 64443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64445 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64449 | GIR_RootConstrainSelectedInstOperands, |
| 64450 | // GIR_Coverage, 7883, |
| 64451 | GIR_EraseRootFromParent_Done, |
| 64452 | // Label 3563: @206210 |
| 64453 | GIM_Try, /*On fail goto*//*Label 3564*/ GIMT_Encode4(206264), // Rule ID 7885 // |
| 64454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64455 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64457 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64459 | // (atomic_load_uinc_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_local_i64>> => (DS_INC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64_gfx9), |
| 64461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64463 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64467 | GIR_RootConstrainSelectedInstOperands, |
| 64468 | // GIR_Coverage, 7885, |
| 64469 | GIR_EraseRootFromParent_Done, |
| 64470 | // Label 3564: @206264 |
| 64471 | GIM_Try, /*On fail goto*//*Label 3565*/ GIMT_Encode4(206318), // Rule ID 7887 // |
| 64472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64473 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64477 | // (atomic_load_uinc_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_uinc_wrap_region_m0_i64>> => (DS_INC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_INC_RTN_U64), |
| 64479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64481 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64485 | GIR_RootConstrainSelectedInstOperands, |
| 64486 | // GIR_Coverage, 7887, |
| 64487 | GIR_EraseRootFromParent_Done, |
| 64488 | // Label 3565: @206318 |
| 64489 | GIM_Try, /*On fail goto*//*Label 3566*/ GIMT_Encode4(206375), // Rule ID 3667 // |
| 64490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64491 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64492 | GIM_CheckHasNoUse, /*MI*/0, |
| 64493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64495 | // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (GLOBAL_ATOMIC_INC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR), |
| 64497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64498 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64502 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64503 | GIR_RootConstrainSelectedInstOperands, |
| 64504 | // GIR_Coverage, 3667, |
| 64505 | GIR_EraseRootFromParent_Done, |
| 64506 | // Label 3566: @206375 |
| 64507 | GIM_Try, /*On fail goto*//*Label 3567*/ GIMT_Encode4(206436), // Rule ID 3669 // |
| 64508 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64509 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64511 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64513 | // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (GLOBAL_ATOMIC_INC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_SADDR_RTN), |
| 64515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64517 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64522 | GIR_RootConstrainSelectedInstOperands, |
| 64523 | // GIR_Coverage, 3669, |
| 64524 | GIR_EraseRootFromParent_Done, |
| 64525 | // Label 3567: @206436 |
| 64526 | GIM_Try, /*On fail goto*//*Label 3568*/ GIMT_Encode4(206488), // Rule ID 3666 // |
| 64527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64528 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64529 | GIM_CheckHasNoUse, /*MI*/0, |
| 64530 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64532 | // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (GLOBAL_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2), |
| 64534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64535 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64538 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64539 | GIR_RootConstrainSelectedInstOperands, |
| 64540 | // GIR_Coverage, 3666, |
| 64541 | GIR_EraseRootFromParent_Done, |
| 64542 | // Label 3568: @206488 |
| 64543 | GIM_Try, /*On fail goto*//*Label 3569*/ GIMT_Encode4(206544), // Rule ID 3668 // |
| 64544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64545 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64547 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64549 | // (atomic_load_uinc_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (GLOBAL_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_INC_X2_RTN), |
| 64551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64553 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64557 | GIR_RootConstrainSelectedInstOperands, |
| 64558 | // GIR_Coverage, 3668, |
| 64559 | GIR_EraseRootFromParent_Done, |
| 64560 | // Label 3569: @206544 |
| 64561 | GIM_Try, /*On fail goto*//*Label 3570*/ GIMT_Encode4(206597), // Rule ID 3317 // |
| 64562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64563 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64564 | GIM_CheckHasNoUse, /*MI*/0, |
| 64565 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64567 | // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_noret_i64>> => (FLAT_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2), |
| 64569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64570 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64574 | GIR_RootConstrainSelectedInstOperands, |
| 64575 | // GIR_Coverage, 3317, |
| 64576 | GIR_EraseRootFromParent_Done, |
| 64577 | // Label 3570: @206597 |
| 64578 | GIM_Try, /*On fail goto*//*Label 3571*/ GIMT_Encode4(206649), // Rule ID 3377 // |
| 64579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64580 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64581 | GIM_CheckHasNoUse, /*MI*/0, |
| 64582 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64584 | // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_noret_i64>> => (FLAT_ATOMIC_INC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2), |
| 64586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64587 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64590 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64591 | GIR_RootConstrainSelectedInstOperands, |
| 64592 | // GIR_Coverage, 3377, |
| 64593 | GIR_EraseRootFromParent_Done, |
| 64594 | // Label 3571: @206649 |
| 64595 | GIM_Try, /*On fail goto*//*Label 3572*/ GIMT_Encode4(206706), // Rule ID 3316 // |
| 64596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64597 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64599 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64601 | // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_flat_i64>> => (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN), |
| 64603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64605 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64609 | GIR_RootConstrainSelectedInstOperands, |
| 64610 | // GIR_Coverage, 3316, |
| 64611 | GIR_EraseRootFromParent_Done, |
| 64612 | // Label 3572: @206706 |
| 64613 | GIM_Try, /*On fail goto*//*Label 3573*/ GIMT_Encode4(206762), // Rule ID 3376 // |
| 64614 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64615 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 64617 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64619 | // (atomic_load_uinc_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_uinc_wrap_global_i64>> => (FLAT_ATOMIC_INC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 64620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_INC_X2_RTN), |
| 64621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64623 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64627 | GIR_RootConstrainSelectedInstOperands, |
| 64628 | // GIR_Coverage, 3376, |
| 64629 | GIR_EraseRootFromParent_Done, |
| 64630 | // Label 3573: @206762 |
| 64631 | GIM_Reject, |
| 64632 | // Label 3551: @206763 |
| 64633 | GIM_Reject, |
| 64634 | // Label 3527: @206764 |
| 64635 | GIM_Reject, |
| 64636 | // Label 32: @206765 |
| 64637 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 3576*/ GIMT_Encode4(209276), |
| 64638 | /*GILLT_s32*//*Label 3574*/ GIMT_Encode4(206784), |
| 64639 | /*GILLT_s64*//*Label 3575*/ GIMT_Encode4(208030), |
| 64640 | // Label 3574: @206784 |
| 64641 | GIM_Try, /*On fail goto*//*Label 3577*/ GIMT_Encode4(208029), |
| 64642 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 64643 | GIM_Try, /*On fail goto*//*Label 3578*/ GIMT_Encode4(206854), // Rule ID 5340 // |
| 64644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64645 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64646 | GIM_CheckHasNoUse, /*MI*/0, |
| 64647 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64649 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (BUFFER_ATOMIC_DEC_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64), |
| 64651 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64657 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64658 | GIR_RootConstrainSelectedInstOperands, |
| 64659 | // GIR_Coverage, 5340, |
| 64660 | GIR_EraseRootFromParent_Done, |
| 64661 | // Label 3578: @206854 |
| 64662 | GIM_Try, /*On fail goto*//*Label 3579*/ GIMT_Encode4(206913), // Rule ID 5344 // |
| 64663 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64664 | GIM_CheckHasNoUse, /*MI*/0, |
| 64665 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64667 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64 anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64), |
| 64669 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64675 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64676 | GIR_RootConstrainSelectedInstOperands, |
| 64677 | // GIR_Coverage, 5344, |
| 64678 | GIR_EraseRootFromParent_Done, |
| 64679 | // Label 3579: @206913 |
| 64680 | GIM_Try, /*On fail goto*//*Label 3580*/ GIMT_Encode4(206979), // Rule ID 5338 // |
| 64681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64682 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64684 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64686 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (BUFFER_ATOMIC_DEC_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_ADDR64_RTN), |
| 64688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64689 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64696 | GIR_RootConstrainSelectedInstOperands, |
| 64697 | // GIR_Coverage, 5338, |
| 64698 | GIR_EraseRootFromParent_Done, |
| 64699 | // Label 3580: @206979 |
| 64700 | GIM_Try, /*On fail goto*//*Label 3581*/ GIMT_Encode4(207042), // Rule ID 5342 // |
| 64701 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64703 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 64705 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_ADDR64_RTN), |
| 64707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64708 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 64710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 64712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 64713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64714 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64715 | GIR_RootConstrainSelectedInstOperands, |
| 64716 | // GIR_Coverage, 5342, |
| 64717 | GIR_EraseRootFromParent_Done, |
| 64718 | // Label 3581: @207042 |
| 64719 | GIM_Try, /*On fail goto*//*Label 3582*/ GIMT_Encode4(207099), // Rule ID 5339 // |
| 64720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64721 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64722 | GIM_CheckHasNoUse, /*MI*/0, |
| 64723 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64724 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64725 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (BUFFER_ATOMIC_DEC_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET), |
| 64727 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64732 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64733 | GIR_RootConstrainSelectedInstOperands, |
| 64734 | // GIR_Coverage, 5339, |
| 64735 | GIR_EraseRootFromParent_Done, |
| 64736 | // Label 3582: @207099 |
| 64737 | GIM_Try, /*On fail goto*//*Label 3583*/ GIMT_Encode4(207153), // Rule ID 5343 // |
| 64738 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64739 | GIM_CheckHasNoUse, /*MI*/0, |
| 64740 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64742 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET), |
| 64744 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64749 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64750 | GIR_RootConstrainSelectedInstOperands, |
| 64751 | // GIR_Coverage, 5343, |
| 64752 | GIR_EraseRootFromParent_Done, |
| 64753 | // Label 3583: @207153 |
| 64754 | GIM_Try, /*On fail goto*//*Label 3584*/ GIMT_Encode4(207214), // Rule ID 5337 // |
| 64755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 64756 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64758 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64759 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64760 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN), |
| 64762 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64763 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64769 | GIR_RootConstrainSelectedInstOperands, |
| 64770 | // GIR_Coverage, 5337, |
| 64771 | GIR_EraseRootFromParent_Done, |
| 64772 | // Label 3584: @207214 |
| 64773 | GIM_Try, /*On fail goto*//*Label 3585*/ GIMT_Encode4(207272), // Rule ID 5341 // |
| 64774 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64776 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64777 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 64778 | // (atomic_load_udec_wrap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 64779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN), |
| 64780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 64781 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 64782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 64783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 64784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64786 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64787 | GIR_RootConstrainSelectedInstOperands, |
| 64788 | // GIR_Coverage, 5341, |
| 64789 | GIR_EraseRootFromParent_Done, |
| 64790 | // Label 3585: @207272 |
| 64791 | GIM_Try, /*On fail goto*//*Label 3586*/ GIMT_Encode4(207322), // Rule ID 7791 // |
| 64792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 64793 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64794 | GIM_CheckHasNoUse, /*MI*/0, |
| 64795 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64797 | // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i32>> => (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32), |
| 64799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64800 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64803 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64804 | GIR_RootConstrainSelectedInstOperands, |
| 64805 | // GIR_Coverage, 7791, |
| 64806 | GIR_EraseRootFromParent_Done, |
| 64807 | // Label 3586: @207322 |
| 64808 | GIM_Try, /*On fail goto*//*Label 3587*/ GIMT_Encode4(207372), // Rule ID 7793 // |
| 64809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64810 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64811 | GIM_CheckHasNoUse, /*MI*/0, |
| 64812 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64814 | // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i32>> => (DS_DEC_U32_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32_gfx9), |
| 64816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64817 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64819 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64821 | GIR_RootConstrainSelectedInstOperands, |
| 64822 | // GIR_Coverage, 7793, |
| 64823 | GIR_EraseRootFromParent_Done, |
| 64824 | // Label 3587: @207372 |
| 64825 | GIM_Try, /*On fail goto*//*Label 3588*/ GIMT_Encode4(207422), // Rule ID 7795 // |
| 64826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64827 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64828 | GIM_CheckHasNoUse, /*MI*/0, |
| 64829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64831 | // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i32>> => (DS_DEC_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U32), |
| 64833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64834 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64838 | GIR_RootConstrainSelectedInstOperands, |
| 64839 | // GIR_Coverage, 7795, |
| 64840 | GIR_EraseRootFromParent_Done, |
| 64841 | // Label 3588: @207422 |
| 64842 | GIM_Try, /*On fail goto*//*Label 3589*/ GIMT_Encode4(207476), // Rule ID 7790 // |
| 64843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 64844 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64846 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64848 | // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i32>> => (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32), |
| 64850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64852 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64855 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64856 | GIR_RootConstrainSelectedInstOperands, |
| 64857 | // GIR_Coverage, 7790, |
| 64858 | GIR_EraseRootFromParent_Done, |
| 64859 | // Label 3589: @207476 |
| 64860 | GIM_Try, /*On fail goto*//*Label 3590*/ GIMT_Encode4(207530), // Rule ID 7792 // |
| 64861 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 64862 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 64863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64864 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64865 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64866 | // (atomic_load_udec_wrap:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i32>> => (DS_DEC_RTN_U32_gfx9:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 64867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32_gfx9), |
| 64868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64870 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64873 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64874 | GIR_RootConstrainSelectedInstOperands, |
| 64875 | // GIR_Coverage, 7792, |
| 64876 | GIR_EraseRootFromParent_Done, |
| 64877 | // Label 3590: @207530 |
| 64878 | GIM_Try, /*On fail goto*//*Label 3591*/ GIMT_Encode4(207584), // Rule ID 7794 // |
| 64879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 64880 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 64881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64882 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 64884 | // (atomic_load_udec_wrap_glue:{ *:[i32] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i32>> => (DS_DEC_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 64885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U32), |
| 64886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 64888 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 64889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64892 | GIR_RootConstrainSelectedInstOperands, |
| 64893 | // GIR_Coverage, 7794, |
| 64894 | GIR_EraseRootFromParent_Done, |
| 64895 | // Label 3591: @207584 |
| 64896 | GIM_Try, /*On fail goto*//*Label 3592*/ GIMT_Encode4(207641), // Rule ID 3615 // |
| 64897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64898 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64899 | GIM_CheckHasNoUse, /*MI*/0, |
| 64900 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64901 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64902 | // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (GLOBAL_ATOMIC_DEC_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR), |
| 64904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64905 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64909 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64910 | GIR_RootConstrainSelectedInstOperands, |
| 64911 | // GIR_Coverage, 3615, |
| 64912 | GIR_EraseRootFromParent_Done, |
| 64913 | // Label 3592: @207641 |
| 64914 | GIM_Try, /*On fail goto*//*Label 3593*/ GIMT_Encode4(207702), // Rule ID 3617 // |
| 64915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64916 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64918 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 64920 | // (atomic_load_udec_wrap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (GLOBAL_ATOMIC_DEC_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 64921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_SADDR_RTN), |
| 64922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 64924 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 64926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 64927 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64929 | GIR_RootConstrainSelectedInstOperands, |
| 64930 | // GIR_Coverage, 3617, |
| 64931 | GIR_EraseRootFromParent_Done, |
| 64932 | // Label 3593: @207702 |
| 64933 | GIM_Try, /*On fail goto*//*Label 3594*/ GIMT_Encode4(207754), // Rule ID 3614 // |
| 64934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64935 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64936 | GIM_CheckHasNoUse, /*MI*/0, |
| 64937 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64939 | // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (GLOBAL_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC), |
| 64941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64942 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64945 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64946 | GIR_RootConstrainSelectedInstOperands, |
| 64947 | // GIR_Coverage, 3614, |
| 64948 | GIR_EraseRootFromParent_Done, |
| 64949 | // Label 3594: @207754 |
| 64950 | GIM_Try, /*On fail goto*//*Label 3595*/ GIMT_Encode4(207810), // Rule ID 3616 // |
| 64951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 64952 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 64954 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64955 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 64956 | // (atomic_load_udec_wrap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (GLOBAL_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_RTN), |
| 64958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 64959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64960 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 64963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64964 | GIR_RootConstrainSelectedInstOperands, |
| 64965 | // GIR_Coverage, 3616, |
| 64966 | GIR_EraseRootFromParent_Done, |
| 64967 | // Label 3595: @207810 |
| 64968 | GIM_Try, /*On fail goto*//*Label 3596*/ GIMT_Encode4(207863), // Rule ID 3293 // |
| 64969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64970 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64971 | GIM_CheckHasNoUse, /*MI*/0, |
| 64972 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64974 | // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i32>> => (FLAT_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC), |
| 64976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64977 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64981 | GIR_RootConstrainSelectedInstOperands, |
| 64982 | // GIR_Coverage, 3293, |
| 64983 | GIR_EraseRootFromParent_Done, |
| 64984 | // Label 3596: @207863 |
| 64985 | GIM_Try, /*On fail goto*//*Label 3597*/ GIMT_Encode4(207915), // Rule ID 3353 // |
| 64986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 64987 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 64988 | GIM_CheckHasNoUse, /*MI*/0, |
| 64989 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 64990 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 64991 | // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i32>> => (FLAT_ATOMIC_DEC VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 64992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC), |
| 64993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 64994 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 64995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 64996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 64997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 64998 | GIR_RootConstrainSelectedInstOperands, |
| 64999 | // GIR_Coverage, 3353, |
| 65000 | GIR_EraseRootFromParent_Done, |
| 65001 | // Label 3597: @207915 |
| 65002 | GIM_Try, /*On fail goto*//*Label 3598*/ GIMT_Encode4(207972), // Rule ID 3292 // |
| 65003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65004 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 65006 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65008 | // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i32>> => (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 65009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN), |
| 65010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65012 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65016 | GIR_RootConstrainSelectedInstOperands, |
| 65017 | // GIR_Coverage, 3292, |
| 65018 | GIR_EraseRootFromParent_Done, |
| 65019 | // Label 3598: @207972 |
| 65020 | GIM_Try, /*On fail goto*//*Label 3599*/ GIMT_Encode4(208028), // Rule ID 3352 // |
| 65021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65022 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 65024 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65026 | // (atomic_load_udec_wrap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i32>> => (FLAT_ATOMIC_DEC_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 65027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_RTN), |
| 65028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65030 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65033 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65034 | GIR_RootConstrainSelectedInstOperands, |
| 65035 | // GIR_Coverage, 3352, |
| 65036 | GIR_EraseRootFromParent_Done, |
| 65037 | // Label 3599: @208028 |
| 65038 | GIM_Reject, |
| 65039 | // Label 3577: @208029 |
| 65040 | GIM_Reject, |
| 65041 | // Label 3575: @208030 |
| 65042 | GIM_Try, /*On fail goto*//*Label 3600*/ GIMT_Encode4(209275), |
| 65043 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65044 | GIM_Try, /*On fail goto*//*Label 3601*/ GIMT_Encode4(208100), // Rule ID 5436 // |
| 65045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 65046 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65047 | GIM_CheckHasNoUse, /*MI*/0, |
| 65048 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65049 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 65050 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (BUFFER_ATOMIC_DEC_X2_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64), |
| 65052 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 65054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 65056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 65057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65059 | GIR_RootConstrainSelectedInstOperands, |
| 65060 | // GIR_Coverage, 5436, |
| 65061 | GIR_EraseRootFromParent_Done, |
| 65062 | // Label 3601: @208100 |
| 65063 | GIM_Try, /*On fail goto*//*Label 3602*/ GIMT_Encode4(208159), // Rule ID 5440 // |
| 65064 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65065 | GIM_CheckHasNoUse, /*MI*/0, |
| 65066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 65068 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64 anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64), |
| 65070 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 65072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 65074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 65075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65077 | GIR_RootConstrainSelectedInstOperands, |
| 65078 | // GIR_Coverage, 5440, |
| 65079 | GIR_EraseRootFromParent_Done, |
| 65080 | // Label 3602: @208159 |
| 65081 | GIM_Try, /*On fail goto*//*Label 3603*/ GIMT_Encode4(208225), // Rule ID 5434 // |
| 65082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 65083 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65085 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65086 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 65087 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (BUFFER_ATOMIC_DEC_X2_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_ADDR64_RTN), |
| 65089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 65090 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 65092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 65094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 65095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65097 | GIR_RootConstrainSelectedInstOperands, |
| 65098 | // GIR_Coverage, 5434, |
| 65099 | GIR_EraseRootFromParent_Done, |
| 65100 | // Label 3603: @208225 |
| 65101 | GIM_Try, /*On fail goto*//*Label 3604*/ GIMT_Encode4(208288), // Rule ID 5438 // |
| 65102 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 65106 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_ADDR64_RTN), |
| 65108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 65109 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 65111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 65113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 65114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65115 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65116 | GIR_RootConstrainSelectedInstOperands, |
| 65117 | // GIR_Coverage, 5438, |
| 65118 | GIR_EraseRootFromParent_Done, |
| 65119 | // Label 3604: @208288 |
| 65120 | GIM_Try, /*On fail goto*//*Label 3605*/ GIMT_Encode4(208345), // Rule ID 5435 // |
| 65121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 65122 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65123 | GIM_CheckHasNoUse, /*MI*/0, |
| 65124 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 65126 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET), |
| 65128 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 65131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65134 | GIR_RootConstrainSelectedInstOperands, |
| 65135 | // GIR_Coverage, 5435, |
| 65136 | GIR_EraseRootFromParent_Done, |
| 65137 | // Label 3605: @208345 |
| 65138 | GIM_Try, /*On fail goto*//*Label 3606*/ GIMT_Encode4(208399), // Rule ID 5439 // |
| 65139 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65140 | GIM_CheckHasNoUse, /*MI*/0, |
| 65141 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 65143 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET), |
| 65145 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 65148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65151 | GIR_RootConstrainSelectedInstOperands, |
| 65152 | // GIR_Coverage, 5439, |
| 65153 | GIR_EraseRootFromParent_Done, |
| 65154 | // Label 3606: @208399 |
| 65155 | GIM_Try, /*On fail goto*//*Label 3607*/ GIMT_Encode4(208460), // Rule ID 5433 // |
| 65156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 65157 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65159 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65160 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 65161 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN), |
| 65163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 65164 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 65167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65170 | GIR_RootConstrainSelectedInstOperands, |
| 65171 | // GIR_Coverage, 5433, |
| 65172 | GIR_EraseRootFromParent_Done, |
| 65173 | // Label 3607: @208460 |
| 65174 | GIM_Try, /*On fail goto*//*Label 3608*/ GIMT_Encode4(208518), // Rule ID 5437 // |
| 65175 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65177 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65178 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 65179 | // (atomic_load_udec_wrap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$vdata_in)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 65180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN), |
| 65181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 65182 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 65183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 65184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 65185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65186 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65187 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65188 | GIR_RootConstrainSelectedInstOperands, |
| 65189 | // GIR_Coverage, 5437, |
| 65190 | GIR_EraseRootFromParent_Done, |
| 65191 | // Label 3608: @208518 |
| 65192 | GIM_Try, /*On fail goto*//*Label 3609*/ GIMT_Encode4(208568), // Rule ID 7890 // |
| 65193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 65194 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 65195 | GIM_CheckHasNoUse, /*MI*/0, |
| 65196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65197 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65198 | // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_noret_i64>> => (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 65199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64), |
| 65200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65201 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65204 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65205 | GIR_RootConstrainSelectedInstOperands, |
| 65206 | // GIR_Coverage, 7890, |
| 65207 | GIR_EraseRootFromParent_Done, |
| 65208 | // Label 3609: @208568 |
| 65209 | GIM_Try, /*On fail goto*//*Label 3610*/ GIMT_Encode4(208618), // Rule ID 7892 // |
| 65210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 65211 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 65212 | GIM_CheckHasNoUse, /*MI*/0, |
| 65213 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65214 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65215 | // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_noret_i64>> => (DS_DEC_U64_gfx9 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 65216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64_gfx9), |
| 65217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65218 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65221 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65222 | GIR_RootConstrainSelectedInstOperands, |
| 65223 | // GIR_Coverage, 7892, |
| 65224 | GIR_EraseRootFromParent_Done, |
| 65225 | // Label 3610: @208618 |
| 65226 | GIM_Try, /*On fail goto*//*Label 3611*/ GIMT_Encode4(208668), // Rule ID 7894 // |
| 65227 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 65228 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 65229 | GIM_CheckHasNoUse, /*MI*/0, |
| 65230 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65231 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65232 | // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_noret_i64>> => (DS_DEC_U64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 65233 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_U64), |
| 65234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65235 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65239 | GIR_RootConstrainSelectedInstOperands, |
| 65240 | // GIR_Coverage, 7894, |
| 65241 | GIR_EraseRootFromParent_Done, |
| 65242 | // Label 3611: @208668 |
| 65243 | GIM_Try, /*On fail goto*//*Label 3612*/ GIMT_Encode4(208722), // Rule ID 7889 // |
| 65244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_LDSRequiresM0Init), |
| 65245 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 65246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65247 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65249 | // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_m0_i64>> => (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 65250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64), |
| 65251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65253 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65257 | GIR_RootConstrainSelectedInstOperands, |
| 65258 | // GIR_Coverage, 7889, |
| 65259 | GIR_EraseRootFromParent_Done, |
| 65260 | // Label 3612: @208722 |
| 65261 | GIM_Try, /*On fail goto*//*Label 3613*/ GIMT_Encode4(208776), // Rule ID 7891 // |
| 65262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotLDSRequiresM0Init), |
| 65263 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 65264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65265 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65266 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65267 | // (atomic_load_udec_wrap:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_local_i64>> => (DS_DEC_RTN_U64_gfx9:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 65268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64_gfx9), |
| 65269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65271 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65275 | GIR_RootConstrainSelectedInstOperands, |
| 65276 | // GIR_Coverage, 7891, |
| 65277 | GIR_EraseRootFromParent_Done, |
| 65278 | // Label 3613: @208776 |
| 65279 | GIM_Try, /*On fail goto*//*Label 3614*/ GIMT_Encode4(208830), // Rule ID 7893 // |
| 65280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGDS), |
| 65281 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/2, |
| 65282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65283 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65284 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 65285 | // (atomic_load_udec_wrap_glue:{ *:[i64] } (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$value)<<P:Predicate_atomic_load_udec_wrap_region_m0_i64>> => (DS_DEC_RTN_U64:{ *:[i64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[i64] }:$value, Offset:{ *:[i32] }:$offset, 1:{ *:[i1] }) |
| 65286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DEC_RTN_U64), |
| 65287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 65289 | GIR_RootToRootCopy, /*OpIdx*/2, // value |
| 65290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65292 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65293 | GIR_RootConstrainSelectedInstOperands, |
| 65294 | // GIR_Coverage, 7893, |
| 65295 | GIR_EraseRootFromParent_Done, |
| 65296 | // Label 3614: @208830 |
| 65297 | GIM_Try, /*On fail goto*//*Label 3615*/ GIMT_Encode4(208887), // Rule ID 3671 // |
| 65298 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 65299 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65300 | GIM_CheckHasNoUse, /*MI*/0, |
| 65301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 65303 | // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (GLOBAL_ATOMIC_DEC_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 65304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR), |
| 65305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 65306 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 65308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65310 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65311 | GIR_RootConstrainSelectedInstOperands, |
| 65312 | // GIR_Coverage, 3671, |
| 65313 | GIR_EraseRootFromParent_Done, |
| 65314 | // Label 3615: @208887 |
| 65315 | GIM_Try, /*On fail goto*//*Label 3616*/ GIMT_Encode4(208948), // Rule ID 3673 // |
| 65316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 65317 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65319 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 65321 | // (atomic_load_udec_wrap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (GLOBAL_ATOMIC_DEC_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 65322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_SADDR_RTN), |
| 65323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 65325 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 65327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 65328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65330 | GIR_RootConstrainSelectedInstOperands, |
| 65331 | // GIR_Coverage, 3673, |
| 65332 | GIR_EraseRootFromParent_Done, |
| 65333 | // Label 3616: @208948 |
| 65334 | GIM_Try, /*On fail goto*//*Label 3617*/ GIMT_Encode4(209000), // Rule ID 3670 // |
| 65335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 65336 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65337 | GIM_CheckHasNoUse, /*MI*/0, |
| 65338 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 65340 | // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (GLOBAL_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2), |
| 65342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65343 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65347 | GIR_RootConstrainSelectedInstOperands, |
| 65348 | // GIR_Coverage, 3670, |
| 65349 | GIR_EraseRootFromParent_Done, |
| 65350 | // Label 3617: @209000 |
| 65351 | GIM_Try, /*On fail goto*//*Label 3618*/ GIMT_Encode4(209056), // Rule ID 3672 // |
| 65352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 65353 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65355 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65356 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 65357 | // (atomic_load_udec_wrap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (GLOBAL_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_DEC_X2_RTN), |
| 65359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65361 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65364 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65365 | GIR_RootConstrainSelectedInstOperands, |
| 65366 | // GIR_Coverage, 3672, |
| 65367 | GIR_EraseRootFromParent_Done, |
| 65368 | // Label 3618: @209056 |
| 65369 | GIM_Try, /*On fail goto*//*Label 3619*/ GIMT_Encode4(209109), // Rule ID 3319 // |
| 65370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65371 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65372 | GIM_CheckHasNoUse, /*MI*/0, |
| 65373 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65374 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65375 | // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_noret_i64>> => (FLAT_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2), |
| 65377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65378 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65381 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65382 | GIR_RootConstrainSelectedInstOperands, |
| 65383 | // GIR_Coverage, 3319, |
| 65384 | GIR_EraseRootFromParent_Done, |
| 65385 | // Label 3619: @209109 |
| 65386 | GIM_Try, /*On fail goto*//*Label 3620*/ GIMT_Encode4(209161), // Rule ID 3379 // |
| 65387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65388 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65389 | GIM_CheckHasNoUse, /*MI*/0, |
| 65390 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65391 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65392 | // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_noret_i64>> => (FLAT_ATOMIC_DEC_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2), |
| 65394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65395 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65399 | GIR_RootConstrainSelectedInstOperands, |
| 65400 | // GIR_Coverage, 3379, |
| 65401 | GIR_EraseRootFromParent_Done, |
| 65402 | // Label 3620: @209161 |
| 65403 | GIM_Try, /*On fail goto*//*Label 3621*/ GIMT_Encode4(209218), // Rule ID 3318 // |
| 65404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65405 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65407 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65409 | // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_flat_i64>> => (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN), |
| 65411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65413 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65417 | GIR_RootConstrainSelectedInstOperands, |
| 65418 | // GIR_Coverage, 3318, |
| 65419 | GIR_EraseRootFromParent_Done, |
| 65420 | // Label 3621: @209218 |
| 65421 | GIM_Try, /*On fail goto*//*Label 3622*/ GIMT_Encode4(209274), // Rule ID 3378 // |
| 65422 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 65423 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 65424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 65425 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 65426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 65427 | // (atomic_load_udec_wrap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data)<<P:Predicate_atomic_load_udec_wrap_global_i64>> => (FLAT_ATOMIC_DEC_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 65428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_DEC_X2_RTN), |
| 65429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 65431 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 65432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 65434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65435 | GIR_RootConstrainSelectedInstOperands, |
| 65436 | // GIR_Coverage, 3378, |
| 65437 | GIR_EraseRootFromParent_Done, |
| 65438 | // Label 3622: @209274 |
| 65439 | GIM_Reject, |
| 65440 | // Label 3600: @209275 |
| 65441 | GIM_Reject, |
| 65442 | // Label 3576: @209276 |
| 65443 | GIM_Reject, |
| 65444 | // Label 33: @209277 |
| 65445 | GIM_Try, /*On fail goto*//*Label 3623*/ GIMT_Encode4(209295), // Rule ID 1107 // |
| 65446 | // MIs[0] ordering |
| 65447 | GIM_CheckIsImm, /*MI*/0, /*Op*/0, |
| 65448 | // MIs[0] scope |
| 65449 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65450 | // (atomic_fence (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope) => (ATOMIC_FENCE (timm:{ *:[i32] }):$ordering, (timm:{ *:[i32] }):$scope) |
| 65451 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::ATOMIC_FENCE), |
| 65452 | GIR_RootConstrainSelectedInstOperands, |
| 65453 | // GIR_Coverage, 1107, |
| 65454 | GIR_Done, |
| 65455 | // Label 3623: @209295 |
| 65456 | GIM_Reject, |
| 65457 | // Label 34: @209296 |
| 65458 | GIM_Try, /*On fail goto*//*Label 3624*/ GIMT_Encode4(209731), |
| 65459 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_smrd_prefetch), |
| 65460 | GIM_Try, /*On fail goto*//*Label 3625*/ GIMT_Encode4(209414), |
| 65461 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/0, |
| 65462 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65463 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 65464 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 65465 | GIM_Try, /*On fail goto*//*Label 3626*/ GIMT_Encode4(209368), // Rule ID 3183 // |
| 65466 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero), |
| 65467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 65468 | // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST), |
| 65470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 65471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65472 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65474 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65475 | GIR_RootConstrainSelectedInstOperands, |
| 65476 | // GIR_Coverage, 3183, |
| 65477 | GIR_EraseRootFromParent_Done, |
| 65478 | // Label 3626: @209368 |
| 65479 | GIM_Try, /*On fail goto*//*Label 3627*/ GIMT_Encode4(209413), // Rule ID 3186 // |
| 65480 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one), |
| 65481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/0, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_imm), |
| 65482 | // (prefetch (SMRDImm:{ *:[iPTR] } i64:{ *:[i64] }:$sbase, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, ?:{ *:[i32] }:$offset, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA), |
| 65484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // sbase |
| 65485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 65486 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65489 | GIR_RootConstrainSelectedInstOperands, |
| 65490 | // GIR_Coverage, 3186, |
| 65491 | GIR_EraseRootFromParent_Done, |
| 65492 | // Label 3627: @209413 |
| 65493 | GIM_Reject, |
| 65494 | // Label 3625: @209414 |
| 65495 | GIM_Try, /*On fail goto*//*Label 3628*/ GIMT_Encode4(209464), // Rule ID 3184 // |
| 65496 | // MIs[0] sbase |
| 65497 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64, |
| 65498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65499 | // MIs[0] Operand 1 |
| 65500 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65501 | // MIs[0] Operand 2 |
| 65502 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 65503 | // MIs[0] Operand 3 |
| 65504 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 65505 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero), |
| 65506 | // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_INST ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST), |
| 65508 | GIR_RootToRootCopy, /*OpIdx*/0, // sbase |
| 65509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65510 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65513 | GIR_RootConstrainSelectedInstOperands, |
| 65514 | // GIR_Coverage, 3184, |
| 65515 | GIR_EraseRootFromParent_Done, |
| 65516 | // Label 3628: @209464 |
| 65517 | GIM_Try, /*On fail goto*//*Label 3629*/ GIMT_Encode4(209572), // Rule ID 3185 // |
| 65518 | // MIs[0] sbase |
| 65519 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32, |
| 65520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 65521 | // MIs[0] Operand 1 |
| 65522 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65523 | // MIs[0] Operand 2 |
| 65524 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 65525 | // MIs[0] Operand 3 |
| 65526 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 65527 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_zero), |
| 65528 | // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_zero>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_INST (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65529 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 65530 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 65531 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 65532 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65533 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 65534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 65535 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 65536 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65537 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase |
| 65538 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 65539 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 65540 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 65541 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65542 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 65543 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 65544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_INST), |
| 65545 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65547 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65550 | GIR_RootConstrainSelectedInstOperands, |
| 65551 | // GIR_Coverage, 3185, |
| 65552 | GIR_EraseRootFromParent_Done, |
| 65553 | // Label 3629: @209572 |
| 65554 | GIM_Try, /*On fail goto*//*Label 3630*/ GIMT_Encode4(209622), // Rule ID 3187 // |
| 65555 | // MIs[0] sbase |
| 65556 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/64, |
| 65557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65558 | // MIs[0] Operand 1 |
| 65559 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65560 | // MIs[0] Operand 2 |
| 65561 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 65562 | // MIs[0] Operand 3 |
| 65563 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 65564 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one), |
| 65565 | // (prefetch SReg_64:{ *:[i64] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_DATA ?:{ *:[i64] }:$sbase, 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA), |
| 65567 | GIR_RootToRootCopy, /*OpIdx*/0, // sbase |
| 65568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65569 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65572 | GIR_RootConstrainSelectedInstOperands, |
| 65573 | // GIR_Coverage, 3187, |
| 65574 | GIR_EraseRootFromParent_Done, |
| 65575 | // Label 3630: @209622 |
| 65576 | GIM_Try, /*On fail goto*//*Label 3631*/ GIMT_Encode4(209730), // Rule ID 3188 // |
| 65577 | // MIs[0] sbase |
| 65578 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32, |
| 65579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 65580 | // MIs[0] Operand 1 |
| 65581 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 65582 | // MIs[0] Operand 2 |
| 65583 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 65584 | // MIs[0] Operand 3 |
| 65585 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 65586 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/3, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_i32imm_one), |
| 65587 | // (prefetch SReg_32:{ *:[i32] }:$sbase, (timm:{ *:[i32] }), (timm:{ *:[i32] }), (timm:{ *:[i32] })<<P:Predicate_i32imm_one>>)<<P:Predicate_smrd_prefetch>> => (S_PREFETCH_DATA (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$sbase, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i32] } 0:{ *:[i32] }), sub1:{ *:[i32] }), 0:{ *:[i32] }, SGPR_NULL:{ *:[i32] }, 0:{ *:[i8] }) |
| 65588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 65589 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 65590 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 65591 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65592 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 65593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 65594 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 65595 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65596 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/0, // sbase |
| 65597 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 65598 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 65599 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 65600 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65601 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 65602 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 65603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_PREFETCH_DATA), |
| 65604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65606 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SGPR_NULL), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 65607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 65608 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 65609 | GIR_RootConstrainSelectedInstOperands, |
| 65610 | // GIR_Coverage, 3188, |
| 65611 | GIR_EraseRootFromParent_Done, |
| 65612 | // Label 3631: @209730 |
| 65613 | GIM_Reject, |
| 65614 | // Label 3624: @209731 |
| 65615 | GIM_Reject, |
| 65616 | // Label 35: @209732 |
| 65617 | GIM_Try, /*On fail goto*//*Label 3632*/ GIMT_Encode4(209759), // Rule ID 1124 // |
| 65618 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_EnableLateCFGStructurize), |
| 65619 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 65620 | // MIs[0] target |
| 65621 | GIM_CheckIsMBB, /*MI*/0, /*Op*/1, |
| 65622 | // (brcond i1:{ *:[i1] }:$vcc, (bb:{ *:[Other] }):$target) => (SI_NON_UNIFORM_BRCOND_PSEUDO:{ *:[i1] } i1:{ *:[i1] }:$vcc, (bb:{ *:[Other] }):$target) |
| 65623 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::SI_NON_UNIFORM_BRCOND_PSEUDO), |
| 65624 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 65625 | GIR_RootConstrainSelectedInstOperands, |
| 65626 | // GIR_Coverage, 1124, |
| 65627 | GIR_Done, |
| 65628 | // Label 3632: @209759 |
| 65629 | GIM_Reject, |
| 65630 | // Label 36: @209760 |
| 65631 | GIM_Try, /*On fail goto*//*Label 3633*/ GIMT_Encode4(209841), |
| 65632 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 65633 | GIM_Try, /*On fail goto*//*Label 3634*/ GIMT_Encode4(209792), // Rule ID 20 // |
| 65634 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getpc), |
| 65635 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 65636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65637 | // (intrinsic_wo_chain:{ *:[i64] } 2970:{ *:[iPTR] }) => (S_GETPC_B64_pseudo:{ *:[i64] }) |
| 65638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETPC_B64_pseudo), |
| 65639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 65640 | GIR_RootConstrainSelectedInstOperands, |
| 65641 | // GIR_Coverage, 20, |
| 65642 | GIR_EraseRootFromParent_Done, |
| 65643 | // Label 3634: @209792 |
| 65644 | GIM_Try, /*On fail goto*//*Label 3635*/ GIMT_Encode4(209816), // Rule ID 1119 // |
| 65645 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_groupstaticsize), |
| 65646 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 65648 | // (intrinsic_wo_chain:{ *:[i32] } 2041:{ *:[iPTR] }) => (GET_GROUPSTATICSIZE:{ *:[i32] }) |
| 65649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GET_GROUPSTATICSIZE), |
| 65650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 65651 | GIR_RootConstrainSelectedInstOperands, |
| 65652 | // GIR_Coverage, 1119, |
| 65653 | GIR_EraseRootFromParent_Done, |
| 65654 | // Label 3635: @209816 |
| 65655 | GIM_Try, /*On fail goto*//*Label 3636*/ GIMT_Encode4(209840), // Rule ID 1127 // |
| 65656 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ps_live), |
| 65657 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 65658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 65659 | // (intrinsic_wo_chain:{ *:[i1] } 2891:{ *:[iPTR] }) => (SI_PS_LIVE:{ *:[i1] }) |
| 65660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_PS_LIVE), |
| 65661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65662 | GIR_RootConstrainSelectedInstOperands, |
| 65663 | // GIR_Coverage, 1127, |
| 65664 | GIR_EraseRootFromParent_Done, |
| 65665 | // Label 3636: @209840 |
| 65666 | GIM_Reject, |
| 65667 | // Label 3633: @209841 |
| 65668 | GIM_Try, /*On fail goto*//*Label 3637*/ GIMT_Encode4(213489), |
| 65669 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 65670 | GIM_Try, /*On fail goto*//*Label 3638*/ GIMT_Encode4(209931), // Rule ID 2280 // |
| 65671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65672 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 65673 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 65674 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65676 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24204), |
| 65677 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65678 | // (intrinsic_wo_chain:{ *:[f16] } 2010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24204>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_EXP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 65679 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 65680 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F16_e64), |
| 65681 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65682 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65683 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65684 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65685 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65686 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 65687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 65688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65689 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65690 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65691 | // GIR_Coverage, 2280, |
| 65692 | GIR_EraseRootFromParent_Done, |
| 65693 | // Label 3638: @209931 |
| 65694 | GIM_Try, /*On fail goto*//*Label 3639*/ GIMT_Encode4(210013), // Rule ID 2282 // |
| 65695 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65696 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 65697 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 65698 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24206), |
| 65701 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65702 | // (intrinsic_wo_chain:{ *:[f16] } 2830:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24206>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_LOG_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 65703 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 65704 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F16_e64), |
| 65705 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65706 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65707 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65708 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65709 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65710 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 65711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 65712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65714 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65715 | // GIR_Coverage, 2282, |
| 65716 | GIR_EraseRootFromParent_Done, |
| 65717 | // Label 3639: @210013 |
| 65718 | GIM_Try, /*On fail goto*//*Label 3640*/ GIMT_Encode4(210095), // Rule ID 2284 // |
| 65719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65720 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 65721 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 65722 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65724 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24198), |
| 65725 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65726 | // (intrinsic_wo_chain:{ *:[f16] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24198>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RCP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 65727 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 65728 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F16_e64), |
| 65729 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65730 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65731 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65732 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65733 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65734 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 65735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 65736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65738 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65739 | // GIR_Coverage, 2284, |
| 65740 | GIR_EraseRootFromParent_Done, |
| 65741 | // Label 3640: @210095 |
| 65742 | GIM_Try, /*On fail goto*//*Label 3641*/ GIMT_Encode4(210177), // Rule ID 2286 // |
| 65743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65744 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 65745 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 65746 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65748 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24200), |
| 65749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65750 | // (intrinsic_wo_chain:{ *:[f16] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24200>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_RSQ_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 65751 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 65752 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F16_e64), |
| 65753 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65754 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65755 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65756 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65757 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65758 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 65759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 65760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65762 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65763 | // GIR_Coverage, 2286, |
| 65764 | GIR_EraseRootFromParent_Done, |
| 65765 | // Label 3641: @210177 |
| 65766 | GIM_Try, /*On fail goto*//*Label 3642*/ GIMT_Encode4(210259), // Rule ID 2289 // |
| 65767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65768 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 65769 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 65770 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 65771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65772 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24202), |
| 65773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65774 | // (intrinsic_wo_chain:{ *:[f16] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24202>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_SQRT_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 65775 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 65776 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F16_e64), |
| 65777 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 65778 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65779 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65780 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65781 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65782 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 65783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 65784 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 65785 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 65786 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65787 | // GIR_Coverage, 2289, |
| 65788 | GIR_EraseRootFromParent_Done, |
| 65789 | // Label 3642: @210259 |
| 65790 | GIM_Try, /*On fail goto*//*Label 3643*/ GIMT_Encode4(210292), // Rule ID 16 // |
| 65791 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh), |
| 65792 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65793 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 65795 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18483), |
| 65796 | // (intrinsic_wo_chain:{ *:[i32] } 3009:{ *:[iPTR] }, i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18483>> => (S_FLBIT_I32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 65797 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32), |
| 65798 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 65799 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 65800 | GIR_RootConstrainSelectedInstOperands, |
| 65801 | // GIR_Coverage, 16, |
| 65802 | GIR_EraseRootFromParent_Done, |
| 65803 | // Label 3643: @210292 |
| 65804 | GIM_Try, /*On fail goto*//*Label 3644*/ GIMT_Encode4(210324), // Rule ID 1108 // |
| 65805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 65806 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_inverse_ballot), |
| 65807 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 65808 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 65810 | // (intrinsic_wo_chain:{ *:[i1] } 2820:{ *:[iPTR] }, i32:{ *:[i32] }:$mask) => (S_INVERSE_BALLOT_U32:{ *:[i1] } i32:{ *:[i32] }:$mask) |
| 65811 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INVERSE_BALLOT_U32), |
| 65812 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 65813 | GIR_RootToRootCopy, /*OpIdx*/2, // mask |
| 65814 | GIR_RootConstrainSelectedInstOperands, |
| 65815 | // GIR_Coverage, 1108, |
| 65816 | GIR_EraseRootFromParent_Done, |
| 65817 | // Label 3644: @210324 |
| 65818 | GIM_Try, /*On fail goto*//*Label 3645*/ GIMT_Encode4(210356), // Rule ID 1109 // |
| 65819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 65820 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_inverse_ballot), |
| 65821 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 65822 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 65823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 65824 | // (intrinsic_wo_chain:{ *:[i1] } 2820:{ *:[iPTR] }, i64:{ *:[i64] }:$mask) => (S_INVERSE_BALLOT_U64:{ *:[i1] } i64:{ *:[i64] }:$mask) |
| 65825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INVERSE_BALLOT_U64), |
| 65826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 65827 | GIR_RootToRootCopy, /*OpIdx*/2, // mask |
| 65828 | GIR_RootConstrainSelectedInstOperands, |
| 65829 | // GIR_Coverage, 1109, |
| 65830 | GIR_EraseRootFromParent_Done, |
| 65831 | // Label 3645: @210356 |
| 65832 | GIM_Try, /*On fail goto*//*Label 3646*/ GIMT_Encode4(210417), // Rule ID 944 // |
| 65833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65834 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 65835 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24193), |
| 65839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65840 | // (intrinsic_wo_chain:{ *:[f32] } 2010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24193>> => (V_S_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F32_e64), |
| 65842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65847 | GIR_RootConstrainSelectedInstOperands, |
| 65848 | // GIR_Coverage, 944, |
| 65849 | GIR_EraseRootFromParent_Done, |
| 65850 | // Label 3646: @210417 |
| 65851 | GIM_Try, /*On fail goto*//*Label 3647*/ GIMT_Encode4(210478), // Rule ID 946 // |
| 65852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 65854 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65855 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65857 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24196), |
| 65858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65859 | // (intrinsic_wo_chain:{ *:[f32] } 2830:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24196>> => (V_S_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F32_e64), |
| 65861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65866 | GIR_RootConstrainSelectedInstOperands, |
| 65867 | // GIR_Coverage, 946, |
| 65868 | GIR_EraseRootFromParent_Done, |
| 65869 | // Label 3647: @210478 |
| 65870 | GIM_Try, /*On fail goto*//*Label 3648*/ GIMT_Encode4(210539), // Rule ID 948 // |
| 65871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 65873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65876 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24198), |
| 65877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65878 | // (intrinsic_wo_chain:{ *:[f32] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24198>> => (V_S_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RCP_F32_e64), |
| 65880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65885 | GIR_RootConstrainSelectedInstOperands, |
| 65886 | // GIR_Coverage, 948, |
| 65887 | GIR_EraseRootFromParent_Done, |
| 65888 | // Label 3648: @210539 |
| 65889 | GIM_Try, /*On fail goto*//*Label 3649*/ GIMT_Encode4(210600), // Rule ID 950 // |
| 65890 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65891 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 65892 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65893 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65895 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24200), |
| 65896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65897 | // (intrinsic_wo_chain:{ *:[f32] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24200>> => (V_S_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_RSQ_F32_e64), |
| 65899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65904 | GIR_RootConstrainSelectedInstOperands, |
| 65905 | // GIR_Coverage, 950, |
| 65906 | GIR_EraseRootFromParent_Done, |
| 65907 | // Label 3649: @210600 |
| 65908 | GIM_Try, /*On fail goto*//*Label 3650*/ GIMT_Encode4(210661), // Rule ID 953 // |
| 65909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 65910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 65911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 65914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24202), |
| 65915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65916 | // (intrinsic_wo_chain:{ *:[f32] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24202>> => (V_S_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F32_e64), |
| 65918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65923 | GIR_RootConstrainSelectedInstOperands, |
| 65924 | // GIR_Coverage, 953, |
| 65925 | GIR_EraseRootFromParent_Done, |
| 65926 | // Label 3650: @210661 |
| 65927 | GIM_Try, /*On fail goto*//*Label 3651*/ GIMT_Encode4(210715), // Rule ID 598 // |
| 65928 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract), |
| 65929 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65930 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 65932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65933 | // (intrinsic_wo_chain:{ *:[f32] } 2027:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FRACT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F32_e64), |
| 65935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65940 | GIR_RootConstrainSelectedInstOperands, |
| 65941 | // GIR_Coverage, 598, |
| 65942 | GIR_EraseRootFromParent_Done, |
| 65943 | // Label 3651: @210715 |
| 65944 | GIM_Try, /*On fail goto*//*Label 3652*/ GIMT_Encode4(210769), // Rule ID 604 // |
| 65945 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 65946 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65947 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 65949 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65950 | // (intrinsic_wo_chain:{ *:[f32] } 2010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_EXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F32_e64), |
| 65952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65957 | GIR_RootConstrainSelectedInstOperands, |
| 65958 | // GIR_Coverage, 604, |
| 65959 | GIR_EraseRootFromParent_Done, |
| 65960 | // Label 3652: @210769 |
| 65961 | GIM_Try, /*On fail goto*//*Label 3653*/ GIMT_Encode4(210823), // Rule ID 606 // |
| 65962 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 65963 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65964 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 65966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65967 | // (intrinsic_wo_chain:{ *:[f32] } 2830:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F32_e64), |
| 65969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65974 | GIR_RootConstrainSelectedInstOperands, |
| 65975 | // GIR_Coverage, 606, |
| 65976 | GIR_EraseRootFromParent_Done, |
| 65977 | // Label 3653: @210823 |
| 65978 | GIM_Try, /*On fail goto*//*Label 3654*/ GIMT_Encode4(210877), // Rule ID 608 // |
| 65979 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 65980 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65981 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 65983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 65984 | // (intrinsic_wo_chain:{ *:[f32] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 65985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F32_e64), |
| 65986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 65987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 65988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 65989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 65990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 65991 | GIR_RootConstrainSelectedInstOperands, |
| 65992 | // GIR_Coverage, 608, |
| 65993 | GIR_EraseRootFromParent_Done, |
| 65994 | // Label 3654: @210877 |
| 65995 | GIM_Try, /*On fail goto*//*Label 3655*/ GIMT_Encode4(210931), // Rule ID 611 // |
| 65996 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 65997 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 65998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 65999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66000 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66001 | // (intrinsic_wo_chain:{ *:[f32] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F32_e64), |
| 66003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66008 | GIR_RootConstrainSelectedInstOperands, |
| 66009 | // GIR_Coverage, 611, |
| 66010 | GIR_EraseRootFromParent_Done, |
| 66011 | // Label 3655: @210931 |
| 66012 | GIM_Try, /*On fail goto*//*Label 3656*/ GIMT_Encode4(210985), // Rule ID 613 // |
| 66013 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 66014 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66015 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66017 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66018 | // (intrinsic_wo_chain:{ *:[f32] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F32_e64), |
| 66020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66025 | GIR_RootConstrainSelectedInstOperands, |
| 66026 | // GIR_Coverage, 613, |
| 66027 | GIR_EraseRootFromParent_Done, |
| 66028 | // Label 3656: @210985 |
| 66029 | GIM_Try, /*On fail goto*//*Label 3657*/ GIMT_Encode4(211039), // Rule ID 614 // |
| 66030 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 66031 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66032 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66034 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66035 | // (intrinsic_wo_chain:{ *:[f64] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F64_e64), |
| 66037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66042 | GIR_RootConstrainSelectedInstOperands, |
| 66043 | // GIR_Coverage, 614, |
| 66044 | GIR_EraseRootFromParent_Done, |
| 66045 | // Label 3657: @211039 |
| 66046 | GIM_Try, /*On fail goto*//*Label 3658*/ GIMT_Encode4(211093), // Rule ID 616 // |
| 66047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 66048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66052 | // (intrinsic_wo_chain:{ *:[f64] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F64_e64), |
| 66054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66059 | GIR_RootConstrainSelectedInstOperands, |
| 66060 | // GIR_Coverage, 616, |
| 66061 | GIR_EraseRootFromParent_Done, |
| 66062 | // Label 3658: @211093 |
| 66063 | GIM_Try, /*On fail goto*//*Label 3659*/ GIMT_Encode4(211147), // Rule ID 618 // |
| 66064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 66065 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66066 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66068 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66069 | // (intrinsic_wo_chain:{ *:[f64] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F64_e64), |
| 66071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66076 | GIR_RootConstrainSelectedInstOperands, |
| 66077 | // GIR_Coverage, 618, |
| 66078 | GIR_EraseRootFromParent_Done, |
| 66079 | // Label 3659: @211147 |
| 66080 | GIM_Try, /*On fail goto*//*Label 3660*/ GIMT_Encode4(211201), // Rule ID 619 // |
| 66081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin), |
| 66082 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66083 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66086 | // (intrinsic_wo_chain:{ *:[f32] } 3010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F32_e64), |
| 66088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66093 | GIR_RootConstrainSelectedInstOperands, |
| 66094 | // GIR_Coverage, 619, |
| 66095 | GIR_EraseRootFromParent_Done, |
| 66096 | // Label 3660: @211201 |
| 66097 | GIM_Try, /*On fail goto*//*Label 3661*/ GIMT_Encode4(211255), // Rule ID 621 // |
| 66098 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos), |
| 66099 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66100 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66102 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66103 | // (intrinsic_wo_chain:{ *:[f32] } 1959:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_COS_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F32_e64), |
| 66105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66110 | GIR_RootConstrainSelectedInstOperands, |
| 66111 | // GIR_Coverage, 621, |
| 66112 | GIR_EraseRootFromParent_Done, |
| 66113 | // Label 3661: @211255 |
| 66114 | GIM_Try, /*On fail goto*//*Label 3662*/ GIMT_Encode4(211294), // Rule ID 628 // |
| 66115 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sffbh), |
| 66116 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66117 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66120 | // (intrinsic_wo_chain:{ *:[i32] } 3009:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_FFBH_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 66121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_I32_e64), |
| 66122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66124 | GIR_RootConstrainSelectedInstOperands, |
| 66125 | // GIR_Coverage, 628, |
| 66126 | GIR_EraseRootFromParent_Done, |
| 66127 | // Label 3662: @211294 |
| 66128 | GIM_Try, /*On fail goto*//*Label 3663*/ GIMT_Encode4(211348), // Rule ID 630 // |
| 66129 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp), |
| 66130 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66131 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66133 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66134 | // (intrinsic_wo_chain:{ *:[i32] } 2028:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_EXP_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F64_e64), |
| 66136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66141 | GIR_RootConstrainSelectedInstOperands, |
| 66142 | // GIR_Coverage, 630, |
| 66143 | GIR_EraseRootFromParent_Done, |
| 66144 | // Label 3663: @211348 |
| 66145 | GIM_Try, /*On fail goto*//*Label 3664*/ GIMT_Encode4(211402), // Rule ID 631 // |
| 66146 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant), |
| 66147 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66148 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66149 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66150 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66151 | // (intrinsic_wo_chain:{ *:[f64] } 2029:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_MANT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F64_e64), |
| 66153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66158 | GIR_RootConstrainSelectedInstOperands, |
| 66159 | // GIR_Coverage, 631, |
| 66160 | GIR_EraseRootFromParent_Done, |
| 66161 | // Label 3664: @211402 |
| 66162 | GIM_Try, /*On fail goto*//*Label 3665*/ GIMT_Encode4(211456), // Rule ID 632 // |
| 66163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract), |
| 66164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66167 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66168 | // (intrinsic_wo_chain:{ *:[f64] } 2027:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FRACT_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64), |
| 66170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66175 | GIR_RootConstrainSelectedInstOperands, |
| 66176 | // GIR_Coverage, 632, |
| 66177 | GIR_EraseRootFromParent_Done, |
| 66178 | // Label 3665: @211456 |
| 66179 | GIM_Try, /*On fail goto*//*Label 3666*/ GIMT_Encode4(211505), // Rule ID 634 // |
| 66180 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp), |
| 66181 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66182 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66183 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66185 | // (intrinsic_wo_chain:{ *:[i32] } 2028:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp)) => (V_FREXP_EXP_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp) |
| 66186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I32_F32_e64), |
| 66187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66191 | GIR_RootConstrainSelectedInstOperands, |
| 66192 | // GIR_Coverage, 634, |
| 66193 | GIR_EraseRootFromParent_Done, |
| 66194 | // Label 3666: @211505 |
| 66195 | GIM_Try, /*On fail goto*//*Label 3667*/ GIMT_Encode4(211559), // Rule ID 635 // |
| 66196 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant), |
| 66197 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66198 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66201 | // (intrinsic_wo_chain:{ *:[f32] } 2029:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_MANT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F32_e64), |
| 66203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66208 | GIR_RootConstrainSelectedInstOperands, |
| 66209 | // GIR_Coverage, 635, |
| 66210 | GIR_EraseRootFromParent_Done, |
| 66211 | // Label 3667: @211559 |
| 66212 | GIM_Try, /*On fail goto*//*Label 3668*/ GIMT_Encode4(211616), // Rule ID 636 // |
| 66213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 66214 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log_clamp), |
| 66215 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66219 | // (intrinsic_wo_chain:{ *:[f32] } 2831:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_CLAMP_F32_e64), |
| 66221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66226 | GIR_RootConstrainSelectedInstOperands, |
| 66227 | // GIR_Coverage, 636, |
| 66228 | GIR_EraseRootFromParent_Done, |
| 66229 | // Label 3668: @211616 |
| 66230 | GIM_Try, /*On fail goto*//*Label 3669*/ GIMT_Encode4(211673), // Rule ID 637 // |
| 66231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 66232 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp_legacy), |
| 66233 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66234 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66236 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66237 | // (intrinsic_wo_chain:{ *:[f32] } 2945:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_LEGACY_F32_e64), |
| 66239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66244 | GIR_RootConstrainSelectedInstOperands, |
| 66245 | // GIR_Coverage, 637, |
| 66246 | GIR_EraseRootFromParent_Done, |
| 66247 | // Label 3669: @211673 |
| 66248 | GIM_Try, /*On fail goto*//*Label 3670*/ GIMT_Encode4(211730), // Rule ID 639 // |
| 66249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 66250 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp), |
| 66251 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66252 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66254 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66255 | // (intrinsic_wo_chain:{ *:[f32] } 2950:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_CLAMP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F32_e64), |
| 66257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66262 | GIR_RootConstrainSelectedInstOperands, |
| 66263 | // GIR_Coverage, 639, |
| 66264 | GIR_EraseRootFromParent_Done, |
| 66265 | // Label 3670: @211730 |
| 66266 | GIM_Try, /*On fail goto*//*Label 3671*/ GIMT_Encode4(211787), // Rule ID 641 // |
| 66267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 66268 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_legacy), |
| 66269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66272 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66273 | // (intrinsic_wo_chain:{ *:[f32] } 2951:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_LEGACY_F32_e64), |
| 66275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66280 | GIR_RootConstrainSelectedInstOperands, |
| 66281 | // GIR_Coverage, 641, |
| 66282 | GIR_EraseRootFromParent_Done, |
| 66283 | // Label 3671: @211787 |
| 66284 | GIM_Try, /*On fail goto*//*Label 3672*/ GIMT_Encode4(211844), // Rule ID 642 // |
| 66285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 66286 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq_clamp), |
| 66287 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 66288 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 66289 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 66290 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66291 | // (intrinsic_wo_chain:{ *:[f64] } 2950:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_CLAMP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_CLAMP_F64_e64), |
| 66293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66298 | GIR_RootConstrainSelectedInstOperands, |
| 66299 | // GIR_Coverage, 642, |
| 66300 | GIR_EraseRootFromParent_Done, |
| 66301 | // Label 3672: @211844 |
| 66302 | GIM_Try, /*On fail goto*//*Label 3673*/ GIMT_Encode4(211901), // Rule ID 656 // |
| 66303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66304 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 66305 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66306 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66307 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66308 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66309 | // (intrinsic_wo_chain:{ *:[f16] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_e64), |
| 66311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66316 | GIR_RootConstrainSelectedInstOperands, |
| 66317 | // GIR_Coverage, 656, |
| 66318 | GIR_EraseRootFromParent_Done, |
| 66319 | // Label 3673: @211901 |
| 66320 | GIM_Try, /*On fail goto*//*Label 3674*/ GIMT_Encode4(211958), // Rule ID 660 // |
| 66321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66322 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 66323 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66327 | // (intrinsic_wo_chain:{ *:[f16] } 2944:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_fake16_e64), |
| 66329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66334 | GIR_RootConstrainSelectedInstOperands, |
| 66335 | // GIR_Coverage, 660, |
| 66336 | GIR_EraseRootFromParent_Done, |
| 66337 | // Label 3674: @211958 |
| 66338 | GIM_Try, /*On fail goto*//*Label 3675*/ GIMT_Encode4(212015), // Rule ID 663 // |
| 66339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66340 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 66341 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66345 | // (intrinsic_wo_chain:{ *:[f16] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_e64), |
| 66347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66352 | GIR_RootConstrainSelectedInstOperands, |
| 66353 | // GIR_Coverage, 663, |
| 66354 | GIR_EraseRootFromParent_Done, |
| 66355 | // Label 3675: @212015 |
| 66356 | GIM_Try, /*On fail goto*//*Label 3676*/ GIMT_Encode4(212072), // Rule ID 667 // |
| 66357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66358 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 66359 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66360 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66363 | // (intrinsic_wo_chain:{ *:[f16] } 3026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_fake16_e64), |
| 66365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66370 | GIR_RootConstrainSelectedInstOperands, |
| 66371 | // GIR_Coverage, 667, |
| 66372 | GIR_EraseRootFromParent_Done, |
| 66373 | // Label 3676: @212072 |
| 66374 | GIM_Try, /*On fail goto*//*Label 3677*/ GIMT_Encode4(212129), // Rule ID 668 // |
| 66375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 66377 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66378 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66381 | // (intrinsic_wo_chain:{ *:[f16] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_e64), |
| 66383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66388 | GIR_RootConstrainSelectedInstOperands, |
| 66389 | // GIR_Coverage, 668, |
| 66390 | GIR_EraseRootFromParent_Done, |
| 66391 | // Label 3677: @212129 |
| 66392 | GIM_Try, /*On fail goto*//*Label 3678*/ GIMT_Encode4(212186), // Rule ID 672 // |
| 66393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 66395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66399 | // (intrinsic_wo_chain:{ *:[f16] } 2949:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RSQ_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_fake16_e64), |
| 66401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66406 | GIR_RootConstrainSelectedInstOperands, |
| 66407 | // GIR_Coverage, 672, |
| 66408 | GIR_EraseRootFromParent_Done, |
| 66409 | // Label 3678: @212186 |
| 66410 | GIM_Try, /*On fail goto*//*Label 3679*/ GIMT_Encode4(212243), // Rule ID 674 // |
| 66411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66412 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 66413 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66414 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66417 | // (intrinsic_wo_chain:{ *:[f16] } 2830:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_e64), |
| 66419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66424 | GIR_RootConstrainSelectedInstOperands, |
| 66425 | // GIR_Coverage, 674, |
| 66426 | GIR_EraseRootFromParent_Done, |
| 66427 | // Label 3679: @212243 |
| 66428 | GIM_Try, /*On fail goto*//*Label 3680*/ GIMT_Encode4(212300), // Rule ID 678 // |
| 66429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66430 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 66431 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66432 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66435 | // (intrinsic_wo_chain:{ *:[f16] } 2830:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_fake16_e64), |
| 66437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66442 | GIR_RootConstrainSelectedInstOperands, |
| 66443 | // GIR_Coverage, 678, |
| 66444 | GIR_EraseRootFromParent_Done, |
| 66445 | // Label 3680: @212300 |
| 66446 | GIM_Try, /*On fail goto*//*Label 3681*/ GIMT_Encode4(212357), // Rule ID 680 // |
| 66447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66448 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 66449 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66450 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66453 | // (intrinsic_wo_chain:{ *:[f16] } 2010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_e64), |
| 66455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66460 | GIR_RootConstrainSelectedInstOperands, |
| 66461 | // GIR_Coverage, 680, |
| 66462 | GIR_EraseRootFromParent_Done, |
| 66463 | // Label 3681: @212357 |
| 66464 | GIM_Try, /*On fail goto*//*Label 3682*/ GIMT_Encode4(212414), // Rule ID 684 // |
| 66465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 66467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66471 | // (intrinsic_wo_chain:{ *:[f16] } 2010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_EXP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_fake16_e64), |
| 66473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66478 | GIR_RootConstrainSelectedInstOperands, |
| 66479 | // GIR_Coverage, 684, |
| 66480 | GIR_EraseRootFromParent_Done, |
| 66481 | // Label 3682: @212414 |
| 66482 | GIM_Try, /*On fail goto*//*Label 3683*/ GIMT_Encode4(212471), // Rule ID 686 // |
| 66483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66484 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin), |
| 66485 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66488 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66489 | // (intrinsic_wo_chain:{ *:[f16] } 3010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_e64), |
| 66491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66496 | GIR_RootConstrainSelectedInstOperands, |
| 66497 | // GIR_Coverage, 686, |
| 66498 | GIR_EraseRootFromParent_Done, |
| 66499 | // Label 3683: @212471 |
| 66500 | GIM_Try, /*On fail goto*//*Label 3684*/ GIMT_Encode4(212528), // Rule ID 690 // |
| 66501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin), |
| 66503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66507 | // (intrinsic_wo_chain:{ *:[f16] } 3010:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_fake16_e64), |
| 66509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66514 | GIR_RootConstrainSelectedInstOperands, |
| 66515 | // GIR_Coverage, 690, |
| 66516 | GIR_EraseRootFromParent_Done, |
| 66517 | // Label 3684: @212528 |
| 66518 | GIM_Try, /*On fail goto*//*Label 3685*/ GIMT_Encode4(212585), // Rule ID 692 // |
| 66519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos), |
| 66521 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66522 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66524 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66525 | // (intrinsic_wo_chain:{ *:[f16] } 1959:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_COS_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_e64), |
| 66527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66532 | GIR_RootConstrainSelectedInstOperands, |
| 66533 | // GIR_Coverage, 692, |
| 66534 | GIR_EraseRootFromParent_Done, |
| 66535 | // Label 3685: @212585 |
| 66536 | GIM_Try, /*On fail goto*//*Label 3686*/ GIMT_Encode4(212642), // Rule ID 696 // |
| 66537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66538 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos), |
| 66539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66543 | // (intrinsic_wo_chain:{ *:[f16] } 1959:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_COS_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_fake16_e64), |
| 66545 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66550 | GIR_RootConstrainSelectedInstOperands, |
| 66551 | // GIR_Coverage, 696, |
| 66552 | GIR_EraseRootFromParent_Done, |
| 66553 | // Label 3686: @212642 |
| 66554 | GIM_Try, /*On fail goto*//*Label 3687*/ GIMT_Encode4(212699), // Rule ID 698 // |
| 66555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66556 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant), |
| 66557 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66561 | // (intrinsic_wo_chain:{ *:[f16] } 2029:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_MANT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_e64), |
| 66563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66568 | GIR_RootConstrainSelectedInstOperands, |
| 66569 | // GIR_Coverage, 698, |
| 66570 | GIR_EraseRootFromParent_Done, |
| 66571 | // Label 3687: @212699 |
| 66572 | GIM_Try, /*On fail goto*//*Label 3688*/ GIMT_Encode4(212756), // Rule ID 700 // |
| 66573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66574 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant), |
| 66575 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66578 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66579 | // (intrinsic_wo_chain:{ *:[f16] } 2029:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_MANT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_fake16_e64), |
| 66581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66586 | GIR_RootConstrainSelectedInstOperands, |
| 66587 | // GIR_Coverage, 700, |
| 66588 | GIR_EraseRootFromParent_Done, |
| 66589 | // Label 3688: @212756 |
| 66590 | GIM_Try, /*On fail goto*//*Label 3689*/ GIMT_Encode4(212813), // Rule ID 701 // |
| 66591 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66592 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp), |
| 66593 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66597 | // (intrinsic_wo_chain:{ *:[i16] } 2028:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_EXP_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_e64), |
| 66599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66604 | GIR_RootConstrainSelectedInstOperands, |
| 66605 | // GIR_Coverage, 701, |
| 66606 | GIR_EraseRootFromParent_Done, |
| 66607 | // Label 3689: @212813 |
| 66608 | GIM_Try, /*On fail goto*//*Label 3690*/ GIMT_Encode4(212870), // Rule ID 702 // |
| 66609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 66610 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_exp), |
| 66611 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66612 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66615 | // (intrinsic_wo_chain:{ *:[i16] } 2028:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FREXP_EXP_I16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_EXP_I16_F16_t16_e64), |
| 66617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66622 | GIR_RootConstrainSelectedInstOperands, |
| 66623 | // GIR_Coverage, 702, |
| 66624 | GIR_EraseRootFromParent_Done, |
| 66625 | // Label 3690: @212870 |
| 66626 | GIM_Try, /*On fail goto*//*Label 3691*/ GIMT_Encode4(212927), // Rule ID 715 // |
| 66627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 66628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract), |
| 66629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66630 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66633 | // (intrinsic_wo_chain:{ *:[f16] } 2027:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FRACT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_e64), |
| 66635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66640 | GIR_RootConstrainSelectedInstOperands, |
| 66641 | // GIR_Coverage, 715, |
| 66642 | GIR_EraseRootFromParent_Done, |
| 66643 | // Label 3691: @212927 |
| 66644 | GIM_Try, /*On fail goto*//*Label 3692*/ GIMT_Encode4(212984), // Rule ID 719 // |
| 66645 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 66646 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract), |
| 66647 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66648 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 66651 | // (intrinsic_wo_chain:{ *:[f16] } 2027:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FRACT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 66652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_fake16_e64), |
| 66653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 66657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 66658 | GIR_RootConstrainSelectedInstOperands, |
| 66659 | // GIR_Coverage, 719, |
| 66660 | GIR_EraseRootFromParent_Done, |
| 66661 | // Label 3692: @212984 |
| 66662 | GIM_Try, /*On fail goto*//*Label 3693*/ GIMT_Encode4(213040), // Rule ID 658 // |
| 66663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66664 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rcp), |
| 66665 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66666 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66669 | // (intrinsic_wo_chain:{ *:[f16] } 2944:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_RCP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_F16_t16_e64), |
| 66671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66677 | GIR_RootConstrainSelectedInstOperands, |
| 66678 | // GIR_Coverage, 658, |
| 66679 | GIR_EraseRootFromParent_Done, |
| 66680 | // Label 3693: @213040 |
| 66681 | GIM_Try, /*On fail goto*//*Label 3694*/ GIMT_Encode4(213096), // Rule ID 665 // |
| 66682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66683 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sqrt), |
| 66684 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66685 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66688 | // (intrinsic_wo_chain:{ *:[f16] } 3026:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_SQRT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_t16_e64), |
| 66690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66696 | GIR_RootConstrainSelectedInstOperands, |
| 66697 | // GIR_Coverage, 665, |
| 66698 | GIR_EraseRootFromParent_Done, |
| 66699 | // Label 3694: @213096 |
| 66700 | GIM_Try, /*On fail goto*//*Label 3695*/ GIMT_Encode4(213152), // Rule ID 670 // |
| 66701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66702 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_rsq), |
| 66703 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66704 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66706 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66707 | // (intrinsic_wo_chain:{ *:[f16] } 2949:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_RSQ_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RSQ_F16_t16_e64), |
| 66709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66715 | GIR_RootConstrainSelectedInstOperands, |
| 66716 | // GIR_Coverage, 670, |
| 66717 | GIR_EraseRootFromParent_Done, |
| 66718 | // Label 3695: @213152 |
| 66719 | GIM_Try, /*On fail goto*//*Label 3696*/ GIMT_Encode4(213208), // Rule ID 676 // |
| 66720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66721 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_log), |
| 66722 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66723 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66725 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66726 | // (intrinsic_wo_chain:{ *:[f16] } 2830:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_LOG_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_t16_e64), |
| 66728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66734 | GIR_RootConstrainSelectedInstOperands, |
| 66735 | // GIR_Coverage, 676, |
| 66736 | GIR_EraseRootFromParent_Done, |
| 66737 | // Label 3696: @213208 |
| 66738 | GIM_Try, /*On fail goto*//*Label 3697*/ GIMT_Encode4(213264), // Rule ID 682 // |
| 66739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66740 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_exp2), |
| 66741 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66745 | // (intrinsic_wo_chain:{ *:[f16] } 2010:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_EXP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_t16_e64), |
| 66747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66753 | GIR_RootConstrainSelectedInstOperands, |
| 66754 | // GIR_Coverage, 682, |
| 66755 | GIR_EraseRootFromParent_Done, |
| 66756 | // Label 3697: @213264 |
| 66757 | GIM_Try, /*On fail goto*//*Label 3698*/ GIMT_Encode4(213320), // Rule ID 688 // |
| 66758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66759 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sin), |
| 66760 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66761 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66763 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66764 | // (intrinsic_wo_chain:{ *:[f16] } 3010:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_SIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SIN_F16_t16_e64), |
| 66766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66772 | GIR_RootConstrainSelectedInstOperands, |
| 66773 | // GIR_Coverage, 688, |
| 66774 | GIR_EraseRootFromParent_Done, |
| 66775 | // Label 3698: @213320 |
| 66776 | GIM_Try, /*On fail goto*//*Label 3699*/ GIMT_Encode4(213376), // Rule ID 694 // |
| 66777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66778 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cos), |
| 66779 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66780 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66783 | // (intrinsic_wo_chain:{ *:[f16] } 1959:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_COS_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_COS_F16_t16_e64), |
| 66785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66791 | GIR_RootConstrainSelectedInstOperands, |
| 66792 | // GIR_Coverage, 694, |
| 66793 | GIR_EraseRootFromParent_Done, |
| 66794 | // Label 3699: @213376 |
| 66795 | GIM_Try, /*On fail goto*//*Label 3700*/ GIMT_Encode4(213432), // Rule ID 699 // |
| 66796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66797 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_frexp_mant), |
| 66798 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66799 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66801 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66802 | // (intrinsic_wo_chain:{ *:[f16] } 2029:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_FREXP_MANT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FREXP_MANT_F16_t16_e64), |
| 66804 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66810 | GIR_RootConstrainSelectedInstOperands, |
| 66811 | // GIR_Coverage, 699, |
| 66812 | GIR_EraseRootFromParent_Done, |
| 66813 | // Label 3700: @213432 |
| 66814 | GIM_Try, /*On fail goto*//*Label 3701*/ GIMT_Encode4(213488), // Rule ID 717 // |
| 66815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 66816 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fract), |
| 66817 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 66818 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 66819 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 66820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 66821 | // (intrinsic_wo_chain:{ *:[f16] } 2027:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_FRACT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 66822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F16_t16_e64), |
| 66823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 66825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 66826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66829 | GIR_RootConstrainSelectedInstOperands, |
| 66830 | // GIR_Coverage, 717, |
| 66831 | GIR_EraseRootFromParent_Done, |
| 66832 | // Label 3701: @213488 |
| 66833 | GIM_Reject, |
| 66834 | // Label 3637: @213489 |
| 66835 | GIM_Try, /*On fail goto*//*Label 3702*/ GIMT_Encode4(215869), |
| 66836 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 66837 | GIM_Try, /*On fail goto*//*Label 3703*/ GIMT_Encode4(213552), // Rule ID 2062 // |
| 66838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_isGFX9Only), |
| 66839 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 66840 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66841 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66843 | // MIs[0] Operand 3 |
| 66844 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 66845 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] }) => (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 66846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa), |
| 66847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66849 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66853 | GIR_RootConstrainSelectedInstOperands, |
| 66854 | // GIR_Coverage, 2062, |
| 66855 | GIR_EraseRootFromParent_Done, |
| 66856 | // Label 3703: @213552 |
| 66857 | GIM_Try, /*On fail goto*//*Label 3704*/ GIMT_Encode4(213607), // Rule ID 2063 // |
| 66858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasCvtFP8VOP1Bug_isGFX9Only), |
| 66859 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 66860 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66861 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66863 | // MIs[0] Operand 3 |
| 66864 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 66865 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] }) => (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 66866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa), |
| 66867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66869 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66873 | GIR_RootConstrainSelectedInstOperands, |
| 66874 | // GIR_Coverage, 2063, |
| 66875 | GIR_EraseRootFromParent_Done, |
| 66876 | // Label 3704: @213607 |
| 66877 | GIM_Try, /*On fail goto*//*Label 3705*/ GIMT_Encode4(213650), // Rule ID 2064 // |
| 66878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only), |
| 66879 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 66880 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66881 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66883 | // MIs[0] Operand 3 |
| 66884 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 66885 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] }) => (V_CVT_F32_FP8_e32:{ *:[f32] } ?:{ *:[i32] }:$src) |
| 66886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_e32), |
| 66887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66888 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66889 | GIR_RootConstrainSelectedInstOperands, |
| 66890 | // GIR_Coverage, 2064, |
| 66891 | GIR_EraseRootFromParent_Done, |
| 66892 | // Label 3705: @213650 |
| 66893 | GIM_Try, /*On fail goto*//*Label 3706*/ GIMT_Encode4(213693), // Rule ID 2065 // |
| 66894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasNoCvtFP8VOP1Bug_isGFX9Only), |
| 66895 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 66896 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66897 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66899 | // MIs[0] Operand 3 |
| 66900 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 66901 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i32] }) => (V_CVT_F32_BF8_e32:{ *:[f32] } ?:{ *:[i32] }:$src) |
| 66902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_e32), |
| 66903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66904 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66905 | GIR_RootConstrainSelectedInstOperands, |
| 66906 | // GIR_Coverage, 2065, |
| 66907 | GIR_EraseRootFromParent_Done, |
| 66908 | // Label 3706: @213693 |
| 66909 | GIM_Try, /*On fail goto*//*Label 3707*/ GIMT_Encode4(213748), // Rule ID 2066 // |
| 66910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 66911 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 66912 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66915 | // MIs[0] Operand 3 |
| 66916 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1), |
| 66917 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] }) => (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] }) |
| 66918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa), |
| 66919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66921 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 66925 | GIR_RootConstrainSelectedInstOperands, |
| 66926 | // GIR_Coverage, 2066, |
| 66927 | GIR_EraseRootFromParent_Done, |
| 66928 | // Label 3707: @213748 |
| 66929 | GIM_Try, /*On fail goto*//*Label 3708*/ GIMT_Encode4(213803), // Rule ID 2067 // |
| 66930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 66931 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 66932 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66933 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66935 | // MIs[0] Operand 3 |
| 66936 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(1), |
| 66937 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 1:{ *:[i32] }) => (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 1:{ *:[i32] }) |
| 66938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa), |
| 66939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66941 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 66945 | GIR_RootConstrainSelectedInstOperands, |
| 66946 | // GIR_Coverage, 2067, |
| 66947 | GIR_EraseRootFromParent_Done, |
| 66948 | // Label 3708: @213803 |
| 66949 | GIM_Try, /*On fail goto*//*Label 3709*/ GIMT_Encode4(213858), // Rule ID 2068 // |
| 66950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 66951 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 66952 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66955 | // MIs[0] Operand 3 |
| 66956 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2), |
| 66957 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] }) => (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] }) |
| 66958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa), |
| 66959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66961 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 66965 | GIR_RootConstrainSelectedInstOperands, |
| 66966 | // GIR_Coverage, 2068, |
| 66967 | GIR_EraseRootFromParent_Done, |
| 66968 | // Label 3709: @213858 |
| 66969 | GIM_Try, /*On fail goto*//*Label 3710*/ GIMT_Encode4(213913), // Rule ID 2069 // |
| 66970 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 66971 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 66972 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66973 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66975 | // MIs[0] Operand 3 |
| 66976 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(2), |
| 66977 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 2:{ *:[i32] }) => (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 2:{ *:[i32] }) |
| 66978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa), |
| 66979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 66980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66981 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 66982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 66984 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 66985 | GIR_RootConstrainSelectedInstOperands, |
| 66986 | // GIR_Coverage, 2069, |
| 66987 | GIR_EraseRootFromParent_Done, |
| 66988 | // Label 3710: @213913 |
| 66989 | GIM_Try, /*On fail goto*//*Label 3711*/ GIMT_Encode4(213968), // Rule ID 2070 // |
| 66990 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 66991 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 66992 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 66993 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 66994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 66995 | // MIs[0] Operand 3 |
| 66996 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3), |
| 66997 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] }) => (V_CVT_F32_FP8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 66998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_sdwa), |
| 66999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67001 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 67005 | GIR_RootConstrainSelectedInstOperands, |
| 67006 | // GIR_Coverage, 2070, |
| 67007 | GIR_EraseRootFromParent_Done, |
| 67008 | // Label 3711: @213968 |
| 67009 | GIM_Try, /*On fail goto*//*Label 3712*/ GIMT_Encode4(214023), // Rule ID 2071 // |
| 67010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 67011 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 67012 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67014 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67015 | // MIs[0] Operand 3 |
| 67016 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(3), |
| 67017 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 3:{ *:[i32] }) => (V_CVT_F32_BF8_sdwa:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 3:{ *:[i32] }) |
| 67018 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_sdwa), |
| 67019 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67021 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 67025 | GIR_RootConstrainSelectedInstOperands, |
| 67026 | // GIR_Coverage, 2071, |
| 67027 | GIR_EraseRootFromParent_Done, |
| 67028 | // Label 3712: @214023 |
| 67029 | GIM_Try, /*On fail goto*//*Label 3713*/ GIMT_Encode4(214066), // Rule ID 2072 // |
| 67030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 67031 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8), |
| 67032 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67035 | // MIs[0] Operand 3 |
| 67036 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 67037 | // (intrinsic_wo_chain:{ *:[v2f32] } 1969:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] }) => (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src) |
| 67038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32), |
| 67039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67040 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67041 | GIR_RootConstrainSelectedInstOperands, |
| 67042 | // GIR_Coverage, 2072, |
| 67043 | GIR_EraseRootFromParent_Done, |
| 67044 | // Label 3713: @214066 |
| 67045 | GIM_Try, /*On fail goto*//*Label 3714*/ GIMT_Encode4(214109), // Rule ID 2073 // |
| 67046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 67047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8), |
| 67048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67049 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67051 | // MIs[0] Operand 3 |
| 67052 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 67053 | // (intrinsic_wo_chain:{ *:[v2f32] } 1968:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] }) => (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src) |
| 67054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32), |
| 67055 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67056 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67057 | GIR_RootConstrainSelectedInstOperands, |
| 67058 | // GIR_Coverage, 2073, |
| 67059 | GIR_EraseRootFromParent_Done, |
| 67060 | // Label 3714: @214109 |
| 67061 | GIM_Try, /*On fail goto*//*Label 3715*/ GIMT_Encode4(214164), // Rule ID 2074 // |
| 67062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 67063 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8), |
| 67064 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67065 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67067 | // MIs[0] Operand 3 |
| 67068 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1), |
| 67069 | // (intrinsic_wo_chain:{ *:[v2f32] } 1969:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] }) => (V_CVT_PK_F32_FP8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] }) |
| 67070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_sdwa), |
| 67071 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67073 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67077 | GIR_RootConstrainSelectedInstOperands, |
| 67078 | // GIR_Coverage, 2074, |
| 67079 | GIR_EraseRootFromParent_Done, |
| 67080 | // Label 3715: @214164 |
| 67081 | GIM_Try, /*On fail goto*//*Label 3716*/ GIMT_Encode4(214219), // Rule ID 2075 // |
| 67082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Only), |
| 67083 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8), |
| 67084 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67085 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67086 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67087 | // MIs[0] Operand 3 |
| 67088 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1), |
| 67089 | // (intrinsic_wo_chain:{ *:[v2f32] } 1968:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] }) => (V_CVT_PK_F32_BF8_sdwa:{ *:[v2f32] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 5:{ *:[i32] }) |
| 67090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_sdwa), |
| 67091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67093 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/5, |
| 67097 | GIR_RootConstrainSelectedInstOperands, |
| 67098 | // GIR_Coverage, 2075, |
| 67099 | GIR_EraseRootFromParent_Done, |
| 67100 | // Label 3716: @214219 |
| 67101 | GIM_Try, /*On fail goto*//*Label 3717*/ GIMT_Encode4(214262), // Rule ID 2078 // |
| 67102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67103 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8), |
| 67104 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67105 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67107 | // MIs[0] Operand 3 |
| 67108 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 67109 | // (intrinsic_wo_chain:{ *:[v2f32] } 1969:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] }) => (V_CVT_PK_F32_FP8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src) |
| 67110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_e32), |
| 67111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67112 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67113 | GIR_RootConstrainSelectedInstOperands, |
| 67114 | // GIR_Coverage, 2078, |
| 67115 | GIR_EraseRootFromParent_Done, |
| 67116 | // Label 3717: @214262 |
| 67117 | GIM_Try, /*On fail goto*//*Label 3718*/ GIMT_Encode4(214305), // Rule ID 2079 // |
| 67118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67119 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8), |
| 67120 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67121 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67123 | // MIs[0] Operand 3 |
| 67124 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(0), |
| 67125 | // (intrinsic_wo_chain:{ *:[v2f32] } 1968:{ *:[iPTR] }, i32:{ *:[i32] }:$src, 0:{ *:[i1] }) => (V_CVT_PK_F32_BF8_e32:{ *:[v2f32] } ?:{ *:[i32] }:$src) |
| 67126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_e32), |
| 67127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67128 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67129 | GIR_RootConstrainSelectedInstOperands, |
| 67130 | // GIR_Coverage, 2079, |
| 67131 | GIR_EraseRootFromParent_Done, |
| 67132 | // Label 3718: @214305 |
| 67133 | GIM_Try, /*On fail goto*//*Label 3719*/ GIMT_Encode4(214360), // Rule ID 2080 // |
| 67134 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67135 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_fp8), |
| 67136 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67137 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67139 | // MIs[0] Operand 3 |
| 67140 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1), |
| 67141 | // (intrinsic_wo_chain:{ *:[v2f32] } 1969:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] }) => (V_CVT_PK_F32_FP8_OP_SEL_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 67142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_FP8_OP_SEL_e64), |
| 67143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67145 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67149 | GIR_RootConstrainSelectedInstOperands, |
| 67150 | // GIR_Coverage, 2080, |
| 67151 | GIR_EraseRootFromParent_Done, |
| 67152 | // Label 3719: @214360 |
| 67153 | GIM_Try, /*On fail goto*//*Label 3720*/ GIMT_Encode4(214415), // Rule ID 2081 // |
| 67154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67155 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_f32_bf8), |
| 67156 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 67157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67159 | // MIs[0] Operand 3 |
| 67160 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/3, GIMT_Encode8(-1), |
| 67161 | // (intrinsic_wo_chain:{ *:[v2f32] } 1968:{ *:[iPTR] }, i32:{ *:[i32] }:$src, -1:{ *:[i1] }) => (V_CVT_PK_F32_BF8_OP_SEL_e64:{ *:[v2f32] } 4:{ *:[i32] }, ?:{ *:[i32] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 67162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_F32_BF8_OP_SEL_e64), |
| 67163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 67165 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 67166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67169 | GIR_RootConstrainSelectedInstOperands, |
| 67170 | // GIR_Coverage, 2081, |
| 67171 | GIR_EraseRootFromParent_Done, |
| 67172 | // Label 3720: @214415 |
| 67173 | GIM_Try, /*On fail goto*//*Label 3721*/ GIMT_Encode4(214456), // Rule ID 2076 // |
| 67174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67175 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_fp8), |
| 67176 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67177 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67179 | // MIs[0] byte_sel |
| 67180 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 67181 | // (intrinsic_wo_chain:{ *:[f32] } 1966:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel) => (V_CVT_F32_FP8_OP_SEL_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i8] } ?:{ *:[i32] }:$byte_sel)) |
| 67182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_FP8_OP_SEL_e64), |
| 67183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67184 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67185 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel |
| 67186 | GIR_RootConstrainSelectedInstOperands, |
| 67187 | // GIR_Coverage, 2076, |
| 67188 | GIR_EraseRootFromParent_Done, |
| 67189 | // Label 3721: @214456 |
| 67190 | GIM_Try, /*On fail goto*//*Label 3722*/ GIMT_Encode4(214497), // Rule ID 2077 // |
| 67191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 67192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_f32_bf8), |
| 67193 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67196 | // MIs[0] byte_sel |
| 67197 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 67198 | // (intrinsic_wo_chain:{ *:[f32] } 1965:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, (timm:{ *:[i32] }):$byte_sel) => (V_CVT_F32_BF8_OP_SEL_e64:{ *:[f32] } ?:{ *:[i32] }:$src0, (as_i32timm:{ *:[i8] } ?:{ *:[i32] }:$byte_sel)) |
| 67199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_BF8_OP_SEL_e64), |
| 67200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67201 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67202 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel |
| 67203 | GIR_RootConstrainSelectedInstOperands, |
| 67204 | // GIR_Coverage, 2077, |
| 67205 | GIR_EraseRootFromParent_Done, |
| 67206 | // Label 3722: @214497 |
| 67207 | GIM_Try, /*On fail goto*//*Label 3723*/ GIMT_Encode4(214546), // Rule ID 110 // |
| 67208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 67209 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz), |
| 67210 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67211 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67212 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 67214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 67215 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 67216 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18523), |
| 67217 | // (intrinsic_wo_chain:{ *:[v2f16] } 1976:{ *:[iPTR] }, SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18523>> => (S_CVT_PK_RTZ_F16_F32:{ *:[v2f16] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 67218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_PK_RTZ_F16_F32), |
| 67219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67220 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67221 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67222 | GIR_RootConstrainSelectedInstOperands, |
| 67223 | // GIR_Coverage, 110, |
| 67224 | GIR_EraseRootFromParent_Done, |
| 67225 | // Label 3723: @214546 |
| 67226 | GIM_Try, /*On fail goto*//*Label 3724*/ GIMT_Encode4(214649), // Rule ID 2141 // |
| 67227 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24), |
| 67228 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 67229 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67230 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67232 | // (intrinsic_wo_chain:{ *:[i64] } 2880:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_I32_I24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] }) |
| 67233 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 67234 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 67235 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64), |
| 67236 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 67237 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0 |
| 67238 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1 |
| 67239 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 67240 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64), |
| 67241 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 67242 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0 |
| 67243 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1 |
| 67244 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 67245 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 67246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 67247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 67248 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 67249 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 67250 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 67251 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 67252 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67253 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67254 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67255 | // GIR_Coverage, 2141, |
| 67256 | GIR_EraseRootFromParent_Done, |
| 67257 | // Label 3724: @214649 |
| 67258 | GIM_Try, /*On fail goto*//*Label 3725*/ GIMT_Encode4(214752), // Rule ID 2143 // |
| 67259 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24), |
| 67260 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 67261 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67262 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67264 | // (intrinsic_wo_chain:{ *:[i64] } 2881:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_MUL_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub0:{ *:[i32] }, (V_MUL_HI_U32_U24_e64:{ *:[i16] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1), sub1:{ *:[i32] }) |
| 67265 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 67266 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 67267 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64), |
| 67268 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 67269 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src0 |
| 67270 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, // src1 |
| 67271 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 67272 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64), |
| 67273 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 67274 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // src0 |
| 67275 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // src1 |
| 67276 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 67277 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 67278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 67279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 67280 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 67281 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 67282 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 67283 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 67284 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67285 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67286 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67287 | // GIR_Coverage, 2143, |
| 67288 | GIR_EraseRootFromParent_Done, |
| 67289 | // Label 3725: @214752 |
| 67290 | GIM_Try, /*On fail goto*//*Label 3726*/ GIMT_Encode4(214826), // Rule ID 725 // |
| 67291 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 67292 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67293 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67294 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67297 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 67298 | // (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 67299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64), |
| 67300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 67306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 67307 | GIR_RootConstrainSelectedInstOperands, |
| 67308 | // GIR_Coverage, 725, |
| 67309 | GIR_EraseRootFromParent_Done, |
| 67310 | // Label 3726: @214826 |
| 67311 | GIM_Try, /*On fail goto*//*Label 3727*/ GIMT_Encode4(214895), // Rule ID 759 // |
| 67312 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_i16), |
| 67313 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67314 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67315 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 67319 | // (intrinsic_wo_chain:{ *:[v2i16] } 1974:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_CVT_PKNORM_I16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 67320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_I16_F32_e64), |
| 67321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 67327 | GIR_RootConstrainSelectedInstOperands, |
| 67328 | // GIR_Coverage, 759, |
| 67329 | GIR_EraseRootFromParent_Done, |
| 67330 | // Label 3727: @214895 |
| 67331 | GIM_Try, /*On fail goto*//*Label 3728*/ GIMT_Encode4(214964), // Rule ID 761 // |
| 67332 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pknorm_u16), |
| 67333 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67334 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67335 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 67339 | // (intrinsic_wo_chain:{ *:[v2i16] } 1975:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_CVT_PKNORM_U16_F32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 67340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKNORM_U16_F32_e64), |
| 67341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 67347 | GIR_RootConstrainSelectedInstOperands, |
| 67348 | // GIR_Coverage, 761, |
| 67349 | GIR_EraseRootFromParent_Done, |
| 67350 | // Label 3728: @214964 |
| 67351 | GIM_Try, /*On fail goto*//*Label 3729*/ GIMT_Encode4(215038), // Rule ID 763 // |
| 67352 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pkrtz), |
| 67353 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67357 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67358 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 67359 | // (intrinsic_wo_chain:{ *:[v2f16] } 1976:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_CVT_PKRTZ_F16_F32_e64:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 67360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PKRTZ_F16_F32_e64), |
| 67361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 67367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 67368 | GIR_RootConstrainSelectedInstOperands, |
| 67369 | // GIR_Coverage, 763, |
| 67370 | GIR_EraseRootFromParent_Done, |
| 67371 | // Label 3729: @215038 |
| 67372 | GIM_Try, /*On fail goto*//*Label 3730*/ GIMT_Encode4(215112), // Rule ID 900 // |
| 67373 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_trig_preop), |
| 67374 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 67375 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 67376 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 67378 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67379 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 67380 | // (intrinsic_wo_chain:{ *:[f64] } 3090:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_TRIG_PREOP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 67381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_TRIG_PREOP_F64_e64), |
| 67382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 67388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 67389 | GIR_RootConstrainSelectedInstOperands, |
| 67390 | // GIR_Coverage, 900, |
| 67391 | GIR_EraseRootFromParent_Done, |
| 67392 | // Label 3730: @215112 |
| 67393 | GIM_Try, /*On fail goto*//*Label 3731*/ GIMT_Encode4(215186), // Rule ID 8053 // |
| 67394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 67395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67399 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 67400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 67401 | // (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 67402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64), |
| 67403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 67405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 67406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 67407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 67408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 67409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 67410 | GIR_RootConstrainSelectedInstOperands, |
| 67411 | // GIR_Coverage, 8053, |
| 67412 | GIR_EraseRootFromParent_Done, |
| 67413 | // Label 3731: @215186 |
| 67414 | GIM_Try, /*On fail goto*//*Label 3732*/ GIMT_Encode4(215235), // Rule ID 557 // |
| 67415 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67416 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67417 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67418 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67421 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67422 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64), |
| 67423 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67426 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67427 | GIR_RootConstrainSelectedInstOperands, |
| 67428 | // GIR_Coverage, 557, |
| 67429 | GIR_EraseRootFromParent_Done, |
| 67430 | // Label 3732: @215235 |
| 67431 | GIM_Try, /*On fail goto*//*Label 3733*/ GIMT_Encode4(215284), // Rule ID 559 // |
| 67432 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67433 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67434 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67435 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67438 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMPX_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F32_e64), |
| 67440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67443 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67444 | GIR_RootConstrainSelectedInstOperands, |
| 67445 | // GIR_Coverage, 559, |
| 67446 | GIR_EraseRootFromParent_Done, |
| 67447 | // Label 3733: @215284 |
| 67448 | GIM_Try, /*On fail goto*//*Label 3734*/ GIMT_Encode4(215333), // Rule ID 561 // |
| 67449 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67450 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67451 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 67452 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67454 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67455 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1) |
| 67456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64), |
| 67457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67460 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67461 | GIR_RootConstrainSelectedInstOperands, |
| 67462 | // GIR_Coverage, 561, |
| 67463 | GIR_EraseRootFromParent_Done, |
| 67464 | // Label 3734: @215333 |
| 67465 | GIM_Try, /*On fail goto*//*Label 3735*/ GIMT_Encode4(215382), // Rule ID 563 // |
| 67466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 67469 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67471 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67472 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMPX_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1) |
| 67473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F64_e64), |
| 67474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67477 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67478 | GIR_RootConstrainSelectedInstOperands, |
| 67479 | // GIR_Coverage, 563, |
| 67480 | GIR_EraseRootFromParent_Done, |
| 67481 | // Label 3735: @215382 |
| 67482 | GIM_Try, /*On fail goto*//*Label 3736*/ GIMT_Encode4(215434), // Rule ID 565 // |
| 67483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 67484 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67485 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67486 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 67487 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67490 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1) |
| 67491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64), |
| 67492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67495 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67496 | GIR_RootConstrainSelectedInstOperands, |
| 67497 | // GIR_Coverage, 565, |
| 67498 | GIR_EraseRootFromParent_Done, |
| 67499 | // Label 3736: @215434 |
| 67500 | GIM_Try, /*On fail goto*//*Label 3737*/ GIMT_Encode4(215486), // Rule ID 567 // |
| 67501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 67502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 67505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67507 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67508 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1) |
| 67509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64), |
| 67510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67513 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67514 | GIR_RootConstrainSelectedInstOperands, |
| 67515 | // GIR_Coverage, 567, |
| 67516 | GIR_EraseRootFromParent_Done, |
| 67517 | // Label 3737: @215486 |
| 67518 | GIM_Try, /*On fail goto*//*Label 3738*/ GIMT_Encode4(215538), // Rule ID 569 // |
| 67519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 67520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67521 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67522 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 67523 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67526 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMPX_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1) |
| 67527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F16_e64), |
| 67528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67531 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67532 | GIR_RootConstrainSelectedInstOperands, |
| 67533 | // GIR_Coverage, 569, |
| 67534 | GIR_EraseRootFromParent_Done, |
| 67535 | // Label 3738: @215538 |
| 67536 | GIM_Try, /*On fail goto*//*Label 3739*/ GIMT_Encode4(215590), // Rule ID 571 // |
| 67537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 67538 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_class), |
| 67539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 67540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 67541 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 67543 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 67544 | // (intrinsic_wo_chain:{ *:[i1] } 1958:{ *:[iPTR] }, (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src1) => (V_CMPX_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1) |
| 67545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMPX_CLASS_F16_t16_e64), |
| 67546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 67547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67549 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67550 | GIR_RootConstrainSelectedInstOperands, |
| 67551 | // GIR_Coverage, 571, |
| 67552 | GIR_EraseRootFromParent_Done, |
| 67553 | // Label 3739: @215590 |
| 67554 | GIM_Try, /*On fail goto*//*Label 3740*/ GIMT_Encode4(215627), // Rule ID 729 // |
| 67555 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_i24), |
| 67556 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67558 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67560 | // (intrinsic_wo_chain:{ *:[i32] } 2880:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MUL_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_I32_I24_e64), |
| 67562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67563 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67564 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67566 | GIR_RootConstrainSelectedInstOperands, |
| 67567 | // GIR_Coverage, 729, |
| 67568 | GIR_EraseRootFromParent_Done, |
| 67569 | // Label 3740: @215627 |
| 67570 | GIM_Try, /*On fail goto*//*Label 3741*/ GIMT_Encode4(215661), // Rule ID 731 // |
| 67571 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_i24), |
| 67572 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67573 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67574 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67576 | // (intrinsic_wo_chain:{ *:[i32] } 2882:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MUL_HI_I32_I24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_I24_e64), |
| 67578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67579 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67580 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67581 | GIR_RootConstrainSelectedInstOperands, |
| 67582 | // GIR_Coverage, 731, |
| 67583 | GIR_EraseRootFromParent_Done, |
| 67584 | // Label 3741: @215661 |
| 67585 | GIM_Try, /*On fail goto*//*Label 3742*/ GIMT_Encode4(215698), // Rule ID 733 // |
| 67586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mul_u24), |
| 67587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67589 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67591 | // (intrinsic_wo_chain:{ *:[i32] } 2881:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MUL_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_U32_U24_e64), |
| 67593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67594 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67595 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67597 | GIR_RootConstrainSelectedInstOperands, |
| 67598 | // GIR_Coverage, 733, |
| 67599 | GIR_EraseRootFromParent_Done, |
| 67600 | // Label 3742: @215698 |
| 67601 | GIM_Try, /*On fail goto*//*Label 3743*/ GIMT_Encode4(215732), // Rule ID 735 // |
| 67602 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mulhi_u24), |
| 67603 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67607 | // (intrinsic_wo_chain:{ *:[i32] } 2883:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MUL_HI_U32_U24_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_U24_e64), |
| 67609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67610 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67611 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67612 | GIR_RootConstrainSelectedInstOperands, |
| 67613 | // GIR_Coverage, 735, |
| 67614 | GIR_EraseRootFromParent_Done, |
| 67615 | // Label 3743: @215732 |
| 67616 | GIM_Try, /*On fail goto*//*Label 3744*/ GIMT_Encode4(215766), // Rule ID 755 // |
| 67617 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_lo), |
| 67618 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67620 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67622 | // (intrinsic_wo_chain:{ *:[i32] } 2835:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MBCNT_LO_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_LO_U32_B32_e64), |
| 67624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67625 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67626 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67627 | GIR_RootConstrainSelectedInstOperands, |
| 67628 | // GIR_Coverage, 755, |
| 67629 | GIR_EraseRootFromParent_Done, |
| 67630 | // Label 3744: @215766 |
| 67631 | GIM_Try, /*On fail goto*//*Label 3745*/ GIMT_Encode4(215800), // Rule ID 756 // |
| 67632 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mbcnt_hi), |
| 67633 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67634 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67635 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67637 | // (intrinsic_wo_chain:{ *:[i32] } 2834:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MBCNT_HI_U32_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MBCNT_HI_U32_B32_e64), |
| 67639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67640 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67641 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67642 | GIR_RootConstrainSelectedInstOperands, |
| 67643 | // GIR_Coverage, 756, |
| 67644 | GIR_EraseRootFromParent_Done, |
| 67645 | // Label 3745: @215800 |
| 67646 | GIM_Try, /*On fail goto*//*Label 3746*/ GIMT_Encode4(215834), // Rule ID 765 // |
| 67647 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u16), |
| 67648 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67650 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67651 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67652 | // (intrinsic_wo_chain:{ *:[v2i16] } 1972:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_CVT_PK_U16_U32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U16_U32_e64), |
| 67654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67655 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67656 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67657 | GIR_RootConstrainSelectedInstOperands, |
| 67658 | // GIR_Coverage, 765, |
| 67659 | GIR_EraseRootFromParent_Done, |
| 67660 | // Label 3746: @215834 |
| 67661 | GIM_Try, /*On fail goto*//*Label 3747*/ GIMT_Encode4(215868), // Rule ID 767 // |
| 67662 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_i16), |
| 67663 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 67664 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67665 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67667 | // (intrinsic_wo_chain:{ *:[v2i16] } 1971:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_CVT_PK_I16_I32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 67668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_I32_e64), |
| 67669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67670 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67671 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67672 | GIR_RootConstrainSelectedInstOperands, |
| 67673 | // GIR_Coverage, 767, |
| 67674 | GIR_EraseRootFromParent_Done, |
| 67675 | // Label 3747: @215868 |
| 67676 | GIM_Reject, |
| 67677 | // Label 3702: @215869 |
| 67678 | GIM_Try, /*On fail goto*//*Label 3748*/ GIMT_Encode4(218850), |
| 67679 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 67680 | GIM_Try, /*On fail goto*//*Label 3749*/ GIMT_Encode4(215967), // Rule ID 6617 // |
| 67681 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10), |
| 67682 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67683 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67684 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67685 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67688 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67690 | // (intrinsic_wo_chain:{ *:[f32] } 2809:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_INTERP_P10_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 67691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F32_inreg), |
| 67692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 67698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 67699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 67701 | GIR_RootConstrainSelectedInstOperands, |
| 67702 | // GIR_Coverage, 6617, |
| 67703 | GIR_EraseRootFromParent_Done, |
| 67704 | // Label 3749: @215967 |
| 67705 | GIM_Try, /*On fail goto*//*Label 3750*/ GIMT_Encode4(216057), // Rule ID 6618 // |
| 67706 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2), |
| 67707 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67708 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67709 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67710 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67713 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 67715 | // (intrinsic_wo_chain:{ *:[f32] } 2811:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_INTERP_P2_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 67716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32_inreg), |
| 67717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 67719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 67721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 67723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 67724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 67726 | GIR_RootConstrainSelectedInstOperands, |
| 67727 | // GIR_Coverage, 6618, |
| 67728 | GIR_EraseRootFromParent_Done, |
| 67729 | // Label 3750: @216057 |
| 67730 | GIM_Try, /*On fail goto*//*Label 3751*/ GIMT_Encode4(216144), // Rule ID 6690 // |
| 67731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts), |
| 67732 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz), |
| 67733 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67734 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67735 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67736 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67739 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67741 | // (intrinsic_wo_chain:{ *:[f32] } 2024:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2)) => (V_MAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 67742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F32_e64), |
| 67743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 67750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67752 | GIR_RootConstrainSelectedInstOperands, |
| 67753 | // GIR_Coverage, 6690, |
| 67754 | GIR_EraseRootFromParent_Done, |
| 67755 | // Label 3751: @216144 |
| 67756 | GIM_Try, /*On fail goto*//*Label 3752*/ GIMT_Encode4(216231), // Rule ID 6694 // |
| 67757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32), |
| 67758 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy), |
| 67759 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67760 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67761 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67762 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67767 | // (intrinsic_wo_chain:{ *:[f32] } 2023:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2)) => (V_FMAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 67768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_LEGACY_F32_e64), |
| 67769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 67776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67778 | GIR_RootConstrainSelectedInstOperands, |
| 67779 | // GIR_Coverage, 6694, |
| 67780 | GIR_EraseRootFromParent_Done, |
| 67781 | // Label 3752: @216231 |
| 67782 | GIM_Try, /*On fail goto*//*Label 3753*/ GIMT_Encode4(216318), // Rule ID 6696 // |
| 67783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 67784 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz), |
| 67785 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 67786 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 67787 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 67788 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 67789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 67793 | // (intrinsic_wo_chain:{ *:[f16] } 2024:{ *:[iPTR] }, (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src0), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src1), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src2)) => (V_MAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f16] }:$src1, 0:{ *:[i32] }, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 67794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F16_e64), |
| 67795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 67798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 67800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 67802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67804 | GIR_RootConstrainSelectedInstOperands, |
| 67805 | // GIR_Coverage, 6696, |
| 67806 | GIR_EraseRootFromParent_Done, |
| 67807 | // Label 3753: @216318 |
| 67808 | GIM_Try, /*On fail goto*//*Label 3754*/ GIMT_Encode4(216381), // Rule ID 2325 // |
| 67809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus), |
| 67810 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_bf8), |
| 67811 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67812 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67813 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67814 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 67817 | // (intrinsic_wo_chain:{ *:[f32] } 1986:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT4_F32_FP8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2) |
| 67818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_BF8), |
| 67819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67820 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67821 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 67823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 67824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67826 | GIR_RootConstrainSelectedInstOperands, |
| 67827 | // GIR_Coverage, 2325, |
| 67828 | GIR_EraseRootFromParent_Done, |
| 67829 | // Label 3754: @216381 |
| 67830 | GIM_Try, /*On fail goto*//*Label 3755*/ GIMT_Encode4(216444), // Rule ID 2326 // |
| 67831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus), |
| 67832 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_fp8), |
| 67833 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67836 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67838 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 67839 | // (intrinsic_wo_chain:{ *:[f32] } 1985:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT4_F32_BF8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2) |
| 67840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_FP8), |
| 67841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67842 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67843 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 67845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 67846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67848 | GIR_RootConstrainSelectedInstOperands, |
| 67849 | // GIR_Coverage, 2326, |
| 67850 | GIR_EraseRootFromParent_Done, |
| 67851 | // Label 3755: @216444 |
| 67852 | GIM_Try, /*On fail goto*//*Label 3756*/ GIMT_Encode4(216507), // Rule ID 2327 // |
| 67853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus), |
| 67854 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_fp8_fp8), |
| 67855 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67858 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 67861 | // (intrinsic_wo_chain:{ *:[f32] } 1987:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT4_F32_FP8_FP8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2) |
| 67862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_FP8_FP8), |
| 67863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67864 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67865 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 67867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 67868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67870 | GIR_RootConstrainSelectedInstOperands, |
| 67871 | // GIR_Coverage, 2327, |
| 67872 | GIR_EraseRootFromParent_Done, |
| 67873 | // Label 3756: @216507 |
| 67874 | GIM_Try, /*On fail goto*//*Label 3757*/ GIMT_Encode4(216570), // Rule ID 2328 // |
| 67875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot11Insts_isGFX12Plus), |
| 67876 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_dot4_f32_bf8_bf8), |
| 67877 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67878 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67879 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67880 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 67883 | // (intrinsic_wo_chain:{ *:[f32] } 1984:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT4_F32_BF8_BF8:{ *:[f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2) |
| 67884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_F32_BF8_BF8), |
| 67885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67886 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67887 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 67889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 67890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67892 | GIR_RootConstrainSelectedInstOperands, |
| 67893 | // GIR_Coverage, 2328, |
| 67894 | GIR_EraseRootFromParent_Done, |
| 67895 | // Label 3757: @216570 |
| 67896 | GIM_Try, /*On fail goto*//*Label 3758*/ GIMT_Encode4(216635), // Rule ID 6612 // |
| 67897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only), |
| 67898 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load), |
| 67899 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67900 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67902 | // MIs[0] attrchan |
| 67903 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 67904 | // MIs[0] attr |
| 67905 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 67906 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 67907 | // (intrinsic_wo_chain:{ *:[f32] } 2827:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (LDS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i8] }) |
| 67908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 67909 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 67910 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0 |
| 67911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_PARAM_LOAD), |
| 67912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67913 | GIR_RootToRootCopy, /*OpIdx*/3, // attr |
| 67914 | GIR_RootToRootCopy, /*OpIdx*/2, // attrchan |
| 67915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 67917 | GIR_RootConstrainSelectedInstOperands, |
| 67918 | // GIR_Coverage, 6612, |
| 67919 | GIR_EraseRootFromParent_Done, |
| 67920 | // Label 3758: @216635 |
| 67921 | GIM_Try, /*On fail goto*//*Label 3759*/ GIMT_Encode4(216703), // Rule ID 6614 // |
| 67922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 67923 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_param_load), |
| 67924 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67925 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67927 | // MIs[0] attrchan |
| 67928 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 67929 | // MIs[0] attr |
| 67930 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 67931 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 67932 | // (intrinsic_wo_chain:{ *:[f32] } 2827:{ *:[iPTR] }, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (DS_PARAM_LOAD:{ *:[f32] } (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, 0:{ *:[i8] }, 1:{ *:[i8] }) |
| 67933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 67934 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 67935 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // M0 |
| 67936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PARAM_LOAD), |
| 67937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67938 | GIR_RootToRootCopy, /*OpIdx*/3, // attr |
| 67939 | GIR_RootToRootCopy, /*OpIdx*/2, // attrchan |
| 67940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 67942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 67943 | GIR_RootConstrainSelectedInstOperands, |
| 67944 | // GIR_Coverage, 6614, |
| 67945 | GIR_EraseRootFromParent_Done, |
| 67946 | // Label 3759: @216703 |
| 67947 | GIM_Try, /*On fail goto*//*Label 3760*/ GIMT_Encode4(216745), // Rule ID 2292 // |
| 67948 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u8), |
| 67949 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67950 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67951 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67952 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67954 | // (intrinsic_wo_chain:{ *:[i32] } 3000:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_SAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) |
| 67955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U8_e64), |
| 67956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67957 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67958 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67959 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 67960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67961 | GIR_RootConstrainSelectedInstOperands, |
| 67962 | // GIR_Coverage, 2292, |
| 67963 | GIR_EraseRootFromParent_Done, |
| 67964 | // Label 3760: @216745 |
| 67965 | GIM_Try, /*On fail goto*//*Label 3761*/ GIMT_Encode4(216787), // Rule ID 2293 // |
| 67966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_hi_u8), |
| 67967 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67968 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67969 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67970 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67972 | // (intrinsic_wo_chain:{ *:[i32] } 2998:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_SAD_HI_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) |
| 67973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_HI_U8_e64), |
| 67974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67975 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67976 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67977 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 67978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67979 | GIR_RootConstrainSelectedInstOperands, |
| 67980 | // GIR_Coverage, 2293, |
| 67981 | GIR_EraseRootFromParent_Done, |
| 67982 | // Label 3761: @216787 |
| 67983 | GIM_Try, /*On fail goto*//*Label 3762*/ GIMT_Encode4(216829), // Rule ID 2294 // |
| 67984 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sad_u16), |
| 67985 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 67986 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 67987 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 67988 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 67989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 67990 | // (intrinsic_wo_chain:{ *:[i32] } 2999:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_SAD_U16_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) |
| 67991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SAD_U16_e64), |
| 67992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 67993 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 67994 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 67995 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 67996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 67997 | GIR_RootConstrainSelectedInstOperands, |
| 67998 | // GIR_Coverage, 2294, |
| 67999 | GIR_EraseRootFromParent_Done, |
| 68000 | // Label 3762: @216829 |
| 68001 | GIM_Try, /*On fail goto*//*Label 3763*/ GIMT_Encode4(216871), // Rule ID 2295 // |
| 68002 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_msad_u8), |
| 68003 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68006 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68008 | // (intrinsic_wo_chain:{ *:[i32] } 2879:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_MSAD_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) |
| 68009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MSAD_U8_e64), |
| 68010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68011 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68012 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68013 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68015 | GIR_RootConstrainSelectedInstOperands, |
| 68016 | // GIR_Coverage, 2295, |
| 68017 | GIR_EraseRootFromParent_Done, |
| 68018 | // Label 3763: @216871 |
| 68019 | GIM_Try, /*On fail goto*//*Label 3764*/ GIMT_Encode4(216913), // Rule ID 2296 // |
| 68020 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_pk_u16_u8), |
| 68021 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 68022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68023 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68024 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 68025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 68026 | // (intrinsic_wo_chain:{ *:[i64] } 2877:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2) => (V_MQSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] }) |
| 68027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_PK_U16_U8_e64), |
| 68028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68029 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68030 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68031 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68033 | GIR_RootConstrainSelectedInstOperands, |
| 68034 | // GIR_Coverage, 2296, |
| 68035 | GIR_EraseRootFromParent_Done, |
| 68036 | // Label 3764: @216913 |
| 68037 | GIM_Try, /*On fail goto*//*Label 3765*/ GIMT_Encode4(216955), // Rule ID 2297 // |
| 68038 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_qsad_pk_u16_u8), |
| 68039 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 68040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68041 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68042 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 68043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 68044 | // (intrinsic_wo_chain:{ *:[i64] } 2892:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2) => (V_QSAD_PK_U16_U8_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, i64:{ *:[i64] }:$src2, 0:{ *:[i1] }) |
| 68045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_QSAD_PK_U16_U8_e64), |
| 68046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68047 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68048 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68049 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68051 | GIR_RootConstrainSelectedInstOperands, |
| 68052 | // GIR_Coverage, 2297, |
| 68053 | GIR_EraseRootFromParent_Done, |
| 68054 | // Label 3765: @216955 |
| 68055 | GIM_Try, /*On fail goto*//*Label 3766*/ GIMT_Encode4(216997), // Rule ID 2298 // |
| 68056 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mqsad_u32_u8), |
| 68057 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 68058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68060 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 68061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 68062 | // (intrinsic_wo_chain:{ *:[v4i32] } 2878:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2) => (V_MQSAD_U32_U8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, 0:{ *:[i1] }) |
| 68063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MQSAD_U32_U8_e64), |
| 68064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68065 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68066 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68067 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68069 | GIR_RootConstrainSelectedInstOperands, |
| 68070 | // GIR_Coverage, 2298, |
| 68071 | GIR_EraseRootFromParent_Done, |
| 68072 | // Label 3766: @216997 |
| 68073 | GIM_Try, /*On fail goto*//*Label 3767*/ GIMT_Encode4(217094), // Rule ID 845 // |
| 68074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts), |
| 68075 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz), |
| 68076 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68077 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68078 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68079 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68082 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68084 | // (intrinsic_wo_chain:{ *:[f32] } 2024:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64), |
| 68086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68095 | GIR_RootConstrainSelectedInstOperands, |
| 68096 | // GIR_Coverage, 845, |
| 68097 | GIR_EraseRootFromParent_Done, |
| 68098 | // Label 3767: @217094 |
| 68099 | GIM_Try, /*On fail goto*//*Label 3768*/ GIMT_Encode4(217191), // Rule ID 847 // |
| 68100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32), |
| 68101 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy), |
| 68102 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68103 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68104 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68105 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68106 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68107 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68110 | // (intrinsic_wo_chain:{ *:[f32] } 2023:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64), |
| 68112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68121 | GIR_RootConstrainSelectedInstOperands, |
| 68122 | // GIR_Coverage, 847, |
| 68123 | GIR_EraseRootFromParent_Done, |
| 68124 | // Label 3768: @217191 |
| 68125 | GIM_Try, /*On fail goto*//*Label 3769*/ GIMT_Encode4(217285), // Rule ID 870 // |
| 68126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubeid), |
| 68127 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68129 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68130 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68132 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68133 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68134 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68135 | // (intrinsic_wo_chain:{ *:[f32] } 1961:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_CUBEID_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEID_F32_e64), |
| 68137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68146 | GIR_RootConstrainSelectedInstOperands, |
| 68147 | // GIR_Coverage, 870, |
| 68148 | GIR_EraseRootFromParent_Done, |
| 68149 | // Label 3769: @217285 |
| 68150 | GIM_Try, /*On fail goto*//*Label 3770*/ GIMT_Encode4(217379), // Rule ID 871 // |
| 68151 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubesc), |
| 68152 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68153 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68154 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68155 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68160 | // (intrinsic_wo_chain:{ *:[f32] } 1963:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_CUBESC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBESC_F32_e64), |
| 68162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68171 | GIR_RootConstrainSelectedInstOperands, |
| 68172 | // GIR_Coverage, 871, |
| 68173 | GIR_EraseRootFromParent_Done, |
| 68174 | // Label 3770: @217379 |
| 68175 | GIM_Try, /*On fail goto*//*Label 3771*/ GIMT_Encode4(217473), // Rule ID 872 // |
| 68176 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubetc), |
| 68177 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68178 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68179 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68180 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68185 | // (intrinsic_wo_chain:{ *:[f32] } 1964:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_CUBETC_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBETC_F32_e64), |
| 68187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68196 | GIR_RootConstrainSelectedInstOperands, |
| 68197 | // GIR_Coverage, 872, |
| 68198 | GIR_EraseRootFromParent_Done, |
| 68199 | // Label 3771: @217473 |
| 68200 | GIM_Try, /*On fail goto*//*Label 3772*/ GIMT_Encode4(217567), // Rule ID 873 // |
| 68201 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cubema), |
| 68202 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68203 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68204 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68205 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68208 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68210 | // (intrinsic_wo_chain:{ *:[f32] } 1962:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_CUBEMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CUBEMA_F32_e64), |
| 68212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68221 | GIR_RootConstrainSelectedInstOperands, |
| 68222 | // GIR_Coverage, 873, |
| 68223 | GIR_EraseRootFromParent_Done, |
| 68224 | // Label 3772: @217567 |
| 68225 | GIM_Try, /*On fail goto*//*Label 3773*/ GIMT_Encode4(217661), // Rule ID 889 // |
| 68226 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3), |
| 68227 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68228 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68229 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68230 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68232 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68235 | // (intrinsic_wo_chain:{ *:[f32] } 2025:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 68237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68246 | GIR_RootConstrainSelectedInstOperands, |
| 68247 | // GIR_Coverage, 889, |
| 68248 | GIR_EraseRootFromParent_Done, |
| 68249 | // Label 3773: @217661 |
| 68250 | GIM_Try, /*On fail goto*//*Label 3774*/ GIMT_Encode4(217750), // Rule ID 893 // |
| 68251 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_u8_f32), |
| 68252 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68253 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68254 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68255 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68259 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68260 | // (intrinsic_wo_chain:{ *:[i32] } 1973:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_CVT_PK_U8_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 68261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_U8_F32_e64), |
| 68262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68270 | GIR_RootConstrainSelectedInstOperands, |
| 68271 | // GIR_Coverage, 893, |
| 68272 | GIR_EraseRootFromParent_Done, |
| 68273 | // Label 3774: @217750 |
| 68274 | GIM_Try, /*On fail goto*//*Label 3775*/ GIMT_Encode4(217844), // Rule ID 894 // |
| 68275 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup), |
| 68276 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68277 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68278 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68279 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68281 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68284 | // (intrinsic_wo_chain:{ *:[f32] } 1981:{ *:[iPTR] }, (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DIV_FIXUP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68285 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F32_e64), |
| 68286 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68295 | GIR_RootConstrainSelectedInstOperands, |
| 68296 | // GIR_Coverage, 894, |
| 68297 | GIR_EraseRootFromParent_Done, |
| 68298 | // Label 3775: @217844 |
| 68299 | GIM_Try, /*On fail goto*//*Label 3776*/ GIMT_Encode4(217938), // Rule ID 896 // |
| 68300 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup), |
| 68301 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 68302 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68303 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 68304 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 68305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 68306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68308 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68309 | // (intrinsic_wo_chain:{ *:[f64] } 1981:{ *:[iPTR] }, (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DIV_FIXUP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F64_e64), |
| 68311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68320 | GIR_RootConstrainSelectedInstOperands, |
| 68321 | // GIR_Coverage, 896, |
| 68322 | GIR_EraseRootFromParent_Done, |
| 68323 | // Label 3776: @217938 |
| 68324 | GIM_Try, /*On fail goto*//*Label 3777*/ GIMT_Encode4(218035), // Rule ID 915 // |
| 68325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only), |
| 68326 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup), |
| 68327 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 68329 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 68330 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68333 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68335 | // (intrinsic_wo_chain:{ *:[f16] } 1981:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DIV_FIXUP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_e64), |
| 68337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68346 | GIR_RootConstrainSelectedInstOperands, |
| 68347 | // GIR_Coverage, 915, |
| 68348 | GIR_EraseRootFromParent_Done, |
| 68349 | // Label 3777: @218035 |
| 68350 | GIM_Try, /*On fail goto*//*Label 3778*/ GIMT_Encode4(218132), // Rule ID 924 // |
| 68351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 68352 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmad_ftz), |
| 68353 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68354 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 68355 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 68356 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68358 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68361 | // (intrinsic_wo_chain:{ *:[f16] } 2024:{ *:[iPTR] }, (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64), |
| 68363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 68371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 68372 | GIR_RootConstrainSelectedInstOperands, |
| 68373 | // GIR_Coverage, 924, |
| 68374 | GIR_EraseRootFromParent_Done, |
| 68375 | // Label 3778: @218132 |
| 68376 | GIM_Try, /*On fail goto*//*Label 3779*/ GIMT_Encode4(218229), // Rule ID 8088 // |
| 68377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaLegacy32), |
| 68378 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fma_legacy), |
| 68379 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68380 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68381 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68382 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 68385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68387 | // (intrinsic_wo_chain:{ *:[f32] } 2023:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 68388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_LEGACY_F32_e64), |
| 68389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 68391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 68392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 68393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 68394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 68397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 68398 | GIR_RootConstrainSelectedInstOperands, |
| 68399 | // GIR_Coverage, 8088, |
| 68400 | GIR_EraseRootFromParent_Done, |
| 68401 | // Label 3779: @218229 |
| 68402 | GIM_Try, /*On fail goto*//*Label 3780*/ GIMT_Encode4(218325), // Rule ID 919 // |
| 68403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 68404 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fixup), |
| 68405 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68406 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 68407 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 68408 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68409 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68410 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68412 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68413 | // (intrinsic_wo_chain:{ *:[f16] } 1981:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DIV_FIXUP_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 68414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FIXUP_F16_gfx9_e64), |
| 68415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68425 | GIR_RootConstrainSelectedInstOperands, |
| 68426 | // GIR_Coverage, 919, |
| 68427 | GIR_EraseRootFromParent_Done, |
| 68428 | // Label 3780: @218325 |
| 68429 | GIM_Try, /*On fail goto*//*Label 3781*/ GIMT_Encode4(218421), // Rule ID 928 // |
| 68430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 68431 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmed3), |
| 68432 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68433 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 68434 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 68435 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68438 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68440 | // (intrinsic_wo_chain:{ *:[f16] } 2025:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 68441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 68442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68452 | GIR_RootConstrainSelectedInstOperands, |
| 68453 | // GIR_Coverage, 928, |
| 68454 | GIR_EraseRootFromParent_Done, |
| 68455 | // Label 3781: @218421 |
| 68456 | GIM_Try, /*On fail goto*//*Label 3782*/ GIMT_Encode4(218511), // Rule ID 942 // |
| 68457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts), |
| 68458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f16_f16), |
| 68459 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68460 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 68461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 68462 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68464 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68467 | // (intrinsic_wo_chain:{ *:[f16] } 2015:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT2_F16_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 68468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F16_F16_e64), |
| 68469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68477 | GIR_RootConstrainSelectedInstOperands, |
| 68478 | // GIR_Coverage, 942, |
| 68479 | GIR_EraseRootFromParent_Done, |
| 68480 | // Label 3782: @218511 |
| 68481 | GIM_Try, /*On fail goto*//*Label 3783*/ GIMT_Encode4(218601), // Rule ID 943 // |
| 68482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts), |
| 68483 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_bf16_bf16), |
| 68484 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68485 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 68486 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 68487 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s16, |
| 68488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68489 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68490 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 68492 | // (intrinsic_wo_chain:{ *:[bf16] } 2014:{ *:[iPTR] }, (VOP3OpSelMods:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[bf16] } bf16:{ *:[bf16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_DOT2_BF16_BF16_e64:{ *:[bf16] } i32:{ *:[i32] }:$src0_modifiers, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2bf16:{ *:[v2bf16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, bf16:{ *:[bf16] }:$src2) |
| 68493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_BF16_BF16_e64), |
| 68494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68502 | GIR_RootConstrainSelectedInstOperands, |
| 68503 | // GIR_Coverage, 943, |
| 68504 | GIR_EraseRootFromParent_Done, |
| 68505 | // Label 3783: @218601 |
| 68506 | GIM_Try, /*On fail goto*//*Label 3784*/ GIMT_Encode4(218650), // Rule ID 850 // |
| 68507 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lerp), |
| 68508 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68509 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68510 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68511 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68513 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68514 | // (intrinsic_wo_chain:{ *:[i32] } 2828:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_LERP_U8_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 68515 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LERP_U8_e64), |
| 68516 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68518 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68519 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68520 | GIR_RootConstrainSelectedInstOperands, |
| 68521 | // GIR_Coverage, 850, |
| 68522 | GIR_EraseRootFromParent_Done, |
| 68523 | // Label 3784: @218650 |
| 68524 | GIM_Try, /*On fail goto*//*Label 3785*/ GIMT_Encode4(218699), // Rule ID 874 // |
| 68525 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ubfe), |
| 68526 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68527 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68528 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68529 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68532 | // (intrinsic_wo_chain:{ *:[i32] } 3091:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_BFE_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 68533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_U32_e64), |
| 68534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68536 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68537 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68538 | GIR_RootConstrainSelectedInstOperands, |
| 68539 | // GIR_Coverage, 874, |
| 68540 | GIR_EraseRootFromParent_Done, |
| 68541 | // Label 3785: @218699 |
| 68542 | GIM_Try, /*On fail goto*//*Label 3786*/ GIMT_Encode4(218748), // Rule ID 876 // |
| 68543 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sbfe), |
| 68544 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68545 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68546 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68547 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68550 | // (intrinsic_wo_chain:{ *:[i32] } 3001:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_BFE_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 68551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64), |
| 68552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68554 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68555 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68556 | GIR_RootConstrainSelectedInstOperands, |
| 68557 | // GIR_Coverage, 876, |
| 68558 | GIR_EraseRootFromParent_Done, |
| 68559 | // Label 3786: @218748 |
| 68560 | GIM_Try, /*On fail goto*//*Label 3787*/ GIMT_Encode4(218797), // Rule ID 880 // |
| 68561 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_alignbyte), |
| 68562 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68563 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68564 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68565 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68568 | // (intrinsic_wo_chain:{ *:[i32] } 1952:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_ALIGNBYTE_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 68569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBYTE_B32_e64), |
| 68570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68572 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68573 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68574 | GIR_RootConstrainSelectedInstOperands, |
| 68575 | // GIR_Coverage, 880, |
| 68576 | GIR_EraseRootFromParent_Done, |
| 68577 | // Label 3787: @218797 |
| 68578 | GIM_Try, /*On fail goto*//*Label 3788*/ GIMT_Encode4(218849), // Rule ID 913 // |
| 68579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 68580 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_perm), |
| 68581 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68582 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68583 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68584 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 68587 | // (intrinsic_wo_chain:{ *:[i32] } 2884:{ *:[iPTR] }, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_PERM_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 68588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 68589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68591 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68592 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68593 | GIR_RootConstrainSelectedInstOperands, |
| 68594 | // GIR_Coverage, 913, |
| 68595 | GIR_EraseRootFromParent_Done, |
| 68596 | // Label 3788: @218849 |
| 68597 | GIM_Reject, |
| 68598 | // Label 3748: @218850 |
| 68599 | GIM_Try, /*On fail goto*//*Label 3789*/ GIMT_Encode4(222446), |
| 68600 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 68601 | GIM_Try, /*On fail goto*//*Label 3790*/ GIMT_Encode4(218911), // Rule ID 2153 // |
| 68602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot5Insts), |
| 68603 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2), |
| 68604 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68605 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 68606 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 68607 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68609 | // MIs[0] Operand 5 |
| 68610 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68611 | // (intrinsic_wo_chain:{ *:[f32] } 2013:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, v2f16:{ *:[v2f16] }:$src1, f32:{ *:[f32] }:$src2, 0:{ *:[i1] }) => (V_DOT2C_F32_F16_e32:{ *:[f32] } ?:{ *:[v2f16] }:$src0, ?:{ *:[v2f16] }:$src1, ?:{ *:[f32] }:$src2) |
| 68612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_F32_F16_e32), |
| 68613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68614 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68615 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68616 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68617 | GIR_RootConstrainSelectedInstOperands, |
| 68618 | // GIR_Coverage, 2153, |
| 68619 | GIR_EraseRootFromParent_Done, |
| 68620 | // Label 3790: @218911 |
| 68621 | GIM_Try, /*On fail goto*//*Label 3791*/ GIMT_Encode4(218964), // Rule ID 2155 // |
| 68622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot6Insts), |
| 68623 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4), |
| 68624 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68625 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68626 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68627 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68629 | // MIs[0] Operand 5 |
| 68630 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68631 | // (intrinsic_wo_chain:{ *:[i32] } 3005:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) => (V_DOT4C_I32_I8_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2) |
| 68632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4C_I32_I8_e32), |
| 68633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68634 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68635 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68636 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68637 | GIR_RootConstrainSelectedInstOperands, |
| 68638 | // GIR_Coverage, 2155, |
| 68639 | GIR_EraseRootFromParent_Done, |
| 68640 | // Label 3791: @218964 |
| 68641 | GIM_Try, /*On fail goto*//*Label 3792*/ GIMT_Encode4(219017), // Rule ID 2156 // |
| 68642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot4Insts), |
| 68643 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2), |
| 68644 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68645 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 68646 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 68647 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68649 | // MIs[0] Operand 5 |
| 68650 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68651 | // (intrinsic_wo_chain:{ *:[i32] } 3004:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) => (V_DOT2C_I32_I16_e32:{ *:[i32] } ?:{ *:[v2i16] }:$src0, ?:{ *:[v2i16] }:$src1, ?:{ *:[i32] }:$src2) |
| 68652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2C_I32_I16_e32), |
| 68653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68654 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68655 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68656 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68657 | GIR_RootConstrainSelectedInstOperands, |
| 68658 | // GIR_Coverage, 2156, |
| 68659 | GIR_EraseRootFromParent_Done, |
| 68660 | // Label 3792: @219017 |
| 68661 | GIM_Try, /*On fail goto*//*Label 3793*/ GIMT_Encode4(219070), // Rule ID 2157 // |
| 68662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot3Insts), |
| 68663 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8), |
| 68664 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68665 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68666 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68667 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68669 | // MIs[0] Operand 5 |
| 68670 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68671 | // (intrinsic_wo_chain:{ *:[i32] } 3006:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, 0:{ *:[i1] }) => (V_DOT8C_I32_I4_e32:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src2) |
| 68672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8C_I32_I4_e32), |
| 68673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68674 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 68675 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 68676 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 68677 | GIR_RootConstrainSelectedInstOperands, |
| 68678 | // GIR_Coverage, 2157, |
| 68679 | GIR_EraseRootFromParent_Done, |
| 68680 | // Label 3793: @219070 |
| 68681 | GIM_Try, /*On fail goto*//*Label 3794*/ GIMT_Encode4(219174), // Rule ID 6615 // |
| 68682 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16), |
| 68683 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68685 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68686 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68688 | // MIs[0] Operand 5 |
| 68689 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68690 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68693 | // (intrinsic_wo_chain:{ *:[f32] } 2810:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_INTERP_P10_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg), |
| 68695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68705 | GIR_RootConstrainSelectedInstOperands, |
| 68706 | // GIR_Coverage, 6615, |
| 68707 | GIR_EraseRootFromParent_Done, |
| 68708 | // Label 3794: @219174 |
| 68709 | GIM_Try, /*On fail goto*//*Label 3795*/ GIMT_Encode4(219278), // Rule ID 6616 // |
| 68710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p10_f16), |
| 68711 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68712 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68713 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68714 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68716 | // MIs[0] Operand 5 |
| 68717 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 68718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68719 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68721 | // (intrinsic_wo_chain:{ *:[f32] } 2810:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] }) => (V_INTERP_P10_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_F16_F32_inreg), |
| 68723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68733 | GIR_RootConstrainSelectedInstOperands, |
| 68734 | // GIR_Coverage, 6616, |
| 68735 | GIR_EraseRootFromParent_Done, |
| 68736 | // Label 3795: @219278 |
| 68737 | GIM_Try, /*On fail goto*//*Label 3796*/ GIMT_Encode4(219382), // Rule ID 6619 // |
| 68738 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16), |
| 68739 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68740 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68741 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68742 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68744 | // MIs[0] Operand 5 |
| 68745 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68746 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68749 | // (intrinsic_wo_chain:{ *:[f16] } 2812:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_INTERP_P2_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg), |
| 68751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68761 | GIR_RootConstrainSelectedInstOperands, |
| 68762 | // GIR_Coverage, 6619, |
| 68763 | GIR_EraseRootFromParent_Done, |
| 68764 | // Label 3796: @219382 |
| 68765 | GIM_Try, /*On fail goto*//*Label 3797*/ GIMT_Encode4(219486), // Rule ID 6620 // |
| 68766 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_inreg_p2_f16), |
| 68767 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68768 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68769 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68770 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68772 | // MIs[0] Operand 5 |
| 68773 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 68774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68777 | // (intrinsic_wo_chain:{ *:[f16] } 2812:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] }) => (V_INTERP_P2_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16_F32_inreg), |
| 68779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68789 | GIR_RootConstrainSelectedInstOperands, |
| 68790 | // GIR_Coverage, 6620, |
| 68791 | GIR_EraseRootFromParent_Done, |
| 68792 | // Label 3797: @219486 |
| 68793 | GIM_Try, /*On fail goto*//*Label 3798*/ GIMT_Encode4(219590), // Rule ID 6621 // |
| 68794 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16), |
| 68795 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68796 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68797 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68798 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68800 | // MIs[0] Operand 5 |
| 68801 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68803 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68804 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68805 | // (intrinsic_wo_chain:{ *:[f32] } 2816:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_INTERP_P10_RTZ_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg), |
| 68807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68817 | GIR_RootConstrainSelectedInstOperands, |
| 68818 | // GIR_Coverage, 6621, |
| 68819 | GIR_EraseRootFromParent_Done, |
| 68820 | // Label 3798: @219590 |
| 68821 | GIM_Try, /*On fail goto*//*Label 3799*/ GIMT_Encode4(219694), // Rule ID 6622 // |
| 68822 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p10_rtz_f16), |
| 68823 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68824 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68825 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68826 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68828 | // MIs[0] Operand 5 |
| 68829 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 68830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68833 | // (intrinsic_wo_chain:{ *:[f32] } 2816:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] }) => (V_INTERP_P10_RTZ_F16_F32_inreg:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P10_RTZ_F16_F32_inreg), |
| 68835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68845 | GIR_RootConstrainSelectedInstOperands, |
| 68846 | // GIR_Coverage, 6622, |
| 68847 | GIR_EraseRootFromParent_Done, |
| 68848 | // Label 3799: @219694 |
| 68849 | GIM_Try, /*On fail goto*//*Label 3800*/ GIMT_Encode4(219798), // Rule ID 6623 // |
| 68850 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16), |
| 68851 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68852 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68853 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68854 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68856 | // MIs[0] Operand 5 |
| 68857 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 68858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68861 | // (intrinsic_wo_chain:{ *:[f16] } 2819:{ *:[iPTR] }, (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_INTERP_P2_RTZ_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg), |
| 68863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68873 | GIR_RootConstrainSelectedInstOperands, |
| 68874 | // GIR_Coverage, 6623, |
| 68875 | GIR_EraseRootFromParent_Done, |
| 68876 | // Label 3800: @219798 |
| 68877 | GIM_Try, /*On fail goto*//*Label 3801*/ GIMT_Encode4(219902), // Rule ID 6624 // |
| 68878 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_rtz_f16), |
| 68879 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 68880 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68881 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68882 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68883 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68884 | // MIs[0] Operand 5 |
| 68885 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 68886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vinterpmods_hi), |
| 68887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68888 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vinterpmods), |
| 68889 | // (intrinsic_wo_chain:{ *:[f16] } 2819:{ *:[iPTR] }, (VINTERPModsHi:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VINTERPMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), -1:{ *:[i1] }) => (V_INTERP_P2_RTZ_F16_F32_inreg:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 7:{ *:[i8] }) |
| 68890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_RTZ_F16_F32_inreg), |
| 68891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/7, |
| 68901 | GIR_RootConstrainSelectedInstOperands, |
| 68902 | // GIR_Coverage, 6624, |
| 68903 | GIR_EraseRootFromParent_Done, |
| 68904 | // Label 3801: @219902 |
| 68905 | GIM_Try, /*On fail goto*//*Label 3802*/ GIMT_Encode4(220016), // Rule ID 2272 // |
| 68906 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 68907 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas), |
| 68908 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68909 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68910 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68911 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68912 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1, |
| 68913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68914 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 68915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 68916 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68918 | // (intrinsic_wo_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] }) => (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2) |
| 68919 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68920 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68921 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC |
| 68922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64), |
| 68923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68932 | GIR_RootConstrainSelectedInstOperands, |
| 68933 | // GIR_Coverage, 2272, |
| 68934 | GIR_EraseRootFromParent_Done, |
| 68935 | // Label 3802: @220016 |
| 68936 | GIM_Try, /*On fail goto*//*Label 3803*/ GIMT_Encode4(220130), // Rule ID 2274 // |
| 68937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 68938 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas), |
| 68939 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 68940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 68941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 68942 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 68943 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1, |
| 68944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 68945 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 68946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 68947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68949 | // (intrinsic_wo_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC:{ *:[i1] }) => (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2) |
| 68950 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68951 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68952 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC |
| 68953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64), |
| 68954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68963 | GIR_RootConstrainSelectedInstOperands, |
| 68964 | // GIR_Coverage, 2274, |
| 68965 | GIR_EraseRootFromParent_Done, |
| 68966 | // Label 3803: @220130 |
| 68967 | GIM_Try, /*On fail goto*//*Label 3804*/ GIMT_Encode4(220244), // Rule ID 2276 // |
| 68968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 68969 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas), |
| 68970 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 68971 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 68972 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 68973 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 68974 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1, |
| 68975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 68976 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 68977 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 68978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 68979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 68980 | // (intrinsic_wo_chain:{ *:[f32] } 1982:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] }) => (V_DIV_FMAS_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f32] }:$src2) |
| 68981 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 68982 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 68983 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO |
| 68984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F32_e64), |
| 68985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 68986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 68987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 68988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 68989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 68990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 68991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 68992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 68994 | GIR_RootConstrainSelectedInstOperands, |
| 68995 | // GIR_Coverage, 2276, |
| 68996 | GIR_EraseRootFromParent_Done, |
| 68997 | // Label 3804: @220244 |
| 68998 | GIM_Try, /*On fail goto*//*Label 3805*/ GIMT_Encode4(220358), // Rule ID 2278 // |
| 68999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 69000 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_div_fmas), |
| 69001 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 69002 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 69003 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 69004 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 69005 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s1, |
| 69006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 69007 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 69008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 69009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 69010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 69011 | // (intrinsic_wo_chain:{ *:[f64] } 1982:{ *:[iPTR] }, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers), VCC_LO:{ *:[i1] }) => (V_DIV_FMAS_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f64] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f64] }:$src2) |
| 69012 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69013 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::VCC_LO), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69014 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // VCC_LO |
| 69015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DIV_FMAS_F64_e64), |
| 69016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69025 | GIR_RootConstrainSelectedInstOperands, |
| 69026 | // GIR_Coverage, 2278, |
| 69027 | GIR_EraseRootFromParent_Done, |
| 69028 | // Label 3805: @220358 |
| 69029 | GIM_Try, /*On fail goto*//*Label 3806*/ GIMT_Encode4(220439), // Rule ID 2218 // |
| 69030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 69031 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32), |
| 69032 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69034 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69035 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69037 | // MIs[0] byte_sel |
| 69038 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 69040 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 69041 | // (intrinsic_wo_chain:{ *:[i32] } 1978:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel) => (V_CVT_SR_FP8_F32_gfx12_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i8] } ?:{ *:[i32] }:$byte_sel)) |
| 69042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_gfx12_e64), |
| 69043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69048 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69049 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel |
| 69050 | GIR_RootConstrainSelectedInstOperands, |
| 69051 | // GIR_Coverage, 2218, |
| 69052 | GIR_EraseRootFromParent_Done, |
| 69053 | // Label 3806: @220439 |
| 69054 | GIM_Try, /*On fail goto*//*Label 3807*/ GIMT_Encode4(220520), // Rule ID 2219 // |
| 69055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX12Plus), |
| 69056 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32), |
| 69057 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69060 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69062 | // MIs[0] byte_sel |
| 69063 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 69065 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 69066 | // (intrinsic_wo_chain:{ *:[i32] } 1977:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$old, (timm:{ *:[i32] }):$byte_sel) => (V_CVT_SR_BF8_F32_gfx12_e64:{ *:[i32] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$old, (as_i32timm:{ *:[i8] } ?:{ *:[i32] }:$byte_sel)) |
| 69067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_gfx12_e64), |
| 69068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69073 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69074 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // byte_sel |
| 69075 | GIR_RootConstrainSelectedInstOperands, |
| 69076 | // GIR_Coverage, 2219, |
| 69077 | GIR_EraseRootFromParent_Done, |
| 69078 | // Label 3807: @220520 |
| 69079 | GIM_Try, /*On fail goto*//*Label 3808*/ GIMT_Encode4(220583), // Rule ID 1104 // |
| 69080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus), |
| 69081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_mov), |
| 69082 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69083 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 69084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69085 | // MIs[0] vsrc |
| 69086 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 69087 | // MIs[0] attrchan |
| 69088 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 69089 | // MIs[0] attr |
| 69090 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69091 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69092 | // (intrinsic_wo_chain:{ *:[f32] } 2813:{ *:[iPTR] }, (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (V_INTERP_MOV_F32:{ *:[f32] } (timm:{ *:[i32] }):$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan) |
| 69093 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69094 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69095 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0 |
| 69096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_MOV_F32), |
| 69097 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69098 | GIR_RootToRootCopy, /*OpIdx*/2, // vsrc |
| 69099 | GIR_RootToRootCopy, /*OpIdx*/4, // attr |
| 69100 | GIR_RootToRootCopy, /*OpIdx*/3, // attrchan |
| 69101 | GIR_RootConstrainSelectedInstOperands, |
| 69102 | // GIR_Coverage, 1104, |
| 69103 | GIR_EraseRootFromParent_Done, |
| 69104 | // Label 3808: @220583 |
| 69105 | GIM_Try, /*On fail goto*//*Label 3809*/ GIMT_Encode4(220646), // Rule ID 1101 // |
| 69106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_has32BankLDS_isNotGFX90APlus), |
| 69107 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1), |
| 69108 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69109 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69110 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 69111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69112 | // MIs[0] attrchan |
| 69113 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 69114 | // MIs[0] attr |
| 69115 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69116 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69117 | // (intrinsic_wo_chain:{ *:[f32] } 2814:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (V_INTERP_P1_F32:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan) |
| 69118 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69119 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69120 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0 |
| 69121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32), |
| 69122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69123 | GIR_RootToRootCopy, /*OpIdx*/2, // vsrc |
| 69124 | GIR_RootToRootCopy, /*OpIdx*/4, // attr |
| 69125 | GIR_RootToRootCopy, /*OpIdx*/3, // attrchan |
| 69126 | GIR_RootConstrainSelectedInstOperands, |
| 69127 | // GIR_Coverage, 1101, |
| 69128 | GIR_EraseRootFromParent_Done, |
| 69129 | // Label 3809: @220646 |
| 69130 | GIM_Try, /*On fail goto*//*Label 3810*/ GIMT_Encode4(220709), // Rule ID 1102 // |
| 69131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_has16BankLDS_isNotGFX90APlus), |
| 69132 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1), |
| 69133 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69135 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 69136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69137 | // MIs[0] attrchan |
| 69138 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 69139 | // MIs[0] attr |
| 69140 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69141 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69142 | // (intrinsic_wo_chain:{ *:[f32] } 2814:{ *:[iPTR] }, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (V_INTERP_P1_F32_16bank:{ *:[f32] } f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan) |
| 69143 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69144 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69145 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // M0 |
| 69146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1_F32_16bank), |
| 69147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69148 | GIR_RootToRootCopy, /*OpIdx*/2, // vsrc |
| 69149 | GIR_RootToRootCopy, /*OpIdx*/4, // attr |
| 69150 | GIR_RootToRootCopy, /*OpIdx*/3, // attrchan |
| 69151 | GIR_RootConstrainSelectedInstOperands, |
| 69152 | // GIR_Coverage, 1102, |
| 69153 | GIR_EraseRootFromParent_Done, |
| 69154 | // Label 3810: @220709 |
| 69155 | GIM_Try, /*On fail goto*//*Label 3811*/ GIMT_Encode4(220771), // Rule ID 2206 // |
| 69156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX9Plus), |
| 69157 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32), |
| 69158 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69159 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69160 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69161 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69163 | // MIs[0] Operand 5 |
| 69164 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 69165 | // (intrinsic_wo_chain:{ *:[i32] } 1970:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] }) => (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64), |
| 69167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69169 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69171 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69172 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69174 | GIR_RootConstrainSelectedInstOperands, |
| 69175 | // GIR_Coverage, 2206, |
| 69176 | GIR_EraseRootFromParent_Done, |
| 69177 | // Label 3811: @220771 |
| 69178 | GIM_Try, /*On fail goto*//*Label 3812*/ GIMT_Encode4(220833), // Rule ID 2207 // |
| 69179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX9Plus), |
| 69180 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32), |
| 69181 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69182 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69183 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69184 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69185 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69186 | // MIs[0] Operand 5 |
| 69187 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 69188 | // (intrinsic_wo_chain:{ *:[i32] } 1967:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i1] }) => (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64), |
| 69190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69192 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69194 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69195 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69197 | GIR_RootConstrainSelectedInstOperands, |
| 69198 | // GIR_Coverage, 2207, |
| 69199 | GIR_EraseRootFromParent_Done, |
| 69200 | // Label 3812: @220833 |
| 69201 | GIM_Try, /*On fail goto*//*Label 3813*/ GIMT_Encode4(220895), // Rule ID 2208 // |
| 69202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX9Plus), |
| 69203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_fp8_f32), |
| 69204 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69206 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69207 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69209 | // MIs[0] Operand 5 |
| 69210 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 69211 | // (intrinsic_wo_chain:{ *:[i32] } 1970:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] }) => (V_CVT_PK_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_FP8_F32_e64), |
| 69213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69215 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69217 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69218 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69220 | GIR_RootConstrainSelectedInstOperands, |
| 69221 | // GIR_Coverage, 2208, |
| 69222 | GIR_EraseRootFromParent_Done, |
| 69223 | // Label 3813: @220895 |
| 69224 | GIM_Try, /*On fail goto*//*Label 3814*/ GIMT_Encode4(220957), // Rule ID 2209 // |
| 69225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX9Plus), |
| 69226 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_pk_bf8_f32), |
| 69227 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69228 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69229 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69230 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69232 | // MIs[0] Operand 5 |
| 69233 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 69234 | // (intrinsic_wo_chain:{ *:[i32] } 1967:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$old, -1:{ *:[i1] }) => (V_CVT_PK_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_BF8_F32_e64), |
| 69236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69238 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69240 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69241 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69243 | GIR_RootConstrainSelectedInstOperands, |
| 69244 | // GIR_Coverage, 2209, |
| 69245 | GIR_EraseRootFromParent_Done, |
| 69246 | // Label 3814: @220957 |
| 69247 | GIM_Try, /*On fail goto*//*Label 3815*/ GIMT_Encode4(221022), // Rule ID 2210 // |
| 69248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69249 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32), |
| 69250 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69251 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69252 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69253 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69255 | // MIs[0] Operand 5 |
| 69256 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 69257 | // (intrinsic_wo_chain:{ *:[i32] } 1978:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] }) => (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64), |
| 69259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69261 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69263 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69265 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69267 | GIR_RootConstrainSelectedInstOperands, |
| 69268 | // GIR_Coverage, 2210, |
| 69269 | GIR_EraseRootFromParent_Done, |
| 69270 | // Label 3815: @221022 |
| 69271 | GIM_Try, /*On fail goto*//*Label 3816*/ GIMT_Encode4(221087), // Rule ID 2211 // |
| 69272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69273 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32), |
| 69274 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69275 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69276 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69277 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69278 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69279 | // MIs[0] Operand 5 |
| 69280 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 69281 | // (intrinsic_wo_chain:{ *:[i32] } 1977:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 0:{ *:[i32] }) => (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64), |
| 69283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69285 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69287 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69289 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69291 | GIR_RootConstrainSelectedInstOperands, |
| 69292 | // GIR_Coverage, 2211, |
| 69293 | GIR_EraseRootFromParent_Done, |
| 69294 | // Label 3816: @221087 |
| 69295 | GIM_Try, /*On fail goto*//*Label 3817*/ GIMT_Encode4(221152), // Rule ID 2212 // |
| 69296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69297 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32), |
| 69298 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69299 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69300 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69301 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69303 | // MIs[0] Operand 5 |
| 69304 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1), |
| 69305 | // (intrinsic_wo_chain:{ *:[i32] } 1978:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] }) => (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64), |
| 69307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69309 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69311 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69313 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69315 | GIR_RootConstrainSelectedInstOperands, |
| 69316 | // GIR_Coverage, 2212, |
| 69317 | GIR_EraseRootFromParent_Done, |
| 69318 | // Label 3817: @221152 |
| 69319 | GIM_Try, /*On fail goto*//*Label 3818*/ GIMT_Encode4(221217), // Rule ID 2213 // |
| 69320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69321 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32), |
| 69322 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69323 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69324 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69325 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69327 | // MIs[0] Operand 5 |
| 69328 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(1), |
| 69329 | // (intrinsic_wo_chain:{ *:[i32] } 1977:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 1:{ *:[i32] }) => (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64), |
| 69331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69333 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69335 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69337 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69339 | GIR_RootConstrainSelectedInstOperands, |
| 69340 | // GIR_Coverage, 2213, |
| 69341 | GIR_EraseRootFromParent_Done, |
| 69342 | // Label 3818: @221217 |
| 69343 | GIM_Try, /*On fail goto*//*Label 3819*/ GIMT_Encode4(221282), // Rule ID 2214 // |
| 69344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69345 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32), |
| 69346 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69347 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69348 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69349 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69351 | // MIs[0] Operand 5 |
| 69352 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2), |
| 69353 | // (intrinsic_wo_chain:{ *:[i32] } 1978:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] }) => (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64), |
| 69355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69357 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69359 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69361 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69363 | GIR_RootConstrainSelectedInstOperands, |
| 69364 | // GIR_Coverage, 2214, |
| 69365 | GIR_EraseRootFromParent_Done, |
| 69366 | // Label 3819: @221282 |
| 69367 | GIM_Try, /*On fail goto*//*Label 3820*/ GIMT_Encode4(221347), // Rule ID 2215 // |
| 69368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69369 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32), |
| 69370 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69371 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69372 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69373 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69375 | // MIs[0] Operand 5 |
| 69376 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(2), |
| 69377 | // (intrinsic_wo_chain:{ *:[i32] } 1977:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 2:{ *:[i32] }) => (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 0:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64), |
| 69379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69381 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69383 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69385 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69387 | GIR_RootConstrainSelectedInstOperands, |
| 69388 | // GIR_Coverage, 2215, |
| 69389 | GIR_EraseRootFromParent_Done, |
| 69390 | // Label 3820: @221347 |
| 69391 | GIM_Try, /*On fail goto*//*Label 3821*/ GIMT_Encode4(221412), // Rule ID 2216 // |
| 69392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69393 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_fp8_f32), |
| 69394 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69396 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69397 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69399 | // MIs[0] Operand 5 |
| 69400 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3), |
| 69401 | // (intrinsic_wo_chain:{ *:[i32] } 1978:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] }) => (V_CVT_SR_FP8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_FP8_F32_e64), |
| 69403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69405 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69407 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69409 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69411 | GIR_RootConstrainSelectedInstOperands, |
| 69412 | // GIR_Coverage, 2216, |
| 69413 | GIR_EraseRootFromParent_Done, |
| 69414 | // Label 3821: @221412 |
| 69415 | GIM_Try, /*On fail goto*//*Label 3822*/ GIMT_Encode4(221477), // Rule ID 2217 // |
| 69416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFP8ConversionInsts_isGFX940Plus), |
| 69417 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_cvt_sr_bf8_f32), |
| 69418 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69419 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69420 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69421 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69423 | // MIs[0] Operand 5 |
| 69424 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(3), |
| 69425 | // (intrinsic_wo_chain:{ *:[i32] } 1977:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$old, 3:{ *:[i32] }) => (V_CVT_SR_BF8_F32_e64:{ *:[i32] } 8:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[i32] }:$src1, 4:{ *:[i32] }, ?:{ *:[i32] }:$old, 0:{ *:[i32] }) |
| 69426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_SR_BF8_F32_e64), |
| 69427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69429 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69431 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/4, |
| 69433 | GIR_RootToRootCopy, /*OpIdx*/4, // old |
| 69434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69435 | GIR_RootConstrainSelectedInstOperands, |
| 69436 | // GIR_Coverage, 2217, |
| 69437 | GIR_EraseRootFromParent_Done, |
| 69438 | // Label 3822: @221477 |
| 69439 | GIM_Try, /*On fail goto*//*Label 3823*/ GIMT_Encode4(221545), // Rule ID 2323 // |
| 69440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts), |
| 69441 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8), |
| 69442 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69443 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69444 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69445 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69447 | // MIs[0] clamp |
| 69448 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69449 | // (intrinsic_wo_chain:{ *:[i32] } 3006:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_DOT8_I32_IU4:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 69450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4), |
| 69451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/9, |
| 69453 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/9, |
| 69455 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69457 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 69458 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69463 | GIR_RootConstrainSelectedInstOperands, |
| 69464 | // GIR_Coverage, 2323, |
| 69465 | GIR_EraseRootFromParent_Done, |
| 69466 | // Label 3823: @221545 |
| 69467 | GIM_Try, /*On fail goto*//*Label 3824*/ GIMT_Encode4(221613), // Rule ID 2324 // |
| 69468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts), |
| 69469 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4), |
| 69470 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69471 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69472 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69473 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69475 | // MIs[0] clamp |
| 69476 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69477 | // (intrinsic_wo_chain:{ *:[i32] } 3005:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_DOT4_I32_IU8:{ *:[i32] } 9:{ *:[i32] }, i32:{ *:[i32] }:$src0, 9:{ *:[i32] }, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 69478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8), |
| 69479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/9, |
| 69481 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/9, |
| 69483 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 69484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69485 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 69486 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69489 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69491 | GIR_RootConstrainSelectedInstOperands, |
| 69492 | // GIR_Coverage, 2324, |
| 69493 | GIR_EraseRootFromParent_Done, |
| 69494 | // Label 3824: @221613 |
| 69495 | GIM_Try, /*On fail goto*//*Label 3825*/ GIMT_Encode4(221717), // Rule ID 980 // |
| 69496 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts), |
| 69497 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot2), |
| 69498 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69499 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 69500 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 69501 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69503 | // MIs[0] clamp |
| 69504 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69505 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69507 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69508 | // (intrinsic_wo_chain:{ *:[i32] } 3004:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT2_I32_I16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_I32_I16), |
| 69510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69517 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69522 | GIR_RootConstrainSelectedInstOperands, |
| 69523 | // GIR_Coverage, 980, |
| 69524 | GIR_EraseRootFromParent_Done, |
| 69525 | // Label 3825: @221717 |
| 69526 | GIM_Try, /*On fail goto*//*Label 3826*/ GIMT_Encode4(221821), // Rule ID 981 // |
| 69527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot2Insts), |
| 69528 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot2), |
| 69529 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 69531 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 69532 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69534 | // MIs[0] clamp |
| 69535 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69536 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69537 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69539 | // (intrinsic_wo_chain:{ *:[i32] } 3092:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT2_U32_U16:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_U32_U16), |
| 69541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69548 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69553 | GIR_RootConstrainSelectedInstOperands, |
| 69554 | // GIR_Coverage, 981, |
| 69555 | GIR_EraseRootFromParent_Done, |
| 69556 | // Label 3826: @221821 |
| 69557 | GIM_Try, /*On fail goto*//*Label 3827*/ GIMT_Encode4(221925), // Rule ID 982 // |
| 69558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot10Insts), |
| 69559 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2), |
| 69560 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69561 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 69562 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 69563 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69565 | // MIs[0] clamp |
| 69566 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69568 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69569 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69570 | // (intrinsic_wo_chain:{ *:[f32] } 2013:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT2_F32_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F32_F16), |
| 69572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69579 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69584 | GIR_RootConstrainSelectedInstOperands, |
| 69585 | // GIR_Coverage, 982, |
| 69586 | GIR_EraseRootFromParent_Done, |
| 69587 | // Label 3827: @221925 |
| 69588 | GIM_Try, /*On fail goto*//*Label 3828*/ GIMT_Encode4(222029), // Rule ID 984 // |
| 69589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts), |
| 69590 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot4), |
| 69591 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69592 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69593 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69594 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69596 | // MIs[0] clamp |
| 69597 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69600 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69601 | // (intrinsic_wo_chain:{ *:[i32] } 3093:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT4_U32_U8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69602 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_U32_U8), |
| 69603 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69610 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69611 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69615 | GIR_RootConstrainSelectedInstOperands, |
| 69616 | // GIR_Coverage, 984, |
| 69617 | GIR_EraseRootFromParent_Done, |
| 69618 | // Label 3828: @222029 |
| 69619 | GIM_Try, /*On fail goto*//*Label 3829*/ GIMT_Encode4(222133), // Rule ID 985 // |
| 69620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot7Insts), |
| 69621 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_udot8), |
| 69622 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69623 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69624 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69625 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69627 | // MIs[0] clamp |
| 69628 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69629 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69632 | // (intrinsic_wo_chain:{ *:[i32] } 3094:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT8_U32_U4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_U32_U4), |
| 69634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69641 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69646 | GIR_RootConstrainSelectedInstOperands, |
| 69647 | // GIR_Coverage, 985, |
| 69648 | GIR_EraseRootFromParent_Done, |
| 69649 | // Label 3829: @222133 |
| 69650 | GIM_Try, /*On fail goto*//*Label 3830*/ GIMT_Encode4(222237), // Rule ID 986 // |
| 69651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts), |
| 69652 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot4), |
| 69653 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69654 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69655 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69656 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69658 | // MIs[0] clamp |
| 69659 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69662 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69663 | // (intrinsic_wo_chain:{ *:[i32] } 3005:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT4_I32_I8:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_I8), |
| 69665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69672 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69677 | GIR_RootConstrainSelectedInstOperands, |
| 69678 | // GIR_Coverage, 986, |
| 69679 | GIR_EraseRootFromParent_Done, |
| 69680 | // Label 3830: @222237 |
| 69681 | GIM_Try, /*On fail goto*//*Label 3831*/ GIMT_Encode4(222341), // Rule ID 987 // |
| 69682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot1Insts), |
| 69683 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sdot8), |
| 69684 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69685 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69686 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69687 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69689 | // MIs[0] clamp |
| 69690 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69693 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69694 | // (intrinsic_wo_chain:{ *:[i32] } 3006:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT8_I32_I4:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_I4), |
| 69696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69703 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69708 | GIR_RootConstrainSelectedInstOperands, |
| 69709 | // GIR_Coverage, 987, |
| 69710 | GIR_EraseRootFromParent_Done, |
| 69711 | // Label 3831: @222341 |
| 69712 | GIM_Try, /*On fail goto*//*Label 3832*/ GIMT_Encode4(222445), // Rule ID 988 // |
| 69713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot9Insts), |
| 69714 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fdot2_f32_bf16), |
| 69715 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 69717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 69718 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 69719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69720 | // MIs[0] clamp |
| 69721 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69724 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmodsdot), |
| 69725 | // (intrinsic_wo_chain:{ *:[f32] } 2016:{ *:[iPTR] }, (VOP3PModsDOT:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PModsDOT:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PModsDOT:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (timm:{ *:[i1] }):$clamp) => (V_DOT2_F32_BF16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2bf16:{ *:[v2bf16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$clamp) |
| 69726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT2_F32_BF16), |
| 69727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 69731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 69732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 69733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 69734 | GIR_RootToRootCopy, /*OpIdx*/5, // clamp |
| 69735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69739 | GIR_RootConstrainSelectedInstOperands, |
| 69740 | // GIR_Coverage, 988, |
| 69741 | GIR_EraseRootFromParent_Done, |
| 69742 | // Label 3832: @222445 |
| 69743 | GIM_Reject, |
| 69744 | // Label 3789: @222446 |
| 69745 | GIM_Try, /*On fail goto*//*Label 3833*/ GIMT_Encode4(222612), |
| 69746 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 69747 | GIM_Try, /*On fail goto*//*Label 3834*/ GIMT_Encode4(222522), // Rule ID 1103 // |
| 69748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX90APlus), |
| 69749 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2), |
| 69750 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69751 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69752 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69753 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 69754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69755 | // MIs[0] attrchan |
| 69756 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69757 | // MIs[0] attr |
| 69758 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69759 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69760 | // (intrinsic_wo_chain:{ *:[f32] } 2817:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, M0:{ *:[i32] }) => (V_INTERP_P2_F32:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$vsrc, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan) |
| 69761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69762 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69763 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0 |
| 69764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F32), |
| 69765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69766 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 69767 | GIR_RootToRootCopy, /*OpIdx*/3, // vsrc |
| 69768 | GIR_RootToRootCopy, /*OpIdx*/5, // attr |
| 69769 | GIR_RootToRootCopy, /*OpIdx*/4, // attrchan |
| 69770 | GIR_RootConstrainSelectedInstOperands, |
| 69771 | // GIR_Coverage, 1103, |
| 69772 | GIR_EraseRootFromParent_Done, |
| 69773 | // Label 3834: @222522 |
| 69774 | GIM_Try, /*On fail goto*//*Label 3835*/ GIMT_Encode4(222611), // Rule ID 927 // |
| 69775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_has32BankLDS_isNotGFX90APlus), |
| 69776 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p1_f16), |
| 69777 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69779 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 69780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69781 | // MIs[0] attrchan |
| 69782 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 69783 | // MIs[0] attr |
| 69784 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69785 | // MIs[0] high |
| 69786 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69787 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 69789 | // (intrinsic_wo_chain:{ *:[f32] } 2815:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] }) => (V_INTERP_P1LL_F16:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i1] }):$high) |
| 69790 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69791 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69792 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/6, // M0 |
| 69793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P1LL_F16), |
| 69794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 69796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 69797 | GIR_RootToRootCopy, /*OpIdx*/4, // attr |
| 69798 | GIR_RootToRootCopy, /*OpIdx*/3, // attrchan |
| 69799 | GIR_RootToRootCopy, /*OpIdx*/5, // high |
| 69800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69802 | GIR_RootConstrainSelectedInstOperands, |
| 69803 | // GIR_Coverage, 927, |
| 69804 | GIR_EraseRootFromParent_Done, |
| 69805 | // Label 3835: @222611 |
| 69806 | GIM_Reject, |
| 69807 | // Label 3833: @222612 |
| 69808 | GIM_Try, /*On fail goto*//*Label 3836*/ GIMT_Encode4(222899), |
| 69809 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 69810 | GIM_Try, /*On fail goto*//*Label 3837*/ GIMT_Encode4(222706), // Rule ID 2321 // |
| 69811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts), |
| 69812 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot4), |
| 69813 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69814 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69815 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 69816 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 69817 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69818 | // MIs[0] clamp |
| 69819 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 69820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 69821 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 69822 | // (intrinsic_wo_chain:{ *:[i32] } 3077:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_mods), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_DOT4_I32_IU8:{ *:[i32] } ?:{ *:[i32] }:$src0_mods, i32:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1_mods, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 69823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT4_I32_IU8), |
| 69824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_mods |
| 69826 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 69827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_mods |
| 69828 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 69829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69830 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 69831 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 69832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69836 | GIR_RootConstrainSelectedInstOperands, |
| 69837 | // GIR_Coverage, 2321, |
| 69838 | GIR_EraseRootFromParent_Done, |
| 69839 | // Label 3837: @222706 |
| 69840 | GIM_Try, /*On fail goto*//*Label 3838*/ GIMT_Encode4(222792), // Rule ID 2322 // |
| 69841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDot8Insts), |
| 69842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_sudot8), |
| 69843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 69844 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69845 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 69846 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 69847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69848 | // MIs[0] clamp |
| 69849 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 69850 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 69851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 69852 | // (intrinsic_wo_chain:{ *:[i32] } 3078:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_mods), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_mods), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_DOT8_I32_IU4:{ *:[i32] } ?:{ *:[i32] }:$src0_mods, i32:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1_mods, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 69853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_DOT8_I32_IU4), |
| 69854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_mods |
| 69856 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 69857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_mods |
| 69858 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 69859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 69860 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 69861 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 69862 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69866 | GIR_RootConstrainSelectedInstOperands, |
| 69867 | // GIR_Coverage, 2322, |
| 69868 | GIR_EraseRootFromParent_Done, |
| 69869 | // Label 3838: @222792 |
| 69870 | GIM_Try, /*On fail goto*//*Label 3839*/ GIMT_Encode4(222898), // Rule ID 926 // |
| 69871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isNotGFX90APlus), |
| 69872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_interp_p2_f16), |
| 69873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 69874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 69875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 69876 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 69877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 69878 | // MIs[0] attrchan |
| 69879 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 69880 | // MIs[0] attr |
| 69881 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 69882 | // MIs[0] high |
| 69883 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 69884 | GIM_RootCheckRegBankForClass, /*Op*/7, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 69885 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 69886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 69887 | // (intrinsic_wo_chain:{ *:[f16] } 2818:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (timm:{ *:[i32] }):$attrchan, (timm:{ *:[i32] }):$attr, (timm:{ *:[i1] }):$high, M0:{ *:[i32] }) => (V_INTERP_P2_F16:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, (timm:{ *:[i32] }):$attr, (timm:{ *:[i32] }):$attrchan, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, (timm:{ *:[i1] }):$high) |
| 69888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 69889 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 69890 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // M0 |
| 69891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_INTERP_P2_F16), |
| 69892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 69893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 69894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 69895 | GIR_RootToRootCopy, /*OpIdx*/5, // attr |
| 69896 | GIR_RootToRootCopy, /*OpIdx*/4, // attrchan |
| 69897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 69898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 69899 | GIR_RootToRootCopy, /*OpIdx*/6, // high |
| 69900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69901 | GIR_RootConstrainSelectedInstOperands, |
| 69902 | // GIR_Coverage, 926, |
| 69903 | GIR_EraseRootFromParent_Done, |
| 69904 | // Label 3839: @222898 |
| 69905 | GIM_Reject, |
| 69906 | // Label 3836: @222899 |
| 69907 | GIM_Reject, |
| 69908 | // Label 37: @222900 |
| 69909 | GIM_Try, /*On fail goto*//*Label 3840*/ GIMT_Encode4(223074), |
| 69910 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 69911 | GIM_Try, /*On fail goto*//*Label 3841*/ GIMT_Encode4(222923), // Rule ID 1088 // |
| 69912 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv), |
| 69913 | // (intrinsic_void 2963:{ *:[iPTR] }) => (S_DCACHE_INV) |
| 69914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV), |
| 69915 | GIR_RootConstrainSelectedInstOperands, |
| 69916 | // GIR_Coverage, 1088, |
| 69917 | GIR_EraseRootFromParent_Done, |
| 69918 | // Label 3841: @222923 |
| 69919 | GIM_Try, /*On fail goto*//*Label 3842*/ GIMT_Encode4(222941), // Rule ID 1089 // |
| 69920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7GFX8GFX9), |
| 69921 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_inv_vol), |
| 69922 | // (intrinsic_void 2964:{ *:[iPTR] }) => (S_DCACHE_INV_VOL) |
| 69923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_INV_VOL), |
| 69924 | GIR_RootConstrainSelectedInstOperands, |
| 69925 | // GIR_Coverage, 1089, |
| 69926 | GIR_EraseRootFromParent_Done, |
| 69927 | // Label 3842: @222941 |
| 69928 | GIM_Try, /*On fail goto*//*Label 3843*/ GIMT_Encode4(222959), // Rule ID 1090 // |
| 69929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus), |
| 69930 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb), |
| 69931 | // (intrinsic_void 2965:{ *:[iPTR] }) => (S_DCACHE_WB) |
| 69932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB), |
| 69933 | GIR_RootConstrainSelectedInstOperands, |
| 69934 | // GIR_Coverage, 1090, |
| 69935 | GIR_EraseRootFromParent_Done, |
| 69936 | // Label 3843: @222959 |
| 69937 | GIM_Try, /*On fail goto*//*Label 3844*/ GIMT_Encode4(222977), // Rule ID 1091 // |
| 69938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasScalarStores_isGFX8Plus), |
| 69939 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_dcache_wb_vol), |
| 69940 | // (intrinsic_void 2966:{ *:[iPTR] }) => (S_DCACHE_WB_VOL) |
| 69941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DCACHE_WB_VOL), |
| 69942 | GIR_RootConstrainSelectedInstOperands, |
| 69943 | // GIR_Coverage, 1091, |
| 69944 | GIR_EraseRootFromParent_Done, |
| 69945 | // Label 3844: @222977 |
| 69946 | GIM_Try, /*On fail goto*//*Label 3845*/ GIMT_Encode4(222995), // Rule ID 1098 // |
| 69947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6), |
| 69948 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_sc), |
| 69949 | // (intrinsic_void 1956:{ *:[iPTR] }) => (BUFFER_WBINVL1_SC) |
| 69950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_SC), |
| 69951 | GIR_RootConstrainSelectedInstOperands, |
| 69952 | // GIR_Coverage, 1098, |
| 69953 | GIR_EraseRootFromParent_Done, |
| 69954 | // Label 3845: @222995 |
| 69955 | GIM_Try, /*On fail goto*//*Label 3846*/ GIMT_Encode4(223013), // Rule ID 1099 // |
| 69956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 69957 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1), |
| 69958 | // (intrinsic_void 1955:{ *:[iPTR] }) => (BUFFER_WBINVL1) |
| 69959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1), |
| 69960 | GIR_RootConstrainSelectedInstOperands, |
| 69961 | // GIR_Coverage, 1099, |
| 69962 | GIR_EraseRootFromParent_Done, |
| 69963 | // Label 3846: @223013 |
| 69964 | GIM_Try, /*On fail goto*//*Label 3847*/ GIMT_Encode4(223031), // Rule ID 1100 // |
| 69965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus), |
| 69966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_buffer_wbinvl1_vol), |
| 69967 | // (intrinsic_void 1957:{ *:[iPTR] }) => (BUFFER_WBINVL1_VOL) |
| 69968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_WBINVL1_VOL), |
| 69969 | GIR_RootConstrainSelectedInstOperands, |
| 69970 | // GIR_Coverage, 1100, |
| 69971 | GIR_EraseRootFromParent_Done, |
| 69972 | // Label 3847: @223031 |
| 69973 | GIM_Try, /*On fail goto*//*Label 3848*/ GIMT_Encode4(223052), // Rule ID 1646 // |
| 69974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 69975 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready), |
| 69976 | // (intrinsic_void 2989:{ *:[iPTR] }) => (S_WAIT_EVENT 0:{ *:[i16] }) |
| 69977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT), |
| 69978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 69979 | GIR_RootConstrainSelectedInstOperands, |
| 69980 | // GIR_Coverage, 1646, |
| 69981 | GIR_EraseRootFromParent_Done, |
| 69982 | // Label 3848: @223052 |
| 69983 | GIM_Try, /*On fail goto*//*Label 3849*/ GIMT_Encode4(223073), // Rule ID 1647 // |
| 69984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 69985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_event_export_ready), |
| 69986 | // (intrinsic_void 2989:{ *:[iPTR] }) => (S_WAIT_EVENT 2:{ *:[i16] }) |
| 69987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EVENT), |
| 69988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/2, |
| 69989 | GIR_RootConstrainSelectedInstOperands, |
| 69990 | // GIR_Coverage, 1647, |
| 69991 | GIR_EraseRootFromParent_Done, |
| 69992 | // Label 3849: @223073 |
| 69993 | GIM_Reject, |
| 69994 | // Label 3840: @223074 |
| 69995 | GIM_Try, /*On fail goto*//*Label 3850*/ GIMT_Encode4(223779), |
| 69996 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 69997 | GIM_Try, /*On fail goto*//*Label 3851*/ GIMT_Encode4(223137), // Rule ID 6655 // |
| 69998 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill), |
| 69999 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 70000 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 70001 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 70002 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 70003 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 70004 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 70005 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 70006 | // (intrinsic_void 2824:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] })) => (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] }) |
| 70007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO), |
| 70008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 70009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70010 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1, |
| 70011 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 70012 | GIR_RootConstrainSelectedInstOperands, |
| 70013 | // GIR_Coverage, 6655, |
| 70014 | GIR_EraseRootFromParent_Done, |
| 70015 | // Label 3851: @223137 |
| 70016 | GIM_Try, /*On fail goto*//*Label 3852*/ GIMT_Encode4(223192), // Rule ID 6658 // |
| 70017 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote), |
| 70018 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 70019 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 70020 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_XOR), |
| 70021 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s1, |
| 70022 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s1, |
| 70023 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/2, uint8_t(-1), |
| 70024 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 70025 | // (intrinsic_void 3122:{ *:[iPTR] }, (xor:{ *:[i1] } i1:{ *:[i1] }:$src, -1:{ *:[i1] })) => (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, -1:{ *:[i1] }) |
| 70026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1), |
| 70027 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 70028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 70029 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1, |
| 70030 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/2, /*MergeInsnID's*/0, 1, |
| 70031 | GIR_RootConstrainSelectedInstOperands, |
| 70032 | // GIR_Coverage, 6658, |
| 70033 | GIR_EraseRootFromParent_Done, |
| 70034 | // Label 3852: @223192 |
| 70035 | GIM_Try, /*On fail goto*//*Label 3853*/ GIMT_Encode4(223212), // Rule ID 180 // |
| 70036 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_nop), |
| 70037 | // MIs[0] simm16 |
| 70038 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70039 | // (intrinsic_void 2975:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_NOP (timm:{ *:[i16] }):$simm16) |
| 70040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_NOP), |
| 70041 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70042 | GIR_RootConstrainSelectedInstOperands, |
| 70043 | // GIR_Coverage, 180, |
| 70044 | GIR_EraseRootFromParent_Done, |
| 70045 | // Label 3853: @223212 |
| 70046 | GIM_Try, /*On fail goto*//*Label 3854*/ GIMT_Encode4(223232), // Rule ID 186 // |
| 70047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_waitcnt), |
| 70048 | // MIs[0] simm16 |
| 70049 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70050 | // (intrinsic_void 2995:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_WAITCNT (timm:{ *:[i32] }):$simm16) |
| 70051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAITCNT), |
| 70052 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70053 | GIR_RootConstrainSelectedInstOperands, |
| 70054 | // GIR_Coverage, 186, |
| 70055 | GIR_EraseRootFromParent_Done, |
| 70056 | // Label 3854: @223232 |
| 70057 | GIM_Try, /*On fail goto*//*Label 3855*/ GIMT_Encode4(223252), // Rule ID 187 // |
| 70058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sethalt), |
| 70059 | // MIs[0] simm16 |
| 70060 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70061 | // (intrinsic_void 2980:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_SETHALT (timm:{ *:[i32] }):$simm16) |
| 70062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETHALT), |
| 70063 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70064 | GIR_RootConstrainSelectedInstOperands, |
| 70065 | // GIR_Coverage, 187, |
| 70066 | GIR_EraseRootFromParent_Done, |
| 70067 | // Label 3855: @223252 |
| 70068 | GIM_Try, /*On fail goto*//*Label 3856*/ GIMT_Encode4(223272), // Rule ID 188 // |
| 70069 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep), |
| 70070 | // MIs[0] simm16 |
| 70071 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70072 | // (intrinsic_void 2983:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_SLEEP (timm:{ *:[i32] }):$simm16) |
| 70073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP), |
| 70074 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70075 | GIR_RootConstrainSelectedInstOperands, |
| 70076 | // GIR_Coverage, 188, |
| 70077 | GIR_EraseRootFromParent_Done, |
| 70078 | // Label 3856: @223272 |
| 70079 | GIM_Try, /*On fail goto*//*Label 3857*/ GIMT_Encode4(223292), // Rule ID 190 // |
| 70080 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setprio), |
| 70081 | // MIs[0] simm16 |
| 70082 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70083 | // (intrinsic_void 2981:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_SETPRIO (timm:{ *:[i16] }):$simm16) |
| 70084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETPRIO), |
| 70085 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70086 | GIR_RootConstrainSelectedInstOperands, |
| 70087 | // GIR_Coverage, 190, |
| 70088 | GIR_EraseRootFromParent_Done, |
| 70089 | // Label 3857: @223292 |
| 70090 | GIM_Try, /*On fail goto*//*Label 3858*/ GIMT_Encode4(223312), // Rule ID 193 // |
| 70091 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_incperflevel), |
| 70092 | // MIs[0] simm16 |
| 70093 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70094 | // (intrinsic_void 2972:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_INCPERFLEVEL (timm:{ *:[i32] }):$simm16) |
| 70095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_INCPERFLEVEL), |
| 70096 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70097 | GIR_RootConstrainSelectedInstOperands, |
| 70098 | // GIR_Coverage, 193, |
| 70099 | GIR_EraseRootFromParent_Done, |
| 70100 | // Label 3858: @223312 |
| 70101 | GIM_Try, /*On fail goto*//*Label 3859*/ GIMT_Encode4(223332), // Rule ID 194 // |
| 70102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_decperflevel), |
| 70103 | // MIs[0] simm16 |
| 70104 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70105 | // (intrinsic_void 2967:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_DECPERFLEVEL (timm:{ *:[i32] }):$simm16) |
| 70106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_DECPERFLEVEL), |
| 70107 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70108 | GIR_RootConstrainSelectedInstOperands, |
| 70109 | // GIR_Coverage, 194, |
| 70110 | GIR_EraseRootFromParent_Done, |
| 70111 | // Label 3859: @223332 |
| 70112 | GIM_Try, /*On fail goto*//*Label 3860*/ GIMT_Encode4(223355), // Rule ID 197 // |
| 70113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 70114 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata_imm), |
| 70115 | // MIs[0] simm16 |
| 70116 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70117 | // (intrinsic_void 2986:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_TTRACEDATA_IMM (timm:{ *:[i16] }):$simm16) |
| 70118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA_IMM), |
| 70119 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70120 | GIR_RootConstrainSelectedInstOperands, |
| 70121 | // GIR_Coverage, 197, |
| 70122 | GIR_EraseRootFromParent_Done, |
| 70123 | // Label 3860: @223355 |
| 70124 | GIM_Try, /*On fail goto*//*Label 3861*/ GIMT_Encode4(223378), // Rule ID 198 // |
| 70125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_loadcnt), |
| 70127 | // MIs[0] simm16 |
| 70128 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70129 | // (intrinsic_void 2992:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_LOADCNT (timm:{ *:[i16] }):$simm16) |
| 70130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_LOADCNT), |
| 70131 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70132 | GIR_RootConstrainSelectedInstOperands, |
| 70133 | // GIR_Coverage, 198, |
| 70134 | GIR_EraseRootFromParent_Done, |
| 70135 | // Label 3861: @223378 |
| 70136 | GIM_Try, /*On fail goto*//*Label 3862*/ GIMT_Encode4(223401), // Rule ID 199 // |
| 70137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70138 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_storecnt), |
| 70139 | // MIs[0] simm16 |
| 70140 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70141 | // (intrinsic_void 2994:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_STORECNT (timm:{ *:[i16] }):$simm16) |
| 70142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_STORECNT), |
| 70143 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70144 | GIR_RootConstrainSelectedInstOperands, |
| 70145 | // GIR_Coverage, 199, |
| 70146 | GIR_EraseRootFromParent_Done, |
| 70147 | // Label 3862: @223401 |
| 70148 | GIM_Try, /*On fail goto*//*Label 3863*/ GIMT_Encode4(223424), // Rule ID 200 // |
| 70149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasImageInsts_isGFX12Plus), |
| 70150 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_samplecnt), |
| 70151 | // MIs[0] simm16 |
| 70152 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70153 | // (intrinsic_void 2993:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_SAMPLECNT (timm:{ *:[i16] }):$simm16) |
| 70154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_SAMPLECNT), |
| 70155 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70156 | GIR_RootConstrainSelectedInstOperands, |
| 70157 | // GIR_Coverage, 200, |
| 70158 | GIR_EraseRootFromParent_Done, |
| 70159 | // Label 3863: @223424 |
| 70160 | GIM_Try, /*On fail goto*//*Label 3864*/ GIMT_Encode4(223447), // Rule ID 201 // |
| 70161 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasImageInsts_isGFX12Plus), |
| 70162 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_bvhcnt), |
| 70163 | // MIs[0] simm16 |
| 70164 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70165 | // (intrinsic_void 2987:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_BVHCNT (timm:{ *:[i16] }):$simm16) |
| 70166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_BVHCNT), |
| 70167 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70168 | GIR_RootConstrainSelectedInstOperands, |
| 70169 | // GIR_Coverage, 201, |
| 70170 | GIR_EraseRootFromParent_Done, |
| 70171 | // Label 3864: @223447 |
| 70172 | GIM_Try, /*On fail goto*//*Label 3865*/ GIMT_Encode4(223470), // Rule ID 202 // |
| 70173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasExportInsts_isGFX12Plus), |
| 70174 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_expcnt), |
| 70175 | // MIs[0] simm16 |
| 70176 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70177 | // (intrinsic_void 2990:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_EXPCNT (timm:{ *:[i16] }):$simm16) |
| 70178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_EXPCNT), |
| 70179 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70180 | GIR_RootConstrainSelectedInstOperands, |
| 70181 | // GIR_Coverage, 202, |
| 70182 | GIR_EraseRootFromParent_Done, |
| 70183 | // Label 3865: @223470 |
| 70184 | GIM_Try, /*On fail goto*//*Label 3866*/ GIMT_Encode4(223493), // Rule ID 203 // |
| 70185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70186 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_dscnt), |
| 70187 | // MIs[0] simm16 |
| 70188 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70189 | // (intrinsic_void 2988:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_DSCNT (timm:{ *:[i16] }):$simm16) |
| 70190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_DSCNT), |
| 70191 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70192 | GIR_RootConstrainSelectedInstOperands, |
| 70193 | // GIR_Coverage, 203, |
| 70194 | GIR_EraseRootFromParent_Done, |
| 70195 | // Label 3866: @223493 |
| 70196 | GIM_Try, /*On fail goto*//*Label 3867*/ GIMT_Encode4(223516), // Rule ID 204 // |
| 70197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70198 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_wait_kmcnt), |
| 70199 | // MIs[0] simm16 |
| 70200 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70201 | // (intrinsic_void 2991:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_WAIT_KMCNT (timm:{ *:[i16] }):$simm16) |
| 70202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WAIT_KMCNT), |
| 70203 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70204 | GIR_RootConstrainSelectedInstOperands, |
| 70205 | // GIR_Coverage, 204, |
| 70206 | GIR_EraseRootFromParent_Done, |
| 70207 | // Label 3867: @223516 |
| 70208 | GIM_Try, /*On fail goto*//*Label 3868*/ GIMT_Encode4(223543), // Rule ID 1087 // |
| 70209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemTimeInst), |
| 70210 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memtime), |
| 70211 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 70213 | // (intrinsic_w_chain:{ *:[i64] } 2974:{ *:[iPTR] }) => (S_MEMTIME:{ *:[i64] }) |
| 70214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMTIME), |
| 70215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70216 | GIR_RootConstrainSelectedInstOperands, |
| 70217 | // GIR_Coverage, 1087, |
| 70218 | GIR_EraseRootFromParent_Done, |
| 70219 | // Label 3868: @223543 |
| 70220 | GIM_Try, /*On fail goto*//*Label 3869*/ GIMT_Encode4(223570), // Rule ID 1092 // |
| 70221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSMemRealTime), |
| 70222 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_memrealtime), |
| 70223 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 70225 | // (intrinsic_w_chain:{ *:[i64] } 2973:{ *:[iPTR] }) => (S_MEMREALTIME:{ *:[i64] }) |
| 70226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MEMREALTIME), |
| 70227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70228 | GIR_RootConstrainSelectedInstOperands, |
| 70229 | // GIR_Coverage, 1092, |
| 70230 | GIR_EraseRootFromParent_Done, |
| 70231 | // Label 3869: @223570 |
| 70232 | GIM_Try, /*On fail goto*//*Label 3870*/ GIMT_Encode4(223597), // Rule ID 1093 // |
| 70233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGetWaveIdInst), |
| 70234 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_get_waveid_in_workgroup), |
| 70235 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 70237 | // (intrinsic_w_chain:{ *:[i32] } 2969:{ *:[iPTR] }) => (S_GET_WAVEID_IN_WORKGROUP:{ *:[i32] }) |
| 70238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GET_WAVEID_IN_WORKGROUP), |
| 70239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70240 | GIR_RootConstrainSelectedInstOperands, |
| 70241 | // GIR_Coverage, 1093, |
| 70242 | GIR_EraseRootFromParent_Done, |
| 70243 | // Label 3870: @223597 |
| 70244 | GIM_Try, /*On fail goto*//*Label 3871*/ GIMT_Encode4(223625), // Rule ID 1128 // |
| 70245 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_live_mask), |
| 70246 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 70247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 70248 | // (intrinsic_w_chain:{ *:[i1] } 2829:{ *:[iPTR] }) => (SI_LIVE_MASK:{ *:[i1] }) |
| 70249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_LIVE_MASK), |
| 70250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 70251 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70252 | GIR_RootConstrainSelectedInstOperands, |
| 70253 | // GIR_Coverage, 1128, |
| 70254 | GIR_EraseRootFromParent_Done, |
| 70255 | // Label 3871: @223625 |
| 70256 | GIM_Try, /*On fail goto*//*Label 3872*/ GIMT_Encode4(223658), // Rule ID 1650 // |
| 70257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9GFX10), |
| 70258 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_pops_exiting_wave_id), |
| 70259 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 70261 | // (intrinsic_w_chain:{ *:[i32] } 2890:{ *:[iPTR] }) => (S_MOV_B32_sideeffects:{ *:[i32] } SRC_POPS_EXITING_WAVE_ID:{ *:[i32] }) |
| 70262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32_sideeffects), |
| 70263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70264 | GIR_AddRegister, /*InsnID*/0, GIMT_Encode2(AMDGPU::SRC_POPS_EXITING_WAVE_ID), /*AddRegisterRegFlags*/GIMT_Encode2(0), |
| 70265 | GIR_RootConstrainSelectedInstOperands, |
| 70266 | // GIR_Coverage, 1650, |
| 70267 | GIR_EraseRootFromParent_Done, |
| 70268 | // Label 3872: @223658 |
| 70269 | GIM_Try, /*On fail goto*//*Label 3873*/ GIMT_Encode4(223682), // Rule ID 189 // |
| 70270 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sleep_var), |
| 70271 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 70272 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 70273 | // (intrinsic_void 2984:{ *:[iPTR] }, SSrc_b32:{ *:[i32] }:$src0) => (S_SLEEP_VAR SSrc_b32:{ *:[i32] }:$src0) |
| 70274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SLEEP_VAR), |
| 70275 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 70276 | GIR_RootConstrainSelectedInstOperands, |
| 70277 | // GIR_Coverage, 189, |
| 70278 | GIR_EraseRootFromParent_Done, |
| 70279 | // Label 3873: @223682 |
| 70280 | GIM_Try, /*On fail goto*//*Label 3874*/ GIMT_Encode4(223718), // Rule ID 195 // |
| 70281 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_ttracedata), |
| 70282 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 70283 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 70284 | // (intrinsic_void 2985:{ *:[iPTR] }, M0:{ *:[i32] }) => (S_TTRACEDATA) |
| 70285 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70286 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70287 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // M0 |
| 70288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_TTRACEDATA), |
| 70289 | GIR_RootConstrainSelectedInstOperands, |
| 70290 | // GIR_Coverage, 195, |
| 70291 | GIR_EraseRootFromParent_Done, |
| 70292 | // Label 3874: @223718 |
| 70293 | GIM_Try, /*On fail goto*//*Label 3875*/ GIMT_Encode4(223748), // Rule ID 6654 // |
| 70294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_kill), |
| 70295 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 70296 | // (intrinsic_void 2824:{ *:[iPTR] }, i1:{ *:[i1] }:$src) => (SI_KILL_I1_PSEUDO SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] }) |
| 70297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_KILL_I1_PSEUDO), |
| 70298 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 70299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70300 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1, |
| 70301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70302 | GIR_RootConstrainSelectedInstOperands, |
| 70303 | // GIR_Coverage, 6654, |
| 70304 | GIR_EraseRootFromParent_Done, |
| 70305 | // Label 3875: @223748 |
| 70306 | GIM_Try, /*On fail goto*//*Label 3876*/ GIMT_Encode4(223778), // Rule ID 6657 // |
| 70307 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wqm_demote), |
| 70308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 70309 | // (intrinsic_void 3122:{ *:[iPTR] }, i1:{ *:[i1] }:$src) => (SI_DEMOTE_I1 SCSrc_i1:{ *:[i1] }:$src, 0:{ *:[i1] }) |
| 70310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_DEMOTE_I1), |
| 70311 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 70312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70313 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/1, |
| 70314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70315 | GIR_RootConstrainSelectedInstOperands, |
| 70316 | // GIR_Coverage, 6657, |
| 70317 | GIR_EraseRootFromParent_Done, |
| 70318 | // Label 3876: @223778 |
| 70319 | GIM_Reject, |
| 70320 | // Label 3850: @223779 |
| 70321 | GIM_Try, /*On fail goto*//*Label 3877*/ GIMT_Encode4(224110), |
| 70322 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 70323 | GIM_Try, /*On fail goto*//*Label 3878*/ GIMT_Encode4(223821), // Rule ID 121 // |
| 70324 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_setreg), |
| 70325 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 70326 | // MIs[0] simm16 |
| 70327 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70328 | GIM_CheckImmOperandPredicate, /*MI*/0, /*MO*/1, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_SIMM16bit), |
| 70329 | // (intrinsic_void 2982:{ *:[iPTR] }, (timm:{ *:[i32] })<<P:Predicate_SIMM16bit>><<X:as_i16timm>>:$simm16, i32:{ *:[i32] }:$sdst) => (S_SETREG_B32 i32:{ *:[i32] }:$sdst, (as_i16timm:{ *:[i32] } (timm:{ *:[i32] }):$simm16)) |
| 70330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SETREG_B32), |
| 70331 | GIR_RootToRootCopy, /*OpIdx*/2, // sdst |
| 70332 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/1, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // simm16 |
| 70333 | GIR_RootConstrainSelectedInstOperands, |
| 70334 | // GIR_Coverage, 121, |
| 70335 | GIR_EraseRootFromParent_Done, |
| 70336 | // Label 3878: @223821 |
| 70337 | GIM_Try, /*On fail goto*//*Label 3879*/ GIMT_Encode4(223853), // Rule ID 25 // |
| 70338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 70339 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn), |
| 70340 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 70342 | // MIs[0] src0 |
| 70343 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 70344 | // (intrinsic_w_chain:{ *:[i32] } 2978:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0) => (S_SENDMSG_RTN_B32:{ *:[i32] } (timm:{ *:[i32] }):$src0) |
| 70345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B32), |
| 70346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70347 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 70348 | GIR_RootConstrainSelectedInstOperands, |
| 70349 | // GIR_Coverage, 25, |
| 70350 | GIR_EraseRootFromParent_Done, |
| 70351 | // Label 3879: @223853 |
| 70352 | GIM_Try, /*On fail goto*//*Label 3880*/ GIMT_Encode4(223885), // Rule ID 26 // |
| 70353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 70354 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg_rtn), |
| 70355 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 70357 | // MIs[0] src0 |
| 70358 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 70359 | // (intrinsic_w_chain:{ *:[i64] } 2978:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0) => (S_SENDMSG_RTN_B64:{ *:[i64] } (timm:{ *:[i32] }):$src0) |
| 70360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG_RTN_B64), |
| 70361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70362 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 70363 | GIR_RootConstrainSelectedInstOperands, |
| 70364 | // GIR_Coverage, 26, |
| 70365 | GIR_EraseRootFromParent_Done, |
| 70366 | // Label 3880: @223885 |
| 70367 | GIM_Try, /*On fail goto*//*Label 3881*/ GIMT_Encode4(223914), // Rule ID 120 // |
| 70368 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_getreg), |
| 70369 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 70371 | // MIs[0] simm16 |
| 70372 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 70373 | // (intrinsic_w_chain:{ *:[i32] } 2971:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16) => (S_GETREG_B32:{ *:[i32] } (timm:{ *:[i32] }):$simm16) |
| 70374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32), |
| 70375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 70376 | GIR_RootToRootCopy, /*OpIdx*/2, // simm16 |
| 70377 | GIR_RootConstrainSelectedInstOperands, |
| 70378 | // GIR_Coverage, 120, |
| 70379 | GIR_EraseRootFromParent_Done, |
| 70380 | // Label 3881: @223914 |
| 70381 | GIM_Try, /*On fail goto*//*Label 3882*/ GIMT_Encode4(223955), // Rule ID 191 // |
| 70382 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsg), |
| 70383 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 70384 | // MIs[0] simm16 |
| 70385 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70386 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 70387 | // (intrinsic_void 2977:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] }) => (S_SENDMSG (timm:{ *:[i32] }):$simm16) |
| 70388 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70389 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70390 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0 |
| 70391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSG), |
| 70392 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70393 | GIR_RootConstrainSelectedInstOperands, |
| 70394 | // GIR_Coverage, 191, |
| 70395 | GIR_EraseRootFromParent_Done, |
| 70396 | // Label 3882: @223955 |
| 70397 | GIM_Try, /*On fail goto*//*Label 3883*/ GIMT_Encode4(223996), // Rule ID 192 // |
| 70398 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_sendmsghalt), |
| 70399 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 70400 | // MIs[0] simm16 |
| 70401 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 70402 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 70403 | // (intrinsic_void 2979:{ *:[iPTR] }, (timm:{ *:[i32] }):$simm16, M0:{ *:[i32] }) => (S_SENDMSGHALT (timm:{ *:[i32] }):$simm16) |
| 70404 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70405 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70406 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0 |
| 70407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_SENDMSGHALT), |
| 70408 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 70409 | GIR_RootConstrainSelectedInstOperands, |
| 70410 | // GIR_Coverage, 192, |
| 70411 | GIR_EraseRootFromParent_Done, |
| 70412 | // Label 3883: @223996 |
| 70413 | GIM_Try, /*On fail goto*//*Label 3884*/ GIMT_Encode4(224051), // Rule ID 6611 // |
| 70414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only), |
| 70415 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load), |
| 70416 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70417 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 70418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 70419 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 70420 | // (intrinsic_w_chain:{ *:[f32] } 2825:{ *:[iPTR] }, M0:{ *:[i32] }) => (LDS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i8] }) |
| 70421 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70422 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70423 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0 |
| 70424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::LDS_DIRECT_LOAD), |
| 70425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70427 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70428 | GIR_RootConstrainSelectedInstOperands, |
| 70429 | // GIR_Coverage, 6611, |
| 70430 | GIR_EraseRootFromParent_Done, |
| 70431 | // Label 3884: @224051 |
| 70432 | GIM_Try, /*On fail goto*//*Label 3885*/ GIMT_Encode4(224109), // Rule ID 6613 // |
| 70433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_lds_direct_load), |
| 70435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 70437 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 70438 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 70439 | // (intrinsic_w_chain:{ *:[f32] } 2825:{ *:[iPTR] }, M0:{ *:[i32] }) => (DS_DIRECT_LOAD:{ *:[f32] } 0:{ *:[i8] }, 1:{ *:[i8] }) |
| 70440 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 70441 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 70442 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // M0 |
| 70443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_DIRECT_LOAD), |
| 70444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70448 | GIR_RootConstrainSelectedInstOperands, |
| 70449 | // GIR_Coverage, 6613, |
| 70450 | GIR_EraseRootFromParent_Done, |
| 70451 | // Label 3885: @224109 |
| 70452 | GIM_Reject, |
| 70453 | // Label 3877: @224110 |
| 70454 | GIM_Try, /*On fail goto*//*Label 3886*/ GIMT_Encode4(230150), |
| 70455 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 70456 | GIM_Try, /*On fail goto*//*Label 3887*/ GIMT_Encode4(224188), // Rule ID 1095 // |
| 70457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding), |
| 70458 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 70459 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70460 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70462 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 70464 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in) => (BUFFER_ATOMIC_CSUB_ADDR64_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 70465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_ADDR64_RTN), |
| 70466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 70467 | GIR_RootToRootCopy, /*OpIdx*/3, // vdata_in |
| 70468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 70469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 70470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 70471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 70472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70474 | GIR_RootConstrainSelectedInstOperands, |
| 70475 | // GIR_Coverage, 1095, |
| 70476 | GIR_EraseRootFromParent_Done, |
| 70477 | // Label 3887: @224188 |
| 70478 | GIM_Try, /*On fail goto*//*Label 3888*/ GIMT_Encode4(224258), // Rule ID 1097 // |
| 70479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding), |
| 70480 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 70481 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70482 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70484 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 70486 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in) => (BUFFER_ATOMIC_CSUB_VBUFFER_ADDR64_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, i64:{ *:[i64] }:$vaddr, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 70487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_ADDR64_RTN), |
| 70488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 70489 | GIR_RootToRootCopy, /*OpIdx*/3, // vdata_in |
| 70490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 70491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 70492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 70493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 70494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70495 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70496 | GIR_RootConstrainSelectedInstOperands, |
| 70497 | // GIR_Coverage, 1097, |
| 70498 | GIR_EraseRootFromParent_Done, |
| 70499 | // Label 3888: @224258 |
| 70500 | GIM_Try, /*On fail goto*//*Label 3889*/ GIMT_Encode4(224323), // Rule ID 1094 // |
| 70501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding), |
| 70502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 70503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70504 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70506 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70507 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 70508 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in) => (BUFFER_ATOMIC_CSUB_OFFSET_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 70509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_OFFSET_RTN), |
| 70510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 70511 | GIR_RootToRootCopy, /*OpIdx*/3, // vdata_in |
| 70512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 70513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 70514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70517 | GIR_RootConstrainSelectedInstOperands, |
| 70518 | // GIR_Coverage, 1094, |
| 70519 | GIR_EraseRootFromParent_Done, |
| 70520 | // Label 3889: @224323 |
| 70521 | GIM_Try, /*On fail goto*//*Label 3890*/ GIMT_Encode4(224388), // Rule ID 1096 // |
| 70522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasGFX10_BEncoding), |
| 70523 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 70524 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70525 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70527 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 70529 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$vdata_in) => (BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset) |
| 70530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CSUB_VBUFFER_OFFSET_RTN), |
| 70531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 70532 | GIR_RootToRootCopy, /*OpIdx*/3, // vdata_in |
| 70533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 70534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 70535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70537 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70538 | GIR_RootConstrainSelectedInstOperands, |
| 70539 | // GIR_Coverage, 1096, |
| 70540 | GIR_EraseRootFromParent_Done, |
| 70541 | // Label 3890: @224388 |
| 70542 | GIM_Try, /*On fail goto*//*Label 3891*/ GIMT_Encode4(224449), // Rule ID 7433 // |
| 70543 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus), |
| 70544 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 70545 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70546 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70547 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 70548 | GIM_CheckHasNoUse, /*MI*/0, |
| 70549 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 70551 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_local_addrspace>> => (DS_COND_SUB_U32 ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 70552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_U32), |
| 70553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 70554 | GIR_RootToRootCopy, /*OpIdx*/3, // value |
| 70555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 70556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70557 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70558 | GIR_RootConstrainSelectedInstOperands, |
| 70559 | // GIR_Coverage, 7433, |
| 70560 | GIR_EraseRootFromParent_Done, |
| 70561 | // Label 3891: @224449 |
| 70562 | GIM_Try, /*On fail goto*//*Label 3892*/ GIMT_Encode4(224510), // Rule ID 7962 // |
| 70563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64), |
| 70564 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70565 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70566 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70567 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 70568 | GIM_CheckHasNoUse, /*MI*/0, |
| 70569 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70570 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 70571 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_local_addrspace>> => (DS_ADD_F64 ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 70572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_F64), |
| 70573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 70574 | GIR_RootToRootCopy, /*OpIdx*/3, // value |
| 70575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 70576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70577 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70578 | GIR_RootConstrainSelectedInstOperands, |
| 70579 | // GIR_Coverage, 7962, |
| 70580 | GIR_EraseRootFromParent_Done, |
| 70581 | // Label 3892: @224510 |
| 70582 | GIM_Try, /*On fail goto*//*Label 3893*/ GIMT_Encode4(224575), // Rule ID 7432 // |
| 70583 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 70584 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 70585 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70586 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70587 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 70588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70589 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70590 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 70591 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$value)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_local_addrspace>> => (DS_COND_SUB_RTN_U32:{ *:[i32] } ?:{ *:[i32] }:$ptr, anonymous_15876:{ *:[i32] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 70592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_COND_SUB_RTN_U32), |
| 70593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 70595 | GIR_RootToRootCopy, /*OpIdx*/3, // value |
| 70596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 70597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70598 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70599 | GIR_RootConstrainSelectedInstOperands, |
| 70600 | // GIR_Coverage, 7432, |
| 70601 | GIR_EraseRootFromParent_Done, |
| 70602 | // Label 3893: @224575 |
| 70603 | GIM_Try, /*On fail goto*//*Label 3894*/ GIMT_Encode4(224640), // Rule ID 7961 // |
| 70604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasLdsAtomicAddF64), |
| 70605 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70606 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70607 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70608 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/1, /*AddrSpace*/3, |
| 70609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 70610 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70611 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 70612 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[iPTR] } i32:{ *:[i32] }:$ptr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$value)<<P:Predicate_int_amdgcn_flat_atomic_fadd_local_addrspace>> => (DS_ADD_RTN_F64:{ *:[f64] } ?:{ *:[i32] }:$ptr, anonymous_15875:{ *:[f64] }:$value, Offset:{ *:[i32] }:$offset, 0:{ *:[i1] }) |
| 70613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_RTN_F64), |
| 70614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // ptr |
| 70616 | GIR_RootToRootCopy, /*OpIdx*/3, // value |
| 70617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 70618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70620 | GIR_RootConstrainSelectedInstOperands, |
| 70621 | // GIR_Coverage, 7961, |
| 70622 | GIR_EraseRootFromParent_Done, |
| 70623 | // Label 3894: @224640 |
| 70624 | GIM_Try, /*On fail goto*//*Label 3895*/ GIMT_Encode4(224708), // Rule ID 3713 // |
| 70625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus), |
| 70626 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 70627 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70628 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70629 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70630 | GIM_CheckHasNoUse, /*MI*/0, |
| 70631 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70633 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_global_addrspace>> => (GLOBAL_ATOMIC_COND_SUB_U32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR), |
| 70635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70636 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70641 | GIR_RootConstrainSelectedInstOperands, |
| 70642 | // GIR_Coverage, 3713, |
| 70643 | GIR_EraseRootFromParent_Done, |
| 70644 | // Label 3895: @224708 |
| 70645 | GIM_Try, /*On fail goto*//*Label 3896*/ GIMT_Encode4(224776), // Rule ID 3771 // |
| 70646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 70647 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70648 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70649 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70650 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70651 | GIM_CheckHasNoUse, /*MI*/0, |
| 70652 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70653 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70654 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR), |
| 70656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70657 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70662 | GIR_RootConstrainSelectedInstOperands, |
| 70663 | // GIR_Coverage, 3771, |
| 70664 | GIR_EraseRootFromParent_Done, |
| 70665 | // Label 3896: @224776 |
| 70666 | GIM_Try, /*On fail goto*//*Label 3897*/ GIMT_Encode4(224844), // Rule ID 3773 // |
| 70667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 70668 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 70669 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70670 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70671 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70672 | GIM_CheckHasNoUse, /*MI*/0, |
| 70673 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70674 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70675 | // (intrinsic_w_chain:{ *:[f32] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR), |
| 70677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70678 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70683 | GIR_RootConstrainSelectedInstOperands, |
| 70684 | // GIR_Coverage, 3773, |
| 70685 | GIR_EraseRootFromParent_Done, |
| 70686 | // Label 3897: @224844 |
| 70687 | GIM_Try, /*On fail goto*//*Label 3898*/ GIMT_Encode4(224912), // Rule ID 3777 // |
| 70688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 70689 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70690 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 70691 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 70692 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70693 | GIM_CheckHasNoUse, /*MI*/0, |
| 70694 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70696 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR), |
| 70698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70699 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70703 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70704 | GIR_RootConstrainSelectedInstOperands, |
| 70705 | // GIR_Coverage, 3777, |
| 70706 | GIR_EraseRootFromParent_Done, |
| 70707 | // Label 3898: @224912 |
| 70708 | GIM_Try, /*On fail goto*//*Label 3899*/ GIMT_Encode4(224980), // Rule ID 3779 // |
| 70709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 70710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 70711 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 70712 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 70713 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70714 | GIM_CheckHasNoUse, /*MI*/0, |
| 70715 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70716 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70717 | // (intrinsic_w_chain:{ *:[v2f16] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR), |
| 70719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70720 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70724 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70725 | GIR_RootConstrainSelectedInstOperands, |
| 70726 | // GIR_Coverage, 3779, |
| 70727 | GIR_EraseRootFromParent_Done, |
| 70728 | // Label 3899: @224980 |
| 70729 | GIM_Try, /*On fail goto*//*Label 3900*/ GIMT_Encode4(225048), // Rule ID 3819 // |
| 70730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 70731 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70732 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70733 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70734 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70735 | GIM_CheckHasNoUse, /*MI*/0, |
| 70736 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70738 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR), |
| 70740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70741 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70745 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70746 | GIR_RootConstrainSelectedInstOperands, |
| 70747 | // GIR_Coverage, 3819, |
| 70748 | GIR_EraseRootFromParent_Done, |
| 70749 | // Label 3900: @225048 |
| 70750 | GIM_Try, /*On fail goto*//*Label 3901*/ GIMT_Encode4(225116), // Rule ID 3823 // |
| 70751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 70752 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 70753 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70754 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70755 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70756 | GIM_CheckHasNoUse, /*MI*/0, |
| 70757 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70759 | // (intrinsic_w_chain:{ *:[f64] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR), |
| 70761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70762 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70766 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70767 | GIR_RootConstrainSelectedInstOperands, |
| 70768 | // GIR_Coverage, 3823, |
| 70769 | GIR_EraseRootFromParent_Done, |
| 70770 | // Label 3901: @225116 |
| 70771 | GIM_Try, /*On fail goto*//*Label 3902*/ GIMT_Encode4(225177), // Rule ID 3657 // |
| 70772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 70773 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 70774 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70775 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70776 | GIM_CheckHasNoUse, /*MI*/0, |
| 70777 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70778 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70779 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_csub_noret>> => (GLOBAL_ATOMIC_CSUB_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR), |
| 70781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70782 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70786 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70787 | GIR_RootConstrainSelectedInstOperands, |
| 70788 | // GIR_Coverage, 3657, |
| 70789 | GIR_EraseRootFromParent_Done, |
| 70790 | // Label 3902: @225177 |
| 70791 | GIM_Try, /*On fail goto*//*Label 3903*/ GIMT_Encode4(225238), // Rule ID 3741 // |
| 70792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 70793 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 70794 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70795 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70796 | GIM_CheckHasNoUse, /*MI*/0, |
| 70797 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70799 | // (intrinsic_w_chain:{ *:[f32] } 2035:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>> => (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR), |
| 70801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70802 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70805 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70806 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70807 | GIR_RootConstrainSelectedInstOperands, |
| 70808 | // GIR_Coverage, 3741, |
| 70809 | GIR_EraseRootFromParent_Done, |
| 70810 | // Label 3903: @225238 |
| 70811 | GIM_Try, /*On fail goto*//*Label 3904*/ GIMT_Encode4(225299), // Rule ID 3745 // |
| 70812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 70813 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 70814 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70815 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70816 | GIM_CheckHasNoUse, /*MI*/0, |
| 70817 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70818 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70819 | // (intrinsic_w_chain:{ *:[f32] } 2033:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>> => (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR), |
| 70821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70822 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70825 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70826 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70827 | GIR_RootConstrainSelectedInstOperands, |
| 70828 | // GIR_Coverage, 3745, |
| 70829 | GIR_EraseRootFromParent_Done, |
| 70830 | // Label 3904: @225299 |
| 70831 | GIM_Try, /*On fail goto*//*Label 3905*/ GIMT_Encode4(225360), // Rule ID 3757 // |
| 70832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 70833 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num), |
| 70834 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70836 | GIM_CheckHasNoUse, /*MI*/0, |
| 70837 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70838 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70839 | // (intrinsic_w_chain:{ *:[f32] } 2036:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>> => (GLOBAL_ATOMIC_FMIN_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR), |
| 70841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70842 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70846 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70847 | GIR_RootConstrainSelectedInstOperands, |
| 70848 | // GIR_Coverage, 3757, |
| 70849 | GIR_EraseRootFromParent_Done, |
| 70850 | // Label 3905: @225360 |
| 70851 | GIM_Try, /*On fail goto*//*Label 3906*/ GIMT_Encode4(225421), // Rule ID 3761 // |
| 70852 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 70853 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num), |
| 70854 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70855 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70856 | GIM_CheckHasNoUse, /*MI*/0, |
| 70857 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70859 | // (intrinsic_w_chain:{ *:[f32] } 2034:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>> => (GLOBAL_ATOMIC_FMAX_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR), |
| 70861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70862 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70866 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70867 | GIR_RootConstrainSelectedInstOperands, |
| 70868 | // GIR_Coverage, 3761, |
| 70869 | GIR_EraseRootFromParent_Done, |
| 70870 | // Label 3906: @225421 |
| 70871 | GIM_Try, /*On fail goto*//*Label 3907*/ GIMT_Encode4(225482), // Rule ID 3803 // |
| 70872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 70873 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 70874 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70876 | GIM_CheckHasNoUse, /*MI*/0, |
| 70877 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70879 | // (intrinsic_w_chain:{ *:[f64] } 2035:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>> => (GLOBAL_ATOMIC_MIN_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR), |
| 70881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70882 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70886 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70887 | GIR_RootConstrainSelectedInstOperands, |
| 70888 | // GIR_Coverage, 3803, |
| 70889 | GIR_EraseRootFromParent_Done, |
| 70890 | // Label 3907: @225482 |
| 70891 | GIM_Try, /*On fail goto*//*Label 3908*/ GIMT_Encode4(225543), // Rule ID 3807 // |
| 70892 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 70893 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 70894 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 70895 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 70896 | GIM_CheckHasNoUse, /*MI*/0, |
| 70897 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70899 | // (intrinsic_w_chain:{ *:[f64] } 2033:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>> => (GLOBAL_ATOMIC_MAX_F64_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR), |
| 70901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70902 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70907 | GIR_RootConstrainSelectedInstOperands, |
| 70908 | // GIR_Coverage, 3807, |
| 70909 | GIR_EraseRootFromParent_Done, |
| 70910 | // Label 3908: @225543 |
| 70911 | GIM_Try, /*On fail goto*//*Label 3909*/ GIMT_Encode4(225604), // Rule ID 3843 // |
| 70912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst), |
| 70913 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16), |
| 70914 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 70915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 70916 | GIM_CheckHasNoUse, /*MI*/0, |
| 70917 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70919 | // (intrinsic_w_chain:{ *:[v2i16] } 2032:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_v2bf16_noret>> => (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR), |
| 70921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70922 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 70926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70927 | GIR_RootConstrainSelectedInstOperands, |
| 70928 | // GIR_Coverage, 3843, |
| 70929 | GIR_EraseRootFromParent_Done, |
| 70930 | // Label 3909: @225604 |
| 70931 | GIM_Try, /*On fail goto*//*Label 3910*/ GIMT_Encode4(225676), // Rule ID 3711 // |
| 70932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_isGFX12Plus), |
| 70933 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 70934 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70935 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70936 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70938 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70940 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_global_addrspace>> => (GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_SADDR_RTN), |
| 70942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70944 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70948 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70949 | GIR_RootConstrainSelectedInstOperands, |
| 70950 | // GIR_Coverage, 3711, |
| 70951 | GIR_EraseRootFromParent_Done, |
| 70952 | // Label 3910: @225676 |
| 70953 | GIM_Try, /*On fail goto*//*Label 3911*/ GIMT_Encode4(225748), // Rule ID 3783 // |
| 70954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 70955 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 70956 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70957 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70958 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70962 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN), |
| 70964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70966 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70971 | GIR_RootConstrainSelectedInstOperands, |
| 70972 | // GIR_Coverage, 3783, |
| 70973 | GIR_EraseRootFromParent_Done, |
| 70974 | // Label 3911: @225748 |
| 70975 | GIM_Try, /*On fail goto*//*Label 3912*/ GIMT_Encode4(225820), // Rule ID 3785 // |
| 70976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 70977 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 70978 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 70979 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 70980 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 70981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 70982 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 70983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 70984 | // (intrinsic_w_chain:{ *:[f32] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 70985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_SADDR_RTN), |
| 70986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 70987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 70988 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 70989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 70990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 70991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 70992 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 70993 | GIR_RootConstrainSelectedInstOperands, |
| 70994 | // GIR_Coverage, 3785, |
| 70995 | GIR_EraseRootFromParent_Done, |
| 70996 | // Label 3912: @225820 |
| 70997 | GIM_Try, /*On fail goto*//*Label 3913*/ GIMT_Encode4(225892), // Rule ID 3787 // |
| 70998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 70999 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71000 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71001 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71002 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71004 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71006 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN), |
| 71008 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71010 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71014 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71015 | GIR_RootConstrainSelectedInstOperands, |
| 71016 | // GIR_Coverage, 3787, |
| 71017 | GIR_EraseRootFromParent_Done, |
| 71018 | // Label 3913: @225892 |
| 71019 | GIM_Try, /*On fail goto*//*Label 3914*/ GIMT_Encode4(225964), // Rule ID 3789 // |
| 71020 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 71021 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71022 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71023 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71024 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71026 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71028 | // (intrinsic_w_chain:{ *:[v2f16] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN:{ *:[v2f16] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_SADDR_RTN), |
| 71030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71032 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71037 | GIR_RootConstrainSelectedInstOperands, |
| 71038 | // GIR_Coverage, 3789, |
| 71039 | GIR_EraseRootFromParent_Done, |
| 71040 | // Label 3914: @225964 |
| 71041 | GIM_Try, /*On fail goto*//*Label 3915*/ GIMT_Encode4(226036), // Rule ID 3821 // |
| 71042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71043 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71044 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71046 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71048 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71049 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71050 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN), |
| 71052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71054 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71059 | GIR_RootConstrainSelectedInstOperands, |
| 71060 | // GIR_Coverage, 3821, |
| 71061 | GIR_EraseRootFromParent_Done, |
| 71062 | // Label 3915: @226036 |
| 71063 | GIM_Try, /*On fail goto*//*Label 3916*/ GIMT_Encode4(226108), // Rule ID 3825 // |
| 71064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71065 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71066 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71067 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71068 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71070 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71072 | // (intrinsic_w_chain:{ *:[f64] } 2031:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_SADDR_RTN), |
| 71074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71076 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71081 | GIR_RootConstrainSelectedInstOperands, |
| 71082 | // GIR_Coverage, 3825, |
| 71083 | GIR_EraseRootFromParent_Done, |
| 71084 | // Label 3916: @226108 |
| 71085 | GIM_Try, /*On fail goto*//*Label 3917*/ GIMT_Encode4(226173), // Rule ID 3655 // |
| 71086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 71087 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 71088 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71089 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71091 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71093 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data) => (GLOBAL_ATOMIC_CSUB_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_SADDR_RTN), |
| 71095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71097 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71102 | GIR_RootConstrainSelectedInstOperands, |
| 71103 | // GIR_Coverage, 3655, |
| 71104 | GIR_EraseRootFromParent_Done, |
| 71105 | // Label 3917: @226173 |
| 71106 | GIM_Try, /*On fail goto*//*Label 3918*/ GIMT_Encode4(226238), // Rule ID 3715 // |
| 71107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 71108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64), |
| 71109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71110 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71112 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71114 | // (intrinsic_w_chain:{ *:[i64] } 2037:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data) => (GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_SADDR_RTN), |
| 71116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71118 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71123 | GIR_RootConstrainSelectedInstOperands, |
| 71124 | // GIR_Coverage, 3715, |
| 71125 | GIR_EraseRootFromParent_Done, |
| 71126 | // Label 3918: @226238 |
| 71127 | GIM_Try, /*On fail goto*//*Label 3919*/ GIMT_Encode4(226303), // Rule ID 3743 // |
| 71128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71129 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71130 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71131 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71133 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71134 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71135 | // (intrinsic_w_chain:{ *:[f32] } 2035:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN), |
| 71137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71139 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71143 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71144 | GIR_RootConstrainSelectedInstOperands, |
| 71145 | // GIR_Coverage, 3743, |
| 71146 | GIR_EraseRootFromParent_Done, |
| 71147 | // Label 3919: @226303 |
| 71148 | GIM_Try, /*On fail goto*//*Label 3920*/ GIMT_Encode4(226368), // Rule ID 3747 // |
| 71149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71150 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71151 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71152 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71154 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71155 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71156 | // (intrinsic_w_chain:{ *:[f32] } 2033:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71157 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN), |
| 71158 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71160 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71165 | GIR_RootConstrainSelectedInstOperands, |
| 71166 | // GIR_Coverage, 3747, |
| 71167 | GIR_EraseRootFromParent_Done, |
| 71168 | // Label 3920: @226368 |
| 71169 | GIM_Try, /*On fail goto*//*Label 3921*/ GIMT_Encode4(226433), // Rule ID 3759 // |
| 71170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71171 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num), |
| 71172 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71173 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71175 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71177 | // (intrinsic_w_chain:{ *:[f32] } 2036:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMIN_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_SADDR_RTN), |
| 71179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71181 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71185 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71186 | GIR_RootConstrainSelectedInstOperands, |
| 71187 | // GIR_Coverage, 3759, |
| 71188 | GIR_EraseRootFromParent_Done, |
| 71189 | // Label 3921: @226433 |
| 71190 | GIM_Try, /*On fail goto*//*Label 3922*/ GIMT_Encode4(226498), // Rule ID 3763 // |
| 71191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num), |
| 71193 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71194 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71196 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71197 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71198 | // (intrinsic_w_chain:{ *:[f32] } 2034:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMAX_SADDR_RTN:{ *:[f32] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71199 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_SADDR_RTN), |
| 71200 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71202 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71207 | GIR_RootConstrainSelectedInstOperands, |
| 71208 | // GIR_Coverage, 3763, |
| 71209 | GIR_EraseRootFromParent_Done, |
| 71210 | // Label 3922: @226498 |
| 71211 | GIM_Try, /*On fail goto*//*Label 3923*/ GIMT_Encode4(226563), // Rule ID 3805 // |
| 71212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71213 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71214 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71215 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71217 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71219 | // (intrinsic_w_chain:{ *:[f64] } 2035:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (GLOBAL_ATOMIC_MIN_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_SADDR_RTN), |
| 71221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71223 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71228 | GIR_RootConstrainSelectedInstOperands, |
| 71229 | // GIR_Coverage, 3805, |
| 71230 | GIR_EraseRootFromParent_Done, |
| 71231 | // Label 3923: @226563 |
| 71232 | GIM_Try, /*On fail goto*//*Label 3924*/ GIMT_Encode4(226628), // Rule ID 3809 // |
| 71233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71234 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71235 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71236 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71237 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71238 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71239 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71240 | // (intrinsic_w_chain:{ *:[f64] } 2033:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (GLOBAL_ATOMIC_MAX_F64_SADDR_RTN:{ *:[f64] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_SADDR_RTN), |
| 71242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71244 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71249 | GIR_RootConstrainSelectedInstOperands, |
| 71250 | // GIR_Coverage, 3809, |
| 71251 | GIR_EraseRootFromParent_Done, |
| 71252 | // Label 3924: @226628 |
| 71253 | GIM_Try, /*On fail goto*//*Label 3925*/ GIMT_Encode4(226693), // Rule ID 3845 // |
| 71254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst), |
| 71255 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16), |
| 71256 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71257 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71259 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71260 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 71261 | // (intrinsic_w_chain:{ *:[v2i16] } 2032:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data) => (GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN:{ *:[v2i16] } ?:{ *:[i32] }:$voffset, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 71262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_SADDR_RTN), |
| 71263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 71265 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 71267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 71268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71269 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71270 | GIR_RootConstrainSelectedInstOperands, |
| 71271 | // GIR_Coverage, 3845, |
| 71272 | GIR_EraseRootFromParent_Done, |
| 71273 | // Label 3925: @226693 |
| 71274 | GIM_Try, /*On fail goto*//*Label 3926*/ GIMT_Encode4(226756), // Rule ID 3712 // |
| 71275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus), |
| 71276 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 71277 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71278 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71279 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71280 | GIM_CheckHasNoUse, /*MI*/0, |
| 71281 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71283 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_global_addrspace>> => (GLOBAL_ATOMIC_COND_SUB_U32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 71284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32), |
| 71285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71286 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71290 | GIR_RootConstrainSelectedInstOperands, |
| 71291 | // GIR_Coverage, 3712, |
| 71292 | GIR_EraseRootFromParent_Done, |
| 71293 | // Label 3926: @226756 |
| 71294 | GIM_Try, /*On fail goto*//*Label 3927*/ GIMT_Encode4(226819), // Rule ID 3770 // |
| 71295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 71296 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71297 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71298 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71299 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71300 | GIM_CheckHasNoUse, /*MI*/0, |
| 71301 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71303 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32), |
| 71305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71306 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71310 | GIR_RootConstrainSelectedInstOperands, |
| 71311 | // GIR_Coverage, 3770, |
| 71312 | GIR_EraseRootFromParent_Done, |
| 71313 | // Label 3927: @226819 |
| 71314 | GIM_Try, /*On fail goto*//*Label 3928*/ GIMT_Encode4(226882), // Rule ID 3772 // |
| 71315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 71316 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71317 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71318 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71319 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71320 | GIM_CheckHasNoUse, /*MI*/0, |
| 71321 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71323 | // (intrinsic_w_chain:{ *:[f32] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32), |
| 71325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71326 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71330 | GIR_RootConstrainSelectedInstOperands, |
| 71331 | // GIR_Coverage, 3772, |
| 71332 | GIR_EraseRootFromParent_Done, |
| 71333 | // Label 3928: @226882 |
| 71334 | GIM_Try, /*On fail goto*//*Label 3929*/ GIMT_Encode4(226945), // Rule ID 3776 // |
| 71335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 71336 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71337 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71338 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71339 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71340 | GIM_CheckHasNoUse, /*MI*/0, |
| 71341 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71343 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 71344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16), |
| 71345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71346 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71350 | GIR_RootConstrainSelectedInstOperands, |
| 71351 | // GIR_Coverage, 3776, |
| 71352 | GIR_EraseRootFromParent_Done, |
| 71353 | // Label 3929: @226945 |
| 71354 | GIM_Try, /*On fail goto*//*Label 3930*/ GIMT_Encode4(227008), // Rule ID 3778 // |
| 71355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 71356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71357 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71358 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71359 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71360 | GIM_CheckHasNoUse, /*MI*/0, |
| 71361 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71363 | // (intrinsic_w_chain:{ *:[v2f16] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 71364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16), |
| 71365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71366 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71369 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71370 | GIR_RootConstrainSelectedInstOperands, |
| 71371 | // GIR_Coverage, 3778, |
| 71372 | GIR_EraseRootFromParent_Done, |
| 71373 | // Label 3930: @227008 |
| 71374 | GIM_Try, /*On fail goto*//*Label 3931*/ GIMT_Encode4(227071), // Rule ID 3818 // |
| 71375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71377 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71378 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71379 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71380 | GIM_CheckHasNoUse, /*MI*/0, |
| 71381 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71383 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64), |
| 71385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71386 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71389 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71390 | GIR_RootConstrainSelectedInstOperands, |
| 71391 | // GIR_Coverage, 3818, |
| 71392 | GIR_EraseRootFromParent_Done, |
| 71393 | // Label 3931: @227071 |
| 71394 | GIM_Try, /*On fail goto*//*Label 3932*/ GIMT_Encode4(227134), // Rule ID 3822 // |
| 71395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71396 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71397 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71398 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71399 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71400 | GIM_CheckHasNoUse, /*MI*/0, |
| 71401 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71403 | // (intrinsic_w_chain:{ *:[f64] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_noret_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64), |
| 71405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71406 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71410 | GIR_RootConstrainSelectedInstOperands, |
| 71411 | // GIR_Coverage, 3822, |
| 71412 | GIR_EraseRootFromParent_Done, |
| 71413 | // Label 3932: @227134 |
| 71414 | GIM_Try, /*On fail goto*//*Label 3933*/ GIMT_Encode4(227190), // Rule ID 3656 // |
| 71415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 71416 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 71417 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71418 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71419 | GIM_CheckHasNoUse, /*MI*/0, |
| 71420 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71422 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_csub_noret>> => (GLOBAL_ATOMIC_CSUB VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 71423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB), |
| 71424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71425 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71428 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71429 | GIR_RootConstrainSelectedInstOperands, |
| 71430 | // GIR_Coverage, 3656, |
| 71431 | GIR_EraseRootFromParent_Done, |
| 71432 | // Label 3933: @227190 |
| 71433 | GIM_Try, /*On fail goto*//*Label 3934*/ GIMT_Encode4(227246), // Rule ID 3740 // |
| 71434 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71435 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71436 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71438 | GIM_CheckHasNoUse, /*MI*/0, |
| 71439 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71441 | // (intrinsic_w_chain:{ *:[f32] } 2035:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>> => (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN), |
| 71443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71444 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71448 | GIR_RootConstrainSelectedInstOperands, |
| 71449 | // GIR_Coverage, 3740, |
| 71450 | GIR_EraseRootFromParent_Done, |
| 71451 | // Label 3934: @227246 |
| 71452 | GIM_Try, /*On fail goto*//*Label 3935*/ GIMT_Encode4(227302), // Rule ID 3744 // |
| 71453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71454 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71455 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71456 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71457 | GIM_CheckHasNoUse, /*MI*/0, |
| 71458 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71460 | // (intrinsic_w_chain:{ *:[f32] } 2033:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>> => (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX), |
| 71462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71463 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71467 | GIR_RootConstrainSelectedInstOperands, |
| 71468 | // GIR_Coverage, 3744, |
| 71469 | GIR_EraseRootFromParent_Done, |
| 71470 | // Label 3935: @227302 |
| 71471 | GIM_Try, /*On fail goto*//*Label 3936*/ GIMT_Encode4(227358), // Rule ID 3756 // |
| 71472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71473 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num), |
| 71474 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71475 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71476 | GIM_CheckHasNoUse, /*MI*/0, |
| 71477 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71479 | // (intrinsic_w_chain:{ *:[f32] } 2036:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_num_noret>> => (GLOBAL_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN), |
| 71481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71482 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71486 | GIR_RootConstrainSelectedInstOperands, |
| 71487 | // GIR_Coverage, 3756, |
| 71488 | GIR_EraseRootFromParent_Done, |
| 71489 | // Label 3936: @227358 |
| 71490 | GIM_Try, /*On fail goto*//*Label 3937*/ GIMT_Encode4(227414), // Rule ID 3760 // |
| 71491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71492 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num), |
| 71493 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71494 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71495 | GIM_CheckHasNoUse, /*MI*/0, |
| 71496 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71498 | // (intrinsic_w_chain:{ *:[f32] } 2034:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_num_noret>> => (GLOBAL_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX), |
| 71500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71501 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71505 | GIR_RootConstrainSelectedInstOperands, |
| 71506 | // GIR_Coverage, 3760, |
| 71507 | GIR_EraseRootFromParent_Done, |
| 71508 | // Label 3937: @227414 |
| 71509 | GIM_Try, /*On fail goto*//*Label 3938*/ GIMT_Encode4(227470), // Rule ID 3802 // |
| 71510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71511 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71512 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71514 | GIM_CheckHasNoUse, /*MI*/0, |
| 71515 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71516 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71517 | // (intrinsic_w_chain:{ *:[f64] } 2035:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmin_noret>> => (GLOBAL_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64), |
| 71519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71520 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71523 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71524 | GIR_RootConstrainSelectedInstOperands, |
| 71525 | // GIR_Coverage, 3802, |
| 71526 | GIR_EraseRootFromParent_Done, |
| 71527 | // Label 3938: @227470 |
| 71528 | GIM_Try, /*On fail goto*//*Label 3939*/ GIMT_Encode4(227526), // Rule ID 3806 // |
| 71529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71530 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71531 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71532 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71533 | GIM_CheckHasNoUse, /*MI*/0, |
| 71534 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71536 | // (intrinsic_w_chain:{ *:[f64] } 2033:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fmax_noret>> => (GLOBAL_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64), |
| 71538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71539 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71543 | GIR_RootConstrainSelectedInstOperands, |
| 71544 | // GIR_Coverage, 3806, |
| 71545 | GIR_EraseRootFromParent_Done, |
| 71546 | // Label 3939: @227526 |
| 71547 | GIM_Try, /*On fail goto*//*Label 3940*/ GIMT_Encode4(227582), // Rule ID 3842 // |
| 71548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst), |
| 71549 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16), |
| 71550 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71551 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71552 | GIM_CheckHasNoUse, /*MI*/0, |
| 71553 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71554 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71555 | // (intrinsic_w_chain:{ *:[v2i16] } 2032:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_v2bf16_noret>> => (GLOBAL_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 71556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16), |
| 71557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71558 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71561 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71562 | GIR_RootConstrainSelectedInstOperands, |
| 71563 | // GIR_Coverage, 3842, |
| 71564 | GIR_EraseRootFromParent_Done, |
| 71565 | // Label 3940: @227582 |
| 71566 | GIM_Try, /*On fail goto*//*Label 3941*/ GIMT_Encode4(227649), // Rule ID 3710 // |
| 71567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts_isGFX12Plus), |
| 71568 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 71569 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71570 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71571 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71572 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71573 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71575 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_global_addrspace>> => (GLOBAL_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 71576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_COND_SUB_U32_RTN), |
| 71577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71579 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71582 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71583 | GIR_RootConstrainSelectedInstOperands, |
| 71584 | // GIR_Coverage, 3710, |
| 71585 | GIR_EraseRootFromParent_Done, |
| 71586 | // Label 3941: @227649 |
| 71587 | GIM_Try, /*On fail goto*//*Label 3942*/ GIMT_Encode4(227716), // Rule ID 3782 // |
| 71588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 71589 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71590 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71591 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71592 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71594 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71596 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN), |
| 71598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71600 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71604 | GIR_RootConstrainSelectedInstOperands, |
| 71605 | // GIR_Coverage, 3782, |
| 71606 | GIR_EraseRootFromParent_Done, |
| 71607 | // Label 3942: @227716 |
| 71608 | GIM_Try, /*On fail goto*//*Label 3943*/ GIMT_Encode4(227783), // Rule ID 3784 // |
| 71609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 71610 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71611 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71612 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71613 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71615 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71617 | // (intrinsic_w_chain:{ *:[f32] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F32_RTN), |
| 71619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71621 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71625 | GIR_RootConstrainSelectedInstOperands, |
| 71626 | // GIR_Coverage, 3784, |
| 71627 | GIR_EraseRootFromParent_Done, |
| 71628 | // Label 3943: @227783 |
| 71629 | GIM_Try, /*On fail goto*//*Label 3944*/ GIMT_Encode4(227850), // Rule ID 3786 // |
| 71630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 71631 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71632 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71634 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71636 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71638 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 71639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN), |
| 71640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71642 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71646 | GIR_RootConstrainSelectedInstOperands, |
| 71647 | // GIR_Coverage, 3786, |
| 71648 | GIR_EraseRootFromParent_Done, |
| 71649 | // Label 3944: @227850 |
| 71650 | GIM_Try, /*On fail goto*//*Label 3945*/ GIMT_Encode4(227917), // Rule ID 3788 // |
| 71651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 71652 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71653 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71654 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71655 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71657 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71659 | // (intrinsic_w_chain:{ *:[v2f16] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 71660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_F16_RTN), |
| 71661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71663 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71667 | GIR_RootConstrainSelectedInstOperands, |
| 71668 | // GIR_Coverage, 3788, |
| 71669 | GIR_EraseRootFromParent_Done, |
| 71670 | // Label 3945: @227917 |
| 71671 | GIM_Try, /*On fail goto*//*Label 3946*/ GIMT_Encode4(227984), // Rule ID 3820 // |
| 71672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 71674 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71675 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71676 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71678 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71680 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN), |
| 71682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71684 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71688 | GIR_RootConstrainSelectedInstOperands, |
| 71689 | // GIR_Coverage, 3820, |
| 71690 | GIR_EraseRootFromParent_Done, |
| 71691 | // Label 3946: @227984 |
| 71692 | GIM_Try, /*On fail goto*//*Label 3947*/ GIMT_Encode4(228051), // Rule ID 3824 // |
| 71693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 71694 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd), |
| 71695 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71696 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71697 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71699 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71700 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71701 | // (intrinsic_w_chain:{ *:[f64] } 2031:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_global_atomic_fadd_global_addrspace>> => (GLOBAL_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ADD_F64_RTN), |
| 71703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71705 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71708 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71709 | GIR_RootConstrainSelectedInstOperands, |
| 71710 | // GIR_Coverage, 3824, |
| 71711 | GIR_EraseRootFromParent_Done, |
| 71712 | // Label 3947: @228051 |
| 71713 | GIM_Try, /*On fail goto*//*Label 3948*/ GIMT_Encode4(228111), // Rule ID 3654 // |
| 71714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 71715 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_csub), |
| 71716 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71719 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71721 | // (intrinsic_w_chain:{ *:[i32] } 2030:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data) => (GLOBAL_ATOMIC_CSUB_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 71722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CSUB_RTN), |
| 71723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71725 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71729 | GIR_RootConstrainSelectedInstOperands, |
| 71730 | // GIR_Coverage, 3654, |
| 71731 | GIR_EraseRootFromParent_Done, |
| 71732 | // Label 3948: @228111 |
| 71733 | GIM_Try, /*On fail goto*//*Label 3949*/ GIMT_Encode4(228171), // Rule ID 3714 // |
| 71734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 71735 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_ordered_add_b64), |
| 71736 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71739 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71741 | // (intrinsic_w_chain:{ *:[i64] } 2037:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i64:{ *:[i64] }:$data) => (GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[i64] }:$data, ?:{ *:[i32] }:$offset) |
| 71742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_ORDERED_ADD_B64_RTN), |
| 71743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71745 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71748 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71749 | GIR_RootConstrainSelectedInstOperands, |
| 71750 | // GIR_Coverage, 3714, |
| 71751 | GIR_EraseRootFromParent_Done, |
| 71752 | // Label 3949: @228171 |
| 71753 | GIM_Try, /*On fail goto*//*Label 3950*/ GIMT_Encode4(228231), // Rule ID 3742 // |
| 71754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71755 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71756 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71759 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71761 | // (intrinsic_w_chain:{ *:[f32] } 2035:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN), |
| 71763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71765 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71769 | GIR_RootConstrainSelectedInstOperands, |
| 71770 | // GIR_Coverage, 3742, |
| 71771 | GIR_EraseRootFromParent_Done, |
| 71772 | // Label 3950: @228231 |
| 71773 | GIM_Try, /*On fail goto*//*Label 3951*/ GIMT_Encode4(228291), // Rule ID 3746 // |
| 71774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasFlatGlobalInsts), |
| 71775 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71776 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71777 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71779 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71780 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71781 | // (intrinsic_w_chain:{ *:[f32] } 2033:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN), |
| 71783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71785 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71788 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71789 | GIR_RootConstrainSelectedInstOperands, |
| 71790 | // GIR_Coverage, 3746, |
| 71791 | GIR_EraseRootFromParent_Done, |
| 71792 | // Label 3951: @228291 |
| 71793 | GIM_Try, /*On fail goto*//*Label 3952*/ GIMT_Encode4(228351), // Rule ID 3758 // |
| 71794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71795 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin_num), |
| 71796 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71797 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71798 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71799 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71801 | // (intrinsic_w_chain:{ *:[f32] } 2036:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMIN_RTN), |
| 71803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71805 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71809 | GIR_RootConstrainSelectedInstOperands, |
| 71810 | // GIR_Coverage, 3758, |
| 71811 | GIR_EraseRootFromParent_Done, |
| 71812 | // Label 3952: @228351 |
| 71813 | GIM_Try, /*On fail goto*//*Label 3953*/ GIMT_Encode4(228411), // Rule ID 3762 // |
| 71814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 71815 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax_num), |
| 71816 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71817 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71819 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71821 | // (intrinsic_w_chain:{ *:[f32] } 2034:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (GLOBAL_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 71822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_FMAX_RTN), |
| 71823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71825 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71828 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71829 | GIR_RootConstrainSelectedInstOperands, |
| 71830 | // GIR_Coverage, 3762, |
| 71831 | GIR_EraseRootFromParent_Done, |
| 71832 | // Label 3953: @228411 |
| 71833 | GIM_Try, /*On fail goto*//*Label 3954*/ GIMT_Encode4(228471), // Rule ID 3804 // |
| 71834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71835 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmin), |
| 71836 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71837 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71839 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71841 | // (intrinsic_w_chain:{ *:[f64] } 2035:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (GLOBAL_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MIN_F64_RTN), |
| 71843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71845 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71849 | GIR_RootConstrainSelectedInstOperands, |
| 71850 | // GIR_Coverage, 3804, |
| 71851 | GIR_EraseRootFromParent_Done, |
| 71852 | // Label 3954: @228471 |
| 71853 | GIM_Try, /*On fail goto*//*Label 3955*/ GIMT_Encode4(228531), // Rule ID 3808 // |
| 71854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasFlatGlobalInsts), |
| 71855 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fmax), |
| 71856 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 71858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71859 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71861 | // (intrinsic_w_chain:{ *:[f64] } 2033:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (GLOBAL_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 71862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_MAX_F64_RTN), |
| 71863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71865 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71868 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71869 | GIR_RootConstrainSelectedInstOperands, |
| 71870 | // GIR_Coverage, 3808, |
| 71871 | GIR_EraseRootFromParent_Done, |
| 71872 | // Label 3955: @228531 |
| 71873 | GIM_Try, /*On fail goto*//*Label 3956*/ GIMT_Encode4(228591), // Rule ID 3844 // |
| 71874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicGlobalPkAddBF16Inst), |
| 71875 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_atomic_fadd_v2bf16), |
| 71876 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 71877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 71878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 71879 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 71881 | // (intrinsic_w_chain:{ *:[v2i16] } 2032:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data) => (GLOBAL_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2i16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 71882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_PK_ADD_BF16_RTN), |
| 71883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71885 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 71888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71889 | GIR_RootConstrainSelectedInstOperands, |
| 71890 | // GIR_Coverage, 3844, |
| 71891 | GIR_EraseRootFromParent_Done, |
| 71892 | // Label 3956: @228591 |
| 71893 | GIM_Try, /*On fail goto*//*Label 3957*/ GIMT_Encode4(228633), // Rule ID 7970 // |
| 71894 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn), |
| 71895 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 71897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71898 | // MIs[0] offset32 |
| 71899 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 71900 | // (intrinsic_w_chain:{ *:[i64] } 1988:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32) => (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)) |
| 71901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN), |
| 71902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71903 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 71904 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32 |
| 71905 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71906 | GIR_RootConstrainSelectedInstOperands, |
| 71907 | // GIR_Coverage, 7970, |
| 71908 | GIR_EraseRootFromParent_Done, |
| 71909 | // Label 3957: @228633 |
| 71910 | GIM_Try, /*On fail goto*//*Label 3958*/ GIMT_Encode4(228724), // Rule ID 7971 // |
| 71911 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_add_gs_reg_rtn), |
| 71912 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71913 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 71914 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 71915 | // MIs[0] offset32 |
| 71916 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 71917 | // (intrinsic_w_chain:{ *:[i32] } 1988:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32) => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_ADD_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 71918 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 71919 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 71920 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_ADD_GS_REG_RTN), |
| 71921 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71922 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 71923 | GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32 |
| 71924 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71925 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 71926 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71927 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71928 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 71929 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 71932 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 71933 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 71934 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 71935 | // GIR_Coverage, 7971, |
| 71936 | GIR_EraseRootFromParent_Done, |
| 71937 | // Label 3958: @228724 |
| 71938 | GIM_Try, /*On fail goto*//*Label 3959*/ GIMT_Encode4(228766), // Rule ID 7972 // |
| 71939 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn), |
| 71940 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 71941 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 71942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 71943 | // MIs[0] offset32 |
| 71944 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 71945 | // (intrinsic_w_chain:{ *:[i64] } 2002:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32) => (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)) |
| 71946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN), |
| 71947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 71948 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 71949 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32 |
| 71950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71951 | GIR_RootConstrainSelectedInstOperands, |
| 71952 | // GIR_Coverage, 7972, |
| 71953 | GIR_EraseRootFromParent_Done, |
| 71954 | // Label 3959: @228766 |
| 71955 | GIM_Try, /*On fail goto*//*Label 3960*/ GIMT_Encode4(228857), // Rule ID 7973 // |
| 71956 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_sub_gs_reg_rtn), |
| 71957 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71958 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 71959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 71960 | // MIs[0] offset32 |
| 71961 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 71962 | // (intrinsic_w_chain:{ *:[i32] } 2002:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset32) => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i64] } (DS_SUB_GS_REG_RTN:{ *:[i64] } VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$offset32)), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 71963 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 71964 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 71965 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SUB_GS_REG_RTN), |
| 71966 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71967 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src |
| 71968 | GIR_CustomOperandRenderer, /*InsnID*/2, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset32 |
| 71969 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 71971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 71973 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 71974 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 71975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 71976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 71977 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 71978 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 71979 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 71980 | // GIR_Coverage, 7973, |
| 71981 | GIR_EraseRootFromParent_Done, |
| 71982 | // Label 3960: @228857 |
| 71983 | GIM_Try, /*On fail goto*//*Label 3961*/ GIMT_Encode4(228921), // Rule ID 3407 // |
| 71984 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts_isGFX12Plus), |
| 71985 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 71986 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 71987 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 71988 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 71989 | GIM_CheckHasNoUse, /*MI*/0, |
| 71990 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 71991 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 71992 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_noret_flat_addrspace>> => (FLAT_ATOMIC_COND_SUB_U32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 71993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32), |
| 71994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 71995 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 71996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 71997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 71998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 71999 | GIR_RootConstrainSelectedInstOperands, |
| 72000 | // GIR_Coverage, 3407, |
| 72001 | GIR_EraseRootFromParent_Done, |
| 72002 | // Label 3961: @228921 |
| 72003 | GIM_Try, /*On fail goto*//*Label 3962*/ GIMT_Encode4(228977), // Rule ID 3753 // |
| 72004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 72005 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin), |
| 72006 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72007 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72008 | GIM_CheckHasNoUse, /*MI*/0, |
| 72009 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72011 | // (intrinsic_w_chain:{ *:[f32] } 2021:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_noret>> => (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN), |
| 72013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72014 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72018 | GIR_RootConstrainSelectedInstOperands, |
| 72019 | // GIR_Coverage, 3753, |
| 72020 | GIR_EraseRootFromParent_Done, |
| 72021 | // Label 3962: @228977 |
| 72022 | GIM_Try, /*On fail goto*//*Label 3963*/ GIMT_Encode4(229033), // Rule ID 3755 // |
| 72023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 72024 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax), |
| 72025 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72026 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72027 | GIM_CheckHasNoUse, /*MI*/0, |
| 72028 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72029 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72030 | // (intrinsic_w_chain:{ *:[f32] } 2019:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_noret>> => (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX), |
| 72032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72033 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72037 | GIR_RootConstrainSelectedInstOperands, |
| 72038 | // GIR_Coverage, 3755, |
| 72039 | GIR_EraseRootFromParent_Done, |
| 72040 | // Label 3963: @229033 |
| 72041 | GIM_Try, /*On fail goto*//*Label 3964*/ GIMT_Encode4(229089), // Rule ID 3765 // |
| 72042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 72043 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num), |
| 72044 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72046 | GIM_CheckHasNoUse, /*MI*/0, |
| 72047 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72049 | // (intrinsic_w_chain:{ *:[f32] } 2022:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_num_noret>> => (FLAT_ATOMIC_FMIN VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN), |
| 72051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72052 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72055 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72056 | GIR_RootConstrainSelectedInstOperands, |
| 72057 | // GIR_Coverage, 3765, |
| 72058 | GIR_EraseRootFromParent_Done, |
| 72059 | // Label 3964: @229089 |
| 72060 | GIM_Try, /*On fail goto*//*Label 3965*/ GIMT_Encode4(229145), // Rule ID 3767 // |
| 72061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 72062 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num), |
| 72063 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72064 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72065 | GIM_CheckHasNoUse, /*MI*/0, |
| 72066 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72068 | // (intrinsic_w_chain:{ *:[f32] } 2020:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_num_noret>> => (FLAT_ATOMIC_FMAX VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX), |
| 72070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72071 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72074 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72075 | GIR_RootConstrainSelectedInstOperands, |
| 72076 | // GIR_Coverage, 3767, |
| 72077 | GIR_EraseRootFromParent_Done, |
| 72078 | // Label 3965: @229145 |
| 72079 | GIM_Try, /*On fail goto*//*Label 3966*/ GIMT_Encode4(229201), // Rule ID 3811 // |
| 72080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGlobalInsts), |
| 72081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin), |
| 72082 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72083 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72084 | GIM_CheckHasNoUse, /*MI*/0, |
| 72085 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72086 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72087 | // (intrinsic_w_chain:{ *:[f64] } 2021:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmin_noret>> => (FLAT_ATOMIC_MIN_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64), |
| 72089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72090 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72094 | GIR_RootConstrainSelectedInstOperands, |
| 72095 | // GIR_Coverage, 3811, |
| 72096 | GIR_EraseRootFromParent_Done, |
| 72097 | // Label 3966: @229201 |
| 72098 | GIM_Try, /*On fail goto*//*Label 3967*/ GIMT_Encode4(229257), // Rule ID 3813 // |
| 72099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGlobalInsts), |
| 72100 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax), |
| 72101 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72102 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72103 | GIM_CheckHasNoUse, /*MI*/0, |
| 72104 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72106 | // (intrinsic_w_chain:{ *:[f64] } 2019:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fmax_noret>> => (FLAT_ATOMIC_MAX_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64), |
| 72108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72109 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72112 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72113 | GIR_RootConstrainSelectedInstOperands, |
| 72114 | // GIR_Coverage, 3813, |
| 72115 | GIR_EraseRootFromParent_Done, |
| 72116 | // Label 3967: @229257 |
| 72117 | GIM_Try, /*On fail goto*//*Label 3968*/ GIMT_Encode4(229313), // Rule ID 3829 // |
| 72118 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 72119 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72120 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72122 | GIM_CheckHasNoUse, /*MI*/0, |
| 72123 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72125 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret>> => (FLAT_ATOMIC_ADD_F64 VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64), |
| 72127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72128 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72132 | GIR_RootConstrainSelectedInstOperands, |
| 72133 | // GIR_Coverage, 3829, |
| 72134 | GIR_EraseRootFromParent_Done, |
| 72135 | // Label 3968: @229313 |
| 72136 | GIM_Try, /*On fail goto*//*Label 3969*/ GIMT_Encode4(229369), // Rule ID 3833 // |
| 72137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst), |
| 72138 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72139 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72140 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72141 | GIM_CheckHasNoUse, /*MI*/0, |
| 72142 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72144 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret>> => (FLAT_ATOMIC_ADD_F32 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32), |
| 72146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72147 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72151 | GIR_RootConstrainSelectedInstOperands, |
| 72152 | // GIR_Coverage, 3833, |
| 72153 | GIR_EraseRootFromParent_Done, |
| 72154 | // Label 3969: @229369 |
| 72155 | GIM_Try, /*On fail goto*//*Label 3970*/ GIMT_Encode4(229425), // Rule ID 3835 // |
| 72156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 72157 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72158 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72159 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 72160 | GIM_CheckHasNoUse, /*MI*/0, |
| 72161 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72163 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_noret>> => (FLAT_ATOMIC_PK_ADD_F16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 72164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16), |
| 72165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72166 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72169 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72170 | GIR_RootConstrainSelectedInstOperands, |
| 72171 | // GIR_Coverage, 3835, |
| 72172 | GIR_EraseRootFromParent_Done, |
| 72173 | // Label 3970: @229425 |
| 72174 | GIM_Try, /*On fail goto*//*Label 3971*/ GIMT_Encode4(229481), // Rule ID 3837 // |
| 72175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 72176 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd_v2bf16), |
| 72177 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72178 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 72179 | GIM_CheckHasNoUse, /*MI*/0, |
| 72180 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72181 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72182 | // (intrinsic_w_chain:{ *:[v2i16] } 2018:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data)<<P:Predicate_int_amdgcn_flat_atomic_fadd_v2bf16_noret>> => (FLAT_ATOMIC_PK_ADD_BF16 VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 72183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16), |
| 72184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72185 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72188 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72189 | GIR_RootConstrainSelectedInstOperands, |
| 72190 | // GIR_Coverage, 3837, |
| 72191 | GIR_EraseRootFromParent_Done, |
| 72192 | // Label 3971: @229481 |
| 72193 | GIM_Try, /*On fail goto*//*Label 3972*/ GIMT_Encode4(229549), // Rule ID 3406 // |
| 72194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace_isGFX12Plus), |
| 72195 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_atomic_cond_sub_u32), |
| 72196 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72197 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72198 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 72199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72200 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72202 | // (intrinsic_w_chain:{ *:[i32] } 1953:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data)<<P:Predicate_int_amdgcn_atomic_cond_sub_u32_flat_addrspace>> => (FLAT_ATOMIC_COND_SUB_U32_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[i32] }:$data, ?:{ *:[i32] }:$offset) |
| 72203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_COND_SUB_U32_RTN), |
| 72204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72206 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72210 | GIR_RootConstrainSelectedInstOperands, |
| 72211 | // GIR_Coverage, 3406, |
| 72212 | GIR_EraseRootFromParent_Done, |
| 72213 | // Label 3972: @229549 |
| 72214 | GIM_Try, /*On fail goto*//*Label 3973*/ GIMT_Encode4(229609), // Rule ID 3752 // |
| 72215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 72216 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin), |
| 72217 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72218 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72220 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72221 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72222 | // (intrinsic_w_chain:{ *:[f32] } 2021:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN), |
| 72224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72226 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72230 | GIR_RootConstrainSelectedInstOperands, |
| 72231 | // GIR_Coverage, 3752, |
| 72232 | GIR_EraseRootFromParent_Done, |
| 72233 | // Label 3973: @229609 |
| 72234 | GIM_Try, /*On fail goto*//*Label 3974*/ GIMT_Encode4(229669), // Rule ID 3754 // |
| 72235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32FlatInsts_HasFlatGlobalInsts), |
| 72236 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax), |
| 72237 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72238 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72240 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72242 | // (intrinsic_w_chain:{ *:[f32] } 2019:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN), |
| 72244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72246 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72250 | GIR_RootConstrainSelectedInstOperands, |
| 72251 | // GIR_Coverage, 3754, |
| 72252 | GIR_EraseRootFromParent_Done, |
| 72253 | // Label 3974: @229669 |
| 72254 | GIM_Try, /*On fail goto*//*Label 3975*/ GIMT_Encode4(229729), // Rule ID 3764 // |
| 72255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 72256 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin_num), |
| 72257 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72258 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72260 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72262 | // (intrinsic_w_chain:{ *:[f32] } 2022:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (FLAT_ATOMIC_FMIN_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMIN_RTN), |
| 72264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72266 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72269 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72270 | GIR_RootConstrainSelectedInstOperands, |
| 72271 | // GIR_Coverage, 3764, |
| 72272 | GIR_EraseRootFromParent_Done, |
| 72273 | // Label 3975: @229729 |
| 72274 | GIM_Try, /*On fail goto*//*Label 3976*/ GIMT_Encode4(229789), // Rule ID 3766 // |
| 72275 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 72276 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax_num), |
| 72277 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72278 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72280 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72281 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72282 | // (intrinsic_w_chain:{ *:[f32] } 2020:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (FLAT_ATOMIC_FMAX_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_FMAX_RTN), |
| 72284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72286 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72289 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72290 | GIR_RootConstrainSelectedInstOperands, |
| 72291 | // GIR_Coverage, 3766, |
| 72292 | GIR_EraseRootFromParent_Done, |
| 72293 | // Label 3976: @229789 |
| 72294 | GIM_Try, /*On fail goto*//*Label 3977*/ GIMT_Encode4(229849), // Rule ID 3810 // |
| 72295 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGlobalInsts), |
| 72296 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmin), |
| 72297 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72298 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 72300 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72302 | // (intrinsic_w_chain:{ *:[f64] } 2021:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (FLAT_ATOMIC_MIN_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MIN_F64_RTN), |
| 72304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72306 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72309 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72310 | GIR_RootConstrainSelectedInstOperands, |
| 72311 | // GIR_Coverage, 3810, |
| 72312 | GIR_EraseRootFromParent_Done, |
| 72313 | // Label 3977: @229849 |
| 72314 | GIM_Try, /*On fail goto*//*Label 3978*/ GIMT_Encode4(229909), // Rule ID 3812 // |
| 72315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64FlatInsts_HasFlatGlobalInsts), |
| 72316 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fmax), |
| 72317 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72318 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 72320 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72322 | // (intrinsic_w_chain:{ *:[f64] } 2019:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (FLAT_ATOMIC_MAX_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_MAX_F64_RTN), |
| 72324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72326 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72330 | GIR_RootConstrainSelectedInstOperands, |
| 72331 | // GIR_Coverage, 3812, |
| 72332 | GIR_EraseRootFromParent_Done, |
| 72333 | // Label 3978: @229909 |
| 72334 | GIM_Try, /*On fail goto*//*Label 3979*/ GIMT_Encode4(229969), // Rule ID 3828 // |
| 72335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 72336 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72337 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 72338 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 72339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 72340 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72342 | // (intrinsic_w_chain:{ *:[f64] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f64:{ *:[f64] }:$data) => (FLAT_ATOMIC_ADD_F64_RTN:{ *:[f64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[f64] }:$data, ?:{ *:[i32] }:$offset) |
| 72343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F64_RTN), |
| 72344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72346 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72350 | GIR_RootConstrainSelectedInstOperands, |
| 72351 | // GIR_Coverage, 3828, |
| 72352 | GIR_EraseRootFromParent_Done, |
| 72353 | // Label 3979: @229969 |
| 72354 | GIM_Try, /*On fail goto*//*Label 3980*/ GIMT_Encode4(230029), // Rule ID 3832 // |
| 72355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAtomicFaddF32Inst), |
| 72356 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72357 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72358 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72359 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72360 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72362 | // (intrinsic_w_chain:{ *:[f32] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), f32:{ *:[f32] }:$data) => (FLAT_ATOMIC_ADD_F32_RTN:{ *:[f32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[f32] }:$data, ?:{ *:[i32] }:$offset) |
| 72363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_ADD_F32_RTN), |
| 72364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72366 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72369 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72370 | GIR_RootConstrainSelectedInstOperands, |
| 72371 | // GIR_Coverage, 3832, |
| 72372 | GIR_EraseRootFromParent_Done, |
| 72373 | // Label 3980: @230029 |
| 72374 | GIM_Try, /*On fail goto*//*Label 3981*/ GIMT_Encode4(230089), // Rule ID 3834 // |
| 72375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 72376 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd), |
| 72377 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72378 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 72379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72380 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72381 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72382 | // (intrinsic_w_chain:{ *:[v2f16] } 2017:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2f16:{ *:[v2f16] }:$data) => (FLAT_ATOMIC_PK_ADD_F16_RTN:{ *:[v2f16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2f16] }:$data, ?:{ *:[i32] }:$offset) |
| 72383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_F16_RTN), |
| 72384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72386 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72389 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72390 | GIR_RootConstrainSelectedInstOperands, |
| 72391 | // GIR_Coverage, 3834, |
| 72392 | GIR_EraseRootFromParent_Done, |
| 72393 | // Label 3981: @230089 |
| 72394 | GIM_Try, /*On fail goto*//*Label 3982*/ GIMT_Encode4(230149), // Rule ID 3836 // |
| 72395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFlatPkAdd16Insts), |
| 72396 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_flat_atomic_fadd_v2bf16), |
| 72397 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72398 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 72399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 72400 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 72401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 72402 | // (intrinsic_w_chain:{ *:[v2i16] } 2018:{ *:[iPTR] }, (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i16:{ *:[v2i16] }:$data) => (FLAT_ATOMIC_PK_ADD_BF16_RTN:{ *:[v2i16] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15876:{ *:[v2i16] }:$data, ?:{ *:[i32] }:$offset) |
| 72403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_PK_ADD_BF16_RTN), |
| 72404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 72406 | GIR_RootToRootCopy, /*OpIdx*/3, // data |
| 72407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 72408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72410 | GIR_RootConstrainSelectedInstOperands, |
| 72411 | // GIR_Coverage, 3836, |
| 72412 | GIR_EraseRootFromParent_Done, |
| 72413 | // Label 3982: @230149 |
| 72414 | GIM_Reject, |
| 72415 | // Label 3886: @230150 |
| 72416 | GIM_Try, /*On fail goto*//*Label 3983*/ GIMT_Encode4(230484), |
| 72417 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 72418 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_compr), |
| 72419 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 72420 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16, |
| 72421 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72422 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72423 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72424 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72425 | GIM_Try, /*On fail goto*//*Label 3984*/ GIMT_Encode4(230258), // Rule ID 6607 // |
| 72426 | // MIs[0] Operand 5 |
| 72427 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 72428 | // MIs[0] vm |
| 72429 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 72430 | // (intrinsic_void 2008:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 72432 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 72433 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72434 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72435 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 72436 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72437 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72438 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP), |
| 72440 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72441 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72442 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72443 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 72445 | GIR_RootToRootCopy, /*OpIdx*/6, // vm |
| 72446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72447 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72449 | GIR_RootConstrainSelectedInstOperands, |
| 72450 | // GIR_Coverage, 6607, |
| 72451 | GIR_EraseRootFromParent_Done, |
| 72452 | // Label 3984: @230258 |
| 72453 | GIM_Try, /*On fail goto*//*Label 3985*/ GIMT_Encode4(230333), // Rule ID 6608 // |
| 72454 | // MIs[0] Operand 5 |
| 72455 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 72456 | // MIs[0] vm |
| 72457 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 72458 | // (intrinsic_void 2008:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2i16] }:$src0, ExpSrc1:{ *:[v2i16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72459 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 72460 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 72461 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72462 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72463 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 72464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72466 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72467 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE), |
| 72468 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72469 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72470 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72471 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72472 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 72473 | GIR_RootToRootCopy, /*OpIdx*/6, // vm |
| 72474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72475 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72476 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72477 | GIR_RootConstrainSelectedInstOperands, |
| 72478 | // GIR_Coverage, 6608, |
| 72479 | GIR_EraseRootFromParent_Done, |
| 72480 | // Label 3985: @230333 |
| 72481 | GIM_Try, /*On fail goto*//*Label 3986*/ GIMT_Encode4(230408), // Rule ID 6609 // |
| 72482 | // MIs[0] Operand 5 |
| 72483 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 72484 | // MIs[0] vm |
| 72485 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 72486 | // (intrinsic_void 2008:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 72488 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 72489 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72490 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72491 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 72492 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72493 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72494 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP), |
| 72496 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72497 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72498 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72500 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 72501 | GIR_RootToRootCopy, /*OpIdx*/6, // vm |
| 72502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72503 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72505 | GIR_RootConstrainSelectedInstOperands, |
| 72506 | // GIR_Coverage, 6609, |
| 72507 | GIR_EraseRootFromParent_Done, |
| 72508 | // Label 3986: @230408 |
| 72509 | GIM_Try, /*On fail goto*//*Label 3987*/ GIMT_Encode4(230483), // Rule ID 6610 // |
| 72510 | // MIs[0] Operand 5 |
| 72511 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(-1), |
| 72512 | // MIs[0] vm |
| 72513 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 72514 | // (intrinsic_void 2008:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[v2f16] }:$src0, ExpSrc1:{ *:[v2f16] }:$src1, (IMPLICIT_DEF:{ *:[i16] }), (IMPLICIT_DEF:{ *:[i16] }), (timm:{ *:[i1] }):$vm, 1:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 72516 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 72517 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72518 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 72520 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 72521 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 72522 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 72523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE), |
| 72524 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72525 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72526 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72527 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 72528 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 72529 | GIR_RootToRootCopy, /*OpIdx*/6, // vm |
| 72530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 72531 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72532 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72533 | GIR_RootConstrainSelectedInstOperands, |
| 72534 | // GIR_Coverage, 6610, |
| 72535 | GIR_EraseRootFromParent_Done, |
| 72536 | // Label 3987: @230483 |
| 72537 | GIM_Reject, |
| 72538 | // Label 3983: @230484 |
| 72539 | GIM_Try, /*On fail goto*//*Label 3988*/ GIMT_Encode4(231241), |
| 72540 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/9, |
| 72541 | GIM_Try, /*On fail goto*//*Label 3989*/ GIMT_Encode4(230576), // Rule ID 6599 // |
| 72542 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp), |
| 72543 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72544 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72545 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72546 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72547 | // MIs[0] tgt |
| 72548 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72549 | // MIs[0] en |
| 72550 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72551 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72552 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72553 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72554 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72555 | // MIs[0] Operand 7 |
| 72556 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 72557 | // MIs[0] vm |
| 72558 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 72559 | // (intrinsic_void 2007:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP), |
| 72561 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72562 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72563 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72564 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72565 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72566 | GIR_RootToRootCopy, /*OpIdx*/8, // vm |
| 72567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72568 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72570 | GIR_RootConstrainSelectedInstOperands, |
| 72571 | // GIR_Coverage, 6599, |
| 72572 | GIR_EraseRootFromParent_Done, |
| 72573 | // Label 3989: @230576 |
| 72574 | GIM_Try, /*On fail goto*//*Label 3990*/ GIMT_Encode4(230660), // Rule ID 6600 // |
| 72575 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp), |
| 72576 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72577 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72578 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72579 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72580 | // MIs[0] tgt |
| 72581 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72582 | // MIs[0] en |
| 72583 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72584 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72585 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72586 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72587 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72588 | // MIs[0] Operand 7 |
| 72589 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1), |
| 72590 | // MIs[0] vm |
| 72591 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 72592 | // (intrinsic_void 2007:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE), |
| 72594 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72595 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72596 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72597 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72598 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72599 | GIR_RootToRootCopy, /*OpIdx*/8, // vm |
| 72600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72601 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72602 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72603 | GIR_RootConstrainSelectedInstOperands, |
| 72604 | // GIR_Coverage, 6600, |
| 72605 | GIR_EraseRootFromParent_Done, |
| 72606 | // Label 3990: @230660 |
| 72607 | GIM_Try, /*On fail goto*//*Label 3991*/ GIMT_Encode4(230744), // Rule ID 6601 // |
| 72608 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp), |
| 72609 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72610 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72611 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72612 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72613 | // MIs[0] tgt |
| 72614 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72615 | // MIs[0] en |
| 72616 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72617 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72618 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72619 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72620 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72621 | // MIs[0] Operand 7 |
| 72622 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 72623 | // MIs[0] vm |
| 72624 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 72625 | // (intrinsic_void 2007:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP), |
| 72627 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72628 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72629 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72630 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72631 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72632 | GIR_RootToRootCopy, /*OpIdx*/8, // vm |
| 72633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72634 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72635 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72636 | GIR_RootConstrainSelectedInstOperands, |
| 72637 | // GIR_Coverage, 6601, |
| 72638 | GIR_EraseRootFromParent_Done, |
| 72639 | // Label 3991: @230744 |
| 72640 | GIM_Try, /*On fail goto*//*Label 3992*/ GIMT_Encode4(230828), // Rule ID 6602 // |
| 72641 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp), |
| 72642 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72643 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72644 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72645 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72646 | // MIs[0] tgt |
| 72647 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72648 | // MIs[0] en |
| 72649 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72650 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72651 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72652 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72653 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72654 | // MIs[0] Operand 7 |
| 72655 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1), |
| 72656 | // MIs[0] vm |
| 72657 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 72658 | // (intrinsic_void 2007:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, (timm:{ *:[i1] }):$vm) => (EXP_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, (timm:{ *:[i1] }):$vm, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_DONE), |
| 72660 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72661 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72662 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72663 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72664 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72665 | GIR_RootToRootCopy, /*OpIdx*/8, // vm |
| 72666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72667 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72669 | GIR_RootConstrainSelectedInstOperands, |
| 72670 | // GIR_Coverage, 6602, |
| 72671 | GIR_EraseRootFromParent_Done, |
| 72672 | // Label 3992: @230828 |
| 72673 | GIM_Try, /*On fail goto*//*Label 3993*/ GIMT_Encode4(230931), // Rule ID 6603 // |
| 72674 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row), |
| 72675 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72676 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72677 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72678 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72679 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 72680 | // MIs[0] tgt |
| 72681 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72682 | // MIs[0] en |
| 72683 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72684 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72685 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72686 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72687 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72688 | // MIs[0] Operand 7 |
| 72689 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 72690 | GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 72691 | // (intrinsic_void 2009:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] }) => (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 72693 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 72694 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0 |
| 72695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW), |
| 72696 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72697 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72698 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72699 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72700 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72703 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72704 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72705 | GIR_RootConstrainSelectedInstOperands, |
| 72706 | // GIR_Coverage, 6603, |
| 72707 | GIR_EraseRootFromParent_Done, |
| 72708 | // Label 3993: @230931 |
| 72709 | GIM_Try, /*On fail goto*//*Label 3994*/ GIMT_Encode4(231034), // Rule ID 6604 // |
| 72710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row), |
| 72711 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72712 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72713 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72714 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72715 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 72716 | // MIs[0] tgt |
| 72717 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72718 | // MIs[0] en |
| 72719 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72720 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72721 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72722 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72723 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72724 | // MIs[0] Operand 7 |
| 72725 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1), |
| 72726 | GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 72727 | // (intrinsic_void 2009:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] }) => (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[i32] }:$src0, ExpSrc1:{ *:[i32] }:$src1, ExpSrc2:{ *:[i32] }:$src2, ExpSrc3:{ *:[i32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72728 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 72729 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 72730 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0 |
| 72731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE), |
| 72732 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72733 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72734 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72735 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72736 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72739 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72741 | GIR_RootConstrainSelectedInstOperands, |
| 72742 | // GIR_Coverage, 6604, |
| 72743 | GIR_EraseRootFromParent_Done, |
| 72744 | // Label 3994: @231034 |
| 72745 | GIM_Try, /*On fail goto*//*Label 3995*/ GIMT_Encode4(231137), // Rule ID 6605 // |
| 72746 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row), |
| 72747 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72748 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72749 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72750 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72751 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 72752 | // MIs[0] tgt |
| 72753 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72754 | // MIs[0] en |
| 72755 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72756 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72757 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72758 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72759 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72760 | // MIs[0] Operand 7 |
| 72761 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 72762 | GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 72763 | // (intrinsic_void 2009:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, M0:{ *:[i32] }) => (EXP_ROW (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72764 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 72765 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 72766 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0 |
| 72767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW), |
| 72768 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72769 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72770 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72771 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72772 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72775 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72776 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72777 | GIR_RootConstrainSelectedInstOperands, |
| 72778 | // GIR_Coverage, 6605, |
| 72779 | GIR_EraseRootFromParent_Done, |
| 72780 | // Label 3995: @231137 |
| 72781 | GIM_Try, /*On fail goto*//*Label 3996*/ GIMT_Encode4(231240), // Rule ID 6606 // |
| 72782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_exp_row), |
| 72783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 72784 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 72785 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 72786 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 72787 | GIM_RootCheckType, /*Op*/8, /*Type*/GILLT_s32, |
| 72788 | // MIs[0] tgt |
| 72789 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 72790 | // MIs[0] en |
| 72791 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 72792 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72793 | GIM_RootCheckRegBankForClass, /*Op*/4, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72794 | GIM_RootCheckRegBankForClass, /*Op*/5, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72795 | GIM_RootCheckRegBankForClass, /*Op*/6, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72796 | // MIs[0] Operand 7 |
| 72797 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(-1), |
| 72798 | GIM_RootCheckRegBankForClass, /*Op*/8, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 72799 | // (intrinsic_void 2009:{ *:[iPTR] }, (timm:{ *:[i32] }):$tgt, (timm:{ *:[i32] }):$en, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, -1:{ *:[i1] }, M0:{ *:[i32] }) => (EXP_ROW_DONE (timm:{ *:[i32] }):$tgt, ExpSrc0:{ *:[f32] }:$src0, ExpSrc1:{ *:[f32] }:$src1, ExpSrc2:{ *:[f32] }:$src2, ExpSrc3:{ *:[f32] }:$src3, 0:{ *:[i1] }, 0:{ *:[i1] }, (timm:{ *:[i32] }):$en) |
| 72800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 72801 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 72802 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, // M0 |
| 72803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::EXP_ROW_DONE), |
| 72804 | GIR_RootToRootCopy, /*OpIdx*/1, // tgt |
| 72805 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 72806 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 72807 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 72808 | GIR_RootToRootCopy, /*OpIdx*/6, // src3 |
| 72809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 72811 | GIR_RootToRootCopy, /*OpIdx*/2, // en |
| 72812 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 72813 | GIR_RootConstrainSelectedInstOperands, |
| 72814 | // GIR_Coverage, 6606, |
| 72815 | GIR_EraseRootFromParent_Done, |
| 72816 | // Label 3996: @231240 |
| 72817 | GIM_Reject, |
| 72818 | // Label 3988: @231241 |
| 72819 | GIM_Reject, |
| 72820 | // Label 38: @231242 |
| 72821 | GIM_Try, /*On fail goto*//*Label 3997*/ GIMT_Encode4(232108), |
| 72822 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 72823 | GIM_Try, /*On fail goto*//*Label 3998*/ GIMT_Encode4(231289), // Rule ID 7297 // |
| 72824 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72825 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72826 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 72829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 72830 | // MIs[1] Operand 1 |
| 72831 | // No operand predicates |
| 72832 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 72833 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, (imm:{ *:[i32] }):$src) => (S_MOV_B32:{ *:[i32] } SReg_32:{ *:[i32] }:$src) |
| 72834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 72835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 72836 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 72837 | GIR_RootConstrainSelectedInstOperands, |
| 72838 | // GIR_Coverage, 7297, |
| 72839 | GIR_EraseRootFromParent_Done, |
| 72840 | // Label 3998: @231289 |
| 72841 | GIM_Try, /*On fail goto*//*Label 3999*/ GIMT_Encode4(231322), // Rule ID 2049 // |
| 72842 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72843 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72844 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72846 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72847 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0) |
| 72848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72850 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72851 | GIR_RootConstrainSelectedInstOperands, |
| 72852 | // GIR_Coverage, 2049, |
| 72853 | GIR_EraseRootFromParent_Done, |
| 72854 | // Label 3999: @231322 |
| 72855 | GIM_Try, /*On fail goto*//*Label 4000*/ GIMT_Encode4(231355), // Rule ID 2050 // |
| 72856 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72857 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72858 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72860 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72861 | // (intrinsic_wo_chain:{ *:[f32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[f32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[f32] } VRegOrLdsSrc_32:{ *:[f32] }:$src0) |
| 72862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72864 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72865 | GIR_RootConstrainSelectedInstOperands, |
| 72866 | // GIR_Coverage, 2050, |
| 72867 | GIR_EraseRootFromParent_Done, |
| 72868 | // Label 4000: @231355 |
| 72869 | GIM_Try, /*On fail goto*//*Label 4001*/ GIMT_Encode4(231388), // Rule ID 2051 // |
| 72870 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72871 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72872 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 72873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72874 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72875 | // (intrinsic_wo_chain:{ *:[v2i16] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[v2i16] }:$src0) => (V_READFIRSTLANE_B32:{ *:[v2i16] } VRegOrLdsSrc_32:{ *:[v2i16] }:$src0) |
| 72876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72877 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72878 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72879 | GIR_RootConstrainSelectedInstOperands, |
| 72880 | // GIR_Coverage, 2051, |
| 72881 | GIR_EraseRootFromParent_Done, |
| 72882 | // Label 4001: @231388 |
| 72883 | GIM_Try, /*On fail goto*//*Label 4002*/ GIMT_Encode4(231421), // Rule ID 2052 // |
| 72884 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72885 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72886 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 72887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72888 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72889 | // (intrinsic_wo_chain:{ *:[v2f16] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[v2f16] }:$src0) => (V_READFIRSTLANE_B32:{ *:[v2f16] } VRegOrLdsSrc_32:{ *:[v2f16] }:$src0) |
| 72890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72892 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72893 | GIR_RootConstrainSelectedInstOperands, |
| 72894 | // GIR_Coverage, 2052, |
| 72895 | GIR_EraseRootFromParent_Done, |
| 72896 | // Label 4002: @231421 |
| 72897 | GIM_Try, /*On fail goto*//*Label 4003*/ GIMT_Encode4(231454), // Rule ID 2053 // |
| 72898 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72899 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72900 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 72901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72902 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72903 | // (intrinsic_wo_chain:{ *:[v2bf16] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[v2bf16] }:$src0) => (V_READFIRSTLANE_B32:{ *:[v2bf16] } VRegOrLdsSrc_32:{ *:[v2bf16] }:$src0) |
| 72904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72906 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72907 | GIR_RootConstrainSelectedInstOperands, |
| 72908 | // GIR_Coverage, 2053, |
| 72909 | GIR_EraseRootFromParent_Done, |
| 72910 | // Label 4003: @231454 |
| 72911 | GIM_Try, /*On fail goto*//*Label 4004*/ GIMT_Encode4(231487), // Rule ID 2054 // |
| 72912 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72913 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 72914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 72915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72916 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72917 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0) |
| 72918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72920 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72921 | GIR_RootConstrainSelectedInstOperands, |
| 72922 | // GIR_Coverage, 2054, |
| 72923 | GIR_EraseRootFromParent_Done, |
| 72924 | // Label 4004: @231487 |
| 72925 | GIM_Try, /*On fail goto*//*Label 4005*/ GIMT_Encode4(231520), // Rule ID 2055 // |
| 72926 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72927 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 72928 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 72929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72930 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72931 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0) |
| 72932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72934 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72935 | GIR_RootConstrainSelectedInstOperands, |
| 72936 | // GIR_Coverage, 2055, |
| 72937 | GIR_EraseRootFromParent_Done, |
| 72938 | // Label 4005: @231520 |
| 72939 | GIM_Try, /*On fail goto*//*Label 4006*/ GIMT_Encode4(231553), // Rule ID 2056 // |
| 72940 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72941 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 72942 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 72943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72944 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72945 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0) |
| 72946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72948 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72949 | GIR_RootConstrainSelectedInstOperands, |
| 72950 | // GIR_Coverage, 2056, |
| 72951 | GIR_EraseRootFromParent_Done, |
| 72952 | // Label 4006: @231553 |
| 72953 | GIM_Try, /*On fail goto*//*Label 4007*/ GIMT_Encode4(231586), // Rule ID 2057 // |
| 72954 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readfirstlane), |
| 72955 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 72956 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 72957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 72958 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VRegOrLds_32RegClassID), |
| 72959 | // (intrinsic_wo_chain:{ *:[i32] } 2946:{ *:[iPTR] }, VRegOrLdsSrc_32:{ *:[i32] }:$src0) => (V_READFIRSTLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0) |
| 72960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READFIRSTLANE_B32), |
| 72961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72962 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72963 | GIR_RootConstrainSelectedInstOperands, |
| 72964 | // GIR_Coverage, 2057, |
| 72965 | GIR_EraseRootFromParent_Done, |
| 72966 | // Label 4007: @231586 |
| 72967 | GIM_Try, /*On fail goto*//*Label 4008*/ GIMT_Encode4(231619), // Rule ID 2082 // |
| 72968 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 72969 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72972 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72973 | // (intrinsic_wo_chain:{ *:[i32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0) => (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0) |
| 72974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 72975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72976 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72977 | GIR_RootConstrainSelectedInstOperands, |
| 72978 | // GIR_Coverage, 2082, |
| 72979 | GIR_EraseRootFromParent_Done, |
| 72980 | // Label 4008: @231619 |
| 72981 | GIM_Try, /*On fail goto*//*Label 4009*/ GIMT_Encode4(231652), // Rule ID 2083 // |
| 72982 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 72983 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 72984 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 72985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72986 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 72987 | // (intrinsic_wo_chain:{ *:[f32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[f32] }:$src0) => (V_PERMLANE64_B32:{ *:[f32] } VRegSrc_32:{ *:[f32] }:$src0) |
| 72988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 72989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 72990 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 72991 | GIR_RootConstrainSelectedInstOperands, |
| 72992 | // GIR_Coverage, 2083, |
| 72993 | GIR_EraseRootFromParent_Done, |
| 72994 | // Label 4009: @231652 |
| 72995 | GIM_Try, /*On fail goto*//*Label 4010*/ GIMT_Encode4(231685), // Rule ID 2084 // |
| 72996 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 72997 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 72998 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 72999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73000 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73001 | // (intrinsic_wo_chain:{ *:[v2i16] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[v2i16] }:$src0) => (V_PERMLANE64_B32:{ *:[v2i16] } VRegSrc_32:{ *:[v2i16] }:$src0) |
| 73002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73004 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73005 | GIR_RootConstrainSelectedInstOperands, |
| 73006 | // GIR_Coverage, 2084, |
| 73007 | GIR_EraseRootFromParent_Done, |
| 73008 | // Label 4010: @231685 |
| 73009 | GIM_Try, /*On fail goto*//*Label 4011*/ GIMT_Encode4(231718), // Rule ID 2085 // |
| 73010 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73011 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73012 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73014 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73015 | // (intrinsic_wo_chain:{ *:[v2f16] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[v2f16] }:$src0) => (V_PERMLANE64_B32:{ *:[v2f16] } VRegSrc_32:{ *:[v2f16] }:$src0) |
| 73016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73018 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73019 | GIR_RootConstrainSelectedInstOperands, |
| 73020 | // GIR_Coverage, 2085, |
| 73021 | GIR_EraseRootFromParent_Done, |
| 73022 | // Label 4011: @231718 |
| 73023 | GIM_Try, /*On fail goto*//*Label 4012*/ GIMT_Encode4(231751), // Rule ID 2086 // |
| 73024 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73025 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73026 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73028 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73029 | // (intrinsic_wo_chain:{ *:[v2bf16] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[v2bf16] }:$src0) => (V_PERMLANE64_B32:{ *:[v2bf16] } VRegSrc_32:{ *:[v2bf16] }:$src0) |
| 73030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73032 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73033 | GIR_RootConstrainSelectedInstOperands, |
| 73034 | // GIR_Coverage, 2086, |
| 73035 | GIR_EraseRootFromParent_Done, |
| 73036 | // Label 4012: @231751 |
| 73037 | GIM_Try, /*On fail goto*//*Label 4013*/ GIMT_Encode4(231784), // Rule ID 2087 // |
| 73038 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73039 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73040 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 73041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73042 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73043 | // (intrinsic_wo_chain:{ *:[i32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0) => (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0) |
| 73044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73046 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73047 | GIR_RootConstrainSelectedInstOperands, |
| 73048 | // GIR_Coverage, 2087, |
| 73049 | GIR_EraseRootFromParent_Done, |
| 73050 | // Label 4013: @231784 |
| 73051 | GIM_Try, /*On fail goto*//*Label 4014*/ GIMT_Encode4(231817), // Rule ID 2088 // |
| 73052 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73053 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 73055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73056 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73057 | // (intrinsic_wo_chain:{ *:[i32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0) => (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0) |
| 73058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73060 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73061 | GIR_RootConstrainSelectedInstOperands, |
| 73062 | // GIR_Coverage, 2088, |
| 73063 | GIR_EraseRootFromParent_Done, |
| 73064 | // Label 4014: @231817 |
| 73065 | GIM_Try, /*On fail goto*//*Label 4015*/ GIMT_Encode4(231850), // Rule ID 2089 // |
| 73066 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73067 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73068 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 73069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73070 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73071 | // (intrinsic_wo_chain:{ *:[i32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0) => (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0) |
| 73072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73074 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73075 | GIR_RootConstrainSelectedInstOperands, |
| 73076 | // GIR_Coverage, 2089, |
| 73077 | GIR_EraseRootFromParent_Done, |
| 73078 | // Label 4015: @231850 |
| 73079 | GIM_Try, /*On fail goto*//*Label 4016*/ GIMT_Encode4(231883), // Rule ID 2090 // |
| 73080 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane64), |
| 73081 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 73083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73084 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73085 | // (intrinsic_wo_chain:{ *:[i32] } 2887:{ *:[iPTR] }, VRegSrc_32:{ *:[i32] }:$src0) => (V_PERMLANE64_B32:{ *:[i32] } VRegSrc_32:{ *:[i32] }:$src0) |
| 73086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE64_B32), |
| 73087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73088 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73089 | GIR_RootConstrainSelectedInstOperands, |
| 73090 | // GIR_Coverage, 2090, |
| 73091 | GIR_EraseRootFromParent_Done, |
| 73092 | // Label 4016: @231883 |
| 73093 | GIM_Try, /*On fail goto*//*Label 4017*/ GIMT_Encode4(231915), // Rule ID 2 // |
| 73094 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm), |
| 73095 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73096 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73098 | // (intrinsic_wo_chain:{ *:[i32] } 2997:{ *:[iPTR] }, i32:{ *:[i32] }:$src0) => (S_WQM_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0) |
| 73099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32), |
| 73100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73101 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73102 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73103 | GIR_RootConstrainSelectedInstOperands, |
| 73104 | // GIR_Coverage, 2, |
| 73105 | GIR_EraseRootFromParent_Done, |
| 73106 | // Label 4017: @231915 |
| 73107 | GIM_Try, /*On fail goto*//*Label 4018*/ GIMT_Encode4(231947), // Rule ID 3 // |
| 73108 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_wqm), |
| 73109 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73110 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 73111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 73112 | // (intrinsic_wo_chain:{ *:[i64] } 2997:{ *:[iPTR] }, i64:{ *:[i64] }:$src0) => (S_WQM_B64:{ *:[i64] }:{ *:[i1] } i64:{ *:[i64] }:$src0) |
| 73113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64), |
| 73114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73115 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73116 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73117 | GIR_RootConstrainSelectedInstOperands, |
| 73118 | // GIR_Coverage, 3, |
| 73119 | GIR_EraseRootFromParent_Done, |
| 73120 | // Label 4018: @231947 |
| 73121 | GIM_Try, /*On fail goto*//*Label 4019*/ GIMT_Encode4(231976), // Rule ID 21 // |
| 73122 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask), |
| 73123 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73124 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73126 | // (intrinsic_wo_chain:{ *:[i32] } 2976:{ *:[iPTR] }, i32:{ *:[i32] }:$src0) => (S_QUADMASK_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 73127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B32), |
| 73128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73129 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73130 | GIR_RootConstrainSelectedInstOperands, |
| 73131 | // GIR_Coverage, 21, |
| 73132 | GIR_EraseRootFromParent_Done, |
| 73133 | // Label 4019: @231976 |
| 73134 | GIM_Try, /*On fail goto*//*Label 4020*/ GIMT_Encode4(232005), // Rule ID 22 // |
| 73135 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_quadmask), |
| 73136 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73137 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 73138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 73139 | // (intrinsic_wo_chain:{ *:[i64] } 2976:{ *:[iPTR] }, i64:{ *:[i64] }:$src0) => (S_QUADMASK_B64:{ *:[i64] } i64:{ *:[i64] }:$src0) |
| 73140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_QUADMASK_B64), |
| 73141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73142 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73143 | GIR_RootConstrainSelectedInstOperands, |
| 73144 | // GIR_Coverage, 22, |
| 73145 | GIR_EraseRootFromParent_Done, |
| 73146 | // Label 4020: @232005 |
| 73147 | GIM_Try, /*On fail goto*//*Label 4021*/ GIMT_Encode4(232037), // Rule ID 24 // |
| 73148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 73149 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_s_bitreplicate), |
| 73150 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73151 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 73153 | // (intrinsic_wo_chain:{ *:[i64] } 2961:{ *:[iPTR] }, i32:{ *:[i32] }:$src0) => (S_BITREPLICATE_B64_B32:{ *:[i64] } i32:{ *:[i32] }:$src0) |
| 73154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BITREPLICATE_B64_B32), |
| 73155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73156 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73157 | GIR_RootConstrainSelectedInstOperands, |
| 73158 | // GIR_Coverage, 24, |
| 73159 | GIR_EraseRootFromParent_Done, |
| 73160 | // Label 4021: @232037 |
| 73161 | GIM_Try, /*On fail goto*//*Label 4022*/ GIMT_Encode4(232072), // Rule ID 1638 // |
| 73162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave32), |
| 73163 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote), |
| 73164 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 73165 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 73166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73167 | // (intrinsic_wo_chain:{ *:[i1] } 3123:{ *:[iPTR] }, i1:{ *:[i1] }:$src0) => (S_WQM_B32:{ *:[i1] }:{ *:[i1] } SSrc_b32:{ *:[i1] }:$src0) |
| 73168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B32), |
| 73169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73170 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73171 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73172 | GIR_RootConstrainSelectedInstOperands, |
| 73173 | // GIR_Coverage, 1638, |
| 73174 | GIR_EraseRootFromParent_Done, |
| 73175 | // Label 4022: @232072 |
| 73176 | GIM_Try, /*On fail goto*//*Label 4023*/ GIMT_Encode4(232107), // Rule ID 1639 // |
| 73177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isWave64), |
| 73178 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wqm_vote), |
| 73179 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 73180 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s1, |
| 73181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 73182 | // (intrinsic_wo_chain:{ *:[i1] } 3123:{ *:[iPTR] }, i1:{ *:[i1] }:$src0) => (S_WQM_B64:{ *:[i1] }:{ *:[i1] } SSrc_b64:{ *:[i1] }:$src0) |
| 73183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_WQM_B64), |
| 73184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73185 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73186 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73187 | GIR_RootConstrainSelectedInstOperands, |
| 73188 | // GIR_Coverage, 1639, |
| 73189 | GIR_EraseRootFromParent_Done, |
| 73190 | // Label 4023: @232107 |
| 73191 | GIM_Reject, |
| 73192 | // Label 3997: @232108 |
| 73193 | GIM_Try, /*On fail goto*//*Label 4024*/ GIMT_Encode4(233492), |
| 73194 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 73195 | GIM_Try, /*On fail goto*//*Label 4025*/ GIMT_Encode4(232168), // Rule ID 1140 // |
| 73196 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 73197 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_permute), |
| 73198 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73199 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73200 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73201 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 73202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 73203 | // (intrinsic_wo_chain:{ *:[i32] } 2001:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0) => (DS_PERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset) |
| 73204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_PERMUTE_B32), |
| 73205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr |
| 73207 | GIR_RootToRootCopy, /*OpIdx*/3, // data0 |
| 73208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 73209 | GIR_RootConstrainSelectedInstOperands, |
| 73210 | // GIR_Coverage, 1140, |
| 73211 | GIR_EraseRootFromParent_Done, |
| 73212 | // Label 4025: @232168 |
| 73213 | GIM_Try, /*On fail goto*//*Label 4026*/ GIMT_Encode4(232220), // Rule ID 1141 // |
| 73214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 73215 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_bpermute), |
| 73216 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73217 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73218 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 73220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_ds_1addr_1offset), |
| 73221 | // (intrinsic_wo_chain:{ *:[i32] } 1990:{ *:[iPTR] }, (DS1Addr1Offset:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$offset), i32:{ *:[i32] }:$data0) => (DS_BPERMUTE_B32:{ *:[i32] } i32:{ *:[i32] }:$addr, i32:{ *:[i32] }:$data0, i32:{ *:[i32] }:$offset) |
| 73222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_BPERMUTE_B32), |
| 73223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // addr |
| 73225 | GIR_RootToRootCopy, /*OpIdx*/3, // data0 |
| 73226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 73227 | GIR_RootConstrainSelectedInstOperands, |
| 73228 | // GIR_Coverage, 1141, |
| 73229 | GIR_EraseRootFromParent_Done, |
| 73230 | // Label 4026: @232220 |
| 73231 | GIM_Try, /*On fail goto*//*Label 4027*/ GIMT_Encode4(232273), // Rule ID 2105 // |
| 73232 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Only), |
| 73233 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8), |
| 73234 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73235 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73237 | // MIs[0] dpp8 |
| 73238 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 73239 | // (intrinsic_wo_chain:{ *:[i32] } 2876:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8) => (V_MOV_B32_dpp8_gfx10:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] }) |
| 73240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx10), |
| 73241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73242 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73243 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73244 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8 |
| 73245 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233), |
| 73246 | GIR_RootConstrainSelectedInstOperands, |
| 73247 | // GIR_Coverage, 2105, |
| 73248 | GIR_EraseRootFromParent_Done, |
| 73249 | // Label 4027: @232273 |
| 73250 | GIM_Try, /*On fail goto*//*Label 4028*/ GIMT_Encode4(232326), // Rule ID 2106 // |
| 73251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only), |
| 73252 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8), |
| 73253 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73254 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73256 | // MIs[0] dpp8 |
| 73257 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 73258 | // (intrinsic_wo_chain:{ *:[i32] } 2876:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8) => (V_MOV_B32_dpp8_gfx11:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] }) |
| 73259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx11), |
| 73260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73261 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73262 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73263 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8 |
| 73264 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233), |
| 73265 | GIR_RootConstrainSelectedInstOperands, |
| 73266 | // GIR_Coverage, 2106, |
| 73267 | GIR_EraseRootFromParent_Done, |
| 73268 | // Label 4028: @232326 |
| 73269 | GIM_Try, /*On fail goto*//*Label 4029*/ GIMT_Encode4(232379), // Rule ID 2107 // |
| 73270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Only), |
| 73271 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp8), |
| 73272 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73273 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73275 | // MIs[0] dpp8 |
| 73276 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 73277 | // (intrinsic_wo_chain:{ *:[i32] } 2876:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp8) => (V_MOV_B32_dpp8_gfx12:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp8), 233:{ *:[i32] }) |
| 73278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp8_gfx12), |
| 73279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73280 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73281 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73282 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp8 |
| 73283 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(233), |
| 73284 | GIR_RootConstrainSelectedInstOperands, |
| 73285 | // GIR_Coverage, 2107, |
| 73286 | GIR_EraseRootFromParent_Done, |
| 73287 | // Label 4029: @232379 |
| 73288 | GIM_Try, /*On fail goto*//*Label 4030*/ GIMT_Encode4(232420), // Rule ID 7434 // |
| 73289 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_ds_swizzle), |
| 73290 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73291 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 73293 | // MIs[0] offset16 |
| 73294 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 73295 | // (intrinsic_wo_chain:{ *:[i32] } 2003:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$offset16) => (DS_SWIZZLE_B32:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, (as_i16timm:{ *:[i16] } ?:{ *:[i32] }:$offset16), 0:{ *:[i1] }) |
| 73296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::DS_SWIZZLE_B32), |
| 73297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73298 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // offset16 |
| 73300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73301 | GIR_RootConstrainSelectedInstOperands, |
| 73302 | // GIR_Coverage, 7434, |
| 73303 | GIR_EraseRootFromParent_Done, |
| 73304 | // Label 4030: @232420 |
| 73305 | GIM_Try, /*On fail goto*//*Label 4031*/ GIMT_Encode4(232454), // Rule ID 2108 // |
| 73306 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73307 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73308 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73309 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73311 | // (intrinsic_wo_chain:{ *:[i32] } 2947:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73314 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73315 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73316 | GIR_RootConstrainSelectedInstOperands, |
| 73317 | // GIR_Coverage, 2108, |
| 73318 | GIR_EraseRootFromParent_Done, |
| 73319 | // Label 4031: @232454 |
| 73320 | GIM_Try, /*On fail goto*//*Label 4032*/ GIMT_Encode4(232488), // Rule ID 2110 // |
| 73321 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73322 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73323 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73324 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73326 | // (intrinsic_wo_chain:{ *:[f32] } 2947:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[f32] } VRegOrLdsSrc_32:{ *:[f32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73329 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73330 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73331 | GIR_RootConstrainSelectedInstOperands, |
| 73332 | // GIR_Coverage, 2110, |
| 73333 | GIR_EraseRootFromParent_Done, |
| 73334 | // Label 4032: @232488 |
| 73335 | GIM_Try, /*On fail goto*//*Label 4033*/ GIMT_Encode4(232522), // Rule ID 2112 // |
| 73336 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73337 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73339 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73341 | // (intrinsic_wo_chain:{ *:[v2i16] } 2947:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[v2i16] } VRegOrLdsSrc_32:{ *:[v2i16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73344 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73345 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73346 | GIR_RootConstrainSelectedInstOperands, |
| 73347 | // GIR_Coverage, 2112, |
| 73348 | GIR_EraseRootFromParent_Done, |
| 73349 | // Label 4033: @232522 |
| 73350 | GIM_Try, /*On fail goto*//*Label 4034*/ GIMT_Encode4(232556), // Rule ID 2114 // |
| 73351 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73352 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73353 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73354 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73356 | // (intrinsic_wo_chain:{ *:[v2f16] } 2947:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[v2f16] } VRegOrLdsSrc_32:{ *:[v2f16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73359 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73360 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73361 | GIR_RootConstrainSelectedInstOperands, |
| 73362 | // GIR_Coverage, 2114, |
| 73363 | GIR_EraseRootFromParent_Done, |
| 73364 | // Label 4034: @232556 |
| 73365 | GIM_Try, /*On fail goto*//*Label 4035*/ GIMT_Encode4(232590), // Rule ID 2116 // |
| 73366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73371 | // (intrinsic_wo_chain:{ *:[v2bf16] } 2947:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[v2bf16] } VRegOrLdsSrc_32:{ *:[v2bf16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73374 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73375 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73376 | GIR_RootConstrainSelectedInstOperands, |
| 73377 | // GIR_Coverage, 2116, |
| 73378 | GIR_EraseRootFromParent_Done, |
| 73379 | // Label 4035: @232590 |
| 73380 | GIM_Try, /*On fail goto*//*Label 4036*/ GIMT_Encode4(232624), // Rule ID 2118 // |
| 73381 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73382 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 73383 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 73384 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73386 | // (intrinsic_wo_chain:{ *:[i32] } 2947:{ *:[iPTR] }, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73389 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73390 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73391 | GIR_RootConstrainSelectedInstOperands, |
| 73392 | // GIR_Coverage, 2118, |
| 73393 | GIR_EraseRootFromParent_Done, |
| 73394 | // Label 4036: @232624 |
| 73395 | GIM_Try, /*On fail goto*//*Label 4037*/ GIMT_Encode4(232658), // Rule ID 2120 // |
| 73396 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73397 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 73398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 73399 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73401 | // (intrinsic_wo_chain:{ *:[i32] } 2947:{ *:[iPTR] }, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73404 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73405 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73406 | GIR_RootConstrainSelectedInstOperands, |
| 73407 | // GIR_Coverage, 2120, |
| 73408 | GIR_EraseRootFromParent_Done, |
| 73409 | // Label 4037: @232658 |
| 73410 | GIM_Try, /*On fail goto*//*Label 4038*/ GIMT_Encode4(232692), // Rule ID 2122 // |
| 73411 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73412 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 73413 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 73414 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73416 | // (intrinsic_wo_chain:{ *:[i32] } 2947:{ *:[iPTR] }, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73419 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73420 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73421 | GIR_RootConstrainSelectedInstOperands, |
| 73422 | // GIR_Coverage, 2122, |
| 73423 | GIR_EraseRootFromParent_Done, |
| 73424 | // Label 4038: @232692 |
| 73425 | GIM_Try, /*On fail goto*//*Label 4039*/ GIMT_Encode4(232726), // Rule ID 2124 // |
| 73426 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_readlane), |
| 73427 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 73428 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 73429 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73430 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 73431 | // (intrinsic_wo_chain:{ *:[i32] } 2947:{ *:[iPTR] }, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_READLANE_B32:{ *:[i32] } VRegOrLdsSrc_32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1) |
| 73432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_READLANE_B32), |
| 73433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73434 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 73435 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 73436 | GIR_RootConstrainSelectedInstOperands, |
| 73437 | // GIR_Coverage, 2124, |
| 73438 | GIR_EraseRootFromParent_Done, |
| 73439 | // Label 4039: @232726 |
| 73440 | GIM_Try, /*On fail goto*//*Label 4040*/ GIMT_Encode4(232763), // Rule ID 6625 // |
| 73441 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73442 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73443 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73444 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73446 | // (intrinsic_wo_chain:{ *:[i32] } 3007:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src, VSrc_b32:{ *:[i32] }:$inactive) |
| 73447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73449 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73450 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73451 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73452 | GIR_RootConstrainSelectedInstOperands, |
| 73453 | // GIR_Coverage, 6625, |
| 73454 | GIR_EraseRootFromParent_Done, |
| 73455 | // Label 4040: @232763 |
| 73456 | GIM_Try, /*On fail goto*//*Label 4041*/ GIMT_Encode4(232800), // Rule ID 6626 // |
| 73457 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73458 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73459 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73460 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73462 | // (intrinsic_wo_chain:{ *:[f32] } 3007:{ *:[iPTR] }, f32:{ *:[f32] }:$src, f32:{ *:[f32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[f32] }:{ *:[i1] } VSrc_b32:{ *:[f32] }:$src, VSrc_b32:{ *:[f32] }:$inactive) |
| 73463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73465 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73466 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73467 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73468 | GIR_RootConstrainSelectedInstOperands, |
| 73469 | // GIR_Coverage, 6626, |
| 73470 | GIR_EraseRootFromParent_Done, |
| 73471 | // Label 4041: @232800 |
| 73472 | GIM_Try, /*On fail goto*//*Label 4042*/ GIMT_Encode4(232837), // Rule ID 6627 // |
| 73473 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73474 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73475 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73476 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 73477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73478 | // (intrinsic_wo_chain:{ *:[v2i16] } 3007:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src, v2i16:{ *:[v2i16] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[v2i16] }:{ *:[i1] } VSrc_b32:{ *:[v2i16] }:$src, VSrc_b32:{ *:[v2i16] }:$inactive) |
| 73479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73480 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73481 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73482 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73483 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73484 | GIR_RootConstrainSelectedInstOperands, |
| 73485 | // GIR_Coverage, 6627, |
| 73486 | GIR_EraseRootFromParent_Done, |
| 73487 | // Label 4042: @232837 |
| 73488 | GIM_Try, /*On fail goto*//*Label 4043*/ GIMT_Encode4(232874), // Rule ID 6628 // |
| 73489 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73490 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73491 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73492 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 73493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73494 | // (intrinsic_wo_chain:{ *:[v2f16] } 3007:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src, v2f16:{ *:[v2f16] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[v2f16] }:{ *:[i1] } VSrc_b32:{ *:[v2f16] }:$src, VSrc_b32:{ *:[v2f16] }:$inactive) |
| 73495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73497 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73498 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73499 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73500 | GIR_RootConstrainSelectedInstOperands, |
| 73501 | // GIR_Coverage, 6628, |
| 73502 | GIR_EraseRootFromParent_Done, |
| 73503 | // Label 4043: @232874 |
| 73504 | GIM_Try, /*On fail goto*//*Label 4044*/ GIMT_Encode4(232911), // Rule ID 6629 // |
| 73505 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73506 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 73507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 73508 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 73509 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73510 | // (intrinsic_wo_chain:{ *:[v2bf16] } 3007:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$src, v2bf16:{ *:[v2bf16] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[v2bf16] }:{ *:[i1] } VSrc_b32:{ *:[v2bf16] }:$src, VSrc_b32:{ *:[v2bf16] }:$inactive) |
| 73511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73513 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73514 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73515 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73516 | GIR_RootConstrainSelectedInstOperands, |
| 73517 | // GIR_Coverage, 6629, |
| 73518 | GIR_EraseRootFromParent_Done, |
| 73519 | // Label 4044: @232911 |
| 73520 | GIM_Try, /*On fail goto*//*Label 4045*/ GIMT_Encode4(232948), // Rule ID 6630 // |
| 73521 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73522 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 73523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 73524 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32, |
| 73525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73526 | // (intrinsic_wo_chain:{ *:[i32] } 3007:{ *:[iPTR] }, p2:{ *:[i32] }:$src, p2:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src, VSrc_b32:{ *:[i32] }:$inactive) |
| 73527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73529 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73530 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73531 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73532 | GIR_RootConstrainSelectedInstOperands, |
| 73533 | // GIR_Coverage, 6630, |
| 73534 | GIR_EraseRootFromParent_Done, |
| 73535 | // Label 4045: @232948 |
| 73536 | GIM_Try, /*On fail goto*//*Label 4046*/ GIMT_Encode4(232985), // Rule ID 6631 // |
| 73537 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73538 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 73539 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 73540 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32, |
| 73541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73542 | // (intrinsic_wo_chain:{ *:[i32] } 3007:{ *:[iPTR] }, p3:{ *:[i32] }:$src, p3:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src, VSrc_b32:{ *:[i32] }:$inactive) |
| 73543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73545 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73546 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73547 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73548 | GIR_RootConstrainSelectedInstOperands, |
| 73549 | // GIR_Coverage, 6631, |
| 73550 | GIR_EraseRootFromParent_Done, |
| 73551 | // Label 4046: @232985 |
| 73552 | GIM_Try, /*On fail goto*//*Label 4047*/ GIMT_Encode4(233022), // Rule ID 6632 // |
| 73553 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73554 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 73555 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 73556 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32, |
| 73557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73558 | // (intrinsic_wo_chain:{ *:[i32] } 3007:{ *:[iPTR] }, p5:{ *:[i32] }:$src, p5:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src, VSrc_b32:{ *:[i32] }:$inactive) |
| 73559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73561 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73562 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73563 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73564 | GIR_RootConstrainSelectedInstOperands, |
| 73565 | // GIR_Coverage, 6632, |
| 73566 | GIR_EraseRootFromParent_Done, |
| 73567 | // Label 4047: @233022 |
| 73568 | GIM_Try, /*On fail goto*//*Label 4048*/ GIMT_Encode4(233059), // Rule ID 6633 // |
| 73569 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73570 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 73571 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 73572 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32, |
| 73573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73574 | // (intrinsic_wo_chain:{ *:[i32] } 3007:{ *:[iPTR] }, p6:{ *:[i32] }:$src, p6:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src, VSrc_b32:{ *:[i32] }:$inactive) |
| 73575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73576 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73577 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73578 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73579 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73580 | GIR_RootConstrainSelectedInstOperands, |
| 73581 | // GIR_Coverage, 6633, |
| 73582 | GIR_EraseRootFromParent_Done, |
| 73583 | // Label 4048: @233059 |
| 73584 | GIM_Try, /*On fail goto*//*Label 4049*/ GIMT_Encode4(233096), // Rule ID 6634 // |
| 73585 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73586 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 73588 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 73589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73590 | // (intrinsic_wo_chain:{ *:[i64] } 3007:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[i64] }:{ *:[i1] } VSrc_b64:{ *:[i64] }:$src, VSrc_b64:{ *:[i64] }:$inactive) |
| 73591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73593 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73594 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73595 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73596 | GIR_RootConstrainSelectedInstOperands, |
| 73597 | // GIR_Coverage, 6634, |
| 73598 | GIR_EraseRootFromParent_Done, |
| 73599 | // Label 4049: @233096 |
| 73600 | GIM_Try, /*On fail goto*//*Label 4050*/ GIMT_Encode4(233133), // Rule ID 6635 // |
| 73601 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73602 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73603 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 73604 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 73605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73606 | // (intrinsic_wo_chain:{ *:[f64] } 3007:{ *:[iPTR] }, f64:{ *:[f64] }:$src, f64:{ *:[f64] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[f64] }:{ *:[i1] } VSrc_b64:{ *:[f64] }:$src, VSrc_b64:{ *:[f64] }:$inactive) |
| 73607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73609 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73610 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73611 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73612 | GIR_RootConstrainSelectedInstOperands, |
| 73613 | // GIR_Coverage, 6635, |
| 73614 | GIR_EraseRootFromParent_Done, |
| 73615 | // Label 4050: @233133 |
| 73616 | GIM_Try, /*On fail goto*//*Label 4051*/ GIMT_Encode4(233170), // Rule ID 6636 // |
| 73617 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73618 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 73619 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 73620 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 73621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73622 | // (intrinsic_wo_chain:{ *:[v2i32] } 3007:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src, v2i32:{ *:[v2i32] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[v2i32] }:{ *:[i1] } VSrc_b64:{ *:[v2i32] }:$src, VSrc_b64:{ *:[v2i32] }:$inactive) |
| 73623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73625 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73626 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73627 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73628 | GIR_RootConstrainSelectedInstOperands, |
| 73629 | // GIR_Coverage, 6636, |
| 73630 | GIR_EraseRootFromParent_Done, |
| 73631 | // Label 4051: @233170 |
| 73632 | GIM_Try, /*On fail goto*//*Label 4052*/ GIMT_Encode4(233207), // Rule ID 6637 // |
| 73633 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73634 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 73635 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 73636 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 73637 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73638 | // (intrinsic_wo_chain:{ *:[v2f32] } 3007:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src, v2f32:{ *:[v2f32] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[v2f32] }:{ *:[i1] } VSrc_b64:{ *:[v2f32] }:$src, VSrc_b64:{ *:[v2f32] }:$inactive) |
| 73639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73641 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73642 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73643 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73644 | GIR_RootConstrainSelectedInstOperands, |
| 73645 | // GIR_Coverage, 6637, |
| 73646 | GIR_EraseRootFromParent_Done, |
| 73647 | // Label 4052: @233207 |
| 73648 | GIM_Try, /*On fail goto*//*Label 4053*/ GIMT_Encode4(233244), // Rule ID 6638 // |
| 73649 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73650 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64, |
| 73651 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 73652 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 73653 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73654 | // (intrinsic_wo_chain:{ *:[i64] } 3007:{ *:[iPTR] }, p0:{ *:[i64] }:$src, p0:{ *:[i64] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[i64] }:{ *:[i1] } VSrc_b64:{ *:[i64] }:$src, VSrc_b64:{ *:[i64] }:$inactive) |
| 73655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73657 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73658 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73659 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73660 | GIR_RootConstrainSelectedInstOperands, |
| 73661 | // GIR_Coverage, 6638, |
| 73662 | GIR_EraseRootFromParent_Done, |
| 73663 | // Label 4053: @233244 |
| 73664 | GIM_Try, /*On fail goto*//*Label 4054*/ GIMT_Encode4(233281), // Rule ID 6639 // |
| 73665 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73666 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 73667 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 73668 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 73669 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73670 | // (intrinsic_wo_chain:{ *:[v4i16] } 3007:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src, v4i16:{ *:[v4i16] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[v4i16] }:{ *:[i1] } VSrc_b64:{ *:[v4i16] }:$src, VSrc_b64:{ *:[v4i16] }:$inactive) |
| 73671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73673 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73674 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73675 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73676 | GIR_RootConstrainSelectedInstOperands, |
| 73677 | // GIR_Coverage, 6639, |
| 73678 | GIR_EraseRootFromParent_Done, |
| 73679 | // Label 4054: @233281 |
| 73680 | GIM_Try, /*On fail goto*//*Label 4055*/ GIMT_Encode4(233318), // Rule ID 6640 // |
| 73681 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73682 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 73683 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 73684 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 73685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73686 | // (intrinsic_wo_chain:{ *:[v4f16] } 3007:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src, v4f16:{ *:[v4f16] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[v4f16] }:{ *:[i1] } VSrc_b64:{ *:[v4f16] }:$src, VSrc_b64:{ *:[v4f16] }:$inactive) |
| 73687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73689 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73690 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73691 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73692 | GIR_RootConstrainSelectedInstOperands, |
| 73693 | // GIR_Coverage, 6640, |
| 73694 | GIR_EraseRootFromParent_Done, |
| 73695 | // Label 4055: @233318 |
| 73696 | GIM_Try, /*On fail goto*//*Label 4056*/ GIMT_Encode4(233355), // Rule ID 6641 // |
| 73697 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive), |
| 73698 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 73699 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 73700 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 73701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73702 | // (intrinsic_wo_chain:{ *:[v4bf16] } 3007:{ *:[iPTR] }, v4bf16:{ *:[v4bf16] }:$src, v4bf16:{ *:[v4bf16] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[v4bf16] }:{ *:[i1] } VSrc_b64:{ *:[v4bf16] }:$src, VSrc_b64:{ *:[v4bf16] }:$inactive) |
| 73703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73704 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73705 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73706 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73707 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73708 | GIR_RootConstrainSelectedInstOperands, |
| 73709 | // GIR_Coverage, 6641, |
| 73710 | GIR_EraseRootFromParent_Done, |
| 73711 | // Label 4056: @233355 |
| 73712 | GIM_Try, /*On fail goto*//*Label 4057*/ GIMT_Encode4(233392), // Rule ID 6642 // |
| 73713 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg), |
| 73714 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73715 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73716 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 73717 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 73718 | // (intrinsic_wo_chain:{ *:[i32] } 3008:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$inactive) => (V_SET_INACTIVE_B32:{ *:[i32] }:{ *:[i1] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$inactive) |
| 73719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B32), |
| 73720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73721 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73722 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73723 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73724 | GIR_RootConstrainSelectedInstOperands, |
| 73725 | // GIR_Coverage, 6642, |
| 73726 | GIR_EraseRootFromParent_Done, |
| 73727 | // Label 4057: @233392 |
| 73728 | GIM_Try, /*On fail goto*//*Label 4058*/ GIMT_Encode4(233429), // Rule ID 6643 // |
| 73729 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_set_inactive_chain_arg), |
| 73730 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 73731 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 73732 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 73733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 73734 | // (intrinsic_wo_chain:{ *:[i64] } 3008:{ *:[iPTR] }, i64:{ *:[i64] }:$src, i64:{ *:[i64] }:$inactive) => (V_SET_INACTIVE_B64:{ *:[i64] }:{ *:[i1] } VReg_64:{ *:[i64] }:$src, VReg_64:{ *:[i64] }:$inactive) |
| 73735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SET_INACTIVE_B64), |
| 73736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73737 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73738 | GIR_RootToRootCopy, /*OpIdx*/3, // inactive |
| 73739 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 73740 | GIR_RootConstrainSelectedInstOperands, |
| 73741 | // GIR_Coverage, 6643, |
| 73742 | GIR_EraseRootFromParent_Done, |
| 73743 | // Label 4058: @233429 |
| 73744 | GIM_Try, /*On fail goto*//*Label 4059*/ GIMT_Encode4(233460), // Rule ID 1112 // |
| 73745 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umin), |
| 73746 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73747 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID), |
| 73749 | // MIs[0] strategy |
| 73750 | // No operand predicates |
| 73751 | // (intrinsic_wo_chain:{ *:[i32] } 3100:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy) => (WAVE_REDUCE_UMIN_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy) |
| 73752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMIN_PSEUDO_U32), |
| 73753 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73754 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73755 | GIR_RootToRootCopy, /*OpIdx*/3, // strategy |
| 73756 | GIR_RootConstrainSelectedInstOperands, |
| 73757 | // GIR_Coverage, 1112, |
| 73758 | GIR_EraseRootFromParent_Done, |
| 73759 | // Label 4059: @233460 |
| 73760 | GIM_Try, /*On fail goto*//*Label 4060*/ GIMT_Encode4(233491), // Rule ID 1113 // |
| 73761 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wave_reduce_umax), |
| 73762 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 73763 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 73764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SGPR_32RegClassID), |
| 73765 | // MIs[0] strategy |
| 73766 | // No operand predicates |
| 73767 | // (intrinsic_wo_chain:{ *:[i32] } 3099:{ *:[iPTR] }, i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy) => (WAVE_REDUCE_UMAX_PSEUDO_U32:{ *:[i32] } i32:{ *:[i32] }:$src, i32:{ *:[i32] }:$strategy) |
| 73768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_REDUCE_UMAX_PSEUDO_U32), |
| 73769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 73770 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 73771 | GIR_RootToRootCopy, /*OpIdx*/3, // strategy |
| 73772 | GIR_RootConstrainSelectedInstOperands, |
| 73773 | // GIR_Coverage, 1113, |
| 73774 | GIR_EraseRootFromParent_Done, |
| 73775 | // Label 4060: @233491 |
| 73776 | GIM_Reject, |
| 73777 | // Label 4024: @233492 |
| 73778 | GIM_Try, /*On fail goto*//*Label 4061*/ GIMT_Encode4(235856), |
| 73779 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/5, |
| 73780 | GIM_Try, /*On fail goto*//*Label 4062*/ GIMT_Encode4(233591), // Rule ID 2390 // |
| 73781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 73782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 73784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 73785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 73786 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 73787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 73788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 73791 | // (intrinsic_wo_chain:{ *:[v8f32] } 3109:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_F16_w32_threeaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 73792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_threeaddr), |
| 73793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 73799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73802 | GIR_RootConstrainSelectedInstOperands, |
| 73803 | // GIR_Coverage, 2390, |
| 73804 | GIR_EraseRootFromParent_Done, |
| 73805 | // Label 4062: @233591 |
| 73806 | GIM_Try, /*On fail goto*//*Label 4063*/ GIMT_Encode4(233682), // Rule ID 2423 // |
| 73807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 73808 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73809 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 73810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 73811 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 73812 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 73813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 73814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73815 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 73817 | // (intrinsic_wo_chain:{ *:[v4f32] } 3109:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_F16_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 73818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_threeaddr), |
| 73819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 73825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73828 | GIR_RootConstrainSelectedInstOperands, |
| 73829 | // GIR_Coverage, 2423, |
| 73830 | GIR_EraseRootFromParent_Done, |
| 73831 | // Label 4063: @233682 |
| 73832 | GIM_Try, /*On fail goto*//*Label 4064*/ GIMT_Encode4(233775), // Rule ID 2375 // |
| 73833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 73834 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73835 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 73836 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 73837 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 73838 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 73839 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 73840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73842 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73843 | // (intrinsic_wo_chain:{ *:[v8f32] } 3109:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_F16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 73844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w32), |
| 73845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73854 | GIR_RootConstrainSelectedInstOperands, |
| 73855 | // GIR_Coverage, 2375, |
| 73856 | GIR_EraseRootFromParent_Done, |
| 73857 | // Label 4064: @233775 |
| 73858 | GIM_Try, /*On fail goto*//*Label 4065*/ GIMT_Encode4(233868), // Rule ID 2376 // |
| 73859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 73860 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 73861 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 73862 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 73863 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 73864 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 73865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 73866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73868 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73869 | // (intrinsic_wo_chain:{ *:[v8f32] } 3106:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF16_twoaddr_w32:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 73870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w32), |
| 73871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73880 | GIR_RootConstrainSelectedInstOperands, |
| 73881 | // GIR_Coverage, 2376, |
| 73882 | GIR_EraseRootFromParent_Done, |
| 73883 | // Label 4065: @233868 |
| 73884 | GIM_Try, /*On fail goto*//*Label 4066*/ GIMT_Encode4(233961), // Rule ID 2381 // |
| 73885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 73886 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73887 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 73888 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 73889 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 73890 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 73891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 73892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73894 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73895 | // (intrinsic_wo_chain:{ *:[v4f32] } 3109:{ *:[iPTR] }, (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_F16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16f16:{ *:[v16f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 73896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_twoaddr_w64), |
| 73897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73906 | GIR_RootConstrainSelectedInstOperands, |
| 73907 | // GIR_Coverage, 2381, |
| 73908 | GIR_EraseRootFromParent_Done, |
| 73909 | // Label 4066: @233961 |
| 73910 | GIM_Try, /*On fail goto*//*Label 4067*/ GIMT_Encode4(234054), // Rule ID 2382 // |
| 73911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 73912 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 73913 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 73914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 73915 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 73916 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 73917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 73918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 73921 | // (intrinsic_wo_chain:{ *:[v4f32] } 3106:{ *:[iPTR] }, (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v16i16] } v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF16_twoaddr_w64:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v16i16:{ *:[v16i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16i16:{ *:[v16i16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 73922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_twoaddr_w64), |
| 73923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73932 | GIR_RootConstrainSelectedInstOperands, |
| 73933 | // GIR_Coverage, 2382, |
| 73934 | GIR_EraseRootFromParent_Done, |
| 73935 | // Label 4067: @234054 |
| 73936 | GIM_Try, /*On fail goto*//*Label 4068*/ GIMT_Encode4(234147), // Rule ID 2389 // |
| 73937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 73938 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73939 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 73940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 73941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 73942 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 73943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 73944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73945 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods), |
| 73947 | // (intrinsic_wo_chain:{ *:[v8f32] } 3109:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 73948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w32_twoaddr), |
| 73949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73958 | GIR_RootConstrainSelectedInstOperands, |
| 73959 | // GIR_Coverage, 2389, |
| 73960 | GIR_EraseRootFromParent_Done, |
| 73961 | // Label 4068: @234147 |
| 73962 | GIM_Try, /*On fail goto*//*Label 4069*/ GIMT_Encode4(234240), // Rule ID 2422 // |
| 73963 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 73964 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_f16), |
| 73965 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 73966 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 73967 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 73968 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 73969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 73970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73971 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 73972 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamods), |
| 73973 | // (intrinsic_wo_chain:{ *:[v4f32] } 3109:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 73974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_F16_w64_twoaddr), |
| 73975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 73976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 73977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 73978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 73979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 73980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 73981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 73982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 73984 | GIR_RootConstrainSelectedInstOperands, |
| 73985 | // GIR_Coverage, 2422, |
| 73986 | GIR_EraseRootFromParent_Done, |
| 73987 | // Label 4069: @234240 |
| 73988 | GIM_Try, /*On fail goto*//*Label 4070*/ GIMT_Encode4(234307), // Rule ID 2392 // |
| 73989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 73990 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 73991 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 73992 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 73993 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 73994 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 73995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 73996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 73997 | // (intrinsic_wo_chain:{ *:[v8f32] } 3106:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF16_w32_threeaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 73998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_threeaddr), |
| 73999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74001 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74003 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74008 | GIR_RootConstrainSelectedInstOperands, |
| 74009 | // GIR_Coverage, 2392, |
| 74010 | GIR_EraseRootFromParent_Done, |
| 74011 | // Label 4070: @234307 |
| 74012 | GIM_Try, /*On fail goto*//*Label 4071*/ GIMT_Encode4(234368), // Rule ID 2402 // |
| 74013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74014 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8), |
| 74015 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74018 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74021 | // (intrinsic_wo_chain:{ *:[v8f32] } 3111:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 74022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_threeaddr), |
| 74023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74024 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74025 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74030 | GIR_RootConstrainSelectedInstOperands, |
| 74031 | // GIR_Coverage, 2402, |
| 74032 | GIR_EraseRootFromParent_Done, |
| 74033 | // Label 4071: @234368 |
| 74034 | GIM_Try, /*On fail goto*//*Label 4072*/ GIMT_Encode4(234429), // Rule ID 2404 // |
| 74035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74036 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8), |
| 74037 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74038 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74039 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74040 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74041 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74043 | // (intrinsic_wo_chain:{ *:[v8f32] } 3110:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 74044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_threeaddr), |
| 74045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74046 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74047 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74052 | GIR_RootConstrainSelectedInstOperands, |
| 74053 | // GIR_Coverage, 2404, |
| 74054 | GIR_EraseRootFromParent_Done, |
| 74055 | // Label 4072: @234429 |
| 74056 | GIM_Try, /*On fail goto*//*Label 4073*/ GIMT_Encode4(234490), // Rule ID 2406 // |
| 74057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74058 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8), |
| 74059 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74060 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74061 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74062 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74065 | // (intrinsic_wo_chain:{ *:[v8f32] } 3108:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 74066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_threeaddr), |
| 74067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74068 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74069 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74074 | GIR_RootConstrainSelectedInstOperands, |
| 74075 | // GIR_Coverage, 2406, |
| 74076 | GIR_EraseRootFromParent_Done, |
| 74077 | // Label 4073: @234490 |
| 74078 | GIM_Try, /*On fail goto*//*Label 4074*/ GIMT_Encode4(234551), // Rule ID 2408 // |
| 74079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74080 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8), |
| 74081 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74082 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74083 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74084 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74085 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74086 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74087 | // (intrinsic_wo_chain:{ *:[v8f32] } 3107:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8f32:{ *:[v8f32] }:$src2) |
| 74088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_threeaddr), |
| 74089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74090 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74091 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74096 | GIR_RootConstrainSelectedInstOperands, |
| 74097 | // GIR_Coverage, 2408, |
| 74098 | GIR_EraseRootFromParent_Done, |
| 74099 | // Label 4074: @234551 |
| 74100 | GIM_Try, /*On fail goto*//*Label 4075*/ GIMT_Encode4(234618), // Rule ID 2425 // |
| 74101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74102 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 74103 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74104 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74105 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 74106 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74109 | // (intrinsic_wo_chain:{ *:[v4f32] } 3106:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF16_w64_threeaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 74110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_threeaddr), |
| 74111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74113 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74115 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74120 | GIR_RootConstrainSelectedInstOperands, |
| 74121 | // GIR_Coverage, 2425, |
| 74122 | GIR_EraseRootFromParent_Done, |
| 74123 | // Label 4075: @234618 |
| 74124 | GIM_Try, /*On fail goto*//*Label 4076*/ GIMT_Encode4(234679), // Rule ID 2435 // |
| 74125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8), |
| 74127 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74129 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74130 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74132 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74133 | // (intrinsic_wo_chain:{ *:[v4f32] } 3111:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 74134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_threeaddr), |
| 74135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74136 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74137 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74142 | GIR_RootConstrainSelectedInstOperands, |
| 74143 | // GIR_Coverage, 2435, |
| 74144 | GIR_EraseRootFromParent_Done, |
| 74145 | // Label 4076: @234679 |
| 74146 | GIM_Try, /*On fail goto*//*Label 4077*/ GIMT_Encode4(234740), // Rule ID 2437 // |
| 74147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74148 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8), |
| 74149 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74150 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74151 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74152 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74154 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74155 | // (intrinsic_wo_chain:{ *:[v4f32] } 3110:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 74156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_threeaddr), |
| 74157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74158 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74159 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74164 | GIR_RootConstrainSelectedInstOperands, |
| 74165 | // GIR_Coverage, 2437, |
| 74166 | GIR_EraseRootFromParent_Done, |
| 74167 | // Label 4077: @234740 |
| 74168 | GIM_Try, /*On fail goto*//*Label 4078*/ GIMT_Encode4(234801), // Rule ID 2439 // |
| 74169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74170 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8), |
| 74171 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74172 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74173 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74174 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74177 | // (intrinsic_wo_chain:{ *:[v4f32] } 3108:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 74178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_threeaddr), |
| 74179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74180 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74181 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74185 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74186 | GIR_RootConstrainSelectedInstOperands, |
| 74187 | // GIR_Coverage, 2439, |
| 74188 | GIR_EraseRootFromParent_Done, |
| 74189 | // Label 4078: @234801 |
| 74190 | GIM_Try, /*On fail goto*//*Label 4079*/ GIMT_Encode4(234862), // Rule ID 2441 // |
| 74191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74192 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8), |
| 74193 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74195 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74196 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74199 | // (intrinsic_wo_chain:{ *:[v4f32] } 3107:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2)) => (V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, 8:{ *:[i32] }, v4f32:{ *:[v4f32] }:$src2) |
| 74200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_threeaddr), |
| 74201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74202 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74203 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74208 | GIR_RootConstrainSelectedInstOperands, |
| 74209 | // GIR_Coverage, 2441, |
| 74210 | GIR_EraseRootFromParent_Done, |
| 74211 | // Label 4079: @234862 |
| 74212 | GIM_Try, /*On fail goto*//*Label 4080*/ GIMT_Encode4(234931), // Rule ID 2391 // |
| 74213 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74214 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 74215 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74216 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74217 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74218 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74221 | // (intrinsic_wo_chain:{ *:[v8f32] } 3106:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 74222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w32_twoaddr), |
| 74223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74225 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74227 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74232 | GIR_RootConstrainSelectedInstOperands, |
| 74233 | // GIR_Coverage, 2391, |
| 74234 | GIR_EraseRootFromParent_Done, |
| 74235 | // Label 4080: @234931 |
| 74236 | GIM_Try, /*On fail goto*//*Label 4081*/ GIMT_Encode4(234994), // Rule ID 2401 // |
| 74237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74238 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8), |
| 74239 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74241 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74242 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74245 | // (intrinsic_wo_chain:{ *:[v8f32] } 3111:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 74246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w32_twoaddr), |
| 74247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74248 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74249 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74254 | GIR_RootConstrainSelectedInstOperands, |
| 74255 | // GIR_Coverage, 2401, |
| 74256 | GIR_EraseRootFromParent_Done, |
| 74257 | // Label 4081: @234994 |
| 74258 | GIM_Try, /*On fail goto*//*Label 4082*/ GIMT_Encode4(235057), // Rule ID 2403 // |
| 74259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74260 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8), |
| 74261 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74263 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74264 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74266 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74267 | // (intrinsic_wo_chain:{ *:[v8f32] } 3110:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 74268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w32_twoaddr), |
| 74269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74270 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74271 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74276 | GIR_RootConstrainSelectedInstOperands, |
| 74277 | // GIR_Coverage, 2403, |
| 74278 | GIR_EraseRootFromParent_Done, |
| 74279 | // Label 4082: @235057 |
| 74280 | GIM_Try, /*On fail goto*//*Label 4083*/ GIMT_Encode4(235120), // Rule ID 2405 // |
| 74281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8), |
| 74283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74285 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74286 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74287 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74289 | // (intrinsic_wo_chain:{ *:[v8f32] } 3108:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 74290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w32_twoaddr), |
| 74291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74292 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74293 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74298 | GIR_RootConstrainSelectedInstOperands, |
| 74299 | // GIR_Coverage, 2405, |
| 74300 | GIR_EraseRootFromParent_Done, |
| 74301 | // Label 4083: @235120 |
| 74302 | GIM_Try, /*On fail goto*//*Label 4084*/ GIMT_Encode4(235183), // Rule ID 2407 // |
| 74303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74304 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8), |
| 74305 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74306 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74307 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 74308 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74309 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74310 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74311 | // (intrinsic_wo_chain:{ *:[v8f32] } 3107:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v8f32] } v8f32:{ *:[v8f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f32:{ *:[v8f32] }:$src2) |
| 74312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w32_twoaddr), |
| 74313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74314 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74315 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74320 | GIR_RootConstrainSelectedInstOperands, |
| 74321 | // GIR_Coverage, 2407, |
| 74322 | GIR_EraseRootFromParent_Done, |
| 74323 | // Label 4084: @235183 |
| 74324 | GIM_Try, /*On fail goto*//*Label 4085*/ GIMT_Encode4(235252), // Rule ID 2424 // |
| 74325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74326 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf16), |
| 74327 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74328 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74329 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 74330 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74333 | // (intrinsic_wo_chain:{ *:[v4f32] } 3106:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 74334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF16_w64_twoaddr), |
| 74335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74337 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74339 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74344 | GIR_RootConstrainSelectedInstOperands, |
| 74345 | // GIR_Coverage, 2424, |
| 74346 | GIR_EraseRootFromParent_Done, |
| 74347 | // Label 4085: @235252 |
| 74348 | GIM_Try, /*On fail goto*//*Label 4086*/ GIMT_Encode4(235315), // Rule ID 2434 // |
| 74349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74350 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_fp8), |
| 74351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74354 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74356 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74357 | // (intrinsic_wo_chain:{ *:[v4f32] } 3111:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 74358 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_FP8_w64_twoaddr), |
| 74359 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74360 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74361 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74366 | GIR_RootConstrainSelectedInstOperands, |
| 74367 | // GIR_Coverage, 2434, |
| 74368 | GIR_EraseRootFromParent_Done, |
| 74369 | // Label 4086: @235315 |
| 74370 | GIM_Try, /*On fail goto*//*Label 4087*/ GIMT_Encode4(235378), // Rule ID 2436 // |
| 74371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74372 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_fp8_bf8), |
| 74373 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74374 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74375 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74376 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74378 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74379 | // (intrinsic_wo_chain:{ *:[v4f32] } 3110:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 74380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_FP8_BF8_w64_twoaddr), |
| 74381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74382 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74383 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74388 | GIR_RootConstrainSelectedInstOperands, |
| 74389 | // GIR_Coverage, 2436, |
| 74390 | GIR_EraseRootFromParent_Done, |
| 74391 | // Label 4087: @235378 |
| 74392 | GIM_Try, /*On fail goto*//*Label 4088*/ GIMT_Encode4(235441), // Rule ID 2438 // |
| 74393 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74394 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_fp8), |
| 74395 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74396 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74397 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74398 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74399 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74401 | // (intrinsic_wo_chain:{ *:[v4f32] } 3108:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 74402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_FP8_w64_twoaddr), |
| 74403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74404 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74405 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74410 | GIR_RootConstrainSelectedInstOperands, |
| 74411 | // GIR_Coverage, 2438, |
| 74412 | GIR_EraseRootFromParent_Done, |
| 74413 | // Label 4088: @235441 |
| 74414 | GIM_Try, /*On fail goto*//*Label 4089*/ GIMT_Encode4(235504), // Rule ID 2440 // |
| 74415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74416 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f32_16x16x16_bf8_bf8), |
| 74417 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74418 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74419 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74420 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74421 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamods), |
| 74423 | // (intrinsic_wo_chain:{ *:[v4f32] } 3107:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (WMMAModsF32NegAbs:{ *:[v4f32] } v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f32:{ *:[v4f32] }:$src2) |
| 74424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F32_16X16X16_BF8_BF8_w64_twoaddr), |
| 74425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74426 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74427 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_modifiers |
| 74429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74432 | GIR_RootConstrainSelectedInstOperands, |
| 74433 | // GIR_Coverage, 2440, |
| 74434 | GIR_EraseRootFromParent_Done, |
| 74435 | // Label 4089: @235504 |
| 74436 | GIM_Try, /*On fail goto*//*Label 4090*/ GIMT_Encode4(235543), // Rule ID 2109 // |
| 74437 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74438 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 74439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74440 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74441 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 74442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74443 | // (intrinsic_wo_chain:{ *:[i32] } 3124:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2) |
| 74444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74446 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74447 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74448 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74449 | GIR_RootConstrainSelectedInstOperands, |
| 74450 | // GIR_Coverage, 2109, |
| 74451 | GIR_EraseRootFromParent_Done, |
| 74452 | // Label 4090: @235543 |
| 74453 | GIM_Try, /*On fail goto*//*Label 4091*/ GIMT_Encode4(235582), // Rule ID 2111 // |
| 74454 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74455 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 74456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 74457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74458 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 74459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74460 | // (intrinsic_wo_chain:{ *:[f32] } 3124:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, f32:{ *:[f32] }:$src2) => (V_WRITELANE_B32:{ *:[f32] } SCSrc_b32:{ *:[f32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[f32] }:$src2) |
| 74461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74463 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74464 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74465 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74466 | GIR_RootConstrainSelectedInstOperands, |
| 74467 | // GIR_Coverage, 2111, |
| 74468 | GIR_EraseRootFromParent_Done, |
| 74469 | // Label 4091: @235582 |
| 74470 | GIM_Try, /*On fail goto*//*Label 4092*/ GIMT_Encode4(235621), // Rule ID 2113 // |
| 74471 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74472 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 74473 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 74474 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74475 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16, |
| 74476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74477 | // (intrinsic_wo_chain:{ *:[v2i16] } 3124:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, v2i16:{ *:[v2i16] }:$src2) => (V_WRITELANE_B32:{ *:[v2i16] } SCSrc_b32:{ *:[v2i16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[v2i16] }:$src2) |
| 74478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74480 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74481 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74482 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74483 | GIR_RootConstrainSelectedInstOperands, |
| 74484 | // GIR_Coverage, 2113, |
| 74485 | GIR_EraseRootFromParent_Done, |
| 74486 | // Label 4092: @235621 |
| 74487 | GIM_Try, /*On fail goto*//*Label 4093*/ GIMT_Encode4(235660), // Rule ID 2115 // |
| 74488 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74489 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 74490 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 74491 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74492 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16, |
| 74493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74494 | // (intrinsic_wo_chain:{ *:[v2f16] } 3124:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, v2f16:{ *:[v2f16] }:$src2) => (V_WRITELANE_B32:{ *:[v2f16] } SCSrc_b32:{ *:[v2f16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[v2f16] }:$src2) |
| 74495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74497 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74498 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74499 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74500 | GIR_RootConstrainSelectedInstOperands, |
| 74501 | // GIR_Coverage, 2115, |
| 74502 | GIR_EraseRootFromParent_Done, |
| 74503 | // Label 4093: @235660 |
| 74504 | GIM_Try, /*On fail goto*//*Label 4094*/ GIMT_Encode4(235699), // Rule ID 2117 // |
| 74505 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74506 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 74507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 74508 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74509 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v2s16, |
| 74510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74511 | // (intrinsic_wo_chain:{ *:[v2bf16] } 3124:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1, v2bf16:{ *:[v2bf16] }:$src2) => (V_WRITELANE_B32:{ *:[v2bf16] } SCSrc_b32:{ *:[v2bf16] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[v2bf16] }:$src2) |
| 74512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74514 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74515 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74516 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74517 | GIR_RootConstrainSelectedInstOperands, |
| 74518 | // GIR_Coverage, 2117, |
| 74519 | GIR_EraseRootFromParent_Done, |
| 74520 | // Label 4094: @235699 |
| 74521 | GIM_Try, /*On fail goto*//*Label 4095*/ GIMT_Encode4(235738), // Rule ID 2119 // |
| 74522 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74523 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 74524 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 74525 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74526 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p2s32, |
| 74527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74528 | // (intrinsic_wo_chain:{ *:[i32] } 3124:{ *:[iPTR] }, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p2:{ *:[i32] }:$src2) => (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2) |
| 74529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74531 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74532 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74533 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74534 | GIR_RootConstrainSelectedInstOperands, |
| 74535 | // GIR_Coverage, 2119, |
| 74536 | GIR_EraseRootFromParent_Done, |
| 74537 | // Label 4095: @235738 |
| 74538 | GIM_Try, /*On fail goto*//*Label 4096*/ GIMT_Encode4(235777), // Rule ID 2121 // |
| 74539 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74540 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 74541 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 74542 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74543 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p3s32, |
| 74544 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74545 | // (intrinsic_wo_chain:{ *:[i32] } 3124:{ *:[iPTR] }, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p3:{ *:[i32] }:$src2) => (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2) |
| 74546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74548 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74549 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74550 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74551 | GIR_RootConstrainSelectedInstOperands, |
| 74552 | // GIR_Coverage, 2121, |
| 74553 | GIR_EraseRootFromParent_Done, |
| 74554 | // Label 4096: @235777 |
| 74555 | GIM_Try, /*On fail goto*//*Label 4097*/ GIMT_Encode4(235816), // Rule ID 2123 // |
| 74556 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74557 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 74558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 74559 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74560 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p5s32, |
| 74561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74562 | // (intrinsic_wo_chain:{ *:[i32] } 3124:{ *:[iPTR] }, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p5:{ *:[i32] }:$src2) => (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2) |
| 74563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74565 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74566 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74567 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74568 | GIR_RootConstrainSelectedInstOperands, |
| 74569 | // GIR_Coverage, 2123, |
| 74570 | GIR_EraseRootFromParent_Done, |
| 74571 | // Label 4097: @235816 |
| 74572 | GIM_Try, /*On fail goto*//*Label 4098*/ GIMT_Encode4(235855), // Rule ID 2125 // |
| 74573 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_writelane), |
| 74574 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 74575 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 74576 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 74577 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_p6s32, |
| 74578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 74579 | // (intrinsic_wo_chain:{ *:[i32] } 3124:{ *:[iPTR] }, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, p6:{ *:[i32] }:$src2) => (V_WRITELANE_B32:{ *:[i32] } SCSrc_b32:{ *:[i32] }:$src0, SCSrc_b32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$src2) |
| 74580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WRITELANE_B32), |
| 74581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74582 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74583 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74584 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 74585 | GIR_RootConstrainSelectedInstOperands, |
| 74586 | // GIR_Coverage, 2125, |
| 74587 | GIR_EraseRootFromParent_Done, |
| 74588 | // Label 4098: @235855 |
| 74589 | GIM_Reject, |
| 74590 | // Label 4061: @235856 |
| 74591 | GIM_Try, /*On fail goto*//*Label 4099*/ GIMT_Encode4(238329), |
| 74592 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/6, |
| 74593 | GIM_Try, /*On fail goto*//*Label 4100*/ GIMT_Encode4(235966), // Rule ID 2394 // |
| 74594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74595 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 74596 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 74597 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74598 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74599 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 74600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74601 | // MIs[0] Operand 5 |
| 74602 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74603 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74606 | // (intrinsic_wo_chain:{ *:[v8f16] } 3104:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2), 0:{ *:[i1] }) => (V_WMMA_F16_16X16X16_F16_w32_threeaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, 8:{ *:[i32] }, v8f16:{ *:[v8f16] }:$src2) |
| 74607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_threeaddr), |
| 74608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74617 | GIR_RootConstrainSelectedInstOperands, |
| 74618 | // GIR_Coverage, 2394, |
| 74619 | GIR_EraseRootFromParent_Done, |
| 74620 | // Label 4100: @235966 |
| 74621 | GIM_Try, /*On fail goto*//*Label 4101*/ GIMT_Encode4(236068), // Rule ID 2427 // |
| 74622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74623 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 74624 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 74625 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74626 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 74627 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 74628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 74629 | // MIs[0] Operand 5 |
| 74630 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74634 | // (intrinsic_wo_chain:{ *:[v4f16] } 3104:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAVISrc:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2), 0:{ *:[i1] }) => (V_WMMA_F16_16X16X16_F16_w64_threeaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, 8:{ *:[i32] }, v4f16:{ *:[v4f16] }:$src2) |
| 74635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_threeaddr), |
| 74636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74645 | GIR_RootConstrainSelectedInstOperands, |
| 74646 | // GIR_Coverage, 2427, |
| 74647 | GIR_EraseRootFromParent_Done, |
| 74648 | // Label 4101: @236068 |
| 74649 | GIM_Try, /*On fail goto*//*Label 4102*/ GIMT_Encode4(236172), // Rule ID 2393 // |
| 74650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74651 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 74652 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 74653 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74654 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74655 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 74656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74657 | // MIs[0] Operand 5 |
| 74658 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs), |
| 74662 | // (intrinsic_wo_chain:{ *:[v8f16] } 3104:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_WMMA_F16_16X16X16_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2) |
| 74663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w32_twoaddr), |
| 74664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 74670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74673 | GIR_RootConstrainSelectedInstOperands, |
| 74674 | // GIR_Coverage, 2393, |
| 74675 | GIR_EraseRootFromParent_Done, |
| 74676 | // Label 4102: @236172 |
| 74677 | GIM_Try, /*On fail goto*//*Label 4103*/ GIMT_Encode4(236276), // Rule ID 2426 // |
| 74678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74679 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 74680 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 74681 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74682 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 74683 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 74684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 74685 | // MIs[0] Operand 5 |
| 74686 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74688 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmamodsf16NegAbs), |
| 74690 | // (intrinsic_wo_chain:{ *:[v4f16] } 3104:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (WMMAModsF16NegAbs:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers), 0:{ *:[i1] }) => (V_WMMA_F16_16X16X16_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4f16:{ *:[v4f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v4f16:{ *:[v4f16] }:$src2) |
| 74691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_w64_twoaddr), |
| 74692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 74698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74701 | GIR_RootConstrainSelectedInstOperands, |
| 74702 | // GIR_Coverage, 2426, |
| 74703 | GIR_EraseRootFromParent_Done, |
| 74704 | // Label 4103: @236276 |
| 74705 | GIM_Try, /*On fail goto*//*Label 4104*/ GIMT_Encode4(236374), // Rule ID 2411 // |
| 74706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74707 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16), |
| 74708 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74709 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74710 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 74711 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74712 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74716 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74717 | // (intrinsic_wo_chain:{ *:[v8f32] } 3084:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_F16_w32_twoaddr:{ *:[v8f32] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w32_twoaddr), |
| 74719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74724 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 74727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74729 | GIR_RootConstrainSelectedInstOperands, |
| 74730 | // GIR_Coverage, 2411, |
| 74731 | GIR_EraseRootFromParent_Done, |
| 74732 | // Label 4104: @236374 |
| 74733 | GIM_Try, /*On fail goto*//*Label 4105*/ GIMT_Encode4(236472), // Rule ID 2413 // |
| 74734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74735 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16), |
| 74736 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 74737 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74738 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 74739 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 74740 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74741 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74742 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74745 | // (intrinsic_wo_chain:{ *:[v8f16] } 3080:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v16f16] } v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v8f16:{ *:[v8f16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F16_16X16X32_F16_w32_twoaddr:{ *:[v8f16] } i32:{ *:[i32] }:$src0_modifiers, v8f16:{ *:[v8f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w32_twoaddr), |
| 74747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74752 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 74755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74757 | GIR_RootConstrainSelectedInstOperands, |
| 74758 | // GIR_Coverage, 2413, |
| 74759 | GIR_EraseRootFromParent_Done, |
| 74760 | // Label 4105: @236472 |
| 74761 | GIM_Try, /*On fail goto*//*Label 4106*/ GIMT_Encode4(236570), // Rule ID 2444 // |
| 74762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74763 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_f16), |
| 74764 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 74765 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74766 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74767 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 74768 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74770 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 74773 | // (intrinsic_wo_chain:{ *:[v4f32] } 3084:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_F16_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 74774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_F16_w64_twoaddr), |
| 74775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74780 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit |
| 74783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74785 | GIR_RootConstrainSelectedInstOperands, |
| 74786 | // GIR_Coverage, 2444, |
| 74787 | GIR_EraseRootFromParent_Done, |
| 74788 | // Label 4106: @236570 |
| 74789 | GIM_Try, /*On fail goto*//*Label 4107*/ GIMT_Encode4(236668), // Rule ID 2446 // |
| 74790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74791 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f16_16x16x32_f16), |
| 74792 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 74793 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74794 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74795 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 74796 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 74798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_wmmamodsf16Neg), |
| 74800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 74801 | // (intrinsic_wo_chain:{ *:[v4f16] } 3080:{ *:[iPTR] }, (WMMAModsF16Neg:{ *:[v4f16] } v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (WMMAModsF16Neg:{ *:[v8f16] } v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), v4f16:{ *:[v4f16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F16_16X16X32_F16_w64_twoaddr:{ *:[v4f16] } i32:{ *:[i32] }:$src0_modifiers, v4f16:{ *:[v4f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v8f16:{ *:[v8f16] }:$src1, v4f16:{ *:[v4f16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 74802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F16_16X16X32_F16_w64_twoaddr), |
| 74803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 74805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 74806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 74807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 74808 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 74810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit |
| 74811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74812 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74813 | GIR_RootConstrainSelectedInstOperands, |
| 74814 | // GIR_Coverage, 2446, |
| 74815 | GIR_EraseRootFromParent_Done, |
| 74816 | // Label 4107: @236668 |
| 74817 | GIM_Try, /*On fail goto*//*Label 4108*/ GIMT_Encode4(236746), // Rule ID 2396 // |
| 74818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74819 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 74820 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 74821 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74822 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 74823 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 74824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74825 | // MIs[0] Operand 5 |
| 74826 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74828 | // (intrinsic_wo_chain:{ *:[v8i16] } 3102:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, (WMMAVISrc:{ *:[v8i16] } v8i16:{ *:[v8i16] }:$src2), 0:{ *:[i1] }) => (V_WMMA_BF16_16X16X16_BF16_w32_threeaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2) |
| 74829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_threeaddr), |
| 74830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74832 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74834 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74839 | GIR_RootConstrainSelectedInstOperands, |
| 74840 | // GIR_Coverage, 2396, |
| 74841 | GIR_EraseRootFromParent_Done, |
| 74842 | // Label 4108: @236746 |
| 74843 | GIM_Try, /*On fail goto*//*Label 4109*/ GIMT_Encode4(236824), // Rule ID 2429 // |
| 74844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 74845 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 74846 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 74847 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 74848 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 74849 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 74850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 74851 | // MIs[0] Operand 5 |
| 74852 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 74853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 74854 | // (intrinsic_wo_chain:{ *:[v4i16] } 3102:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, (WMMAVISrc:{ *:[v4i16] } v4i16:{ *:[v4i16] }:$src2), 0:{ *:[i1] }) => (V_WMMA_BF16_16X16X16_BF16_w64_threeaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2) |
| 74855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_threeaddr), |
| 74856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74858 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74860 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74865 | GIR_RootConstrainSelectedInstOperands, |
| 74866 | // GIR_Coverage, 2429, |
| 74867 | GIR_EraseRootFromParent_Done, |
| 74868 | // Label 4109: @236824 |
| 74869 | GIM_Try, /*On fail goto*//*Label 4110*/ GIMT_Encode4(236898), // Rule ID 2412 // |
| 74870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74871 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16), |
| 74872 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74873 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74874 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 74875 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74876 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74879 | // (intrinsic_wo_chain:{ *:[v8f32] } 3081:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr:{ *:[v8f32] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w32_twoaddr), |
| 74881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74883 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74885 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74886 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 74889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74891 | GIR_RootConstrainSelectedInstOperands, |
| 74892 | // GIR_Coverage, 2412, |
| 74893 | GIR_EraseRootFromParent_Done, |
| 74894 | // Label 4110: @236898 |
| 74895 | GIM_Try, /*On fail goto*//*Label 4111*/ GIMT_Encode4(236972), // Rule ID 2414 // |
| 74896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74897 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16), |
| 74898 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 74899 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 74900 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 74901 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 74902 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 74904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74905 | // (intrinsic_wo_chain:{ *:[v8i16] } 3079:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w32_twoaddr), |
| 74907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74909 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 74911 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74912 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 74915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 74917 | GIR_RootConstrainSelectedInstOperands, |
| 74918 | // GIR_Coverage, 2414, |
| 74919 | GIR_EraseRootFromParent_Done, |
| 74920 | // Label 4111: @236972 |
| 74921 | GIM_Try, /*On fail goto*//*Label 4112*/ GIMT_Encode4(237034), // Rule ID 2418 // |
| 74922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74923 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8), |
| 74924 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74925 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74926 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 74927 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74928 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74931 | // (intrinsic_wo_chain:{ *:[v8f32] } 3086:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w32_twoaddr), |
| 74933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74934 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74935 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74936 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 74939 | GIR_RootConstrainSelectedInstOperands, |
| 74940 | // GIR_Coverage, 2418, |
| 74941 | GIR_EraseRootFromParent_Done, |
| 74942 | // Label 4112: @237034 |
| 74943 | GIM_Try, /*On fail goto*//*Label 4113*/ GIMT_Encode4(237096), // Rule ID 2419 // |
| 74944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74945 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8), |
| 74946 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74947 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74948 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 74949 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74950 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74953 | // (intrinsic_wo_chain:{ *:[v8f32] } 3085:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w32_twoaddr), |
| 74955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74956 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74957 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74958 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 74961 | GIR_RootConstrainSelectedInstOperands, |
| 74962 | // GIR_Coverage, 2419, |
| 74963 | GIR_EraseRootFromParent_Done, |
| 74964 | // Label 4113: @237096 |
| 74965 | GIM_Try, /*On fail goto*//*Label 4114*/ GIMT_Encode4(237158), // Rule ID 2420 // |
| 74966 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74967 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8), |
| 74968 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74969 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74970 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 74971 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74972 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74974 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74975 | // (intrinsic_wo_chain:{ *:[v8f32] } 3083:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w32_twoaddr), |
| 74977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 74978 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 74979 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 74980 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 74981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 74982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 74983 | GIR_RootConstrainSelectedInstOperands, |
| 74984 | // GIR_Coverage, 2420, |
| 74985 | GIR_EraseRootFromParent_Done, |
| 74986 | // Label 4114: @237158 |
| 74987 | GIM_Try, /*On fail goto*//*Label 4115*/ GIMT_Encode4(237220), // Rule ID 2421 // |
| 74988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 74989 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8), |
| 74990 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 74991 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 74992 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 74993 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s32, |
| 74994 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 74995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 74996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 74997 | // (intrinsic_wo_chain:{ *:[v8f32] } 3082:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit)) => (V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr:{ *:[v8f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v8f32:{ *:[v8f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit) |
| 74998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w32_twoaddr), |
| 74999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75000 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75001 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75002 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_16bit |
| 75005 | GIR_RootConstrainSelectedInstOperands, |
| 75006 | // GIR_Coverage, 2421, |
| 75007 | GIR_EraseRootFromParent_Done, |
| 75008 | // Label 4115: @237220 |
| 75009 | GIM_Try, /*On fail goto*//*Label 4116*/ GIMT_Encode4(237294), // Rule ID 2445 // |
| 75010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75011 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf16), |
| 75012 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 75014 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 75015 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 75016 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75018 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75019 | // (intrinsic_wo_chain:{ *:[v4f32] } 3081:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr:{ *:[v4f32] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF16_w64_twoaddr), |
| 75021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75023 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75025 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75026 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75031 | GIR_RootConstrainSelectedInstOperands, |
| 75032 | // GIR_Coverage, 2445, |
| 75033 | GIR_EraseRootFromParent_Done, |
| 75034 | // Label 4116: @237294 |
| 75035 | GIM_Try, /*On fail goto*//*Label 4117*/ GIMT_Encode4(237368), // Rule ID 2447 // |
| 75036 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75037 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_bf16_16x16x32_bf16), |
| 75038 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 75039 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 75040 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 75041 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 75042 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 75044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75045 | // (intrinsic_wo_chain:{ *:[v4i16] } 3079:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, v4i16:{ *:[v4i16] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_BF16_16X16X32_BF16_w64_twoaddr), |
| 75047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75049 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75051 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75052 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75057 | GIR_RootConstrainSelectedInstOperands, |
| 75058 | // GIR_Coverage, 2447, |
| 75059 | GIR_EraseRootFromParent_Done, |
| 75060 | // Label 4117: @237368 |
| 75061 | GIM_Try, /*On fail goto*//*Label 4118*/ GIMT_Encode4(237430), // Rule ID 2451 // |
| 75062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75063 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_fp8), |
| 75064 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75065 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75066 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75067 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 75068 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75070 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75071 | // (intrinsic_wo_chain:{ *:[v4f32] } 3086:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_FP8_w64_twoaddr), |
| 75073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75074 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75075 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75076 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75079 | GIR_RootConstrainSelectedInstOperands, |
| 75080 | // GIR_Coverage, 2451, |
| 75081 | GIR_EraseRootFromParent_Done, |
| 75082 | // Label 4118: @237430 |
| 75083 | GIM_Try, /*On fail goto*//*Label 4119*/ GIMT_Encode4(237492), // Rule ID 2452 // |
| 75084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75085 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_fp8_bf8), |
| 75086 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75087 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75088 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75089 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 75090 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75093 | // (intrinsic_wo_chain:{ *:[v4f32] } 3085:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_FP8_BF8_w64_twoaddr), |
| 75095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75096 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75097 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75098 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75101 | GIR_RootConstrainSelectedInstOperands, |
| 75102 | // GIR_Coverage, 2452, |
| 75103 | GIR_EraseRootFromParent_Done, |
| 75104 | // Label 4119: @237492 |
| 75105 | GIM_Try, /*On fail goto*//*Label 4120*/ GIMT_Encode4(237554), // Rule ID 2453 // |
| 75106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75107 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_fp8), |
| 75108 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75109 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75110 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75111 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 75112 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75115 | // (intrinsic_wo_chain:{ *:[v4f32] } 3083:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_FP8_w64_twoaddr), |
| 75117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75118 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75119 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75120 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75123 | GIR_RootConstrainSelectedInstOperands, |
| 75124 | // GIR_Coverage, 2453, |
| 75125 | GIR_EraseRootFromParent_Done, |
| 75126 | // Label 4120: @237554 |
| 75127 | GIM_Try, /*On fail goto*//*Label 4121*/ GIMT_Encode4(237616), // Rule ID 2454 // |
| 75128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75129 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_f32_16x16x32_bf8_bf8), |
| 75130 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75131 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75132 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75133 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 75134 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75135 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75136 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 75137 | // (intrinsic_wo_chain:{ *:[v4f32] } 3082:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit)) => (V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr:{ *:[v4f32] } i32:{ *:[i32] }:$src0, v2i32:{ *:[v2i32] }:$src1, v4f32:{ *:[v4f32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit) |
| 75138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_F32_16X16X32_BF8_BF8_w64_twoaddr), |
| 75139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75140 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75141 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75142 | GIR_RootToRootCopy, /*OpIdx*/4, // srcTiedDef |
| 75143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 75144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // index_key_8bit |
| 75145 | GIR_RootConstrainSelectedInstOperands, |
| 75146 | // GIR_Coverage, 2454, |
| 75147 | GIR_EraseRootFromParent_Done, |
| 75148 | // Label 4121: @237616 |
| 75149 | GIM_Try, /*On fail goto*//*Label 4122*/ GIMT_Encode4(237688), // Rule ID 2373 // |
| 75150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75151 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 75152 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16, |
| 75153 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75154 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75155 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16, |
| 75156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75158 | // (intrinsic_wo_chain:{ *:[v16f16] } 3104:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F16_16X16X16_F16_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2) |
| 75159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w32), |
| 75160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75162 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75164 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75166 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75171 | GIR_RootConstrainSelectedInstOperands, |
| 75172 | // GIR_Coverage, 2373, |
| 75173 | GIR_EraseRootFromParent_Done, |
| 75174 | // Label 4122: @237688 |
| 75175 | GIM_Try, /*On fail goto*//*Label 4123*/ GIMT_Encode4(237760), // Rule ID 2377 // |
| 75176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75177 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 75178 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16, |
| 75179 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75180 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75181 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16, |
| 75182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75184 | // (intrinsic_wo_chain:{ *:[v16i16] } 3102:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_BF16_16X16X16_BF16_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2) |
| 75185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w32), |
| 75186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75188 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75190 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75192 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75193 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75197 | GIR_RootConstrainSelectedInstOperands, |
| 75198 | // GIR_Coverage, 2377, |
| 75199 | GIR_EraseRootFromParent_Done, |
| 75200 | // Label 4123: @237760 |
| 75201 | GIM_Try, /*On fail goto*//*Label 4124*/ GIMT_Encode4(237832), // Rule ID 2378 // |
| 75202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75203 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied), |
| 75204 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16, |
| 75205 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75206 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75207 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16, |
| 75208 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75210 | // (intrinsic_wo_chain:{ *:[v16f16] } 3105:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v16f16:{ *:[v16f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32:{ *:[v16f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16f16:{ *:[v16f16] }:$src2) |
| 75211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w32), |
| 75212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75214 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75216 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75218 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75223 | GIR_RootConstrainSelectedInstOperands, |
| 75224 | // GIR_Coverage, 2378, |
| 75225 | GIR_EraseRootFromParent_Done, |
| 75226 | // Label 4124: @237832 |
| 75227 | GIM_Try, /*On fail goto*//*Label 4125*/ GIMT_Encode4(237904), // Rule ID 2379 // |
| 75228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75229 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied), |
| 75230 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s16, |
| 75231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75232 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75233 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s16, |
| 75234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75235 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75236 | // (intrinsic_wo_chain:{ *:[v16i16] } 3103:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v16i16:{ *:[v16i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32:{ *:[v16i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v16i16:{ *:[v16i16] }:$src2) |
| 75237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w32), |
| 75238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75240 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75242 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75244 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75249 | GIR_RootConstrainSelectedInstOperands, |
| 75250 | // GIR_Coverage, 2379, |
| 75251 | GIR_EraseRootFromParent_Done, |
| 75252 | // Label 4125: @237904 |
| 75253 | GIM_Try, /*On fail goto*//*Label 4126*/ GIMT_Encode4(237976), // Rule ID 2383 // |
| 75254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75255 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16), |
| 75256 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 75257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75258 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75259 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 75260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75262 | // (intrinsic_wo_chain:{ *:[v8f16] } 3104:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F16_16X16X16_F16_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2) |
| 75263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_twoaddr_w64), |
| 75264 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75266 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75268 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75270 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75275 | GIR_RootConstrainSelectedInstOperands, |
| 75276 | // GIR_Coverage, 2383, |
| 75277 | GIR_EraseRootFromParent_Done, |
| 75278 | // Label 4126: @237976 |
| 75279 | GIM_Try, /*On fail goto*//*Label 4127*/ GIMT_Encode4(238048), // Rule ID 2384 // |
| 75280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75281 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 75282 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 75283 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75284 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75285 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 75286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75288 | // (intrinsic_wo_chain:{ *:[v8i16] } 3102:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_BF16_16X16X16_BF16_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2) |
| 75289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_twoaddr_w64), |
| 75290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75292 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75294 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75296 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75301 | GIR_RootConstrainSelectedInstOperands, |
| 75302 | // GIR_Coverage, 2384, |
| 75303 | GIR_EraseRootFromParent_Done, |
| 75304 | // Label 4127: @238048 |
| 75305 | GIM_Try, /*On fail goto*//*Label 4128*/ GIMT_Encode4(238120), // Rule ID 2385 // |
| 75306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75307 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_f16_16x16x16_f16_tied), |
| 75308 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 75309 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75310 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75311 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 75312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75314 | // (intrinsic_wo_chain:{ *:[v8f16] } 3105:{ *:[iPTR] }, v16f16:{ *:[v16f16] }:$src0, v16f16:{ *:[v16f16] }:$src1, v8f16:{ *:[v8f16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64:{ *:[v8f16] } 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src0, 8:{ *:[i32] }, v16f16:{ *:[v16f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8f16:{ *:[v8f16] }:$src2) |
| 75315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_F16_16X16X16_F16_TIED_twoaddr_w64), |
| 75316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75318 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75320 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75322 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75327 | GIR_RootConstrainSelectedInstOperands, |
| 75328 | // GIR_Coverage, 2385, |
| 75329 | GIR_EraseRootFromParent_Done, |
| 75330 | // Label 4128: @238120 |
| 75331 | GIM_Try, /*On fail goto*//*Label 4129*/ GIMT_Encode4(238192), // Rule ID 2386 // |
| 75332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75333 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16_tied), |
| 75334 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 75335 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v16s16, |
| 75336 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v16s16, |
| 75337 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 75338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_wmmaopselvop3pmods), |
| 75340 | // (intrinsic_wo_chain:{ *:[v8i16] } 3103:{ *:[iPTR] }, v16i16:{ *:[v16i16] }:$src0, v16i16:{ *:[v16i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, (WMMAOpSelVOP3PMods:{ *:[i1] } i32:{ *:[i32] }:$src2_modifiers)) => (V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64:{ *:[v8i16] } 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src0, 8:{ *:[i32] }, v16i16:{ *:[v16i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v8i16:{ *:[v8i16] }:$src2) |
| 75341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_TIED_twoaddr_w64), |
| 75342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75344 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75345 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75346 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2_modifiers |
| 75348 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75353 | GIR_RootConstrainSelectedInstOperands, |
| 75354 | // GIR_Coverage, 2386, |
| 75355 | GIR_EraseRootFromParent_Done, |
| 75356 | // Label 4129: @238192 |
| 75357 | GIM_Try, /*On fail goto*//*Label 4130*/ GIMT_Encode4(238260), // Rule ID 2395 // |
| 75358 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75359 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 75360 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 75361 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v8s16, |
| 75362 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 75363 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v8s16, |
| 75364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75365 | // MIs[0] Operand 5 |
| 75366 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 75367 | // (intrinsic_wo_chain:{ *:[v8i16] } 3102:{ *:[iPTR] }, v8i16:{ *:[v8i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v8i16:{ *:[v8i16] }:$src2, 0:{ *:[i1] }) => (V_WMMA_BF16_16X16X16_BF16_w32_twoaddr:{ *:[v8i16] } 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src0, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src1, 8:{ *:[i32] }, v8i16:{ *:[v8i16] }:$src2) |
| 75368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w32_twoaddr), |
| 75369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75371 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75373 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75375 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75378 | GIR_RootConstrainSelectedInstOperands, |
| 75379 | // GIR_Coverage, 2395, |
| 75380 | GIR_EraseRootFromParent_Done, |
| 75381 | // Label 4130: @238260 |
| 75382 | GIM_Try, /*On fail goto*//*Label 4131*/ GIMT_Encode4(238328), // Rule ID 2428 // |
| 75383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75384 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_bf16_16x16x16_bf16), |
| 75385 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 75386 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 75387 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 75388 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s16, |
| 75389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 75390 | // MIs[0] Operand 5 |
| 75391 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/5, GIMT_Encode8(0), |
| 75392 | // (intrinsic_wo_chain:{ *:[v4i16] } 3102:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4i16:{ *:[v4i16] }:$src2, 0:{ *:[i1] }) => (V_WMMA_BF16_16X16X16_BF16_w64_twoaddr:{ *:[v4i16] } 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src0, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src1, 8:{ *:[i32] }, v4i16:{ *:[v4i16] }:$src2) |
| 75393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_BF16_16X16X16_BF16_w64_twoaddr), |
| 75394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75396 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 75397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75398 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 75399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75400 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 75401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75403 | GIR_RootConstrainSelectedInstOperands, |
| 75404 | // GIR_Coverage, 2428, |
| 75405 | GIR_EraseRootFromParent_Done, |
| 75406 | // Label 4131: @238328 |
| 75407 | GIM_Reject, |
| 75408 | // Label 4099: @238329 |
| 75409 | GIM_Try, /*On fail goto*//*Label 4132*/ GIMT_Encode4(238601), |
| 75410 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/7, |
| 75411 | GIM_Try, /*On fail goto*//*Label 4133*/ GIMT_Encode4(238407), // Rule ID 2091 // |
| 75412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 75413 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp), |
| 75414 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 75415 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75416 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 75417 | // MIs[0] dpp_ctrl |
| 75418 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 75419 | // MIs[0] row_mask |
| 75420 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 75421 | // MIs[0] bank_mask |
| 75422 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75423 | // MIs[0] bound_ctrl |
| 75424 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75425 | // (intrinsic_wo_chain:{ *:[i32] } 2875:{ *:[iPTR] }, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$src, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 75426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 75427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75428 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 75429 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 75430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 75431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 75432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 75433 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 75434 | GIR_RootConstrainSelectedInstOperands, |
| 75435 | // GIR_Coverage, 2091, |
| 75436 | GIR_EraseRootFromParent_Done, |
| 75437 | // Label 4133: @238407 |
| 75438 | GIM_Try, /*On fail goto*//*Label 4134*/ GIMT_Encode4(238474), // Rule ID 7284 // |
| 75439 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mov_dpp), |
| 75440 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 75441 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 75442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 75443 | // MIs[0] dpp_ctrl |
| 75444 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 75445 | // MIs[0] row_mask |
| 75446 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 75447 | // MIs[0] bank_mask |
| 75448 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75449 | // MIs[0] bound_ctrl |
| 75450 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75451 | // (intrinsic_wo_chain:{ *:[i64] } 2875:{ *:[iPTR] }, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$src, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 75452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 75453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75454 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 75455 | GIR_RootToRootCopy, /*OpIdx*/2, // src |
| 75456 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 75457 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 75458 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 75459 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 75460 | GIR_RootConstrainSelectedInstOperands, |
| 75461 | // GIR_Coverage, 7284, |
| 75462 | GIR_EraseRootFromParent_Done, |
| 75463 | // Label 4134: @238474 |
| 75464 | GIM_Try, /*On fail goto*//*Label 4135*/ GIMT_Encode4(238537), // Rule ID 2270 // |
| 75465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 75466 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16_var), |
| 75467 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 75468 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75469 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75470 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 75471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 75472 | // MIs[0] fi |
| 75473 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75474 | // MIs[0] bc |
| 75475 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75476 | // (intrinsic_wo_chain:{ *:[i32] } 2886:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in) |
| 75477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_VAR_B32_e64), |
| 75478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 75480 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75481 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 75482 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 75483 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 75484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75485 | GIR_RootConstrainSelectedInstOperands, |
| 75486 | // GIR_Coverage, 2270, |
| 75487 | GIR_EraseRootFromParent_Done, |
| 75488 | // Label 4135: @238537 |
| 75489 | GIM_Try, /*On fail goto*//*Label 4136*/ GIMT_Encode4(238600), // Rule ID 2271 // |
| 75490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 75491 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16_var), |
| 75492 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 75493 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75494 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75495 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 75496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 75497 | // MIs[0] fi |
| 75498 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75499 | // MIs[0] bc |
| 75500 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75501 | // (intrinsic_wo_chain:{ *:[i32] } 2889:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_VAR_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), VGPR_32:{ *:[i32] }:$src1, VGPR_32:{ *:[i32] }:$vdst_in) |
| 75502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_VAR_B32_e64), |
| 75503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75504 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 75505 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75506 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 75507 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 75508 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 75509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75510 | GIR_RootConstrainSelectedInstOperands, |
| 75511 | // GIR_Coverage, 2271, |
| 75512 | GIR_EraseRootFromParent_Done, |
| 75513 | // Label 4136: @238600 |
| 75514 | GIM_Reject, |
| 75515 | // Label 4132: @238601 |
| 75516 | GIM_Try, /*On fail goto*//*Label 4137*/ GIMT_Encode4(247893), |
| 75517 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/8, |
| 75518 | GIM_Try, /*On fail goto*//*Label 4138*/ GIMT_Encode4(238690), // Rule ID 2398 // |
| 75519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75520 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75521 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75522 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75523 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75524 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75526 | // MIs[0] clamp |
| 75527 | // No operand predicates |
| 75528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75529 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75531 | // (intrinsic_wo_chain:{ *:[v8i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU8_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_threeaddr), |
| 75533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75535 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75537 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75539 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75541 | GIR_RootConstrainSelectedInstOperands, |
| 75542 | // GIR_Coverage, 2398, |
| 75543 | GIR_EraseRootFromParent_Done, |
| 75544 | // Label 4138: @238690 |
| 75545 | GIM_Try, /*On fail goto*//*Label 4139*/ GIMT_Encode4(238771), // Rule ID 2400 // |
| 75546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75547 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75548 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75549 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75550 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75551 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75553 | // MIs[0] clamp |
| 75554 | // No operand predicates |
| 75555 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75556 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75557 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75558 | // (intrinsic_wo_chain:{ *:[v8i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU4_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_threeaddr), |
| 75560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75562 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75564 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75566 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75568 | GIR_RootConstrainSelectedInstOperands, |
| 75569 | // GIR_Coverage, 2400, |
| 75570 | GIR_EraseRootFromParent_Done, |
| 75571 | // Label 4139: @238771 |
| 75572 | GIM_Try, /*On fail goto*//*Label 4140*/ GIMT_Encode4(238852), // Rule ID 2410 // |
| 75573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75574 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4), |
| 75575 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75576 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75577 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75578 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75580 | // MIs[0] clamp |
| 75581 | // No operand predicates |
| 75582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75584 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75585 | // (intrinsic_wo_chain:{ *:[v8i32] } 3114:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, (WMMAVISrc:{ *:[v8i32] } v8i32:{ *:[v8i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X32_IU4_w32_threeaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_threeaddr), |
| 75587 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75589 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75591 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75593 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75595 | GIR_RootConstrainSelectedInstOperands, |
| 75596 | // GIR_Coverage, 2410, |
| 75597 | GIR_EraseRootFromParent_Done, |
| 75598 | // Label 4140: @238852 |
| 75599 | GIM_Try, /*On fail goto*//*Label 4141*/ GIMT_Encode4(238933), // Rule ID 2431 // |
| 75600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75601 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75602 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75603 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75604 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75605 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75607 | // MIs[0] clamp |
| 75608 | // No operand predicates |
| 75609 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75611 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75612 | // (intrinsic_wo_chain:{ *:[v4i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU8_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_threeaddr), |
| 75614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75616 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75618 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75620 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75622 | GIR_RootConstrainSelectedInstOperands, |
| 75623 | // GIR_Coverage, 2431, |
| 75624 | GIR_EraseRootFromParent_Done, |
| 75625 | // Label 4141: @238933 |
| 75626 | GIM_Try, /*On fail goto*//*Label 4142*/ GIMT_Encode4(239014), // Rule ID 2433 // |
| 75627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75628 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75629 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75630 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75631 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75632 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75634 | // MIs[0] clamp |
| 75635 | // No operand predicates |
| 75636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75639 | // (intrinsic_wo_chain:{ *:[v4i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU4_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_threeaddr), |
| 75641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75643 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75645 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75647 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75649 | GIR_RootConstrainSelectedInstOperands, |
| 75650 | // GIR_Coverage, 2433, |
| 75651 | GIR_EraseRootFromParent_Done, |
| 75652 | // Label 4142: @239014 |
| 75653 | GIM_Try, /*On fail goto*//*Label 4143*/ GIMT_Encode4(239095), // Rule ID 2443 // |
| 75654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75655 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4), |
| 75656 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75658 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75659 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75661 | // MIs[0] clamp |
| 75662 | // No operand predicates |
| 75663 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_wmmavisrc), |
| 75666 | // (intrinsic_wo_chain:{ *:[v4i32] } 3114:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, (WMMAVISrc:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$src2), i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X32_IU4_w64_threeaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_threeaddr), |
| 75668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75670 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75672 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 75674 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75676 | GIR_RootConstrainSelectedInstOperands, |
| 75677 | // GIR_Coverage, 2443, |
| 75678 | GIR_EraseRootFromParent_Done, |
| 75679 | // Label 4143: @239095 |
| 75680 | GIM_Try, /*On fail goto*//*Label 4144*/ GIMT_Encode4(239175), // Rule ID 2374 // |
| 75681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75682 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75683 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75684 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 75685 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 75686 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75687 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75688 | // MIs[0] clamp |
| 75689 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75690 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75692 | // (intrinsic_wo_chain:{ *:[v8i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_WMMA_I32_16X16X16_IU8_twoaddr_w32:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w32), |
| 75694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75696 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75698 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75700 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75701 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75704 | GIR_RootConstrainSelectedInstOperands, |
| 75705 | // GIR_Coverage, 2374, |
| 75706 | GIR_EraseRootFromParent_Done, |
| 75707 | // Label 4144: @239175 |
| 75708 | GIM_Try, /*On fail goto*//*Label 4145*/ GIMT_Encode4(239255), // Rule ID 2380 // |
| 75709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave32), |
| 75710 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75711 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75712 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75713 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75714 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75716 | // MIs[0] clamp |
| 75717 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75719 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75720 | // (intrinsic_wo_chain:{ *:[v8i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_WMMA_I32_16X16X16_IU4_twoaddr_w32:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w32), |
| 75722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75724 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75726 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75728 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75729 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75732 | GIR_RootConstrainSelectedInstOperands, |
| 75733 | // GIR_Coverage, 2380, |
| 75734 | GIR_EraseRootFromParent_Done, |
| 75735 | // Label 4145: @239255 |
| 75736 | GIM_Try, /*On fail goto*//*Label 4146*/ GIMT_Encode4(239335), // Rule ID 2387 // |
| 75737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75738 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75739 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75740 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 75741 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 75742 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75744 | // MIs[0] clamp |
| 75745 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75746 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75748 | // (intrinsic_wo_chain:{ *:[v4i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v4i32:{ *:[v4i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_WMMA_I32_16X16X16_IU8_twoaddr_w64:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, v4i32:{ *:[v4i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_twoaddr_w64), |
| 75750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75752 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75754 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75755 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75756 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75757 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75760 | GIR_RootConstrainSelectedInstOperands, |
| 75761 | // GIR_Coverage, 2387, |
| 75762 | GIR_EraseRootFromParent_Done, |
| 75763 | // Label 4146: @239335 |
| 75764 | GIM_Try, /*On fail goto*//*Label 4147*/ GIMT_Encode4(239415), // Rule ID 2388 // |
| 75765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Only_isWave64), |
| 75766 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75767 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75768 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75769 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75770 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75772 | // MIs[0] clamp |
| 75773 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75776 | // (intrinsic_wo_chain:{ *:[v4i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i1] }):$clamp) => (V_WMMA_I32_16X16X16_IU4_twoaddr_w64:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, 8:{ *:[i32] }, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_twoaddr_w64), |
| 75778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75780 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75782 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/8, |
| 75784 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75785 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75788 | GIR_RootConstrainSelectedInstOperands, |
| 75789 | // GIR_Coverage, 2388, |
| 75790 | GIR_EraseRootFromParent_Done, |
| 75791 | // Label 4147: @239415 |
| 75792 | GIM_Try, /*On fail goto*//*Label 4148*/ GIMT_Encode4(239486), // Rule ID 2397 // |
| 75793 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75794 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75795 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75796 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75797 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75798 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75800 | // MIs[0] clamp |
| 75801 | // No operand predicates |
| 75802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75803 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75804 | // (intrinsic_wo_chain:{ *:[v8i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU8_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w32_twoaddr), |
| 75806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75808 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75810 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75811 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75812 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75814 | GIR_RootConstrainSelectedInstOperands, |
| 75815 | // GIR_Coverage, 2397, |
| 75816 | GIR_EraseRootFromParent_Done, |
| 75817 | // Label 4148: @239486 |
| 75818 | GIM_Try, /*On fail goto*//*Label 4149*/ GIMT_Encode4(239557), // Rule ID 2399 // |
| 75819 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75820 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75821 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75822 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75823 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75824 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75826 | // MIs[0] clamp |
| 75827 | // No operand predicates |
| 75828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75829 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75830 | // (intrinsic_wo_chain:{ *:[v8i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w32_twoaddr), |
| 75832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75834 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75836 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75837 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75838 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75840 | GIR_RootConstrainSelectedInstOperands, |
| 75841 | // GIR_Coverage, 2399, |
| 75842 | GIR_EraseRootFromParent_Done, |
| 75843 | // Label 4149: @239557 |
| 75844 | GIM_Try, /*On fail goto*//*Label 4150*/ GIMT_Encode4(239628), // Rule ID 2409 // |
| 75845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 75846 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4), |
| 75847 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 75848 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 75849 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 75850 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 75851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 75852 | // MIs[0] clamp |
| 75853 | // No operand predicates |
| 75854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75855 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75856 | // (intrinsic_wo_chain:{ *:[v8i32] } 3114:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w32_twoaddr), |
| 75858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75860 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75862 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75863 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75864 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75866 | GIR_RootConstrainSelectedInstOperands, |
| 75867 | // GIR_Coverage, 2409, |
| 75868 | GIR_EraseRootFromParent_Done, |
| 75869 | // Label 4150: @239628 |
| 75870 | GIM_Try, /*On fail goto*//*Label 4151*/ GIMT_Encode4(239699), // Rule ID 2430 // |
| 75871 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75872 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu8), |
| 75873 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75874 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75875 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75876 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75878 | // MIs[0] clamp |
| 75879 | // No operand predicates |
| 75880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75882 | // (intrinsic_wo_chain:{ *:[v4i32] } 3113:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU8_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU8_w64_twoaddr), |
| 75884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75886 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75888 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75889 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75890 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75892 | GIR_RootConstrainSelectedInstOperands, |
| 75893 | // GIR_Coverage, 2430, |
| 75894 | GIR_EraseRootFromParent_Done, |
| 75895 | // Label 4151: @239699 |
| 75896 | GIM_Try, /*On fail goto*//*Label 4152*/ GIMT_Encode4(239770), // Rule ID 2432 // |
| 75897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75898 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x16_iu4), |
| 75899 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75900 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75901 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75902 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75903 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75904 | // MIs[0] clamp |
| 75905 | // No operand predicates |
| 75906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75908 | // (intrinsic_wo_chain:{ *:[v4i32] } 3112:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X16_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X16_IU4_w64_twoaddr), |
| 75910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75912 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75914 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75915 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75916 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75918 | GIR_RootConstrainSelectedInstOperands, |
| 75919 | // GIR_Coverage, 2432, |
| 75920 | GIR_EraseRootFromParent_Done, |
| 75921 | // Label 4152: @239770 |
| 75922 | GIM_Try, /*On fail goto*//*Label 4153*/ GIMT_Encode4(239841), // Rule ID 2442 // |
| 75923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 75924 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_wmma_i32_16x16x32_iu4), |
| 75925 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 75926 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75927 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 75928 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 75929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 75930 | // MIs[0] clamp |
| 75931 | // No operand predicates |
| 75932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 75934 | // (intrinsic_wo_chain:{ *:[v4i32] } 3114:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_WMMA_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 75935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_WMMA_I32_16X16X32_IU4_w64_twoaddr), |
| 75936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 75938 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 75939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 75940 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 75941 | GIR_RootToRootCopy, /*OpIdx*/6, // src2 |
| 75942 | GIR_RootToRootCopy, /*OpIdx*/7, // clamp |
| 75943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 75944 | GIR_RootConstrainSelectedInstOperands, |
| 75945 | // GIR_Coverage, 2442, |
| 75946 | GIR_EraseRootFromParent_Done, |
| 75947 | // Label 4153: @239841 |
| 75948 | GIM_Try, /*On fail goto*//*Label 4154*/ GIMT_Encode4(239914), // Rule ID 2092 // |
| 75949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 75950 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 75951 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 75952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75953 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75954 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 75955 | // MIs[0] dpp_ctrl |
| 75956 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 75957 | // MIs[0] row_mask |
| 75958 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75959 | // MIs[0] bank_mask |
| 75960 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75961 | // MIs[0] bound_ctrl |
| 75962 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75963 | // (intrinsic_wo_chain:{ *:[i32] } 3096:{ *:[iPTR] }, i32:{ *:[i32] }:$old, i32:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 75964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 75965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75966 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 75967 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 75968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 75969 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 75970 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 75971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 75972 | GIR_RootConstrainSelectedInstOperands, |
| 75973 | // GIR_Coverage, 2092, |
| 75974 | GIR_EraseRootFromParent_Done, |
| 75975 | // Label 4154: @239914 |
| 75976 | GIM_Try, /*On fail goto*//*Label 4155*/ GIMT_Encode4(239987), // Rule ID 2093 // |
| 75977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 75978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 75979 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 75980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 75981 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 75982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 75983 | // MIs[0] dpp_ctrl |
| 75984 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 75985 | // MIs[0] row_mask |
| 75986 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 75987 | // MIs[0] bank_mask |
| 75988 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 75989 | // MIs[0] bound_ctrl |
| 75990 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 75991 | // (intrinsic_wo_chain:{ *:[f32] } 3096:{ *:[iPTR] }, f32:{ *:[f32] }:$old, f32:{ *:[f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[f32] } VGPR_32:{ *:[f32] }:$old, VGPR_32:{ *:[f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 75992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 75993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 75994 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 75995 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 75996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 75997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 75998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 75999 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76000 | GIR_RootConstrainSelectedInstOperands, |
| 76001 | // GIR_Coverage, 2093, |
| 76002 | GIR_EraseRootFromParent_Done, |
| 76003 | // Label 4155: @239987 |
| 76004 | GIM_Try, /*On fail goto*//*Label 4156*/ GIMT_Encode4(240060), // Rule ID 2094 // |
| 76005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76006 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76007 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76011 | // MIs[0] dpp_ctrl |
| 76012 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76013 | // MIs[0] row_mask |
| 76014 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76015 | // MIs[0] bank_mask |
| 76016 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76017 | // MIs[0] bound_ctrl |
| 76018 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76019 | // (intrinsic_wo_chain:{ *:[v2i16] } 3096:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$old, v2i16:{ *:[v2i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[v2i16] } VGPR_32:{ *:[v2i16] }:$old, VGPR_32:{ *:[v2i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76022 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76023 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76024 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76025 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76026 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76028 | GIR_RootConstrainSelectedInstOperands, |
| 76029 | // GIR_Coverage, 2094, |
| 76030 | GIR_EraseRootFromParent_Done, |
| 76031 | // Label 4156: @240060 |
| 76032 | GIM_Try, /*On fail goto*//*Label 4157*/ GIMT_Encode4(240133), // Rule ID 2095 // |
| 76033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76034 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76035 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76036 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76037 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76039 | // MIs[0] dpp_ctrl |
| 76040 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76041 | // MIs[0] row_mask |
| 76042 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76043 | // MIs[0] bank_mask |
| 76044 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76045 | // MIs[0] bound_ctrl |
| 76046 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76047 | // (intrinsic_wo_chain:{ *:[v2f16] } 3096:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$old, v2f16:{ *:[v2f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$old, VGPR_32:{ *:[v2f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76050 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76051 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76052 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76053 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76054 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76055 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76056 | GIR_RootConstrainSelectedInstOperands, |
| 76057 | // GIR_Coverage, 2095, |
| 76058 | GIR_EraseRootFromParent_Done, |
| 76059 | // Label 4157: @240133 |
| 76060 | GIM_Try, /*On fail goto*//*Label 4158*/ GIMT_Encode4(240206), // Rule ID 2096 // |
| 76061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76062 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76063 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76065 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76067 | // MIs[0] dpp_ctrl |
| 76068 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76069 | // MIs[0] row_mask |
| 76070 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76071 | // MIs[0] bank_mask |
| 76072 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76073 | // MIs[0] bound_ctrl |
| 76074 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76075 | // (intrinsic_wo_chain:{ *:[v2bf16] } 3096:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$old, v2bf16:{ *:[v2bf16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[v2bf16] } VGPR_32:{ *:[v2bf16] }:$old, VGPR_32:{ *:[v2bf16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76078 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76079 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76080 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76081 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76082 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76083 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76084 | GIR_RootConstrainSelectedInstOperands, |
| 76085 | // GIR_Coverage, 2096, |
| 76086 | GIR_EraseRootFromParent_Done, |
| 76087 | // Label 4158: @240206 |
| 76088 | GIM_Try, /*On fail goto*//*Label 4159*/ GIMT_Encode4(240279), // Rule ID 2097 // |
| 76089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76090 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76091 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 76092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 76093 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32, |
| 76094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76095 | // MIs[0] dpp_ctrl |
| 76096 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76097 | // MIs[0] row_mask |
| 76098 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76099 | // MIs[0] bank_mask |
| 76100 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76101 | // MIs[0] bound_ctrl |
| 76102 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76103 | // (intrinsic_wo_chain:{ *:[i32] } 3096:{ *:[iPTR] }, p2:{ *:[i32] }:$old, p2:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76106 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76107 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76108 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76110 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76111 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76112 | GIR_RootConstrainSelectedInstOperands, |
| 76113 | // GIR_Coverage, 2097, |
| 76114 | GIR_EraseRootFromParent_Done, |
| 76115 | // Label 4159: @240279 |
| 76116 | GIM_Try, /*On fail goto*//*Label 4160*/ GIMT_Encode4(240352), // Rule ID 2098 // |
| 76117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76118 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76119 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 76120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 76121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32, |
| 76122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76123 | // MIs[0] dpp_ctrl |
| 76124 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76125 | // MIs[0] row_mask |
| 76126 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76127 | // MIs[0] bank_mask |
| 76128 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76129 | // MIs[0] bound_ctrl |
| 76130 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76131 | // (intrinsic_wo_chain:{ *:[i32] } 3096:{ *:[iPTR] }, p3:{ *:[i32] }:$old, p3:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76134 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76135 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76136 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76137 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76138 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76139 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76140 | GIR_RootConstrainSelectedInstOperands, |
| 76141 | // GIR_Coverage, 2098, |
| 76142 | GIR_EraseRootFromParent_Done, |
| 76143 | // Label 4160: @240352 |
| 76144 | GIM_Try, /*On fail goto*//*Label 4161*/ GIMT_Encode4(240425), // Rule ID 2099 // |
| 76145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76146 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76147 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 76148 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 76149 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32, |
| 76150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76151 | // MIs[0] dpp_ctrl |
| 76152 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76153 | // MIs[0] row_mask |
| 76154 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76155 | // MIs[0] bank_mask |
| 76156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76157 | // MIs[0] bound_ctrl |
| 76158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76159 | // (intrinsic_wo_chain:{ *:[i32] } 3096:{ *:[iPTR] }, p5:{ *:[i32] }:$old, p5:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76162 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76163 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76164 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76165 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76166 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76167 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76168 | GIR_RootConstrainSelectedInstOperands, |
| 76169 | // GIR_Coverage, 2099, |
| 76170 | GIR_EraseRootFromParent_Done, |
| 76171 | // Label 4161: @240425 |
| 76172 | GIM_Try, /*On fail goto*//*Label 4162*/ GIMT_Encode4(240498), // Rule ID 2100 // |
| 76173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 76174 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76175 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 76176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 76177 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32, |
| 76178 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76179 | // MIs[0] dpp_ctrl |
| 76180 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76181 | // MIs[0] row_mask |
| 76182 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76183 | // MIs[0] bank_mask |
| 76184 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76185 | // MIs[0] bound_ctrl |
| 76186 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76187 | // (intrinsic_wo_chain:{ *:[i32] } 3096:{ *:[iPTR] }, p6:{ *:[i32] }:$old, p6:{ *:[i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B32_dpp:{ *:[i32] } VGPR_32:{ *:[i32] }:$old, VGPR_32:{ *:[i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_dpp), |
| 76189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76190 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76191 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76192 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76193 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76194 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76196 | GIR_RootConstrainSelectedInstOperands, |
| 76197 | // GIR_Coverage, 2100, |
| 76198 | GIR_EraseRootFromParent_Done, |
| 76199 | // Label 4162: @240498 |
| 76200 | GIM_Try, /*On fail goto*//*Label 4163*/ GIMT_Encode4(240568), // Rule ID 7285 // |
| 76201 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76202 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 76203 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 76204 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 76205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76206 | // MIs[0] dpp_ctrl |
| 76207 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76208 | // MIs[0] row_mask |
| 76209 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76210 | // MIs[0] bank_mask |
| 76211 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76212 | // MIs[0] bound_ctrl |
| 76213 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76214 | // (intrinsic_wo_chain:{ *:[i64] } 3096:{ *:[iPTR] }, i64:{ *:[i64] }:$old, i64:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76217 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76218 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76219 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76220 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76221 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76222 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76223 | GIR_RootConstrainSelectedInstOperands, |
| 76224 | // GIR_Coverage, 7285, |
| 76225 | GIR_EraseRootFromParent_Done, |
| 76226 | // Label 4163: @240568 |
| 76227 | GIM_Try, /*On fail goto*//*Label 4164*/ GIMT_Encode4(240638), // Rule ID 7286 // |
| 76228 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76229 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 76230 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 76231 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 76232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76233 | // MIs[0] dpp_ctrl |
| 76234 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76235 | // MIs[0] row_mask |
| 76236 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76237 | // MIs[0] bank_mask |
| 76238 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76239 | // MIs[0] bound_ctrl |
| 76240 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76241 | // (intrinsic_wo_chain:{ *:[f64] } 3096:{ *:[iPTR] }, f64:{ *:[f64] }:$old, f64:{ *:[f64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[f64] } VReg_64_Align2:{ *:[f64] }:$old, VReg_64_Align2:{ *:[f64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76244 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76245 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76248 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76249 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76250 | GIR_RootConstrainSelectedInstOperands, |
| 76251 | // GIR_Coverage, 7286, |
| 76252 | GIR_EraseRootFromParent_Done, |
| 76253 | // Label 4164: @240638 |
| 76254 | GIM_Try, /*On fail goto*//*Label 4165*/ GIMT_Encode4(240708), // Rule ID 7287 // |
| 76255 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76256 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 76257 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 76258 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 76259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76260 | // MIs[0] dpp_ctrl |
| 76261 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76262 | // MIs[0] row_mask |
| 76263 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76264 | // MIs[0] bank_mask |
| 76265 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76266 | // MIs[0] bound_ctrl |
| 76267 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76268 | // (intrinsic_wo_chain:{ *:[v2i32] } 3096:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$old, v2i32:{ *:[v2i32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[v2i32] } VReg_64_Align2:{ *:[v2i32] }:$old, VReg_64_Align2:{ *:[v2i32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76271 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76272 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76273 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76274 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76277 | GIR_RootConstrainSelectedInstOperands, |
| 76278 | // GIR_Coverage, 7287, |
| 76279 | GIR_EraseRootFromParent_Done, |
| 76280 | // Label 4165: @240708 |
| 76281 | GIM_Try, /*On fail goto*//*Label 4166*/ GIMT_Encode4(240778), // Rule ID 7288 // |
| 76282 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76283 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 76284 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 76285 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 76286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76287 | // MIs[0] dpp_ctrl |
| 76288 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76289 | // MIs[0] row_mask |
| 76290 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76291 | // MIs[0] bank_mask |
| 76292 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76293 | // MIs[0] bound_ctrl |
| 76294 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76295 | // (intrinsic_wo_chain:{ *:[v2f32] } 3096:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$old, v2f32:{ *:[v2f32] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[v2f32] } VReg_64_Align2:{ *:[v2f32] }:$old, VReg_64_Align2:{ *:[v2f32] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76298 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76299 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76301 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76302 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76303 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76304 | GIR_RootConstrainSelectedInstOperands, |
| 76305 | // GIR_Coverage, 7288, |
| 76306 | GIR_EraseRootFromParent_Done, |
| 76307 | // Label 4166: @240778 |
| 76308 | GIM_Try, /*On fail goto*//*Label 4167*/ GIMT_Encode4(240848), // Rule ID 7289 // |
| 76309 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76310 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p0s64, |
| 76311 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p0s64, |
| 76312 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p0s64, |
| 76313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76314 | // MIs[0] dpp_ctrl |
| 76315 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76316 | // MIs[0] row_mask |
| 76317 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76318 | // MIs[0] bank_mask |
| 76319 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76320 | // MIs[0] bound_ctrl |
| 76321 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76322 | // (intrinsic_wo_chain:{ *:[i64] } 3096:{ *:[iPTR] }, p0:{ *:[i64] }:$old, p0:{ *:[i64] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[i64] } VReg_64_Align2:{ *:[i64] }:$old, VReg_64_Align2:{ *:[i64] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76325 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76326 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76327 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76328 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76329 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76330 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76331 | GIR_RootConstrainSelectedInstOperands, |
| 76332 | // GIR_Coverage, 7289, |
| 76333 | GIR_EraseRootFromParent_Done, |
| 76334 | // Label 4167: @240848 |
| 76335 | GIM_Try, /*On fail goto*//*Label 4168*/ GIMT_Encode4(240918), // Rule ID 7290 // |
| 76336 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76337 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 76338 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 76339 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 76340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76341 | // MIs[0] dpp_ctrl |
| 76342 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76343 | // MIs[0] row_mask |
| 76344 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76345 | // MIs[0] bank_mask |
| 76346 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76347 | // MIs[0] bound_ctrl |
| 76348 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76349 | // (intrinsic_wo_chain:{ *:[v4i16] } 3096:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$old, v4i16:{ *:[v4i16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[v4i16] } VReg_64_Align2:{ *:[v4i16] }:$old, VReg_64_Align2:{ *:[v4i16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76352 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76353 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76354 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76355 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76356 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76357 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76358 | GIR_RootConstrainSelectedInstOperands, |
| 76359 | // GIR_Coverage, 7290, |
| 76360 | GIR_EraseRootFromParent_Done, |
| 76361 | // Label 4168: @240918 |
| 76362 | GIM_Try, /*On fail goto*//*Label 4169*/ GIMT_Encode4(240988), // Rule ID 7291 // |
| 76363 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76364 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 76365 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 76366 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 76367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76368 | // MIs[0] dpp_ctrl |
| 76369 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76370 | // MIs[0] row_mask |
| 76371 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76372 | // MIs[0] bank_mask |
| 76373 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76374 | // MIs[0] bound_ctrl |
| 76375 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76376 | // (intrinsic_wo_chain:{ *:[v4f16] } 3096:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$old, v4f16:{ *:[v4f16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[v4f16] } VReg_64_Align2:{ *:[v4f16] }:$old, VReg_64_Align2:{ *:[v4f16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76379 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76380 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76381 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76384 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76385 | GIR_RootConstrainSelectedInstOperands, |
| 76386 | // GIR_Coverage, 7291, |
| 76387 | GIR_EraseRootFromParent_Done, |
| 76388 | // Label 4169: @240988 |
| 76389 | GIM_Try, /*On fail goto*//*Label 4170*/ GIMT_Encode4(241058), // Rule ID 7292 // |
| 76390 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_update_dpp), |
| 76391 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 76392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 76393 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 76394 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 76395 | // MIs[0] dpp_ctrl |
| 76396 | GIM_CheckIsImm, /*MI*/0, /*Op*/4, |
| 76397 | // MIs[0] row_mask |
| 76398 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76399 | // MIs[0] bank_mask |
| 76400 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76401 | // MIs[0] bound_ctrl |
| 76402 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76403 | // (intrinsic_wo_chain:{ *:[v4bf16] } 3096:{ *:[iPTR] }, v4bf16:{ *:[v4bf16] }:$old, v4bf16:{ *:[v4bf16] }:$src, (timm:{ *:[i32] }):$dpp_ctrl, (timm:{ *:[i32] }):$row_mask, (timm:{ *:[i32] }):$bank_mask, (timm:{ *:[i1] }):$bound_ctrl) => (V_MOV_B64_DPP_PSEUDO:{ *:[v4bf16] } VReg_64_Align2:{ *:[v4bf16] }:$old, VReg_64_Align2:{ *:[v4bf16] }:$src, (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$dpp_ctrl), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$row_mask), (as_i32timm:{ *:[i32] } ?:{ *:[i32] }:$bank_mask), (as_i1timm:{ *:[i1] } ?:{ *:[i1] }:$bound_ctrl)) |
| 76404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_DPP_PSEUDO), |
| 76405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76406 | GIR_RootToRootCopy, /*OpIdx*/2, // old |
| 76407 | GIR_RootToRootCopy, /*OpIdx*/3, // src |
| 76408 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/4, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // dpp_ctrl |
| 76409 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/5, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // row_mask |
| 76410 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bank_mask |
| 76411 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // bound_ctrl |
| 76412 | GIR_RootConstrainSelectedInstOperands, |
| 76413 | // GIR_Coverage, 7292, |
| 76414 | GIR_EraseRootFromParent_Done, |
| 76415 | // Label 4170: @241058 |
| 76416 | GIM_Try, /*On fail goto*//*Label 4171*/ GIMT_Encode4(241129), // Rule ID 2249 // |
| 76417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76418 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76419 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 76420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76422 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76423 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76425 | // MIs[0] fi |
| 76426 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76427 | // MIs[0] bc |
| 76428 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76429 | // (intrinsic_wo_chain:{ *:[i32] } 2885:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76433 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76434 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76435 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76437 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76438 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76440 | GIR_RootConstrainSelectedInstOperands, |
| 76441 | // GIR_Coverage, 2249, |
| 76442 | GIR_EraseRootFromParent_Done, |
| 76443 | // Label 4171: @241129 |
| 76444 | GIM_Try, /*On fail goto*//*Label 4172*/ GIMT_Encode4(241200), // Rule ID 2250 // |
| 76445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76446 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76447 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 76448 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76449 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76450 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76451 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76453 | // MIs[0] fi |
| 76454 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76455 | // MIs[0] bc |
| 76456 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76457 | // (intrinsic_wo_chain:{ *:[i32] } 2888:{ *:[iPTR] }, i32:{ *:[i32] }:$vdst_in, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76460 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76461 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76462 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76463 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76465 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76466 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76468 | GIR_RootConstrainSelectedInstOperands, |
| 76469 | // GIR_Coverage, 2250, |
| 76470 | GIR_EraseRootFromParent_Done, |
| 76471 | // Label 4172: @241200 |
| 76472 | GIM_Try, /*On fail goto*//*Label 4173*/ GIMT_Encode4(241271), // Rule ID 2251 // |
| 76473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76474 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76475 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 76476 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76477 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76478 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76479 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76481 | // MIs[0] fi |
| 76482 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76483 | // MIs[0] bc |
| 76484 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76485 | // (intrinsic_wo_chain:{ *:[f32] } 2885:{ *:[iPTR] }, f32:{ *:[f32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[f32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[f32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[f32] }:$vdst_in) |
| 76486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76488 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76489 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76490 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76491 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76493 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76494 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76496 | GIR_RootConstrainSelectedInstOperands, |
| 76497 | // GIR_Coverage, 2251, |
| 76498 | GIR_EraseRootFromParent_Done, |
| 76499 | // Label 4173: @241271 |
| 76500 | GIM_Try, /*On fail goto*//*Label 4174*/ GIMT_Encode4(241342), // Rule ID 2252 // |
| 76501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76502 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76503 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 76504 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76505 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76506 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76507 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76509 | // MIs[0] fi |
| 76510 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76511 | // MIs[0] bc |
| 76512 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76513 | // (intrinsic_wo_chain:{ *:[f32] } 2888:{ *:[iPTR] }, f32:{ *:[f32] }:$vdst_in, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[f32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[f32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[f32] }:$vdst_in) |
| 76514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76516 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76517 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76518 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76519 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76521 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76522 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76524 | GIR_RootConstrainSelectedInstOperands, |
| 76525 | // GIR_Coverage, 2252, |
| 76526 | GIR_EraseRootFromParent_Done, |
| 76527 | // Label 4174: @241342 |
| 76528 | GIM_Try, /*On fail goto*//*Label 4175*/ GIMT_Encode4(241413), // Rule ID 2253 // |
| 76529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76530 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76531 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76534 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76535 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76536 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76537 | // MIs[0] fi |
| 76538 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76539 | // MIs[0] bc |
| 76540 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76541 | // (intrinsic_wo_chain:{ *:[v2i16] } 2885:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[v2i16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2i16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in) |
| 76542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76545 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76546 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76547 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76549 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76550 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76552 | GIR_RootConstrainSelectedInstOperands, |
| 76553 | // GIR_Coverage, 2253, |
| 76554 | GIR_EraseRootFromParent_Done, |
| 76555 | // Label 4175: @241413 |
| 76556 | GIM_Try, /*On fail goto*//*Label 4176*/ GIMT_Encode4(241484), // Rule ID 2254 // |
| 76557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76558 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76559 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76560 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76561 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76562 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76563 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76565 | // MIs[0] fi |
| 76566 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76567 | // MIs[0] bc |
| 76568 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76569 | // (intrinsic_wo_chain:{ *:[v2i16] } 2888:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$vdst_in, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[v2i16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2i16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2i16] }:$vdst_in) |
| 76570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76573 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76574 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76575 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76577 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76578 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76580 | GIR_RootConstrainSelectedInstOperands, |
| 76581 | // GIR_Coverage, 2254, |
| 76582 | GIR_EraseRootFromParent_Done, |
| 76583 | // Label 4176: @241484 |
| 76584 | GIM_Try, /*On fail goto*//*Label 4177*/ GIMT_Encode4(241555), // Rule ID 2255 // |
| 76585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76586 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76587 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76588 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76589 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76590 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76591 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76593 | // MIs[0] fi |
| 76594 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76595 | // MIs[0] bc |
| 76596 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76597 | // (intrinsic_wo_chain:{ *:[v2f16] } 2885:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[v2f16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2f16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2f16] }:$vdst_in) |
| 76598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76600 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76601 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76602 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76603 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76605 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76606 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76608 | GIR_RootConstrainSelectedInstOperands, |
| 76609 | // GIR_Coverage, 2255, |
| 76610 | GIR_EraseRootFromParent_Done, |
| 76611 | // Label 4177: @241555 |
| 76612 | GIM_Try, /*On fail goto*//*Label 4178*/ GIMT_Encode4(241626), // Rule ID 2256 // |
| 76613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76614 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76615 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76616 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76617 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76618 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76619 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76621 | // MIs[0] fi |
| 76622 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76623 | // MIs[0] bc |
| 76624 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76625 | // (intrinsic_wo_chain:{ *:[v2f16] } 2888:{ *:[iPTR] }, v2f16:{ *:[v2f16] }:$vdst_in, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[v2f16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2f16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2f16] }:$vdst_in) |
| 76626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76628 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76629 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76630 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76631 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76633 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76634 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76636 | GIR_RootConstrainSelectedInstOperands, |
| 76637 | // GIR_Coverage, 2256, |
| 76638 | GIR_EraseRootFromParent_Done, |
| 76639 | // Label 4178: @241626 |
| 76640 | GIM_Try, /*On fail goto*//*Label 4179*/ GIMT_Encode4(241697), // Rule ID 2257 // |
| 76641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76642 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76643 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76644 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76645 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76646 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76647 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76649 | // MIs[0] fi |
| 76650 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76651 | // MIs[0] bc |
| 76652 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76653 | // (intrinsic_wo_chain:{ *:[v2bf16] } 2885:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$vdst_in, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[v2bf16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2bf16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2bf16] }:$vdst_in) |
| 76654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76656 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76657 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76658 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76659 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76661 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76662 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76664 | GIR_RootConstrainSelectedInstOperands, |
| 76665 | // GIR_Coverage, 2257, |
| 76666 | GIR_EraseRootFromParent_Done, |
| 76667 | // Label 4179: @241697 |
| 76668 | GIM_Try, /*On fail goto*//*Label 4180*/ GIMT_Encode4(241768), // Rule ID 2258 // |
| 76669 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76670 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76671 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 76672 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 76673 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 76674 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76675 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76677 | // MIs[0] fi |
| 76678 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76679 | // MIs[0] bc |
| 76680 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76681 | // (intrinsic_wo_chain:{ *:[v2bf16] } 2888:{ *:[iPTR] }, v2bf16:{ *:[v2bf16] }:$vdst_in, v2bf16:{ *:[v2bf16] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[v2bf16] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[v2bf16] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[v2bf16] }:$vdst_in) |
| 76682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76684 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76685 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76686 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76687 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76689 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76690 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76692 | GIR_RootConstrainSelectedInstOperands, |
| 76693 | // GIR_Coverage, 2258, |
| 76694 | GIR_EraseRootFromParent_Done, |
| 76695 | // Label 4180: @241768 |
| 76696 | GIM_Try, /*On fail goto*//*Label 4181*/ GIMT_Encode4(241839), // Rule ID 2259 // |
| 76697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76698 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76699 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 76700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 76701 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32, |
| 76702 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76703 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76705 | // MIs[0] fi |
| 76706 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76707 | // MIs[0] bc |
| 76708 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76709 | // (intrinsic_wo_chain:{ *:[i32] } 2885:{ *:[iPTR] }, p2:{ *:[i32] }:$vdst_in, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76712 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76713 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76714 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76715 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76717 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76718 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76720 | GIR_RootConstrainSelectedInstOperands, |
| 76721 | // GIR_Coverage, 2259, |
| 76722 | GIR_EraseRootFromParent_Done, |
| 76723 | // Label 4181: @241839 |
| 76724 | GIM_Try, /*On fail goto*//*Label 4182*/ GIMT_Encode4(241910), // Rule ID 2260 // |
| 76725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76726 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76727 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p2s32, |
| 76728 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p2s32, |
| 76729 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p2s32, |
| 76730 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76731 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76733 | // MIs[0] fi |
| 76734 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76735 | // MIs[0] bc |
| 76736 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76737 | // (intrinsic_wo_chain:{ *:[i32] } 2888:{ *:[iPTR] }, p2:{ *:[i32] }:$vdst_in, p2:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76741 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76742 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76743 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76745 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76746 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76748 | GIR_RootConstrainSelectedInstOperands, |
| 76749 | // GIR_Coverage, 2260, |
| 76750 | GIR_EraseRootFromParent_Done, |
| 76751 | // Label 4182: @241910 |
| 76752 | GIM_Try, /*On fail goto*//*Label 4183*/ GIMT_Encode4(241981), // Rule ID 2261 // |
| 76753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76754 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76755 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 76756 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 76757 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32, |
| 76758 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76759 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76761 | // MIs[0] fi |
| 76762 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76763 | // MIs[0] bc |
| 76764 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76765 | // (intrinsic_wo_chain:{ *:[i32] } 2885:{ *:[iPTR] }, p3:{ *:[i32] }:$vdst_in, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76768 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76769 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76770 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76771 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76773 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76774 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76776 | GIR_RootConstrainSelectedInstOperands, |
| 76777 | // GIR_Coverage, 2261, |
| 76778 | GIR_EraseRootFromParent_Done, |
| 76779 | // Label 4183: @241981 |
| 76780 | GIM_Try, /*On fail goto*//*Label 4184*/ GIMT_Encode4(242052), // Rule ID 2262 // |
| 76781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76782 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76783 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p3s32, |
| 76784 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p3s32, |
| 76785 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p3s32, |
| 76786 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76787 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76789 | // MIs[0] fi |
| 76790 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76791 | // MIs[0] bc |
| 76792 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76793 | // (intrinsic_wo_chain:{ *:[i32] } 2888:{ *:[iPTR] }, p3:{ *:[i32] }:$vdst_in, p3:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76796 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76797 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76798 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76799 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76801 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76802 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76804 | GIR_RootConstrainSelectedInstOperands, |
| 76805 | // GIR_Coverage, 2262, |
| 76806 | GIR_EraseRootFromParent_Done, |
| 76807 | // Label 4184: @242052 |
| 76808 | GIM_Try, /*On fail goto*//*Label 4185*/ GIMT_Encode4(242123), // Rule ID 2263 // |
| 76809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76810 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76811 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 76812 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 76813 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32, |
| 76814 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76815 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76817 | // MIs[0] fi |
| 76818 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76819 | // MIs[0] bc |
| 76820 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76821 | // (intrinsic_wo_chain:{ *:[i32] } 2885:{ *:[iPTR] }, p5:{ *:[i32] }:$vdst_in, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76824 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76825 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76826 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76827 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76829 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76830 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76832 | GIR_RootConstrainSelectedInstOperands, |
| 76833 | // GIR_Coverage, 2263, |
| 76834 | GIR_EraseRootFromParent_Done, |
| 76835 | // Label 4185: @242123 |
| 76836 | GIM_Try, /*On fail goto*//*Label 4186*/ GIMT_Encode4(242194), // Rule ID 2264 // |
| 76837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76838 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76839 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p5s32, |
| 76840 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p5s32, |
| 76841 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p5s32, |
| 76842 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76843 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76845 | // MIs[0] fi |
| 76846 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76847 | // MIs[0] bc |
| 76848 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76849 | // (intrinsic_wo_chain:{ *:[i32] } 2888:{ *:[iPTR] }, p5:{ *:[i32] }:$vdst_in, p5:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76852 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76853 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76855 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76857 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76858 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76860 | GIR_RootConstrainSelectedInstOperands, |
| 76861 | // GIR_Coverage, 2264, |
| 76862 | GIR_EraseRootFromParent_Done, |
| 76863 | // Label 4186: @242194 |
| 76864 | GIM_Try, /*On fail goto*//*Label 4187*/ GIMT_Encode4(242265), // Rule ID 2265 // |
| 76865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76866 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlane16), |
| 76867 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 76868 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 76869 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32, |
| 76870 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76871 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76873 | // MIs[0] fi |
| 76874 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76875 | // MIs[0] bc |
| 76876 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76877 | // (intrinsic_wo_chain:{ *:[i32] } 2885:{ *:[iPTR] }, p6:{ *:[i32] }:$vdst_in, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANE16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANE16_B32_e64), |
| 76879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76880 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76881 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76882 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76883 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76885 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76886 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76888 | GIR_RootConstrainSelectedInstOperands, |
| 76889 | // GIR_Coverage, 2265, |
| 76890 | GIR_EraseRootFromParent_Done, |
| 76891 | // Label 4187: @242265 |
| 76892 | GIM_Try, /*On fail goto*//*Label 4188*/ GIMT_Encode4(242336), // Rule ID 2266 // |
| 76893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 76894 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_permlanex16), |
| 76895 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_p6s32, |
| 76896 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_p6s32, |
| 76897 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_p6s32, |
| 76898 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 76899 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 76900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 76901 | // MIs[0] fi |
| 76902 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76903 | // MIs[0] bc |
| 76904 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76905 | // (intrinsic_wo_chain:{ *:[i32] } 2888:{ *:[iPTR] }, p6:{ *:[i32] }:$vdst_in, p6:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2, (timm:{ *:[i1] }):$fi, (timm:{ *:[i1] }):$bc) => (V_PERMLANEX16_B32_e64:{ *:[i32] } (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$fi), VGPR_32:{ *:[i32] }:$src0, (opsel_i1timm:{ *:[i32] } ?:{ *:[i1] }:$bc), SCSrc_b32:{ *:[i32] }:$src1, 0:{ *:[i32] }, SCSrc_b32:{ *:[i32] }:$src2, VGPR_32:{ *:[i32] }:$vdst_in) |
| 76906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERMLANEX16_B32_e64), |
| 76907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76908 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // fi |
| 76909 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 76910 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderOpSelTImm), // bc |
| 76911 | GIR_RootToRootCopy, /*OpIdx*/4, // src1 |
| 76912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76913 | GIR_RootToRootCopy, /*OpIdx*/5, // src2 |
| 76914 | GIR_RootToRootCopy, /*OpIdx*/2, // vdst_in |
| 76915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 76916 | GIR_RootConstrainSelectedInstOperands, |
| 76917 | // GIR_Coverage, 2266, |
| 76918 | GIR_EraseRootFromParent_Done, |
| 76919 | // Label 4188: @242336 |
| 76920 | GIM_Try, /*On fail goto*//*Label 4189*/ GIMT_Encode4(242397), // Rule ID 989 // |
| 76921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 76922 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32), |
| 76923 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 76924 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76925 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76926 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 76927 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 76928 | // MIs[0] cbsz |
| 76929 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76930 | // MIs[0] abid |
| 76931 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76932 | // MIs[0] blgp |
| 76933 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76934 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25064), |
| 76935 | // (intrinsic_wo_chain:{ *:[v4f32] } 2862:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25064>> => (V_MFMA_F32_4X4X1F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 76936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_e64), |
| 76937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76938 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 76939 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 76940 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 76941 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 76942 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 76943 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 76944 | GIR_RootConstrainSelectedInstOperands, |
| 76945 | // GIR_Coverage, 989, |
| 76946 | GIR_EraseRootFromParent_Done, |
| 76947 | // Label 4189: @242397 |
| 76948 | GIM_Try, /*On fail goto*//*Label 4190*/ GIMT_Encode4(242458), // Rule ID 990 // |
| 76949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 76950 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x1f32), |
| 76951 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 76952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76953 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76954 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 76955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 76956 | // MIs[0] cbsz |
| 76957 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76958 | // MIs[0] abid |
| 76959 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76960 | // MIs[0] blgp |
| 76961 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76962 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25066), |
| 76963 | // (intrinsic_wo_chain:{ *:[v4f32] } 2862:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25066>> => (V_MFMA_F32_4X4X1F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 76964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X1F32_vgprcd_e64), |
| 76965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76966 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 76967 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 76968 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 76969 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 76970 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 76971 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 76972 | GIR_RootConstrainSelectedInstOperands, |
| 76973 | // GIR_Coverage, 990, |
| 76974 | GIR_EraseRootFromParent_Done, |
| 76975 | // Label 4190: @242458 |
| 76976 | GIM_Try, /*On fail goto*//*Label 4191*/ GIMT_Encode4(242519), // Rule ID 991 // |
| 76977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 76978 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32), |
| 76979 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 76980 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 76981 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 76982 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 76983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 76984 | // MIs[0] cbsz |
| 76985 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 76986 | // MIs[0] abid |
| 76987 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 76988 | // MIs[0] blgp |
| 76989 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 76990 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25070), |
| 76991 | // (intrinsic_wo_chain:{ *:[v16f32] } 2838:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25070>> => (V_MFMA_F32_16X16X1F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 76992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_e64), |
| 76993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 76994 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 76995 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 76996 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 76997 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 76998 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 76999 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77000 | GIR_RootConstrainSelectedInstOperands, |
| 77001 | // GIR_Coverage, 991, |
| 77002 | GIR_EraseRootFromParent_Done, |
| 77003 | // Label 4191: @242519 |
| 77004 | GIM_Try, /*On fail goto*//*Label 4192*/ GIMT_Encode4(242580), // Rule ID 992 // |
| 77005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77006 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x1f32), |
| 77007 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77010 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77011 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77012 | // MIs[0] cbsz |
| 77013 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77014 | // MIs[0] abid |
| 77015 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77016 | // MIs[0] blgp |
| 77017 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77018 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25072), |
| 77019 | // (intrinsic_wo_chain:{ *:[v16f32] } 2838:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25072>> => (V_MFMA_F32_16X16X1F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X1F32_mac_vgprcd_e64), |
| 77021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77022 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77023 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77024 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77025 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77026 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77027 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77028 | GIR_RootConstrainSelectedInstOperands, |
| 77029 | // GIR_Coverage, 992, |
| 77030 | GIR_EraseRootFromParent_Done, |
| 77031 | // Label 4192: @242580 |
| 77032 | GIM_Try, /*On fail goto*//*Label 4193*/ GIMT_Encode4(242641), // Rule ID 993 // |
| 77033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77034 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32), |
| 77035 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77036 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77037 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77038 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77040 | // MIs[0] cbsz |
| 77041 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77042 | // MIs[0] abid |
| 77043 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77044 | // MIs[0] blgp |
| 77045 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77046 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25074), |
| 77047 | // (intrinsic_wo_chain:{ *:[v4f32] } 2846:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25074>> => (V_MFMA_F32_16X16X4F32_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_e64), |
| 77049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77050 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77051 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77052 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77053 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77054 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77055 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77056 | GIR_RootConstrainSelectedInstOperands, |
| 77057 | // GIR_Coverage, 993, |
| 77058 | GIR_EraseRootFromParent_Done, |
| 77059 | // Label 4193: @242641 |
| 77060 | GIM_Try, /*On fail goto*//*Label 4194*/ GIMT_Encode4(242702), // Rule ID 994 // |
| 77061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77062 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f32), |
| 77063 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77065 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77066 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77068 | // MIs[0] cbsz |
| 77069 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77070 | // MIs[0] abid |
| 77071 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77072 | // MIs[0] blgp |
| 77073 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77074 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25076), |
| 77075 | // (intrinsic_wo_chain:{ *:[v4f32] } 2846:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25076>> => (V_MFMA_F32_16X16X4F32_vgprcd_e64:{ *:[v4f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77076 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F32_vgprcd_e64), |
| 77077 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77078 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77079 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77080 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77081 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77082 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77083 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77084 | GIR_RootConstrainSelectedInstOperands, |
| 77085 | // GIR_Coverage, 994, |
| 77086 | GIR_EraseRootFromParent_Done, |
| 77087 | // Label 4194: @242702 |
| 77088 | GIM_Try, /*On fail goto*//*Label 4195*/ GIMT_Encode4(242763), // Rule ID 995 // |
| 77089 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77090 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32), |
| 77091 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77092 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77093 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77094 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID), |
| 77096 | // MIs[0] cbsz |
| 77097 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77098 | // MIs[0] abid |
| 77099 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77100 | // MIs[0] blgp |
| 77101 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77102 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25080), |
| 77103 | // (intrinsic_wo_chain:{ *:[v32f32] } 2853:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25080>> => (V_MFMA_F32_32X32X1F32_mac_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_e64), |
| 77105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77106 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77107 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77108 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77109 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77110 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77111 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77112 | GIR_RootConstrainSelectedInstOperands, |
| 77113 | // GIR_Coverage, 995, |
| 77114 | GIR_EraseRootFromParent_Done, |
| 77115 | // Label 4195: @242763 |
| 77116 | GIM_Try, /*On fail goto*//*Label 4196*/ GIMT_Encode4(242824), // Rule ID 996 // |
| 77117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77118 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x1f32), |
| 77119 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77120 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77121 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77122 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 77124 | // MIs[0] cbsz |
| 77125 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77126 | // MIs[0] abid |
| 77127 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77128 | // MIs[0] blgp |
| 77129 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77130 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25082), |
| 77131 | // (intrinsic_wo_chain:{ *:[v32f32] } 2853:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25082>> => (V_MFMA_F32_32X32X1F32_mac_vgprcd_e64:{ *:[v32f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X1F32_mac_vgprcd_e64), |
| 77133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77134 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77135 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77136 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77137 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77138 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77139 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77140 | GIR_RootConstrainSelectedInstOperands, |
| 77141 | // GIR_Coverage, 996, |
| 77142 | GIR_EraseRootFromParent_Done, |
| 77143 | // Label 4196: @242824 |
| 77144 | GIM_Try, /*On fail goto*//*Label 4197*/ GIMT_Encode4(242885), // Rule ID 997 // |
| 77145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77146 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32), |
| 77147 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77148 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77149 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77150 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77152 | // MIs[0] cbsz |
| 77153 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77154 | // MIs[0] abid |
| 77155 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77156 | // MIs[0] blgp |
| 77157 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77158 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25084), |
| 77159 | // (intrinsic_wo_chain:{ *:[v16f32] } 2855:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25084>> => (V_MFMA_F32_32X32X2F32_mac_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_e64), |
| 77161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77162 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77163 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77164 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77165 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77166 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77167 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77168 | GIR_RootConstrainSelectedInstOperands, |
| 77169 | // GIR_Coverage, 997, |
| 77170 | GIR_EraseRootFromParent_Done, |
| 77171 | // Label 4197: @242885 |
| 77172 | GIM_Try, /*On fail goto*//*Label 4198*/ GIMT_Encode4(242946), // Rule ID 998 // |
| 77173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77174 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2f32), |
| 77175 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77176 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77177 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77178 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77180 | // MIs[0] cbsz |
| 77181 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77182 | // MIs[0] abid |
| 77183 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77184 | // MIs[0] blgp |
| 77185 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77186 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25086), |
| 77187 | // (intrinsic_wo_chain:{ *:[v16f32] } 2855:{ *:[iPTR] }, f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25086>> => (V_MFMA_F32_32X32X2F32_mac_vgprcd_e64:{ *:[v16f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2F32_mac_vgprcd_e64), |
| 77189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77190 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77191 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77192 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77193 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77194 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77195 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77196 | GIR_RootConstrainSelectedInstOperands, |
| 77197 | // GIR_Coverage, 998, |
| 77198 | GIR_EraseRootFromParent_Done, |
| 77199 | // Label 4198: @242946 |
| 77200 | GIM_Try, /*On fail goto*//*Label 4199*/ GIMT_Encode4(243007), // Rule ID 999 // |
| 77201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77202 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16), |
| 77203 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77204 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77205 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77206 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77208 | // MIs[0] cbsz |
| 77209 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77210 | // MIs[0] abid |
| 77211 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77212 | // MIs[0] blgp |
| 77213 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77214 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25088), |
| 77215 | // (intrinsic_wo_chain:{ *:[v4f32] } 2865:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25088>> => (V_MFMA_F32_4X4X4F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_e64), |
| 77217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77218 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77219 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77220 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77221 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77222 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77223 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77224 | GIR_RootConstrainSelectedInstOperands, |
| 77225 | // GIR_Coverage, 999, |
| 77226 | GIR_EraseRootFromParent_Done, |
| 77227 | // Label 4199: @243007 |
| 77228 | GIM_Try, /*On fail goto*//*Label 4200*/ GIMT_Encode4(243068), // Rule ID 1000 // |
| 77229 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77230 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4f16), |
| 77231 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77232 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77233 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77234 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77235 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77236 | // MIs[0] cbsz |
| 77237 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77238 | // MIs[0] abid |
| 77239 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77240 | // MIs[0] blgp |
| 77241 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77242 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25090), |
| 77243 | // (intrinsic_wo_chain:{ *:[v4f32] } 2865:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25090>> => (V_MFMA_F32_4X4X4F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4F16_vgprcd_e64), |
| 77245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77246 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77247 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77248 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77249 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77250 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77251 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77252 | GIR_RootConstrainSelectedInstOperands, |
| 77253 | // GIR_Coverage, 1000, |
| 77254 | GIR_EraseRootFromParent_Done, |
| 77255 | // Label 4200: @243068 |
| 77256 | GIM_Try, /*On fail goto*//*Label 4201*/ GIMT_Encode4(243129), // Rule ID 1001 // |
| 77257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77258 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8), |
| 77259 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77260 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77261 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77262 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77264 | // MIs[0] cbsz |
| 77265 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77266 | // MIs[0] abid |
| 77267 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77268 | // MIs[0] blgp |
| 77269 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77270 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25092), |
| 77271 | // (intrinsic_wo_chain:{ *:[v4i32] } 2874:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25092>> => (V_MFMA_I32_4X4X4I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_e64), |
| 77273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77274 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77275 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77276 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77277 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77278 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77279 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77280 | GIR_RootConstrainSelectedInstOperands, |
| 77281 | // GIR_Coverage, 1001, |
| 77282 | GIR_EraseRootFromParent_Done, |
| 77283 | // Label 4201: @243129 |
| 77284 | GIM_Try, /*On fail goto*//*Label 4202*/ GIMT_Encode4(243190), // Rule ID 1002 // |
| 77285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77286 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_4x4x4i8), |
| 77287 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77288 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77289 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77290 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77292 | // MIs[0] cbsz |
| 77293 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77294 | // MIs[0] abid |
| 77295 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77296 | // MIs[0] blgp |
| 77297 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77298 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25094), |
| 77299 | // (intrinsic_wo_chain:{ *:[v4i32] } 2874:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25094>> => (V_MFMA_I32_4X4X4I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_4X4X4I8_vgprcd_e64), |
| 77301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77302 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77303 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77304 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77305 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77306 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77307 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77308 | GIR_RootConstrainSelectedInstOperands, |
| 77309 | // GIR_Coverage, 1002, |
| 77310 | GIR_EraseRootFromParent_Done, |
| 77311 | // Label 4202: @243190 |
| 77312 | GIM_Try, /*On fail goto*//*Label 4203*/ GIMT_Encode4(243251), // Rule ID 1003 // |
| 77313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77314 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16), |
| 77315 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77317 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77318 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77320 | // MIs[0] cbsz |
| 77321 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77322 | // MIs[0] abid |
| 77323 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77324 | // MIs[0] blgp |
| 77325 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25098), |
| 77327 | // (intrinsic_wo_chain:{ *:[v16f32] } 2845:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25098>> => (V_MFMA_F32_16X16X4F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_e64), |
| 77329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77330 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77331 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77332 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77333 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77334 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77335 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77336 | GIR_RootConstrainSelectedInstOperands, |
| 77337 | // GIR_Coverage, 1003, |
| 77338 | GIR_EraseRootFromParent_Done, |
| 77339 | // Label 4203: @243251 |
| 77340 | GIM_Try, /*On fail goto*//*Label 4204*/ GIMT_Encode4(243312), // Rule ID 1004 // |
| 77341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77342 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4f16), |
| 77343 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77344 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77345 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77346 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77348 | // MIs[0] cbsz |
| 77349 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77350 | // MIs[0] abid |
| 77351 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77352 | // MIs[0] blgp |
| 77353 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77354 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25100), |
| 77355 | // (intrinsic_wo_chain:{ *:[v16f32] } 2845:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25100>> => (V_MFMA_F32_16X16X4F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4F16_mac_vgprcd_e64), |
| 77357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77358 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77359 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77360 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77361 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77362 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77363 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77364 | GIR_RootConstrainSelectedInstOperands, |
| 77365 | // GIR_Coverage, 1004, |
| 77366 | GIR_EraseRootFromParent_Done, |
| 77367 | // Label 4204: @243312 |
| 77368 | GIM_Try, /*On fail goto*//*Label 4205*/ GIMT_Encode4(243373), // Rule ID 1005 // |
| 77369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77370 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16), |
| 77371 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77372 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77373 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77374 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77376 | // MIs[0] cbsz |
| 77377 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77378 | // MIs[0] abid |
| 77379 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77380 | // MIs[0] blgp |
| 77381 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77382 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25102), |
| 77383 | // (intrinsic_wo_chain:{ *:[v4f32] } 2837:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25102>> => (V_MFMA_F32_16X16X16F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_e64), |
| 77385 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77386 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77387 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77388 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77389 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77390 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77391 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77392 | GIR_RootConstrainSelectedInstOperands, |
| 77393 | // GIR_Coverage, 1005, |
| 77394 | GIR_EraseRootFromParent_Done, |
| 77395 | // Label 4205: @243373 |
| 77396 | GIM_Try, /*On fail goto*//*Label 4206*/ GIMT_Encode4(243434), // Rule ID 1006 // |
| 77397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77398 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16f16), |
| 77399 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77400 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77401 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77402 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77404 | // MIs[0] cbsz |
| 77405 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77406 | // MIs[0] abid |
| 77407 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77408 | // MIs[0] blgp |
| 77409 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77410 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25104), |
| 77411 | // (intrinsic_wo_chain:{ *:[v4f32] } 2837:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25104>> => (V_MFMA_F32_16X16X16F16_vgprcd_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16F16_vgprcd_e64), |
| 77413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77414 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77415 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77416 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77417 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77418 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77419 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77420 | GIR_RootConstrainSelectedInstOperands, |
| 77421 | // GIR_Coverage, 1006, |
| 77422 | GIR_EraseRootFromParent_Done, |
| 77423 | // Label 4206: @243434 |
| 77424 | GIM_Try, /*On fail goto*//*Label 4207*/ GIMT_Encode4(243495), // Rule ID 1007 // |
| 77425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77426 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8), |
| 77427 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77428 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77429 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77430 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77432 | // MIs[0] cbsz |
| 77433 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77434 | // MIs[0] abid |
| 77435 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77436 | // MIs[0] blgp |
| 77437 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77438 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25108), |
| 77439 | // (intrinsic_wo_chain:{ *:[v16i32] } 2870:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25108>> => (V_MFMA_I32_16X16X4I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_e64), |
| 77441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77442 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77443 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77444 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77445 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77446 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77447 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77448 | GIR_RootConstrainSelectedInstOperands, |
| 77449 | // GIR_Coverage, 1007, |
| 77450 | GIR_EraseRootFromParent_Done, |
| 77451 | // Label 4207: @243495 |
| 77452 | GIM_Try, /*On fail goto*//*Label 4208*/ GIMT_Encode4(243556), // Rule ID 1008 // |
| 77453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77454 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x4i8), |
| 77455 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77456 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77457 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77458 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77459 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77460 | // MIs[0] cbsz |
| 77461 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77462 | // MIs[0] abid |
| 77463 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77464 | // MIs[0] blgp |
| 77465 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77466 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25110), |
| 77467 | // (intrinsic_wo_chain:{ *:[v16i32] } 2870:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25110>> => (V_MFMA_I32_16X16X4I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X4I8_mac_vgprcd_e64), |
| 77469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77470 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77471 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77472 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77473 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77474 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77475 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77476 | GIR_RootConstrainSelectedInstOperands, |
| 77477 | // GIR_Coverage, 1008, |
| 77478 | GIR_EraseRootFromParent_Done, |
| 77479 | // Label 4208: @243556 |
| 77480 | GIM_Try, /*On fail goto*//*Label 4209*/ GIMT_Encode4(243617), // Rule ID 1009 // |
| 77481 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77482 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16), |
| 77483 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77484 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77485 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77486 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID), |
| 77488 | // MIs[0] cbsz |
| 77489 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77490 | // MIs[0] abid |
| 77491 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77492 | // MIs[0] blgp |
| 77493 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77494 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25114), |
| 77495 | // (intrinsic_wo_chain:{ *:[v32f32] } 2859:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25114>> => (V_MFMA_F32_32X32X4F16_mac_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_e64), |
| 77497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77498 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77499 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77500 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77501 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77502 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77503 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77504 | GIR_RootConstrainSelectedInstOperands, |
| 77505 | // GIR_Coverage, 1009, |
| 77506 | GIR_EraseRootFromParent_Done, |
| 77507 | // Label 4209: @243617 |
| 77508 | GIM_Try, /*On fail goto*//*Label 4210*/ GIMT_Encode4(243678), // Rule ID 1010 // |
| 77509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77510 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4f16), |
| 77511 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77512 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77513 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77514 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 77516 | // MIs[0] cbsz |
| 77517 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77518 | // MIs[0] abid |
| 77519 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77520 | // MIs[0] blgp |
| 77521 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77522 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25116), |
| 77523 | // (intrinsic_wo_chain:{ *:[v32f32] } 2859:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25116>> => (V_MFMA_F32_32X32X4F16_mac_vgprcd_e64:{ *:[v32f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4F16_mac_vgprcd_e64), |
| 77525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77526 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77527 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77528 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77529 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77530 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77531 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77532 | GIR_RootConstrainSelectedInstOperands, |
| 77533 | // GIR_Coverage, 1010, |
| 77534 | GIR_EraseRootFromParent_Done, |
| 77535 | // Label 4210: @243678 |
| 77536 | GIM_Try, /*On fail goto*//*Label 4211*/ GIMT_Encode4(243739), // Rule ID 1011 // |
| 77537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77538 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16), |
| 77539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77540 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77541 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77542 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77544 | // MIs[0] cbsz |
| 77545 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77546 | // MIs[0] abid |
| 77547 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77548 | // MIs[0] blgp |
| 77549 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77550 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25118), |
| 77551 | // (intrinsic_wo_chain:{ *:[v16f32] } 2861:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25118>> => (V_MFMA_F32_32X32X8F16_mac_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_e64), |
| 77553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77554 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77555 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77556 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77557 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77558 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77559 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77560 | GIR_RootConstrainSelectedInstOperands, |
| 77561 | // GIR_Coverage, 1011, |
| 77562 | GIR_EraseRootFromParent_Done, |
| 77563 | // Label 4211: @243739 |
| 77564 | GIM_Try, /*On fail goto*//*Label 4212*/ GIMT_Encode4(243800), // Rule ID 1012 // |
| 77565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77566 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8f16), |
| 77567 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77568 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 77569 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 77570 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77572 | // MIs[0] cbsz |
| 77573 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77574 | // MIs[0] abid |
| 77575 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77576 | // MIs[0] blgp |
| 77577 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77578 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25120), |
| 77579 | // (intrinsic_wo_chain:{ *:[v16f32] } 2861:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25120>> => (V_MFMA_F32_32X32X8F16_mac_vgprcd_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v4f16:{ *:[v4f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8F16_mac_vgprcd_e64), |
| 77581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77582 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77583 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77584 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77585 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77586 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77587 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77588 | GIR_RootConstrainSelectedInstOperands, |
| 77589 | // GIR_Coverage, 1012, |
| 77590 | GIR_EraseRootFromParent_Done, |
| 77591 | // Label 4212: @243800 |
| 77592 | GIM_Try, /*On fail goto*//*Label 4213*/ GIMT_Encode4(243861), // Rule ID 1013 // |
| 77593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77594 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8), |
| 77595 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77596 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77597 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77598 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID), |
| 77600 | // MIs[0] cbsz |
| 77601 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77602 | // MIs[0] abid |
| 77603 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77604 | // MIs[0] blgp |
| 77605 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77606 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25124), |
| 77607 | // (intrinsic_wo_chain:{ *:[v32i32] } 2872:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25124>> => (V_MFMA_I32_32X32X4I8_mac_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_e64), |
| 77609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77610 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77611 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77612 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77613 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77614 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77615 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77616 | GIR_RootConstrainSelectedInstOperands, |
| 77617 | // GIR_Coverage, 1013, |
| 77618 | GIR_EraseRootFromParent_Done, |
| 77619 | // Label 4213: @243861 |
| 77620 | GIM_Try, /*On fail goto*//*Label 4214*/ GIMT_Encode4(243922), // Rule ID 1014 // |
| 77621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMAIInsts), |
| 77622 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x4i8), |
| 77623 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77624 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77625 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77626 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 77628 | // MIs[0] cbsz |
| 77629 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77630 | // MIs[0] abid |
| 77631 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77632 | // MIs[0] blgp |
| 77633 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77634 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25126), |
| 77635 | // (intrinsic_wo_chain:{ *:[v32i32] } 2872:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25126>> => (V_MFMA_I32_32X32X4I8_mac_vgprcd_e64:{ *:[v32i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v32i32:{ *:[v32i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X4I8_mac_vgprcd_e64), |
| 77637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77638 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77639 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77640 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77641 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77642 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77643 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77644 | GIR_RootConstrainSelectedInstOperands, |
| 77645 | // GIR_Coverage, 1014, |
| 77646 | GIR_EraseRootFromParent_Done, |
| 77647 | // Label 4214: @243922 |
| 77648 | GIM_Try, /*On fail goto*//*Label 4215*/ GIMT_Encode4(243983), // Rule ID 1015 // |
| 77649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77650 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8), |
| 77651 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77652 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77653 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77654 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77656 | // MIs[0] cbsz |
| 77657 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77658 | // MIs[0] abid |
| 77659 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77660 | // MIs[0] blgp |
| 77661 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77662 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25128), |
| 77663 | // (intrinsic_wo_chain:{ *:[v4i32] } 2868:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25128>> => (V_MFMA_I32_16X16X16I8_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_e64), |
| 77665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77666 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77667 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77668 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77669 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77670 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77671 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77672 | GIR_RootConstrainSelectedInstOperands, |
| 77673 | // GIR_Coverage, 1015, |
| 77674 | GIR_EraseRootFromParent_Done, |
| 77675 | // Label 4215: @243983 |
| 77676 | GIM_Try, /*On fail goto*//*Label 4216*/ GIMT_Encode4(244044), // Rule ID 1016 // |
| 77677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77678 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x16i8), |
| 77679 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77680 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77681 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77682 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77684 | // MIs[0] cbsz |
| 77685 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77686 | // MIs[0] abid |
| 77687 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77688 | // MIs[0] blgp |
| 77689 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77690 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25130), |
| 77691 | // (intrinsic_wo_chain:{ *:[v4i32] } 2868:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25130>> => (V_MFMA_I32_16X16X16I8_vgprcd_e64:{ *:[v4i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X16I8_vgprcd_e64), |
| 77693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77694 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77695 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77696 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77697 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77698 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77699 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77700 | GIR_RootConstrainSelectedInstOperands, |
| 77701 | // GIR_Coverage, 1016, |
| 77702 | GIR_EraseRootFromParent_Done, |
| 77703 | // Label 4216: @244044 |
| 77704 | GIM_Try, /*On fail goto*//*Label 4217*/ GIMT_Encode4(244105), // Rule ID 1017 // |
| 77705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77706 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8), |
| 77707 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77708 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77709 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77710 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77712 | // MIs[0] cbsz |
| 77713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77714 | // MIs[0] abid |
| 77715 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77716 | // MIs[0] blgp |
| 77717 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77718 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25132), |
| 77719 | // (intrinsic_wo_chain:{ *:[v16i32] } 2873:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25132>> => (V_MFMA_I32_32X32X8I8_mac_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_e64), |
| 77721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77722 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77723 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77724 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77725 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77726 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77727 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77728 | GIR_RootConstrainSelectedInstOperands, |
| 77729 | // GIR_Coverage, 1017, |
| 77730 | GIR_EraseRootFromParent_Done, |
| 77731 | // Label 4217: @244105 |
| 77732 | GIM_Try, /*On fail goto*//*Label 4218*/ GIMT_Encode4(244166), // Rule ID 1018 // |
| 77733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77734 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x8i8), |
| 77735 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 77737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 77738 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77739 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77740 | // MIs[0] cbsz |
| 77741 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77742 | // MIs[0] abid |
| 77743 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77744 | // MIs[0] blgp |
| 77745 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77746 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25134), |
| 77747 | // (intrinsic_wo_chain:{ *:[v16i32] } 2873:{ *:[iPTR] }, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25134>> => (V_MFMA_I32_32X32X8I8_mac_vgprcd_e64:{ *:[v16i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X8I8_mac_vgprcd_e64), |
| 77749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77750 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77751 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77752 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77753 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77754 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77755 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77756 | GIR_RootConstrainSelectedInstOperands, |
| 77757 | // GIR_Coverage, 1018, |
| 77758 | GIR_EraseRootFromParent_Done, |
| 77759 | // Label 4218: @244166 |
| 77760 | GIM_Try, /*On fail goto*//*Label 4219*/ GIMT_Encode4(244227), // Rule ID 1019 // |
| 77761 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77762 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16), |
| 77763 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77764 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77765 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77766 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77767 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77768 | // MIs[0] cbsz |
| 77769 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77770 | // MIs[0] abid |
| 77771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77772 | // MIs[0] blgp |
| 77773 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77774 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25136), |
| 77775 | // (intrinsic_wo_chain:{ *:[v4f32] } 2863:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25136>> => (V_MFMA_F32_4X4X2BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_e64), |
| 77777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77778 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77779 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77780 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77781 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77782 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77783 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77784 | GIR_RootConstrainSelectedInstOperands, |
| 77785 | // GIR_Coverage, 1019, |
| 77786 | GIR_EraseRootFromParent_Done, |
| 77787 | // Label 4219: @244227 |
| 77788 | GIM_Try, /*On fail goto*//*Label 4220*/ GIMT_Encode4(244288), // Rule ID 1020 // |
| 77789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77790 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x2bf16), |
| 77791 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77792 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77793 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77794 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77796 | // MIs[0] cbsz |
| 77797 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77798 | // MIs[0] abid |
| 77799 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77800 | // MIs[0] blgp |
| 77801 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77802 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25138), |
| 77803 | // (intrinsic_wo_chain:{ *:[v4f32] } 2863:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25138>> => (V_MFMA_F32_4X4X2BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77804 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X2BF16_vgprcd_e64), |
| 77805 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77806 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77807 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77808 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77809 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77810 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77811 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77812 | GIR_RootConstrainSelectedInstOperands, |
| 77813 | // GIR_Coverage, 1020, |
| 77814 | GIR_EraseRootFromParent_Done, |
| 77815 | // Label 4220: @244288 |
| 77816 | GIM_Try, /*On fail goto*//*Label 4221*/ GIMT_Encode4(244349), // Rule ID 1021 // |
| 77817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77818 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16), |
| 77819 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77820 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77821 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77822 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77824 | // MIs[0] cbsz |
| 77825 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77826 | // MIs[0] abid |
| 77827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77828 | // MIs[0] blgp |
| 77829 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77830 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25142), |
| 77831 | // (intrinsic_wo_chain:{ *:[v16f32] } 2839:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25142>> => (V_MFMA_F32_16X16X2BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_e64), |
| 77833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77834 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77835 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77836 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77837 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77838 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77839 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77840 | GIR_RootConstrainSelectedInstOperands, |
| 77841 | // GIR_Coverage, 1021, |
| 77842 | GIR_EraseRootFromParent_Done, |
| 77843 | // Label 4221: @244349 |
| 77844 | GIM_Try, /*On fail goto*//*Label 4222*/ GIMT_Encode4(244410), // Rule ID 1022 // |
| 77845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77846 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x2bf16), |
| 77847 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77848 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77849 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77850 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 77852 | // MIs[0] cbsz |
| 77853 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77854 | // MIs[0] abid |
| 77855 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77856 | // MIs[0] blgp |
| 77857 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77858 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25144), |
| 77859 | // (intrinsic_wo_chain:{ *:[v16f32] } 2839:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25144>> => (V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X2BF16_mac_vgprcd_e64), |
| 77861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77862 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77863 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77864 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77865 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77866 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77867 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77868 | GIR_RootConstrainSelectedInstOperands, |
| 77869 | // GIR_Coverage, 1022, |
| 77870 | GIR_EraseRootFromParent_Done, |
| 77871 | // Label 4222: @244410 |
| 77872 | GIM_Try, /*On fail goto*//*Label 4223*/ GIMT_Encode4(244471), // Rule ID 1023 // |
| 77873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77874 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16), |
| 77875 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77876 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77877 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77878 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 77880 | // MIs[0] cbsz |
| 77881 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77882 | // MIs[0] abid |
| 77883 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77884 | // MIs[0] blgp |
| 77885 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77886 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25146), |
| 77887 | // (intrinsic_wo_chain:{ *:[v4f32] } 2848:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25146>> => (V_MFMA_F32_16X16X8BF16_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_e64), |
| 77889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77890 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77891 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77892 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77893 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77894 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77895 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77896 | GIR_RootConstrainSelectedInstOperands, |
| 77897 | // GIR_Coverage, 1023, |
| 77898 | GIR_EraseRootFromParent_Done, |
| 77899 | // Label 4223: @244471 |
| 77900 | GIM_Try, /*On fail goto*//*Label 4224*/ GIMT_Encode4(244532), // Rule ID 1024 // |
| 77901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8bf16), |
| 77903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 77904 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77905 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77906 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 77907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 77908 | // MIs[0] cbsz |
| 77909 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77910 | // MIs[0] abid |
| 77911 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77912 | // MIs[0] blgp |
| 77913 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25148), |
| 77915 | // (intrinsic_wo_chain:{ *:[v4f32] } 2848:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25148>> => (V_MFMA_F32_16X16X8BF16_vgprcd_e64:{ *:[v4f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8BF16_vgprcd_e64), |
| 77917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77918 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77919 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77920 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77921 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77922 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77923 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77924 | GIR_RootConstrainSelectedInstOperands, |
| 77925 | // GIR_Coverage, 1024, |
| 77926 | GIR_EraseRootFromParent_Done, |
| 77927 | // Label 4224: @244532 |
| 77928 | GIM_Try, /*On fail goto*//*Label 4225*/ GIMT_Encode4(244593), // Rule ID 1025 // |
| 77929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77930 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16), |
| 77931 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77932 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77933 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77934 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID), |
| 77936 | // MIs[0] cbsz |
| 77937 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77938 | // MIs[0] abid |
| 77939 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77940 | // MIs[0] blgp |
| 77941 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77942 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25152), |
| 77943 | // (intrinsic_wo_chain:{ *:[v32f32] } 2854:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25152>> => (V_MFMA_F32_32X32X2BF16_mac_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_e64), |
| 77945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77946 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77947 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77948 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77949 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77950 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77951 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77952 | GIR_RootConstrainSelectedInstOperands, |
| 77953 | // GIR_Coverage, 1025, |
| 77954 | GIR_EraseRootFromParent_Done, |
| 77955 | // Label 4225: @244593 |
| 77956 | GIM_Try, /*On fail goto*//*Label 4226*/ GIMT_Encode4(244654), // Rule ID 1026 // |
| 77957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77958 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x2bf16), |
| 77959 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 77960 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77961 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77962 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 77963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 77964 | // MIs[0] cbsz |
| 77965 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77966 | // MIs[0] abid |
| 77967 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77968 | // MIs[0] blgp |
| 77969 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77970 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25154), |
| 77971 | // (intrinsic_wo_chain:{ *:[v32f32] } 2854:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25154>> => (V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64:{ *:[v32f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 77972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X2BF16_mac_vgprcd_e64), |
| 77973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 77974 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 77975 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 77976 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 77977 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 77978 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 77979 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 77980 | GIR_RootConstrainSelectedInstOperands, |
| 77981 | // GIR_Coverage, 1026, |
| 77982 | GIR_EraseRootFromParent_Done, |
| 77983 | // Label 4226: @244654 |
| 77984 | GIM_Try, /*On fail goto*//*Label 4227*/ GIMT_Encode4(244715), // Rule ID 1027 // |
| 77985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 77986 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16), |
| 77987 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 77988 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 77989 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 77990 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 77991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 77992 | // MIs[0] cbsz |
| 77993 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 77994 | // MIs[0] abid |
| 77995 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 77996 | // MIs[0] blgp |
| 77997 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 77998 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25156), |
| 77999 | // (intrinsic_wo_chain:{ *:[v16f32] } 2857:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25156>> => (V_MFMA_F32_32X32X4BF16_mac_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_e64), |
| 78001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78002 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78003 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78004 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78005 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78006 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78007 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78008 | GIR_RootConstrainSelectedInstOperands, |
| 78009 | // GIR_Coverage, 1027, |
| 78010 | GIR_EraseRootFromParent_Done, |
| 78011 | // Label 4227: @244715 |
| 78012 | GIM_Try, /*On fail goto*//*Label 4228*/ GIMT_Encode4(244776), // Rule ID 1028 // |
| 78013 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX908orGFX90A), |
| 78014 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16), |
| 78015 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78016 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 78017 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 78018 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78019 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78020 | // MIs[0] cbsz |
| 78021 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78022 | // MIs[0] abid |
| 78023 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78024 | // MIs[0] blgp |
| 78025 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78026 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25158), |
| 78027 | // (intrinsic_wo_chain:{ *:[v16f32] } 2857:{ *:[iPTR] }, v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25158>> => (V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64:{ *:[v16f32] } v2i16:{ *:[v2i16] }:$src0, v2i16:{ *:[v2i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_mac_vgprcd_e64), |
| 78029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78030 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78031 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78032 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78033 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78034 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78035 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78036 | GIR_RootConstrainSelectedInstOperands, |
| 78037 | // GIR_Coverage, 1028, |
| 78038 | GIR_EraseRootFromParent_Done, |
| 78039 | // Label 4228: @244776 |
| 78040 | GIM_Try, /*On fail goto*//*Label 4229*/ GIMT_Encode4(244837), // Rule ID 1029 // |
| 78041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78042 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k), |
| 78043 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 78044 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78045 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78046 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 78047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_1024RegClassID), |
| 78048 | // MIs[0] cbsz |
| 78049 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78050 | // MIs[0] abid |
| 78051 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78052 | // MIs[0] blgp |
| 78053 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78054 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25162), |
| 78055 | // (intrinsic_wo_chain:{ *:[v32f32] } 2858:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25162>> => (V_MFMA_F32_32X32X4BF16_1K_mac_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_e64), |
| 78057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78058 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78059 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78060 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78061 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78062 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78063 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78064 | GIR_RootConstrainSelectedInstOperands, |
| 78065 | // GIR_Coverage, 1029, |
| 78066 | GIR_EraseRootFromParent_Done, |
| 78067 | // Label 4229: @244837 |
| 78068 | GIM_Try, /*On fail goto*//*Label 4230*/ GIMT_Encode4(244898), // Rule ID 1030 // |
| 78069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78070 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4bf16_1k), |
| 78071 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v32s32, |
| 78072 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78073 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78074 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v32s32, |
| 78075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_1024RegClassID), |
| 78076 | // MIs[0] cbsz |
| 78077 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78078 | // MIs[0] abid |
| 78079 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78080 | // MIs[0] blgp |
| 78081 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78082 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25164), |
| 78083 | // (intrinsic_wo_chain:{ *:[v32f32] } 2858:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25164>> => (V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64:{ *:[v32f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v32f32:{ *:[v32f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4BF16_1K_mac_vgprcd_e64), |
| 78085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78086 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78087 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78088 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78089 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78090 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78091 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78092 | GIR_RootConstrainSelectedInstOperands, |
| 78093 | // GIR_Coverage, 1030, |
| 78094 | GIR_EraseRootFromParent_Done, |
| 78095 | // Label 4230: @244898 |
| 78096 | GIM_Try, /*On fail goto*//*Label 4231*/ GIMT_Encode4(244959), // Rule ID 1031 // |
| 78097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78098 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k), |
| 78099 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78100 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78101 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78102 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78104 | // MIs[0] cbsz |
| 78105 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78106 | // MIs[0] abid |
| 78107 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78108 | // MIs[0] blgp |
| 78109 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78110 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25168), |
| 78111 | // (intrinsic_wo_chain:{ *:[v16f32] } 2844:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25168>> => (V_MFMA_F32_16X16X4BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_e64), |
| 78113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78114 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78115 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78116 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78117 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78118 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78119 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78120 | GIR_RootConstrainSelectedInstOperands, |
| 78121 | // GIR_Coverage, 1031, |
| 78122 | GIR_EraseRootFromParent_Done, |
| 78123 | // Label 4231: @244959 |
| 78124 | GIM_Try, /*On fail goto*//*Label 4232*/ GIMT_Encode4(245020), // Rule ID 1032 // |
| 78125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78126 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x4bf16_1k), |
| 78127 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78128 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78129 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78130 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78132 | // MIs[0] cbsz |
| 78133 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78134 | // MIs[0] abid |
| 78135 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78136 | // MIs[0] blgp |
| 78137 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78138 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25170), |
| 78139 | // (intrinsic_wo_chain:{ *:[v16f32] } 2844:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25170>> => (V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X4BF16_1K_mac_vgprcd_e64), |
| 78141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78142 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78143 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78144 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78145 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78146 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78147 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78148 | GIR_RootConstrainSelectedInstOperands, |
| 78149 | // GIR_Coverage, 1032, |
| 78150 | GIR_EraseRootFromParent_Done, |
| 78151 | // Label 4232: @245020 |
| 78152 | GIM_Try, /*On fail goto*//*Label 4233*/ GIMT_Encode4(245081), // Rule ID 1033 // |
| 78153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78154 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k), |
| 78155 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78156 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78157 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78158 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78160 | // MIs[0] cbsz |
| 78161 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78162 | // MIs[0] abid |
| 78163 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78164 | // MIs[0] blgp |
| 78165 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78166 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25172), |
| 78167 | // (intrinsic_wo_chain:{ *:[v4f32] } 2864:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25172>> => (V_MFMA_F32_4X4X4BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78168 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_e64), |
| 78169 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78170 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78171 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78172 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78173 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78174 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78175 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78176 | GIR_RootConstrainSelectedInstOperands, |
| 78177 | // GIR_Coverage, 1033, |
| 78178 | GIR_EraseRootFromParent_Done, |
| 78179 | // Label 4233: @245081 |
| 78180 | GIM_Try, /*On fail goto*//*Label 4234*/ GIMT_Encode4(245142), // Rule ID 1034 // |
| 78181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78182 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_4x4x4bf16_1k), |
| 78183 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78185 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78186 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78188 | // MIs[0] cbsz |
| 78189 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78190 | // MIs[0] abid |
| 78191 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78192 | // MIs[0] blgp |
| 78193 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78194 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25174), |
| 78195 | // (intrinsic_wo_chain:{ *:[v4f32] } 2864:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25174>> => (V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_4X4X4BF16_1K_vgprcd_e64), |
| 78197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78198 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78199 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78200 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78201 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78202 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78203 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78204 | GIR_RootConstrainSelectedInstOperands, |
| 78205 | // GIR_Coverage, 1034, |
| 78206 | GIR_EraseRootFromParent_Done, |
| 78207 | // Label 4234: @245142 |
| 78208 | GIM_Try, /*On fail goto*//*Label 4235*/ GIMT_Encode4(245203), // Rule ID 1035 // |
| 78209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78210 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k), |
| 78211 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78212 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78213 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78214 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78216 | // MIs[0] cbsz |
| 78217 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78218 | // MIs[0] abid |
| 78219 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78220 | // MIs[0] blgp |
| 78221 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78222 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25176), |
| 78223 | // (intrinsic_wo_chain:{ *:[v16f32] } 2860:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25176>> => (V_MFMA_F32_32X32X8BF16_1K_mac_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_e64), |
| 78225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78226 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78227 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78228 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78229 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78230 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78231 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78232 | GIR_RootConstrainSelectedInstOperands, |
| 78233 | // GIR_Coverage, 1035, |
| 78234 | GIR_EraseRootFromParent_Done, |
| 78235 | // Label 4235: @245203 |
| 78236 | GIM_Try, /*On fail goto*//*Label 4236*/ GIMT_Encode4(245264), // Rule ID 1036 // |
| 78237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78238 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x8bf16_1k), |
| 78239 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78240 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78241 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78242 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78244 | // MIs[0] cbsz |
| 78245 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78246 | // MIs[0] abid |
| 78247 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78248 | // MIs[0] blgp |
| 78249 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78250 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25178), |
| 78251 | // (intrinsic_wo_chain:{ *:[v16f32] } 2860:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25178>> => (V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X8BF16_1K_mac_vgprcd_e64), |
| 78253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78254 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78255 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78256 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78257 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78258 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78259 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78260 | GIR_RootConstrainSelectedInstOperands, |
| 78261 | // GIR_Coverage, 1036, |
| 78262 | GIR_EraseRootFromParent_Done, |
| 78263 | // Label 4236: @245264 |
| 78264 | GIM_Try, /*On fail goto*//*Label 4237*/ GIMT_Encode4(245325), // Rule ID 1037 // |
| 78265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78266 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k), |
| 78267 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78268 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78269 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78270 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78271 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78272 | // MIs[0] cbsz |
| 78273 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78274 | // MIs[0] abid |
| 78275 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78276 | // MIs[0] blgp |
| 78277 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78278 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25180), |
| 78279 | // (intrinsic_wo_chain:{ *:[v4f32] } 2836:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25180>> => (V_MFMA_F32_16X16X16BF16_1K_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_e64), |
| 78281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78282 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78283 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78284 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78285 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78286 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78287 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78288 | GIR_RootConstrainSelectedInstOperands, |
| 78289 | // GIR_Coverage, 1037, |
| 78290 | GIR_EraseRootFromParent_Done, |
| 78291 | // Label 4237: @245325 |
| 78292 | GIM_Try, /*On fail goto*//*Label 4238*/ GIMT_Encode4(245386), // Rule ID 1038 // |
| 78293 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78294 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x16bf16_1k), |
| 78295 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78296 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 78297 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s16, |
| 78298 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78300 | // MIs[0] cbsz |
| 78301 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78302 | // MIs[0] abid |
| 78303 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78304 | // MIs[0] blgp |
| 78305 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25182), |
| 78307 | // (intrinsic_wo_chain:{ *:[v4f32] } 2836:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25182>> => (V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v4i16:{ *:[v4i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X16BF16_1K_vgprcd_e64), |
| 78309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78310 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78311 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78312 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78313 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78314 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78315 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78316 | GIR_RootConstrainSelectedInstOperands, |
| 78317 | // GIR_Coverage, 1038, |
| 78318 | GIR_EraseRootFromParent_Done, |
| 78319 | // Label 4238: @245386 |
| 78320 | GIM_Try, /*On fail goto*//*Label 4239*/ GIMT_Encode4(245447), // Rule ID 1039 // |
| 78321 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78322 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64), |
| 78323 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64, |
| 78324 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78325 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78326 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64, |
| 78327 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_256RegClassID), |
| 78328 | // MIs[0] cbsz |
| 78329 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78330 | // MIs[0] abid |
| 78331 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78332 | // MIs[0] blgp |
| 78333 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25186), |
| 78335 | // (intrinsic_wo_chain:{ *:[v4f64] } 2866:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25186>> => (V_MFMA_F64_16X16X4F64_mac_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_e64), |
| 78337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78338 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78339 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78340 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78341 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78342 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78343 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78344 | GIR_RootConstrainSelectedInstOperands, |
| 78345 | // GIR_Coverage, 1039, |
| 78346 | GIR_EraseRootFromParent_Done, |
| 78347 | // Label 4239: @245447 |
| 78348 | GIM_Try, /*On fail goto*//*Label 4240*/ GIMT_Encode4(245508), // Rule ID 1040 // |
| 78349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78350 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_16x16x4f64), |
| 78351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s64, |
| 78352 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78353 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78354 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s64, |
| 78355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 78356 | // MIs[0] cbsz |
| 78357 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78358 | // MIs[0] abid |
| 78359 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78360 | // MIs[0] blgp |
| 78361 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78362 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25188), |
| 78363 | // (intrinsic_wo_chain:{ *:[v4f64] } 2866:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25188>> => (V_MFMA_F64_16X16X4F64_mac_vgprcd_e64:{ *:[v4f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, v4f64:{ *:[v4f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_16X16X4F64_mac_vgprcd_e64), |
| 78365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78366 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78367 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78368 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78369 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78370 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78371 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78372 | GIR_RootConstrainSelectedInstOperands, |
| 78373 | // GIR_Coverage, 1040, |
| 78374 | GIR_EraseRootFromParent_Done, |
| 78375 | // Label 4240: @245508 |
| 78376 | GIM_Try, /*On fail goto*//*Label 4241*/ GIMT_Encode4(245569), // Rule ID 1041 // |
| 78377 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78378 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64), |
| 78379 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 78380 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78381 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78382 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 78383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_64RegClassID), |
| 78384 | // MIs[0] cbsz |
| 78385 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78386 | // MIs[0] abid |
| 78387 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78388 | // MIs[0] blgp |
| 78389 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78390 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25190), |
| 78391 | // (intrinsic_wo_chain:{ *:[f64] } 2867:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25190>> => (V_MFMA_F64_4X4X4F64_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_e64), |
| 78393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78394 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78395 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78396 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78397 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78398 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78399 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78400 | GIR_RootConstrainSelectedInstOperands, |
| 78401 | // GIR_Coverage, 1041, |
| 78402 | GIR_EraseRootFromParent_Done, |
| 78403 | // Label 4241: @245569 |
| 78404 | GIM_Try, /*On fail goto*//*Label 4242*/ GIMT_Encode4(245630), // Rule ID 1042 // |
| 78405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX90APlus), |
| 78406 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f64_4x4x4f64), |
| 78407 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s64, |
| 78408 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78409 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78410 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s64, |
| 78411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 78412 | // MIs[0] cbsz |
| 78413 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78414 | // MIs[0] abid |
| 78415 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78416 | // MIs[0] blgp |
| 78417 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78418 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25192), |
| 78419 | // (intrinsic_wo_chain:{ *:[f64] } 2867:{ *:[iPTR] }, f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25192>> => (V_MFMA_F64_4X4X4F64_vgprcd_e64:{ *:[f64] } f64:{ *:[f64] }:$src0, f64:{ *:[f64] }:$src1, f64:{ *:[f64] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F64_4X4X4F64_vgprcd_e64), |
| 78421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78422 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78423 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78424 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78425 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78426 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78427 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78428 | GIR_RootConstrainSelectedInstOperands, |
| 78429 | // GIR_Coverage, 1042, |
| 78430 | GIR_EraseRootFromParent_Done, |
| 78431 | // Label 4242: @245630 |
| 78432 | GIM_Try, /*On fail goto*//*Label 4243*/ GIMT_Encode4(245691), // Rule ID 1043 // |
| 78433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78434 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8), |
| 78435 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78436 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78437 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78438 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78440 | // MIs[0] cbsz |
| 78441 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78442 | // MIs[0] abid |
| 78443 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78444 | // MIs[0] blgp |
| 78445 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78446 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25196), |
| 78447 | // (intrinsic_wo_chain:{ *:[v16i32] } 2871:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25196>> => (V_MFMA_I32_32X32X16I8_mac_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_e64), |
| 78449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78450 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78451 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78452 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78453 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78454 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78455 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78456 | GIR_RootConstrainSelectedInstOperands, |
| 78457 | // GIR_Coverage, 1043, |
| 78458 | GIR_EraseRootFromParent_Done, |
| 78459 | // Label 4243: @245691 |
| 78460 | GIM_Try, /*On fail goto*//*Label 4244*/ GIMT_Encode4(245752), // Rule ID 1044 // |
| 78461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78462 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_32x32x16_i8), |
| 78463 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78464 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78465 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78466 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78468 | // MIs[0] cbsz |
| 78469 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78470 | // MIs[0] abid |
| 78471 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78472 | // MIs[0] blgp |
| 78473 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78474 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25198), |
| 78475 | // (intrinsic_wo_chain:{ *:[v16i32] } 2871:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25198>> => (V_MFMA_I32_32X32X16I8_mac_vgprcd_e64:{ *:[v16i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16i32:{ *:[v16i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_32X32X16I8_mac_vgprcd_e64), |
| 78477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78478 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78479 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78480 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78481 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78482 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78483 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78484 | GIR_RootConstrainSelectedInstOperands, |
| 78485 | // GIR_Coverage, 1044, |
| 78486 | GIR_EraseRootFromParent_Done, |
| 78487 | // Label 4244: @245752 |
| 78488 | GIM_Try, /*On fail goto*//*Label 4245*/ GIMT_Encode4(245813), // Rule ID 1045 // |
| 78489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78490 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8), |
| 78491 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78492 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78493 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78494 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78496 | // MIs[0] cbsz |
| 78497 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78498 | // MIs[0] abid |
| 78499 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78500 | // MIs[0] blgp |
| 78501 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78502 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25200), |
| 78503 | // (intrinsic_wo_chain:{ *:[v4i32] } 2869:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25200>> => (V_MFMA_I32_16X16X32I8_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_e64), |
| 78505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78506 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78507 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78508 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78509 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78510 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78511 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78512 | GIR_RootConstrainSelectedInstOperands, |
| 78513 | // GIR_Coverage, 1045, |
| 78514 | GIR_EraseRootFromParent_Done, |
| 78515 | // Label 4245: @245813 |
| 78516 | GIM_Try, /*On fail goto*//*Label 4246*/ GIMT_Encode4(245874), // Rule ID 1046 // |
| 78517 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78518 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_i32_16x16x32_i8), |
| 78519 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78520 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78521 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78522 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78524 | // MIs[0] cbsz |
| 78525 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78526 | // MIs[0] abid |
| 78527 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78528 | // MIs[0] blgp |
| 78529 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78530 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25202), |
| 78531 | // (intrinsic_wo_chain:{ *:[v4i32] } 2869:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25202>> => (V_MFMA_I32_16X16X32I8_vgprcd_e64:{ *:[v4i32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4i32:{ *:[v4i32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_I32_16X16X32I8_vgprcd_e64), |
| 78533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78534 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78535 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78536 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78537 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78538 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78539 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78540 | GIR_RootConstrainSelectedInstOperands, |
| 78541 | // GIR_Coverage, 1046, |
| 78542 | GIR_EraseRootFromParent_Done, |
| 78543 | // Label 4246: @245874 |
| 78544 | GIM_Try, /*On fail goto*//*Label 4247*/ GIMT_Encode4(245935), // Rule ID 1047 // |
| 78545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78546 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32), |
| 78547 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78548 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 78549 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 78550 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78551 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78552 | // MIs[0] cbsz |
| 78553 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78554 | // MIs[0] abid |
| 78555 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78556 | // MIs[0] blgp |
| 78557 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78558 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25204), |
| 78559 | // (intrinsic_wo_chain:{ *:[v4f32] } 2847:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25204>> => (V_MFMA_F32_16X16X8XF32_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_e64), |
| 78561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78562 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78563 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78564 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78565 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78566 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78567 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78568 | GIR_RootConstrainSelectedInstOperands, |
| 78569 | // GIR_Coverage, 1047, |
| 78570 | GIR_EraseRootFromParent_Done, |
| 78571 | // Label 4247: @245935 |
| 78572 | GIM_Try, /*On fail goto*//*Label 4248*/ GIMT_Encode4(245996), // Rule ID 1048 // |
| 78573 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78574 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x8_xf32), |
| 78575 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78576 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 78577 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 78578 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78580 | // MIs[0] cbsz |
| 78581 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78582 | // MIs[0] abid |
| 78583 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78584 | // MIs[0] blgp |
| 78585 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78586 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25206), |
| 78587 | // (intrinsic_wo_chain:{ *:[v4f32] } 2847:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25206>> => (V_MFMA_F32_16X16X8XF32_vgprcd_e64:{ *:[v4f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X8XF32_vgprcd_e64), |
| 78589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78590 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78591 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78592 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78593 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78594 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78595 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78596 | GIR_RootConstrainSelectedInstOperands, |
| 78597 | // GIR_Coverage, 1048, |
| 78598 | GIR_EraseRootFromParent_Done, |
| 78599 | // Label 4248: @245996 |
| 78600 | GIM_Try, /*On fail goto*//*Label 4249*/ GIMT_Encode4(246057), // Rule ID 1049 // |
| 78601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78602 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32), |
| 78603 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 78605 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 78606 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78608 | // MIs[0] cbsz |
| 78609 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78610 | // MIs[0] abid |
| 78611 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78612 | // MIs[0] blgp |
| 78613 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78614 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25210), |
| 78615 | // (intrinsic_wo_chain:{ *:[v16f32] } 2856:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25210>> => (V_MFMA_F32_32X32X4XF32_mac_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_e64), |
| 78617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78618 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78619 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78620 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78621 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78622 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78623 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78624 | GIR_RootConstrainSelectedInstOperands, |
| 78625 | // GIR_Coverage, 1049, |
| 78626 | GIR_EraseRootFromParent_Done, |
| 78627 | // Label 4249: @246057 |
| 78628 | GIM_Try, /*On fail goto*//*Label 4250*/ GIMT_Encode4(246118), // Rule ID 1050 // |
| 78629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78630 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x4_xf32), |
| 78631 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78632 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 78633 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 78634 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78636 | // MIs[0] cbsz |
| 78637 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78638 | // MIs[0] abid |
| 78639 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78640 | // MIs[0] blgp |
| 78641 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78642 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25212), |
| 78643 | // (intrinsic_wo_chain:{ *:[v16f32] } 2856:{ *:[iPTR] }, v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25212>> => (V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64:{ *:[v16f32] } v2f32:{ *:[v2f32] }:$src0, v2f32:{ *:[v2f32] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X4XF32_mac_vgprcd_e64), |
| 78645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78646 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78647 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78648 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78649 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78650 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78651 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78652 | GIR_RootConstrainSelectedInstOperands, |
| 78653 | // GIR_Coverage, 1050, |
| 78654 | GIR_EraseRootFromParent_Done, |
| 78655 | // Label 4250: @246118 |
| 78656 | GIM_Try, /*On fail goto*//*Label 4251*/ GIMT_Encode4(246179), // Rule ID 1051 // |
| 78657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78658 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8), |
| 78659 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78660 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78661 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78662 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78664 | // MIs[0] cbsz |
| 78665 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78666 | // MIs[0] abid |
| 78667 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78668 | // MIs[0] blgp |
| 78669 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78670 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25214), |
| 78671 | // (intrinsic_wo_chain:{ *:[v4f32] } 2840:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25214>> => (V_MFMA_F32_16X16X32_BF8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_e64), |
| 78673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78674 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78675 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78676 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78677 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78678 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78679 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78680 | GIR_RootConstrainSelectedInstOperands, |
| 78681 | // GIR_Coverage, 1051, |
| 78682 | GIR_EraseRootFromParent_Done, |
| 78683 | // Label 4251: @246179 |
| 78684 | GIM_Try, /*On fail goto*//*Label 4252*/ GIMT_Encode4(246240), // Rule ID 1052 // |
| 78685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78686 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_bf8), |
| 78687 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78688 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78689 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78690 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78692 | // MIs[0] cbsz |
| 78693 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78694 | // MIs[0] abid |
| 78695 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78696 | // MIs[0] blgp |
| 78697 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25216), |
| 78699 | // (intrinsic_wo_chain:{ *:[v4f32] } 2840:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25216>> => (V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_BF8_vgprcd_e64), |
| 78701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78702 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78703 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78704 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78705 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78706 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78707 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78708 | GIR_RootConstrainSelectedInstOperands, |
| 78709 | // GIR_Coverage, 1052, |
| 78710 | GIR_EraseRootFromParent_Done, |
| 78711 | // Label 4252: @246240 |
| 78712 | GIM_Try, /*On fail goto*//*Label 4253*/ GIMT_Encode4(246301), // Rule ID 1053 // |
| 78713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78714 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8), |
| 78715 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78716 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78717 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78718 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78720 | // MIs[0] cbsz |
| 78721 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78722 | // MIs[0] abid |
| 78723 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78724 | // MIs[0] blgp |
| 78725 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78726 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25218), |
| 78727 | // (intrinsic_wo_chain:{ *:[v4f32] } 2841:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25218>> => (V_MFMA_F32_16X16X32_BF8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_e64), |
| 78729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78730 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78731 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78732 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78733 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78734 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78735 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78736 | GIR_RootConstrainSelectedInstOperands, |
| 78737 | // GIR_Coverage, 1053, |
| 78738 | GIR_EraseRootFromParent_Done, |
| 78739 | // Label 4253: @246301 |
| 78740 | GIM_Try, /*On fail goto*//*Label 4254*/ GIMT_Encode4(246362), // Rule ID 1054 // |
| 78741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78742 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_bf8_fp8), |
| 78743 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78744 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78745 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78746 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78748 | // MIs[0] cbsz |
| 78749 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78750 | // MIs[0] abid |
| 78751 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78752 | // MIs[0] blgp |
| 78753 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78754 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25220), |
| 78755 | // (intrinsic_wo_chain:{ *:[v4f32] } 2841:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25220>> => (V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_BF8_FP8_vgprcd_e64), |
| 78757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78758 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78759 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78760 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78761 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78762 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78763 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78764 | GIR_RootConstrainSelectedInstOperands, |
| 78765 | // GIR_Coverage, 1054, |
| 78766 | GIR_EraseRootFromParent_Done, |
| 78767 | // Label 4254: @246362 |
| 78768 | GIM_Try, /*On fail goto*//*Label 4255*/ GIMT_Encode4(246423), // Rule ID 1055 // |
| 78769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78770 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8), |
| 78771 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78772 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78773 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78774 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78776 | // MIs[0] cbsz |
| 78777 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78778 | // MIs[0] abid |
| 78779 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78780 | // MIs[0] blgp |
| 78781 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78782 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25222), |
| 78783 | // (intrinsic_wo_chain:{ *:[v4f32] } 2842:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25222>> => (V_MFMA_F32_16X16X32_FP8_BF8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_e64), |
| 78785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78786 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78787 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78788 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78789 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78790 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78791 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78792 | GIR_RootConstrainSelectedInstOperands, |
| 78793 | // GIR_Coverage, 1055, |
| 78794 | GIR_EraseRootFromParent_Done, |
| 78795 | // Label 4255: @246423 |
| 78796 | GIM_Try, /*On fail goto*//*Label 4256*/ GIMT_Encode4(246484), // Rule ID 1056 // |
| 78797 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78798 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_bf8), |
| 78799 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78800 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78801 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78802 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78804 | // MIs[0] cbsz |
| 78805 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78806 | // MIs[0] abid |
| 78807 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78808 | // MIs[0] blgp |
| 78809 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78810 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25224), |
| 78811 | // (intrinsic_wo_chain:{ *:[v4f32] } 2842:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25224>> => (V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_BF8_vgprcd_e64), |
| 78813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78814 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78815 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78816 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78817 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78818 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78819 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78820 | GIR_RootConstrainSelectedInstOperands, |
| 78821 | // GIR_Coverage, 1056, |
| 78822 | GIR_EraseRootFromParent_Done, |
| 78823 | // Label 4256: @246484 |
| 78824 | GIM_Try, /*On fail goto*//*Label 4257*/ GIMT_Encode4(246545), // Rule ID 1057 // |
| 78825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78826 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8), |
| 78827 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78828 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78829 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78830 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_128RegClassID), |
| 78832 | // MIs[0] cbsz |
| 78833 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78834 | // MIs[0] abid |
| 78835 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78836 | // MIs[0] blgp |
| 78837 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25226), |
| 78839 | // (intrinsic_wo_chain:{ *:[v4f32] } 2843:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25226>> => (V_MFMA_F32_16X16X32_FP8_FP8_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_e64), |
| 78841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78842 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78843 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78844 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78845 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78846 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78847 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78848 | GIR_RootConstrainSelectedInstOperands, |
| 78849 | // GIR_Coverage, 1057, |
| 78850 | GIR_EraseRootFromParent_Done, |
| 78851 | // Label 4257: @246545 |
| 78852 | GIM_Try, /*On fail goto*//*Label 4258*/ GIMT_Encode4(246606), // Rule ID 1058 // |
| 78853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78854 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_16x16x32_fp8_fp8), |
| 78855 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 78856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78857 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78858 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 78859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 78860 | // MIs[0] cbsz |
| 78861 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78862 | // MIs[0] abid |
| 78863 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78864 | // MIs[0] blgp |
| 78865 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78866 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25228), |
| 78867 | // (intrinsic_wo_chain:{ *:[v4f32] } 2843:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25228>> => (V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64:{ *:[v4f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v4f32:{ *:[v4f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_16X16X32_FP8_FP8_vgprcd_e64), |
| 78869 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78870 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78871 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78872 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78873 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78874 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78875 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78876 | GIR_RootConstrainSelectedInstOperands, |
| 78877 | // GIR_Coverage, 1058, |
| 78878 | GIR_EraseRootFromParent_Done, |
| 78879 | // Label 4258: @246606 |
| 78880 | GIM_Try, /*On fail goto*//*Label 4259*/ GIMT_Encode4(246667), // Rule ID 1059 // |
| 78881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78882 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8), |
| 78883 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78884 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78885 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78886 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78888 | // MIs[0] cbsz |
| 78889 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78890 | // MIs[0] abid |
| 78891 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78892 | // MIs[0] blgp |
| 78893 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78894 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25232), |
| 78895 | // (intrinsic_wo_chain:{ *:[v16f32] } 2849:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25232>> => (V_MFMA_F32_32X32X16_BF8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_e64), |
| 78897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78898 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78899 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78900 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78901 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78902 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78903 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78904 | GIR_RootConstrainSelectedInstOperands, |
| 78905 | // GIR_Coverage, 1059, |
| 78906 | GIR_EraseRootFromParent_Done, |
| 78907 | // Label 4259: @246667 |
| 78908 | GIM_Try, /*On fail goto*//*Label 4260*/ GIMT_Encode4(246728), // Rule ID 1060 // |
| 78909 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78910 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_bf8), |
| 78911 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78914 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78916 | // MIs[0] cbsz |
| 78917 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78918 | // MIs[0] abid |
| 78919 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78920 | // MIs[0] blgp |
| 78921 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78922 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25234), |
| 78923 | // (intrinsic_wo_chain:{ *:[v16f32] } 2849:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25234>> => (V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_BF8_mac_vgprcd_e64), |
| 78925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78926 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78927 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78928 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78929 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78930 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78931 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78932 | GIR_RootConstrainSelectedInstOperands, |
| 78933 | // GIR_Coverage, 1060, |
| 78934 | GIR_EraseRootFromParent_Done, |
| 78935 | // Label 4260: @246728 |
| 78936 | GIM_Try, /*On fail goto*//*Label 4261*/ GIMT_Encode4(246789), // Rule ID 1061 // |
| 78937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78938 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8), |
| 78939 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78940 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78941 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78942 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 78944 | // MIs[0] cbsz |
| 78945 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78946 | // MIs[0] abid |
| 78947 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78948 | // MIs[0] blgp |
| 78949 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78950 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25236), |
| 78951 | // (intrinsic_wo_chain:{ *:[v16f32] } 2850:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25236>> => (V_MFMA_F32_32X32X16_BF8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_e64), |
| 78953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78954 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78955 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78956 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78957 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78958 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78959 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78960 | GIR_RootConstrainSelectedInstOperands, |
| 78961 | // GIR_Coverage, 1061, |
| 78962 | GIR_EraseRootFromParent_Done, |
| 78963 | // Label 4261: @246789 |
| 78964 | GIM_Try, /*On fail goto*//*Label 4262*/ GIMT_Encode4(246850), // Rule ID 1062 // |
| 78965 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78966 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_bf8_fp8), |
| 78967 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78968 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78969 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78970 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 78972 | // MIs[0] cbsz |
| 78973 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 78974 | // MIs[0] abid |
| 78975 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 78976 | // MIs[0] blgp |
| 78977 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 78978 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25238), |
| 78979 | // (intrinsic_wo_chain:{ *:[v16f32] } 2850:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25238>> => (V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 78980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_BF8_FP8_mac_vgprcd_e64), |
| 78981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 78982 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 78983 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 78984 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 78985 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 78986 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 78987 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 78988 | GIR_RootConstrainSelectedInstOperands, |
| 78989 | // GIR_Coverage, 1062, |
| 78990 | GIR_EraseRootFromParent_Done, |
| 78991 | // Label 4262: @246850 |
| 78992 | GIM_Try, /*On fail goto*//*Label 4263*/ GIMT_Encode4(246911), // Rule ID 1063 // |
| 78993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 78994 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8), |
| 78995 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 78996 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 78997 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 78998 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 78999 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 79000 | // MIs[0] cbsz |
| 79001 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 79002 | // MIs[0] abid |
| 79003 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79004 | // MIs[0] blgp |
| 79005 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79006 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25240), |
| 79007 | // (intrinsic_wo_chain:{ *:[v16f32] } 2851:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25240>> => (V_MFMA_F32_32X32X16_FP8_BF8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 79008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_e64), |
| 79009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79010 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79011 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79012 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79013 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 79014 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 79015 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 79016 | GIR_RootConstrainSelectedInstOperands, |
| 79017 | // GIR_Coverage, 1063, |
| 79018 | GIR_EraseRootFromParent_Done, |
| 79019 | // Label 4263: @246911 |
| 79020 | GIM_Try, /*On fail goto*//*Label 4264*/ GIMT_Encode4(246972), // Rule ID 1064 // |
| 79021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79022 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_bf8), |
| 79023 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79024 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 79025 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 79026 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 79028 | // MIs[0] cbsz |
| 79029 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 79030 | // MIs[0] abid |
| 79031 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79032 | // MIs[0] blgp |
| 79033 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79034 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25242), |
| 79035 | // (intrinsic_wo_chain:{ *:[v16f32] } 2851:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25242>> => (V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 79036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_BF8_mac_vgprcd_e64), |
| 79037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79038 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79039 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79040 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79041 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 79042 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 79043 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 79044 | GIR_RootConstrainSelectedInstOperands, |
| 79045 | // GIR_Coverage, 1064, |
| 79046 | GIR_EraseRootFromParent_Done, |
| 79047 | // Label 4264: @246972 |
| 79048 | GIM_Try, /*On fail goto*//*Label 4265*/ GIMT_Encode4(247033), // Rule ID 1065 // |
| 79049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79050 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8), |
| 79051 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79052 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 79053 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 79054 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AReg_512RegClassID), |
| 79056 | // MIs[0] cbsz |
| 79057 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 79058 | // MIs[0] abid |
| 79059 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79060 | // MIs[0] blgp |
| 79061 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79062 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25244), |
| 79063 | // (intrinsic_wo_chain:{ *:[v16f32] } 2852:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25244>> => (V_MFMA_F32_32X32X16_FP8_FP8_mac_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 79064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_e64), |
| 79065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79066 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79067 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79068 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79069 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 79070 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 79071 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 79072 | GIR_RootConstrainSelectedInstOperands, |
| 79073 | // GIR_Coverage, 1065, |
| 79074 | GIR_EraseRootFromParent_Done, |
| 79075 | // Label 4265: @247033 |
| 79076 | GIM_Try, /*On fail goto*//*Label 4266*/ GIMT_Encode4(247094), // Rule ID 1066 // |
| 79077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79078 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_mfma_f32_32x32x16_fp8_fp8), |
| 79079 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79080 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 79081 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 79082 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_512RegClassID), |
| 79084 | // MIs[0] cbsz |
| 79085 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 79086 | // MIs[0] abid |
| 79087 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79088 | // MIs[0] blgp |
| 79089 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79090 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_25246), |
| 79091 | // (intrinsic_wo_chain:{ *:[v16f32] } 2852:{ *:[iPTR] }, i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp)<<P:Predicate_anonymous_25246>> => (V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64:{ *:[v16f32] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, v16f32:{ *:[v16f32] }:$src2, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, (timm:{ *:[i32] }):$blgp) |
| 79092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MFMA_F32_32X32X16_FP8_FP8_mac_vgprcd_e64), |
| 79093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79094 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79095 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79096 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79097 | GIR_RootToRootCopy, /*OpIdx*/5, // cbsz |
| 79098 | GIR_RootToRootCopy, /*OpIdx*/6, // abid |
| 79099 | GIR_RootToRootCopy, /*OpIdx*/7, // blgp |
| 79100 | GIR_RootConstrainSelectedInstOperands, |
| 79101 | // GIR_Coverage, 1066, |
| 79102 | GIR_EraseRootFromParent_Done, |
| 79103 | // Label 4266: @247094 |
| 79104 | GIM_Try, /*On fail goto*//*Label 4267*/ GIMT_Encode4(247151), // Rule ID 1067 // |
| 79105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79106 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_f16), |
| 79107 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79108 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 79109 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 79110 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79111 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79113 | // MIs[0] cbsz |
| 79114 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79115 | // MIs[0] abid |
| 79116 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79117 | // (intrinsic_wo_chain:{ *:[v4f32] } 3012:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X32_F16_e64:{ *:[v4f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_F16_e64), |
| 79119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79120 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79121 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79122 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79123 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79124 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79125 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79126 | GIR_RootConstrainSelectedInstOperands, |
| 79127 | // GIR_Coverage, 1067, |
| 79128 | GIR_EraseRootFromParent_Done, |
| 79129 | // Label 4267: @247151 |
| 79130 | GIM_Try, /*On fail goto*//*Label 4268*/ GIMT_Encode4(247208), // Rule ID 1068 // |
| 79131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79132 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_f16), |
| 79133 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79134 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 79135 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 79136 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79137 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79139 | // MIs[0] cbsz |
| 79140 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79141 | // MIs[0] abid |
| 79142 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79143 | // (intrinsic_wo_chain:{ *:[v16f32] } 3018:{ *:[iPTR] }, v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X16_F16_e64:{ *:[v16f32] } v4f16:{ *:[v4f16] }:$src0, v8f16:{ *:[v8f16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_F16_e64), |
| 79145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79146 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79147 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79148 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79149 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79150 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79151 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79152 | GIR_RootConstrainSelectedInstOperands, |
| 79153 | // GIR_Coverage, 1068, |
| 79154 | GIR_EraseRootFromParent_Done, |
| 79155 | // Label 4268: @247208 |
| 79156 | GIM_Try, /*On fail goto*//*Label 4269*/ GIMT_Encode4(247265), // Rule ID 1069 // |
| 79157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79158 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x32_bf16), |
| 79159 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79160 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 79161 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 79162 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79163 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79165 | // MIs[0] cbsz |
| 79166 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79167 | // MIs[0] abid |
| 79168 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79169 | // (intrinsic_wo_chain:{ *:[v4f32] } 3011:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X32_BF16_e64:{ *:[v4f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X32_BF16_e64), |
| 79171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79172 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79173 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79174 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79175 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79176 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79177 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79178 | GIR_RootConstrainSelectedInstOperands, |
| 79179 | // GIR_Coverage, 1069, |
| 79180 | GIR_EraseRootFromParent_Done, |
| 79181 | // Label 4269: @247265 |
| 79182 | GIM_Try, /*On fail goto*//*Label 4270*/ GIMT_Encode4(247322), // Rule ID 1070 // |
| 79183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79184 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x16_bf16), |
| 79185 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s16, |
| 79187 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v8s16, |
| 79188 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79189 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79191 | // MIs[0] cbsz |
| 79192 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79193 | // MIs[0] abid |
| 79194 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79195 | // (intrinsic_wo_chain:{ *:[v16f32] } 3017:{ *:[iPTR] }, v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X16_BF16_e64:{ *:[v16f32] } v4i16:{ *:[v4i16] }:$src0, v8i16:{ *:[v8i16] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X16_BF16_e64), |
| 79197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79198 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79199 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79200 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79201 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79202 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79203 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79204 | GIR_RootConstrainSelectedInstOperands, |
| 79205 | // GIR_Coverage, 1070, |
| 79206 | GIR_EraseRootFromParent_Done, |
| 79207 | // Label 4270: @247322 |
| 79208 | GIM_Try, /*On fail goto*//*Label 4271*/ GIMT_Encode4(247379), // Rule ID 1071 // |
| 79209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79210 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_16x16x64_i8), |
| 79211 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79212 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79213 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79214 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79215 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79217 | // MIs[0] cbsz |
| 79218 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79219 | // MIs[0] abid |
| 79220 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79221 | // (intrinsic_wo_chain:{ *:[v4i32] } 3023:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4i32:{ *:[v4i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_I32_16X16X64_I8_e64:{ *:[v4i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4i32:{ *:[v4i32] }:$src2) |
| 79222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_16X16X64_I8_e64), |
| 79223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79224 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79225 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79226 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79227 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79228 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79229 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79230 | GIR_RootConstrainSelectedInstOperands, |
| 79231 | // GIR_Coverage, 1071, |
| 79232 | GIR_EraseRootFromParent_Done, |
| 79233 | // Label 4271: @247379 |
| 79234 | GIM_Try, /*On fail goto*//*Label 4272*/ GIMT_Encode4(247436), // Rule ID 1072 // |
| 79235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79236 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_i32_32x32x32_i8), |
| 79237 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79239 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79240 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79241 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79242 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79243 | // MIs[0] cbsz |
| 79244 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79245 | // MIs[0] abid |
| 79246 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79247 | // (intrinsic_wo_chain:{ *:[v16i32] } 3024:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16i32:{ *:[v16i32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_I32_32X32X32_I8_e64:{ *:[v16i32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16i32:{ *:[v16i32] }:$src2) |
| 79248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_I32_32X32X32_I8_e64), |
| 79249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79250 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79251 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79252 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79253 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79254 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79255 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79256 | GIR_RootConstrainSelectedInstOperands, |
| 79257 | // GIR_Coverage, 1072, |
| 79258 | GIR_EraseRootFromParent_Done, |
| 79259 | // Label 4272: @247436 |
| 79260 | GIM_Try, /*On fail goto*//*Label 4273*/ GIMT_Encode4(247493), // Rule ID 1073 // |
| 79261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79262 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_bf8), |
| 79263 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79264 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79265 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79266 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79267 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79269 | // MIs[0] cbsz |
| 79270 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79271 | // MIs[0] abid |
| 79272 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79273 | // (intrinsic_wo_chain:{ *:[v4f32] } 3013:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X64_BF8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_BF8_e64), |
| 79275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79276 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79277 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79278 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79279 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79280 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79281 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79282 | GIR_RootConstrainSelectedInstOperands, |
| 79283 | // GIR_Coverage, 1073, |
| 79284 | GIR_EraseRootFromParent_Done, |
| 79285 | // Label 4273: @247493 |
| 79286 | GIM_Try, /*On fail goto*//*Label 4274*/ GIMT_Encode4(247550), // Rule ID 1074 // |
| 79287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79288 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_bf8_fp8), |
| 79289 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79290 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79291 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79292 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79293 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79295 | // MIs[0] cbsz |
| 79296 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79297 | // MIs[0] abid |
| 79298 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79299 | // (intrinsic_wo_chain:{ *:[v4f32] } 3014:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X64_BF8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_BF8_FP8_e64), |
| 79301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79302 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79303 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79304 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79305 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79306 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79307 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79308 | GIR_RootConstrainSelectedInstOperands, |
| 79309 | // GIR_Coverage, 1074, |
| 79310 | GIR_EraseRootFromParent_Done, |
| 79311 | // Label 4274: @247550 |
| 79312 | GIM_Try, /*On fail goto*//*Label 4275*/ GIMT_Encode4(247607), // Rule ID 1075 // |
| 79313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79314 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_bf8), |
| 79315 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79316 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79317 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79318 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79319 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79320 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79321 | // MIs[0] cbsz |
| 79322 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79323 | // MIs[0] abid |
| 79324 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79325 | // (intrinsic_wo_chain:{ *:[v4f32] } 3015:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X64_FP8_BF8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_BF8_e64), |
| 79327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79328 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79329 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79330 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79331 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79332 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79333 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79334 | GIR_RootConstrainSelectedInstOperands, |
| 79335 | // GIR_Coverage, 1075, |
| 79336 | GIR_EraseRootFromParent_Done, |
| 79337 | // Label 4275: @247607 |
| 79338 | GIM_Try, /*On fail goto*//*Label 4276*/ GIMT_Encode4(247664), // Rule ID 1076 // |
| 79339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79340 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_16x16x64_fp8_fp8), |
| 79341 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79342 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79343 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79344 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v4s32, |
| 79345 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79347 | // MIs[0] cbsz |
| 79348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79349 | // MIs[0] abid |
| 79350 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79351 | // (intrinsic_wo_chain:{ *:[v4f32] } 3016:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v4f32:{ *:[v4f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_16X16X64_FP8_FP8_e64:{ *:[v4f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v4f32:{ *:[v4f32] }:$src2) |
| 79352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_16X16X64_FP8_FP8_e64), |
| 79353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79354 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79355 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79356 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79357 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79358 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79359 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79360 | GIR_RootConstrainSelectedInstOperands, |
| 79361 | // GIR_Coverage, 1076, |
| 79362 | GIR_EraseRootFromParent_Done, |
| 79363 | // Label 4276: @247664 |
| 79364 | GIM_Try, /*On fail goto*//*Label 4277*/ GIMT_Encode4(247721), // Rule ID 1077 // |
| 79365 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79366 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_bf8), |
| 79367 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79369 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79370 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79371 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79372 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79373 | // MIs[0] cbsz |
| 79374 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79375 | // MIs[0] abid |
| 79376 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79377 | // (intrinsic_wo_chain:{ *:[v16f32] } 3019:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X32_BF8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_BF8_e64), |
| 79379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79380 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79381 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79382 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79383 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79384 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79385 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79386 | GIR_RootConstrainSelectedInstOperands, |
| 79387 | // GIR_Coverage, 1077, |
| 79388 | GIR_EraseRootFromParent_Done, |
| 79389 | // Label 4277: @247721 |
| 79390 | GIM_Try, /*On fail goto*//*Label 4278*/ GIMT_Encode4(247778), // Rule ID 1078 // |
| 79391 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79392 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_bf8_fp8), |
| 79393 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79394 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79395 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79396 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79397 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79399 | // MIs[0] cbsz |
| 79400 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79401 | // MIs[0] abid |
| 79402 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79403 | // (intrinsic_wo_chain:{ *:[v16f32] } 3020:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X32_BF8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_BF8_FP8_e64), |
| 79405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79406 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79407 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79408 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79409 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79410 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79411 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79412 | GIR_RootConstrainSelectedInstOperands, |
| 79413 | // GIR_Coverage, 1078, |
| 79414 | GIR_EraseRootFromParent_Done, |
| 79415 | // Label 4278: @247778 |
| 79416 | GIM_Try, /*On fail goto*//*Label 4279*/ GIMT_Encode4(247835), // Rule ID 1079 // |
| 79417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79418 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_bf8), |
| 79419 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79422 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79423 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79425 | // MIs[0] cbsz |
| 79426 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79427 | // MIs[0] abid |
| 79428 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79429 | // (intrinsic_wo_chain:{ *:[v16f32] } 3021:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X32_FP8_BF8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_BF8_e64), |
| 79431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79432 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79433 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79434 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79435 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79436 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79437 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79438 | GIR_RootConstrainSelectedInstOperands, |
| 79439 | // GIR_Coverage, 1079, |
| 79440 | GIR_EraseRootFromParent_Done, |
| 79441 | // Label 4279: @247835 |
| 79442 | GIM_Try, /*On fail goto*//*Label 4280*/ GIMT_Encode4(247892), // Rule ID 1080 // |
| 79443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX940Plus), |
| 79444 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_smfmac_f32_32x32x32_fp8_fp8), |
| 79445 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v16s32, |
| 79446 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 79447 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 79448 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_v16s32, |
| 79449 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_512RegClassID), |
| 79451 | // MIs[0] cbsz |
| 79452 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 79453 | // MIs[0] abid |
| 79454 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 79455 | // (intrinsic_wo_chain:{ *:[v16f32] } 3022:{ *:[iPTR] }, v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, v16f32:{ *:[v16f32] }:$src2, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid) => (V_SMFMAC_F32_32X32X32_FP8_FP8_e64:{ *:[v16f32] } v2i32:{ *:[v2i32] }:$src0, v4i32:{ *:[v4i32] }:$src1, i32:{ *:[i32] }:$idx, (timm:{ *:[i32] }):$cbsz, (timm:{ *:[i32] }):$abid, v16f32:{ *:[v16f32] }:$src2) |
| 79456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SMFMAC_F32_32X32X32_FP8_FP8_e64), |
| 79457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79458 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 79459 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 79460 | GIR_RootToRootCopy, /*OpIdx*/5, // idx |
| 79461 | GIR_RootToRootCopy, /*OpIdx*/6, // cbsz |
| 79462 | GIR_RootToRootCopy, /*OpIdx*/7, // abid |
| 79463 | GIR_RootToRootCopy, /*OpIdx*/4, // src2 |
| 79464 | GIR_RootConstrainSelectedInstOperands, |
| 79465 | // GIR_Coverage, 1080, |
| 79466 | GIR_EraseRootFromParent_Done, |
| 79467 | // Label 4280: @247892 |
| 79468 | GIM_Reject, |
| 79469 | // Label 4137: @247893 |
| 79470 | GIM_Try, /*On fail goto*//*Label 4281*/ GIMT_Encode4(248433), |
| 79471 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/9, |
| 79472 | GIM_Try, /*On fail goto*//*Label 4282*/ GIMT_Encode4(247992), // Rule ID 2415 // |
| 79473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79474 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8), |
| 79475 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 79476 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 79477 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 79478 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 79479 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79480 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 79481 | // MIs[0] clamp |
| 79482 | // No operand predicates |
| 79483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 79486 | // (intrinsic_wo_chain:{ *:[v8i32] } 3088:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp) |
| 79487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w32_twoaddr), |
| 79488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79490 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79492 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79493 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 79495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 79496 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79498 | GIR_RootConstrainSelectedInstOperands, |
| 79499 | // GIR_Coverage, 2415, |
| 79500 | GIR_EraseRootFromParent_Done, |
| 79501 | // Label 4282: @247992 |
| 79502 | GIM_Try, /*On fail goto*//*Label 4283*/ GIMT_Encode4(248083), // Rule ID 2416 // |
| 79503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79504 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4), |
| 79505 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 79506 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 79507 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 79508 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 79509 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 79511 | // MIs[0] clamp |
| 79512 | // No operand predicates |
| 79513 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 79516 | // (intrinsic_wo_chain:{ *:[v8i32] } 3087:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp) |
| 79517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w32_twoaddr), |
| 79518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79520 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79522 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79523 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 79525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 79526 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79528 | GIR_RootConstrainSelectedInstOperands, |
| 79529 | // GIR_Coverage, 2416, |
| 79530 | GIR_EraseRootFromParent_Done, |
| 79531 | // Label 4283: @248083 |
| 79532 | GIM_Try, /*On fail goto*//*Label 4284*/ GIMT_Encode4(248174), // Rule ID 2448 // |
| 79533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79534 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu8), |
| 79535 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79536 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 79537 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 79538 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 79539 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 79541 | // MIs[0] clamp |
| 79542 | // No operand predicates |
| 79543 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex8), |
| 79546 | // (intrinsic_wo_chain:{ *:[v4i32] } 3088:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex8:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit), i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_8bit, i1:{ *:[i1] }:$clamp) |
| 79547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU8_w64_twoaddr), |
| 79548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79550 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79552 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79553 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 79555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_8bit |
| 79556 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79558 | GIR_RootConstrainSelectedInstOperands, |
| 79559 | // GIR_Coverage, 2448, |
| 79560 | GIR_EraseRootFromParent_Done, |
| 79561 | // Label 4284: @248174 |
| 79562 | GIM_Try, /*On fail goto*//*Label 4285*/ GIMT_Encode4(248265), // Rule ID 2449 // |
| 79563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79564 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x32_iu4), |
| 79565 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79566 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 79567 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 79568 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 79569 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 79571 | // MIs[0] clamp |
| 79572 | // No operand predicates |
| 79573 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 79576 | // (intrinsic_wo_chain:{ *:[v4i32] } 3087:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp) |
| 79577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X32_IU4_w64_twoaddr), |
| 79578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79580 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79582 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79583 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 79585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 79586 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79588 | GIR_RootConstrainSelectedInstOperands, |
| 79589 | // GIR_Coverage, 2449, |
| 79590 | GIR_EraseRootFromParent_Done, |
| 79591 | // Label 4285: @248265 |
| 79592 | GIM_Try, /*On fail goto*//*Label 4286*/ GIMT_Encode4(248356), // Rule ID 2450 // |
| 79593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79594 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4), |
| 79595 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s32, |
| 79596 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 79597 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v2s32, |
| 79598 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v4s32, |
| 79599 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 79601 | // MIs[0] clamp |
| 79602 | // No operand predicates |
| 79603 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/7, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_swmmacindex16), |
| 79606 | // (intrinsic_wo_chain:{ *:[v4i32] } 3089:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), i32:{ *:[i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, (SWMMACIndex16:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit), i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr:{ *:[v4i32] } i32:{ *:[i32] }:$src0_modifiers, i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i32:{ *:[v2i32] }:$src1, v4i32:{ *:[v4i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$index_key_16bit, i1:{ *:[i1] }:$clamp) |
| 79607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w64_twoaddr), |
| 79608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79610 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79612 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79613 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 79615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // index_key_16bit |
| 79616 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79618 | GIR_RootConstrainSelectedInstOperands, |
| 79619 | // GIR_Coverage, 2450, |
| 79620 | GIR_EraseRootFromParent_Done, |
| 79621 | // Label 4286: @248356 |
| 79622 | GIM_Try, /*On fail goto*//*Label 4287*/ GIMT_Encode4(248432), // Rule ID 2417 // |
| 79623 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79624 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_swmmac_i32_16x16x64_iu4), |
| 79625 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s32, |
| 79626 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 79627 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_v4s32, |
| 79628 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_v8s32, |
| 79629 | GIM_RootCheckType, /*Op*/7, /*Type*/GILLT_s32, |
| 79630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_256RegClassID), |
| 79631 | // MIs[0] clamp |
| 79632 | // No operand predicates |
| 79633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmodsneg), |
| 79635 | // (intrinsic_wo_chain:{ *:[v8i32] } 3089:{ *:[iPTR] }, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers), v2i32:{ *:[v2i32] }:$src0, (VOP3PModsNeg:{ *:[i1] } i32:{ *:[i32] }:$src1_modifiers), v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) => (V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr:{ *:[v8i32] } i32:{ *:[i32] }:$src0_modifiers, v2i32:{ *:[v2i32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v4i32:{ *:[v4i32] }:$src1, v8i32:{ *:[v8i32] }:$srcTiedDef, i32:{ *:[i32] }:$src2, i1:{ *:[i1] }:$clamp) |
| 79636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SWMMAC_I32_16X16X64_IU4_w32_twoaddr), |
| 79637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0_modifiers |
| 79639 | GIR_RootToRootCopy, /*OpIdx*/3, // src0 |
| 79640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1_modifiers |
| 79641 | GIR_RootToRootCopy, /*OpIdx*/5, // src1 |
| 79642 | GIR_RootToRootCopy, /*OpIdx*/6, // srcTiedDef |
| 79643 | GIR_RootToRootCopy, /*OpIdx*/7, // src2 |
| 79644 | GIR_RootToRootCopy, /*OpIdx*/8, // clamp |
| 79645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79646 | GIR_RootConstrainSelectedInstOperands, |
| 79647 | // GIR_Coverage, 2417, |
| 79648 | GIR_EraseRootFromParent_Done, |
| 79649 | // Label 4287: @248432 |
| 79650 | GIM_Reject, |
| 79651 | // Label 4281: @248433 |
| 79652 | GIM_Reject, |
| 79653 | // Label 39: @248434 |
| 79654 | GIM_Try, /*On fail goto*//*Label 4288*/ GIMT_Encode4(248510), |
| 79655 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/1, |
| 79656 | GIM_Try, /*On fail goto*//*Label 4289*/ GIMT_Encode4(248457), // Rule ID 183 // |
| 79657 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier), |
| 79658 | // (intrinsic_void 2952:{ *:[iPTR] }) => (S_BARRIER) |
| 79659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER), |
| 79660 | GIR_RootConstrainSelectedInstOperands, |
| 79661 | // GIR_Coverage, 183, |
| 79662 | GIR_EraseRootFromParent_Done, |
| 79663 | // Label 4289: @248457 |
| 79664 | GIM_Try, /*On fail goto*//*Label 4290*/ GIMT_Encode4(248472), // Rule ID 1120 // |
| 79665 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_wave_barrier), |
| 79666 | // (intrinsic_void 3097:{ *:[iPTR] }) => (WAVE_BARRIER) |
| 79667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::WAVE_BARRIER), |
| 79668 | GIR_RootConstrainSelectedInstOperands, |
| 79669 | // GIR_Coverage, 1120, |
| 79670 | GIR_EraseRootFromParent_Done, |
| 79671 | // Label 4290: @248472 |
| 79672 | GIM_Try, /*On fail goto*//*Label 4291*/ GIMT_Encode4(248491), // Rule ID 1129 // |
| 79673 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_unreachable), |
| 79674 | // (intrinsic_void 3095:{ *:[iPTR] }) => (SI_MASKED_UNREACHABLE) |
| 79675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_MASKED_UNREACHABLE), |
| 79676 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79677 | GIR_RootConstrainSelectedInstOperands, |
| 79678 | // GIR_Coverage, 1129, |
| 79679 | GIR_EraseRootFromParent_Done, |
| 79680 | // Label 4291: @248491 |
| 79681 | GIM_Try, /*On fail goto*//*Label 4292*/ GIMT_Encode4(248509), // Rule ID 1641 // |
| 79682 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_endpgm), |
| 79683 | // (intrinsic_void 2006:{ *:[iPTR] }) => (S_ENDPGM 0:{ *:[i16] }) |
| 79684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ENDPGM), |
| 79685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79686 | GIR_RootConstrainSelectedInstOperands, |
| 79687 | // GIR_Coverage, 1641, |
| 79688 | GIR_EraseRootFromParent_Done, |
| 79689 | // Label 4292: @248509 |
| 79690 | GIM_Reject, |
| 79691 | // Label 4288: @248510 |
| 79692 | GIM_Try, /*On fail goto*//*Label 4293*/ GIMT_Encode4(248658), |
| 79693 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/2, |
| 79694 | GIM_Try, /*On fail goto*//*Label 4294*/ GIMT_Encode4(248538), // Rule ID 43 // |
| 79695 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_signal), |
| 79696 | // MIs[0] src0 |
| 79697 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 79698 | // (intrinsic_void 2956:{ *:[iPTR] }, (timm:{ *:[i32] }):$src0) => (S_BARRIER_SIGNAL_IMM (timm:{ *:[i32] }):$src0) |
| 79699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_SIGNAL_IMM), |
| 79700 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 79701 | GIR_RootConstrainSelectedInstOperands, |
| 79702 | // GIR_Coverage, 43, |
| 79703 | GIR_EraseRootFromParent_Done, |
| 79704 | // Label 4294: @248538 |
| 79705 | GIM_Try, /*On fail goto*//*Label 4295*/ GIMT_Encode4(248558), // Rule ID 184 // |
| 79706 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_wait), |
| 79707 | // MIs[0] simm16 |
| 79708 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 79709 | // (intrinsic_void 2960:{ *:[iPTR] }, (timm:{ *:[i16] }):$simm16) => (S_BARRIER_WAIT (timm:{ *:[i16] }):$simm16) |
| 79710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_WAIT), |
| 79711 | GIR_RootToRootCopy, /*OpIdx*/1, // simm16 |
| 79712 | GIR_RootConstrainSelectedInstOperands, |
| 79713 | // GIR_Coverage, 184, |
| 79714 | GIR_EraseRootFromParent_Done, |
| 79715 | // Label 4295: @248558 |
| 79716 | GIM_Try, /*On fail goto*//*Label 4296*/ GIMT_Encode4(248578), // Rule ID 1121 // |
| 79717 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_barrier), |
| 79718 | // MIs[0] mask |
| 79719 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 79720 | // (intrinsic_void 3002:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask) => (SCHED_BARRIER (timm:{ *:[i32] }):$mask) |
| 79721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_BARRIER), |
| 79722 | GIR_RootToRootCopy, /*OpIdx*/1, // mask |
| 79723 | GIR_RootConstrainSelectedInstOperands, |
| 79724 | // GIR_Coverage, 1121, |
| 79725 | GIR_EraseRootFromParent_Done, |
| 79726 | // Label 4296: @248578 |
| 79727 | GIM_Try, /*On fail goto*//*Label 4297*/ GIMT_Encode4(248598), // Rule ID 1123 // |
| 79728 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_iglp_opt), |
| 79729 | // MIs[0] mask |
| 79730 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 79731 | // (intrinsic_void 2045:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask) => (IGLP_OPT (timm:{ *:[i32] }):$mask) |
| 79732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::IGLP_OPT), |
| 79733 | GIR_RootToRootCopy, /*OpIdx*/1, // mask |
| 79734 | GIR_RootConstrainSelectedInstOperands, |
| 79735 | // GIR_Coverage, 1123, |
| 79736 | GIR_EraseRootFromParent_Done, |
| 79737 | // Label 4297: @248598 |
| 79738 | GIM_Try, /*On fail goto*//*Label 4298*/ GIMT_Encode4(248621), // Rule ID 1130 // |
| 79739 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec), |
| 79740 | // MIs[0] src |
| 79741 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 79742 | // (intrinsic_void 2807:{ *:[iPTR] }, (timm:{ *:[i64] }):$src) => (SI_INIT_EXEC (timm:{ *:[i64] }):$src) |
| 79743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC), |
| 79744 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 79745 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0, |
| 79746 | GIR_RootConstrainSelectedInstOperands, |
| 79747 | // GIR_Coverage, 1130, |
| 79748 | GIR_EraseRootFromParent_Done, |
| 79749 | // Label 4298: @248621 |
| 79750 | GIM_Try, /*On fail goto*//*Label 4299*/ GIMT_Encode4(248657), // Rule ID 41 // |
| 79751 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_s_barrier_signal_var), |
| 79752 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 79753 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::M0_CLASSRegClassID), |
| 79754 | // (intrinsic_void 2959:{ *:[iPTR] }, M0:{ *:[i32] }) => (S_BARRIER_SIGNAL_M0) |
| 79755 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 79756 | GIR_AddRegister, /*InsnID*/1, GIMT_Encode2(AMDGPU::M0), /*AddRegisterRegFlags*/GIMT_Encode2(RegState::Define), |
| 79757 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // M0 |
| 79758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BARRIER_SIGNAL_M0), |
| 79759 | GIR_RootConstrainSelectedInstOperands, |
| 79760 | // GIR_Coverage, 41, |
| 79761 | GIR_EraseRootFromParent_Done, |
| 79762 | // Label 4299: @248657 |
| 79763 | GIM_Reject, |
| 79764 | // Label 4293: @248658 |
| 79765 | GIM_Try, /*On fail goto*//*Label 4300*/ GIMT_Encode4(249615), |
| 79766 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/3, |
| 79767 | GIM_Try, /*On fail goto*//*Label 4301*/ GIMT_Encode4(248726), // Rule ID 3717 // |
| 79768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79769 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64), |
| 79770 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 79771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 79772 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79774 | // (intrinsic_w_chain:{ *:[v2i32] } 2040:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B64_w32_SADDR:{ *:[v2i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32_SADDR), |
| 79776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79781 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79782 | GIR_RootConstrainSelectedInstOperands, |
| 79783 | // GIR_Coverage, 3717, |
| 79784 | GIR_EraseRootFromParent_Done, |
| 79785 | // Label 4301: @248726 |
| 79786 | GIM_Try, /*On fail goto*//*Label 4302*/ GIMT_Encode4(248786), // Rule ID 3719 // |
| 79787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79788 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79789 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79793 | // (intrinsic_w_chain:{ *:[v8i16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR), |
| 79795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79801 | GIR_RootConstrainSelectedInstOperands, |
| 79802 | // GIR_Coverage, 3719, |
| 79803 | GIR_EraseRootFromParent_Done, |
| 79804 | // Label 4302: @248786 |
| 79805 | GIM_Try, /*On fail goto*//*Label 4303*/ GIMT_Encode4(248846), // Rule ID 3721 // |
| 79806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79807 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79808 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79810 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79812 | // (intrinsic_w_chain:{ *:[v8f16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR), |
| 79814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79820 | GIR_RootConstrainSelectedInstOperands, |
| 79821 | // GIR_Coverage, 3721, |
| 79822 | GIR_EraseRootFromParent_Done, |
| 79823 | // Label 4303: @248846 |
| 79824 | GIM_Try, /*On fail goto*//*Label 4304*/ GIMT_Encode4(248906), // Rule ID 3723 // |
| 79825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79826 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79827 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79829 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79831 | // (intrinsic_w_chain:{ *:[v8bf16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32_SADDR:{ *:[v8bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32_SADDR), |
| 79833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79838 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79839 | GIR_RootConstrainSelectedInstOperands, |
| 79840 | // GIR_Coverage, 3723, |
| 79841 | GIR_EraseRootFromParent_Done, |
| 79842 | // Label 4304: @248906 |
| 79843 | GIM_Try, /*On fail goto*//*Label 4305*/ GIMT_Encode4(248966), // Rule ID 3725 // |
| 79844 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79845 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64), |
| 79846 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 79847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 79848 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79849 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79850 | // (intrinsic_w_chain:{ *:[i32] } 2040:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B64_w64_SADDR:{ *:[i32] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64_SADDR), |
| 79852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79857 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79858 | GIR_RootConstrainSelectedInstOperands, |
| 79859 | // GIR_Coverage, 3725, |
| 79860 | GIR_EraseRootFromParent_Done, |
| 79861 | // Label 4305: @248966 |
| 79862 | GIM_Try, /*On fail goto*//*Label 4306*/ GIMT_Encode4(249026), // Rule ID 3727 // |
| 79863 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79864 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79865 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 79866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 79867 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79868 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79869 | // (intrinsic_w_chain:{ *:[v4i16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4i16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR), |
| 79871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79877 | GIR_RootConstrainSelectedInstOperands, |
| 79878 | // GIR_Coverage, 3727, |
| 79879 | GIR_EraseRootFromParent_Done, |
| 79880 | // Label 4306: @249026 |
| 79881 | GIM_Try, /*On fail goto*//*Label 4307*/ GIMT_Encode4(249086), // Rule ID 3729 // |
| 79882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79883 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79884 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 79885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 79886 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79888 | // (intrinsic_w_chain:{ *:[v4f16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4f16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR), |
| 79890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79895 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79896 | GIR_RootConstrainSelectedInstOperands, |
| 79897 | // GIR_Coverage, 3729, |
| 79898 | GIR_EraseRootFromParent_Done, |
| 79899 | // Label 4307: @249086 |
| 79900 | GIM_Try, /*On fail goto*//*Label 4308*/ GIMT_Encode4(249146), // Rule ID 3731 // |
| 79901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79902 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79903 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 79904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 79905 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 79907 | // (intrinsic_w_chain:{ *:[v4bf16] } 2039:{ *:[iPTR] }, (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64_SADDR:{ *:[v4bf16] } ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$voffset, ?:{ *:[i32] }:$offset, 0:{ *:[i32] }) |
| 79908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64_SADDR), |
| 79909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 79911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 79912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 79913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79915 | GIR_RootConstrainSelectedInstOperands, |
| 79916 | // GIR_Coverage, 3731, |
| 79917 | GIR_EraseRootFromParent_Done, |
| 79918 | // Label 4308: @249146 |
| 79919 | GIM_Try, /*On fail goto*//*Label 4309*/ GIMT_Encode4(249201), // Rule ID 3716 // |
| 79920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79921 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64), |
| 79922 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 79923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 79924 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 79926 | // (intrinsic_w_chain:{ *:[v2i32] } 2040:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B64_w32:{ *:[v2i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 79927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w32), |
| 79928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 79930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 79931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79932 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79933 | GIR_RootConstrainSelectedInstOperands, |
| 79934 | // GIR_Coverage, 3716, |
| 79935 | GIR_EraseRootFromParent_Done, |
| 79936 | // Label 4309: @249201 |
| 79937 | GIM_Try, /*On fail goto*//*Label 4310*/ GIMT_Encode4(249256), // Rule ID 3718 // |
| 79938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79939 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79940 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79941 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79942 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79943 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 79944 | // (intrinsic_w_chain:{ *:[v8i16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32:{ *:[v8i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 79945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32), |
| 79946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 79948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 79949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79951 | GIR_RootConstrainSelectedInstOperands, |
| 79952 | // GIR_Coverage, 3718, |
| 79953 | GIR_EraseRootFromParent_Done, |
| 79954 | // Label 4310: @249256 |
| 79955 | GIM_Try, /*On fail goto*//*Label 4311*/ GIMT_Encode4(249311), // Rule ID 3720 // |
| 79956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79957 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79958 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79960 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 79962 | // (intrinsic_w_chain:{ *:[v8f16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32:{ *:[v8f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 79963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32), |
| 79964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 79966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 79967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79969 | GIR_RootConstrainSelectedInstOperands, |
| 79970 | // GIR_Coverage, 3720, |
| 79971 | GIR_EraseRootFromParent_Done, |
| 79972 | // Label 4311: @249311 |
| 79973 | GIM_Try, /*On fail goto*//*Label 4312*/ GIMT_Encode4(249366), // Rule ID 3722 // |
| 79974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave32), |
| 79975 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 79976 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v8s16, |
| 79977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 79978 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 79980 | // (intrinsic_w_chain:{ *:[v8bf16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w32:{ *:[v8bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 79981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w32), |
| 79982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 79983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 79984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 79985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 79986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 79987 | GIR_RootConstrainSelectedInstOperands, |
| 79988 | // GIR_Coverage, 3722, |
| 79989 | GIR_EraseRootFromParent_Done, |
| 79990 | // Label 4312: @249366 |
| 79991 | GIM_Try, /*On fail goto*//*Label 4313*/ GIMT_Encode4(249421), // Rule ID 3724 // |
| 79992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 79993 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b64), |
| 79994 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 79995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 79996 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 79997 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 79998 | // (intrinsic_w_chain:{ *:[i32] } 2040:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B64_w64:{ *:[i32] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 79999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B64_w64), |
| 80000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 80002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 80003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80004 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 80005 | GIR_RootConstrainSelectedInstOperands, |
| 80006 | // GIR_Coverage, 3724, |
| 80007 | GIR_EraseRootFromParent_Done, |
| 80008 | // Label 4313: @249421 |
| 80009 | GIM_Try, /*On fail goto*//*Label 4314*/ GIMT_Encode4(249476), // Rule ID 3726 // |
| 80010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 80011 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 80012 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 80013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 80014 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 80015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 80016 | // (intrinsic_w_chain:{ *:[v4i16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64:{ *:[v4i16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 80017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64), |
| 80018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 80020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 80021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 80023 | GIR_RootConstrainSelectedInstOperands, |
| 80024 | // GIR_Coverage, 3726, |
| 80025 | GIR_EraseRootFromParent_Done, |
| 80026 | // Label 4314: @249476 |
| 80027 | GIM_Try, /*On fail goto*//*Label 4315*/ GIMT_Encode4(249531), // Rule ID 3728 // |
| 80028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 80029 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 80030 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 80031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 80032 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 80033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 80034 | // (intrinsic_w_chain:{ *:[v4f16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64:{ *:[v4f16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 80035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64), |
| 80036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 80038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 80039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 80041 | GIR_RootConstrainSelectedInstOperands, |
| 80042 | // GIR_Coverage, 3728, |
| 80043 | GIR_EraseRootFromParent_Done, |
| 80044 | // Label 4315: @249531 |
| 80045 | GIM_Try, /*On fail goto*//*Label 4316*/ GIMT_Encode4(249586), // Rule ID 3730 // |
| 80046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus_isWave64), |
| 80047 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_global_load_tr_b128), |
| 80048 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v4s16, |
| 80049 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 80050 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/2, /*SizeInBits*/0, |
| 80051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 80052 | // (intrinsic_w_chain:{ *:[v4bf16] } 2039:{ *:[iPTR] }, (GlobalOffset:{ *:[iPTR] } VReg_64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset)) => (GLOBAL_LOAD_TR_B128_w64:{ *:[v4bf16] } ?:{ *:[i64] }:$vaddr, ?:{ *:[i32] }:$offset) |
| 80053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_LOAD_TR_B128_w64), |
| 80054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 80056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 80057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 80059 | GIR_RootConstrainSelectedInstOperands, |
| 80060 | // GIR_Coverage, 3730, |
| 80061 | GIR_EraseRootFromParent_Done, |
| 80062 | // Label 4316: @249586 |
| 80063 | GIM_Try, /*On fail goto*//*Label 4317*/ GIMT_Encode4(249614), // Rule ID 1131 // |
| 80064 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_init_exec_from_input), |
| 80065 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 80066 | // MIs[0] shift |
| 80067 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 80068 | // (intrinsic_void 2808:{ *:[iPTR] }, i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift) => (SI_INIT_EXEC_FROM_INPUT i32:{ *:[i32] }:$input, (timm:{ *:[i32] }):$shift) |
| 80069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SI_INIT_EXEC_FROM_INPUT), |
| 80070 | GIR_RootToRootCopy, /*OpIdx*/1, // input |
| 80071 | GIR_RootToRootCopy, /*OpIdx*/2, // shift |
| 80072 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::EXEC*/0, |
| 80073 | GIR_RootConstrainSelectedInstOperands, |
| 80074 | // GIR_Coverage, 1131, |
| 80075 | GIR_EraseRootFromParent_Done, |
| 80076 | // Label 4317: @249614 |
| 80077 | GIM_Reject, |
| 80078 | // Label 4300: @249615 |
| 80079 | GIM_Try, /*On fail goto*//*Label 4318*/ GIMT_Encode4(249648), // Rule ID 1122 // |
| 80080 | GIM_CheckNumOperands, /*MI*/0, /*Expected*/4, |
| 80081 | GIM_CheckIntrinsicID, /*MI*/0, /*Op*/0, GIMT_Encode2(Intrinsic::amdgcn_sched_group_barrier), |
| 80082 | // MIs[0] mask |
| 80083 | GIM_CheckIsImm, /*MI*/0, /*Op*/1, |
| 80084 | // MIs[0] size |
| 80085 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 80086 | // MIs[0] syncid |
| 80087 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 80088 | // (intrinsic_void 3003:{ *:[iPTR] }, (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid) => (SCHED_GROUP_BARRIER (timm:{ *:[i32] }):$mask, (timm:{ *:[i32] }):$size, (timm:{ *:[i32] }):$syncid) |
| 80089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::SCHED_GROUP_BARRIER), |
| 80090 | GIR_RootToRootCopy, /*OpIdx*/1, // mask |
| 80091 | GIR_RootToRootCopy, /*OpIdx*/2, // size |
| 80092 | GIR_RootToRootCopy, /*OpIdx*/3, // syncid |
| 80093 | GIR_RootConstrainSelectedInstOperands, |
| 80094 | // GIR_Coverage, 1122, |
| 80095 | GIR_EraseRootFromParent_Done, |
| 80096 | // Label 4318: @249648 |
| 80097 | GIM_Reject, |
| 80098 | // Label 40: @249649 |
| 80099 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4322*/ GIMT_Encode4(249977), |
| 80100 | /*GILLT_s16*//*Label 4319*/ GIMT_Encode4(249672), |
| 80101 | /*GILLT_s32*//*Label 4320*/ GIMT_Encode4(249709), |
| 80102 | /*GILLT_s64*//*Label 4321*/ GIMT_Encode4(249743), |
| 80103 | // Label 4319: @249672 |
| 80104 | GIM_Try, /*On fail goto*//*Label 4323*/ GIMT_Encode4(249708), // Rule ID 2193 // |
| 80105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 80106 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80108 | // (anyext:{ *:[i16] } i1:{ *:[i1] }:$src) => (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src) |
| 80109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 80115 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80116 | GIR_RootConstrainSelectedInstOperands, |
| 80117 | // GIR_Coverage, 2193, |
| 80118 | GIR_EraseRootFromParent_Done, |
| 80119 | // Label 4323: @249708 |
| 80120 | GIM_Reject, |
| 80121 | // Label 4320: @249709 |
| 80122 | GIM_Try, /*On fail goto*//*Label 4324*/ GIMT_Encode4(249742), // Rule ID 7076 // |
| 80123 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80125 | // (anyext:{ *:[i32] } i1:{ *:[i1] }:$src0) => (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0) |
| 80126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 80132 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 80133 | GIR_RootConstrainSelectedInstOperands, |
| 80134 | // GIR_Coverage, 7076, |
| 80135 | GIR_EraseRootFromParent_Done, |
| 80136 | // Label 4324: @249742 |
| 80137 | GIM_Reject, |
| 80138 | // Label 4321: @249743 |
| 80139 | GIM_Try, /*On fail goto*//*Label 4325*/ GIMT_Encode4(249826), // Rule ID 2102 // |
| 80140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 80141 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80143 | // (anyext:{ *:[i64] } i16:{ *:[i16] }:$src) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (COPY:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (V_MOV_B32_e32:{ *:[i16] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80144 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80145 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 80146 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 80147 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80148 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80149 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80150 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 80151 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80152 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80153 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80156 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80157 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 80159 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80160 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80161 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80162 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80163 | // GIR_Coverage, 2102, |
| 80164 | GIR_EraseRootFromParent_Done, |
| 80165 | // Label 4325: @249826 |
| 80166 | GIM_Try, /*On fail goto*//*Label 4326*/ GIMT_Encode4(249884), // Rule ID 7149 // |
| 80167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 80168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80169 | // (anyext:{ *:[i64] } i32:{ *:[i32] }:$src) => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (IMPLICIT_DEF:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80170 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80171 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 80172 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80173 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80176 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80177 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80178 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80179 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80180 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80181 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 80182 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 80183 | // GIR_Coverage, 7149, |
| 80184 | GIR_EraseRootFromParent_Done, |
| 80185 | // Label 4326: @249884 |
| 80186 | GIM_Try, /*On fail goto*//*Label 4327*/ GIMT_Encode4(249976), // Rule ID 7151 // |
| 80187 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80189 | // (anyext:{ *:[i64] } i1:{ *:[i1] }:$src) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80190 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 80191 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 80192 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80193 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80194 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80196 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80197 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80198 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80199 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80200 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80201 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 80202 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80206 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80207 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 80209 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80210 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80211 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80212 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80213 | // GIR_Coverage, 7151, |
| 80214 | GIR_EraseRootFromParent_Done, |
| 80215 | // Label 4327: @249976 |
| 80216 | GIM_Reject, |
| 80217 | // Label 4322: @249977 |
| 80218 | GIM_Reject, |
| 80219 | // Label 41: @249978 |
| 80220 | GIM_Try, /*On fail goto*//*Label 4328*/ GIMT_Encode4(250102), |
| 80221 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 80222 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4331*/ GIMT_Encode4(250101), |
| 80223 | /*GILLT_s16*//*Label 4329*/ GIMT_Encode4(250005), |
| 80224 | /*GILLT_s32*//*Label 4330*/ GIMT_Encode4(250053), |
| 80225 | // Label 4329: @250005 |
| 80226 | GIM_Try, /*On fail goto*//*Label 4332*/ GIMT_Encode4(250052), // Rule ID 7197 // |
| 80227 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 80228 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36152), |
| 80229 | // (trunc:{ *:[i1] } i16:{ *:[i16] }:$a)<<P:Predicate_anonymous_36152>> => (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i16] }:$a), 1:{ *:[i32] }) |
| 80230 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 80231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 80232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80233 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 80234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 80235 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64), |
| 80237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 80240 | GIR_RootConstrainSelectedInstOperands, |
| 80241 | // GIR_Coverage, 7197, |
| 80242 | GIR_EraseRootFromParent_Done, |
| 80243 | // Label 4332: @250052 |
| 80244 | GIM_Reject, |
| 80245 | // Label 4330: @250053 |
| 80246 | GIM_Try, /*On fail goto*//*Label 4333*/ GIMT_Encode4(250100), // Rule ID 7196 // |
| 80247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 80248 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36152), |
| 80249 | // (trunc:{ *:[i1] } i32:{ *:[i32] }:$a)<<P:Predicate_anonymous_36152>> => (V_CMP_EQ_U32_e64:{ *:[i1] } (V_AND_B32_e64:{ *:[i16] } 1:{ *:[i32] }, ?:{ *:[i32] }:$a), 1:{ *:[i32] }) |
| 80250 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 80251 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 80252 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80253 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 80254 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 80255 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64), |
| 80257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80258 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 80260 | GIR_RootConstrainSelectedInstOperands, |
| 80261 | // GIR_Coverage, 7196, |
| 80262 | GIR_EraseRootFromParent_Done, |
| 80263 | // Label 4333: @250100 |
| 80264 | GIM_Reject, |
| 80265 | // Label 4331: @250101 |
| 80266 | GIM_Reject, |
| 80267 | // Label 4328: @250102 |
| 80268 | GIM_Reject, |
| 80269 | // Label 42: @250103 |
| 80270 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4337*/ GIMT_Encode4(250209), |
| 80271 | /*GILLT_s16*//*Label 4334*/ GIMT_Encode4(250126), |
| 80272 | /*GILLT_s32*//*Label 4335*/ GIMT_Encode4(250146), |
| 80273 | /*GILLT_s64*//*Label 4336*/ GIMT_Encode4(250166), |
| 80274 | // Label 4334: @250126 |
| 80275 | GIM_Try, /*On fail goto*//*Label 4338*/ GIMT_Encode4(250145), // Rule ID 1644 // |
| 80276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 80277 | // MIs[0] Operand 1 |
| 80278 | // No operand predicates |
| 80279 | // (imm:{ *:[i16] }):$imm => (S_MOV_B32:{ *:[i16] } (imm:{ *:[i16] }):$imm) |
| 80280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80282 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 80283 | GIR_RootConstrainSelectedInstOperands, |
| 80284 | // GIR_Coverage, 1644, |
| 80285 | GIR_EraseRootFromParent_Done, |
| 80286 | // Label 4338: @250145 |
| 80287 | GIM_Reject, |
| 80288 | // Label 4335: @250146 |
| 80289 | GIM_Try, /*On fail goto*//*Label 4339*/ GIMT_Encode4(250165), // Rule ID 7055 // |
| 80290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 80291 | // MIs[0] Operand 1 |
| 80292 | // No operand predicates |
| 80293 | // (imm:{ *:[i32] }):$imm => (S_MOV_B32:{ *:[i32] } (imm:{ *:[i32] }):$imm) |
| 80294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80296 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 80297 | GIR_RootConstrainSelectedInstOperands, |
| 80298 | // GIR_Coverage, 7055, |
| 80299 | GIR_EraseRootFromParent_Done, |
| 80300 | // Label 4339: @250165 |
| 80301 | GIM_Reject, |
| 80302 | // Label 4336: @250166 |
| 80303 | GIM_Try, /*On fail goto*//*Label 4340*/ GIMT_Encode4(250189), // Rule ID 7069 // |
| 80304 | GIM_CheckAPIntImmPredicate, /*MI*/0, /*Predicate*/GIMT_Encode2(GICXXPred_APInt_Predicate_InlineImm64), |
| 80305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80306 | // MIs[0] Operand 1 |
| 80307 | // No operand predicates |
| 80308 | // (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm => (S_MOV_B64:{ *:[i64] } (imm:{ *:[i64] })<<P:Predicate_InlineImm64>>:$imm) |
| 80309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64), |
| 80310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80311 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 80312 | GIR_RootConstrainSelectedInstOperands, |
| 80313 | // GIR_Coverage, 7069, |
| 80314 | GIR_EraseRootFromParent_Done, |
| 80315 | // Label 4340: @250189 |
| 80316 | GIM_Try, /*On fail goto*//*Label 4341*/ GIMT_Encode4(250208), // Rule ID 7062 // |
| 80317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80318 | // MIs[0] Operand 1 |
| 80319 | // No operand predicates |
| 80320 | // (imm:{ *:[i64] }):$imm => (S_MOV_B64_IMM_PSEUDO:{ *:[i64] } (imm:{ *:[i64] }):$imm) |
| 80321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B64_IMM_PSEUDO), |
| 80322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80323 | GIR_CopyConstantAsSImm, /*NewInsnID*/0, /*OldInsnID*/0, // imm |
| 80324 | GIR_RootConstrainSelectedInstOperands, |
| 80325 | // GIR_Coverage, 7062, |
| 80326 | GIR_EraseRootFromParent_Done, |
| 80327 | // Label 4341: @250208 |
| 80328 | GIM_Reject, |
| 80329 | // Label 4337: @250209 |
| 80330 | GIM_Reject, |
| 80331 | // Label 43: @250210 |
| 80332 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4344*/ GIMT_Encode4(250296), |
| 80333 | /*GILLT_s16*//*Label 4342*/ GIMT_Encode4(250229), |
| 80334 | /*GILLT_s32*//*Label 4343*/ GIMT_Encode4(250274), |
| 80335 | // Label 4342: @250229 |
| 80336 | GIM_Try, /*On fail goto*//*Label 4345*/ GIMT_Encode4(250273), |
| 80337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 80338 | GIM_Try, /*On fail goto*//*Label 4346*/ GIMT_Encode4(250255), // Rule ID 7065 // |
| 80339 | // MIs[0] Operand 1 |
| 80340 | // No operand predicates |
| 80341 | // (fpimm:{ *:[f16] }):$imm => (S_MOV_B32:{ *:[f16] } (bitcast_fpimm_to_i32:{ *:[i32] } ?:{ *:[f16] }:$imm)) |
| 80342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80344 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm |
| 80345 | GIR_RootConstrainSelectedInstOperands, |
| 80346 | // GIR_Coverage, 7065, |
| 80347 | GIR_EraseRootFromParent_Done, |
| 80348 | // Label 4346: @250255 |
| 80349 | GIM_Try, /*On fail goto*//*Label 4347*/ GIMT_Encode4(250272), // Rule ID 7066 // |
| 80350 | // MIs[0] Operand 1 |
| 80351 | // No operand predicates |
| 80352 | // (fpimm:{ *:[bf16] }):$imm => (S_MOV_B32:{ *:[bf16] } (bitcast_fpimm_to_i32:{ *:[i32] } ?:{ *:[bf16] }:$imm)) |
| 80353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80355 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm |
| 80356 | GIR_RootConstrainSelectedInstOperands, |
| 80357 | // GIR_Coverage, 7066, |
| 80358 | GIR_EraseRootFromParent_Done, |
| 80359 | // Label 4347: @250272 |
| 80360 | GIM_Reject, |
| 80361 | // Label 4345: @250273 |
| 80362 | GIM_Reject, |
| 80363 | // Label 4343: @250274 |
| 80364 | GIM_Try, /*On fail goto*//*Label 4348*/ GIMT_Encode4(250295), // Rule ID 7064 // |
| 80365 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 80366 | // MIs[0] Operand 1 |
| 80367 | // No operand predicates |
| 80368 | // (fpimm:{ *:[f32] }):$imm => (S_MOV_B32:{ *:[f32] } (bitcast_fpimm_to_i32:{ *:[f32] } ?:{ *:[f32] }:$imm)) |
| 80369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 80371 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/0, /*Renderer*/GIMT_Encode2(GICR_renderBitcastImm), // imm |
| 80372 | GIR_RootConstrainSelectedInstOperands, |
| 80373 | // GIR_Coverage, 7064, |
| 80374 | GIR_EraseRootFromParent_Done, |
| 80375 | // Label 4348: @250295 |
| 80376 | GIM_Reject, |
| 80377 | // Label 4344: @250296 |
| 80378 | GIM_Reject, |
| 80379 | // Label 44: @250297 |
| 80380 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4352*/ GIMT_Encode4(251087), |
| 80381 | /*GILLT_s16*//*Label 4349*/ GIMT_Encode4(250320), |
| 80382 | /*GILLT_s32*//*Label 4350*/ GIMT_Encode4(250357), |
| 80383 | /*GILLT_s64*//*Label 4351*/ GIMT_Encode4(250445), |
| 80384 | // Label 4349: @250320 |
| 80385 | GIM_Try, /*On fail goto*//*Label 4353*/ GIMT_Encode4(250356), // Rule ID 2194 // |
| 80386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 80387 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80389 | // (sext:{ *:[i16] } i1:{ *:[i1] }:$src) => (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src) |
| 80390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80395 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80396 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80397 | GIR_RootConstrainSelectedInstOperands, |
| 80398 | // GIR_Coverage, 2194, |
| 80399 | GIR_EraseRootFromParent_Done, |
| 80400 | // Label 4353: @250356 |
| 80401 | GIM_Reject, |
| 80402 | // Label 4350: @250357 |
| 80403 | GIM_Try, /*On fail goto*//*Label 4354*/ GIMT_Encode4(250380), // Rule ID 1645 // |
| 80404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 80406 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18534), |
| 80407 | // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_18534>> => (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src) |
| 80408 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16), |
| 80409 | GIR_RootConstrainSelectedInstOperands, |
| 80410 | // GIR_Coverage, 1645, |
| 80411 | GIR_Done, |
| 80412 | // Label 4354: @250380 |
| 80413 | GIM_Try, /*On fail goto*//*Label 4355*/ GIMT_Encode4(250411), // Rule ID 2201 // |
| 80414 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80416 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23739), |
| 80417 | // (sext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_23739>> => (V_BFE_I32_e64:{ *:[i32] } i16:{ *:[i16] }:$src, 0:{ *:[i32] }, 16:{ *:[i32] }) |
| 80418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64), |
| 80419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80420 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/16, |
| 80423 | GIR_RootConstrainSelectedInstOperands, |
| 80424 | // GIR_Coverage, 2201, |
| 80425 | GIR_EraseRootFromParent_Done, |
| 80426 | // Label 4355: @250411 |
| 80427 | GIM_Try, /*On fail goto*//*Label 4356*/ GIMT_Encode4(250444), // Rule ID 7074 // |
| 80428 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80429 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80430 | // (sext:{ *:[i32] } i1:{ *:[i1] }:$src0) => (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, i1:{ *:[i1] }:$src0) |
| 80431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/uint8_t(-1), |
| 80437 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 80438 | GIR_RootConstrainSelectedInstOperands, |
| 80439 | // GIR_Coverage, 7074, |
| 80440 | GIR_EraseRootFromParent_Done, |
| 80441 | // Label 4356: @250444 |
| 80442 | GIM_Reject, |
| 80443 | // Label 4351: @250445 |
| 80444 | GIM_Try, /*On fail goto*//*Label 4357*/ GIMT_Encode4(250587), // Rule ID 1655 // |
| 80445 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80446 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80447 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18534), |
| 80448 | // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_18534>> => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_ASHR_I32:{ *:[i1] }:{ *:[i1] } (S_SEXT_I32_I16:{ *:[i32] } ?:{ *:[i16] }:$src), (S_MOV_B32:{ *:[i1] } 31:{ *:[i32] })), SGPR_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80449 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80450 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 80451 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 80452 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 80453 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1, |
| 80454 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80455 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80456 | GIR_AddImm8, /*InsnID*/5, /*Imm*/31, |
| 80457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 80458 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16), |
| 80459 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80460 | GIR_Copy, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80461 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 80462 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32), |
| 80463 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80464 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 80465 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 80466 | GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0, |
| 80467 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 80468 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 80469 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80470 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 80471 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80472 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_SEXT_I32_I16), |
| 80473 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80474 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80479 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80480 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 80481 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80482 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80483 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 80484 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 80485 | // GIR_Coverage, 1655, |
| 80486 | GIR_EraseRootFromParent_Done, |
| 80487 | // Label 4357: @250587 |
| 80488 | GIM_Try, /*On fail goto*//*Label 4358*/ GIMT_Encode4(250806), // Rule ID 2202 // |
| 80489 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80491 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23739), |
| 80492 | // (sext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_23739>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] })), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e32:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 31:{ *:[i32] }), (V_BFE_I32_e64:{ *:[i32] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i16] } 0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 16:{ *:[i32] }))), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80493 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80494 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 80495 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 80496 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 80497 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 80498 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16, |
| 80499 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 80500 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s16, |
| 80501 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s16, |
| 80502 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80503 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80504 | GIR_AddImm8, /*InsnID*/9, /*Imm*/16, |
| 80505 | GIR_ConstrainSelectedInstOperands, /*InsnID*/9, |
| 80506 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80507 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80508 | GIR_AddImm8, /*InsnID*/8, /*Imm*/0, |
| 80509 | GIR_ConstrainSelectedInstOperands, /*InsnID*/8, |
| 80510 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64), |
| 80511 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80512 | GIR_Copy, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80513 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/7, |
| 80514 | GIR_AddSimpleTempRegister, /*InsnID*/7, /*TempRegID*/8, |
| 80515 | GIR_ConstrainSelectedInstOperands, /*InsnID*/7, |
| 80516 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80517 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80518 | GIR_AddImm8, /*InsnID*/6, /*Imm*/31, |
| 80519 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 80520 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e32), |
| 80521 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80522 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/5, |
| 80523 | GIR_AddSimpleTempRegister, /*InsnID*/5, /*TempRegID*/6, |
| 80524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 80525 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 80526 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80527 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 80528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 80529 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80530 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80531 | GIR_AddImm8, /*InsnID*/3, /*Imm*/16, |
| 80532 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 80533 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80534 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80535 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80536 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80537 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFE_I32_e64), |
| 80538 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80539 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80540 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 80541 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 80542 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80545 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80546 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 80548 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80549 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80550 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80551 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80552 | // GIR_Coverage, 2202, |
| 80553 | GIR_EraseRootFromParent_Done, |
| 80554 | // Label 4358: @250806 |
| 80555 | GIM_Try, /*On fail goto*//*Label 4359*/ GIMT_Encode4(250895), // Rule ID 7152 // |
| 80556 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 80557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80558 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18534), |
| 80559 | // (sext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_18534>> => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_ASHR_I32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i32] }:$src, 31:{ *:[i32] }), SReg_32_XM0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80561 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 80562 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32), |
| 80563 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80564 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80565 | GIR_AddImm8, /*InsnID*/2, /*Imm*/31, |
| 80566 | GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for AMDGPU::SCC*/0, |
| 80567 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 80569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80570 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 80571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80574 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80575 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80576 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80577 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80578 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 80579 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 80580 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 80581 | // GIR_Coverage, 7152, |
| 80582 | GIR_EraseRootFromParent_Done, |
| 80583 | // Label 4359: @250895 |
| 80584 | GIM_Try, /*On fail goto*//*Label 4360*/ GIMT_Encode4(250981), // Rule ID 7153 // |
| 80585 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 80586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80587 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23739), |
| 80588 | // (sext:{ *:[i64] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_23739>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (V_ASHRREV_I32_e64:{ *:[i16] } 31:{ *:[i32] }, ?:{ *:[i32] }:$src), VGPR_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 80589 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 80590 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 80591 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64), |
| 80592 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80593 | GIR_AddImm8, /*InsnID*/2, /*Imm*/31, |
| 80594 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80595 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80596 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 80597 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80598 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 80599 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80602 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80603 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80604 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80605 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80606 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80607 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80608 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80609 | // GIR_Coverage, 7153, |
| 80610 | GIR_EraseRootFromParent_Done, |
| 80611 | // Label 4360: @250981 |
| 80612 | GIM_Try, /*On fail goto*//*Label 4361*/ GIMT_Encode4(251086), // Rule ID 7154 // |
| 80613 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80615 | // (sext:{ *:[i64] } i1:{ *:[i1] }:$src) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub1:{ *:[i32] }) |
| 80616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 80617 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 80618 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80619 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80620 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80621 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80622 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 80623 | GIR_AddImm8, /*InsnID*/2, /*Imm*/uint8_t(-1), |
| 80624 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 80626 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80627 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80628 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80629 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80630 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 80631 | GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1), |
| 80632 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 80633 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 80635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 80636 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80637 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 80638 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 80639 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 80640 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 80641 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80642 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80643 | // GIR_Coverage, 7154, |
| 80644 | GIR_EraseRootFromParent_Done, |
| 80645 | // Label 4361: @251086 |
| 80646 | GIM_Reject, |
| 80647 | // Label 4352: @251087 |
| 80648 | GIM_Reject, |
| 80649 | // Label 45: @251088 |
| 80650 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4365*/ GIMT_Encode4(252675), |
| 80651 | /*GILLT_s16*//*Label 4362*/ GIMT_Encode4(251111), |
| 80652 | /*GILLT_s32*//*Label 4363*/ GIMT_Encode4(251148), |
| 80653 | /*GILLT_s64*//*Label 4364*/ GIMT_Encode4(252279), |
| 80654 | // Label 4362: @251111 |
| 80655 | GIM_Try, /*On fail goto*//*Label 4366*/ GIMT_Encode4(251147), // Rule ID 2192 // |
| 80656 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 80657 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 80658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80659 | // (zext:{ *:[i16] } i1:{ *:[i1] }:$src) => (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src) |
| 80660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 80661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 80666 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 80667 | GIR_RootConstrainSelectedInstOperands, |
| 80668 | // GIR_Coverage, 2192, |
| 80669 | GIR_EraseRootFromParent_Done, |
| 80670 | // Label 4366: @251147 |
| 80671 | GIM_Reject, |
| 80672 | // Label 4363: @251148 |
| 80673 | GIM_Try, /*On fail goto*//*Label 4367*/ GIMT_Encode4(251224), // Rule ID 2189 // |
| 80674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80675 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 80679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80680 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80681 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 80682 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 80683 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80684 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 80685 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 80686 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 80687 | // MIs[3] Operand 1 |
| 80688 | // No operand predicates |
| 80689 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 80690 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 80691 | // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)) => (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64), |
| 80693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 80695 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80696 | GIR_RootConstrainSelectedInstOperands, |
| 80697 | // GIR_Coverage, 2189, |
| 80698 | GIR_EraseRootFromParent_Done, |
| 80699 | // Label 4367: @251224 |
| 80700 | GIM_Try, /*On fail goto*//*Label 4368*/ GIMT_Encode4(251300), // Rule ID 2185 // |
| 80701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80702 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80704 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80705 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 80706 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80707 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80708 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 80709 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 80710 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80711 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 80712 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 80713 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 80714 | // MIs[3] Operand 1 |
| 80715 | // No operand predicates |
| 80716 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 80717 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 80718 | // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)) => (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64), |
| 80720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80721 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 80722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80723 | GIR_RootConstrainSelectedInstOperands, |
| 80724 | // GIR_Coverage, 2185, |
| 80725 | GIR_EraseRootFromParent_Done, |
| 80726 | // Label 4368: @251300 |
| 80727 | GIM_Try, /*On fail goto*//*Label 4369*/ GIMT_Encode4(251376), // Rule ID 2181 // |
| 80728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80729 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 80733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80735 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 80736 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 80737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 80739 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 80740 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 80741 | // MIs[3] Operand 1 |
| 80742 | // No operand predicates |
| 80743 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 80744 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 80745 | // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>)) => (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64), |
| 80747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80748 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 80749 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80750 | GIR_RootConstrainSelectedInstOperands, |
| 80751 | // GIR_Coverage, 2181, |
| 80752 | GIR_EraseRootFromParent_Done, |
| 80753 | // Label 4369: @251376 |
| 80754 | GIM_Try, /*On fail goto*//*Label 4370*/ GIMT_Encode4(251440), // Rule ID 2167 // |
| 80755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80758 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80759 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 80760 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80761 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80762 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 80763 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 80764 | GIM_CheckI64ImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_I64_Predicate_NegSubInlineIntConst16), |
| 80765 | // MIs[2] Operand 1 |
| 80766 | // No operand predicates |
| 80767 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80768 | // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>><<X:NegateImm>>:$src1)) => (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, (NegateImm:{ *:[i16 i32 bf16 f16 f32 v2i16 v2f16 v2bf16] } (imm:{ *:[i16] })<<P:Predicate_NegSubInlineIntConst16>>:$src1)) |
| 80769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64), |
| 80770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80771 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80772 | GIR_CustomRenderer, /*InsnID*/0, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderNegateImm), // src1 |
| 80773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80774 | GIR_RootConstrainSelectedInstOperands, |
| 80775 | // GIR_Coverage, 2167, |
| 80776 | GIR_EraseRootFromParent_Done, |
| 80777 | // Label 4370: @251440 |
| 80778 | GIM_Try, /*On fail goto*//*Label 4371*/ GIMT_Encode4(251511), // Rule ID 2203 // |
| 80779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80782 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80783 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 80784 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80785 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80786 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 80787 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 80788 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80789 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 80790 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80791 | // (zext:{ *:[i32] } (add:{ *:[i16] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2) |
| 80792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64), |
| 80793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 80795 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 80796 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 80797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80798 | GIR_RootConstrainSelectedInstOperands, |
| 80799 | // GIR_Coverage, 2203, |
| 80800 | GIR_EraseRootFromParent_Done, |
| 80801 | // Label 4371: @251511 |
| 80802 | GIM_Try, /*On fail goto*//*Label 4372*/ GIMT_Encode4(251582), // Rule ID 8125 // |
| 80803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80804 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80805 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80806 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80807 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 80808 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80809 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80810 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 80811 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_MUL), |
| 80812 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 80813 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 80814 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 80815 | // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src2, (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MAD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, VSrc_b16:{ *:[i16] }:$src2) |
| 80816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_U16_e64), |
| 80817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 80819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 80820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 80821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80822 | GIR_RootConstrainSelectedInstOperands, |
| 80823 | // GIR_Coverage, 8125, |
| 80824 | GIR_EraseRootFromParent_Done, |
| 80825 | // Label 4372: @251582 |
| 80826 | GIM_Try, /*On fail goto*//*Label 4373*/ GIMT_Encode4(251652), // Rule ID 7206 // |
| 80827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 80828 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80830 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80831 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BSWAP), |
| 80832 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80833 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80834 | // (zext:{ *:[i32] } (bswap:{ *:[i16] } i16:{ *:[i16] }:$a)) => (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] })) |
| 80835 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 80836 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 80837 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 80838 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(202113025), |
| 80839 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 80840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 80841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // a |
| 80844 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 80845 | GIR_RootConstrainSelectedInstOperands, |
| 80846 | // GIR_Coverage, 7206, |
| 80847 | GIR_EraseRootFromParent_Done, |
| 80848 | // Label 4373: @251652 |
| 80849 | GIM_Try, /*On fail goto*//*Label 4374*/ GIMT_Encode4(251703), // Rule ID 2158 // |
| 80850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80851 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80853 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80854 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 80855 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80856 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80857 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80858 | // (zext:{ *:[i32] } (add:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_ADD_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64), |
| 80860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80862 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 80863 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80864 | GIR_RootConstrainSelectedInstOperands, |
| 80865 | // GIR_Coverage, 2158, |
| 80866 | GIR_EraseRootFromParent_Done, |
| 80867 | // Label 4374: @251703 |
| 80868 | GIM_Try, /*On fail goto*//*Label 4375*/ GIMT_Encode4(251751), // Rule ID 2188 // |
| 80869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80870 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80872 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80873 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ASHR), |
| 80874 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80875 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80876 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80877 | // (zext:{ *:[i32] } (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_ASHRREV_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64), |
| 80879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80880 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 80881 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80882 | GIR_RootConstrainSelectedInstOperands, |
| 80883 | // GIR_Coverage, 2188, |
| 80884 | GIR_EraseRootFromParent_Done, |
| 80885 | // Label 4375: @251751 |
| 80886 | GIM_Try, /*On fail goto*//*Label 4376*/ GIMT_Encode4(251799), // Rule ID 2184 // |
| 80887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80888 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80889 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80890 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80891 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_LSHR), |
| 80892 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80893 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80894 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80895 | // (zext:{ *:[i32] } (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_LSHRREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64), |
| 80897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 80899 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80900 | GIR_RootConstrainSelectedInstOperands, |
| 80901 | // GIR_Coverage, 2184, |
| 80902 | GIR_EraseRootFromParent_Done, |
| 80903 | // Label 4376: @251799 |
| 80904 | GIM_Try, /*On fail goto*//*Label 4377*/ GIMT_Encode4(251847), // Rule ID 2168 // |
| 80905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80906 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80909 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_MUL), |
| 80910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80911 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80912 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80913 | // (zext:{ *:[i32] } (mul:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MUL_LO_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LO_U16_e64), |
| 80915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80916 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80917 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 80918 | GIR_RootConstrainSelectedInstOperands, |
| 80919 | // GIR_Coverage, 2168, |
| 80920 | GIR_EraseRootFromParent_Done, |
| 80921 | // Label 4377: @251847 |
| 80922 | GIM_Try, /*On fail goto*//*Label 4378*/ GIMT_Encode4(251895), // Rule ID 2180 // |
| 80923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80924 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SHL), |
| 80928 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80929 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80930 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80931 | // (zext:{ *:[i32] } (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_LSHLREV_B16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64), |
| 80933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80934 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 80935 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 80936 | GIR_RootConstrainSelectedInstOperands, |
| 80937 | // GIR_Coverage, 2180, |
| 80938 | GIR_EraseRootFromParent_Done, |
| 80939 | // Label 4378: @251895 |
| 80940 | GIM_Try, /*On fail goto*//*Label 4379*/ GIMT_Encode4(251943), // Rule ID 2174 // |
| 80941 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80942 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80944 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80945 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 80946 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80947 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80948 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80949 | // (zext:{ *:[i32] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MAX_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64), |
| 80951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80952 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80953 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 80954 | GIR_RootConstrainSelectedInstOperands, |
| 80955 | // GIR_Coverage, 2174, |
| 80956 | GIR_EraseRootFromParent_Done, |
| 80957 | // Label 4379: @251943 |
| 80958 | GIM_Try, /*On fail goto*//*Label 4380*/ GIMT_Encode4(251991), // Rule ID 2172 // |
| 80959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80960 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80962 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80963 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 80964 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80965 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80966 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80967 | // (zext:{ *:[i32] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MIN_I16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64), |
| 80969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80970 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80971 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 80972 | GIR_RootConstrainSelectedInstOperands, |
| 80973 | // GIR_Coverage, 2172, |
| 80974 | GIR_EraseRootFromParent_Done, |
| 80975 | // Label 4380: @251991 |
| 80976 | GIM_Try, /*On fail goto*//*Label 4381*/ GIMT_Encode4(252042), // Rule ID 2170 // |
| 80977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80978 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 80981 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), |
| 80982 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 80983 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 80984 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 80985 | // (zext:{ *:[i32] } (sub:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_SUB_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 80986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64), |
| 80987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 80988 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 80989 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 80990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 80991 | GIR_RootConstrainSelectedInstOperands, |
| 80992 | // GIR_Coverage, 2170, |
| 80993 | GIR_EraseRootFromParent_Done, |
| 80994 | // Label 4381: @252042 |
| 80995 | GIM_Try, /*On fail goto*//*Label 4382*/ GIMT_Encode4(252090), // Rule ID 2178 // |
| 80996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 80997 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 80998 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 80999 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81000 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 81001 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81002 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81003 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81004 | // (zext:{ *:[i32] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MAX_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 81005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64), |
| 81006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 81009 | GIR_RootConstrainSelectedInstOperands, |
| 81010 | // GIR_Coverage, 2178, |
| 81011 | GIR_EraseRootFromParent_Done, |
| 81012 | // Label 4382: @252090 |
| 81013 | GIM_Try, /*On fail goto*//*Label 4383*/ GIMT_Encode4(252138), // Rule ID 2176 // |
| 81014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8GFX9), |
| 81015 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 81019 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81020 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81021 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81022 | // (zext:{ *:[i32] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MIN_U16_e64:{ *:[i32] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1) |
| 81023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64), |
| 81024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81025 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 81027 | GIR_RootConstrainSelectedInstOperands, |
| 81028 | // GIR_Coverage, 2176, |
| 81029 | GIR_EraseRootFromParent_Done, |
| 81030 | // Label 4383: @252138 |
| 81031 | GIM_Try, /*On fail goto*//*Label 4384*/ GIMT_Encode4(252193), // Rule ID 1656 // |
| 81032 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81033 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81034 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18546), |
| 81035 | // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_18546>> => (S_AND_B32:{ *:[i32] }:{ *:[i1] } (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src) |
| 81036 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 81037 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81038 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81039 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 81040 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 81042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 81043 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81044 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 81045 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 81046 | GIR_RootConstrainSelectedInstOperands, |
| 81047 | // GIR_Coverage, 1656, |
| 81048 | GIR_EraseRootFromParent_Done, |
| 81049 | // Label 4384: @252193 |
| 81050 | GIM_Try, /*On fail goto*//*Label 4385*/ GIMT_Encode4(252245), // Rule ID 7189 // |
| 81051 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81053 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36143), |
| 81054 | // (zext:{ *:[i32] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_36143>> => (V_AND_B32_e64:{ *:[i32] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src) |
| 81055 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 81056 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81057 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81058 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(65535), |
| 81059 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 81061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81063 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 81064 | GIR_RootConstrainSelectedInstOperands, |
| 81065 | // GIR_Coverage, 7189, |
| 81066 | GIR_EraseRootFromParent_Done, |
| 81067 | // Label 4385: @252245 |
| 81068 | GIM_Try, /*On fail goto*//*Label 4386*/ GIMT_Encode4(252278), // Rule ID 7075 // |
| 81069 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 81070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81071 | // (zext:{ *:[i32] } i1:{ *:[i1] }:$src0) => (V_CNDMASK_B32_e64:{ *:[i32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, i1:{ *:[i1] }:$src0) |
| 81072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 81073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 81078 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81079 | GIR_RootConstrainSelectedInstOperands, |
| 81080 | // GIR_Coverage, 7075, |
| 81081 | GIR_EraseRootFromParent_Done, |
| 81082 | // Label 4386: @252278 |
| 81083 | GIM_Reject, |
| 81084 | // Label 4364: @252279 |
| 81085 | GIM_Try, /*On fail goto*//*Label 4387*/ GIMT_Encode4(252410), // Rule ID 1654 // |
| 81086 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81088 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18546), |
| 81089 | // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_18546>> => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_AND_B32:{ *:[i1] }:{ *:[i1] } ?:{ *:[i16] }:$src, (S_MOV_B32:{ *:[i1] } 65535:{ *:[i32] })), SGPR_32:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 81090 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 81091 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 81092 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 81093 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s1, |
| 81094 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81095 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81096 | GIR_AddImm8, /*InsnID*/4, /*Imm*/0, |
| 81097 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 81098 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81099 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81100 | GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(65535), |
| 81101 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 81102 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 81103 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81104 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 81105 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 81106 | GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for AMDGPU::SCC*/0, |
| 81107 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 81108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 81109 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81110 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 81111 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 81113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 81114 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81115 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 81116 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 81117 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 81118 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81119 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 81120 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 81121 | // GIR_Coverage, 1654, |
| 81122 | GIR_EraseRootFromParent_Done, |
| 81123 | // Label 4387: @252410 |
| 81124 | GIM_Try, /*On fail goto*//*Label 4388*/ GIMT_Encode4(252521), // Rule ID 7190 // |
| 81125 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81127 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36143), |
| 81128 | // (zext:{ *:[i64] } i16:{ *:[i16] }:$src)<<P:Predicate_anonymous_36143>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_AND_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 65535:{ *:[i32] }), ?:{ *:[i16] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 81129 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 81130 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 81131 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 81132 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81133 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81134 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 81135 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 81136 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81137 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81138 | GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(65535), |
| 81139 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 81140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 81141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81142 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 81143 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 81144 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 81146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 81147 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81148 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 81149 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 81150 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 81151 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81152 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81153 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81154 | // GIR_Coverage, 7190, |
| 81155 | GIR_EraseRootFromParent_Done, |
| 81156 | // Label 4388: @252521 |
| 81157 | GIM_Try, /*On fail goto*//*Label 4389*/ GIMT_Encode4(252582), // Rule ID 7148 // |
| 81158 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 81159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81160 | // (zext:{ *:[i64] } i32:{ *:[i32] }:$src) => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, ?:{ *:[i32] }:$src, sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 81161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 81162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81164 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 81165 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 81167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 81168 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 81169 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 81170 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81171 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 81172 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81173 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 81174 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 81175 | // GIR_Coverage, 7148, |
| 81176 | GIR_EraseRootFromParent_Done, |
| 81177 | // Label 4389: @252582 |
| 81178 | GIM_Try, /*On fail goto*//*Label 4390*/ GIMT_Encode4(252674), // Rule ID 7150 // |
| 81179 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 81180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81181 | // (zext:{ *:[i64] } i1:{ *:[i1] }:$src) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, ?:{ *:[i1] }:$src), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 81182 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 81183 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 81184 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 81185 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81186 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 81187 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 81188 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 81189 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 81190 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 81191 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 81192 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 81193 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 81194 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 81195 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 81196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 81197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 81198 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 81199 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 81200 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 81201 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 81202 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81203 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81204 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81205 | // GIR_Coverage, 7150, |
| 81206 | GIR_EraseRootFromParent_Done, |
| 81207 | // Label 4390: @252674 |
| 81208 | GIM_Reject, |
| 81209 | // Label 4365: @252675 |
| 81210 | GIM_Reject, |
| 81211 | // Label 46: @252676 |
| 81212 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4395*/ GIMT_Encode4(253865), |
| 81213 | /*GILLT_s16*//*Label 4391*/ GIMT_Encode4(252703), |
| 81214 | /*GILLT_s32*//*Label 4392*/ GIMT_Encode4(252860), |
| 81215 | /*GILLT_s64*//*Label 4393*/ GIMT_Encode4(253309), |
| 81216 | /*GILLT_v2s16*//*Label 4394*/ GIMT_Encode4(253696), |
| 81217 | // Label 4391: @252703 |
| 81218 | GIM_Try, /*On fail goto*//*Label 4396*/ GIMT_Encode4(252859), |
| 81219 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81220 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 81221 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81222 | GIM_Try, /*On fail goto*//*Label 4397*/ GIMT_Encode4(252769), // Rule ID 778 // |
| 81223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 81224 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81225 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81226 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81227 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81228 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81229 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81230 | // MIs[2] Operand 1 |
| 81231 | // No operand predicates |
| 81232 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 81233 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81234 | // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64), |
| 81236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81237 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81238 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81239 | GIR_RootConstrainSelectedInstOperands, |
| 81240 | // GIR_Coverage, 778, |
| 81241 | GIR_EraseRootFromParent_Done, |
| 81242 | // Label 4397: @252769 |
| 81243 | GIM_Try, /*On fail goto*//*Label 4398*/ GIMT_Encode4(252820), // Rule ID 780 // |
| 81244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 81245 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81246 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81247 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81248 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81249 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81250 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81251 | // MIs[2] Operand 1 |
| 81252 | // No operand predicates |
| 81253 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 81254 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81255 | // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_LSHLREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64), |
| 81257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81258 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81259 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81260 | GIR_RootConstrainSelectedInstOperands, |
| 81261 | // GIR_Coverage, 780, |
| 81262 | GIR_EraseRootFromParent_Done, |
| 81263 | // Label 4398: @252820 |
| 81264 | GIM_Try, /*On fail goto*//*Label 4399*/ GIMT_Encode4(252839), // Rule ID 777 // |
| 81265 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 81266 | // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_LSHLREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_e64), |
| 81268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81269 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81270 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81271 | GIR_RootConstrainSelectedInstOperands, |
| 81272 | // GIR_Coverage, 777, |
| 81273 | GIR_EraseRootFromParent_Done, |
| 81274 | // Label 4399: @252839 |
| 81275 | GIM_Try, /*On fail goto*//*Label 4400*/ GIMT_Encode4(252858), // Rule ID 779 // |
| 81276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 81277 | // (shl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_LSHLREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B16_t16_e64), |
| 81279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81280 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81281 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81282 | GIR_RootConstrainSelectedInstOperands, |
| 81283 | // GIR_Coverage, 779, |
| 81284 | GIR_EraseRootFromParent_Done, |
| 81285 | // Label 4400: @252858 |
| 81286 | GIM_Reject, |
| 81287 | // Label 4396: @252859 |
| 81288 | GIM_Reject, |
| 81289 | // Label 4392: @252860 |
| 81290 | GIM_Try, /*On fail goto*//*Label 4401*/ GIMT_Encode4(253308), |
| 81291 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 81292 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 81293 | GIM_Try, /*On fail goto*//*Label 4402*/ GIMT_Encode4(252966), // Rule ID 2223 // |
| 81294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 81295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81297 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 81298 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81299 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81300 | GIM_CheckHasOneUse, /*MI*/1, |
| 81301 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x |
| 81302 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y |
| 81303 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 81304 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 81305 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 81306 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 81307 | GIM_RecordNamedOperand, /*MI*/2, /*Op*/1, /*StoreIdx*/2, // Name : pred:2:z |
| 81308 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 81309 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81310 | // MIs[3] Operand 1 |
| 81311 | // No operand predicates |
| 81312 | GIM_CheckCxxInsnPredicate, /*MI*/2, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24025), |
| 81314 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 81315 | // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_24026>>, (and:{ *:[i32] } i32:{ *:[i32] }:$src2:$pred:2:z, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:2:Predicate_anonymous_24025>> => (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 81316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64), |
| 81317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81318 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81319 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 81320 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 81321 | GIR_RootConstrainSelectedInstOperands, |
| 81322 | // GIR_Coverage, 2223, |
| 81323 | GIR_EraseRootFromParent_Done, |
| 81324 | // Label 4402: @252966 |
| 81325 | GIM_Try, /*On fail goto*//*Label 4403*/ GIMT_Encode4(253034), // Rule ID 71 // |
| 81326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81327 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81328 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81329 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81330 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81331 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81332 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81333 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81334 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81335 | // MIs[2] Operand 1 |
| 81336 | // No operand predicates |
| 81337 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81338 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18509), |
| 81339 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81340 | // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_18509>> => (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 81342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 81343 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81344 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81345 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 81346 | GIR_RootConstrainSelectedInstOperands, |
| 81347 | // GIR_Coverage, 71, |
| 81348 | GIR_EraseRootFromParent_Done, |
| 81349 | // Label 4403: @253034 |
| 81350 | GIM_Try, /*On fail goto*//*Label 4404*/ GIMT_Encode4(253099), // Rule ID 2222 // |
| 81351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 81352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81353 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 81354 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_ADD), |
| 81355 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81356 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81357 | GIM_CheckHasOneUse, /*MI*/1, |
| 81358 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:2:x |
| 81359 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:2:y |
| 81360 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:2:z |
| 81361 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24025), |
| 81362 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 81363 | // (shl:{ *:[i32] } (add:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:2:x, i32:{ *:[i32] }:$src1:$pred:2:y)<<P:Predicate_anonymous_24026>>, i32:{ *:[i32] }:$src2:$pred:2:z)<<P:2:Predicate_anonymous_24025>> => (V_ADD_LSHL_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 81364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_LSHL_U32_e64), |
| 81365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 81368 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 81369 | GIR_RootConstrainSelectedInstOperands, |
| 81370 | // GIR_Coverage, 2222, |
| 81371 | GIR_EraseRootFromParent_Done, |
| 81372 | // Label 4404: @253099 |
| 81373 | GIM_Try, /*On fail goto*//*Label 4405*/ GIMT_Encode4(253133), // Rule ID 70 // |
| 81374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81375 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81376 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81377 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18509), |
| 81378 | // (shl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18509>> => (S_LSHL_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81379 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B32), |
| 81380 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 81381 | GIR_RootConstrainSelectedInstOperands, |
| 81382 | // GIR_Coverage, 70, |
| 81383 | GIR_Done, |
| 81384 | // Label 4405: @253133 |
| 81385 | GIM_Try, /*On fail goto*//*Label 4406*/ GIMT_Encode4(253157), // Rule ID 2130 // |
| 81386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81387 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23237), |
| 81388 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23237>> => (V_LSHLREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0) |
| 81389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 81390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81391 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 81392 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81393 | GIR_RootConstrainSelectedInstOperands, |
| 81394 | // GIR_Coverage, 2130, |
| 81395 | GIR_EraseRootFromParent_Done, |
| 81396 | // Label 4406: @253157 |
| 81397 | GIM_Try, /*On fail goto*//*Label 4407*/ GIMT_Encode4(253209), // Rule ID 750 // |
| 81398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81399 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81400 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81401 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81402 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81403 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81404 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81405 | // MIs[2] Operand 1 |
| 81406 | // No operand predicates |
| 81407 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81408 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81409 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 81411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81412 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81413 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81414 | GIR_RootConstrainSelectedInstOperands, |
| 81415 | // GIR_Coverage, 750, |
| 81416 | GIR_EraseRootFromParent_Done, |
| 81417 | // Label 4407: @253209 |
| 81418 | GIM_Try, /*On fail goto*//*Label 4408*/ GIMT_Encode4(253264), // Rule ID 776 // |
| 81419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81421 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81422 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81423 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81424 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81425 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81426 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81427 | // MIs[2] Operand 1 |
| 81428 | // No operand predicates |
| 81429 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81430 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81431 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64), |
| 81433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81434 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81436 | GIR_RootConstrainSelectedInstOperands, |
| 81437 | // GIR_Coverage, 776, |
| 81438 | GIR_EraseRootFromParent_Done, |
| 81439 | // Label 4408: @253264 |
| 81440 | GIM_Try, /*On fail goto*//*Label 4409*/ GIMT_Encode4(253284), // Rule ID 749 // |
| 81441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81442 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0) => (V_LSHLREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 81444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81445 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81446 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81447 | GIR_RootConstrainSelectedInstOperands, |
| 81448 | // GIR_Coverage, 749, |
| 81449 | GIR_EraseRootFromParent_Done, |
| 81450 | // Label 4409: @253284 |
| 81451 | GIM_Try, /*On fail goto*//*Label 4410*/ GIMT_Encode4(253307), // Rule ID 775 // |
| 81452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81454 | // (shl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_LSHL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81455 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B32_e64), |
| 81456 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 81457 | GIR_RootConstrainSelectedInstOperands, |
| 81458 | // GIR_Coverage, 775, |
| 81459 | GIR_Done, |
| 81460 | // Label 4410: @253307 |
| 81461 | GIM_Reject, |
| 81462 | // Label 4401: @253308 |
| 81463 | GIM_Reject, |
| 81464 | // Label 4393: @253309 |
| 81465 | GIM_Try, /*On fail goto*//*Label 4411*/ GIMT_Encode4(253695), |
| 81466 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 81467 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 81468 | GIM_Try, /*On fail goto*//*Label 4412*/ GIMT_Encode4(253388), // Rule ID 73 // |
| 81469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81470 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81471 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81472 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81473 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81474 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81475 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81476 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81477 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81478 | // MIs[2] Operand 1 |
| 81479 | // No operand predicates |
| 81480 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81481 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18510), |
| 81482 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81483 | // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_18510>> => (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64), |
| 81485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 81486 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81487 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81488 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 81489 | GIR_RootConstrainSelectedInstOperands, |
| 81490 | // GIR_Coverage, 73, |
| 81491 | GIR_EraseRootFromParent_Done, |
| 81492 | // Label 4412: @253388 |
| 81493 | GIM_Try, /*On fail goto*//*Label 4413*/ GIMT_Encode4(253422), // Rule ID 72 // |
| 81494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81495 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81496 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81497 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18510), |
| 81498 | // (shl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18510>> => (S_LSHL_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81499 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHL_B64), |
| 81500 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 81501 | GIR_RootConstrainSelectedInstOperands, |
| 81502 | // GIR_Coverage, 72, |
| 81503 | GIR_Done, |
| 81504 | // Label 4413: @253422 |
| 81505 | GIM_Try, /*On fail goto*//*Label 4414*/ GIMT_Encode4(253487), // Rule ID 902 // |
| 81506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81511 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81512 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81514 | // MIs[2] Operand 1 |
| 81515 | // No operand predicates |
| 81516 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81517 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81519 | // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 81520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64), |
| 81521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81523 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81524 | GIR_RootConstrainSelectedInstOperands, |
| 81525 | // GIR_Coverage, 902, |
| 81526 | GIR_EraseRootFromParent_Done, |
| 81527 | // Label 4414: @253487 |
| 81528 | GIM_Try, /*On fail goto*//*Label 4415*/ GIMT_Encode4(253550), // Rule ID 912 // |
| 81529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11), |
| 81530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81531 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81532 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81533 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81534 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81535 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81536 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81537 | // MIs[2] Operand 1 |
| 81538 | // No operand predicates |
| 81539 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81540 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81541 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81542 | // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64), |
| 81544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81546 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81547 | GIR_RootConstrainSelectedInstOperands, |
| 81548 | // GIR_Coverage, 912, |
| 81549 | GIR_EraseRootFromParent_Done, |
| 81550 | // Label 4415: @253550 |
| 81551 | GIM_Try, /*On fail goto*//*Label 4416*/ GIMT_Encode4(253583), // Rule ID 901 // |
| 81552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81554 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81555 | // (shl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1) => (V_LSHL_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 81556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHL_B64_e64), |
| 81557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81559 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 81560 | GIR_RootConstrainSelectedInstOperands, |
| 81561 | // GIR_Coverage, 901, |
| 81562 | GIR_EraseRootFromParent_Done, |
| 81563 | // Label 4416: @253583 |
| 81564 | GIM_Try, /*On fail goto*//*Label 4417*/ GIMT_Encode4(253616), // Rule ID 911 // |
| 81565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8GFX9GFX10GFX11), |
| 81566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81568 | // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_LSHLREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_e64), |
| 81570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81572 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81573 | GIR_RootConstrainSelectedInstOperands, |
| 81574 | // GIR_Coverage, 911, |
| 81575 | GIR_EraseRootFromParent_Done, |
| 81576 | // Label 4417: @253616 |
| 81577 | GIM_Try, /*On fail goto*//*Label 4418*/ GIMT_Encode4(253671), // Rule ID 843 // |
| 81578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 81579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81580 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81581 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81582 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81583 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81584 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81585 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81586 | // MIs[2] Operand 1 |
| 81587 | // No operand predicates |
| 81588 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81589 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81590 | // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64), |
| 81592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81593 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81594 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81595 | GIR_RootConstrainSelectedInstOperands, |
| 81596 | // GIR_Coverage, 843, |
| 81597 | GIR_EraseRootFromParent_Done, |
| 81598 | // Label 4418: @253671 |
| 81599 | GIM_Try, /*On fail goto*//*Label 4419*/ GIMT_Encode4(253694), // Rule ID 842 // |
| 81600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 81601 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81602 | // (shl:{ *:[i64] } i64:{ *:[i64] }:$src1, i32:{ *:[i32] }:$src0) => (V_LSHLREV_B64_pseudo_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81603 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B64_pseudo_e64), |
| 81604 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81605 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81606 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81607 | GIR_RootConstrainSelectedInstOperands, |
| 81608 | // GIR_Coverage, 842, |
| 81609 | GIR_EraseRootFromParent_Done, |
| 81610 | // Label 4419: @253694 |
| 81611 | GIM_Reject, |
| 81612 | // Label 4411: @253695 |
| 81613 | GIM_Reject, |
| 81614 | // Label 4394: @253696 |
| 81615 | GIM_Try, /*On fail goto*//*Label 4420*/ GIMT_Encode4(253864), |
| 81616 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 81617 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 81618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81619 | GIM_Try, /*On fail goto*//*Label 4421*/ GIMT_Encode4(253802), // Rule ID 975 // |
| 81620 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81621 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81622 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 81623 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 81624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81625 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81626 | // MIs[2] Operand 1 |
| 81627 | // No operand predicates |
| 81628 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 81629 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 81631 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 81632 | // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>) => (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 81633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16), |
| 81634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 81636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 81637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 81638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 81639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81644 | GIR_RootConstrainSelectedInstOperands, |
| 81645 | // GIR_Coverage, 975, |
| 81646 | GIR_EraseRootFromParent_Done, |
| 81647 | // Label 4421: @253802 |
| 81648 | GIM_Try, /*On fail goto*//*Label 4422*/ GIMT_Encode4(253863), // Rule ID 974 // |
| 81649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 81650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 81651 | // (shl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_PK_LSHLREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 81652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHLREV_B16), |
| 81653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 81655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 81656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 81657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 81658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 81663 | GIR_RootConstrainSelectedInstOperands, |
| 81664 | // GIR_Coverage, 974, |
| 81665 | GIR_EraseRootFromParent_Done, |
| 81666 | // Label 4422: @253863 |
| 81667 | GIM_Reject, |
| 81668 | // Label 4420: @253864 |
| 81669 | GIM_Reject, |
| 81670 | // Label 4395: @253865 |
| 81671 | GIM_Reject, |
| 81672 | // Label 47: @253866 |
| 81673 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4427*/ GIMT_Encode4(254817), |
| 81674 | /*GILLT_s16*//*Label 4423*/ GIMT_Encode4(253893), |
| 81675 | /*GILLT_s32*//*Label 4424*/ GIMT_Encode4(254050), |
| 81676 | /*GILLT_s64*//*Label 4425*/ GIMT_Encode4(254339), |
| 81677 | /*GILLT_v2s16*//*Label 4426*/ GIMT_Encode4(254648), |
| 81678 | // Label 4423: @253893 |
| 81679 | GIM_Try, /*On fail goto*//*Label 4428*/ GIMT_Encode4(254049), |
| 81680 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 81681 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 81682 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81683 | GIM_Try, /*On fail goto*//*Label 4429*/ GIMT_Encode4(253959), // Rule ID 782 // |
| 81684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 81685 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81686 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81687 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81688 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81689 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81690 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81691 | // MIs[2] Operand 1 |
| 81692 | // No operand predicates |
| 81693 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 81694 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81695 | // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64), |
| 81697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81699 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81700 | GIR_RootConstrainSelectedInstOperands, |
| 81701 | // GIR_Coverage, 782, |
| 81702 | GIR_EraseRootFromParent_Done, |
| 81703 | // Label 4429: @253959 |
| 81704 | GIM_Try, /*On fail goto*//*Label 4430*/ GIMT_Encode4(254010), // Rule ID 784 // |
| 81705 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 81706 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81707 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81708 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 81709 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 81710 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81711 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81712 | // MIs[2] Operand 1 |
| 81713 | // No operand predicates |
| 81714 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 81715 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81716 | // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_LSHRREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64), |
| 81718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81719 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81720 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81721 | GIR_RootConstrainSelectedInstOperands, |
| 81722 | // GIR_Coverage, 784, |
| 81723 | GIR_EraseRootFromParent_Done, |
| 81724 | // Label 4430: @254010 |
| 81725 | GIM_Try, /*On fail goto*//*Label 4431*/ GIMT_Encode4(254029), // Rule ID 781 // |
| 81726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 81727 | // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_LSHRREV_B16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_e64), |
| 81729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81730 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81731 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81732 | GIR_RootConstrainSelectedInstOperands, |
| 81733 | // GIR_Coverage, 781, |
| 81734 | GIR_EraseRootFromParent_Done, |
| 81735 | // Label 4431: @254029 |
| 81736 | GIM_Try, /*On fail goto*//*Label 4432*/ GIMT_Encode4(254048), // Rule ID 783 // |
| 81737 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 81738 | // (srl:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_LSHRREV_B16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 81739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B16_t16_e64), |
| 81740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81741 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81742 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81743 | GIR_RootConstrainSelectedInstOperands, |
| 81744 | // GIR_Coverage, 783, |
| 81745 | GIR_EraseRootFromParent_Done, |
| 81746 | // Label 4432: @254048 |
| 81747 | GIM_Reject, |
| 81748 | // Label 4428: @254049 |
| 81749 | GIM_Reject, |
| 81750 | // Label 4424: @254050 |
| 81751 | GIM_Try, /*On fail goto*//*Label 4433*/ GIMT_Encode4(254338), |
| 81752 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 81753 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 81754 | GIM_Try, /*On fail goto*//*Label 4434*/ GIMT_Encode4(254129), // Rule ID 75 // |
| 81755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81756 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81757 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81758 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81759 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81760 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81761 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81762 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81763 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81764 | // MIs[2] Operand 1 |
| 81765 | // No operand predicates |
| 81766 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81767 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18511), |
| 81768 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81769 | // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_18511>> => (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32), |
| 81771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 81772 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81773 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81774 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 81775 | GIR_RootConstrainSelectedInstOperands, |
| 81776 | // GIR_Coverage, 75, |
| 81777 | GIR_EraseRootFromParent_Done, |
| 81778 | // Label 4434: @254129 |
| 81779 | GIM_Try, /*On fail goto*//*Label 4435*/ GIMT_Encode4(254163), // Rule ID 74 // |
| 81780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81781 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81782 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81783 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18511), |
| 81784 | // (srl:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18511>> => (S_LSHR_B32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81785 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B32), |
| 81786 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 81787 | GIR_RootConstrainSelectedInstOperands, |
| 81788 | // GIR_Coverage, 74, |
| 81789 | GIR_Done, |
| 81790 | // Label 4435: @254163 |
| 81791 | GIM_Try, /*On fail goto*//*Label 4436*/ GIMT_Encode4(254187), // Rule ID 2126 // |
| 81792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23233), |
| 81794 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23233>> => (V_LSHRREV_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0) |
| 81795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64), |
| 81796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81797 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 81798 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81799 | GIR_RootConstrainSelectedInstOperands, |
| 81800 | // GIR_Coverage, 2126, |
| 81801 | GIR_EraseRootFromParent_Done, |
| 81802 | // Label 4436: @254187 |
| 81803 | GIM_Try, /*On fail goto*//*Label 4437*/ GIMT_Encode4(254239), // Rule ID 746 // |
| 81804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81806 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81808 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81809 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81810 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81811 | // MIs[2] Operand 1 |
| 81812 | // No operand predicates |
| 81813 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81814 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81815 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64), |
| 81817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81818 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 81819 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81820 | GIR_RootConstrainSelectedInstOperands, |
| 81821 | // GIR_Coverage, 746, |
| 81822 | GIR_EraseRootFromParent_Done, |
| 81823 | // Label 4437: @254239 |
| 81824 | GIM_Try, /*On fail goto*//*Label 4438*/ GIMT_Encode4(254294), // Rule ID 772 // |
| 81825 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81826 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81827 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81828 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81829 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81830 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81831 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81832 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81833 | // MIs[2] Operand 1 |
| 81834 | // No operand predicates |
| 81835 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 81836 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81837 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64), |
| 81839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81840 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81841 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81842 | GIR_RootConstrainSelectedInstOperands, |
| 81843 | // GIR_Coverage, 772, |
| 81844 | GIR_EraseRootFromParent_Done, |
| 81845 | // Label 4438: @254294 |
| 81846 | GIM_Try, /*On fail goto*//*Label 4439*/ GIMT_Encode4(254314), // Rule ID 745 // |
| 81847 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81848 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0) => (V_LSHRREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64), |
| 81850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81851 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 81852 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81853 | GIR_RootConstrainSelectedInstOperands, |
| 81854 | // GIR_Coverage, 745, |
| 81855 | GIR_EraseRootFromParent_Done, |
| 81856 | // Label 4439: @254314 |
| 81857 | GIM_Try, /*On fail goto*//*Label 4440*/ GIMT_Encode4(254337), // Rule ID 771 // |
| 81858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81860 | // (srl:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_LSHR_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 81861 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B32_e64), |
| 81862 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 81863 | GIR_RootConstrainSelectedInstOperands, |
| 81864 | // GIR_Coverage, 771, |
| 81865 | GIR_Done, |
| 81866 | // Label 4440: @254337 |
| 81867 | GIM_Reject, |
| 81868 | // Label 4433: @254338 |
| 81869 | GIM_Reject, |
| 81870 | // Label 4425: @254339 |
| 81871 | GIM_Try, /*On fail goto*//*Label 4441*/ GIMT_Encode4(254647), |
| 81872 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 81873 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 81874 | GIM_Try, /*On fail goto*//*Label 4442*/ GIMT_Encode4(254418), // Rule ID 77 // |
| 81875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81876 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81877 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81878 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81879 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81880 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81881 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81882 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81883 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81884 | // MIs[2] Operand 1 |
| 81885 | // No operand predicates |
| 81886 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81887 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18512), |
| 81888 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81889 | // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_18512>> => (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64), |
| 81891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 81892 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 81893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81894 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 81895 | GIR_RootConstrainSelectedInstOperands, |
| 81896 | // GIR_Coverage, 77, |
| 81897 | GIR_EraseRootFromParent_Done, |
| 81898 | // Label 4442: @254418 |
| 81899 | GIM_Try, /*On fail goto*//*Label 4443*/ GIMT_Encode4(254452), // Rule ID 76 // |
| 81900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81901 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 81902 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 81903 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18512), |
| 81904 | // (srl:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18512>> => (S_LSHR_B64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 81905 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_LSHR_B64), |
| 81906 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 81907 | GIR_RootConstrainSelectedInstOperands, |
| 81908 | // GIR_Coverage, 76, |
| 81909 | GIR_Done, |
| 81910 | // Label 4443: @254452 |
| 81911 | GIM_Try, /*On fail goto*//*Label 4444*/ GIMT_Encode4(254517), // Rule ID 904 // |
| 81912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81915 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81916 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81917 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81918 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81919 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81920 | // MIs[2] Operand 1 |
| 81921 | // No operand predicates |
| 81922 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81923 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81924 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81925 | // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 81926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64), |
| 81927 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 81930 | GIR_RootConstrainSelectedInstOperands, |
| 81931 | // GIR_Coverage, 904, |
| 81932 | GIR_EraseRootFromParent_Done, |
| 81933 | // Label 4444: @254517 |
| 81934 | GIM_Try, /*On fail goto*//*Label 4445*/ GIMT_Encode4(254580), // Rule ID 908 // |
| 81935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 81936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81937 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81938 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81939 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 81940 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 81941 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81942 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81943 | // MIs[2] Operand 1 |
| 81944 | // No operand predicates |
| 81945 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 81946 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 81947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81948 | // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64), |
| 81950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81952 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81953 | GIR_RootConstrainSelectedInstOperands, |
| 81954 | // GIR_Coverage, 908, |
| 81955 | GIR_EraseRootFromParent_Done, |
| 81956 | // Label 4445: @254580 |
| 81957 | GIM_Try, /*On fail goto*//*Label 4446*/ GIMT_Encode4(254613), // Rule ID 903 // |
| 81958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 81959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81961 | // (srl:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1) => (V_LSHR_B64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 81962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHR_B64_e64), |
| 81963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81965 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 81966 | GIR_RootConstrainSelectedInstOperands, |
| 81967 | // GIR_Coverage, 903, |
| 81968 | GIR_EraseRootFromParent_Done, |
| 81969 | // Label 4446: @254613 |
| 81970 | GIM_Try, /*On fail goto*//*Label 4447*/ GIMT_Encode4(254646), // Rule ID 907 // |
| 81971 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 81972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 81973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 81974 | // (srl:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_LSHRREV_B64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 81975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B64_e64), |
| 81976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 81977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 81978 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 81979 | GIR_RootConstrainSelectedInstOperands, |
| 81980 | // GIR_Coverage, 907, |
| 81981 | GIR_EraseRootFromParent_Done, |
| 81982 | // Label 4447: @254646 |
| 81983 | GIM_Reject, |
| 81984 | // Label 4441: @254647 |
| 81985 | GIM_Reject, |
| 81986 | // Label 4426: @254648 |
| 81987 | GIM_Try, /*On fail goto*//*Label 4448*/ GIMT_Encode4(254816), |
| 81988 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 81989 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 81990 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 81991 | GIM_Try, /*On fail goto*//*Label 4449*/ GIMT_Encode4(254754), // Rule ID 979 // |
| 81992 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 81993 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 81994 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 81995 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 81996 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 81997 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 81998 | // MIs[2] Operand 1 |
| 81999 | // No operand predicates |
| 82000 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 82001 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82002 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82003 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82004 | // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>) => (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 82005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16), |
| 82006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 82008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 82009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 82010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 82011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82016 | GIR_RootConstrainSelectedInstOperands, |
| 82017 | // GIR_Coverage, 979, |
| 82018 | GIR_EraseRootFromParent_Done, |
| 82019 | // Label 4449: @254754 |
| 82020 | GIM_Try, /*On fail goto*//*Label 4450*/ GIMT_Encode4(254815), // Rule ID 978 // |
| 82021 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82023 | // (srl:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_PK_LSHRREV_B16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 82024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_LSHRREV_B16), |
| 82025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 82027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 82028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 82029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 82030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82035 | GIR_RootConstrainSelectedInstOperands, |
| 82036 | // GIR_Coverage, 978, |
| 82037 | GIR_EraseRootFromParent_Done, |
| 82038 | // Label 4450: @254815 |
| 82039 | GIM_Reject, |
| 82040 | // Label 4448: @254816 |
| 82041 | GIM_Reject, |
| 82042 | // Label 4427: @254817 |
| 82043 | GIM_Reject, |
| 82044 | // Label 48: @254818 |
| 82045 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4455*/ GIMT_Encode4(255769), |
| 82046 | /*GILLT_s16*//*Label 4451*/ GIMT_Encode4(254845), |
| 82047 | /*GILLT_s32*//*Label 4452*/ GIMT_Encode4(255002), |
| 82048 | /*GILLT_s64*//*Label 4453*/ GIMT_Encode4(255291), |
| 82049 | /*GILLT_v2s16*//*Label 4454*/ GIMT_Encode4(255600), |
| 82050 | // Label 4451: @254845 |
| 82051 | GIM_Try, /*On fail goto*//*Label 4456*/ GIMT_Encode4(255001), |
| 82052 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 82053 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 82054 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82055 | GIM_Try, /*On fail goto*//*Label 4457*/ GIMT_Encode4(254911), // Rule ID 786 // |
| 82056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82057 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82058 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82059 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 82060 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 82061 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82062 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82063 | // MIs[2] Operand 1 |
| 82064 | // No operand predicates |
| 82065 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 82066 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82067 | // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64), |
| 82069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82070 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 82071 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82072 | GIR_RootConstrainSelectedInstOperands, |
| 82073 | // GIR_Coverage, 786, |
| 82074 | GIR_EraseRootFromParent_Done, |
| 82075 | // Label 4457: @254911 |
| 82076 | GIM_Try, /*On fail goto*//*Label 4458*/ GIMT_Encode4(254962), // Rule ID 788 // |
| 82077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 82078 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82079 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82080 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 82081 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 82082 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82083 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82084 | // MIs[2] Operand 1 |
| 82085 | // No operand predicates |
| 82086 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 82087 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82088 | // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, (and:{ *:[i16] } i16:{ *:[i16] }:$src0, (imm:{ *:[i16] }))<<P:Predicate_csh_mask_16>>) => (V_ASHRREV_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64), |
| 82090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 82092 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82093 | GIR_RootConstrainSelectedInstOperands, |
| 82094 | // GIR_Coverage, 788, |
| 82095 | GIR_EraseRootFromParent_Done, |
| 82096 | // Label 4458: @254962 |
| 82097 | GIM_Try, /*On fail goto*//*Label 4459*/ GIMT_Encode4(254981), // Rule ID 785 // |
| 82098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82099 | // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_ASHRREV_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_e64), |
| 82101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82102 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82103 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82104 | GIR_RootConstrainSelectedInstOperands, |
| 82105 | // GIR_Coverage, 785, |
| 82106 | GIR_EraseRootFromParent_Done, |
| 82107 | // Label 4459: @254981 |
| 82108 | GIM_Try, /*On fail goto*//*Label 4460*/ GIMT_Encode4(255000), // Rule ID 787 // |
| 82109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 82110 | // (sra:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0) => (V_ASHRREV_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I16_t16_e64), |
| 82112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82113 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82114 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82115 | GIR_RootConstrainSelectedInstOperands, |
| 82116 | // GIR_Coverage, 787, |
| 82117 | GIR_EraseRootFromParent_Done, |
| 82118 | // Label 4460: @255000 |
| 82119 | GIM_Reject, |
| 82120 | // Label 4456: @255001 |
| 82121 | GIM_Reject, |
| 82122 | // Label 4452: @255002 |
| 82123 | GIM_Try, /*On fail goto*//*Label 4461*/ GIMT_Encode4(255290), |
| 82124 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 82125 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 82126 | GIM_Try, /*On fail goto*//*Label 4462*/ GIMT_Encode4(255081), // Rule ID 79 // |
| 82127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82128 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82129 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82130 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82131 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82132 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82133 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82134 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82135 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82136 | // MIs[2] Operand 1 |
| 82137 | // No operand predicates |
| 82138 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 82139 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18513), |
| 82140 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82141 | // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>)<<P:Predicate_anonymous_18513>> => (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 82142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32), |
| 82143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82144 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 82146 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 82147 | GIR_RootConstrainSelectedInstOperands, |
| 82148 | // GIR_Coverage, 79, |
| 82149 | GIR_EraseRootFromParent_Done, |
| 82150 | // Label 4462: @255081 |
| 82151 | GIM_Try, /*On fail goto*//*Label 4463*/ GIMT_Encode4(255115), // Rule ID 78 // |
| 82152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82153 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82154 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82155 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18513), |
| 82156 | // (sra:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18513>> => (S_ASHR_I32:{ *:[i32] }:{ *:[i1] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 82157 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I32), |
| 82158 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 82159 | GIR_RootConstrainSelectedInstOperands, |
| 82160 | // GIR_Coverage, 78, |
| 82161 | GIR_Done, |
| 82162 | // Label 4463: @255115 |
| 82163 | GIM_Try, /*On fail goto*//*Label 4464*/ GIMT_Encode4(255139), // Rule ID 2128 // |
| 82164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82165 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23235), |
| 82166 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_23235>> => (V_ASHRREV_I32_e64:{ *:[i32] } ?:{ *:[i32] }:$src1, ?:{ *:[i32] }:$src0) |
| 82167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64), |
| 82168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82169 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 82170 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82171 | GIR_RootConstrainSelectedInstOperands, |
| 82172 | // GIR_Coverage, 2128, |
| 82173 | GIR_EraseRootFromParent_Done, |
| 82174 | // Label 4464: @255139 |
| 82175 | GIM_Try, /*On fail goto*//*Label 4465*/ GIMT_Encode4(255191), // Rule ID 748 // |
| 82176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82177 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82178 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82179 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82180 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82181 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82182 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82183 | // MIs[2] Operand 1 |
| 82184 | // No operand predicates |
| 82185 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 82186 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82187 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, (and:{ *:[i32] } i32:{ *:[i32] }:$src0, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64), |
| 82189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82190 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 82191 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82192 | GIR_RootConstrainSelectedInstOperands, |
| 82193 | // GIR_Coverage, 748, |
| 82194 | GIR_EraseRootFromParent_Done, |
| 82195 | // Label 4465: @255191 |
| 82196 | GIM_Try, /*On fail goto*//*Label 4466*/ GIMT_Encode4(255246), // Rule ID 774 // |
| 82197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 82198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82202 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82203 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82204 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82205 | // MIs[2] Operand 1 |
| 82206 | // No operand predicates |
| 82207 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_32), |
| 82208 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82209 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_32>>) => (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64), |
| 82211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82212 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 82214 | GIR_RootConstrainSelectedInstOperands, |
| 82215 | // GIR_Coverage, 774, |
| 82216 | GIR_EraseRootFromParent_Done, |
| 82217 | // Label 4466: @255246 |
| 82218 | GIM_Try, /*On fail goto*//*Label 4467*/ GIMT_Encode4(255266), // Rule ID 747 // |
| 82219 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82220 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0) => (V_ASHRREV_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I32_e64), |
| 82222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82223 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82224 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82225 | GIR_RootConstrainSelectedInstOperands, |
| 82226 | // GIR_Coverage, 747, |
| 82227 | GIR_EraseRootFromParent_Done, |
| 82228 | // Label 4467: @255266 |
| 82229 | GIM_Try, /*On fail goto*//*Label 4468*/ GIMT_Encode4(255289), // Rule ID 773 // |
| 82230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 82231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82232 | // (sra:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_ASHR_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82233 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I32_e64), |
| 82234 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 82235 | GIR_RootConstrainSelectedInstOperands, |
| 82236 | // GIR_Coverage, 773, |
| 82237 | GIR_Done, |
| 82238 | // Label 4468: @255289 |
| 82239 | GIM_Reject, |
| 82240 | // Label 4461: @255290 |
| 82241 | GIM_Reject, |
| 82242 | // Label 4453: @255291 |
| 82243 | GIM_Try, /*On fail goto*//*Label 4469*/ GIMT_Encode4(255599), |
| 82244 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 82245 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 82246 | GIM_Try, /*On fail goto*//*Label 4470*/ GIMT_Encode4(255370), // Rule ID 81 // |
| 82247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 82248 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 82249 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82250 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82251 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82252 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82253 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82254 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82255 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82256 | // MIs[2] Operand 1 |
| 82257 | // No operand predicates |
| 82258 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 82259 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18514), |
| 82260 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82261 | // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, (and:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>)<<P:Predicate_anonymous_18514>> => (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 82262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64), |
| 82263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82264 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82265 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 82266 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 82267 | GIR_RootConstrainSelectedInstOperands, |
| 82268 | // GIR_Coverage, 81, |
| 82269 | GIR_EraseRootFromParent_Done, |
| 82270 | // Label 4470: @255370 |
| 82271 | GIM_Try, /*On fail goto*//*Label 4471*/ GIMT_Encode4(255404), // Rule ID 80 // |
| 82272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 82273 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 82274 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 82275 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18514), |
| 82276 | // (sra:{ *:[i64] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18514>> => (S_ASHR_I64:{ *:[i64] }:{ *:[i1] } SSrc_b64:{ *:[i64] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 82277 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ASHR_I64), |
| 82278 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 82279 | GIR_RootConstrainSelectedInstOperands, |
| 82280 | // GIR_Coverage, 80, |
| 82281 | GIR_Done, |
| 82282 | // Label 4471: @255404 |
| 82283 | GIM_Try, /*On fail goto*//*Label 4472*/ GIMT_Encode4(255469), // Rule ID 906 // |
| 82284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 82285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 82286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82287 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82289 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82290 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82291 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82292 | // MIs[2] Operand 1 |
| 82293 | // No operand predicates |
| 82294 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 82295 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 82297 | // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), (and:{ *:[i32] } i32:{ *:[i32] }:$src1, (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 82298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64), |
| 82299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 82301 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 82302 | GIR_RootConstrainSelectedInstOperands, |
| 82303 | // GIR_Coverage, 906, |
| 82304 | GIR_EraseRootFromParent_Done, |
| 82305 | // Label 4472: @255469 |
| 82306 | GIM_Try, /*On fail goto*//*Label 4473*/ GIMT_Encode4(255532), // Rule ID 910 // |
| 82307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 82308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 82309 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82310 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82311 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 82312 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 82313 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82314 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82315 | // MIs[2] Operand 1 |
| 82316 | // No operand predicates |
| 82317 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_64), |
| 82318 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82319 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 82320 | // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (and:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), (imm:{ *:[i32] }))<<P:Predicate_csh_mask_64>>) => (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 82321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64), |
| 82322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 82324 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82325 | GIR_RootConstrainSelectedInstOperands, |
| 82326 | // GIR_Coverage, 910, |
| 82327 | GIR_EraseRootFromParent_Done, |
| 82328 | // Label 4473: @255532 |
| 82329 | GIM_Try, /*On fail goto*//*Label 4474*/ GIMT_Encode4(255565), // Rule ID 905 // |
| 82330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 82331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 82332 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 82333 | // (sra:{ *:[i64] } (VOP3Mods0:{ *:[i64] } i64:{ *:[i64] }:$src0), i32:{ *:[i32] }:$src1) => (V_ASHR_I64_e64:{ *:[i64] } i64:{ *:[i64] }:$src0, i32:{ *:[i32] }:$src1) |
| 82334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHR_I64_e64), |
| 82335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 82337 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 82338 | GIR_RootConstrainSelectedInstOperands, |
| 82339 | // GIR_Coverage, 905, |
| 82340 | GIR_EraseRootFromParent_Done, |
| 82341 | // Label 4474: @255565 |
| 82342 | GIM_Try, /*On fail goto*//*Label 4475*/ GIMT_Encode4(255598), // Rule ID 909 // |
| 82343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 82344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 82345 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 82346 | // (sra:{ *:[i64] } i64:{ *:[i64] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_ASHRREV_I64_e64:{ *:[i64] } i32:{ *:[i32] }:$src0, i64:{ *:[i64] }:$src1) |
| 82347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ASHRREV_I64_e64), |
| 82348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 82350 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 82351 | GIR_RootConstrainSelectedInstOperands, |
| 82352 | // GIR_Coverage, 909, |
| 82353 | GIR_EraseRootFromParent_Done, |
| 82354 | // Label 4475: @255598 |
| 82355 | GIM_Reject, |
| 82356 | // Label 4469: @255599 |
| 82357 | GIM_Reject, |
| 82358 | // Label 4454: @255600 |
| 82359 | GIM_Try, /*On fail goto*//*Label 4476*/ GIMT_Encode4(255768), |
| 82360 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 82361 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 82362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82363 | GIM_Try, /*On fail goto*//*Label 4477*/ GIMT_Encode4(255706), // Rule ID 977 // |
| 82364 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 82365 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_AND), |
| 82366 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 82367 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_v2s16, |
| 82368 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 82369 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_CONSTANT), |
| 82370 | // MIs[2] Operand 1 |
| 82371 | // No operand predicates |
| 82372 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_csh_mask_16), |
| 82373 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 82374 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82375 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82376 | // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (and:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (imm:{ *:[v2i16] }))<<P:Predicate_csh_mask_16>>) => (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 82377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16), |
| 82378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 82380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 82381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 82382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 82383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82388 | GIR_RootConstrainSelectedInstOperands, |
| 82389 | // GIR_Coverage, 977, |
| 82390 | GIR_EraseRootFromParent_Done, |
| 82391 | // Label 4477: @255706 |
| 82392 | GIM_Try, /*On fail goto*//*Label 4478*/ GIMT_Encode4(255767), // Rule ID 976 // |
| 82393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82394 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 82395 | // (sra:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_PK_ASHRREV_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 82396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ASHRREV_I16), |
| 82397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 82399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 82400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 82401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 82402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 82407 | GIR_RootConstrainSelectedInstOperands, |
| 82408 | // GIR_Coverage, 976, |
| 82409 | GIR_EraseRootFromParent_Done, |
| 82410 | // Label 4478: @255767 |
| 82411 | GIM_Reject, |
| 82412 | // Label 4476: @255768 |
| 82413 | GIM_Reject, |
| 82414 | // Label 4455: @255769 |
| 82415 | GIM_Reject, |
| 82416 | // Label 49: @255770 |
| 82417 | GIM_Try, /*On fail goto*//*Label 4479*/ GIMT_Encode4(255814), // Rule ID 879 // |
| 82418 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 82419 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 82420 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 82421 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 82422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 82424 | // (fshr:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_ALIGNBIT_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 82425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 82426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 82428 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 82429 | GIR_RootToRootCopy, /*OpIdx*/3, // src2 |
| 82430 | GIR_RootConstrainSelectedInstOperands, |
| 82431 | // GIR_Coverage, 879, |
| 82432 | GIR_EraseRootFromParent_Done, |
| 82433 | // Label 4479: @255814 |
| 82434 | GIM_Reject, |
| 82435 | // Label 50: @255815 |
| 82436 | GIM_Try, /*On fail goto*//*Label 4480*/ GIMT_Encode4(255846), // Rule ID 7091 // |
| 82437 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 82438 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 82439 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 82440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 82441 | // (rotr:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_ALIGNBIT_B32_e64:{ *:[i32] } ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src0, ?:{ *:[i32] }:$src1) |
| 82442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 82443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 82444 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82445 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 82446 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 82447 | GIR_RootConstrainSelectedInstOperands, |
| 82448 | // GIR_Coverage, 7091, |
| 82449 | GIR_EraseRootFromParent_Done, |
| 82450 | // Label 4480: @255846 |
| 82451 | GIM_Reject, |
| 82452 | // Label 51: @255847 |
| 82453 | GIM_Try, /*On fail goto*//*Label 4481*/ GIMT_Encode4(256868), |
| 82454 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 82455 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4485*/ GIMT_Encode4(256568), |
| 82456 | /*GILLT_s16*//*Label 4482*/ GIMT_Encode4(255878), |
| 82457 | /*GILLT_s32*//*Label 4483*/ GIMT_Encode4(256372), |
| 82458 | /*GILLT_s64*//*Label 4484*/ GIMT_Encode4(256470), |
| 82459 | // Label 4482: @255878 |
| 82460 | GIM_Try, /*On fail goto*//*Label 4486*/ GIMT_Encode4(256371), |
| 82461 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 82462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 82463 | GIM_Try, /*On fail goto*//*Label 4487*/ GIMT_Encode4(255914), // Rule ID 423 // |
| 82464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82465 | // MIs[0] Operand 1 |
| 82466 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 82467 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLT:{ *:[Other] }) => (V_CMP_LT_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_e64), |
| 82469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82470 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82471 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82472 | GIR_RootConstrainSelectedInstOperands, |
| 82473 | // GIR_Coverage, 423, |
| 82474 | GIR_EraseRootFromParent_Done, |
| 82475 | // Label 4487: @255914 |
| 82476 | GIM_Try, /*On fail goto*//*Label 4488*/ GIMT_Encode4(255938), // Rule ID 424 // |
| 82477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82478 | // MIs[0] Operand 1 |
| 82479 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 82480 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLT:{ *:[Other] }) => (V_CMP_LT_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I16_t16_e64), |
| 82482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82483 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82484 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82485 | GIR_RootConstrainSelectedInstOperands, |
| 82486 | // GIR_Coverage, 424, |
| 82487 | GIR_EraseRootFromParent_Done, |
| 82488 | // Label 4488: @255938 |
| 82489 | GIM_Try, /*On fail goto*//*Label 4489*/ GIMT_Encode4(255962), // Rule ID 427 // |
| 82490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82491 | // MIs[0] Operand 1 |
| 82492 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 82493 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLE:{ *:[Other] }) => (V_CMP_LE_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_e64), |
| 82495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82496 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82497 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82498 | GIR_RootConstrainSelectedInstOperands, |
| 82499 | // GIR_Coverage, 427, |
| 82500 | GIR_EraseRootFromParent_Done, |
| 82501 | // Label 4489: @255962 |
| 82502 | GIM_Try, /*On fail goto*//*Label 4490*/ GIMT_Encode4(255986), // Rule ID 428 // |
| 82503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82504 | // MIs[0] Operand 1 |
| 82505 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 82506 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETLE:{ *:[Other] }) => (V_CMP_LE_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I16_t16_e64), |
| 82508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82509 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82510 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82511 | GIR_RootConstrainSelectedInstOperands, |
| 82512 | // GIR_Coverage, 428, |
| 82513 | GIR_EraseRootFromParent_Done, |
| 82514 | // Label 4490: @255986 |
| 82515 | GIM_Try, /*On fail goto*//*Label 4491*/ GIMT_Encode4(256010), // Rule ID 429 // |
| 82516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82517 | // MIs[0] Operand 1 |
| 82518 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 82519 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGT:{ *:[Other] }) => (V_CMP_GT_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_e64), |
| 82521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82522 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82523 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82524 | GIR_RootConstrainSelectedInstOperands, |
| 82525 | // GIR_Coverage, 429, |
| 82526 | GIR_EraseRootFromParent_Done, |
| 82527 | // Label 4491: @256010 |
| 82528 | GIM_Try, /*On fail goto*//*Label 4492*/ GIMT_Encode4(256034), // Rule ID 430 // |
| 82529 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82530 | // MIs[0] Operand 1 |
| 82531 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 82532 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGT:{ *:[Other] }) => (V_CMP_GT_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I16_t16_e64), |
| 82534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82535 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82536 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82537 | GIR_RootConstrainSelectedInstOperands, |
| 82538 | // GIR_Coverage, 430, |
| 82539 | GIR_EraseRootFromParent_Done, |
| 82540 | // Label 4492: @256034 |
| 82541 | GIM_Try, /*On fail goto*//*Label 4493*/ GIMT_Encode4(256058), // Rule ID 433 // |
| 82542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82543 | // MIs[0] Operand 1 |
| 82544 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 82545 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGE:{ *:[Other] }) => (V_CMP_GE_I16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_e64), |
| 82547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82548 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82549 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82550 | GIR_RootConstrainSelectedInstOperands, |
| 82551 | // GIR_Coverage, 433, |
| 82552 | GIR_EraseRootFromParent_Done, |
| 82553 | // Label 4493: @256058 |
| 82554 | GIM_Try, /*On fail goto*//*Label 4494*/ GIMT_Encode4(256082), // Rule ID 434 // |
| 82555 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82556 | // MIs[0] Operand 1 |
| 82557 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 82558 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETGE:{ *:[Other] }) => (V_CMP_GE_I16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I16_t16_e64), |
| 82560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82561 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82562 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82563 | GIR_RootConstrainSelectedInstOperands, |
| 82564 | // GIR_Coverage, 434, |
| 82565 | GIR_EraseRootFromParent_Done, |
| 82566 | // Label 4494: @256082 |
| 82567 | GIM_Try, /*On fail goto*//*Label 4495*/ GIMT_Encode4(256106), // Rule ID 439 // |
| 82568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82569 | // MIs[0] Operand 1 |
| 82570 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 82571 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULT:{ *:[Other] }) => (V_CMP_LT_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_e64), |
| 82573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82574 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82575 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82576 | GIR_RootConstrainSelectedInstOperands, |
| 82577 | // GIR_Coverage, 439, |
| 82578 | GIR_EraseRootFromParent_Done, |
| 82579 | // Label 4495: @256106 |
| 82580 | GIM_Try, /*On fail goto*//*Label 4496*/ GIMT_Encode4(256130), // Rule ID 440 // |
| 82581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82582 | // MIs[0] Operand 1 |
| 82583 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 82584 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULT:{ *:[Other] }) => (V_CMP_LT_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U16_t16_e64), |
| 82586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82587 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82588 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82589 | GIR_RootConstrainSelectedInstOperands, |
| 82590 | // GIR_Coverage, 440, |
| 82591 | GIR_EraseRootFromParent_Done, |
| 82592 | // Label 4496: @256130 |
| 82593 | GIM_Try, /*On fail goto*//*Label 4497*/ GIMT_Encode4(256154), // Rule ID 441 // |
| 82594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82595 | // MIs[0] Operand 1 |
| 82596 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 82597 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETEQ:{ *:[Other] }) => (V_CMP_EQ_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_e64), |
| 82599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82600 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82601 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82602 | GIR_RootConstrainSelectedInstOperands, |
| 82603 | // GIR_Coverage, 441, |
| 82604 | GIR_EraseRootFromParent_Done, |
| 82605 | // Label 4497: @256154 |
| 82606 | GIM_Try, /*On fail goto*//*Label 4498*/ GIMT_Encode4(256178), // Rule ID 443 // |
| 82607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82608 | // MIs[0] Operand 1 |
| 82609 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 82610 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETEQ:{ *:[Other] }) => (V_CMP_EQ_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U16_t16_e64), |
| 82612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82613 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82614 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82615 | GIR_RootConstrainSelectedInstOperands, |
| 82616 | // GIR_Coverage, 443, |
| 82617 | GIR_EraseRootFromParent_Done, |
| 82618 | // Label 4498: @256178 |
| 82619 | GIM_Try, /*On fail goto*//*Label 4499*/ GIMT_Encode4(256202), // Rule ID 445 // |
| 82620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82621 | // MIs[0] Operand 1 |
| 82622 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 82623 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULE:{ *:[Other] }) => (V_CMP_LE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U16_e64), |
| 82625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82626 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82627 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82628 | GIR_RootConstrainSelectedInstOperands, |
| 82629 | // GIR_Coverage, 445, |
| 82630 | GIR_EraseRootFromParent_Done, |
| 82631 | // Label 4499: @256202 |
| 82632 | GIM_Try, /*On fail goto*//*Label 4500*/ GIMT_Encode4(256226), // Rule ID 446 // |
| 82633 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82634 | // MIs[0] Operand 1 |
| 82635 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 82636 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETULE:{ *:[Other] }) => (V_CMP_LE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U16_t16_e64), |
| 82638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82639 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82640 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82641 | GIR_RootConstrainSelectedInstOperands, |
| 82642 | // GIR_Coverage, 446, |
| 82643 | GIR_EraseRootFromParent_Done, |
| 82644 | // Label 4500: @256226 |
| 82645 | GIM_Try, /*On fail goto*//*Label 4501*/ GIMT_Encode4(256250), // Rule ID 447 // |
| 82646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82647 | // MIs[0] Operand 1 |
| 82648 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 82649 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGT:{ *:[Other] }) => (V_CMP_GT_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U16_e64), |
| 82651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82652 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82653 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82654 | GIR_RootConstrainSelectedInstOperands, |
| 82655 | // GIR_Coverage, 447, |
| 82656 | GIR_EraseRootFromParent_Done, |
| 82657 | // Label 4501: @256250 |
| 82658 | GIM_Try, /*On fail goto*//*Label 4502*/ GIMT_Encode4(256274), // Rule ID 448 // |
| 82659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82660 | // MIs[0] Operand 1 |
| 82661 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 82662 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGT:{ *:[Other] }) => (V_CMP_GT_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U16_t16_e64), |
| 82664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82665 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82666 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82667 | GIR_RootConstrainSelectedInstOperands, |
| 82668 | // GIR_Coverage, 448, |
| 82669 | GIR_EraseRootFromParent_Done, |
| 82670 | // Label 4502: @256274 |
| 82671 | GIM_Try, /*On fail goto*//*Label 4503*/ GIMT_Encode4(256298), // Rule ID 449 // |
| 82672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82673 | // MIs[0] Operand 1 |
| 82674 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 82675 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETNE:{ *:[Other] }) => (V_CMP_NE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U16_e64), |
| 82677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82678 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82679 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82680 | GIR_RootConstrainSelectedInstOperands, |
| 82681 | // GIR_Coverage, 449, |
| 82682 | GIR_EraseRootFromParent_Done, |
| 82683 | // Label 4503: @256298 |
| 82684 | GIM_Try, /*On fail goto*//*Label 4504*/ GIMT_Encode4(256322), // Rule ID 451 // |
| 82685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82686 | // MIs[0] Operand 1 |
| 82687 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 82688 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETNE:{ *:[Other] }) => (V_CMP_NE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U16_t16_e64), |
| 82690 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82691 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82692 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82693 | GIR_RootConstrainSelectedInstOperands, |
| 82694 | // GIR_Coverage, 451, |
| 82695 | GIR_EraseRootFromParent_Done, |
| 82696 | // Label 4504: @256322 |
| 82697 | GIM_Try, /*On fail goto*//*Label 4505*/ GIMT_Encode4(256346), // Rule ID 453 // |
| 82698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 82699 | // MIs[0] Operand 1 |
| 82700 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 82701 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGE:{ *:[Other] }) => (V_CMP_GE_U16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U16_e64), |
| 82703 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82704 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82705 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82706 | GIR_RootConstrainSelectedInstOperands, |
| 82707 | // GIR_Coverage, 453, |
| 82708 | GIR_EraseRootFromParent_Done, |
| 82709 | // Label 4505: @256346 |
| 82710 | GIM_Try, /*On fail goto*//*Label 4506*/ GIMT_Encode4(256370), // Rule ID 454 // |
| 82711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 82712 | // MIs[0] Operand 1 |
| 82713 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 82714 | // (setcc:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1, SETUGE:{ *:[Other] }) => (V_CMP_GE_U16_t16_e64:{ *:[i1] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 82715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U16_t16_e64), |
| 82716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82717 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82718 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82719 | GIR_RootConstrainSelectedInstOperands, |
| 82720 | // GIR_Coverage, 454, |
| 82721 | GIR_EraseRootFromParent_Done, |
| 82722 | // Label 4506: @256370 |
| 82723 | GIM_Reject, |
| 82724 | // Label 4486: @256371 |
| 82725 | GIM_Reject, |
| 82726 | // Label 4483: @256372 |
| 82727 | GIM_Try, /*On fail goto*//*Label 4507*/ GIMT_Encode4(256469), |
| 82728 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 82729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 82730 | GIM_Try, /*On fail goto*//*Label 4508*/ GIMT_Encode4(256405), // Rule ID 490 // |
| 82731 | // MIs[0] Operand 1 |
| 82732 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 82733 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETLT:{ *:[Other] }) => (V_CMP_LT_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I32_e64), |
| 82735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82736 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82737 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82738 | GIR_RootConstrainSelectedInstOperands, |
| 82739 | // GIR_Coverage, 490, |
| 82740 | GIR_EraseRootFromParent_Done, |
| 82741 | // Label 4508: @256405 |
| 82742 | GIM_Try, /*On fail goto*//*Label 4509*/ GIMT_Encode4(256426), // Rule ID 492 // |
| 82743 | // MIs[0] Operand 1 |
| 82744 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 82745 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETLE:{ *:[Other] }) => (V_CMP_LE_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I32_e64), |
| 82747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82748 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82749 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82750 | GIR_RootConstrainSelectedInstOperands, |
| 82751 | // GIR_Coverage, 492, |
| 82752 | GIR_EraseRootFromParent_Done, |
| 82753 | // Label 4509: @256426 |
| 82754 | GIM_Try, /*On fail goto*//*Label 4510*/ GIMT_Encode4(256447), // Rule ID 493 // |
| 82755 | // MIs[0] Operand 1 |
| 82756 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 82757 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETGT:{ *:[Other] }) => (V_CMP_GT_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I32_e64), |
| 82759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82760 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82761 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82762 | GIR_RootConstrainSelectedInstOperands, |
| 82763 | // GIR_Coverage, 493, |
| 82764 | GIR_EraseRootFromParent_Done, |
| 82765 | // Label 4510: @256447 |
| 82766 | GIM_Try, /*On fail goto*//*Label 4511*/ GIMT_Encode4(256468), // Rule ID 495 // |
| 82767 | // MIs[0] Operand 1 |
| 82768 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 82769 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETGE:{ *:[Other] }) => (V_CMP_GE_I32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I32_e64), |
| 82771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82772 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82773 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82774 | GIR_RootConstrainSelectedInstOperands, |
| 82775 | // GIR_Coverage, 495, |
| 82776 | GIR_EraseRootFromParent_Done, |
| 82777 | // Label 4511: @256468 |
| 82778 | GIM_Reject, |
| 82779 | // Label 4507: @256469 |
| 82780 | GIM_Reject, |
| 82781 | // Label 4484: @256470 |
| 82782 | GIM_Try, /*On fail goto*//*Label 4512*/ GIMT_Encode4(256567), |
| 82783 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 82784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 82785 | GIM_Try, /*On fail goto*//*Label 4513*/ GIMT_Encode4(256503), // Rule ID 506 // |
| 82786 | // MIs[0] Operand 1 |
| 82787 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLT), |
| 82788 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETLT:{ *:[Other] }) => (V_CMP_LT_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_I64_e64), |
| 82790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82791 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82792 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82793 | GIR_RootConstrainSelectedInstOperands, |
| 82794 | // GIR_Coverage, 506, |
| 82795 | GIR_EraseRootFromParent_Done, |
| 82796 | // Label 4513: @256503 |
| 82797 | GIM_Try, /*On fail goto*//*Label 4514*/ GIMT_Encode4(256524), // Rule ID 508 // |
| 82798 | // MIs[0] Operand 1 |
| 82799 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SLE), |
| 82800 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETLE:{ *:[Other] }) => (V_CMP_LE_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_I64_e64), |
| 82802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82803 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82804 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82805 | GIR_RootConstrainSelectedInstOperands, |
| 82806 | // GIR_Coverage, 508, |
| 82807 | GIR_EraseRootFromParent_Done, |
| 82808 | // Label 4514: @256524 |
| 82809 | GIM_Try, /*On fail goto*//*Label 4515*/ GIMT_Encode4(256545), // Rule ID 509 // |
| 82810 | // MIs[0] Operand 1 |
| 82811 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGT), |
| 82812 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETGT:{ *:[Other] }) => (V_CMP_GT_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_I64_e64), |
| 82814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82815 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82816 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82817 | GIR_RootConstrainSelectedInstOperands, |
| 82818 | // GIR_Coverage, 509, |
| 82819 | GIR_EraseRootFromParent_Done, |
| 82820 | // Label 4515: @256545 |
| 82821 | GIM_Try, /*On fail goto*//*Label 4516*/ GIMT_Encode4(256566), // Rule ID 511 // |
| 82822 | // MIs[0] Operand 1 |
| 82823 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_SGE), |
| 82824 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETGE:{ *:[Other] }) => (V_CMP_GE_I64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_I64_e64), |
| 82826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82827 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82828 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82829 | GIR_RootConstrainSelectedInstOperands, |
| 82830 | // GIR_Coverage, 511, |
| 82831 | GIR_EraseRootFromParent_Done, |
| 82832 | // Label 4516: @256566 |
| 82833 | GIM_Reject, |
| 82834 | // Label 4512: @256567 |
| 82835 | GIM_Reject, |
| 82836 | // Label 4485: @256568 |
| 82837 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 4519*/ GIMT_Encode4(256867), |
| 82838 | /*GILLT_s32*//*Label 4517*/ GIMT_Encode4(256587), |
| 82839 | /*GILLT_s64*//*Label 4518*/ GIMT_Encode4(256727), |
| 82840 | // Label 4517: @256587 |
| 82841 | GIM_Try, /*On fail goto*//*Label 4520*/ GIMT_Encode4(256726), |
| 82842 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 82843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 82844 | GIM_Try, /*On fail goto*//*Label 4521*/ GIMT_Encode4(256620), // Rule ID 522 // |
| 82845 | // MIs[0] Operand 1 |
| 82846 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 82847 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETULT:{ *:[Other] }) => (V_CMP_LT_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U32_e64), |
| 82849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82850 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82851 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82852 | GIR_RootConstrainSelectedInstOperands, |
| 82853 | // GIR_Coverage, 522, |
| 82854 | GIR_EraseRootFromParent_Done, |
| 82855 | // Label 4521: @256620 |
| 82856 | GIM_Try, /*On fail goto*//*Label 4522*/ GIMT_Encode4(256641), // Rule ID 523 // |
| 82857 | // MIs[0] Operand 1 |
| 82858 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 82859 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETEQ:{ *:[Other] }) => (V_CMP_EQ_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U32_e64), |
| 82861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82862 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82863 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82864 | GIR_RootConstrainSelectedInstOperands, |
| 82865 | // GIR_Coverage, 523, |
| 82866 | GIR_EraseRootFromParent_Done, |
| 82867 | // Label 4522: @256641 |
| 82868 | GIM_Try, /*On fail goto*//*Label 4523*/ GIMT_Encode4(256662), // Rule ID 525 // |
| 82869 | // MIs[0] Operand 1 |
| 82870 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 82871 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETULE:{ *:[Other] }) => (V_CMP_LE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U32_e64), |
| 82873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82874 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82875 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82876 | GIR_RootConstrainSelectedInstOperands, |
| 82877 | // GIR_Coverage, 525, |
| 82878 | GIR_EraseRootFromParent_Done, |
| 82879 | // Label 4523: @256662 |
| 82880 | GIM_Try, /*On fail goto*//*Label 4524*/ GIMT_Encode4(256683), // Rule ID 526 // |
| 82881 | // MIs[0] Operand 1 |
| 82882 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 82883 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGT:{ *:[Other] }) => (V_CMP_GT_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U32_e64), |
| 82885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82886 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82887 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82888 | GIR_RootConstrainSelectedInstOperands, |
| 82889 | // GIR_Coverage, 526, |
| 82890 | GIR_EraseRootFromParent_Done, |
| 82891 | // Label 4524: @256683 |
| 82892 | GIM_Try, /*On fail goto*//*Label 4525*/ GIMT_Encode4(256704), // Rule ID 527 // |
| 82893 | // MIs[0] Operand 1 |
| 82894 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 82895 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETNE:{ *:[Other] }) => (V_CMP_NE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U32_e64), |
| 82897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82898 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82899 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82900 | GIR_RootConstrainSelectedInstOperands, |
| 82901 | // GIR_Coverage, 527, |
| 82902 | GIR_EraseRootFromParent_Done, |
| 82903 | // Label 4525: @256704 |
| 82904 | GIM_Try, /*On fail goto*//*Label 4526*/ GIMT_Encode4(256725), // Rule ID 529 // |
| 82905 | // MIs[0] Operand 1 |
| 82906 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 82907 | // (setcc:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, SETUGE:{ *:[Other] }) => (V_CMP_GE_U32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 82908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U32_e64), |
| 82909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82910 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82911 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82912 | GIR_RootConstrainSelectedInstOperands, |
| 82913 | // GIR_Coverage, 529, |
| 82914 | GIR_EraseRootFromParent_Done, |
| 82915 | // Label 4526: @256725 |
| 82916 | GIM_Reject, |
| 82917 | // Label 4520: @256726 |
| 82918 | GIM_Reject, |
| 82919 | // Label 4518: @256727 |
| 82920 | GIM_Try, /*On fail goto*//*Label 4527*/ GIMT_Encode4(256866), |
| 82921 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 82922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 82923 | GIM_Try, /*On fail goto*//*Label 4528*/ GIMT_Encode4(256760), // Rule ID 540 // |
| 82924 | // MIs[0] Operand 1 |
| 82925 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULT), |
| 82926 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETULT:{ *:[Other] }) => (V_CMP_LT_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_U64_e64), |
| 82928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82929 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82930 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82931 | GIR_RootConstrainSelectedInstOperands, |
| 82932 | // GIR_Coverage, 540, |
| 82933 | GIR_EraseRootFromParent_Done, |
| 82934 | // Label 4528: @256760 |
| 82935 | GIM_Try, /*On fail goto*//*Label 4529*/ GIMT_Encode4(256781), // Rule ID 541 // |
| 82936 | // MIs[0] Operand 1 |
| 82937 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_EQ), |
| 82938 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETEQ:{ *:[Other] }) => (V_CMP_EQ_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_U64_e64), |
| 82940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82941 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82942 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82943 | GIR_RootConstrainSelectedInstOperands, |
| 82944 | // GIR_Coverage, 541, |
| 82945 | GIR_EraseRootFromParent_Done, |
| 82946 | // Label 4529: @256781 |
| 82947 | GIM_Try, /*On fail goto*//*Label 4530*/ GIMT_Encode4(256802), // Rule ID 543 // |
| 82948 | // MIs[0] Operand 1 |
| 82949 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_ULE), |
| 82950 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETULE:{ *:[Other] }) => (V_CMP_LE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_U64_e64), |
| 82952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82953 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82954 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82955 | GIR_RootConstrainSelectedInstOperands, |
| 82956 | // GIR_Coverage, 543, |
| 82957 | GIR_EraseRootFromParent_Done, |
| 82958 | // Label 4530: @256802 |
| 82959 | GIM_Try, /*On fail goto*//*Label 4531*/ GIMT_Encode4(256823), // Rule ID 544 // |
| 82960 | // MIs[0] Operand 1 |
| 82961 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGT), |
| 82962 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETUGT:{ *:[Other] }) => (V_CMP_GT_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_U64_e64), |
| 82964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82965 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82966 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82967 | GIR_RootConstrainSelectedInstOperands, |
| 82968 | // GIR_Coverage, 544, |
| 82969 | GIR_EraseRootFromParent_Done, |
| 82970 | // Label 4531: @256823 |
| 82971 | GIM_Try, /*On fail goto*//*Label 4532*/ GIMT_Encode4(256844), // Rule ID 545 // |
| 82972 | // MIs[0] Operand 1 |
| 82973 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_NE), |
| 82974 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETNE:{ *:[Other] }) => (V_CMP_NE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NE_U64_e64), |
| 82976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82977 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82978 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82979 | GIR_RootConstrainSelectedInstOperands, |
| 82980 | // GIR_Coverage, 545, |
| 82981 | GIR_EraseRootFromParent_Done, |
| 82982 | // Label 4532: @256844 |
| 82983 | GIM_Try, /*On fail goto*//*Label 4533*/ GIMT_Encode4(256865), // Rule ID 547 // |
| 82984 | // MIs[0] Operand 1 |
| 82985 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::ICMP_UGE), |
| 82986 | // (setcc:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1, SETUGE:{ *:[Other] }) => (V_CMP_GE_U64_e64:{ *:[i1] } i64:{ *:[i64] }:$src0, i64:{ *:[i64] }:$src1) |
| 82987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_U64_e64), |
| 82988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 82989 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 82990 | GIR_RootToRootCopy, /*OpIdx*/3, // src1 |
| 82991 | GIR_RootConstrainSelectedInstOperands, |
| 82992 | // GIR_Coverage, 547, |
| 82993 | GIR_EraseRootFromParent_Done, |
| 82994 | // Label 4533: @256865 |
| 82995 | GIM_Reject, |
| 82996 | // Label 4527: @256866 |
| 82997 | GIM_Reject, |
| 82998 | // Label 4519: @256867 |
| 82999 | GIM_Reject, |
| 83000 | // Label 4481: @256868 |
| 83001 | GIM_Reject, |
| 83002 | // Label 52: @256869 |
| 83003 | GIM_Try, /*On fail goto*//*Label 4534*/ GIMT_Encode4(260163), |
| 83004 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 83005 | GIM_SwitchType, /*MI*/0, /*Op*/2, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4538*/ GIMT_Encode4(260162), |
| 83006 | /*GILLT_s16*//*Label 4535*/ GIMT_Encode4(256900), |
| 83007 | /*GILLT_s32*//*Label 4536*/ GIMT_Encode4(258566), |
| 83008 | /*GILLT_s64*//*Label 4537*/ GIMT_Encode4(259364), |
| 83009 | // Label 4535: @256900 |
| 83010 | GIM_Try, /*On fail goto*//*Label 4539*/ GIMT_Encode4(258565), |
| 83011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 83012 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 83013 | GIM_Try, /*On fail goto*//*Label 4540*/ GIMT_Encode4(256971), // Rule ID 347 // |
| 83014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83015 | // MIs[0] Operand 1 |
| 83016 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 83017 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83018 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83019 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] }) => (V_CMP_LT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F16_e64), |
| 83021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83027 | GIR_RootConstrainSelectedInstOperands, |
| 83028 | // GIR_Coverage, 347, |
| 83029 | GIR_EraseRootFromParent_Done, |
| 83030 | // Label 4540: @256971 |
| 83031 | GIM_Try, /*On fail goto*//*Label 4541*/ GIMT_Encode4(257030), // Rule ID 349 // |
| 83032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83033 | // MIs[0] Operand 1 |
| 83034 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 83035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83036 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83037 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] }) => (V_CMP_LT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F16_t16_e64), |
| 83039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83045 | GIR_RootConstrainSelectedInstOperands, |
| 83046 | // GIR_Coverage, 349, |
| 83047 | GIR_EraseRootFromParent_Done, |
| 83048 | // Label 4541: @257030 |
| 83049 | GIM_Try, /*On fail goto*//*Label 4542*/ GIMT_Encode4(257089), // Rule ID 351 // |
| 83050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83051 | // MIs[0] Operand 1 |
| 83052 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 83053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83054 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83055 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] }) => (V_CMP_EQ_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64), |
| 83057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83063 | GIR_RootConstrainSelectedInstOperands, |
| 83064 | // GIR_Coverage, 351, |
| 83065 | GIR_EraseRootFromParent_Done, |
| 83066 | // Label 4542: @257089 |
| 83067 | GIM_Try, /*On fail goto*//*Label 4543*/ GIMT_Encode4(257148), // Rule ID 353 // |
| 83068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83069 | // MIs[0] Operand 1 |
| 83070 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 83071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83073 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] }) => (V_CMP_EQ_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64), |
| 83075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83081 | GIR_RootConstrainSelectedInstOperands, |
| 83082 | // GIR_Coverage, 353, |
| 83083 | GIR_EraseRootFromParent_Done, |
| 83084 | // Label 4543: @257148 |
| 83085 | GIM_Try, /*On fail goto*//*Label 4544*/ GIMT_Encode4(257207), // Rule ID 355 // |
| 83086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83087 | // MIs[0] Operand 1 |
| 83088 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 83089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83091 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] }) => (V_CMP_LE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F16_e64), |
| 83093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83099 | GIR_RootConstrainSelectedInstOperands, |
| 83100 | // GIR_Coverage, 355, |
| 83101 | GIR_EraseRootFromParent_Done, |
| 83102 | // Label 4544: @257207 |
| 83103 | GIM_Try, /*On fail goto*//*Label 4545*/ GIMT_Encode4(257266), // Rule ID 357 // |
| 83104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83105 | // MIs[0] Operand 1 |
| 83106 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 83107 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83109 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] }) => (V_CMP_LE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F16_t16_e64), |
| 83111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83117 | GIR_RootConstrainSelectedInstOperands, |
| 83118 | // GIR_Coverage, 357, |
| 83119 | GIR_EraseRootFromParent_Done, |
| 83120 | // Label 4545: @257266 |
| 83121 | GIM_Try, /*On fail goto*//*Label 4546*/ GIMT_Encode4(257325), // Rule ID 359 // |
| 83122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83123 | // MIs[0] Operand 1 |
| 83124 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 83125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83127 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] }) => (V_CMP_GT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F16_e64), |
| 83129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83135 | GIR_RootConstrainSelectedInstOperands, |
| 83136 | // GIR_Coverage, 359, |
| 83137 | GIR_EraseRootFromParent_Done, |
| 83138 | // Label 4546: @257325 |
| 83139 | GIM_Try, /*On fail goto*//*Label 4547*/ GIMT_Encode4(257384), // Rule ID 361 // |
| 83140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83141 | // MIs[0] Operand 1 |
| 83142 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 83143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83145 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] }) => (V_CMP_GT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F16_t16_e64), |
| 83147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83153 | GIR_RootConstrainSelectedInstOperands, |
| 83154 | // GIR_Coverage, 361, |
| 83155 | GIR_EraseRootFromParent_Done, |
| 83156 | // Label 4547: @257384 |
| 83157 | GIM_Try, /*On fail goto*//*Label 4548*/ GIMT_Encode4(257443), // Rule ID 363 // |
| 83158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83159 | // MIs[0] Operand 1 |
| 83160 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE), |
| 83161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83163 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] }) => (V_CMP_LG_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F16_e64), |
| 83165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83171 | GIR_RootConstrainSelectedInstOperands, |
| 83172 | // GIR_Coverage, 363, |
| 83173 | GIR_EraseRootFromParent_Done, |
| 83174 | // Label 4548: @257443 |
| 83175 | GIM_Try, /*On fail goto*//*Label 4549*/ GIMT_Encode4(257502), // Rule ID 365 // |
| 83176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83177 | // MIs[0] Operand 1 |
| 83178 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE), |
| 83179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83181 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] }) => (V_CMP_LG_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F16_t16_e64), |
| 83183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83189 | GIR_RootConstrainSelectedInstOperands, |
| 83190 | // GIR_Coverage, 365, |
| 83191 | GIR_EraseRootFromParent_Done, |
| 83192 | // Label 4549: @257502 |
| 83193 | GIM_Try, /*On fail goto*//*Label 4550*/ GIMT_Encode4(257561), // Rule ID 367 // |
| 83194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83195 | // MIs[0] Operand 1 |
| 83196 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE), |
| 83197 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83199 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] }) => (V_CMP_GE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F16_e64), |
| 83201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83207 | GIR_RootConstrainSelectedInstOperands, |
| 83208 | // GIR_Coverage, 367, |
| 83209 | GIR_EraseRootFromParent_Done, |
| 83210 | // Label 4550: @257561 |
| 83211 | GIM_Try, /*On fail goto*//*Label 4551*/ GIMT_Encode4(257620), // Rule ID 369 // |
| 83212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83213 | // MIs[0] Operand 1 |
| 83214 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE), |
| 83215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83217 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] }) => (V_CMP_GE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F16_t16_e64), |
| 83219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83225 | GIR_RootConstrainSelectedInstOperands, |
| 83226 | // GIR_Coverage, 369, |
| 83227 | GIR_EraseRootFromParent_Done, |
| 83228 | // Label 4551: @257620 |
| 83229 | GIM_Try, /*On fail goto*//*Label 4552*/ GIMT_Encode4(257679), // Rule ID 371 // |
| 83230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83231 | // MIs[0] Operand 1 |
| 83232 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 83233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83235 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] }) => (V_CMP_O_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F16_e64), |
| 83237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83243 | GIR_RootConstrainSelectedInstOperands, |
| 83244 | // GIR_Coverage, 371, |
| 83245 | GIR_EraseRootFromParent_Done, |
| 83246 | // Label 4552: @257679 |
| 83247 | GIM_Try, /*On fail goto*//*Label 4553*/ GIMT_Encode4(257738), // Rule ID 372 // |
| 83248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83249 | // MIs[0] Operand 1 |
| 83250 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 83251 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83253 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] }) => (V_CMP_O_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F16_t16_e64), |
| 83255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83261 | GIR_RootConstrainSelectedInstOperands, |
| 83262 | // GIR_Coverage, 372, |
| 83263 | GIR_EraseRootFromParent_Done, |
| 83264 | // Label 4553: @257738 |
| 83265 | GIM_Try, /*On fail goto*//*Label 4554*/ GIMT_Encode4(257797), // Rule ID 373 // |
| 83266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83267 | // MIs[0] Operand 1 |
| 83268 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 83269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83271 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] }) => (V_CMP_U_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F16_e64), |
| 83273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83279 | GIR_RootConstrainSelectedInstOperands, |
| 83280 | // GIR_Coverage, 373, |
| 83281 | GIR_EraseRootFromParent_Done, |
| 83282 | // Label 4554: @257797 |
| 83283 | GIM_Try, /*On fail goto*//*Label 4555*/ GIMT_Encode4(257856), // Rule ID 374 // |
| 83284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83285 | // MIs[0] Operand 1 |
| 83286 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 83287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83289 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] }) => (V_CMP_U_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F16_t16_e64), |
| 83291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83297 | GIR_RootConstrainSelectedInstOperands, |
| 83298 | // GIR_Coverage, 374, |
| 83299 | GIR_EraseRootFromParent_Done, |
| 83300 | // Label 4555: @257856 |
| 83301 | GIM_Try, /*On fail goto*//*Label 4556*/ GIMT_Encode4(257915), // Rule ID 375 // |
| 83302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83303 | // MIs[0] Operand 1 |
| 83304 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT), |
| 83305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83307 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] }) => (V_CMP_NGE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F16_e64), |
| 83309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83315 | GIR_RootConstrainSelectedInstOperands, |
| 83316 | // GIR_Coverage, 375, |
| 83317 | GIR_EraseRootFromParent_Done, |
| 83318 | // Label 4556: @257915 |
| 83319 | GIM_Try, /*On fail goto*//*Label 4557*/ GIMT_Encode4(257974), // Rule ID 376 // |
| 83320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83321 | // MIs[0] Operand 1 |
| 83322 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT), |
| 83323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83325 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] }) => (V_CMP_NGE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F16_t16_e64), |
| 83327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83333 | GIR_RootConstrainSelectedInstOperands, |
| 83334 | // GIR_Coverage, 376, |
| 83335 | GIR_EraseRootFromParent_Done, |
| 83336 | // Label 4557: @257974 |
| 83337 | GIM_Try, /*On fail goto*//*Label 4558*/ GIMT_Encode4(258033), // Rule ID 377 // |
| 83338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83339 | // MIs[0] Operand 1 |
| 83340 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ), |
| 83341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83343 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] }) => (V_CMP_NLG_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F16_e64), |
| 83345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83351 | GIR_RootConstrainSelectedInstOperands, |
| 83352 | // GIR_Coverage, 377, |
| 83353 | GIR_EraseRootFromParent_Done, |
| 83354 | // Label 4558: @258033 |
| 83355 | GIM_Try, /*On fail goto*//*Label 4559*/ GIMT_Encode4(258092), // Rule ID 378 // |
| 83356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83357 | // MIs[0] Operand 1 |
| 83358 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ), |
| 83359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83361 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] }) => (V_CMP_NLG_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F16_t16_e64), |
| 83363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83369 | GIR_RootConstrainSelectedInstOperands, |
| 83370 | // GIR_Coverage, 378, |
| 83371 | GIR_EraseRootFromParent_Done, |
| 83372 | // Label 4559: @258092 |
| 83373 | GIM_Try, /*On fail goto*//*Label 4560*/ GIMT_Encode4(258151), // Rule ID 379 // |
| 83374 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83375 | // MIs[0] Operand 1 |
| 83376 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 83377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83378 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83379 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] }) => (V_CMP_NGT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83380 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F16_e64), |
| 83381 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83387 | GIR_RootConstrainSelectedInstOperands, |
| 83388 | // GIR_Coverage, 379, |
| 83389 | GIR_EraseRootFromParent_Done, |
| 83390 | // Label 4560: @258151 |
| 83391 | GIM_Try, /*On fail goto*//*Label 4561*/ GIMT_Encode4(258210), // Rule ID 380 // |
| 83392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83393 | // MIs[0] Operand 1 |
| 83394 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 83395 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83397 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] }) => (V_CMP_NGT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F16_t16_e64), |
| 83399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83405 | GIR_RootConstrainSelectedInstOperands, |
| 83406 | // GIR_Coverage, 380, |
| 83407 | GIR_EraseRootFromParent_Done, |
| 83408 | // Label 4561: @258210 |
| 83409 | GIM_Try, /*On fail goto*//*Label 4562*/ GIMT_Encode4(258269), // Rule ID 381 // |
| 83410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83411 | // MIs[0] Operand 1 |
| 83412 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT), |
| 83413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83415 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] }) => (V_CMP_NLE_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F16_e64), |
| 83417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83423 | GIR_RootConstrainSelectedInstOperands, |
| 83424 | // GIR_Coverage, 381, |
| 83425 | GIR_EraseRootFromParent_Done, |
| 83426 | // Label 4562: @258269 |
| 83427 | GIM_Try, /*On fail goto*//*Label 4563*/ GIMT_Encode4(258328), // Rule ID 382 // |
| 83428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83429 | // MIs[0] Operand 1 |
| 83430 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT), |
| 83431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83433 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] }) => (V_CMP_NLE_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F16_t16_e64), |
| 83435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83441 | GIR_RootConstrainSelectedInstOperands, |
| 83442 | // GIR_Coverage, 382, |
| 83443 | GIR_EraseRootFromParent_Done, |
| 83444 | // Label 4563: @258328 |
| 83445 | GIM_Try, /*On fail goto*//*Label 4564*/ GIMT_Encode4(258387), // Rule ID 383 // |
| 83446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83447 | // MIs[0] Operand 1 |
| 83448 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 83449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83450 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83451 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] }) => (V_CMP_NEQ_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F16_e64), |
| 83453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83459 | GIR_RootConstrainSelectedInstOperands, |
| 83460 | // GIR_Coverage, 383, |
| 83461 | GIR_EraseRootFromParent_Done, |
| 83462 | // Label 4564: @258387 |
| 83463 | GIM_Try, /*On fail goto*//*Label 4565*/ GIMT_Encode4(258446), // Rule ID 384 // |
| 83464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83465 | // MIs[0] Operand 1 |
| 83466 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 83467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83468 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83469 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] }) => (V_CMP_NEQ_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F16_t16_e64), |
| 83471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83477 | GIR_RootConstrainSelectedInstOperands, |
| 83478 | // GIR_Coverage, 384, |
| 83479 | GIR_EraseRootFromParent_Done, |
| 83480 | // Label 4565: @258446 |
| 83481 | GIM_Try, /*On fail goto*//*Label 4566*/ GIMT_Encode4(258505), // Rule ID 385 // |
| 83482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 83483 | // MIs[0] Operand 1 |
| 83484 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 83485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83486 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83487 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] }) => (V_CMP_NLT_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F16_e64), |
| 83489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83495 | GIR_RootConstrainSelectedInstOperands, |
| 83496 | // GIR_Coverage, 385, |
| 83497 | GIR_EraseRootFromParent_Done, |
| 83498 | // Label 4566: @258505 |
| 83499 | GIM_Try, /*On fail goto*//*Label 4567*/ GIMT_Encode4(258564), // Rule ID 386 // |
| 83500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasTrue16BitInsts), |
| 83501 | // MIs[0] Operand 1 |
| 83502 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 83503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83504 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83505 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] }) => (V_CMP_NLT_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F16_t16_e64), |
| 83507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83513 | GIR_RootConstrainSelectedInstOperands, |
| 83514 | // GIR_Coverage, 386, |
| 83515 | GIR_EraseRootFromParent_Done, |
| 83516 | // Label 4567: @258564 |
| 83517 | GIM_Reject, |
| 83518 | // Label 4539: @258565 |
| 83519 | GIM_Reject, |
| 83520 | // Label 4536: @258566 |
| 83521 | GIM_Try, /*On fail goto*//*Label 4568*/ GIMT_Encode4(259363), |
| 83522 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 83523 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 83524 | GIM_Try, /*On fail goto*//*Label 4569*/ GIMT_Encode4(258634), // Rule ID 206 // |
| 83525 | // MIs[0] Operand 1 |
| 83526 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 83527 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83529 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] }) => (V_CMP_LT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F32_e64), |
| 83531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83537 | GIR_RootConstrainSelectedInstOperands, |
| 83538 | // GIR_Coverage, 206, |
| 83539 | GIR_EraseRootFromParent_Done, |
| 83540 | // Label 4569: @258634 |
| 83541 | GIM_Try, /*On fail goto*//*Label 4570*/ GIMT_Encode4(258690), // Rule ID 208 // |
| 83542 | // MIs[0] Operand 1 |
| 83543 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 83544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83546 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] }) => (V_CMP_EQ_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64), |
| 83548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83554 | GIR_RootConstrainSelectedInstOperands, |
| 83555 | // GIR_Coverage, 208, |
| 83556 | GIR_EraseRootFromParent_Done, |
| 83557 | // Label 4570: @258690 |
| 83558 | GIM_Try, /*On fail goto*//*Label 4571*/ GIMT_Encode4(258746), // Rule ID 210 // |
| 83559 | // MIs[0] Operand 1 |
| 83560 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 83561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83563 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] }) => (V_CMP_LE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F32_e64), |
| 83565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83571 | GIR_RootConstrainSelectedInstOperands, |
| 83572 | // GIR_Coverage, 210, |
| 83573 | GIR_EraseRootFromParent_Done, |
| 83574 | // Label 4571: @258746 |
| 83575 | GIM_Try, /*On fail goto*//*Label 4572*/ GIMT_Encode4(258802), // Rule ID 212 // |
| 83576 | // MIs[0] Operand 1 |
| 83577 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 83578 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83580 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] }) => (V_CMP_GT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F32_e64), |
| 83582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83588 | GIR_RootConstrainSelectedInstOperands, |
| 83589 | // GIR_Coverage, 212, |
| 83590 | GIR_EraseRootFromParent_Done, |
| 83591 | // Label 4572: @258802 |
| 83592 | GIM_Try, /*On fail goto*//*Label 4573*/ GIMT_Encode4(258858), // Rule ID 214 // |
| 83593 | // MIs[0] Operand 1 |
| 83594 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE), |
| 83595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83597 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] }) => (V_CMP_LG_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F32_e64), |
| 83599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83605 | GIR_RootConstrainSelectedInstOperands, |
| 83606 | // GIR_Coverage, 214, |
| 83607 | GIR_EraseRootFromParent_Done, |
| 83608 | // Label 4573: @258858 |
| 83609 | GIM_Try, /*On fail goto*//*Label 4574*/ GIMT_Encode4(258914), // Rule ID 216 // |
| 83610 | // MIs[0] Operand 1 |
| 83611 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE), |
| 83612 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83614 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] }) => (V_CMP_GE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F32_e64), |
| 83616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83622 | GIR_RootConstrainSelectedInstOperands, |
| 83623 | // GIR_Coverage, 216, |
| 83624 | GIR_EraseRootFromParent_Done, |
| 83625 | // Label 4574: @258914 |
| 83626 | GIM_Try, /*On fail goto*//*Label 4575*/ GIMT_Encode4(258970), // Rule ID 218 // |
| 83627 | // MIs[0] Operand 1 |
| 83628 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 83629 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83631 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] }) => (V_CMP_O_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F32_e64), |
| 83633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83639 | GIR_RootConstrainSelectedInstOperands, |
| 83640 | // GIR_Coverage, 218, |
| 83641 | GIR_EraseRootFromParent_Done, |
| 83642 | // Label 4575: @258970 |
| 83643 | GIM_Try, /*On fail goto*//*Label 4576*/ GIMT_Encode4(259026), // Rule ID 219 // |
| 83644 | // MIs[0] Operand 1 |
| 83645 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 83646 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83647 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83648 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] }) => (V_CMP_U_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F32_e64), |
| 83650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83656 | GIR_RootConstrainSelectedInstOperands, |
| 83657 | // GIR_Coverage, 219, |
| 83658 | GIR_EraseRootFromParent_Done, |
| 83659 | // Label 4576: @259026 |
| 83660 | GIM_Try, /*On fail goto*//*Label 4577*/ GIMT_Encode4(259082), // Rule ID 220 // |
| 83661 | // MIs[0] Operand 1 |
| 83662 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT), |
| 83663 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83665 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] }) => (V_CMP_NGE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F32_e64), |
| 83667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83673 | GIR_RootConstrainSelectedInstOperands, |
| 83674 | // GIR_Coverage, 220, |
| 83675 | GIR_EraseRootFromParent_Done, |
| 83676 | // Label 4577: @259082 |
| 83677 | GIM_Try, /*On fail goto*//*Label 4578*/ GIMT_Encode4(259138), // Rule ID 221 // |
| 83678 | // MIs[0] Operand 1 |
| 83679 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ), |
| 83680 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83681 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83682 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] }) => (V_CMP_NLG_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F32_e64), |
| 83684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83690 | GIR_RootConstrainSelectedInstOperands, |
| 83691 | // GIR_Coverage, 221, |
| 83692 | GIR_EraseRootFromParent_Done, |
| 83693 | // Label 4578: @259138 |
| 83694 | GIM_Try, /*On fail goto*//*Label 4579*/ GIMT_Encode4(259194), // Rule ID 222 // |
| 83695 | // MIs[0] Operand 1 |
| 83696 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 83697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83698 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83699 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] }) => (V_CMP_NGT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F32_e64), |
| 83701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83707 | GIR_RootConstrainSelectedInstOperands, |
| 83708 | // GIR_Coverage, 222, |
| 83709 | GIR_EraseRootFromParent_Done, |
| 83710 | // Label 4579: @259194 |
| 83711 | GIM_Try, /*On fail goto*//*Label 4580*/ GIMT_Encode4(259250), // Rule ID 223 // |
| 83712 | // MIs[0] Operand 1 |
| 83713 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT), |
| 83714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83716 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] }) => (V_CMP_NLE_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F32_e64), |
| 83718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83724 | GIR_RootConstrainSelectedInstOperands, |
| 83725 | // GIR_Coverage, 223, |
| 83726 | GIR_EraseRootFromParent_Done, |
| 83727 | // Label 4580: @259250 |
| 83728 | GIM_Try, /*On fail goto*//*Label 4581*/ GIMT_Encode4(259306), // Rule ID 224 // |
| 83729 | // MIs[0] Operand 1 |
| 83730 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 83731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83732 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83733 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] }) => (V_CMP_NEQ_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F32_e64), |
| 83735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83741 | GIR_RootConstrainSelectedInstOperands, |
| 83742 | // GIR_Coverage, 224, |
| 83743 | GIR_EraseRootFromParent_Done, |
| 83744 | // Label 4581: @259306 |
| 83745 | GIM_Try, /*On fail goto*//*Label 4582*/ GIMT_Encode4(259362), // Rule ID 225 // |
| 83746 | // MIs[0] Operand 1 |
| 83747 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 83748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83750 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] }) => (V_CMP_NLT_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F32_e64), |
| 83752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83758 | GIR_RootConstrainSelectedInstOperands, |
| 83759 | // GIR_Coverage, 225, |
| 83760 | GIR_EraseRootFromParent_Done, |
| 83761 | // Label 4582: @259362 |
| 83762 | GIM_Reject, |
| 83763 | // Label 4568: @259363 |
| 83764 | GIM_Reject, |
| 83765 | // Label 4537: @259364 |
| 83766 | GIM_Try, /*On fail goto*//*Label 4583*/ GIMT_Encode4(260161), |
| 83767 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 83768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 83769 | GIM_Try, /*On fail goto*//*Label 4584*/ GIMT_Encode4(259432), // Rule ID 244 // |
| 83770 | // MIs[0] Operand 1 |
| 83771 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLT), |
| 83772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83774 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLT:{ *:[Other] }) => (V_CMP_LT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LT_F64_e64), |
| 83776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83782 | GIR_RootConstrainSelectedInstOperands, |
| 83783 | // GIR_Coverage, 244, |
| 83784 | GIR_EraseRootFromParent_Done, |
| 83785 | // Label 4584: @259432 |
| 83786 | GIM_Try, /*On fail goto*//*Label 4585*/ GIMT_Encode4(259488), // Rule ID 246 // |
| 83787 | // MIs[0] Operand 1 |
| 83788 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OEQ), |
| 83789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83791 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOEQ:{ *:[Other] }) => (V_CMP_EQ_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64), |
| 83793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83799 | GIR_RootConstrainSelectedInstOperands, |
| 83800 | // GIR_Coverage, 246, |
| 83801 | GIR_EraseRootFromParent_Done, |
| 83802 | // Label 4585: @259488 |
| 83803 | GIM_Try, /*On fail goto*//*Label 4586*/ GIMT_Encode4(259544), // Rule ID 248 // |
| 83804 | // MIs[0] Operand 1 |
| 83805 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OLE), |
| 83806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83808 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOLE:{ *:[Other] }) => (V_CMP_LE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LE_F64_e64), |
| 83810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83816 | GIR_RootConstrainSelectedInstOperands, |
| 83817 | // GIR_Coverage, 248, |
| 83818 | GIR_EraseRootFromParent_Done, |
| 83819 | // Label 4586: @259544 |
| 83820 | GIM_Try, /*On fail goto*//*Label 4587*/ GIMT_Encode4(259600), // Rule ID 250 // |
| 83821 | // MIs[0] Operand 1 |
| 83822 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGT), |
| 83823 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83825 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGT:{ *:[Other] }) => (V_CMP_GT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GT_F64_e64), |
| 83827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83833 | GIR_RootConstrainSelectedInstOperands, |
| 83834 | // GIR_Coverage, 250, |
| 83835 | GIR_EraseRootFromParent_Done, |
| 83836 | // Label 4587: @259600 |
| 83837 | GIM_Try, /*On fail goto*//*Label 4588*/ GIMT_Encode4(259656), // Rule ID 252 // |
| 83838 | // MIs[0] Operand 1 |
| 83839 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ONE), |
| 83840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83842 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETONE:{ *:[Other] }) => (V_CMP_LG_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_LG_F64_e64), |
| 83844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83850 | GIR_RootConstrainSelectedInstOperands, |
| 83851 | // GIR_Coverage, 252, |
| 83852 | GIR_EraseRootFromParent_Done, |
| 83853 | // Label 4588: @259656 |
| 83854 | GIM_Try, /*On fail goto*//*Label 4589*/ GIMT_Encode4(259712), // Rule ID 254 // |
| 83855 | // MIs[0] Operand 1 |
| 83856 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_OGE), |
| 83857 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83859 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETOGE:{ *:[Other] }) => (V_CMP_GE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_GE_F64_e64), |
| 83861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83867 | GIR_RootConstrainSelectedInstOperands, |
| 83868 | // GIR_Coverage, 254, |
| 83869 | GIR_EraseRootFromParent_Done, |
| 83870 | // Label 4589: @259712 |
| 83871 | GIM_Try, /*On fail goto*//*Label 4590*/ GIMT_Encode4(259768), // Rule ID 256 // |
| 83872 | // MIs[0] Operand 1 |
| 83873 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ORD), |
| 83874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83876 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETO:{ *:[Other] }) => (V_CMP_O_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_O_F64_e64), |
| 83878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83884 | GIR_RootConstrainSelectedInstOperands, |
| 83885 | // GIR_Coverage, 256, |
| 83886 | GIR_EraseRootFromParent_Done, |
| 83887 | // Label 4590: @259768 |
| 83888 | GIM_Try, /*On fail goto*//*Label 4591*/ GIMT_Encode4(259824), // Rule ID 257 // |
| 83889 | // MIs[0] Operand 1 |
| 83890 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNO), |
| 83891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83893 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUO:{ *:[Other] }) => (V_CMP_U_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_U_F64_e64), |
| 83895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83901 | GIR_RootConstrainSelectedInstOperands, |
| 83902 | // GIR_Coverage, 257, |
| 83903 | GIR_EraseRootFromParent_Done, |
| 83904 | // Label 4591: @259824 |
| 83905 | GIM_Try, /*On fail goto*//*Label 4592*/ GIMT_Encode4(259880), // Rule ID 258 // |
| 83906 | // MIs[0] Operand 1 |
| 83907 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULT), |
| 83908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83909 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83910 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULT:{ *:[Other] }) => (V_CMP_NGE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGE_F64_e64), |
| 83912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83918 | GIR_RootConstrainSelectedInstOperands, |
| 83919 | // GIR_Coverage, 258, |
| 83920 | GIR_EraseRootFromParent_Done, |
| 83921 | // Label 4592: @259880 |
| 83922 | GIM_Try, /*On fail goto*//*Label 4593*/ GIMT_Encode4(259936), // Rule ID 259 // |
| 83923 | // MIs[0] Operand 1 |
| 83924 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UEQ), |
| 83925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83927 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUEQ:{ *:[Other] }) => (V_CMP_NLG_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLG_F64_e64), |
| 83929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83935 | GIR_RootConstrainSelectedInstOperands, |
| 83936 | // GIR_Coverage, 259, |
| 83937 | GIR_EraseRootFromParent_Done, |
| 83938 | // Label 4593: @259936 |
| 83939 | GIM_Try, /*On fail goto*//*Label 4594*/ GIMT_Encode4(259992), // Rule ID 260 // |
| 83940 | // MIs[0] Operand 1 |
| 83941 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_ULE), |
| 83942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83943 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83944 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETULE:{ *:[Other] }) => (V_CMP_NGT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NGT_F64_e64), |
| 83946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83952 | GIR_RootConstrainSelectedInstOperands, |
| 83953 | // GIR_Coverage, 260, |
| 83954 | GIR_EraseRootFromParent_Done, |
| 83955 | // Label 4594: @259992 |
| 83956 | GIM_Try, /*On fail goto*//*Label 4595*/ GIMT_Encode4(260048), // Rule ID 261 // |
| 83957 | // MIs[0] Operand 1 |
| 83958 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGT), |
| 83959 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83961 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGT:{ *:[Other] }) => (V_CMP_NLE_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLE_F64_e64), |
| 83963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83969 | GIR_RootConstrainSelectedInstOperands, |
| 83970 | // GIR_Coverage, 261, |
| 83971 | GIR_EraseRootFromParent_Done, |
| 83972 | // Label 4595: @260048 |
| 83973 | GIM_Try, /*On fail goto*//*Label 4596*/ GIMT_Encode4(260104), // Rule ID 262 // |
| 83974 | // MIs[0] Operand 1 |
| 83975 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UNE), |
| 83976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83977 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83978 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUNE:{ *:[Other] }) => (V_CMP_NEQ_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NEQ_F64_e64), |
| 83980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 83983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 83984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 83985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 83986 | GIR_RootConstrainSelectedInstOperands, |
| 83987 | // GIR_Coverage, 262, |
| 83988 | GIR_EraseRootFromParent_Done, |
| 83989 | // Label 4596: @260104 |
| 83990 | GIM_Try, /*On fail goto*//*Label 4597*/ GIMT_Encode4(260160), // Rule ID 263 // |
| 83991 | // MIs[0] Operand 1 |
| 83992 | GIM_CheckCmpPredicate, /*MI*/0, /*Op*/1, /*Predicate*/GIMT_Encode2(CmpInst::FCMP_UGE), |
| 83993 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 83994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 83995 | // (setcc:{ *:[i1] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), SETUGE:{ *:[Other] }) => (V_CMP_NLT_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp) |
| 83996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_NLT_F64_e64), |
| 83997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 83998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 83999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84003 | GIR_RootConstrainSelectedInstOperands, |
| 84004 | // GIR_Coverage, 263, |
| 84005 | GIR_EraseRootFromParent_Done, |
| 84006 | // Label 4597: @260160 |
| 84007 | GIM_Reject, |
| 84008 | // Label 4583: @260161 |
| 84009 | GIM_Reject, |
| 84010 | // Label 4538: @260162 |
| 84011 | GIM_Reject, |
| 84012 | // Label 4534: @260163 |
| 84013 | GIM_Reject, |
| 84014 | // Label 53: @260164 |
| 84015 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4600*/ GIMT_Encode4(260367), |
| 84016 | /*GILLT_s16*//*Label 4598*/ GIMT_Encode4(260183), |
| 84017 | /*GILLT_s32*//*Label 4599*/ GIMT_Encode4(260251), |
| 84018 | // Label 4598: @260183 |
| 84019 | GIM_Try, /*On fail goto*//*Label 4601*/ GIMT_Encode4(260250), |
| 84020 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 84021 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84022 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 84023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84024 | GIM_Try, /*On fail goto*//*Label 4602*/ GIMT_Encode4(260225), // Rule ID 6702 // |
| 84025 | // (select:{ *:[f16] } i1:{ *:[i1] }:$src0, f16:{ *:[f16] }:$src1, f16:{ *:[f16] }:$src2) => (V_CNDMASK_B32_e64:{ *:[f16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src2, 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src1, SSrc_i1:{ *:[i1] }:$src0) |
| 84026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 84027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84029 | GIR_RootToRootCopy, /*OpIdx*/3, // src2 |
| 84030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84031 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84032 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84033 | GIR_RootConstrainSelectedInstOperands, |
| 84034 | // GIR_Coverage, 6702, |
| 84035 | GIR_EraseRootFromParent_Done, |
| 84036 | // Label 4602: @260225 |
| 84037 | GIM_Try, /*On fail goto*//*Label 4603*/ GIMT_Encode4(260249), // Rule ID 6703 // |
| 84038 | // (select:{ *:[i16] } i1:{ *:[i1] }:$src0, i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src2) => (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$src2, 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$src1, SSrc_i1:{ *:[i1] }:$src0) |
| 84039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 84040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84041 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84042 | GIR_RootToRootCopy, /*OpIdx*/3, // src2 |
| 84043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84044 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84045 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84046 | GIR_RootConstrainSelectedInstOperands, |
| 84047 | // GIR_Coverage, 6703, |
| 84048 | GIR_EraseRootFromParent_Done, |
| 84049 | // Label 4603: @260249 |
| 84050 | GIM_Reject, |
| 84051 | // Label 4601: @260250 |
| 84052 | GIM_Reject, |
| 84053 | // Label 4599: @260251 |
| 84054 | GIM_Try, /*On fail goto*//*Label 4604*/ GIMT_Encode4(260366), |
| 84055 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 84056 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84057 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 84058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84059 | GIM_Try, /*On fail goto*//*Label 4605*/ GIMT_Encode4(260317), // Rule ID 6700 // |
| 84060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 84061 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 84062 | // (select:{ *:[i32] } i1:{ *:[i1] }:$src0, (VOP3ModsNonCanonicalizing:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3ModsNonCanonicalizing:{ *:[i32] } i32:{ *:[i32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_CNDMASK_B32_e64:{ *:[i32] } FP32InputMods:{ *:[i32] }:$src2_mods, VSrc_b32:{ *:[i32] }:$src2, FP32InputMods:{ *:[i32] }:$src1_mods, VSrc_b32:{ *:[i32] }:$src1, SSrc_i1:{ *:[i1] }:$src0) |
| 84063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 84064 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src2_mods |
| 84066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src2 |
| 84067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 84068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84069 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84070 | GIR_RootConstrainSelectedInstOperands, |
| 84071 | // GIR_Coverage, 6700, |
| 84072 | GIR_EraseRootFromParent_Done, |
| 84073 | // Label 4605: @260317 |
| 84074 | GIM_Try, /*On fail goto*//*Label 4606*/ GIMT_Encode4(260365), // Rule ID 6701 // |
| 84075 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 84076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 84077 | // (select:{ *:[f32] } i1:{ *:[i1] }:$src0, (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_CNDMASK_B32_e64:{ *:[f32] } FP32InputMods:{ *:[i32] }:$src2_mods, VSrc_b32:{ *:[f32] }:$src2, FP32InputMods:{ *:[i32] }:$src1_mods, VSrc_b32:{ *:[f32] }:$src1, SSrc_i1:{ *:[i1] }:$src0) |
| 84078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 84079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src2_mods |
| 84081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src2 |
| 84082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 84083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84084 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84085 | GIR_RootConstrainSelectedInstOperands, |
| 84086 | // GIR_Coverage, 6701, |
| 84087 | GIR_EraseRootFromParent_Done, |
| 84088 | // Label 4606: @260365 |
| 84089 | GIM_Reject, |
| 84090 | // Label 4604: @260366 |
| 84091 | GIM_Reject, |
| 84092 | // Label 4600: @260367 |
| 84093 | GIM_Reject, |
| 84094 | // Label 54: @260368 |
| 84095 | GIM_Try, /*On fail goto*//*Label 4607*/ GIMT_Encode4(260476), |
| 84096 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 84097 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84098 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84099 | GIM_Try, /*On fail goto*//*Label 4608*/ GIMT_Encode4(260413), // Rule ID 88 // |
| 84100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84102 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84103 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84104 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18516), |
| 84105 | // (mulhu:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18516>> => (S_MUL_HI_U32:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 84106 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_HI_U32), |
| 84107 | GIR_RootConstrainSelectedInstOperands, |
| 84108 | // GIR_Coverage, 88, |
| 84109 | GIR_Done, |
| 84110 | // Label 4608: @260413 |
| 84111 | GIM_Try, /*On fail goto*//*Label 4609*/ GIMT_Encode4(260475), |
| 84112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84113 | GIM_Try, /*On fail goto*//*Label 4610*/ GIMT_Encode4(260448), // Rule ID 862 // |
| 84114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84115 | // (mulhu:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (V_MUL_HI_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 84116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_e64), |
| 84117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84119 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84120 | GIR_RootConstrainSelectedInstOperands, |
| 84121 | // GIR_Coverage, 862, |
| 84122 | GIR_EraseRootFromParent_Done, |
| 84123 | // Label 4610: @260448 |
| 84124 | GIM_Try, /*On fail goto*//*Label 4611*/ GIMT_Encode4(260474), // Rule ID 8102 // |
| 84125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84126 | // (mulhu:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_MUL_HI_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 84127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_U32_e64), |
| 84128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84130 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 84131 | GIR_RootConstrainSelectedInstOperands, |
| 84132 | // GIR_Coverage, 8102, |
| 84133 | GIR_EraseRootFromParent_Done, |
| 84134 | // Label 4611: @260474 |
| 84135 | GIM_Reject, |
| 84136 | // Label 4609: @260475 |
| 84137 | GIM_Reject, |
| 84138 | // Label 4607: @260476 |
| 84139 | GIM_Reject, |
| 84140 | // Label 55: @260477 |
| 84141 | GIM_Try, /*On fail goto*//*Label 4612*/ GIMT_Encode4(260585), |
| 84142 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 84143 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84144 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84145 | GIM_Try, /*On fail goto*//*Label 4613*/ GIMT_Encode4(260522), // Rule ID 89 // |
| 84146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84147 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84148 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84149 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84150 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18517), |
| 84151 | // (mulhs:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18517>> => (S_MUL_HI_I32:{ *:[i32] } SSrc_b32:{ *:[i32] }:$src0, SSrc_b32:{ *:[i32] }:$src1) |
| 84152 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_HI_I32), |
| 84153 | GIR_RootConstrainSelectedInstOperands, |
| 84154 | // GIR_Coverage, 89, |
| 84155 | GIR_Done, |
| 84156 | // Label 4613: @260522 |
| 84157 | GIM_Try, /*On fail goto*//*Label 4614*/ GIMT_Encode4(260584), |
| 84158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84159 | GIM_Try, /*On fail goto*//*Label 4615*/ GIMT_Encode4(260557), // Rule ID 863 // |
| 84160 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84161 | // (mulhs:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1) => (V_MUL_HI_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 84162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_e64), |
| 84163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84165 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84166 | GIR_RootConstrainSelectedInstOperands, |
| 84167 | // GIR_Coverage, 863, |
| 84168 | GIR_EraseRootFromParent_Done, |
| 84169 | // Label 4615: @260557 |
| 84170 | GIM_Try, /*On fail goto*//*Label 4616*/ GIMT_Encode4(260583), // Rule ID 8103 // |
| 84171 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84172 | // (mulhs:{ *:[i32] } i32:{ *:[i32] }:$src1, (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_MUL_HI_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 84173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_HI_I32_e64), |
| 84174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84176 | GIR_RootToRootCopy, /*OpIdx*/1, // src1 |
| 84177 | GIR_RootConstrainSelectedInstOperands, |
| 84178 | // GIR_Coverage, 8103, |
| 84179 | GIR_EraseRootFromParent_Done, |
| 84180 | // Label 4616: @260583 |
| 84181 | GIM_Reject, |
| 84182 | // Label 4614: @260584 |
| 84183 | GIM_Reject, |
| 84184 | // Label 4612: @260585 |
| 84185 | GIM_Reject, |
| 84186 | // Label 56: @260586 |
| 84187 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4620*/ GIMT_Encode4(260851), |
| 84188 | /*GILLT_s16*//*Label 4617*/ GIMT_Encode4(260613), |
| 84189 | /*GILLT_s32*//*Label 4618*/ GIMT_Encode4(260707), GIMT_Encode4(0), |
| 84190 | /*GILLT_v2s16*//*Label 4619*/ GIMT_Encode4(260776), |
| 84191 | // Label 4617: @260613 |
| 84192 | GIM_Try, /*On fail goto*//*Label 4621*/ GIMT_Encode4(260706), |
| 84193 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84194 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84196 | GIM_Try, /*On fail goto*//*Label 4622*/ GIMT_Encode4(260683), // Rule ID 2267 // |
| 84197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 84198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84200 | // (uaddsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_NC_U16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 84201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_NC_U16_e64), |
| 84202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84209 | GIR_RootConstrainSelectedInstOperands, |
| 84210 | // GIR_Coverage, 2267, |
| 84211 | GIR_EraseRootFromParent_Done, |
| 84212 | // Label 4622: @260683 |
| 84213 | GIM_Try, /*On fail goto*//*Label 4623*/ GIMT_Encode4(260705), // Rule ID 2199 // |
| 84214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasIntClamp), |
| 84215 | // (uaddsat:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_ADD_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, 1:{ *:[i1] }) |
| 84216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U16_e64), |
| 84217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84218 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84219 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84221 | GIR_RootConstrainSelectedInstOperands, |
| 84222 | // GIR_Coverage, 2199, |
| 84223 | GIR_EraseRootFromParent_Done, |
| 84224 | // Label 4623: @260705 |
| 84225 | GIM_Reject, |
| 84226 | // Label 4621: @260706 |
| 84227 | GIM_Reject, |
| 84228 | // Label 4618: @260707 |
| 84229 | GIM_Try, /*On fail goto*//*Label 4624*/ GIMT_Encode4(260775), |
| 84230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84233 | GIM_Try, /*On fail goto*//*Label 4625*/ GIMT_Encode4(260744), // Rule ID 2197 // |
| 84234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts_HasIntClamp), |
| 84235 | // (uaddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_ADD_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_U32_e64), |
| 84237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84238 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84239 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84241 | GIR_RootConstrainSelectedInstOperands, |
| 84242 | // GIR_Coverage, 2197, |
| 84243 | GIR_EraseRootFromParent_Done, |
| 84244 | // Label 4625: @260744 |
| 84245 | GIM_Try, /*On fail goto*//*Label 4626*/ GIMT_Encode4(260774), // Rule ID 2195 // |
| 84246 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasIntClamp), |
| 84247 | // (uaddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_ADD_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84248 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 84249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_CO_U32_e64), |
| 84250 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84251 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 84252 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84253 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84255 | GIR_RootConstrainSelectedInstOperands, |
| 84256 | // GIR_Coverage, 2195, |
| 84257 | GIR_EraseRootFromParent_Done, |
| 84258 | // Label 4626: @260774 |
| 84259 | GIM_Reject, |
| 84260 | // Label 4624: @260775 |
| 84261 | GIM_Reject, |
| 84262 | // Label 4619: @260776 |
| 84263 | GIM_Try, /*On fail goto*//*Label 4627*/ GIMT_Encode4(260850), // Rule ID 2299 // |
| 84264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 84265 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 84266 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 84267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84270 | // (uaddsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_U16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] }) |
| 84271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_U16), |
| 84272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84282 | GIR_RootConstrainSelectedInstOperands, |
| 84283 | // GIR_Coverage, 2299, |
| 84284 | GIR_EraseRootFromParent_Done, |
| 84285 | // Label 4627: @260850 |
| 84286 | GIM_Reject, |
| 84287 | // Label 4620: @260851 |
| 84288 | GIM_Reject, |
| 84289 | // Label 57: @260852 |
| 84290 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4631*/ GIMT_Encode4(261053), |
| 84291 | /*GILLT_s16*//*Label 4628*/ GIMT_Encode4(260879), |
| 84292 | /*GILLT_s32*//*Label 4629*/ GIMT_Encode4(260945), GIMT_Encode4(0), |
| 84293 | /*GILLT_v2s16*//*Label 4630*/ GIMT_Encode4(260978), |
| 84294 | // Label 4628: @260879 |
| 84295 | GIM_Try, /*On fail goto*//*Label 4632*/ GIMT_Encode4(260944), // Rule ID 2236 // |
| 84296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84297 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84298 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84302 | // (saddsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_I16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 84303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_I16_e64), |
| 84304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84311 | GIR_RootConstrainSelectedInstOperands, |
| 84312 | // GIR_Coverage, 2236, |
| 84313 | GIR_EraseRootFromParent_Done, |
| 84314 | // Label 4632: @260944 |
| 84315 | GIM_Reject, |
| 84316 | // Label 4629: @260945 |
| 84317 | GIM_Try, /*On fail goto*//*Label 4633*/ GIMT_Encode4(260977), // Rule ID 2233 // |
| 84318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84319 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84320 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84322 | // (saddsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_ADD_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_I32_e64), |
| 84324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84325 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84326 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84328 | GIR_RootConstrainSelectedInstOperands, |
| 84329 | // GIR_Coverage, 2233, |
| 84330 | GIR_EraseRootFromParent_Done, |
| 84331 | // Label 4633: @260977 |
| 84332 | GIM_Reject, |
| 84333 | // Label 4630: @260978 |
| 84334 | GIM_Try, /*On fail goto*//*Label 4634*/ GIMT_Encode4(261052), // Rule ID 2300 // |
| 84335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 84336 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 84337 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 84338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84341 | // (saddsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_I16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] }) |
| 84342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_I16), |
| 84343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84352 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84353 | GIR_RootConstrainSelectedInstOperands, |
| 84354 | // GIR_Coverage, 2300, |
| 84355 | GIR_EraseRootFromParent_Done, |
| 84356 | // Label 4634: @261052 |
| 84357 | GIM_Reject, |
| 84358 | // Label 4631: @261053 |
| 84359 | GIM_Reject, |
| 84360 | // Label 58: @261054 |
| 84361 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4638*/ GIMT_Encode4(261319), |
| 84362 | /*GILLT_s16*//*Label 4635*/ GIMT_Encode4(261081), |
| 84363 | /*GILLT_s32*//*Label 4636*/ GIMT_Encode4(261175), GIMT_Encode4(0), |
| 84364 | /*GILLT_v2s16*//*Label 4637*/ GIMT_Encode4(261244), |
| 84365 | // Label 4635: @261081 |
| 84366 | GIM_Try, /*On fail goto*//*Label 4639*/ GIMT_Encode4(261174), |
| 84367 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84368 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84370 | GIM_Try, /*On fail goto*//*Label 4640*/ GIMT_Encode4(261151), // Rule ID 2268 // |
| 84371 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX10Plus), |
| 84372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84373 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84374 | // (usubsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_NC_U16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 84375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_NC_U16_e64), |
| 84376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84383 | GIR_RootConstrainSelectedInstOperands, |
| 84384 | // GIR_Coverage, 2268, |
| 84385 | GIR_EraseRootFromParent_Done, |
| 84386 | // Label 4640: @261151 |
| 84387 | GIM_Try, /*On fail goto*//*Label 4641*/ GIMT_Encode4(261173), // Rule ID 2200 // |
| 84388 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasIntClamp), |
| 84389 | // (usubsat:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_SUB_U16_e64:{ *:[i16] } VSrc_b16:{ *:[i16] }:$src0, VSrc_b16:{ *:[i16] }:$src1, 1:{ *:[i1] }) |
| 84390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U16_e64), |
| 84391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84392 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84393 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84394 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84395 | GIR_RootConstrainSelectedInstOperands, |
| 84396 | // GIR_Coverage, 2200, |
| 84397 | GIR_EraseRootFromParent_Done, |
| 84398 | // Label 4641: @261173 |
| 84399 | GIM_Reject, |
| 84400 | // Label 4639: @261174 |
| 84401 | GIM_Reject, |
| 84402 | // Label 4636: @261175 |
| 84403 | GIM_Try, /*On fail goto*//*Label 4642*/ GIMT_Encode4(261243), |
| 84404 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84405 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84407 | GIM_Try, /*On fail goto*//*Label 4643*/ GIMT_Encode4(261212), // Rule ID 2198 // |
| 84408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts_HasIntClamp), |
| 84409 | // (usubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_SUB_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e64), |
| 84411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84412 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84413 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84415 | GIR_RootConstrainSelectedInstOperands, |
| 84416 | // GIR_Coverage, 2198, |
| 84417 | GIR_EraseRootFromParent_Done, |
| 84418 | // Label 4643: @261212 |
| 84419 | GIM_Try, /*On fail goto*//*Label 4644*/ GIMT_Encode4(261242), // Rule ID 2196 // |
| 84420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasIntClamp), |
| 84421 | // (usubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_SUB_CO_U32_e64:{ *:[i32] }:{ *:[i1] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 84423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e64), |
| 84424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84425 | GIR_AddTempRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define|RegState::Dead), |
| 84426 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84427 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84429 | GIR_RootConstrainSelectedInstOperands, |
| 84430 | // GIR_Coverage, 2196, |
| 84431 | GIR_EraseRootFromParent_Done, |
| 84432 | // Label 4644: @261242 |
| 84433 | GIM_Reject, |
| 84434 | // Label 4642: @261243 |
| 84435 | GIM_Reject, |
| 84436 | // Label 4637: @261244 |
| 84437 | GIM_Try, /*On fail goto*//*Label 4645*/ GIMT_Encode4(261318), // Rule ID 2301 // |
| 84438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 84439 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 84440 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 84441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84442 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84443 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84444 | // (usubsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_SUB_U16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] }) |
| 84445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_U16), |
| 84446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84451 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84452 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84456 | GIR_RootConstrainSelectedInstOperands, |
| 84457 | // GIR_Coverage, 2301, |
| 84458 | GIR_EraseRootFromParent_Done, |
| 84459 | // Label 4645: @261318 |
| 84460 | GIM_Reject, |
| 84461 | // Label 4638: @261319 |
| 84462 | GIM_Reject, |
| 84463 | // Label 59: @261320 |
| 84464 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4649*/ GIMT_Encode4(261521), |
| 84465 | /*GILLT_s16*//*Label 4646*/ GIMT_Encode4(261347), |
| 84466 | /*GILLT_s32*//*Label 4647*/ GIMT_Encode4(261413), GIMT_Encode4(0), |
| 84467 | /*GILLT_v2s16*//*Label 4648*/ GIMT_Encode4(261446), |
| 84468 | // Label 4646: @261347 |
| 84469 | GIM_Try, /*On fail goto*//*Label 4650*/ GIMT_Encode4(261412), // Rule ID 2237 // |
| 84470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opsel), |
| 84476 | // (ssubsat:{ *:[i16] } (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSel:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_I16_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[i16] }:$src1, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 84477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_I16_e64), |
| 84478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84485 | GIR_RootConstrainSelectedInstOperands, |
| 84486 | // GIR_Coverage, 2237, |
| 84487 | GIR_EraseRootFromParent_Done, |
| 84488 | // Label 4650: @261412 |
| 84489 | GIM_Reject, |
| 84490 | // Label 4647: @261413 |
| 84491 | GIM_Try, /*On fail goto*//*Label 4651*/ GIMT_Encode4(261445), // Rule ID 2234 // |
| 84492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 84493 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84494 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84496 | // (ssubsat:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_SUB_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, 1:{ *:[i1] }) |
| 84497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_I32_e64), |
| 84498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84499 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 84500 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 84501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84502 | GIR_RootConstrainSelectedInstOperands, |
| 84503 | // GIR_Coverage, 2234, |
| 84504 | GIR_EraseRootFromParent_Done, |
| 84505 | // Label 4651: @261445 |
| 84506 | GIM_Reject, |
| 84507 | // Label 4648: @261446 |
| 84508 | GIM_Try, /*On fail goto*//*Label 4652*/ GIMT_Encode4(261520), // Rule ID 2302 // |
| 84509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 84510 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 84511 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 84512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84513 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84515 | // (ssubsat:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_SUB_I16:{ *:[v2i16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2i16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[v2i16] }:$src1, 1:{ *:[i1] }) |
| 84516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_SUB_I16), |
| 84517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 84523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84527 | GIR_RootConstrainSelectedInstOperands, |
| 84528 | // GIR_Coverage, 2302, |
| 84529 | GIR_EraseRootFromParent_Done, |
| 84530 | // Label 4652: @261520 |
| 84531 | GIM_Reject, |
| 84532 | // Label 4649: @261521 |
| 84533 | GIM_Reject, |
| 84534 | // Label 60: @261522 |
| 84535 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4658*/ GIMT_Encode4(262879), |
| 84536 | /*GILLT_s16*//*Label 4653*/ GIMT_Encode4(261553), |
| 84537 | /*GILLT_s32*//*Label 4654*/ GIMT_Encode4(261915), |
| 84538 | /*GILLT_s64*//*Label 4655*/ GIMT_Encode4(262479), |
| 84539 | /*GILLT_v2s16*//*Label 4656*/ GIMT_Encode4(262732), |
| 84540 | /*GILLT_v2s32*//*Label 4657*/ GIMT_Encode4(262804), |
| 84541 | // Label 4653: @261553 |
| 84542 | GIM_Try, /*On fail goto*//*Label 4659*/ GIMT_Encode4(261914), |
| 84543 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84544 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84545 | GIM_Try, /*On fail goto*//*Label 4660*/ GIMT_Encode4(261599), // Rule ID 99 // |
| 84546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 84547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84548 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84549 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84550 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18518), |
| 84551 | // (fadd:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18518>> => (S_ADD_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 84552 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F16), |
| 84553 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 84554 | GIR_RootConstrainSelectedInstOperands, |
| 84555 | // GIR_Coverage, 99, |
| 84556 | GIR_Done, |
| 84557 | // Label 4660: @261599 |
| 84558 | GIM_Try, /*On fail goto*//*Label 4661*/ GIMT_Encode4(261662), // Rule ID 790 // |
| 84559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 84560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84563 | // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64), |
| 84565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84572 | GIR_RootConstrainSelectedInstOperands, |
| 84573 | // GIR_Coverage, 790, |
| 84574 | GIR_EraseRootFromParent_Done, |
| 84575 | // Label 4661: @261662 |
| 84576 | GIM_Try, /*On fail goto*//*Label 4662*/ GIMT_Encode4(261725), // Rule ID 794 // |
| 84577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 84578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84581 | // (fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84582 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64), |
| 84583 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84590 | GIR_RootConstrainSelectedInstOperands, |
| 84591 | // GIR_Coverage, 794, |
| 84592 | GIR_EraseRootFromParent_Done, |
| 84593 | // Label 4662: @261725 |
| 84594 | GIM_Try, /*On fail goto*//*Label 4663*/ GIMT_Encode4(261788), // Rule ID 8063 // |
| 84595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 84596 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84599 | // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64), |
| 84601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 84603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 84605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 84607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 84608 | GIR_RootConstrainSelectedInstOperands, |
| 84609 | // GIR_Coverage, 8063, |
| 84610 | GIR_EraseRootFromParent_Done, |
| 84611 | // Label 4663: @261788 |
| 84612 | GIM_Try, /*On fail goto*//*Label 4664*/ GIMT_Encode4(261851), // Rule ID 8065 // |
| 84613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 84614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84617 | // (fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64), |
| 84619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 84621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 84623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 84625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 84626 | GIR_RootConstrainSelectedInstOperands, |
| 84627 | // GIR_Coverage, 8065, |
| 84628 | GIR_EraseRootFromParent_Done, |
| 84629 | // Label 4664: @261851 |
| 84630 | GIM_Try, /*On fail goto*//*Label 4665*/ GIMT_Encode4(261913), // Rule ID 792 // |
| 84631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 84632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 84633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 84634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 84635 | // (fadd:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 84636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64), |
| 84637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84645 | GIR_RootConstrainSelectedInstOperands, |
| 84646 | // GIR_Coverage, 792, |
| 84647 | GIR_EraseRootFromParent_Done, |
| 84648 | // Label 4665: @261913 |
| 84649 | GIM_Reject, |
| 84650 | // Label 4659: @261914 |
| 84651 | GIM_Reject, |
| 84652 | // Label 4654: @261915 |
| 84653 | GIM_Try, /*On fail goto*//*Label 4666*/ GIMT_Encode4(262478), |
| 84654 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 84655 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 84656 | GIM_Try, /*On fail goto*//*Label 4667*/ GIMT_Encode4(262022), // Rule ID 10781 // |
| 84657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10), |
| 84658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84660 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 84661 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 84662 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 84663 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 84664 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 84665 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84667 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84668 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84669 | // (fadd:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2), (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1))) => (V_MAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 84670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_LEGACY_F32_e64), |
| 84671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 84676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 84678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84680 | GIR_RootConstrainSelectedInstOperands, |
| 84681 | // GIR_Coverage, 10781, |
| 84682 | GIR_EraseRootFromParent_Done, |
| 84683 | // Label 4667: @262022 |
| 84684 | GIM_Try, /*On fail goto*//*Label 4668*/ GIMT_Encode4(262124), // Rule ID 10783 // |
| 84685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals), |
| 84686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84687 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 84688 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 84689 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 84690 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 84691 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 84692 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 84693 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84695 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84696 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 84697 | // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mod), (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mod))) => (V_MAD_LEGACY_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mod, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mod, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mod, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 84698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_LEGACY_F32_e64), |
| 84699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mod |
| 84701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mod |
| 84703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 84704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mod |
| 84705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 84706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84708 | GIR_RootConstrainSelectedInstOperands, |
| 84709 | // GIR_Coverage, 10783, |
| 84710 | GIR_EraseRootFromParent_Done, |
| 84711 | // Label 4668: @262124 |
| 84712 | GIM_Try, /*On fail goto*//*Label 4669*/ GIMT_Encode4(262220), // Rule ID 6692 // |
| 84713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals_isGFX6GFX7GFX10), |
| 84714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84715 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84716 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 84717 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 84718 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 84719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 84720 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 84721 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84723 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84724 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 84725 | // (fadd:{ *:[f32] } (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1)), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2)) => (V_MAC_LEGACY_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 84726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_LEGACY_F32_e64), |
| 84727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 84734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84736 | GIR_RootConstrainSelectedInstOperands, |
| 84737 | // GIR_Coverage, 6692, |
| 84738 | GIR_EraseRootFromParent_Done, |
| 84739 | // Label 4669: @262220 |
| 84740 | GIM_Try, /*On fail goto*//*Label 4670*/ GIMT_Encode4(262322), // Rule ID 6698 // |
| 84741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts_NoFP32Denormals), |
| 84742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 84744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_INTRINSIC), |
| 84745 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/4, |
| 84746 | GIM_CheckIntrinsicID, /*MI*/1, /*Op*/1, GIMT_Encode2(Intrinsic::amdgcn_fmul_legacy), |
| 84747 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 84748 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 84749 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 84750 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 84751 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84752 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84753 | // (fadd:{ *:[f32] } (intrinsic_wo_chain:{ *:[f32] } 2026:{ *:[iPTR] }, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mod)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mod)) => (V_MAD_LEGACY_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mod, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mod, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mod, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 84754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_LEGACY_F32_e64), |
| 84755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mod |
| 84757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mod |
| 84759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mod |
| 84761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 84762 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84764 | GIR_RootConstrainSelectedInstOperands, |
| 84765 | // GIR_Coverage, 6698, |
| 84766 | GIR_EraseRootFromParent_Done, |
| 84767 | // Label 4670: @262322 |
| 84768 | GIM_Try, /*On fail goto*//*Label 4671*/ GIMT_Encode4(262357), // Rule ID 91 // |
| 84769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 84770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84771 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84772 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84773 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18518), |
| 84774 | // (fadd:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18518>> => (S_ADD_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 84775 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F32), |
| 84776 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 84777 | GIR_RootConstrainSelectedInstOperands, |
| 84778 | // GIR_Coverage, 91, |
| 84779 | GIR_Done, |
| 84780 | // Label 4671: @262357 |
| 84781 | GIM_Try, /*On fail goto*//*Label 4672*/ GIMT_Encode4(262417), // Rule ID 722 // |
| 84782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84783 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84785 | // (fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64), |
| 84787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84794 | GIR_RootConstrainSelectedInstOperands, |
| 84795 | // GIR_Coverage, 722, |
| 84796 | GIR_EraseRootFromParent_Done, |
| 84797 | // Label 4672: @262417 |
| 84798 | GIM_Try, /*On fail goto*//*Label 4673*/ GIMT_Encode4(262477), // Rule ID 8052 // |
| 84799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84801 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84802 | // (fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64), |
| 84804 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 84806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 84808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 84810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 84811 | GIR_RootConstrainSelectedInstOperands, |
| 84812 | // GIR_Coverage, 8052, |
| 84813 | GIR_EraseRootFromParent_Done, |
| 84814 | // Label 4673: @262477 |
| 84815 | GIM_Reject, |
| 84816 | // Label 4666: @262478 |
| 84817 | GIM_Reject, |
| 84818 | // Label 4655: @262479 |
| 84819 | GIM_Try, /*On fail goto*//*Label 4674*/ GIMT_Encode4(262731), |
| 84820 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 84821 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 84822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 84823 | GIM_Try, /*On fail goto*//*Label 4675*/ GIMT_Encode4(262553), // Rule ID 836 // |
| 84824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 84825 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84826 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84827 | // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64), |
| 84829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84836 | GIR_RootConstrainSelectedInstOperands, |
| 84837 | // GIR_Coverage, 836, |
| 84838 | GIR_EraseRootFromParent_Done, |
| 84839 | // Label 4675: @262553 |
| 84840 | GIM_Try, /*On fail goto*//*Label 4676*/ GIMT_Encode4(262612), // Rule ID 854 // |
| 84841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 84842 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84844 | // (fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64), |
| 84846 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84853 | GIR_RootConstrainSelectedInstOperands, |
| 84854 | // GIR_Coverage, 854, |
| 84855 | GIR_EraseRootFromParent_Done, |
| 84856 | // Label 4676: @262612 |
| 84857 | GIM_Try, /*On fail goto*//*Label 4677*/ GIMT_Encode4(262671), // Rule ID 8081 // |
| 84858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 84859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84861 | // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64), |
| 84863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 84865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 84867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 84869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 84870 | GIR_RootConstrainSelectedInstOperands, |
| 84871 | // GIR_Coverage, 8081, |
| 84872 | GIR_EraseRootFromParent_Done, |
| 84873 | // Label 4677: @262671 |
| 84874 | GIM_Try, /*On fail goto*//*Label 4678*/ GIMT_Encode4(262730), // Rule ID 8094 // |
| 84875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 84876 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 84877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84878 | // (fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64), |
| 84880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 84882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 84883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 84884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 84885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 84886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 84887 | GIR_RootConstrainSelectedInstOperands, |
| 84888 | // GIR_Coverage, 8094, |
| 84889 | GIR_EraseRootFromParent_Done, |
| 84890 | // Label 4678: @262730 |
| 84891 | GIM_Reject, |
| 84892 | // Label 4674: @262731 |
| 84893 | GIM_Reject, |
| 84894 | // Label 4656: @262732 |
| 84895 | GIM_Try, /*On fail goto*//*Label 4679*/ GIMT_Encode4(262803), // Rule ID 958 // |
| 84896 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 84897 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 84898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84901 | // (fadd:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 84902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F16), |
| 84903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84913 | GIR_RootConstrainSelectedInstOperands, |
| 84914 | // GIR_Coverage, 958, |
| 84915 | GIR_EraseRootFromParent_Done, |
| 84916 | // Label 4679: @262803 |
| 84917 | GIM_Reject, |
| 84918 | // Label 4657: @262804 |
| 84919 | GIM_Try, /*On fail goto*//*Label 4680*/ GIMT_Encode4(262878), // Rule ID 1086 // |
| 84920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 84921 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 84922 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 84923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 84924 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 84926 | // (fadd:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1) |
| 84927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32), |
| 84928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84933 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84934 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 84938 | GIR_RootConstrainSelectedInstOperands, |
| 84939 | // GIR_Coverage, 1086, |
| 84940 | GIR_EraseRootFromParent_Done, |
| 84941 | // Label 4680: @262878 |
| 84942 | GIM_Reject, |
| 84943 | // Label 4658: @262879 |
| 84944 | GIM_Reject, |
| 84945 | // Label 61: @262880 |
| 84946 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4683*/ GIMT_Encode4(263243), |
| 84947 | /*GILLT_s16*//*Label 4681*/ GIMT_Encode4(262899), |
| 84948 | /*GILLT_s32*//*Label 4682*/ GIMT_Encode4(263135), |
| 84949 | // Label 4681: @262899 |
| 84950 | GIM_Try, /*On fail goto*//*Label 4684*/ GIMT_Encode4(263134), |
| 84951 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 84952 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 84953 | GIM_Try, /*On fail goto*//*Label 4685*/ GIMT_Encode4(262945), // Rule ID 107 // |
| 84954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 84955 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84956 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84957 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 84958 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18522), |
| 84959 | // (fsub:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18522>> => (S_SUB_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 84960 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F16), |
| 84961 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 84962 | GIR_RootConstrainSelectedInstOperands, |
| 84963 | // GIR_Coverage, 107, |
| 84964 | GIR_Done, |
| 84965 | // Label 4685: @262945 |
| 84966 | GIM_Try, /*On fail goto*//*Label 4686*/ GIMT_Encode4(263008), // Rule ID 796 // |
| 84967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 84968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84971 | // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_e64), |
| 84973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84980 | GIR_RootConstrainSelectedInstOperands, |
| 84981 | // GIR_Coverage, 796, |
| 84982 | GIR_EraseRootFromParent_Done, |
| 84983 | // Label 4686: @263008 |
| 84984 | GIM_Try, /*On fail goto*//*Label 4687*/ GIMT_Encode4(263071), // Rule ID 800 // |
| 84985 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 84986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 84987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 84988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 84989 | // (fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 84990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_fake16_e64), |
| 84991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 84992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 84993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 84994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 84995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 84996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 84997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 84998 | GIR_RootConstrainSelectedInstOperands, |
| 84999 | // GIR_Coverage, 800, |
| 85000 | GIR_EraseRootFromParent_Done, |
| 85001 | // Label 4687: @263071 |
| 85002 | GIM_Try, /*On fail goto*//*Label 4688*/ GIMT_Encode4(263133), // Rule ID 798 // |
| 85003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 85004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 85005 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85007 | // (fsub:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 85008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_t16_e64), |
| 85009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85017 | GIR_RootConstrainSelectedInstOperands, |
| 85018 | // GIR_Coverage, 798, |
| 85019 | GIR_EraseRootFromParent_Done, |
| 85020 | // Label 4688: @263133 |
| 85021 | GIM_Reject, |
| 85022 | // Label 4684: @263134 |
| 85023 | GIM_Reject, |
| 85024 | // Label 4682: @263135 |
| 85025 | GIM_Try, /*On fail goto*//*Label 4689*/ GIMT_Encode4(263242), |
| 85026 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 85027 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 85028 | GIM_Try, /*On fail goto*//*Label 4690*/ GIMT_Encode4(263181), // Rule ID 109 // |
| 85029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 85030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85031 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85032 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85033 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18522), |
| 85034 | // (fsub:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18522>> => (S_SUB_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 85035 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F32), |
| 85036 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 85037 | GIR_RootConstrainSelectedInstOperands, |
| 85038 | // GIR_Coverage, 109, |
| 85039 | GIR_Done, |
| 85040 | // Label 4690: @263181 |
| 85041 | GIM_Try, /*On fail goto*//*Label 4691*/ GIMT_Encode4(263241), // Rule ID 724 // |
| 85042 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85045 | // (fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F32_e64), |
| 85047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85054 | GIR_RootConstrainSelectedInstOperands, |
| 85055 | // GIR_Coverage, 724, |
| 85056 | GIR_EraseRootFromParent_Done, |
| 85057 | // Label 4691: @263241 |
| 85058 | GIM_Reject, |
| 85059 | // Label 4689: @263242 |
| 85060 | GIM_Reject, |
| 85061 | // Label 4683: @263243 |
| 85062 | GIM_Reject, |
| 85063 | // Label 62: @263244 |
| 85064 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4697*/ GIMT_Encode4(264629), |
| 85065 | /*GILLT_s16*//*Label 4692*/ GIMT_Encode4(263275), |
| 85066 | /*GILLT_s32*//*Label 4693*/ GIMT_Encode4(263637), |
| 85067 | /*GILLT_s64*//*Label 4694*/ GIMT_Encode4(263805), |
| 85068 | /*GILLT_v2s16*//*Label 4695*/ GIMT_Encode4(264482), |
| 85069 | /*GILLT_v2s32*//*Label 4696*/ GIMT_Encode4(264554), |
| 85070 | // Label 4692: @263275 |
| 85071 | GIM_Try, /*On fail goto*//*Label 4698*/ GIMT_Encode4(263636), |
| 85072 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 85073 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 85074 | GIM_Try, /*On fail goto*//*Label 4699*/ GIMT_Encode4(263321), // Rule ID 101 // |
| 85075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 85076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85077 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85078 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85079 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18521), |
| 85080 | // (fmul:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18521>> => (S_MUL_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 85081 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F16), |
| 85082 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 85083 | GIR_RootConstrainSelectedInstOperands, |
| 85084 | // GIR_Coverage, 101, |
| 85085 | GIR_Done, |
| 85086 | // Label 4699: @263321 |
| 85087 | GIM_Try, /*On fail goto*//*Label 4700*/ GIMT_Encode4(263384), // Rule ID 802 // |
| 85088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 85089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85092 | // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 85094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85101 | GIR_RootConstrainSelectedInstOperands, |
| 85102 | // GIR_Coverage, 802, |
| 85103 | GIR_EraseRootFromParent_Done, |
| 85104 | // Label 4700: @263384 |
| 85105 | GIM_Try, /*On fail goto*//*Label 4701*/ GIMT_Encode4(263447), // Rule ID 806 // |
| 85106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 85107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85110 | // (fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 85112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85119 | GIR_RootConstrainSelectedInstOperands, |
| 85120 | // GIR_Coverage, 806, |
| 85121 | GIR_EraseRootFromParent_Done, |
| 85122 | // Label 4701: @263447 |
| 85123 | GIM_Try, /*On fail goto*//*Label 4702*/ GIMT_Encode4(263510), // Rule ID 8067 // |
| 85124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 85125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85128 | // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 85130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85137 | GIR_RootConstrainSelectedInstOperands, |
| 85138 | // GIR_Coverage, 8067, |
| 85139 | GIR_EraseRootFromParent_Done, |
| 85140 | // Label 4702: @263510 |
| 85141 | GIM_Try, /*On fail goto*//*Label 4703*/ GIMT_Encode4(263573), // Rule ID 8069 // |
| 85142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 85143 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85146 | // (fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 85148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85155 | GIR_RootConstrainSelectedInstOperands, |
| 85156 | // GIR_Coverage, 8069, |
| 85157 | GIR_EraseRootFromParent_Done, |
| 85158 | // Label 4703: @263573 |
| 85159 | GIM_Try, /*On fail goto*//*Label 4704*/ GIMT_Encode4(263635), // Rule ID 804 // |
| 85160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 85161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 85162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85164 | // (fmul:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 85165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64), |
| 85166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85174 | GIR_RootConstrainSelectedInstOperands, |
| 85175 | // GIR_Coverage, 804, |
| 85176 | GIR_EraseRootFromParent_Done, |
| 85177 | // Label 4704: @263635 |
| 85178 | GIM_Reject, |
| 85179 | // Label 4698: @263636 |
| 85180 | GIM_Reject, |
| 85181 | // Label 4693: @263637 |
| 85182 | GIM_Try, /*On fail goto*//*Label 4705*/ GIMT_Encode4(263804), |
| 85183 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 85184 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 85185 | GIM_Try, /*On fail goto*//*Label 4706*/ GIMT_Encode4(263683), // Rule ID 97 // |
| 85186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 85187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85188 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85189 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85190 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18521), |
| 85191 | // (fmul:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18521>> => (S_MUL_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 85192 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F32), |
| 85193 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 85194 | GIR_RootConstrainSelectedInstOperands, |
| 85195 | // GIR_Coverage, 97, |
| 85196 | GIR_Done, |
| 85197 | // Label 4706: @263683 |
| 85198 | GIM_Try, /*On fail goto*//*Label 4707*/ GIMT_Encode4(263743), // Rule ID 728 // |
| 85199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85202 | // (fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 85204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85211 | GIR_RootConstrainSelectedInstOperands, |
| 85212 | // GIR_Coverage, 728, |
| 85213 | GIR_EraseRootFromParent_Done, |
| 85214 | // Label 4707: @263743 |
| 85215 | GIM_Try, /*On fail goto*//*Label 4708*/ GIMT_Encode4(263803), // Rule ID 8056 // |
| 85216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85219 | // (fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 85221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85228 | GIR_RootConstrainSelectedInstOperands, |
| 85229 | // GIR_Coverage, 8056, |
| 85230 | GIR_EraseRootFromParent_Done, |
| 85231 | // Label 4708: @263803 |
| 85232 | GIM_Reject, |
| 85233 | // Label 4705: @263804 |
| 85234 | GIM_Reject, |
| 85235 | // Label 4694: @263805 |
| 85236 | GIM_Try, /*On fail goto*//*Label 4709*/ GIMT_Encode4(264481), |
| 85237 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 85238 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 85239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 85240 | GIM_Try, /*On fail goto*//*Label 4710*/ GIMT_Encode4(263894), // Rule ID 7427 // |
| 85241 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85242 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85243 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64), |
| 85244 | // MIs[1] Operand 1 |
| 85245 | // No operand predicates |
| 85246 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85248 | // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85249 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85250 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85251 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85252 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85253 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 85257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85262 | GIR_RootConstrainSelectedInstOperands, |
| 85263 | // GIR_Coverage, 7427, |
| 85264 | GIR_EraseRootFromParent_Done, |
| 85265 | // Label 4710: @263894 |
| 85266 | GIM_Try, /*On fail goto*//*Label 4711*/ GIMT_Encode4(263968), // Rule ID 11986 // |
| 85267 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85268 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85269 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64), |
| 85270 | // MIs[1] Operand 1 |
| 85271 | // No operand predicates |
| 85272 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85274 | // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods)) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85275 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85276 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85277 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85278 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85279 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 85283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85285 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85287 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85288 | GIR_RootConstrainSelectedInstOperands, |
| 85289 | // GIR_Coverage, 11986, |
| 85290 | GIR_EraseRootFromParent_Done, |
| 85291 | // Label 4711: @263968 |
| 85292 | GIM_Try, /*On fail goto*//*Label 4712*/ GIMT_Encode4(264044), // Rule ID 7431 // |
| 85293 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85294 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 85295 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 85296 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 85297 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85298 | GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 85299 | // MIs[2] Operand 1 |
| 85300 | // No operand predicates |
| 85301 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85302 | // (fmul:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85306 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85307 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 85311 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 85312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85313 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85314 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85316 | GIR_RootConstrainSelectedInstOperands, |
| 85317 | // GIR_Coverage, 7431, |
| 85318 | GIR_EraseRootFromParent_Done, |
| 85319 | // Label 4712: @264044 |
| 85320 | GIM_Try, /*On fail goto*//*Label 4713*/ GIMT_Encode4(264120), // Rule ID 11990 // |
| 85321 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85322 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85323 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 85324 | // MIs[1] Operand 1 |
| 85325 | // No operand predicates |
| 85326 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 85327 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 85328 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 85329 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 85330 | // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0)) => (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85331 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85332 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85333 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85334 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85335 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 85339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 85340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85344 | GIR_RootConstrainSelectedInstOperands, |
| 85345 | // GIR_Coverage, 11990, |
| 85346 | GIR_EraseRootFromParent_Done, |
| 85347 | // Label 4713: @264120 |
| 85348 | GIM_Try, /*On fail goto*//*Label 4714*/ GIMT_Encode4(264182), // Rule ID 11988 // |
| 85349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 85350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85351 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 85352 | // MIs[1] Operand 1 |
| 85353 | // No operand predicates |
| 85354 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85355 | // (fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, f64:{ *:[f64] }:$src0) => (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85356 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85357 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85358 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85359 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85364 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 85365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85366 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85369 | GIR_RootConstrainSelectedInstOperands, |
| 85370 | // GIR_Coverage, 11988, |
| 85371 | GIR_EraseRootFromParent_Done, |
| 85372 | // Label 4714: @264182 |
| 85373 | GIM_Try, /*On fail goto*//*Label 4715*/ GIMT_Encode4(264244), // Rule ID 7429 // |
| 85374 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 85375 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 85376 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 85377 | // MIs[1] Operand 1 |
| 85378 | // No operand predicates |
| 85379 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 85380 | // (fmul:{ *:[f64] } f64:{ *:[f64] }:$src0, (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 85381 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 85382 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 85383 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 85384 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 85385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 85386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 85387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 85389 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 85390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85391 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 85392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85394 | GIR_RootConstrainSelectedInstOperands, |
| 85395 | // GIR_Coverage, 7429, |
| 85396 | GIR_EraseRootFromParent_Done, |
| 85397 | // Label 4715: @264244 |
| 85398 | GIM_Try, /*On fail goto*//*Label 4716*/ GIMT_Encode4(264303), // Rule ID 837 // |
| 85399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 85400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85402 | // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_pseudo_e64), |
| 85404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85411 | GIR_RootConstrainSelectedInstOperands, |
| 85412 | // GIR_Coverage, 837, |
| 85413 | GIR_EraseRootFromParent_Done, |
| 85414 | // Label 4716: @264303 |
| 85415 | GIM_Try, /*On fail goto*//*Label 4717*/ GIMT_Encode4(264362), // Rule ID 856 // |
| 85416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 85417 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85418 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85419 | // (fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85420 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64), |
| 85421 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85428 | GIR_RootConstrainSelectedInstOperands, |
| 85429 | // GIR_Coverage, 856, |
| 85430 | GIR_EraseRootFromParent_Done, |
| 85431 | // Label 4717: @264362 |
| 85432 | GIM_Try, /*On fail goto*//*Label 4718*/ GIMT_Encode4(264421), // Rule ID 8082 // |
| 85433 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 85434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85436 | // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_pseudo_e64), |
| 85438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85445 | GIR_RootConstrainSelectedInstOperands, |
| 85446 | // GIR_Coverage, 8082, |
| 85447 | GIR_EraseRootFromParent_Done, |
| 85448 | // Label 4718: @264421 |
| 85449 | GIM_Try, /*On fail goto*//*Label 4719*/ GIMT_Encode4(264480), // Rule ID 8096 // |
| 85450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 85451 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85453 | // (fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64), |
| 85455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85462 | GIR_RootConstrainSelectedInstOperands, |
| 85463 | // GIR_Coverage, 8096, |
| 85464 | GIR_EraseRootFromParent_Done, |
| 85465 | // Label 4719: @264480 |
| 85466 | GIM_Reject, |
| 85467 | // Label 4709: @264481 |
| 85468 | GIM_Reject, |
| 85469 | // Label 4695: @264482 |
| 85470 | GIM_Try, /*On fail goto*//*Label 4720*/ GIMT_Encode4(264553), // Rule ID 960 // |
| 85471 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 85472 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 85473 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85476 | // (fmul:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MUL_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 85477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16), |
| 85478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85488 | GIR_RootConstrainSelectedInstOperands, |
| 85489 | // GIR_Coverage, 960, |
| 85490 | GIR_EraseRootFromParent_Done, |
| 85491 | // Label 4720: @264553 |
| 85492 | GIM_Reject, |
| 85493 | // Label 4696: @264554 |
| 85494 | GIM_Try, /*On fail goto*//*Label 4721*/ GIMT_Encode4(264628), // Rule ID 1084 // |
| 85495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 85496 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 85497 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 85498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 85499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85500 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85501 | // (fmul:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MUL_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1) |
| 85502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32), |
| 85503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85509 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85513 | GIR_RootConstrainSelectedInstOperands, |
| 85514 | // GIR_Coverage, 1084, |
| 85515 | GIR_EraseRootFromParent_Done, |
| 85516 | // Label 4721: @264628 |
| 85517 | GIM_Reject, |
| 85518 | // Label 4697: @264629 |
| 85519 | GIM_Reject, |
| 85520 | // Label 63: @264630 |
| 85521 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4727*/ GIMT_Encode4(266270), |
| 85522 | /*GILLT_s16*//*Label 4722*/ GIMT_Encode4(264661), |
| 85523 | /*GILLT_s32*//*Label 4723*/ GIMT_Encode4(265098), |
| 85524 | /*GILLT_s64*//*Label 4724*/ GIMT_Encode4(265851), |
| 85525 | /*GILLT_v2s16*//*Label 4725*/ GIMT_Encode4(266083), |
| 85526 | /*GILLT_v2s32*//*Label 4726*/ GIMT_Encode4(266175), |
| 85527 | // Label 4722: @264661 |
| 85528 | GIM_Try, /*On fail goto*//*Label 4728*/ GIMT_Encode4(265097), |
| 85529 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 85530 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 85531 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 85532 | GIM_Try, /*On fail goto*//*Label 4729*/ GIMT_Encode4(264714), // Rule ID 115 // |
| 85533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 85534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85535 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85536 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85537 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85538 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18524), |
| 85539 | // (fma:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)<<P:Predicate_anonymous_18524>> => (S_FMAC_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2) |
| 85540 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F16), |
| 85541 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 85542 | GIR_RootConstrainSelectedInstOperands, |
| 85543 | // GIR_Coverage, 115, |
| 85544 | GIR_Done, |
| 85545 | // Label 4729: @264714 |
| 85546 | GIM_Try, /*On fail goto*//*Label 4730*/ GIMT_Encode4(264784), // Rule ID 7236 // |
| 85547 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts_isGFX10Plus), |
| 85548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85552 | // (fma:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src2)) => (V_FMAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2) |
| 85553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F16_e64), |
| 85554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85563 | GIR_RootConstrainSelectedInstOperands, |
| 85564 | // GIR_Coverage, 7236, |
| 85565 | GIR_EraseRootFromParent_Done, |
| 85566 | // Label 4730: @264784 |
| 85567 | GIM_Try, /*On fail goto*//*Label 4731*/ GIMT_Encode4(264857), // Rule ID 7237 // |
| 85568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts_isGFX10Plus), |
| 85569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85570 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85572 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85573 | // (fma:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f16] } f32:{ *:[f32] }:$src2)) => (V_FMAC_F16_t16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2) |
| 85574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F16_t16_e64), |
| 85575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85585 | GIR_RootConstrainSelectedInstOperands, |
| 85586 | // GIR_Coverage, 7237, |
| 85587 | GIR_EraseRootFromParent_Done, |
| 85588 | // Label 4731: @264857 |
| 85589 | GIM_Try, /*On fail goto*//*Label 4732*/ GIMT_Encode4(264937), // Rule ID 918 // |
| 85590 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only), |
| 85591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85592 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85593 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85594 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85595 | // (fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64), |
| 85597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85606 | GIR_RootConstrainSelectedInstOperands, |
| 85607 | // GIR_Coverage, 918, |
| 85608 | GIR_EraseRootFromParent_Done, |
| 85609 | // Label 4732: @264937 |
| 85610 | GIM_Try, /*On fail goto*//*Label 4733*/ GIMT_Encode4(265017), // Rule ID 8111 // |
| 85611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only), |
| 85612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85616 | // (fma:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64), |
| 85618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85627 | GIR_RootConstrainSelectedInstOperands, |
| 85628 | // GIR_Coverage, 8111, |
| 85629 | GIR_EraseRootFromParent_Done, |
| 85630 | // Label 4733: @265017 |
| 85631 | GIM_Try, /*On fail goto*//*Label 4734*/ GIMT_Encode4(265096), // Rule ID 922 // |
| 85632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 85633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 85637 | // (fma:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 85638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_gfx9_e64), |
| 85639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85649 | GIR_RootConstrainSelectedInstOperands, |
| 85650 | // GIR_Coverage, 922, |
| 85651 | GIR_EraseRootFromParent_Done, |
| 85652 | // Label 4734: @265096 |
| 85653 | GIM_Reject, |
| 85654 | // Label 4728: @265097 |
| 85655 | GIM_Reject, |
| 85656 | // Label 4723: @265098 |
| 85657 | GIM_Try, /*On fail goto*//*Label 4735*/ GIMT_Encode4(265850), |
| 85658 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 85659 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 85660 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 85661 | GIM_Try, /*On fail goto*//*Label 4736*/ GIMT_Encode4(265191), // Rule ID 2312 // |
| 85662 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85667 | // (fma:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 85668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 85671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 85673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85679 | GIR_RootConstrainSelectedInstOperands, |
| 85680 | // GIR_Coverage, 2312, |
| 85681 | GIR_EraseRootFromParent_Done, |
| 85682 | // Label 4736: @265191 |
| 85683 | GIM_Try, /*On fail goto*//*Label 4737*/ GIMT_Encode4(265270), // Rule ID 2313 // |
| 85684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85688 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85689 | // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }) |
| 85690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 85693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 85695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85698 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85701 | GIR_RootConstrainSelectedInstOperands, |
| 85702 | // GIR_Coverage, 2313, |
| 85703 | GIR_EraseRootFromParent_Done, |
| 85704 | // Label 4737: @265270 |
| 85705 | GIM_Try, /*On fail goto*//*Label 4738*/ GIMT_Encode4(265349), // Rule ID 2314 // |
| 85706 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85709 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85710 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85711 | // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 85712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 85715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 85717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85723 | GIR_RootConstrainSelectedInstOperands, |
| 85724 | // GIR_Coverage, 2314, |
| 85725 | GIR_EraseRootFromParent_Done, |
| 85726 | // Label 4738: @265349 |
| 85727 | GIM_Try, /*On fail goto*//*Label 4739*/ GIMT_Encode4(265428), // Rule ID 8150 // |
| 85728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85730 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85732 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85733 | // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 85734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 85737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 85739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85745 | GIR_RootConstrainSelectedInstOperands, |
| 85746 | // GIR_Coverage, 8150, |
| 85747 | GIR_EraseRootFromParent_Done, |
| 85748 | // Label 4739: @265428 |
| 85749 | GIM_Try, /*On fail goto*//*Label 4740*/ GIMT_Encode4(265507), // Rule ID 8151 // |
| 85750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85752 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85755 | // (fma:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }) |
| 85756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 85759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 85761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85767 | GIR_RootConstrainSelectedInstOperands, |
| 85768 | // GIR_Coverage, 8151, |
| 85769 | GIR_EraseRootFromParent_Done, |
| 85770 | // Label 4740: @265507 |
| 85771 | GIM_Try, /*On fail goto*//*Label 4741*/ GIMT_Encode4(265586), // Rule ID 8152 // |
| 85772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 85773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 85776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 85777 | // (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_FMA_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 85778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIX_F32), |
| 85779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 85781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 85783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 85785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85789 | GIR_RootConstrainSelectedInstOperands, |
| 85790 | // GIR_Coverage, 8152, |
| 85791 | GIR_EraseRootFromParent_Done, |
| 85792 | // Label 4741: @265586 |
| 85793 | GIM_Try, /*On fail goto*//*Label 4742*/ GIMT_Encode4(265625), // Rule ID 113 // |
| 85794 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 85795 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85796 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85797 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85798 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 85799 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18524), |
| 85800 | // (fma:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)<<P:Predicate_anonymous_18524>> => (S_FMAC_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2) |
| 85801 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F32), |
| 85802 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 85803 | GIR_RootConstrainSelectedInstOperands, |
| 85804 | // GIR_Coverage, 113, |
| 85805 | GIR_Done, |
| 85806 | // Label 4742: @265625 |
| 85807 | GIM_Try, /*On fail goto*//*Label 4743*/ GIMT_Encode4(265695), // Rule ID 7235 // |
| 85808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasDLInsts), |
| 85809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85813 | // (fma:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2)) => (V_FMAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2) |
| 85814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F32_e64), |
| 85815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85824 | GIR_RootConstrainSelectedInstOperands, |
| 85825 | // GIR_Coverage, 7235, |
| 85826 | GIR_EraseRootFromParent_Done, |
| 85827 | // Label 4743: @265695 |
| 85828 | GIM_Try, /*On fail goto*//*Label 4744*/ GIMT_Encode4(265772), // Rule ID 849 // |
| 85829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85833 | // (fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64), |
| 85835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85844 | GIR_RootConstrainSelectedInstOperands, |
| 85845 | // GIR_Coverage, 849, |
| 85846 | GIR_EraseRootFromParent_Done, |
| 85847 | // Label 4744: @265772 |
| 85848 | GIM_Try, /*On fail goto*//*Label 4745*/ GIMT_Encode4(265849), // Rule ID 8090 // |
| 85849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85850 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85852 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85853 | // (fma:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85854 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64), |
| 85855 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85864 | GIR_RootConstrainSelectedInstOperands, |
| 85865 | // GIR_Coverage, 8090, |
| 85866 | GIR_EraseRootFromParent_Done, |
| 85867 | // Label 4745: @265849 |
| 85868 | GIM_Reject, |
| 85869 | // Label 4735: @265850 |
| 85870 | GIM_Reject, |
| 85871 | // Label 4724: @265851 |
| 85872 | GIM_Try, /*On fail goto*//*Label 4746*/ GIMT_Encode4(266082), |
| 85873 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 85874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 85875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 85876 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 85877 | GIM_Try, /*On fail goto*//*Label 4747*/ GIMT_Encode4(265935), // Rule ID 7238 // |
| 85878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmacF64Inst), |
| 85879 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 85882 | // (fma:{ *:[f64] } (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src0), (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src1), (VOP3NoMods:{ *:[f64] } f64:{ *:[f64] }:$src2)) => (V_FMAC_F64_e64:{ *:[f64] } 0:{ *:[i32] }, ?:{ *:[f64] }:$src0, 0:{ *:[i32] }, ?:{ *:[f64] }:$src1, 0:{ *:[i32] }, ?:{ *:[f64] }:$src2) |
| 85883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMAC_F64_e64), |
| 85884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85893 | GIR_RootConstrainSelectedInstOperands, |
| 85894 | // GIR_Coverage, 7238, |
| 85895 | GIR_EraseRootFromParent_Done, |
| 85896 | // Label 4747: @265935 |
| 85897 | GIM_Try, /*On fail goto*//*Label 4748*/ GIMT_Encode4(266008), // Rule ID 852 // |
| 85898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 85900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85901 | // (fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64), |
| 85903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 85911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 85912 | GIR_RootConstrainSelectedInstOperands, |
| 85913 | // GIR_Coverage, 852, |
| 85914 | GIR_EraseRootFromParent_Done, |
| 85915 | // Label 4748: @266008 |
| 85916 | GIM_Try, /*On fail goto*//*Label 4749*/ GIMT_Encode4(266081), // Rule ID 8092 // |
| 85917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 85918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 85919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 85920 | // (fma:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 85921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64), |
| 85922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 85924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 85925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 85926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 85927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 85930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 85931 | GIR_RootConstrainSelectedInstOperands, |
| 85932 | // GIR_Coverage, 8092, |
| 85933 | GIR_EraseRootFromParent_Done, |
| 85934 | // Label 4749: @266081 |
| 85935 | GIM_Reject, |
| 85936 | // Label 4746: @266082 |
| 85937 | GIM_Reject, |
| 85938 | // Label 4725: @266083 |
| 85939 | GIM_Try, /*On fail goto*//*Label 4750*/ GIMT_Encode4(266174), // Rule ID 956 // |
| 85940 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 85941 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 85942 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 85943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 85944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85945 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85947 | // (fma:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_PK_FMA_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f16:{ *:[v2f16] }:$src2) |
| 85948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F16), |
| 85949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85961 | GIR_RootConstrainSelectedInstOperands, |
| 85962 | // GIR_Coverage, 956, |
| 85963 | GIR_EraseRootFromParent_Done, |
| 85964 | // Label 4750: @266174 |
| 85965 | GIM_Reject, |
| 85966 | // Label 4726: @266175 |
| 85967 | GIM_Try, /*On fail goto*//*Label 4751*/ GIMT_Encode4(266269), // Rule ID 1082 // |
| 85968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 85969 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 85970 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 85971 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 85972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 85973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85974 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85975 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 85976 | // (fma:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_PK_FMA_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f32:{ *:[v2f32] }:$src2) |
| 85977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F32), |
| 85978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 85979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 85980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 85981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 85982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 85983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 85984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 85985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 85990 | GIR_RootConstrainSelectedInstOperands, |
| 85991 | // GIR_Coverage, 1082, |
| 85992 | GIR_EraseRootFromParent_Done, |
| 85993 | // Label 4751: @266269 |
| 85994 | GIM_Reject, |
| 85995 | // Label 4727: @266270 |
| 85996 | GIM_Reject, |
| 85997 | // Label 64: @266271 |
| 85998 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4754*/ GIMT_Encode4(267216), |
| 85999 | /*GILLT_s16*//*Label 4752*/ GIMT_Encode4(266290), |
| 86000 | /*GILLT_s32*//*Label 4753*/ GIMT_Encode4(266528), |
| 86001 | // Label 4752: @266290 |
| 86002 | GIM_Try, /*On fail goto*//*Label 4755*/ GIMT_Encode4(266527), |
| 86003 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86004 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 86005 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 86006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86007 | GIM_Try, /*On fail goto*//*Label 4756*/ GIMT_Encode4(266374), // Rule ID 6695 // |
| 86008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 86009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86012 | // (fmad:{ *:[f16] } (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src0), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src1), (VOP3NoMods:{ *:[f16] } f16:{ *:[f16] }:$src2)) => (V_MAC_F16_e64:{ *:[f16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src0, 0:{ *:[i32] }, ?:{ *:[f16] }:$src1, 0:{ *:[i32] }, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 86013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F16_e64), |
| 86014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86021 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86023 | GIR_RootConstrainSelectedInstOperands, |
| 86024 | // GIR_Coverage, 6695, |
| 86025 | GIR_EraseRootFromParent_Done, |
| 86026 | // Label 4756: @266374 |
| 86027 | GIM_Try, /*On fail goto*//*Label 4757*/ GIMT_Encode4(266450), // Rule ID 923 // |
| 86028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 86029 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 86031 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 86032 | // (fmad:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64), |
| 86034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 86040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86043 | GIR_RootConstrainSelectedInstOperands, |
| 86044 | // GIR_Coverage, 923, |
| 86045 | GIR_EraseRootFromParent_Done, |
| 86046 | // Label 4757: @266450 |
| 86047 | GIM_Try, /*On fail goto*//*Label 4758*/ GIMT_Encode4(266526), // Rule ID 8112 // |
| 86048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts), |
| 86049 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 86050 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86051 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 86052 | // (fmad:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F16_e64), |
| 86054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 86056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 86057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 86058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 86059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 86060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 86062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 86063 | GIR_RootConstrainSelectedInstOperands, |
| 86064 | // GIR_Coverage, 8112, |
| 86065 | GIR_EraseRootFromParent_Done, |
| 86066 | // Label 4758: @266526 |
| 86067 | GIM_Reject, |
| 86068 | // Label 4755: @266527 |
| 86069 | GIM_Reject, |
| 86070 | // Label 4753: @266528 |
| 86071 | GIM_Try, /*On fail goto*//*Label 4759*/ GIMT_Encode4(267215), |
| 86072 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 86073 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 86074 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 86075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86076 | GIM_Try, /*On fail goto*//*Label 4760*/ GIMT_Encode4(266621), // Rule ID 2303 // |
| 86077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86079 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86081 | // (fmad:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 86082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 86085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 86087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86093 | GIR_RootConstrainSelectedInstOperands, |
| 86094 | // GIR_Coverage, 2303, |
| 86095 | GIR_EraseRootFromParent_Done, |
| 86096 | // Label 4760: @266621 |
| 86097 | GIM_Try, /*On fail goto*//*Label 4761*/ GIMT_Encode4(266696), // Rule ID 2304 // |
| 86098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86099 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86102 | // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }) |
| 86103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 86106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 86108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86114 | GIR_RootConstrainSelectedInstOperands, |
| 86115 | // GIR_Coverage, 2304, |
| 86116 | GIR_EraseRootFromParent_Done, |
| 86117 | // Label 4761: @266696 |
| 86118 | GIM_Try, /*On fail goto*//*Label 4762*/ GIMT_Encode4(266771), // Rule ID 2305 // |
| 86119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86121 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86122 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86123 | // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 86124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 86127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 86129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86135 | GIR_RootConstrainSelectedInstOperands, |
| 86136 | // GIR_Coverage, 2305, |
| 86137 | GIR_EraseRootFromParent_Done, |
| 86138 | // Label 4762: @266771 |
| 86139 | GIM_Try, /*On fail goto*//*Label 4763*/ GIMT_Encode4(266837), // Rule ID 6689 // |
| 86140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts), |
| 86141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_no_mods), |
| 86144 | // (fmad:{ *:[f32] } (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src0), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src1), (VOP3NoMods:{ *:[f32] } f32:{ *:[f32] }:$src2)) => (V_MAC_F32_e64:{ *:[f32] } 0:{ *:[i32] }, ?:{ *:[f32] }:$src0, 0:{ *:[i32] }, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 86145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAC_F32_e64), |
| 86146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86155 | GIR_RootConstrainSelectedInstOperands, |
| 86156 | // GIR_Coverage, 6689, |
| 86157 | GIR_EraseRootFromParent_Done, |
| 86158 | // Label 4763: @266837 |
| 86159 | GIM_Try, /*On fail goto*//*Label 4764*/ GIMT_Encode4(266912), // Rule ID 8147 // |
| 86160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86164 | // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 86165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 86168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 86169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 86170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 86171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86176 | GIR_RootConstrainSelectedInstOperands, |
| 86177 | // GIR_Coverage, 8147, |
| 86178 | GIR_EraseRootFromParent_Done, |
| 86179 | // Label 4764: @266912 |
| 86180 | GIM_Try, /*On fail goto*//*Label 4765*/ GIMT_Encode4(266987), // Rule ID 8148 // |
| 86181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86185 | // (fmad:{ *:[f32] } (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }) |
| 86186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 86189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 86190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 86191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 86192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86197 | GIR_RootConstrainSelectedInstOperands, |
| 86198 | // GIR_Coverage, 8148, |
| 86199 | GIR_EraseRootFromParent_Done, |
| 86200 | // Label 4765: @266987 |
| 86201 | GIM_Try, /*On fail goto*//*Label 4766*/ GIMT_Encode4(267062), // Rule ID 8149 // |
| 86202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 86203 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86204 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 86205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods_ext), |
| 86206 | // (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3PMadMixModsExt:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAD_MIX_F32:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }) |
| 86207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIX_F32), |
| 86208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 86210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 86211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 86212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 86213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 86214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86218 | GIR_RootConstrainSelectedInstOperands, |
| 86219 | // GIR_Coverage, 8149, |
| 86220 | GIR_EraseRootFromParent_Done, |
| 86221 | // Label 4766: @267062 |
| 86222 | GIM_Try, /*On fail goto*//*Label 4767*/ GIMT_Encode4(267138), // Rule ID 844 // |
| 86223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts), |
| 86224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86225 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 86226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 86227 | // (fmad:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64), |
| 86229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 86235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86238 | GIR_RootConstrainSelectedInstOperands, |
| 86239 | // GIR_Coverage, 844, |
| 86240 | GIR_EraseRootFromParent_Done, |
| 86241 | // Label 4767: @267138 |
| 86242 | GIM_Try, /*On fail goto*//*Label 4768*/ GIMT_Encode4(267214), // Rule ID 8087 // |
| 86243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMacF32Insts), |
| 86244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 86245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 86247 | // (fmad:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MAD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_F32_e64), |
| 86249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 86251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 86252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 86253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 86254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 86255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 86256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 86257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 86258 | GIR_RootConstrainSelectedInstOperands, |
| 86259 | // GIR_Coverage, 8087, |
| 86260 | GIR_EraseRootFromParent_Done, |
| 86261 | // Label 4768: @267214 |
| 86262 | GIM_Reject, |
| 86263 | // Label 4759: @267215 |
| 86264 | GIM_Reject, |
| 86265 | // Label 4754: @267216 |
| 86266 | GIM_Reject, |
| 86267 | // Label 65: @267217 |
| 86268 | GIM_Try, /*On fail goto*//*Label 4769*/ GIMT_Encode4(267334), // Rule ID 7073 // |
| 86269 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 86270 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 86271 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 86272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 86274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 86275 | // (fpow:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)) => (V_EXP_F32_e64:{ *:[f32] } 0:{ *:[i32] }, (V_MUL_LEGACY_F32_e64:{ *:[i16] } ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, (V_LOG_F32_e64:{ *:[i16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0), 0:{ *:[i1] }, 0:{ *:[i32] })) |
| 86276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86277 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 86278 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F32_e64), |
| 86279 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86280 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 86281 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86282 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 86283 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 86284 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 86285 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_LEGACY_F32_e64), |
| 86286 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86287 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 86288 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86289 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 86290 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 86291 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 86292 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 86293 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F32_e64), |
| 86295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86300 | GIR_RootConstrainSelectedInstOperands, |
| 86301 | // GIR_Coverage, 7073, |
| 86302 | GIR_EraseRootFromParent_Done, |
| 86303 | // Label 4769: @267334 |
| 86304 | GIM_Reject, |
| 86305 | // Label 66: @267335 |
| 86306 | GIM_Try, /*On fail goto*//*Label 4770*/ GIMT_Encode4(267557), |
| 86307 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 86308 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86309 | GIM_Try, /*On fail goto*//*Label 4771*/ GIMT_Encode4(267417), // Rule ID 2281 // |
| 86310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 86311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 86312 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24204), |
| 86313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86314 | // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24204>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_EXP_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 86315 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86316 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_EXP_F16_e64), |
| 86317 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86318 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86319 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86320 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86321 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86322 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86325 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86326 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 86327 | // GIR_Coverage, 2281, |
| 86328 | GIR_EraseRootFromParent_Done, |
| 86329 | // Label 4771: @267417 |
| 86330 | GIM_Try, /*On fail goto*//*Label 4772*/ GIMT_Encode4(267511), |
| 86331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86332 | GIM_Try, /*On fail goto*//*Label 4773*/ GIMT_Encode4(267468), // Rule ID 681 // |
| 86333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 86334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86335 | // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_EXP_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_e64), |
| 86337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86342 | GIR_RootConstrainSelectedInstOperands, |
| 86343 | // GIR_Coverage, 681, |
| 86344 | GIR_EraseRootFromParent_Done, |
| 86345 | // Label 4773: @267468 |
| 86346 | GIM_Try, /*On fail goto*//*Label 4774*/ GIMT_Encode4(267510), // Rule ID 685 // |
| 86347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 86348 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86349 | // (fexp2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_EXP_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_fake16_e64), |
| 86351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86356 | GIR_RootConstrainSelectedInstOperands, |
| 86357 | // GIR_Coverage, 685, |
| 86358 | GIR_EraseRootFromParent_Done, |
| 86359 | // Label 4774: @267510 |
| 86360 | GIM_Reject, |
| 86361 | // Label 4772: @267511 |
| 86362 | GIM_Try, /*On fail goto*//*Label 4775*/ GIMT_Encode4(267556), // Rule ID 683 // |
| 86363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 86364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 86365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 86366 | // (fexp2:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_EXP_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 86367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_EXP_F16_t16_e64), |
| 86368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86374 | GIR_RootConstrainSelectedInstOperands, |
| 86375 | // GIR_Coverage, 683, |
| 86376 | GIR_EraseRootFromParent_Done, |
| 86377 | // Label 4775: @267556 |
| 86378 | GIM_Reject, |
| 86379 | // Label 4770: @267557 |
| 86380 | GIM_Reject, |
| 86381 | // Label 67: @267558 |
| 86382 | GIM_Try, /*On fail goto*//*Label 4776*/ GIMT_Encode4(267780), |
| 86383 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 86384 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86385 | GIM_Try, /*On fail goto*//*Label 4777*/ GIMT_Encode4(267640), // Rule ID 2283 // |
| 86386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 86387 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 86388 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24206), |
| 86389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86390 | // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24206>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_LOG_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 86391 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86392 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_LOG_F16_e64), |
| 86393 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86394 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86395 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86396 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86397 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86398 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86401 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86402 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 86403 | // GIR_Coverage, 2283, |
| 86404 | GIR_EraseRootFromParent_Done, |
| 86405 | // Label 4777: @267640 |
| 86406 | GIM_Try, /*On fail goto*//*Label 4778*/ GIMT_Encode4(267734), |
| 86407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86408 | GIM_Try, /*On fail goto*//*Label 4779*/ GIMT_Encode4(267691), // Rule ID 675 // |
| 86409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 86410 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86411 | // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_e64), |
| 86413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86418 | GIR_RootConstrainSelectedInstOperands, |
| 86419 | // GIR_Coverage, 675, |
| 86420 | GIR_EraseRootFromParent_Done, |
| 86421 | // Label 4779: @267691 |
| 86422 | GIM_Try, /*On fail goto*//*Label 4780*/ GIMT_Encode4(267733), // Rule ID 679 // |
| 86423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 86424 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86425 | // (flog2:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_LOG_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_fake16_e64), |
| 86427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86432 | GIR_RootConstrainSelectedInstOperands, |
| 86433 | // GIR_Coverage, 679, |
| 86434 | GIR_EraseRootFromParent_Done, |
| 86435 | // Label 4780: @267733 |
| 86436 | GIM_Reject, |
| 86437 | // Label 4778: @267734 |
| 86438 | GIM_Try, /*On fail goto*//*Label 4781*/ GIMT_Encode4(267779), // Rule ID 677 // |
| 86439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 86440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 86441 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 86442 | // (flog2:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_LOG_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 86443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LOG_F16_t16_e64), |
| 86444 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 86450 | GIR_RootConstrainSelectedInstOperands, |
| 86451 | // GIR_Coverage, 677, |
| 86452 | GIR_EraseRootFromParent_Done, |
| 86453 | // Label 4781: @267779 |
| 86454 | GIM_Reject, |
| 86455 | // Label 4776: @267780 |
| 86456 | GIM_Reject, |
| 86457 | // Label 68: @267781 |
| 86458 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4785*/ GIMT_Encode4(268073), |
| 86459 | /*GILLT_s16*//*Label 4782*/ GIMT_Encode4(267804), |
| 86460 | /*GILLT_s32*//*Label 4783*/ GIMT_Encode4(267939), |
| 86461 | /*GILLT_s64*//*Label 4784*/ GIMT_Encode4(268006), |
| 86462 | // Label 4782: @267804 |
| 86463 | GIM_Try, /*On fail goto*//*Label 4786*/ GIMT_Encode4(267938), |
| 86464 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86465 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 86466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86467 | GIM_Try, /*On fail goto*//*Label 4787*/ GIMT_Encode4(267878), // Rule ID 2146 // |
| 86468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 86469 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86471 | // (fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod) |
| 86472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_e64), |
| 86473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86480 | GIR_RootConstrainSelectedInstOperands, |
| 86481 | // GIR_Coverage, 2146, |
| 86482 | GIR_EraseRootFromParent_Done, |
| 86483 | // Label 4787: @267878 |
| 86484 | GIM_Try, /*On fail goto*//*Label 4788*/ GIMT_Encode4(267937), // Rule ID 2148 // |
| 86485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 86486 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86488 | // (fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F16_t16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod) |
| 86489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_t16_e64), |
| 86490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86497 | GIR_RootConstrainSelectedInstOperands, |
| 86498 | // GIR_Coverage, 2148, |
| 86499 | GIR_EraseRootFromParent_Done, |
| 86500 | // Label 4788: @267937 |
| 86501 | GIM_Reject, |
| 86502 | // Label 4786: @267938 |
| 86503 | GIM_Reject, |
| 86504 | // Label 4783: @267939 |
| 86505 | GIM_Try, /*On fail goto*//*Label 4789*/ GIMT_Encode4(268005), // Rule ID 758 // |
| 86506 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 86507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 86508 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86510 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 86511 | // (fldexp:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F32_e64), |
| 86513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86520 | GIR_RootConstrainSelectedInstOperands, |
| 86521 | // GIR_Coverage, 758, |
| 86522 | GIR_EraseRootFromParent_Done, |
| 86523 | // Label 4789: @268005 |
| 86524 | GIM_Reject, |
| 86525 | // Label 4784: @268006 |
| 86526 | GIM_Try, /*On fail goto*//*Label 4790*/ GIMT_Encode4(268072), // Rule ID 899 // |
| 86527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 86528 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 86529 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 86531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 86532 | // (fldexp:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 86533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 86534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 86536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 86537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 86538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 86539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 86540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 86541 | GIR_RootConstrainSelectedInstOperands, |
| 86542 | // GIR_Coverage, 899, |
| 86543 | GIR_EraseRootFromParent_Done, |
| 86544 | // Label 4790: @268072 |
| 86545 | GIM_Reject, |
| 86546 | // Label 4785: @268073 |
| 86547 | GIM_Reject, |
| 86548 | // Label 69: @268074 |
| 86549 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4796*/ GIMT_Encode4(269942), |
| 86550 | /*GILLT_s16*//*Label 4791*/ GIMT_Encode4(268105), |
| 86551 | /*GILLT_s32*//*Label 4792*/ GIMT_Encode4(268603), |
| 86552 | /*GILLT_s64*//*Label 4793*/ GIMT_Encode4(268857), |
| 86553 | /*GILLT_v2s16*//*Label 4794*/ GIMT_Encode4(269529), |
| 86554 | /*GILLT_v2s32*//*Label 4795*/ GIMT_Encode4(269885), |
| 86555 | // Label 4791: @268105 |
| 86556 | GIM_Try, /*On fail goto*//*Label 4797*/ GIMT_Encode4(268602), |
| 86557 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 86558 | GIM_Try, /*On fail goto*//*Label 4798*/ GIMT_Encode4(268186), // Rule ID 7013 // |
| 86559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 86563 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86564 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86565 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86566 | // (fneg:{ *:[f16] } (fabs:{ *:[f16] } SReg_32:{ *:[f16] }:$src))<<P:Predicate_anonymous_35929>> => (S_OR_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] })) |
| 86567 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86568 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86569 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86570 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86571 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 86573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86576 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86577 | GIR_RootConstrainSelectedInstOperands, |
| 86578 | // GIR_Coverage, 7013, |
| 86579 | GIR_EraseRootFromParent_Done, |
| 86580 | // Label 4798: @268186 |
| 86581 | GIM_Try, /*On fail goto*//*Label 4799*/ GIMT_Encode4(268259), // Rule ID 7016 // |
| 86582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86583 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86584 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86585 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 86586 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86587 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86588 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86589 | // (fneg:{ *:[bf16] } (fabs:{ *:[bf16] } SReg_32:{ *:[bf16] }:$src))<<P:Predicate_anonymous_35929>> => (S_OR_B32:{ *:[bf16] }:{ *:[i1] } SReg_32:{ *:[bf16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] })) |
| 86590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86591 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86592 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86593 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86594 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 86596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86597 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86599 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86600 | GIR_RootConstrainSelectedInstOperands, |
| 86601 | // GIR_Coverage, 7016, |
| 86602 | GIR_EraseRootFromParent_Done, |
| 86603 | // Label 4799: @268259 |
| 86604 | GIM_Try, /*On fail goto*//*Label 4800*/ GIMT_Encode4(268325), // Rule ID 7032 // |
| 86605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86606 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86607 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86608 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 86609 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86610 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86611 | // (fneg:{ *:[f16] } (fabs:{ *:[f16] } VGPR_32:{ *:[f16] }:$src)) => (V_OR_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src) |
| 86612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86615 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86616 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 86618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86620 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86621 | GIR_RootConstrainSelectedInstOperands, |
| 86622 | // GIR_Coverage, 7032, |
| 86623 | GIR_EraseRootFromParent_Done, |
| 86624 | // Label 4800: @268325 |
| 86625 | GIM_Try, /*On fail goto*//*Label 4801*/ GIMT_Encode4(268391), // Rule ID 7035 // |
| 86626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86628 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86629 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 86630 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86631 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86632 | // (fneg:{ *:[bf16] } (fabs:{ *:[bf16] } VGPR_32:{ *:[bf16] }:$src)) => (V_OR_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[bf16] }:$src) |
| 86633 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86634 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86635 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86636 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86637 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 86639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86640 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86642 | GIR_RootConstrainSelectedInstOperands, |
| 86643 | // GIR_Coverage, 7035, |
| 86644 | GIR_EraseRootFromParent_Done, |
| 86645 | // Label 4801: @268391 |
| 86646 | GIM_Try, /*On fail goto*//*Label 4802*/ GIMT_Encode4(268447), // Rule ID 7011 // |
| 86647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86648 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86649 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86650 | // (fneg:{ *:[f16] } SReg_32:{ *:[f16] }:$src)<<P:Predicate_anonymous_35929>> => (S_XOR_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] })) |
| 86651 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86652 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86653 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86654 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86655 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 86657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86658 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86660 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86661 | GIR_RootConstrainSelectedInstOperands, |
| 86662 | // GIR_Coverage, 7011, |
| 86663 | GIR_EraseRootFromParent_Done, |
| 86664 | // Label 4802: @268447 |
| 86665 | GIM_Try, /*On fail goto*//*Label 4803*/ GIMT_Encode4(268503), // Rule ID 7014 // |
| 86666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86667 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86668 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86669 | // (fneg:{ *:[bf16] } SReg_32:{ *:[bf16] }:$src)<<P:Predicate_anonymous_35929>> => (S_XOR_B32:{ *:[bf16] }:{ *:[i1] } SReg_32:{ *:[bf16] }:$src, (S_MOV_B32:{ *:[i1] } 32768:{ *:[i32] })) |
| 86670 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86671 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86672 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86673 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86674 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 86676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86677 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86679 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86680 | GIR_RootConstrainSelectedInstOperands, |
| 86681 | // GIR_Coverage, 7014, |
| 86682 | GIR_EraseRootFromParent_Done, |
| 86683 | // Label 4803: @268503 |
| 86684 | GIM_Try, /*On fail goto*//*Label 4804*/ GIMT_Encode4(268552), // Rule ID 7031 // |
| 86685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86686 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86687 | // (fneg:{ *:[f16] } VGPR_32:{ *:[f16] }:$src) => (V_XOR_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src) |
| 86688 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86689 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86690 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86691 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86692 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 86694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86695 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86696 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86697 | GIR_RootConstrainSelectedInstOperands, |
| 86698 | // GIR_Coverage, 7031, |
| 86699 | GIR_EraseRootFromParent_Done, |
| 86700 | // Label 4804: @268552 |
| 86701 | GIM_Try, /*On fail goto*//*Label 4805*/ GIMT_Encode4(268601), // Rule ID 7034 // |
| 86702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86703 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86704 | // (fneg:{ *:[bf16] } VGPR_32:{ *:[bf16] }:$src) => (V_XOR_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32768:{ *:[i32] }), VGPR_32:{ *:[bf16] }:$src) |
| 86705 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86706 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86707 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86708 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32768), |
| 86709 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 86711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86713 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86714 | GIR_RootConstrainSelectedInstOperands, |
| 86715 | // GIR_Coverage, 7034, |
| 86716 | GIR_EraseRootFromParent_Done, |
| 86717 | // Label 4805: @268601 |
| 86718 | GIM_Reject, |
| 86719 | // Label 4797: @268602 |
| 86720 | GIM_Reject, |
| 86721 | // Label 4792: @268603 |
| 86722 | GIM_Try, /*On fail goto*//*Label 4806*/ GIMT_Encode4(268856), |
| 86723 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 86724 | GIM_Try, /*On fail goto*//*Label 4807*/ GIMT_Encode4(268684), // Rule ID 7008 // |
| 86725 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86726 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86727 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86728 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 86729 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86730 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86731 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86732 | // (fneg:{ *:[f32] } (fabs:{ *:[f32] } SReg_32:{ *:[f32] }:$src))<<P:Predicate_anonymous_35929>> => (S_OR_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483648:{ *:[i32] })) |
| 86733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86736 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648), |
| 86737 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 86739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86741 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86742 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86743 | GIR_RootConstrainSelectedInstOperands, |
| 86744 | // GIR_Coverage, 7008, |
| 86745 | GIR_EraseRootFromParent_Done, |
| 86746 | // Label 4807: @268684 |
| 86747 | GIM_Try, /*On fail goto*//*Label 4808*/ GIMT_Encode4(268750), // Rule ID 7027 // |
| 86748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86749 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86750 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86751 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 86752 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86753 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86754 | // (fneg:{ *:[f32] } (fabs:{ *:[f32] } VGPR_32:{ *:[f32] }:$src)) => (V_OR_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483648:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src) |
| 86755 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86756 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86757 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86758 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648), |
| 86759 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 86761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86762 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 86764 | GIR_RootConstrainSelectedInstOperands, |
| 86765 | // GIR_Coverage, 7027, |
| 86766 | GIR_EraseRootFromParent_Done, |
| 86767 | // Label 4808: @268750 |
| 86768 | GIM_Try, /*On fail goto*//*Label 4809*/ GIMT_Encode4(268806), // Rule ID 7010 // |
| 86769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86770 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86771 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86772 | // (fneg:{ *:[f32] } SReg_32:{ *:[f32] }:$src)<<P:Predicate_anonymous_35929>> => (S_XOR_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483648:{ *:[i32] })) |
| 86773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 86774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86776 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648), |
| 86777 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 86779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 86780 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86781 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86782 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 86783 | GIR_RootConstrainSelectedInstOperands, |
| 86784 | // GIR_Coverage, 7010, |
| 86785 | GIR_EraseRootFromParent_Done, |
| 86786 | // Label 4809: @268806 |
| 86787 | GIM_Try, /*On fail goto*//*Label 4810*/ GIMT_Encode4(268855), // Rule ID 7029 // |
| 86788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86789 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86790 | // (fneg:{ *:[f32] } VGPR_32:{ *:[f32] }:$src) => (V_XOR_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483648:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src) |
| 86791 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 86792 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86793 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86794 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483648), |
| 86795 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 86796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 86797 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 86798 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86799 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 86800 | GIR_RootConstrainSelectedInstOperands, |
| 86801 | // GIR_Coverage, 7029, |
| 86802 | GIR_EraseRootFromParent_Done, |
| 86803 | // Label 4810: @268855 |
| 86804 | GIM_Reject, |
| 86805 | // Label 4806: @268856 |
| 86806 | GIM_Reject, |
| 86807 | // Label 4793: @268857 |
| 86808 | GIM_Try, /*On fail goto*//*Label 4811*/ GIMT_Encode4(269528), |
| 86809 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 86810 | GIM_Try, /*On fail goto*//*Label 4812*/ GIMT_Encode4(269050), // Rule ID 7026 // |
| 86811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 86815 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86816 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86817 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86818 | // (fneg:{ *:[f64] } (fabs:{ *:[f64] } SReg_64:{ *:[f64] }:$src))<<P:Predicate_anonymous_35929>> => (REG_SEQUENCE:{ *:[f64] } SReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_OR_B32:{ *:[i1] }:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] }), (S_MOV_B32:{ *:[i1] } 2147483648:{ *:[i32] })), SReg_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 86819 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86820 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 86821 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 86822 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 86823 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1, |
| 86824 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86825 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86826 | GIR_AddImm, /*InsnID*/5, /*Imm*/GIMT_Encode8(2147483648), |
| 86827 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 86828 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86829 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86830 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 86831 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 86832 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86833 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 86834 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86835 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 86836 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 86837 | GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0, |
| 86838 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 86839 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86840 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86841 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 86842 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 86843 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86844 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86845 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 86846 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 86847 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 86849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86850 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86851 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 86852 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 86853 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 86854 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86855 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 86856 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 86857 | // GIR_Coverage, 7026, |
| 86858 | GIR_EraseRootFromParent_Done, |
| 86859 | // Label 4812: @269050 |
| 86860 | GIM_Try, /*On fail goto*//*Label 4813*/ GIMT_Encode4(269211), // Rule ID 7041 // |
| 86861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86862 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86863 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 86864 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 86865 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86866 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 86867 | // (fneg:{ *:[f64] } (fabs:{ *:[f64] } VReg_64:{ *:[f64] }:$src)) => (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_OR_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483648:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 86868 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86869 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 86870 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 86871 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 86872 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86873 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86874 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 86875 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86876 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86877 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86878 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86879 | GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483648), |
| 86880 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 86881 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 86882 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86883 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 86884 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 86885 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 86886 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86887 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86888 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/1, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 86889 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86890 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 86892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86893 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86894 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 86895 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 86896 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 86897 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86898 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86899 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86900 | // GIR_Coverage, 7041, |
| 86901 | GIR_EraseRootFromParent_Done, |
| 86902 | // Label 4813: @269211 |
| 86903 | GIM_Try, /*On fail goto*//*Label 4814*/ GIMT_Encode4(269381), // Rule ID 7025 // |
| 86904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86905 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86906 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 86907 | // (fneg:{ *:[f64] } SReg_64:{ *:[f64] }:$src)<<P:Predicate_anonymous_35929>> => (REG_SEQUENCE:{ *:[f64] } SReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_XOR_B32:{ *:[i1] }:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] }), (S_MOV_B32:{ *:[i32] } 2147483648:{ *:[i32] })), SReg_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 86908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86909 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 86910 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 86911 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 86912 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 86913 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86914 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86915 | GIR_AddImm, /*InsnID*/5, /*Imm*/GIMT_Encode8(2147483648), |
| 86916 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 86917 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86918 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86919 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 86920 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 86921 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86922 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 86923 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86924 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 86925 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 86926 | GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0, |
| 86927 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 86928 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86929 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86930 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 86931 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 86932 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86933 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86934 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 86935 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 86936 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 86938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86940 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 86941 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 86942 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 86943 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 86944 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 86945 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 86946 | // GIR_Coverage, 7025, |
| 86947 | GIR_EraseRootFromParent_Done, |
| 86948 | // Label 4814: @269381 |
| 86949 | GIM_Try, /*On fail goto*//*Label 4815*/ GIMT_Encode4(269527), // Rule ID 7040 // |
| 86950 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86951 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86952 | // (fneg:{ *:[f64] } VReg_64:{ *:[f64] }:$src) => (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_XOR_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483648:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 86953 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 86954 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 86955 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 86956 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 86957 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86958 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86959 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 86960 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86961 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86962 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 86963 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86964 | GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483648), |
| 86965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 86966 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 86967 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86968 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 86969 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 86970 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 86971 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 86972 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 86973 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 86974 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86975 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86976 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 86977 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 86978 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 86979 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 86980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 86981 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 86982 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 86983 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86984 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 86985 | // GIR_Coverage, 7040, |
| 86986 | GIR_EraseRootFromParent_Done, |
| 86987 | // Label 4815: @269527 |
| 86988 | GIM_Reject, |
| 86989 | // Label 4811: @269528 |
| 86990 | GIM_Reject, |
| 86991 | // Label 4794: @269529 |
| 86992 | GIM_Try, /*On fail goto*//*Label 4816*/ GIMT_Encode4(269884), |
| 86993 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 86994 | GIM_Try, /*On fail goto*//*Label 4817*/ GIMT_Encode4(269639), // Rule ID 7019 // |
| 86995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 86996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 86997 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BITCAST), |
| 86998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 86999 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 87000 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_AND), |
| 87001 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 87002 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 87003 | GIM_CheckHasOneUse, /*MI*/2, |
| 87004 | GIM_CheckRegBankForClass, /*MI*/2, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87005 | GIM_CheckConstantInt, /*MI*/2, /*Op*/2, GIMT_Encode8(2147450879), |
| 87006 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 87007 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 87008 | // (fneg:{ *:[v2f16] } (bitconvert:{ *:[v2f16] } (and:{ *:[i32] } SReg_32:{ *:[i32] }:$src, 2147450879:{ *:[i32] })<<P:Predicate_and_oneuse>>))<<P:Predicate_anonymous_35929>> => (S_OR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[i32] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] })) |
| 87009 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 87010 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 87011 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87012 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416), |
| 87013 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 87015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src |
| 87017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87018 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 87019 | GIR_RootConstrainSelectedInstOperands, |
| 87020 | // GIR_Coverage, 7019, |
| 87021 | GIR_EraseRootFromParent_Done, |
| 87022 | // Label 4817: @269639 |
| 87023 | GIM_Try, /*On fail goto*//*Label 4818*/ GIMT_Encode4(269712), // Rule ID 7020 // |
| 87024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87025 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87026 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 87027 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 87028 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87029 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 87030 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87031 | // (fneg:{ *:[v2f16] } (fabs:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src))<<P:Predicate_anonymous_35929>> => (S_OR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] })) |
| 87032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 87033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 87034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87035 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416), |
| 87036 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_OR_B32), |
| 87038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87039 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 87040 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87041 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 87042 | GIR_RootConstrainSelectedInstOperands, |
| 87043 | // GIR_Coverage, 7020, |
| 87044 | GIR_EraseRootFromParent_Done, |
| 87045 | // Label 4818: @269712 |
| 87046 | GIM_Try, /*On fail goto*//*Label 4819*/ GIMT_Encode4(269778), // Rule ID 7038 // |
| 87047 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87048 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87049 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 87050 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_v2s16, |
| 87051 | GIM_CheckRegBankForClass, /*MI*/1, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87052 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87053 | // (fneg:{ *:[v2f16] } (fabs:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src)) => (V_OR_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147516416:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src) |
| 87054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 87056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87057 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416), |
| 87058 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_OR_B32_e64), |
| 87060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87061 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src |
| 87063 | GIR_RootConstrainSelectedInstOperands, |
| 87064 | // GIR_Coverage, 7038, |
| 87065 | GIR_EraseRootFromParent_Done, |
| 87066 | // Label 4819: @269778 |
| 87067 | GIM_Try, /*On fail goto*//*Label 4820*/ GIMT_Encode4(269834), // Rule ID 7017 // |
| 87068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87069 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87070 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35929), |
| 87071 | // (fneg:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src)<<P:Predicate_anonymous_35929>> => (S_XOR_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147516416:{ *:[i32] })) |
| 87072 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 87073 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 87074 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87075 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416), |
| 87076 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_XOR_B32), |
| 87078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87079 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 87080 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87081 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 87082 | GIR_RootConstrainSelectedInstOperands, |
| 87083 | // GIR_Coverage, 7017, |
| 87084 | GIR_EraseRootFromParent_Done, |
| 87085 | // Label 4820: @269834 |
| 87086 | GIM_Try, /*On fail goto*//*Label 4821*/ GIMT_Encode4(269883), // Rule ID 7036 // |
| 87087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87088 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87089 | // (fneg:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src) => (V_XOR_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147516416:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src) |
| 87090 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87091 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 87092 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87093 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147516416), |
| 87094 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_XOR_B32_e64), |
| 87096 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87097 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87098 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 87099 | GIR_RootConstrainSelectedInstOperands, |
| 87100 | // GIR_Coverage, 7036, |
| 87101 | GIR_EraseRootFromParent_Done, |
| 87102 | // Label 4821: @269883 |
| 87103 | GIM_Reject, |
| 87104 | // Label 4816: @269884 |
| 87105 | GIM_Reject, |
| 87106 | // Label 4795: @269885 |
| 87107 | GIM_Try, /*On fail goto*//*Label 4822*/ GIMT_Encode4(269941), // Rule ID 7042 // |
| 87108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 87109 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 87110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87111 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87112 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35965), |
| 87113 | // (fneg:{ *:[v2f32] } VReg_64:{ *:[v2f32] }:$src)<<P:Predicate_anonymous_35965>> => (V_PK_ADD_F32:{ *:[v2f32] } 11:{ *:[i32] }, VReg_64:{ *:[v2f32] }:$src, 11:{ *:[i32] }, 0:{ *:[i64] }, 0:{ *:[i1] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }) |
| 87114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32), |
| 87115 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 87117 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 87118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/11, |
| 87119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87125 | GIR_RootConstrainSelectedInstOperands, |
| 87126 | // GIR_Coverage, 7042, |
| 87127 | GIR_EraseRootFromParent_Done, |
| 87128 | // Label 4822: @269941 |
| 87129 | GIM_Reject, |
| 87130 | // Label 4796: @269942 |
| 87131 | GIM_Reject, |
| 87132 | // Label 70: @269943 |
| 87133 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 4825*/ GIMT_Encode4(270242), |
| 87134 | /*GILLT_s32*//*Label 4823*/ GIMT_Encode4(269962), |
| 87135 | /*GILLT_s64*//*Label 4824*/ GIMT_Encode4(270091), |
| 87136 | // Label 4823: @269962 |
| 87137 | GIM_Try, /*On fail goto*//*Label 4826*/ GIMT_Encode4(270090), |
| 87138 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87139 | GIM_Try, /*On fail goto*//*Label 4827*/ GIMT_Encode4(269997), // Rule ID 31 // |
| 87140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 87141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18491), |
| 87143 | // (fpextend:{ *:[f32] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_18491>> => (S_CVT_F32_F16:{ *:[f32] } f16:{ *:[f16] }:$src0) |
| 87144 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_F16), |
| 87145 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 87146 | GIR_RootConstrainSelectedInstOperands, |
| 87147 | // GIR_Coverage, 31, |
| 87148 | GIR_Done, |
| 87149 | // Label 4827: @269997 |
| 87150 | GIM_Try, /*On fail goto*//*Label 4828*/ GIMT_Encode4(270043), // Rule ID 589 // |
| 87151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87154 | // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64), |
| 87156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87161 | GIR_RootConstrainSelectedInstOperands, |
| 87162 | // GIR_Coverage, 589, |
| 87163 | GIR_EraseRootFromParent_Done, |
| 87164 | // Label 4828: @270043 |
| 87165 | GIM_Try, /*On fail goto*//*Label 4829*/ GIMT_Encode4(270089), // Rule ID 591 // |
| 87166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87168 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87169 | // (fpextend:{ *:[f32] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_F16_t16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87170 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64), |
| 87171 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87176 | GIR_RootConstrainSelectedInstOperands, |
| 87177 | // GIR_Coverage, 591, |
| 87178 | GIR_EraseRootFromParent_Done, |
| 87179 | // Label 4829: @270089 |
| 87180 | GIM_Reject, |
| 87181 | // Label 4826: @270090 |
| 87182 | GIM_Reject, |
| 87183 | // Label 4824: @270091 |
| 87184 | GIM_Try, /*On fail goto*//*Label 4830*/ GIMT_Encode4(270143), // Rule ID 6668 // |
| 87185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87186 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87188 | // (fpextend:{ *:[f64] } f16:{ *:[f16] }:$src) => (V_CVT_F64_F32_e32:{ *:[f64] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src)) |
| 87189 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87190 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64), |
| 87191 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87192 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87193 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87194 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87195 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87196 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e32), |
| 87198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87199 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87200 | GIR_RootConstrainSelectedInstOperands, |
| 87201 | // GIR_Coverage, 6668, |
| 87202 | GIR_EraseRootFromParent_Done, |
| 87203 | // Label 4830: @270143 |
| 87204 | GIM_Try, /*On fail goto*//*Label 4831*/ GIMT_Encode4(270195), // Rule ID 6682 // |
| 87205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87207 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87208 | // (fpextend:{ *:[f64] } f16:{ *:[f16] }:$src) => (V_CVT_F64_F32_e32:{ *:[f64] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[f16] }:$src)) |
| 87209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87210 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64), |
| 87211 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87212 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87213 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87214 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87215 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87216 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e32), |
| 87218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87219 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87220 | GIR_RootConstrainSelectedInstOperands, |
| 87221 | // GIR_Coverage, 6682, |
| 87222 | GIR_EraseRootFromParent_Done, |
| 87223 | // Label 4831: @270195 |
| 87224 | GIM_Try, /*On fail goto*//*Label 4832*/ GIMT_Encode4(270241), // Rule ID 577 // |
| 87225 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87228 | // (fpextend:{ *:[f64] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F64_F32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87229 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_F32_e64), |
| 87230 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87235 | GIR_RootConstrainSelectedInstOperands, |
| 87236 | // GIR_Coverage, 577, |
| 87237 | GIR_EraseRootFromParent_Done, |
| 87238 | // Label 4832: @270241 |
| 87239 | GIM_Reject, |
| 87240 | // Label 4825: @270242 |
| 87241 | GIM_Reject, |
| 87242 | // Label 71: @270243 |
| 87243 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4835*/ GIMT_Encode4(270880), |
| 87244 | /*GILLT_s16*//*Label 4833*/ GIMT_Encode4(270262), |
| 87245 | /*GILLT_s32*//*Label 4834*/ GIMT_Encode4(270833), |
| 87246 | // Label 4833: @270262 |
| 87247 | GIM_Try, /*On fail goto*//*Label 4836*/ GIMT_Encode4(270832), |
| 87248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87249 | GIM_Try, /*On fail goto*//*Label 4837*/ GIMT_Encode4(270388), // Rule ID 2315 // |
| 87250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 87251 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87252 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87253 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMA), |
| 87254 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 87255 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 87256 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 87257 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87258 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87259 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87260 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87261 | // (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))) => (V_FMA_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })) |
| 87262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 87263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16), |
| 87267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 87271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 87272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 87273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 87274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87275 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87278 | GIR_RootConstrainSelectedInstOperands, |
| 87279 | // GIR_Coverage, 2315, |
| 87280 | GIR_EraseRootFromParent_Done, |
| 87281 | // Label 4837: @270388 |
| 87282 | GIM_Try, /*On fail goto*//*Label 4838*/ GIMT_Encode4(270506), // Rule ID 2306 // |
| 87283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 87284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87285 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87286 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAD), |
| 87287 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 87288 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 87289 | GIM_CheckType, /*MI*/1, /*Op*/3, /*Type*/GILLT_s32, |
| 87290 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87291 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87292 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87293 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87294 | // (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers))) => (V_MAD_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_modifiers, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })) |
| 87295 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 87296 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87297 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87298 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16), |
| 87300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 87304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 87305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 87306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 87307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87308 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87311 | GIR_RootConstrainSelectedInstOperands, |
| 87312 | // GIR_Coverage, 2306, |
| 87313 | GIR_EraseRootFromParent_Done, |
| 87314 | // Label 4838: @270506 |
| 87315 | GIM_Try, /*On fail goto*//*Label 4839*/ GIMT_Encode4(270609), // Rule ID 2310 // |
| 87316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 87317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 87320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 87321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 87322 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87323 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87324 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87325 | // (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))) => (V_MAD_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })) |
| 87326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 87327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16), |
| 87331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 87335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 87336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87339 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87342 | GIR_RootConstrainSelectedInstOperands, |
| 87343 | // GIR_Coverage, 2310, |
| 87344 | GIR_EraseRootFromParent_Done, |
| 87345 | // Label 4839: @270609 |
| 87346 | GIM_Try, /*On fail goto*//*Label 4840*/ GIMT_Encode4(270712), // Rule ID 2319 // |
| 87347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 87348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 87350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMUL), |
| 87351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 87352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 87353 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 87354 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87355 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 87356 | // (fpround:{ *:[f16] } (fmul:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))) => (V_FMA_MIXLO_F16:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f32] }:$src1, 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] })) |
| 87357 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 87358 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 87359 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87360 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16), |
| 87362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 87366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 87367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87373 | GIR_RootConstrainSelectedInstOperands, |
| 87374 | // GIR_Coverage, 2319, |
| 87375 | GIR_EraseRootFromParent_Done, |
| 87376 | // Label 4840: @270712 |
| 87377 | GIM_Try, /*On fail goto*//*Label 4841*/ GIMT_Encode4(270739), // Rule ID 36 // |
| 87378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 87379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87380 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18496), |
| 87381 | // (fpround:{ *:[f16] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18496>> => (S_CVT_F16_F32:{ *:[f16] } f32:{ *:[f32] }:$src0) |
| 87382 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F16_F32), |
| 87383 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 87384 | GIR_RootConstrainSelectedInstOperands, |
| 87385 | // GIR_Coverage, 36, |
| 87386 | GIR_Done, |
| 87387 | // Label 4841: @270739 |
| 87388 | GIM_Try, /*On fail goto*//*Label 4842*/ GIMT_Encode4(270785), // Rule ID 585 // |
| 87389 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87391 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87392 | // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_F32_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64), |
| 87394 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87399 | GIR_RootConstrainSelectedInstOperands, |
| 87400 | // GIR_Coverage, 585, |
| 87401 | GIR_EraseRootFromParent_Done, |
| 87402 | // Label 4842: @270785 |
| 87403 | GIM_Try, /*On fail goto*//*Label 4843*/ GIMT_Encode4(270831), // Rule ID 587 // |
| 87404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87407 | // (fpround:{ *:[f16] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_F32_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64), |
| 87409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87414 | GIR_RootConstrainSelectedInstOperands, |
| 87415 | // GIR_Coverage, 587, |
| 87416 | GIR_EraseRootFromParent_Done, |
| 87417 | // Label 4843: @270831 |
| 87418 | GIM_Reject, |
| 87419 | // Label 4836: @270832 |
| 87420 | GIM_Reject, |
| 87421 | // Label 4834: @270833 |
| 87422 | GIM_Try, /*On fail goto*//*Label 4844*/ GIMT_Encode4(270879), // Rule ID 575 // |
| 87423 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87426 | // (fpround:{ *:[f32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_F64_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F64_e64), |
| 87428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87433 | GIR_RootConstrainSelectedInstOperands, |
| 87434 | // GIR_Coverage, 575, |
| 87435 | GIR_EraseRootFromParent_Done, |
| 87436 | // Label 4844: @270879 |
| 87437 | GIM_Reject, |
| 87438 | // Label 4835: @270880 |
| 87439 | GIM_Reject, |
| 87440 | // Label 72: @270881 |
| 87441 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(10), /*)*//*default:*//*Label 4848*/ GIMT_Encode4(271444), |
| 87442 | /*GILLT_s1*//*Label 4845*/ GIMT_Encode4(270904), |
| 87443 | /*GILLT_s16*//*Label 4846*/ GIMT_Encode4(271119), |
| 87444 | /*GILLT_s32*//*Label 4847*/ GIMT_Encode4(271217), |
| 87445 | // Label 4845: @270904 |
| 87446 | GIM_Try, /*On fail goto*//*Label 4849*/ GIMT_Encode4(270959), // Rule ID 7156 // |
| 87447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87448 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87450 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87451 | // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F16_e64:{ *:[i1] } 0:{ *:[i32] }, 48128:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] }) |
| 87452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64), |
| 87453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87455 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128), |
| 87456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87458 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87459 | GIR_RootConstrainSelectedInstOperands, |
| 87460 | // GIR_Coverage, 7156, |
| 87461 | GIR_EraseRootFromParent_Done, |
| 87462 | // Label 4849: @270959 |
| 87463 | GIM_Try, /*On fail goto*//*Label 4850*/ GIMT_Encode4(271014), // Rule ID 7158 // |
| 87464 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87465 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87468 | // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, 48128:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] }) |
| 87469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64), |
| 87470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87472 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128), |
| 87473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87476 | GIR_RootConstrainSelectedInstOperands, |
| 87477 | // GIR_Coverage, 7158, |
| 87478 | GIR_EraseRootFromParent_Done, |
| 87479 | // Label 4850: @271014 |
| 87480 | GIM_Try, /*On fail goto*//*Label 4851*/ GIMT_Encode4(271066), // Rule ID 7160 // |
| 87481 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87482 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87484 | // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] }) |
| 87485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64), |
| 87486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87488 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864), |
| 87489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87492 | GIR_RootConstrainSelectedInstOperands, |
| 87493 | // GIR_Coverage, 7160, |
| 87494 | GIR_EraseRootFromParent_Done, |
| 87495 | // Label 4851: @271066 |
| 87496 | GIM_Try, /*On fail goto*//*Label 4852*/ GIMT_Encode4(271118), // Rule ID 7162 // |
| 87497 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87500 | // (fp_to_sint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, -4616189618054758400:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] }) |
| 87501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64), |
| 87502 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87504 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(-4616189618054758400), |
| 87505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87508 | GIR_RootConstrainSelectedInstOperands, |
| 87509 | // GIR_Coverage, 7162, |
| 87510 | GIR_EraseRootFromParent_Done, |
| 87511 | // Label 4852: @271118 |
| 87512 | GIM_Reject, |
| 87513 | // Label 4846: @271119 |
| 87514 | GIM_Try, /*On fail goto*//*Label 4853*/ GIMT_Encode4(271216), |
| 87515 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87517 | GIM_Try, /*On fail goto*//*Label 4854*/ GIMT_Encode4(271173), // Rule ID 653 // |
| 87518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 87519 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87520 | // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_I16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I16_F16_e64), |
| 87522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87527 | GIR_RootConstrainSelectedInstOperands, |
| 87528 | // GIR_Coverage, 653, |
| 87529 | GIR_EraseRootFromParent_Done, |
| 87530 | // Label 4854: @271173 |
| 87531 | GIM_Try, /*On fail goto*//*Label 4855*/ GIMT_Encode4(271215), // Rule ID 655 // |
| 87532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87534 | // (fp_to_sint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_I16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I16_F16_t16_e64), |
| 87536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87541 | GIR_RootConstrainSelectedInstOperands, |
| 87542 | // GIR_Coverage, 655, |
| 87543 | GIR_EraseRootFromParent_Done, |
| 87544 | // Label 4855: @271215 |
| 87545 | GIM_Reject, |
| 87546 | // Label 4853: @271216 |
| 87547 | GIM_Reject, |
| 87548 | // Label 4847: @271217 |
| 87549 | GIM_Try, /*On fail goto*//*Label 4856*/ GIMT_Encode4(271247), // Rule ID 29 // |
| 87550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 87551 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87553 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18489), |
| 87554 | // (fp_to_sint:{ *:[i32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18489>> => (S_CVT_I32_F32:{ *:[i32] } f32:{ *:[f32] }:$src0) |
| 87555 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_I32_F32), |
| 87556 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 87557 | GIR_RootConstrainSelectedInstOperands, |
| 87558 | // GIR_Coverage, 29, |
| 87559 | GIR_Done, |
| 87560 | // Label 4856: @271247 |
| 87561 | GIM_Try, /*On fail goto*//*Label 4857*/ GIMT_Encode4(271299), // Rule ID 6670 // |
| 87562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87565 | // (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$src) => (V_CVT_I32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src)) |
| 87566 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87567 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64), |
| 87568 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87569 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87570 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87571 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87572 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87573 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e32), |
| 87575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87576 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87577 | GIR_RootConstrainSelectedInstOperands, |
| 87578 | // GIR_Coverage, 6670, |
| 87579 | GIR_EraseRootFromParent_Done, |
| 87580 | // Label 4857: @271299 |
| 87581 | GIM_Try, /*On fail goto*//*Label 4858*/ GIMT_Encode4(271351), // Rule ID 6684 // |
| 87582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87585 | // (fp_to_sint:{ *:[i32] } f16:{ *:[f16] }:$src) => (V_CVT_I32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src)) |
| 87586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64), |
| 87588 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87589 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87590 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87591 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87592 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87593 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e32), |
| 87595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87597 | GIR_RootConstrainSelectedInstOperands, |
| 87598 | // GIR_Coverage, 6684, |
| 87599 | GIR_EraseRootFromParent_Done, |
| 87600 | // Label 4858: @271351 |
| 87601 | GIM_Try, /*On fail goto*//*Label 4859*/ GIMT_Encode4(271397), // Rule ID 573 // |
| 87602 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87605 | // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_I32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F64_e64), |
| 87607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87612 | GIR_RootConstrainSelectedInstOperands, |
| 87613 | // GIR_Coverage, 573, |
| 87614 | GIR_EraseRootFromParent_Done, |
| 87615 | // Label 4859: @271397 |
| 87616 | GIM_Try, /*On fail goto*//*Label 4860*/ GIMT_Encode4(271443), // Rule ID 583 // |
| 87617 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87619 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87620 | // (fp_to_sint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_I32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_I32_F32_e64), |
| 87622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87627 | GIR_RootConstrainSelectedInstOperands, |
| 87628 | // GIR_Coverage, 583, |
| 87629 | GIR_EraseRootFromParent_Done, |
| 87630 | // Label 4860: @271443 |
| 87631 | GIM_Reject, |
| 87632 | // Label 4848: @271444 |
| 87633 | GIM_Reject, |
| 87634 | // Label 73: @271445 |
| 87635 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(7), GIMT_Encode2(10), /*)*//*default:*//*Label 4864*/ GIMT_Encode4(272008), |
| 87636 | /*GILLT_s1*//*Label 4861*/ GIMT_Encode4(271468), |
| 87637 | /*GILLT_s16*//*Label 4862*/ GIMT_Encode4(271683), |
| 87638 | /*GILLT_s32*//*Label 4863*/ GIMT_Encode4(271781), |
| 87639 | // Label 4861: @271468 |
| 87640 | GIM_Try, /*On fail goto*//*Label 4865*/ GIMT_Encode4(271523), // Rule ID 7155 // |
| 87641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87642 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87644 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87645 | // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F16_e64:{ *:[i1] } 0:{ *:[i32] }, 15360:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] }) |
| 87646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_e64), |
| 87647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87649 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360), |
| 87650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87653 | GIR_RootConstrainSelectedInstOperands, |
| 87654 | // GIR_Coverage, 7155, |
| 87655 | GIR_EraseRootFromParent_Done, |
| 87656 | // Label 4865: @271523 |
| 87657 | GIM_Try, /*On fail goto*//*Label 4866*/ GIMT_Encode4(271578), // Rule ID 7157 // |
| 87658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87659 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87662 | // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F16_t16_e64:{ *:[i1] } 0:{ *:[i32] }, 15360:{ *:[i16] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, 0:{ *:[i1] }) |
| 87663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F16_t16_e64), |
| 87664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87666 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360), |
| 87667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87670 | GIR_RootConstrainSelectedInstOperands, |
| 87671 | // GIR_Coverage, 7157, |
| 87672 | GIR_EraseRootFromParent_Done, |
| 87673 | // Label 4866: @271578 |
| 87674 | GIM_Try, /*On fail goto*//*Label 4867*/ GIMT_Encode4(271630), // Rule ID 7159 // |
| 87675 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87677 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87678 | // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F32_e64:{ *:[i1] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f32] }:$src0, 0:{ *:[i1] }) |
| 87679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F32_e64), |
| 87680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87682 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216), |
| 87683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87686 | GIR_RootConstrainSelectedInstOperands, |
| 87687 | // GIR_Coverage, 7159, |
| 87688 | GIR_EraseRootFromParent_Done, |
| 87689 | // Label 4867: @271630 |
| 87690 | GIM_Try, /*On fail goto*//*Label 4868*/ GIMT_Encode4(271682), // Rule ID 7161 // |
| 87691 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 87693 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 87694 | // (fp_to_uint:{ *:[i1] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CMP_EQ_F64_e64:{ *:[i1] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f64] }:$src0, 0:{ *:[i1] }) |
| 87695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_EQ_F64_e64), |
| 87696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 87697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87698 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(4607182418800017408), |
| 87699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87702 | GIR_RootConstrainSelectedInstOperands, |
| 87703 | // GIR_Coverage, 7161, |
| 87704 | GIR_EraseRootFromParent_Done, |
| 87705 | // Label 4868: @271682 |
| 87706 | GIM_Reject, |
| 87707 | // Label 4862: @271683 |
| 87708 | GIM_Try, /*On fail goto*//*Label 4869*/ GIMT_Encode4(271780), |
| 87709 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87711 | GIM_Try, /*On fail goto*//*Label 4870*/ GIMT_Encode4(271737), // Rule ID 652 // |
| 87712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 87713 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87714 | // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_U16_F16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U16_F16_e64), |
| 87716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87721 | GIR_RootConstrainSelectedInstOperands, |
| 87722 | // GIR_Coverage, 652, |
| 87723 | GIR_EraseRootFromParent_Done, |
| 87724 | // Label 4870: @271737 |
| 87725 | GIM_Try, /*On fail goto*//*Label 4871*/ GIMT_Encode4(271779), // Rule ID 654 // |
| 87726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87727 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87728 | // (fp_to_uint:{ *:[i16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_U16_F16_t16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U16_F16_t16_e64), |
| 87730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87735 | GIR_RootConstrainSelectedInstOperands, |
| 87736 | // GIR_Coverage, 654, |
| 87737 | GIR_EraseRootFromParent_Done, |
| 87738 | // Label 4871: @271779 |
| 87739 | GIM_Reject, |
| 87740 | // Label 4869: @271780 |
| 87741 | GIM_Reject, |
| 87742 | // Label 4863: @271781 |
| 87743 | GIM_Try, /*On fail goto*//*Label 4872*/ GIMT_Encode4(271811), // Rule ID 30 // |
| 87744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 87745 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87747 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18490), |
| 87748 | // (fp_to_uint:{ *:[i32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18490>> => (S_CVT_U32_F32:{ *:[i32] } f32:{ *:[f32] }:$src0) |
| 87749 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_U32_F32), |
| 87750 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 87751 | GIR_RootConstrainSelectedInstOperands, |
| 87752 | // GIR_Coverage, 30, |
| 87753 | GIR_Done, |
| 87754 | // Label 4872: @271811 |
| 87755 | GIM_Try, /*On fail goto*//*Label 4873*/ GIMT_Encode4(271863), // Rule ID 6671 // |
| 87756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87757 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87759 | // (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$src) => (V_CVT_U32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src)) |
| 87760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_e64), |
| 87762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87763 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87764 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87765 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87766 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87767 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e32), |
| 87769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87770 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87771 | GIR_RootConstrainSelectedInstOperands, |
| 87772 | // GIR_Coverage, 6671, |
| 87773 | GIR_EraseRootFromParent_Done, |
| 87774 | // Label 4873: @271863 |
| 87775 | GIM_Try, /*On fail goto*//*Label 4874*/ GIMT_Encode4(271915), // Rule ID 6685 // |
| 87776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87777 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87779 | // (fp_to_uint:{ *:[i32] } f16:{ *:[f16] }:$src) => (V_CVT_U32_F32_e32:{ *:[i32] } (V_CVT_F32_F16_t16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[f16] }:$src)) |
| 87780 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87781 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_F16_t16_e64), |
| 87782 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87783 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87784 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87785 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87786 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87787 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e32), |
| 87789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87790 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87791 | GIR_RootConstrainSelectedInstOperands, |
| 87792 | // GIR_Coverage, 6685, |
| 87793 | GIR_EraseRootFromParent_Done, |
| 87794 | // Label 4874: @271915 |
| 87795 | GIM_Try, /*On fail goto*//*Label 4875*/ GIMT_Encode4(271961), // Rule ID 578 // |
| 87796 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 87797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87799 | // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_U32_F64_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F64_e64), |
| 87801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87806 | GIR_RootConstrainSelectedInstOperands, |
| 87807 | // GIR_Coverage, 578, |
| 87808 | GIR_EraseRootFromParent_Done, |
| 87809 | // Label 4875: @271961 |
| 87810 | GIM_Try, /*On fail goto*//*Label 4876*/ GIMT_Encode4(272007), // Rule ID 582 // |
| 87811 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87814 | // (fp_to_uint:{ *:[i32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_U32_F32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_U32_F32_e64), |
| 87816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 87818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 87820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 87821 | GIR_RootConstrainSelectedInstOperands, |
| 87822 | // GIR_Coverage, 582, |
| 87823 | GIR_EraseRootFromParent_Done, |
| 87824 | // Label 4876: @272007 |
| 87825 | GIM_Reject, |
| 87826 | // Label 4864: @272008 |
| 87827 | GIM_Reject, |
| 87828 | // Label 74: @272009 |
| 87829 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4880*/ GIMT_Encode4(272555), |
| 87830 | /*GILLT_s16*//*Label 4877*/ GIMT_Encode4(272032), |
| 87831 | /*GILLT_s32*//*Label 4878*/ GIMT_Encode4(272349), |
| 87832 | /*GILLT_s64*//*Label 4879*/ GIMT_Encode4(272461), |
| 87833 | // Label 4877: @272032 |
| 87834 | GIM_Try, /*On fail goto*//*Label 4881*/ GIMT_Encode4(272084), // Rule ID 6672 // |
| 87835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87836 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87838 | // (sint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src) => (V_CVT_F16_F32_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_I32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src)) |
| 87839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e32), |
| 87841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87842 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87843 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64), |
| 87845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87847 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87850 | GIR_RootConstrainSelectedInstOperands, |
| 87851 | // GIR_Coverage, 6672, |
| 87852 | GIR_EraseRootFromParent_Done, |
| 87853 | // Label 4881: @272084 |
| 87854 | GIM_Try, /*On fail goto*//*Label 4882*/ GIMT_Encode4(272136), // Rule ID 6686 // |
| 87855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87856 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87858 | // (sint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src) => (V_CVT_F16_F32_t16_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_I32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src)) |
| 87859 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87860 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e32), |
| 87861 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87862 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87863 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64), |
| 87865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87870 | GIR_RootConstrainSelectedInstOperands, |
| 87871 | // GIR_Coverage, 6686, |
| 87872 | GIR_EraseRootFromParent_Done, |
| 87873 | // Label 4882: @272136 |
| 87874 | GIM_Try, /*On fail goto*//*Label 4883*/ GIMT_Encode4(272198), // Rule ID 7179 // |
| 87875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 87876 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 87877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87878 | // (sint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src) => (V_CVT_F16_F32_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 87879 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87880 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 87881 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87882 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87883 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87884 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87885 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(3212836864), |
| 87886 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87887 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e32), |
| 87889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87890 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87891 | GIR_RootConstrainSelectedInstOperands, |
| 87892 | // GIR_Coverage, 7179, |
| 87893 | GIR_EraseRootFromParent_Done, |
| 87894 | // Label 4883: @272198 |
| 87895 | GIM_Try, /*On fail goto*//*Label 4884*/ GIMT_Encode4(272260), // Rule ID 7180 // |
| 87896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87897 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 87898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32_Lo128RegClassID), |
| 87899 | // (sint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src) => (V_CVT_F16_F32_t16_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 87900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 87902 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87903 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87904 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87905 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87906 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(3212836864), |
| 87907 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 87908 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 87909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e32), |
| 87910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 87912 | GIR_RootConstrainSelectedInstOperands, |
| 87913 | // GIR_Coverage, 7180, |
| 87914 | GIR_EraseRootFromParent_Done, |
| 87915 | // Label 4884: @272260 |
| 87916 | GIM_Try, /*On fail goto*//*Label 4885*/ GIMT_Encode4(272304), // Rule ID 649 // |
| 87917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 87918 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87921 | // (sint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_I16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_I16_e64), |
| 87923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 87926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 87927 | GIR_RootConstrainSelectedInstOperands, |
| 87928 | // GIR_Coverage, 649, |
| 87929 | GIR_EraseRootFromParent_Done, |
| 87930 | // Label 4885: @272304 |
| 87931 | GIM_Try, /*On fail goto*//*Label 4886*/ GIMT_Encode4(272348), // Rule ID 651 // |
| 87932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 87933 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 87934 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87935 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87936 | // (sint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_I16_t16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_I16_t16_e64), |
| 87938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 87941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 87942 | GIR_RootConstrainSelectedInstOperands, |
| 87943 | // GIR_Coverage, 651, |
| 87944 | GIR_EraseRootFromParent_Done, |
| 87945 | // Label 4886: @272348 |
| 87946 | GIM_Reject, |
| 87947 | // Label 4878: @272349 |
| 87948 | GIM_Try, /*On fail goto*//*Label 4887*/ GIMT_Encode4(272379), // Rule ID 27 // |
| 87949 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 87950 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 87952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18487), |
| 87953 | // (sint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18487>> => (S_CVT_F32_I32:{ *:[f32] } i32:{ *:[i32] }:$src0) |
| 87954 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_I32), |
| 87955 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 87956 | GIR_RootConstrainSelectedInstOperands, |
| 87957 | // GIR_Coverage, 27, |
| 87958 | GIR_Done, |
| 87959 | // Label 4887: @272379 |
| 87960 | GIM_Try, /*On fail goto*//*Label 4888*/ GIMT_Encode4(272419), // Rule ID 7183 // |
| 87961 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 87962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87963 | // (sint_to_fp:{ *:[f32] } i1:{ *:[i1] }:$src) => (V_CNDMASK_B32_e64:{ *:[f32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 3212836864:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src) |
| 87964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 87965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 87969 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864), |
| 87970 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 87971 | GIR_RootConstrainSelectedInstOperands, |
| 87972 | // GIR_Coverage, 7183, |
| 87973 | GIR_EraseRootFromParent_Done, |
| 87974 | // Label 4888: @272419 |
| 87975 | GIM_Try, /*On fail goto*//*Label 4889*/ GIMT_Encode4(272460), // Rule ID 580 // |
| 87976 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 87977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 87978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 87979 | // (sint_to_fp:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_I32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 87980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_I32_e64), |
| 87981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 87982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 87983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 87984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 87985 | GIR_RootConstrainSelectedInstOperands, |
| 87986 | // GIR_Coverage, 580, |
| 87987 | GIR_EraseRootFromParent_Done, |
| 87988 | // Label 4889: @272460 |
| 87989 | GIM_Reject, |
| 87990 | // Label 4879: @272461 |
| 87991 | GIM_Try, /*On fail goto*//*Label 4890*/ GIMT_Encode4(272513), // Rule ID 7185 // |
| 87992 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 87993 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 87994 | // (sint_to_fp:{ *:[f64] } i1:{ *:[i1] }:$src) => (V_CVT_F64_I32_e32:{ *:[f64] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, -1:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 87995 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 87996 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 87997 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 87998 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 87999 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88000 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88001 | GIR_AddImm8, /*InsnID*/1, /*Imm*/uint8_t(-1), |
| 88002 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88003 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88004 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_I32_e32), |
| 88005 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88006 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88007 | GIR_RootConstrainSelectedInstOperands, |
| 88008 | // GIR_Coverage, 7185, |
| 88009 | GIR_EraseRootFromParent_Done, |
| 88010 | // Label 4890: @272513 |
| 88011 | GIM_Try, /*On fail goto*//*Label 4891*/ GIMT_Encode4(272554), // Rule ID 574 // |
| 88012 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88014 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 88015 | // (sint_to_fp:{ *:[f64] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F64_I32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 88016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_I32_e64), |
| 88017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 88020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 88021 | GIR_RootConstrainSelectedInstOperands, |
| 88022 | // GIR_Coverage, 574, |
| 88023 | GIR_EraseRootFromParent_Done, |
| 88024 | // Label 4891: @272554 |
| 88025 | GIM_Reject, |
| 88026 | // Label 4880: @272555 |
| 88027 | GIM_Reject, |
| 88028 | // Label 75: @272556 |
| 88029 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4895*/ GIMT_Encode4(273102), |
| 88030 | /*GILLT_s16*//*Label 4892*/ GIMT_Encode4(272579), |
| 88031 | /*GILLT_s32*//*Label 4893*/ GIMT_Encode4(272896), |
| 88032 | /*GILLT_s64*//*Label 4894*/ GIMT_Encode4(273008), |
| 88033 | // Label 4892: @272579 |
| 88034 | GIM_Try, /*On fail goto*//*Label 4896*/ GIMT_Encode4(272631), // Rule ID 6673 // |
| 88035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 88036 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88038 | // (uint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src) => (V_CVT_F16_F32_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_U32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src)) |
| 88039 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88040 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e32), |
| 88041 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88042 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88043 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e64), |
| 88045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88050 | GIR_RootConstrainSelectedInstOperands, |
| 88051 | // GIR_Coverage, 6673, |
| 88052 | GIR_EraseRootFromParent_Done, |
| 88053 | // Label 4896: @272631 |
| 88054 | GIM_Try, /*On fail goto*//*Label 4897*/ GIMT_Encode4(272683), // Rule ID 6687 // |
| 88055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88056 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88057 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88058 | // (uint_to_fp:{ *:[f16] } i32:{ *:[i32] }:$src) => (V_CVT_F16_F32_t16_e64:{ *:[f16] } 0:{ *:[i32] }, (V_CVT_F32_U32_e32:{ *:[i16] } VSrc_b32:{ *:[i32] }:$src)) |
| 88059 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88060 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e32), |
| 88061 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88062 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88063 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e64), |
| 88065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88067 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88070 | GIR_RootConstrainSelectedInstOperands, |
| 88071 | // GIR_Coverage, 6687, |
| 88072 | GIR_EraseRootFromParent_Done, |
| 88073 | // Label 4897: @272683 |
| 88074 | GIM_Try, /*On fail goto*//*Label 4898*/ GIMT_Encode4(272745), // Rule ID 7181 // |
| 88075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 88076 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 88077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88078 | // (uint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src) => (V_CVT_F16_F32_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 88079 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88080 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 88081 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88082 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88083 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88084 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88085 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(1065353216), |
| 88086 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88087 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_e32), |
| 88089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88091 | GIR_RootConstrainSelectedInstOperands, |
| 88092 | // GIR_Coverage, 7181, |
| 88093 | GIR_EraseRootFromParent_Done, |
| 88094 | // Label 4898: @272745 |
| 88095 | GIM_Try, /*On fail goto*//*Label 4899*/ GIMT_Encode4(272807), // Rule ID 7182 // |
| 88096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88097 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 88098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32_Lo128RegClassID), |
| 88099 | // (uint_to_fp:{ *:[f16] } i1:{ *:[i1] }:$src) => (V_CVT_F16_F32_t16_e32:{ *:[f16] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 88100 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88101 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 88102 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88103 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88104 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88105 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88106 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(1065353216), |
| 88107 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88108 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_F32_t16_e32), |
| 88110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88111 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88112 | GIR_RootConstrainSelectedInstOperands, |
| 88113 | // GIR_Coverage, 7182, |
| 88114 | GIR_EraseRootFromParent_Done, |
| 88115 | // Label 4899: @272807 |
| 88116 | GIM_Try, /*On fail goto*//*Label 4900*/ GIMT_Encode4(272851), // Rule ID 648 // |
| 88117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 88118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 88121 | // (uint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_U16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 88122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_U16_e64), |
| 88123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 88126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 88127 | GIR_RootConstrainSelectedInstOperands, |
| 88128 | // GIR_Coverage, 648, |
| 88129 | GIR_EraseRootFromParent_Done, |
| 88130 | // Label 4900: @272851 |
| 88131 | GIM_Try, /*On fail goto*//*Label 4901*/ GIMT_Encode4(272895), // Rule ID 650 // |
| 88132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88133 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 88136 | // (uint_to_fp:{ *:[f16] } (VOP3Mods0:{ *:[i16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F16_U16_t16_e64:{ *:[f16] } i16:{ *:[i16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 88137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F16_U16_t16_e64), |
| 88138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 88141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 88142 | GIR_RootConstrainSelectedInstOperands, |
| 88143 | // GIR_Coverage, 650, |
| 88144 | GIR_EraseRootFromParent_Done, |
| 88145 | // Label 4901: @272895 |
| 88146 | GIM_Reject, |
| 88147 | // Label 4893: @272896 |
| 88148 | GIM_Try, /*On fail goto*//*Label 4902*/ GIMT_Encode4(272926), // Rule ID 28 // |
| 88149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 88150 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88152 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18488), |
| 88153 | // (uint_to_fp:{ *:[f32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18488>> => (S_CVT_F32_U32:{ *:[f32] } i32:{ *:[i32] }:$src0) |
| 88154 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CVT_F32_U32), |
| 88155 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 88156 | GIR_RootConstrainSelectedInstOperands, |
| 88157 | // GIR_Coverage, 28, |
| 88158 | GIR_Done, |
| 88159 | // Label 4902: @272926 |
| 88160 | GIM_Try, /*On fail goto*//*Label 4903*/ GIMT_Encode4(272966), // Rule ID 7184 // |
| 88161 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 88162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88163 | // (uint_to_fp:{ *:[f32] } i1:{ *:[i1] }:$src) => (V_CNDMASK_B32_e64:{ *:[f32] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1065353216:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src) |
| 88164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 88165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88169 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216), |
| 88170 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88171 | GIR_RootConstrainSelectedInstOperands, |
| 88172 | // GIR_Coverage, 7184, |
| 88173 | GIR_EraseRootFromParent_Done, |
| 88174 | // Label 4903: @272966 |
| 88175 | GIM_Try, /*On fail goto*//*Label 4904*/ GIMT_Encode4(273007), // Rule ID 581 // |
| 88176 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88178 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 88179 | // (uint_to_fp:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_U32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 88180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_U32_e64), |
| 88181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 88184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 88185 | GIR_RootConstrainSelectedInstOperands, |
| 88186 | // GIR_Coverage, 581, |
| 88187 | GIR_EraseRootFromParent_Done, |
| 88188 | // Label 4904: @273007 |
| 88189 | GIM_Reject, |
| 88190 | // Label 4894: @273008 |
| 88191 | GIM_Try, /*On fail goto*//*Label 4905*/ GIMT_Encode4(273060), // Rule ID 7186 // |
| 88192 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s1, |
| 88193 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88194 | // (uint_to_fp:{ *:[f64] } i1:{ *:[i1] }:$src) => (V_CVT_F64_U32_e32:{ *:[f64] } (V_CNDMASK_B32_e64:{ *:[i16] } 0:{ *:[i32] }, 0:{ *:[i32] }, 0:{ *:[i32] }, 1:{ *:[i32] }, SSrc_i1:{ *:[i1] }:$src)) |
| 88195 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88196 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B32_e64), |
| 88197 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88198 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88199 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88200 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 88201 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 88202 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 88203 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_U32_e32), |
| 88205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88206 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88207 | GIR_RootConstrainSelectedInstOperands, |
| 88208 | // GIR_Coverage, 7186, |
| 88209 | GIR_EraseRootFromParent_Done, |
| 88210 | // Label 4905: @273060 |
| 88211 | GIM_Try, /*On fail goto*//*Label 4906*/ GIMT_Encode4(273101), // Rule ID 579 // |
| 88212 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88214 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 88215 | // (uint_to_fp:{ *:[f64] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F64_U32_e64:{ *:[f64] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 88216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F64_U32_e64), |
| 88217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 88220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 88221 | GIR_RootConstrainSelectedInstOperands, |
| 88222 | // GIR_Coverage, 579, |
| 88223 | GIR_EraseRootFromParent_Done, |
| 88224 | // Label 4906: @273101 |
| 88225 | GIM_Reject, |
| 88226 | // Label 4895: @273102 |
| 88227 | GIM_Reject, |
| 88228 | // Label 76: @273103 |
| 88229 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4911*/ GIMT_Encode4(273906), |
| 88230 | /*GILLT_s16*//*Label 4907*/ GIMT_Encode4(273130), |
| 88231 | /*GILLT_s32*//*Label 4908*/ GIMT_Encode4(273350), |
| 88232 | /*GILLT_s64*//*Label 4909*/ GIMT_Encode4(273465), |
| 88233 | /*GILLT_v2s16*//*Label 4910*/ GIMT_Encode4(273791), |
| 88234 | // Label 4907: @273130 |
| 88235 | GIM_Try, /*On fail goto*//*Label 4912*/ GIMT_Encode4(273349), |
| 88236 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88237 | GIM_Try, /*On fail goto*//*Label 4913*/ GIMT_Encode4(273194), // Rule ID 7012 // |
| 88238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88239 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88240 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35931), |
| 88241 | // (fabs:{ *:[f16] } SReg_32:{ *:[f16] }:$src)<<P:Predicate_anonymous_35931>> => (S_AND_B32:{ *:[f16] }:{ *:[i1] } SReg_32:{ *:[f16] }:$src, (S_MOV_B32:{ *:[i1] } 32767:{ *:[i32] })) |
| 88242 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 88243 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88244 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88245 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88246 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 88248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88249 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88250 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88251 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 88252 | GIR_RootConstrainSelectedInstOperands, |
| 88253 | // GIR_Coverage, 7012, |
| 88254 | GIR_EraseRootFromParent_Done, |
| 88255 | // Label 4913: @273194 |
| 88256 | GIM_Try, /*On fail goto*//*Label 4914*/ GIMT_Encode4(273250), // Rule ID 7015 // |
| 88257 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88258 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88259 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35931), |
| 88260 | // (fabs:{ *:[bf16] } SReg_32:{ *:[bf16] }:$src)<<P:Predicate_anonymous_35931>> => (S_AND_B32:{ *:[bf16] }:{ *:[i1] } SReg_32:{ *:[bf16] }:$src, (S_MOV_B32:{ *:[i1] } 32767:{ *:[i32] })) |
| 88261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 88262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88264 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88265 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 88267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88268 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88269 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88270 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 88271 | GIR_RootConstrainSelectedInstOperands, |
| 88272 | // GIR_Coverage, 7015, |
| 88273 | GIR_EraseRootFromParent_Done, |
| 88274 | // Label 4914: @273250 |
| 88275 | GIM_Try, /*On fail goto*//*Label 4915*/ GIMT_Encode4(273299), // Rule ID 7030 // |
| 88276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88277 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88278 | // (fabs:{ *:[f16] } VGPR_32:{ *:[f16] }:$src) => (V_AND_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), VGPR_32:{ *:[f16] }:$src) |
| 88279 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88280 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88281 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88282 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88283 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 88285 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88286 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88287 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88288 | GIR_RootConstrainSelectedInstOperands, |
| 88289 | // GIR_Coverage, 7030, |
| 88290 | GIR_EraseRootFromParent_Done, |
| 88291 | // Label 4915: @273299 |
| 88292 | GIM_Try, /*On fail goto*//*Label 4916*/ GIMT_Encode4(273348), // Rule ID 7033 // |
| 88293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88294 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88295 | // (fabs:{ *:[bf16] } VGPR_32:{ *:[bf16] }:$src) => (V_AND_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), VGPR_32:{ *:[bf16] }:$src) |
| 88296 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88297 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88298 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88299 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88300 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 88302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88303 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88304 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88305 | GIR_RootConstrainSelectedInstOperands, |
| 88306 | // GIR_Coverage, 7033, |
| 88307 | GIR_EraseRootFromParent_Done, |
| 88308 | // Label 4916: @273348 |
| 88309 | GIM_Reject, |
| 88310 | // Label 4912: @273349 |
| 88311 | GIM_Reject, |
| 88312 | // Label 4908: @273350 |
| 88313 | GIM_Try, /*On fail goto*//*Label 4917*/ GIMT_Encode4(273464), |
| 88314 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88315 | GIM_Try, /*On fail goto*//*Label 4918*/ GIMT_Encode4(273414), // Rule ID 7009 // |
| 88316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88317 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88318 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35931), |
| 88319 | // (fabs:{ *:[f32] } SReg_32:{ *:[f32] }:$src)<<P:Predicate_anonymous_35931>> => (S_AND_B32:{ *:[f32] }:{ *:[i1] } SReg_32:{ *:[f32] }:$src, (S_MOV_B32:{ *:[i1] } 2147483647:{ *:[i32] })) |
| 88320 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 88321 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88322 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88323 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88324 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 88326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88327 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88328 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88329 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 88330 | GIR_RootConstrainSelectedInstOperands, |
| 88331 | // GIR_Coverage, 7009, |
| 88332 | GIR_EraseRootFromParent_Done, |
| 88333 | // Label 4918: @273414 |
| 88334 | GIM_Try, /*On fail goto*//*Label 4919*/ GIMT_Encode4(273463), // Rule ID 7028 // |
| 88335 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88336 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88337 | // (fabs:{ *:[f32] } VGPR_32:{ *:[f32] }:$src) => (V_AND_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), VGPR_32:{ *:[f32] }:$src) |
| 88338 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88339 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88340 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88341 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88342 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 88344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88345 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88346 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88347 | GIR_RootConstrainSelectedInstOperands, |
| 88348 | // GIR_Coverage, 7028, |
| 88349 | GIR_EraseRootFromParent_Done, |
| 88350 | // Label 4919: @273463 |
| 88351 | GIM_Reject, |
| 88352 | // Label 4917: @273464 |
| 88353 | GIM_Reject, |
| 88354 | // Label 4909: @273465 |
| 88355 | GIM_Try, /*On fail goto*//*Label 4920*/ GIMT_Encode4(273790), |
| 88356 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 88357 | GIM_Try, /*On fail goto*//*Label 4921*/ GIMT_Encode4(273643), // Rule ID 7024 // |
| 88358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88359 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88360 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35931), |
| 88361 | // (fabs:{ *:[f64] } SReg_64:{ *:[f64] }:$src)<<P:Predicate_anonymous_35931>> => (REG_SEQUENCE:{ *:[f64] } SReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_AND_B32:{ *:[i1] }:{ *:[i1] } (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] }), (S_MOV_B32:{ *:[i1] } 2147483647:{ *:[i32] })), SReg_32:{ *:[i32] }), sub1:{ *:[i32] }) |
| 88362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 88363 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 88364 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 88365 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 88366 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1, |
| 88367 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88368 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88369 | GIR_AddImm, /*InsnID*/5, /*Imm*/GIMT_Encode8(2147483647), |
| 88370 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 88371 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88372 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88373 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 88374 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 88375 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88376 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 88377 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88378 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 88379 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 88380 | GIR_SetImplicitDefDead, /*InsnID*/3, /*OpIdx for AMDGPU::SCC*/0, |
| 88381 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 88382 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88383 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88384 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 88385 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88388 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 88389 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 88390 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 88392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 88393 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88394 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 88395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88396 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 88397 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88398 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 88399 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 88400 | // GIR_Coverage, 7024, |
| 88401 | GIR_EraseRootFromParent_Done, |
| 88402 | // Label 4921: @273643 |
| 88403 | GIM_Try, /*On fail goto*//*Label 4922*/ GIMT_Encode4(273789), // Rule ID 7039 // |
| 88404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88405 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88406 | // (fabs:{ *:[f64] } VReg_64:{ *:[f64] }:$src) => (REG_SEQUENCE:{ *:[f64] } VReg_64:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub0:{ *:[i32] }), sub0:{ *:[i32] }, (V_AND_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i32] } 2147483647:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[f64] }:$src, sub1:{ *:[i32] })), sub1:{ *:[i32] }) |
| 88407 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 88408 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 88409 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s32, |
| 88410 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 88411 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88412 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88413 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // src |
| 88414 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88415 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88416 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88417 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88418 | GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(2147483647), |
| 88419 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 88420 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 88421 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88422 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 88423 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 88424 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88425 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88427 | GIR_CopySubReg, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // src |
| 88428 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88429 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 88431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 88432 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88433 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 88434 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88435 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 88436 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 88437 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88438 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88439 | // GIR_Coverage, 7039, |
| 88440 | GIR_EraseRootFromParent_Done, |
| 88441 | // Label 4922: @273789 |
| 88442 | GIM_Reject, |
| 88443 | // Label 4920: @273790 |
| 88444 | GIM_Reject, |
| 88445 | // Label 4910: @273791 |
| 88446 | GIM_Try, /*On fail goto*//*Label 4923*/ GIMT_Encode4(273905), |
| 88447 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 88448 | GIM_Try, /*On fail goto*//*Label 4924*/ GIMT_Encode4(273855), // Rule ID 7018 // |
| 88449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88450 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 88451 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35931), |
| 88452 | // (fabs:{ *:[v2f16] } SReg_32:{ *:[v2f16] }:$src)<<P:Predicate_anonymous_35931>> => (S_AND_B32:{ *:[v2f16] }:{ *:[i1] } SReg_32:{ *:[v2f16] }:$src, (S_MOV_B32:{ *:[i1] } 2147450879:{ *:[i32] })) |
| 88453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 88454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88456 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147450879), |
| 88457 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 88459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88460 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88462 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 88463 | GIR_RootConstrainSelectedInstOperands, |
| 88464 | // GIR_Coverage, 7018, |
| 88465 | GIR_EraseRootFromParent_Done, |
| 88466 | // Label 4924: @273855 |
| 88467 | GIM_Try, /*On fail goto*//*Label 4925*/ GIMT_Encode4(273904), // Rule ID 7037 // |
| 88468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88469 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88470 | // (fabs:{ *:[v2f16] } VGPR_32:{ *:[v2f16] }:$src) => (V_AND_B32_e64:{ *:[v2f16] } (S_MOV_B32:{ *:[i16] } 2147450879:{ *:[i32] }), VGPR_32:{ *:[v2f16] }:$src) |
| 88471 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88472 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88473 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88474 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147450879), |
| 88475 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_AND_B32_e64), |
| 88477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88479 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 88480 | GIR_RootConstrainSelectedInstOperands, |
| 88481 | // GIR_Coverage, 7037, |
| 88482 | GIR_EraseRootFromParent_Done, |
| 88483 | // Label 4925: @273904 |
| 88484 | GIM_Reject, |
| 88485 | // Label 4923: @273905 |
| 88486 | GIM_Reject, |
| 88487 | // Label 4911: @273906 |
| 88488 | GIM_Reject, |
| 88489 | // Label 77: @273907 |
| 88490 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 4928*/ GIMT_Encode4(274463), |
| 88491 | /*GILLT_s16*//*Label 4926*/ GIMT_Encode4(273926), |
| 88492 | /*GILLT_s32*//*Label 4927*/ GIMT_Encode4(274180), |
| 88493 | // Label 4926: @273926 |
| 88494 | GIM_Try, /*On fail goto*//*Label 4929*/ GIMT_Encode4(274179), |
| 88495 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88496 | GIM_Try, /*On fail goto*//*Label 4930*/ GIMT_Encode4(273984), // Rule ID 7043 // |
| 88497 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 88498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88499 | // (fcopysign:{ *:[f16] } f16:{ *:[f16] }:$src0, f16:{ *:[f16] }:$src1) => (V_BFI_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[f16] }:$src0, ?:{ *:[f16] }:$src1) |
| 88500 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88501 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88502 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88503 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88504 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88507 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88508 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88509 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 88510 | GIR_RootConstrainSelectedInstOperands, |
| 88511 | // GIR_Coverage, 7043, |
| 88512 | GIR_EraseRootFromParent_Done, |
| 88513 | // Label 4930: @273984 |
| 88514 | GIM_Try, /*On fail goto*//*Label 4931*/ GIMT_Encode4(274056), // Rule ID 7046 // |
| 88515 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 88516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88517 | // (fcopysign:{ *:[f16] } f16:{ *:[f16] }:$src0, f32:{ *:[f32] }:$src1) => (V_BFI_B32_e64:{ *:[f16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[f16] }:$src0, (V_LSHRREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f32] }:$src1)) |
| 88518 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88519 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 88520 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64), |
| 88521 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88522 | GIR_AddImm8, /*InsnID*/2, /*Imm*/16, |
| 88523 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1 |
| 88524 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88525 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88526 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88527 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88528 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88531 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88532 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88534 | GIR_RootConstrainSelectedInstOperands, |
| 88535 | // GIR_Coverage, 7046, |
| 88536 | GIR_EraseRootFromParent_Done, |
| 88537 | // Label 4931: @274056 |
| 88538 | GIM_Try, /*On fail goto*//*Label 4932*/ GIMT_Encode4(274106), // Rule ID 7048 // |
| 88539 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 88540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88541 | // (fcopysign:{ *:[bf16] } bf16:{ *:[bf16] }:$src0, bf16:{ *:[bf16] }:$src1) => (V_BFI_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[bf16] }:$src0, ?:{ *:[bf16] }:$src1) |
| 88542 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88543 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88544 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88545 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88546 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88550 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88551 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 88552 | GIR_RootConstrainSelectedInstOperands, |
| 88553 | // GIR_Coverage, 7048, |
| 88554 | GIR_EraseRootFromParent_Done, |
| 88555 | // Label 4932: @274106 |
| 88556 | GIM_Try, /*On fail goto*//*Label 4933*/ GIMT_Encode4(274178), // Rule ID 7051 // |
| 88557 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 88558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88559 | // (fcopysign:{ *:[bf16] } bf16:{ *:[bf16] }:$src0, f32:{ *:[f32] }:$src1) => (V_BFI_B32_e64:{ *:[bf16] } (S_MOV_B32:{ *:[i16] } 32767:{ *:[i32] }), ?:{ *:[bf16] }:$src0, (V_LSHRREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f32] }:$src1)) |
| 88560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88561 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 88562 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHRREV_B32_e64), |
| 88563 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88564 | GIR_AddImm8, /*InsnID*/2, /*Imm*/16, |
| 88565 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1 |
| 88566 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88567 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88568 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88569 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(32767), |
| 88570 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88573 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88574 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88575 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88576 | GIR_RootConstrainSelectedInstOperands, |
| 88577 | // GIR_Coverage, 7051, |
| 88578 | GIR_EraseRootFromParent_Done, |
| 88579 | // Label 4933: @274178 |
| 88580 | GIM_Reject, |
| 88581 | // Label 4929: @274179 |
| 88582 | GIM_Reject, |
| 88583 | // Label 4927: @274180 |
| 88584 | GIM_Try, /*On fail goto*//*Label 4934*/ GIMT_Encode4(274462), |
| 88585 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88586 | GIM_Try, /*On fail goto*//*Label 4935*/ GIMT_Encode4(274260), // Rule ID 7044 // |
| 88587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 88588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88589 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f16:{ *:[f16] }:$src1) => (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (V_LSHLREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[f16] }:$src1)) |
| 88590 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88591 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 88592 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 88593 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88594 | GIR_AddImm8, /*InsnID*/2, /*Imm*/16, |
| 88595 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1 |
| 88596 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88597 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88598 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88599 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88600 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88603 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88604 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88605 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88606 | GIR_RootConstrainSelectedInstOperands, |
| 88607 | // GIR_Coverage, 7044, |
| 88608 | GIR_EraseRootFromParent_Done, |
| 88609 | // Label 4935: @274260 |
| 88610 | GIM_Try, /*On fail goto*//*Label 4936*/ GIMT_Encode4(274332), // Rule ID 7049 // |
| 88611 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 88612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88613 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, bf16:{ *:[bf16] }:$src1) => (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (V_LSHLREV_B32_e64:{ *:[i16] } 16:{ *:[i32] }, ?:{ *:[bf16] }:$src1)) |
| 88614 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88615 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 88616 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_LSHLREV_B32_e64), |
| 88617 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88618 | GIR_AddImm8, /*InsnID*/2, /*Imm*/16, |
| 88619 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // src1 |
| 88620 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 88621 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88622 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88623 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88624 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88627 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88628 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88629 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88630 | GIR_RootConstrainSelectedInstOperands, |
| 88631 | // GIR_Coverage, 7049, |
| 88632 | GIR_EraseRootFromParent_Done, |
| 88633 | // Label 4936: @274332 |
| 88634 | GIM_Try, /*On fail goto*//*Label 4937*/ GIMT_Encode4(274382), // Rule ID 7087 // |
| 88635 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 88636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88637 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f32:{ *:[f32] }:$src1) => (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, ?:{ *:[f32] }:$src1) |
| 88638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88641 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88642 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88646 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88647 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 88648 | GIR_RootConstrainSelectedInstOperands, |
| 88649 | // GIR_Coverage, 7087, |
| 88650 | GIR_EraseRootFromParent_Done, |
| 88651 | // Label 4937: @274382 |
| 88652 | GIM_Try, /*On fail goto*//*Label 4938*/ GIMT_Encode4(274461), // Rule ID 7088 // |
| 88653 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 88654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88655 | // (fcopysign:{ *:[f32] } f32:{ *:[f32] }:$src0, f64:{ *:[f64] }:$src1) => (V_BFI_B32_e64:{ *:[f32] } (S_MOV_B32:{ *:[i16] } 2147483647:{ *:[i32] }), ?:{ *:[f32] }:$src0, (EXTRACT_SUBREG:{ *:[i32] } SReg_64:{ *:[f64] }:$src1, sub1:{ *:[i32] })) |
| 88656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88657 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 88658 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 88659 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88660 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, /*SubRegIdx*/GIMT_Encode2(11), // src1 |
| 88661 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 88662 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 88663 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 88664 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88665 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(2147483647), |
| 88666 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 88668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88670 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 88671 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 88672 | GIR_RootConstrainSelectedInstOperands, |
| 88673 | // GIR_Coverage, 7088, |
| 88674 | GIR_EraseRootFromParent_Done, |
| 88675 | // Label 4938: @274461 |
| 88676 | GIM_Reject, |
| 88677 | // Label 4934: @274462 |
| 88678 | GIM_Reject, |
| 88679 | // Label 4928: @274463 |
| 88680 | GIM_Reject, |
| 88681 | // Label 78: @274464 |
| 88682 | GIM_Try, /*On fail goto*//*Label 4939*/ GIMT_Encode4(274732), |
| 88683 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s1, |
| 88684 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 4943*/ GIMT_Encode4(274731), |
| 88685 | /*GILLT_s16*//*Label 4940*/ GIMT_Encode4(274495), |
| 88686 | /*GILLT_s32*//*Label 4941*/ GIMT_Encode4(274615), |
| 88687 | /*GILLT_s64*//*Label 4942*/ GIMT_Encode4(274673), |
| 88688 | // Label 4940: @274495 |
| 88689 | GIM_Try, /*On fail goto*//*Label 4944*/ GIMT_Encode4(274614), |
| 88690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 88691 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 88692 | GIM_Try, /*On fail goto*//*Label 4945*/ GIMT_Encode4(274560), // Rule ID 2455 // |
| 88693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 88694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 88695 | // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask) => (V_CMP_CLASS_F16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f16:{ *:[f16] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask)) |
| 88696 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88697 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 88698 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88699 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 88700 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_e64), |
| 88702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 88704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88705 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88706 | GIR_RootConstrainSelectedInstOperands, |
| 88707 | // GIR_Coverage, 2455, |
| 88708 | GIR_EraseRootFromParent_Done, |
| 88709 | // Label 4945: @274560 |
| 88710 | GIM_Try, /*On fail goto*//*Label 4946*/ GIMT_Encode4(274613), // Rule ID 2456 // |
| 88711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 88713 | // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask) => (V_CMP_CLASS_F16_t16_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f16:{ *:[f16] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask)) |
| 88714 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88715 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 88716 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88717 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 88718 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F16_t16_e64), |
| 88720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 88722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88723 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88724 | GIR_RootConstrainSelectedInstOperands, |
| 88725 | // GIR_Coverage, 2456, |
| 88726 | GIR_EraseRootFromParent_Done, |
| 88727 | // Label 4946: @274613 |
| 88728 | GIM_Reject, |
| 88729 | // Label 4944: @274614 |
| 88730 | GIM_Reject, |
| 88731 | // Label 4941: @274615 |
| 88732 | GIM_Try, /*On fail goto*//*Label 4947*/ GIMT_Encode4(274672), // Rule ID 2457 // |
| 88733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 88734 | // MIs[0] mask |
| 88735 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 88736 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 88737 | // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask) => (V_CMP_CLASS_F32_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f32:{ *:[f32] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask)) |
| 88738 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88739 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 88740 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88741 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 88742 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F32_e64), |
| 88744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 88746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88747 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88748 | GIR_RootConstrainSelectedInstOperands, |
| 88749 | // GIR_Coverage, 2457, |
| 88750 | GIR_EraseRootFromParent_Done, |
| 88751 | // Label 4947: @274672 |
| 88752 | GIM_Reject, |
| 88753 | // Label 4942: @274673 |
| 88754 | GIM_Try, /*On fail goto*//*Label 4948*/ GIMT_Encode4(274730), // Rule ID 2458 // |
| 88755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_1RegClassID), |
| 88756 | // MIs[0] mask |
| 88757 | GIM_CheckIsImm, /*MI*/0, /*Op*/2, |
| 88758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3modsnoncanonicalizing), |
| 88759 | // (is_fpclass:{ *:[i1] } (VOP3ModsNonCanonicalizing:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (timm:{ *:[i32] }):$mask) => (V_CMP_CLASS_F64_e64:{ *:[i1] } i32:{ *:[i32] }:$src0_mods, f64:{ *:[f64] }:$src0, (V_MOV_B32_e32:{ *:[i16] } (timm:{ *:[i32] }):$mask)) |
| 88760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 88761 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B32_e32), |
| 88762 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 88763 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // mask |
| 88764 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 88765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64), |
| 88766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 88767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 88768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 88769 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 88770 | GIR_RootConstrainSelectedInstOperands, |
| 88771 | // GIR_Coverage, 2458, |
| 88772 | GIR_EraseRootFromParent_Done, |
| 88773 | // Label 4948: @274730 |
| 88774 | GIM_Reject, |
| 88775 | // Label 4943: @274731 |
| 88776 | GIM_Reject, |
| 88777 | // Label 4939: @274732 |
| 88778 | GIM_Reject, |
| 88779 | // Label 79: @274733 |
| 88780 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 4954*/ GIMT_Encode4(275932), |
| 88781 | /*GILLT_s16*//*Label 4949*/ GIMT_Encode4(274764), |
| 88782 | /*GILLT_s32*//*Label 4950*/ GIMT_Encode4(275202), |
| 88783 | /*GILLT_s64*//*Label 4951*/ GIMT_Encode4(275422), |
| 88784 | /*GILLT_v2s16*//*Label 4952*/ GIMT_Encode4(275679), |
| 88785 | /*GILLT_v2s32*//*Label 4953*/ GIMT_Encode4(275864), |
| 88786 | // Label 4949: @274764 |
| 88787 | GIM_Try, /*On fail goto*//*Label 4955*/ GIMT_Encode4(275201), |
| 88788 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 88789 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88790 | GIM_Try, /*On fail goto*//*Label 4956*/ GIMT_Encode4(274824), // Rule ID 7226 // |
| 88791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasMinMaxDenormModes_NotHasTrue16BitInsts), |
| 88792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88793 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 88794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 88795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88802 | GIR_RootConstrainSelectedInstOperands, |
| 88803 | // GIR_Coverage, 7226, |
| 88804 | GIR_EraseRootFromParent_Done, |
| 88805 | // Label 4956: @274824 |
| 88806 | GIM_Try, /*On fail goto*//*Label 4957*/ GIMT_Encode4(274872), // Rule ID 7227 // |
| 88807 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_HasMinMaxDenormModes_HasTrue16BitInsts), |
| 88808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88809 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F16_fake16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 88810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 88811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88818 | GIR_RootConstrainSelectedInstOperands, |
| 88819 | // GIR_Coverage, 7227, |
| 88820 | GIR_EraseRootFromParent_Done, |
| 88821 | // Label 4957: @274872 |
| 88822 | GIM_Try, /*On fail goto*//*Label 4958*/ GIMT_Encode4(274920), // Rule ID 7232 // |
| 88823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_Has16BitInsts_NotHasMinMaxDenormModes_NotHasTrue16BitInsts), |
| 88824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88825 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 88826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 88827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88834 | GIR_RootConstrainSelectedInstOperands, |
| 88835 | // GIR_Coverage, 7232, |
| 88836 | GIR_EraseRootFromParent_Done, |
| 88837 | // Label 4958: @274920 |
| 88838 | GIM_Try, /*On fail goto*//*Label 4959*/ GIMT_Encode4(274968), // Rule ID 7233 // |
| 88839 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_Has16BitInsts_HasTrue16BitInsts_NotHasMinMaxDenormModes), |
| 88840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88841 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F16_fake16_e64:{ *:[f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 88842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 88843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88850 | GIR_RootConstrainSelectedInstOperands, |
| 88851 | // GIR_Coverage, 7233, |
| 88852 | GIR_EraseRootFromParent_Done, |
| 88853 | // Label 4959: @274968 |
| 88854 | GIM_Try, /*On fail goto*//*Label 4960*/ GIMT_Encode4(275033), // Rule ID 7215 // |
| 88855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 88856 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 88857 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 88858 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 88859 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 88860 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88861 | // (fcanonicalize:{ *:[f16] } (fneg:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))) => (V_MUL_F16_e64:{ *:[f16] } 0:{ *:[i32] }, 48128:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src) |
| 88862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 88863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88865 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128), |
| 88866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88870 | GIR_RootConstrainSelectedInstOperands, |
| 88871 | // GIR_Coverage, 7215, |
| 88872 | GIR_EraseRootFromParent_Done, |
| 88873 | // Label 4960: @275033 |
| 88874 | GIM_Try, /*On fail goto*//*Label 4961*/ GIMT_Encode4(275098), // Rule ID 7217 // |
| 88875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 88877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 88878 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 88879 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 88880 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88881 | // (fcanonicalize:{ *:[f16] } (fneg:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods))) => (V_MUL_F16_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, 48128:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src) |
| 88882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 88883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88885 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(48128), |
| 88886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88890 | GIR_RootConstrainSelectedInstOperands, |
| 88891 | // GIR_Coverage, 7217, |
| 88892 | GIR_EraseRootFromParent_Done, |
| 88893 | // Label 4961: @275098 |
| 88894 | GIM_Try, /*On fail goto*//*Label 4962*/ GIMT_Encode4(275149), // Rule ID 7214 // |
| 88895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 88896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88897 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MUL_F16_e64:{ *:[f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src) |
| 88898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 88899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88901 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360), |
| 88902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88906 | GIR_RootConstrainSelectedInstOperands, |
| 88907 | // GIR_Coverage, 7214, |
| 88908 | GIR_EraseRootFromParent_Done, |
| 88909 | // Label 4962: @275149 |
| 88910 | GIM_Try, /*On fail goto*//*Label 4963*/ GIMT_Encode4(275200), // Rule ID 7216 // |
| 88911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 88912 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88913 | // (fcanonicalize:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MUL_F16_fake16_e64:{ *:[f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f16] }:$src) |
| 88914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 88915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88917 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360), |
| 88918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88920 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88922 | GIR_RootConstrainSelectedInstOperands, |
| 88923 | // GIR_Coverage, 7216, |
| 88924 | GIR_EraseRootFromParent_Done, |
| 88925 | // Label 4963: @275200 |
| 88926 | GIM_Reject, |
| 88927 | // Label 4955: @275201 |
| 88928 | GIM_Reject, |
| 88929 | // Label 4950: @275202 |
| 88930 | GIM_Try, /*On fail goto*//*Label 4964*/ GIMT_Encode4(275421), |
| 88931 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 88932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 88933 | GIM_Try, /*On fail goto*//*Label 4965*/ GIMT_Encode4(275262), // Rule ID 7223 // |
| 88934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes), |
| 88935 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88936 | // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src) |
| 88937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 88938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88945 | GIR_RootConstrainSelectedInstOperands, |
| 88946 | // GIR_Coverage, 7223, |
| 88947 | GIR_EraseRootFromParent_Done, |
| 88948 | // Label 4965: @275262 |
| 88949 | GIM_Try, /*On fail goto*//*Label 4966*/ GIMT_Encode4(275310), // Rule ID 7229 // |
| 88950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FalsePredicate_NotHasMinMaxDenormModes), |
| 88951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88952 | // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src) |
| 88953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 88954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88961 | GIR_RootConstrainSelectedInstOperands, |
| 88962 | // GIR_Coverage, 7229, |
| 88963 | GIR_EraseRootFromParent_Done, |
| 88964 | // Label 4966: @275310 |
| 88965 | GIM_Try, /*On fail goto*//*Label 4967*/ GIMT_Encode4(275372), // Rule ID 7220 // |
| 88966 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 88967 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FNEG), |
| 88968 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 88969 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 88970 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88971 | // (fcanonicalize:{ *:[f32] } (fneg:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods))) => (V_MUL_F32_e64:{ *:[f32] } 0:{ *:[i32] }, 3212836864:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src) |
| 88972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 88973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88975 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(3212836864), |
| 88976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88980 | GIR_RootConstrainSelectedInstOperands, |
| 88981 | // GIR_Coverage, 7220, |
| 88982 | GIR_EraseRootFromParent_Done, |
| 88983 | // Label 4967: @275372 |
| 88984 | GIM_Try, /*On fail goto*//*Label 4968*/ GIMT_Encode4(275420), // Rule ID 7219 // |
| 88985 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 88986 | // (fcanonicalize:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MUL_F32_e64:{ *:[f32] } 0:{ *:[i32] }, 1065353216:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f32] }:$src) |
| 88987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 88988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 88989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88990 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216), |
| 88991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 88992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 88993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 88995 | GIR_RootConstrainSelectedInstOperands, |
| 88996 | // GIR_Coverage, 7219, |
| 88997 | GIR_EraseRootFromParent_Done, |
| 88998 | // Label 4968: @275420 |
| 88999 | GIM_Reject, |
| 89000 | // Label 4964: @275421 |
| 89001 | GIM_Reject, |
| 89002 | // Label 4951: @275422 |
| 89003 | GIM_Try, /*On fail goto*//*Label 4969*/ GIMT_Encode4(275678), |
| 89004 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 89005 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 89006 | GIM_Try, /*On fail goto*//*Label 4970*/ GIMT_Encode4(275482), // Rule ID 7224 // |
| 89007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes_isNotGFX12Plus), |
| 89008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89009 | // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src) |
| 89010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 89011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89018 | GIR_RootConstrainSelectedInstOperands, |
| 89019 | // GIR_Coverage, 7224, |
| 89020 | GIR_EraseRootFromParent_Done, |
| 89021 | // Label 4970: @275482 |
| 89022 | GIM_Try, /*On fail goto*//*Label 4971*/ GIMT_Encode4(275530), // Rule ID 7225 // |
| 89023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes_isGFX12Plus), |
| 89024 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89025 | // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_NUM_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src) |
| 89026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 89027 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89033 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89034 | GIR_RootConstrainSelectedInstOperands, |
| 89035 | // GIR_Coverage, 7225, |
| 89036 | GIR_EraseRootFromParent_Done, |
| 89037 | // Label 4971: @275530 |
| 89038 | GIM_Try, /*On fail goto*//*Label 4972*/ GIMT_Encode4(275578), // Rule ID 7230 // |
| 89039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isNotGFX12Plus), |
| 89040 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89041 | // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src) |
| 89042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 89043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89050 | GIR_RootConstrainSelectedInstOperands, |
| 89051 | // GIR_Coverage, 7230, |
| 89052 | GIR_EraseRootFromParent_Done, |
| 89053 | // Label 4972: @275578 |
| 89054 | GIM_Try, /*On fail goto*//*Label 4973*/ GIMT_Encode4(275626), // Rule ID 7231 // |
| 89055 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP64Denormals_NotHasMinMaxDenormModes_isGFX12Plus), |
| 89056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89057 | // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MAX_NUM_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src) |
| 89058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 89059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89066 | GIR_RootConstrainSelectedInstOperands, |
| 89067 | // GIR_Coverage, 7231, |
| 89068 | GIR_EraseRootFromParent_Done, |
| 89069 | // Label 4973: @275626 |
| 89070 | GIM_Try, /*On fail goto*//*Label 4974*/ GIMT_Encode4(275677), // Rule ID 7222 // |
| 89071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 89072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89073 | // (fcanonicalize:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_MUL_F64_e64:{ *:[f64] } 0:{ *:[i32] }, 4607182418800017408:{ *:[i64] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[f64] }:$src) |
| 89074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64), |
| 89075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89077 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(4607182418800017408), |
| 89078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89082 | GIR_RootConstrainSelectedInstOperands, |
| 89083 | // GIR_Coverage, 7222, |
| 89084 | GIR_EraseRootFromParent_Done, |
| 89085 | // Label 4974: @275677 |
| 89086 | GIM_Reject, |
| 89087 | // Label 4969: @275678 |
| 89088 | GIM_Reject, |
| 89089 | // Label 4952: @275679 |
| 89090 | GIM_Try, /*On fail goto*//*Label 4975*/ GIMT_Encode4(275863), |
| 89091 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 89092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89093 | GIM_Try, /*On fail goto*//*Label 4976*/ GIMT_Encode4(275748), // Rule ID 7228 // |
| 89094 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMinMaxDenormModes), |
| 89095 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 89096 | // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] }) |
| 89097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16), |
| 89098 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89105 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89108 | GIR_RootConstrainSelectedInstOperands, |
| 89109 | // GIR_Coverage, 7228, |
| 89110 | GIR_EraseRootFromParent_Done, |
| 89111 | // Label 4976: @275748 |
| 89112 | GIM_Try, /*On fail goto*//*Label 4977*/ GIMT_Encode4(275805), // Rule ID 7234 // |
| 89113 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_FP16Denormals_NotHasMinMaxDenormModes), |
| 89114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 89115 | // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] }) |
| 89116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16), |
| 89117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89127 | GIR_RootConstrainSelectedInstOperands, |
| 89128 | // GIR_Coverage, 7234, |
| 89129 | GIR_EraseRootFromParent_Done, |
| 89130 | // Label 4977: @275805 |
| 89131 | GIM_Try, /*On fail goto*//*Label 4978*/ GIMT_Encode4(275862), // Rule ID 7218 // |
| 89132 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 89133 | // (fcanonicalize:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_PK_MUL_F16:{ *:[v2f16] } 0:{ *:[i32] }, 15360:{ *:[i32] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f16] }:$src, 0:{ *:[i1] }) |
| 89134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16), |
| 89135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89137 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(15360), |
| 89138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89145 | GIR_RootConstrainSelectedInstOperands, |
| 89146 | // GIR_Coverage, 7218, |
| 89147 | GIR_EraseRootFromParent_Done, |
| 89148 | // Label 4978: @275862 |
| 89149 | GIM_Reject, |
| 89150 | // Label 4975: @275863 |
| 89151 | GIM_Reject, |
| 89152 | // Label 4953: @275864 |
| 89153 | GIM_Try, /*On fail goto*//*Label 4979*/ GIMT_Encode4(275931), // Rule ID 7221 // |
| 89154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 89155 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 89156 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 89157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 89158 | // (fcanonicalize:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src, i32:{ *:[i32] }:$src_mods)) => (V_PK_MUL_F32:{ *:[v2f32] } 0:{ *:[i32] }, 1065353216:{ *:[i64] }, ?:{ *:[i32] }:$src_mods, ?:{ *:[v2f32] }:$src) |
| 89159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32), |
| 89160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89162 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(1065353216), |
| 89163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src_mods |
| 89164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src |
| 89165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89170 | GIR_RootConstrainSelectedInstOperands, |
| 89171 | // GIR_Coverage, 7221, |
| 89172 | GIR_EraseRootFromParent_Done, |
| 89173 | // Label 4979: @275931 |
| 89174 | GIM_Reject, |
| 89175 | // Label 4954: @275932 |
| 89176 | GIM_Reject, |
| 89177 | // Label 80: @275933 |
| 89178 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 4984*/ GIMT_Encode4(312271), |
| 89179 | /*GILLT_s16*//*Label 4980*/ GIMT_Encode4(275960), |
| 89180 | /*GILLT_s32*//*Label 4981*/ GIMT_Encode4(294434), |
| 89181 | /*GILLT_s64*//*Label 4982*/ GIMT_Encode4(311946), |
| 89182 | /*GILLT_v2s16*//*Label 4983*/ GIMT_Encode4(312199), |
| 89183 | // Label 4980: @275960 |
| 89184 | GIM_Try, /*On fail goto*//*Label 4985*/ GIMT_Encode4(294433), |
| 89185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 89186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 89187 | GIM_Try, /*On fail goto*//*Label 4986*/ GIMT_Encode4(276106), // Rule ID 11897 // |
| 89188 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89190 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89191 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89192 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89193 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89195 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89196 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89197 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89198 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89199 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89200 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89201 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89202 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89203 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89204 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89205 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89206 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89207 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89208 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89209 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89221 | GIR_RootConstrainSelectedInstOperands, |
| 89222 | // GIR_Coverage, 11897, |
| 89223 | GIR_EraseRootFromParent_Done, |
| 89224 | // Label 4986: @276106 |
| 89225 | GIM_Try, /*On fail goto*//*Label 4987*/ GIMT_Encode4(276241), // Rule ID 11898 // |
| 89226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89227 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89228 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89229 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89230 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89231 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89232 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89233 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89234 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89235 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89236 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89237 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89238 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89239 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89240 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89241 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89242 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89243 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89244 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89245 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89246 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89247 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89257 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89259 | GIR_RootConstrainSelectedInstOperands, |
| 89260 | // GIR_Coverage, 11898, |
| 89261 | GIR_EraseRootFromParent_Done, |
| 89262 | // Label 4987: @276241 |
| 89263 | GIM_Try, /*On fail goto*//*Label 4988*/ GIMT_Encode4(276376), // Rule ID 11901 // |
| 89264 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89266 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89267 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89268 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89269 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89270 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89271 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89272 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89273 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89274 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89275 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89276 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89277 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89278 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89279 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89280 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89281 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89282 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89283 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89284 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89285 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89294 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89295 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89297 | GIR_RootConstrainSelectedInstOperands, |
| 89298 | // GIR_Coverage, 11901, |
| 89299 | GIR_EraseRootFromParent_Done, |
| 89300 | // Label 4988: @276376 |
| 89301 | GIM_Try, /*On fail goto*//*Label 4989*/ GIMT_Encode4(276511), // Rule ID 11902 // |
| 89302 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89304 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89305 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89306 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89307 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89308 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89309 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89310 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89311 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89312 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89313 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89314 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89315 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89316 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89317 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89318 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89319 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89320 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89321 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89322 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89323 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89335 | GIR_RootConstrainSelectedInstOperands, |
| 89336 | // GIR_Coverage, 11902, |
| 89337 | GIR_EraseRootFromParent_Done, |
| 89338 | // Label 4989: @276511 |
| 89339 | GIM_Try, /*On fail goto*//*Label 4990*/ GIMT_Encode4(276646), // Rule ID 11882 // |
| 89340 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89343 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89345 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89346 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89347 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89348 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89349 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89350 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89351 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89352 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89353 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89354 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89355 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89356 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89357 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89358 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89359 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89360 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89361 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89373 | GIR_RootConstrainSelectedInstOperands, |
| 89374 | // GIR_Coverage, 11882, |
| 89375 | GIR_EraseRootFromParent_Done, |
| 89376 | // Label 4990: @276646 |
| 89377 | GIM_Try, /*On fail goto*//*Label 4991*/ GIMT_Encode4(276781), // Rule ID 11883 // |
| 89378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89380 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89381 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89382 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89383 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89384 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89385 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89386 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89387 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89388 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89389 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89390 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89391 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89392 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89393 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89394 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89395 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89396 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89397 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89398 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89399 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89409 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89411 | GIR_RootConstrainSelectedInstOperands, |
| 89412 | // GIR_Coverage, 11883, |
| 89413 | GIR_EraseRootFromParent_Done, |
| 89414 | // Label 4991: @276781 |
| 89415 | GIM_Try, /*On fail goto*//*Label 4992*/ GIMT_Encode4(276916), // Rule ID 11886 // |
| 89416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89418 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89419 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89420 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89421 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89422 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89423 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89424 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89425 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89426 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89427 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89428 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89429 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89430 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89431 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89432 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89433 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89434 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89435 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89436 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89437 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89449 | GIR_RootConstrainSelectedInstOperands, |
| 89450 | // GIR_Coverage, 11886, |
| 89451 | GIR_EraseRootFromParent_Done, |
| 89452 | // Label 4992: @276916 |
| 89453 | GIM_Try, /*On fail goto*//*Label 4993*/ GIMT_Encode4(277051), // Rule ID 11887 // |
| 89454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89456 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89457 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89458 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89459 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89460 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89461 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89462 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89463 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89464 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89465 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89466 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89467 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89468 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89469 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89470 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89471 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89472 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89473 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89474 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89475 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89487 | GIR_RootConstrainSelectedInstOperands, |
| 89488 | // GIR_Coverage, 11887, |
| 89489 | GIR_EraseRootFromParent_Done, |
| 89490 | // Label 4993: @277051 |
| 89491 | GIM_Try, /*On fail goto*//*Label 4994*/ GIMT_Encode4(277186), // Rule ID 7379 // |
| 89492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89493 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89494 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89495 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89496 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89497 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89498 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89499 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89500 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89501 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89502 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89503 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89504 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89505 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89506 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89507 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89508 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89509 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89510 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89511 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89512 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89513 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89523 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89525 | GIR_RootConstrainSelectedInstOperands, |
| 89526 | // GIR_Coverage, 7379, |
| 89527 | GIR_EraseRootFromParent_Done, |
| 89528 | // Label 4994: @277186 |
| 89529 | GIM_Try, /*On fail goto*//*Label 4995*/ GIMT_Encode4(277321), // Rule ID 11896 // |
| 89530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89531 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89532 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89533 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89534 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89535 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89536 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89537 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89538 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89539 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89540 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89541 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89542 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89543 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89544 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89545 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89546 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89547 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89548 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89549 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89550 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89551 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89563 | GIR_RootConstrainSelectedInstOperands, |
| 89564 | // GIR_Coverage, 11896, |
| 89565 | GIR_EraseRootFromParent_Done, |
| 89566 | // Label 4995: @277321 |
| 89567 | GIM_Try, /*On fail goto*//*Label 4996*/ GIMT_Encode4(277456), // Rule ID 11899 // |
| 89568 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89570 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89571 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89572 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89573 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89574 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89575 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89576 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89577 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89578 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89579 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89580 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89581 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89582 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89584 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89585 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89586 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89587 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89588 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89589 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89601 | GIR_RootConstrainSelectedInstOperands, |
| 89602 | // GIR_Coverage, 11899, |
| 89603 | GIR_EraseRootFromParent_Done, |
| 89604 | // Label 4996: @277456 |
| 89605 | GIM_Try, /*On fail goto*//*Label 4997*/ GIMT_Encode4(277591), // Rule ID 11900 // |
| 89606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89609 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89612 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89613 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89614 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89615 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89616 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89617 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89618 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89619 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89620 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89622 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89623 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89624 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89625 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89626 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89627 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89639 | GIR_RootConstrainSelectedInstOperands, |
| 89640 | // GIR_Coverage, 11900, |
| 89641 | GIR_EraseRootFromParent_Done, |
| 89642 | // Label 4997: @277591 |
| 89643 | GIM_Try, /*On fail goto*//*Label 4998*/ GIMT_Encode4(277726), // Rule ID 7378 // |
| 89644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89647 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89649 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89650 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89651 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89652 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89653 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89654 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89655 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89656 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89657 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89658 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89659 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89660 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89661 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89662 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89663 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89664 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89665 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89677 | GIR_RootConstrainSelectedInstOperands, |
| 89678 | // GIR_Coverage, 7378, |
| 89679 | GIR_EraseRootFromParent_Done, |
| 89680 | // Label 4998: @277726 |
| 89681 | GIM_Try, /*On fail goto*//*Label 4999*/ GIMT_Encode4(277861), // Rule ID 11881 // |
| 89682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89687 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89689 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89691 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89692 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89693 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89694 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89695 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89696 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89699 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89700 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89701 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89702 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89703 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89715 | GIR_RootConstrainSelectedInstOperands, |
| 89716 | // GIR_Coverage, 11881, |
| 89717 | GIR_EraseRootFromParent_Done, |
| 89718 | // Label 4999: @277861 |
| 89719 | GIM_Try, /*On fail goto*//*Label 5000*/ GIMT_Encode4(277996), // Rule ID 11884 // |
| 89720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89724 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89725 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89726 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89727 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89728 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89729 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89730 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89731 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89732 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89733 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89734 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89735 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89737 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89738 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89739 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89740 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89741 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89753 | GIR_RootConstrainSelectedInstOperands, |
| 89754 | // GIR_Coverage, 11884, |
| 89755 | GIR_EraseRootFromParent_Done, |
| 89756 | // Label 5000: @277996 |
| 89757 | GIM_Try, /*On fail goto*//*Label 5001*/ GIMT_Encode4(278131), // Rule ID 11885 // |
| 89758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89760 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89761 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89762 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89763 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89764 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89765 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89766 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89767 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89768 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 89769 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89770 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89771 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89772 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89773 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89774 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89775 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89776 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89777 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89778 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89779 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89781 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89791 | GIR_RootConstrainSelectedInstOperands, |
| 89792 | // GIR_Coverage, 11885, |
| 89793 | GIR_EraseRootFromParent_Done, |
| 89794 | // Label 5001: @278131 |
| 89795 | GIM_Try, /*On fail goto*//*Label 5002*/ GIMT_Encode4(278266), // Rule ID 11867 // |
| 89796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89801 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89802 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89803 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89804 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89805 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89806 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89807 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89808 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89809 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89810 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89811 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89812 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89813 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89814 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89815 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89816 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89817 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89829 | GIR_RootConstrainSelectedInstOperands, |
| 89830 | // GIR_Coverage, 11867, |
| 89831 | GIR_EraseRootFromParent_Done, |
| 89832 | // Label 5002: @278266 |
| 89833 | GIM_Try, /*On fail goto*//*Label 5003*/ GIMT_Encode4(278401), // Rule ID 11868 // |
| 89834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89839 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89840 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89841 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89842 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89843 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89844 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89845 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89846 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89847 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89848 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89851 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89852 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89853 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89854 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89855 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89867 | GIR_RootConstrainSelectedInstOperands, |
| 89868 | // GIR_Coverage, 11868, |
| 89869 | GIR_EraseRootFromParent_Done, |
| 89870 | // Label 5003: @278401 |
| 89871 | GIM_Try, /*On fail goto*//*Label 5004*/ GIMT_Encode4(278536), // Rule ID 11871 // |
| 89872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89874 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89875 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89876 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89877 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89878 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89879 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89880 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89881 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89882 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89883 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89884 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89885 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89886 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89887 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89889 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89890 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89891 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89892 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89893 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89905 | GIR_RootConstrainSelectedInstOperands, |
| 89906 | // GIR_Coverage, 11871, |
| 89907 | GIR_EraseRootFromParent_Done, |
| 89908 | // Label 5004: @278536 |
| 89909 | GIM_Try, /*On fail goto*//*Label 5005*/ GIMT_Encode4(278671), // Rule ID 11872 // |
| 89910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89912 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89913 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89914 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89915 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89916 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89917 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89918 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89919 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89920 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89921 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 89922 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89923 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89924 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89925 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89926 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89927 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89928 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89929 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89930 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89931 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 89935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 89936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 89937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 89938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89943 | GIR_RootConstrainSelectedInstOperands, |
| 89944 | // GIR_Coverage, 11872, |
| 89945 | GIR_EraseRootFromParent_Done, |
| 89946 | // Label 5005: @278671 |
| 89947 | GIM_Try, /*On fail goto*//*Label 5006*/ GIMT_Encode4(278806), // Rule ID 11852 // |
| 89948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89953 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89954 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89955 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89956 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89957 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89958 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89959 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89960 | // MIs[3] VOP3Mods:src0:src0_mods |
| 89961 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 89962 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89963 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 89964 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 89965 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 89966 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 89967 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 89968 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 89969 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 89970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 89971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 89972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 89973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 89974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 89975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 89976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 89977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 89978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 89981 | GIR_RootConstrainSelectedInstOperands, |
| 89982 | // GIR_Coverage, 11852, |
| 89983 | GIR_EraseRootFromParent_Done, |
| 89984 | // Label 5006: @278806 |
| 89985 | GIM_Try, /*On fail goto*//*Label 5007*/ GIMT_Encode4(278941), // Rule ID 11853 // |
| 89986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 89987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 89988 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 89989 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 89990 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 89991 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 89992 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 89993 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 89994 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 89995 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 89996 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 89997 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 89998 | // MIs[3] VOP3Mods:src1:src1_mods |
| 89999 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90000 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90002 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90003 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90004 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90005 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90006 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90007 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 90011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 90012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90019 | GIR_RootConstrainSelectedInstOperands, |
| 90020 | // GIR_Coverage, 11853, |
| 90021 | GIR_EraseRootFromParent_Done, |
| 90022 | // Label 5007: @278941 |
| 90023 | GIM_Try, /*On fail goto*//*Label 5008*/ GIMT_Encode4(279076), // Rule ID 11856 // |
| 90024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90029 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90030 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90031 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90032 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90033 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90034 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 90035 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90036 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90037 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90038 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90039 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90040 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90041 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90042 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90043 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90044 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90045 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90057 | GIR_RootConstrainSelectedInstOperands, |
| 90058 | // GIR_Coverage, 11856, |
| 90059 | GIR_EraseRootFromParent_Done, |
| 90060 | // Label 5008: @279076 |
| 90061 | GIM_Try, /*On fail goto*//*Label 5009*/ GIMT_Encode4(279211), // Rule ID 11857 // |
| 90062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90064 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90065 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90066 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90067 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90068 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90069 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90070 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90071 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90072 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 90073 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90074 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90075 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90076 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90077 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90078 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90079 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90080 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90081 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90082 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90083 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90095 | GIR_RootConstrainSelectedInstOperands, |
| 90096 | // GIR_Coverage, 11857, |
| 90097 | GIR_EraseRootFromParent_Done, |
| 90098 | // Label 5009: @279211 |
| 90099 | GIM_Try, /*On fail goto*//*Label 5010*/ GIMT_Encode4(279346), // Rule ID 7377 // |
| 90100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90103 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90106 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90107 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90108 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90109 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90110 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90111 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90112 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90113 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90114 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90116 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90117 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90118 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90119 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90120 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90121 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 90125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 90126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90133 | GIR_RootConstrainSelectedInstOperands, |
| 90134 | // GIR_Coverage, 7377, |
| 90135 | GIR_EraseRootFromParent_Done, |
| 90136 | // Label 5010: @279346 |
| 90137 | GIM_Try, /*On fail goto*//*Label 5011*/ GIMT_Encode4(279481), // Rule ID 11866 // |
| 90138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90143 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90145 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90146 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90147 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90148 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90149 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90150 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90151 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90152 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90153 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90154 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90155 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90156 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90157 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90158 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90159 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 90163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 90164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90171 | GIR_RootConstrainSelectedInstOperands, |
| 90172 | // GIR_Coverage, 11866, |
| 90173 | GIR_EraseRootFromParent_Done, |
| 90174 | // Label 5011: @279481 |
| 90175 | GIM_Try, /*On fail goto*//*Label 5012*/ GIMT_Encode4(279616), // Rule ID 11869 // |
| 90176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90178 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90179 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90180 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90181 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90182 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90183 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90184 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90185 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90186 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90187 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90188 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90189 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90190 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90191 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90192 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90193 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90194 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90195 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90196 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90197 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90209 | GIR_RootConstrainSelectedInstOperands, |
| 90210 | // GIR_Coverage, 11869, |
| 90211 | GIR_EraseRootFromParent_Done, |
| 90212 | // Label 5012: @279616 |
| 90213 | GIM_Try, /*On fail goto*//*Label 5013*/ GIMT_Encode4(279751), // Rule ID 11870 // |
| 90214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90217 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90218 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90219 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90220 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90221 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90222 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90223 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90224 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90225 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90226 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90227 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90228 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90229 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90230 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90231 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90232 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90233 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90234 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90235 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90247 | GIR_RootConstrainSelectedInstOperands, |
| 90248 | // GIR_Coverage, 11870, |
| 90249 | GIR_EraseRootFromParent_Done, |
| 90250 | // Label 5013: @279751 |
| 90251 | GIM_Try, /*On fail goto*//*Label 5014*/ GIMT_Encode4(279886), // Rule ID 7376 // |
| 90252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90255 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90259 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90261 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90262 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90263 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90264 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90265 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90266 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90268 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90269 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90270 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90271 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90272 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90273 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 90277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 90278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90285 | GIR_RootConstrainSelectedInstOperands, |
| 90286 | // GIR_Coverage, 7376, |
| 90287 | GIR_EraseRootFromParent_Done, |
| 90288 | // Label 5014: @279886 |
| 90289 | GIM_Try, /*On fail goto*//*Label 5015*/ GIMT_Encode4(280021), // Rule ID 11851 // |
| 90290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90292 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90293 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90294 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90295 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90296 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90297 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90298 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90299 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90300 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90301 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90302 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90303 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90304 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90305 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90307 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90308 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90309 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90310 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90311 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 90315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 90316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90323 | GIR_RootConstrainSelectedInstOperands, |
| 90324 | // GIR_Coverage, 11851, |
| 90325 | GIR_EraseRootFromParent_Done, |
| 90326 | // Label 5015: @280021 |
| 90327 | GIM_Try, /*On fail goto*//*Label 5016*/ GIMT_Encode4(280156), // Rule ID 11854 // |
| 90328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90330 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90331 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90332 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90333 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90334 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90335 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90336 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90337 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90338 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90339 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90340 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90341 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90342 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90343 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90344 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90345 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90346 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90347 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90348 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90349 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90361 | GIR_RootConstrainSelectedInstOperands, |
| 90362 | // GIR_Coverage, 11854, |
| 90363 | GIR_EraseRootFromParent_Done, |
| 90364 | // Label 5016: @280156 |
| 90365 | GIM_Try, /*On fail goto*//*Label 5017*/ GIMT_Encode4(280291), // Rule ID 11855 // |
| 90366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90371 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90372 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 90373 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90374 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90375 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90376 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 90377 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90378 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90379 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 90380 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 90382 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90383 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90384 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90385 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90386 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90387 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 90393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 90394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 90395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 90396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90399 | GIR_RootConstrainSelectedInstOperands, |
| 90400 | // GIR_Coverage, 11855, |
| 90401 | GIR_EraseRootFromParent_Done, |
| 90402 | // Label 5017: @280291 |
| 90403 | GIM_Try, /*On fail goto*//*Label 5018*/ GIMT_Encode4(280426), // Rule ID 11907 // |
| 90404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90406 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90407 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90408 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90409 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90410 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90411 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90412 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90413 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90414 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90415 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90416 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90417 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90418 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90419 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90420 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90421 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90422 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90423 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90424 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90425 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90437 | GIR_RootConstrainSelectedInstOperands, |
| 90438 | // GIR_Coverage, 11907, |
| 90439 | GIR_EraseRootFromParent_Done, |
| 90440 | // Label 5018: @280426 |
| 90441 | GIM_Try, /*On fail goto*//*Label 5019*/ GIMT_Encode4(280561), // Rule ID 11908 // |
| 90442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90445 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90446 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90447 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90448 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90449 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90450 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90451 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90452 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90453 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90454 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90455 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90456 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90458 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90459 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90460 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90461 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90462 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90463 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90475 | GIR_RootConstrainSelectedInstOperands, |
| 90476 | // GIR_Coverage, 11908, |
| 90477 | GIR_EraseRootFromParent_Done, |
| 90478 | // Label 5019: @280561 |
| 90479 | GIM_Try, /*On fail goto*//*Label 5020*/ GIMT_Encode4(280696), // Rule ID 11909 // |
| 90480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90482 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90483 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90484 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90485 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90486 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90487 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90488 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90489 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90490 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90491 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90492 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90493 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90494 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90495 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90496 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90497 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90498 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90499 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90500 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90501 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90513 | GIR_RootConstrainSelectedInstOperands, |
| 90514 | // GIR_Coverage, 11909, |
| 90515 | GIR_EraseRootFromParent_Done, |
| 90516 | // Label 5020: @280696 |
| 90517 | GIM_Try, /*On fail goto*//*Label 5021*/ GIMT_Encode4(280831), // Rule ID 11910 // |
| 90518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90520 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90521 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90523 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90524 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90525 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90526 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90527 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90528 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90529 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90530 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90531 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90532 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90534 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90535 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90536 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90537 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90538 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90539 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90551 | GIR_RootConstrainSelectedInstOperands, |
| 90552 | // GIR_Coverage, 11910, |
| 90553 | GIR_EraseRootFromParent_Done, |
| 90554 | // Label 5021: @280831 |
| 90555 | GIM_Try, /*On fail goto*//*Label 5022*/ GIMT_Encode4(280966), // Rule ID 11847 // |
| 90556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90558 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90559 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90560 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90561 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90562 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90563 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90564 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90565 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90566 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90567 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90568 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90569 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90570 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90571 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90572 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90573 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90574 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90575 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90576 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90577 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90589 | GIR_RootConstrainSelectedInstOperands, |
| 90590 | // GIR_Coverage, 11847, |
| 90591 | GIR_EraseRootFromParent_Done, |
| 90592 | // Label 5022: @280966 |
| 90593 | GIM_Try, /*On fail goto*//*Label 5023*/ GIMT_Encode4(281101), // Rule ID 11848 // |
| 90594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90600 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90601 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90602 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90603 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90604 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90605 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90606 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90607 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90608 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90609 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90610 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90611 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90612 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90613 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90614 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90615 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90627 | GIR_RootConstrainSelectedInstOperands, |
| 90628 | // GIR_Coverage, 11848, |
| 90629 | GIR_EraseRootFromParent_Done, |
| 90630 | // Label 5023: @281101 |
| 90631 | GIM_Try, /*On fail goto*//*Label 5024*/ GIMT_Encode4(281236), // Rule ID 11849 // |
| 90632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90634 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90635 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90636 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90637 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90638 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90639 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90640 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90641 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90642 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90643 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90644 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90645 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90646 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90648 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90649 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90650 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90651 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90652 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90653 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90665 | GIR_RootConstrainSelectedInstOperands, |
| 90666 | // GIR_Coverage, 11849, |
| 90667 | GIR_EraseRootFromParent_Done, |
| 90668 | // Label 5024: @281236 |
| 90669 | GIM_Try, /*On fail goto*//*Label 5025*/ GIMT_Encode4(281371), // Rule ID 11850 // |
| 90670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90676 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90677 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 90678 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90679 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90680 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90681 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90682 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90683 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90684 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90685 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90686 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90687 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90688 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90689 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90690 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90691 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90703 | GIR_RootConstrainSelectedInstOperands, |
| 90704 | // GIR_Coverage, 11850, |
| 90705 | GIR_EraseRootFromParent_Done, |
| 90706 | // Label 5025: @281371 |
| 90707 | GIM_Try, /*On fail goto*//*Label 5026*/ GIMT_Encode4(281506), // Rule ID 11892 // |
| 90708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90710 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90711 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90712 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90713 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90714 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90715 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90716 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90717 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90718 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90719 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90720 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90721 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90722 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90723 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90724 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90725 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90726 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90727 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90728 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90729 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90741 | GIR_RootConstrainSelectedInstOperands, |
| 90742 | // GIR_Coverage, 11892, |
| 90743 | GIR_EraseRootFromParent_Done, |
| 90744 | // Label 5026: @281506 |
| 90745 | GIM_Try, /*On fail goto*//*Label 5027*/ GIMT_Encode4(281641), // Rule ID 11893 // |
| 90746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90748 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90749 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90750 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90751 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90752 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90753 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90754 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90755 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90756 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90757 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90758 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90759 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90760 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90761 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90762 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90763 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90764 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90765 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90766 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90767 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90779 | GIR_RootConstrainSelectedInstOperands, |
| 90780 | // GIR_Coverage, 11893, |
| 90781 | GIR_EraseRootFromParent_Done, |
| 90782 | // Label 5027: @281641 |
| 90783 | GIM_Try, /*On fail goto*//*Label 5028*/ GIMT_Encode4(281776), // Rule ID 11894 // |
| 90784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90787 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90790 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90791 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90792 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90793 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90795 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90796 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90797 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90798 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90800 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90801 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90802 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90803 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90804 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90805 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90817 | GIR_RootConstrainSelectedInstOperands, |
| 90818 | // GIR_Coverage, 11894, |
| 90819 | GIR_EraseRootFromParent_Done, |
| 90820 | // Label 5028: @281776 |
| 90821 | GIM_Try, /*On fail goto*//*Label 5029*/ GIMT_Encode4(281911), // Rule ID 11895 // |
| 90822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90827 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90828 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90829 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90830 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90831 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90832 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90833 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90834 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90835 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90836 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90839 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90840 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90841 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90842 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90843 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90855 | GIR_RootConstrainSelectedInstOperands, |
| 90856 | // GIR_Coverage, 11895, |
| 90857 | GIR_EraseRootFromParent_Done, |
| 90858 | // Label 5029: @281911 |
| 90859 | GIM_Try, /*On fail goto*//*Label 5030*/ GIMT_Encode4(282046), // Rule ID 11832 // |
| 90860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90862 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90863 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90864 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90865 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90866 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90867 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90868 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90869 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90870 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90871 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90872 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90873 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90874 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90875 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90876 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90877 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90878 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90879 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90880 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90881 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90893 | GIR_RootConstrainSelectedInstOperands, |
| 90894 | // GIR_Coverage, 11832, |
| 90895 | GIR_EraseRootFromParent_Done, |
| 90896 | // Label 5030: @282046 |
| 90897 | GIM_Try, /*On fail goto*//*Label 5031*/ GIMT_Encode4(282181), // Rule ID 11833 // |
| 90898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90900 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90901 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90902 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90903 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90904 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90905 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90906 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90907 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90908 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90909 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90910 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90911 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90912 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90915 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90916 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90917 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90918 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90919 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 90923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 90924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 90925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 90926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90931 | GIR_RootConstrainSelectedInstOperands, |
| 90932 | // GIR_Coverage, 11833, |
| 90933 | GIR_EraseRootFromParent_Done, |
| 90934 | // Label 5031: @282181 |
| 90935 | GIM_Try, /*On fail goto*//*Label 5032*/ GIMT_Encode4(282316), // Rule ID 11834 // |
| 90936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90941 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90942 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90943 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90944 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90945 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90946 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90947 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90948 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90949 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90950 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90951 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90953 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90954 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90955 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90956 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90957 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 90962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 90963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 90964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 90965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 90966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 90969 | GIR_RootConstrainSelectedInstOperands, |
| 90970 | // GIR_Coverage, 11834, |
| 90971 | GIR_EraseRootFromParent_Done, |
| 90972 | // Label 5032: @282316 |
| 90973 | GIM_Try, /*On fail goto*//*Label 5033*/ GIMT_Encode4(282451), // Rule ID 11835 // |
| 90974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 90975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 90976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 90977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 90978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 90979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 90980 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 90981 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 90982 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 90983 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 90984 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 90985 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 90986 | // MIs[3] VOP3Mods:src1:src1_mods |
| 90987 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 90988 | // MIs[3] VOP3Mods:src0:src0_mods |
| 90989 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 90990 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 90991 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 90992 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 90993 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 90994 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 90995 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 90996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 90997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 90998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 90999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 91000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 91003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 91004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91007 | GIR_RootConstrainSelectedInstOperands, |
| 91008 | // GIR_Coverage, 11835, |
| 91009 | GIR_EraseRootFromParent_Done, |
| 91010 | // Label 5033: @282451 |
| 91011 | GIM_Try, /*On fail goto*//*Label 5034*/ GIMT_Encode4(282586), // Rule ID 11903 // |
| 91012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91014 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91015 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91016 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91017 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91018 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91019 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91020 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91021 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91022 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91023 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91024 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91025 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91026 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91027 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91028 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91029 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91030 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91031 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91032 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91033 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91045 | GIR_RootConstrainSelectedInstOperands, |
| 91046 | // GIR_Coverage, 11903, |
| 91047 | GIR_EraseRootFromParent_Done, |
| 91048 | // Label 5034: @282586 |
| 91049 | GIM_Try, /*On fail goto*//*Label 5035*/ GIMT_Encode4(282721), // Rule ID 11904 // |
| 91050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91052 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91053 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91054 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91055 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91056 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91057 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91058 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91059 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91060 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91061 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91062 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91063 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91064 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91065 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91066 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91067 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91068 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91069 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91070 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91071 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91083 | GIR_RootConstrainSelectedInstOperands, |
| 91084 | // GIR_Coverage, 11904, |
| 91085 | GIR_EraseRootFromParent_Done, |
| 91086 | // Label 5035: @282721 |
| 91087 | GIM_Try, /*On fail goto*//*Label 5036*/ GIMT_Encode4(282856), // Rule ID 11905 // |
| 91088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91091 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91092 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91093 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91094 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91095 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91096 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91097 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91098 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91099 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91100 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91101 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91102 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91103 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91104 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91105 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91106 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91107 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91108 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91109 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91121 | GIR_RootConstrainSelectedInstOperands, |
| 91122 | // GIR_Coverage, 11905, |
| 91123 | GIR_EraseRootFromParent_Done, |
| 91124 | // Label 5036: @282856 |
| 91125 | GIM_Try, /*On fail goto*//*Label 5037*/ GIMT_Encode4(282991), // Rule ID 11906 // |
| 91126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91129 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91131 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91132 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91133 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91134 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91135 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91136 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91137 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91138 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91139 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91140 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91141 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91143 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91144 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91145 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91146 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91147 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91159 | GIR_RootConstrainSelectedInstOperands, |
| 91160 | // GIR_Coverage, 11906, |
| 91161 | GIR_EraseRootFromParent_Done, |
| 91162 | // Label 5037: @282991 |
| 91163 | GIM_Try, /*On fail goto*//*Label 5038*/ GIMT_Encode4(283126), // Rule ID 11843 // |
| 91164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91166 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91167 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91168 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91169 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91170 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91171 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91172 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91173 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91174 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91175 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91176 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91177 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91178 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91179 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91180 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91181 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91182 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91183 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91184 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91185 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91197 | GIR_RootConstrainSelectedInstOperands, |
| 91198 | // GIR_Coverage, 11843, |
| 91199 | GIR_EraseRootFromParent_Done, |
| 91200 | // Label 5038: @283126 |
| 91201 | GIM_Try, /*On fail goto*//*Label 5039*/ GIMT_Encode4(283261), // Rule ID 11844 // |
| 91202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91204 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91205 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91206 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91207 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91208 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91209 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91210 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91211 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91212 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91213 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91214 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91215 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91216 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91217 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91218 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91219 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91220 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91221 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91222 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91223 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91235 | GIR_RootConstrainSelectedInstOperands, |
| 91236 | // GIR_Coverage, 11844, |
| 91237 | GIR_EraseRootFromParent_Done, |
| 91238 | // Label 5039: @283261 |
| 91239 | GIM_Try, /*On fail goto*//*Label 5040*/ GIMT_Encode4(283396), // Rule ID 11845 // |
| 91240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91242 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91243 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91244 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91245 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91246 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91247 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91248 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91249 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91250 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91251 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91252 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91253 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91254 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91255 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91256 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91257 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91258 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91259 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91260 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91261 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91273 | GIR_RootConstrainSelectedInstOperands, |
| 91274 | // GIR_Coverage, 11845, |
| 91275 | GIR_EraseRootFromParent_Done, |
| 91276 | // Label 5040: @283396 |
| 91277 | GIM_Try, /*On fail goto*//*Label 5041*/ GIMT_Encode4(283531), // Rule ID 11846 // |
| 91278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91283 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91284 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91285 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91286 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91287 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91288 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91289 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91290 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91291 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91292 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91293 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91294 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91295 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91296 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91297 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91298 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91299 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91311 | GIR_RootConstrainSelectedInstOperands, |
| 91312 | // GIR_Coverage, 11846, |
| 91313 | GIR_EraseRootFromParent_Done, |
| 91314 | // Label 5041: @283531 |
| 91315 | GIM_Try, /*On fail goto*//*Label 5042*/ GIMT_Encode4(283666), // Rule ID 11888 // |
| 91316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91322 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91323 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91324 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91325 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91326 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91327 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91328 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91329 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91330 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91332 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91333 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91334 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91335 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91336 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91337 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91349 | GIR_RootConstrainSelectedInstOperands, |
| 91350 | // GIR_Coverage, 11888, |
| 91351 | GIR_EraseRootFromParent_Done, |
| 91352 | // Label 5042: @283666 |
| 91353 | GIM_Try, /*On fail goto*//*Label 5043*/ GIMT_Encode4(283801), // Rule ID 11889 // |
| 91354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91360 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91361 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91362 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91363 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91364 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91365 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91366 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91367 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91368 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91369 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91370 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91371 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91372 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91373 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91374 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91375 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91387 | GIR_RootConstrainSelectedInstOperands, |
| 91388 | // GIR_Coverage, 11889, |
| 91389 | GIR_EraseRootFromParent_Done, |
| 91390 | // Label 5043: @283801 |
| 91391 | GIM_Try, /*On fail goto*//*Label 5044*/ GIMT_Encode4(283936), // Rule ID 11890 // |
| 91392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91397 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91398 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91399 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91400 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91401 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91402 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91403 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91404 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91405 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91406 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91407 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91408 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91409 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91410 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91411 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91412 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91413 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91425 | GIR_RootConstrainSelectedInstOperands, |
| 91426 | // GIR_Coverage, 11890, |
| 91427 | GIR_EraseRootFromParent_Done, |
| 91428 | // Label 5044: @283936 |
| 91429 | GIM_Try, /*On fail goto*//*Label 5045*/ GIMT_Encode4(284071), // Rule ID 11891 // |
| 91430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91433 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91435 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91437 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91438 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91439 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91440 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91441 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91442 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91443 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91444 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91445 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91446 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91447 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91448 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91449 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91450 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91451 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91463 | GIR_RootConstrainSelectedInstOperands, |
| 91464 | // GIR_Coverage, 11891, |
| 91465 | GIR_EraseRootFromParent_Done, |
| 91466 | // Label 5045: @284071 |
| 91467 | GIM_Try, /*On fail goto*//*Label 5046*/ GIMT_Encode4(284206), // Rule ID 11828 // |
| 91468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91470 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91471 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91472 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91473 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91474 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91475 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91476 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91477 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91478 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91479 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91480 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91481 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91482 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91483 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91484 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91485 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91486 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91487 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91488 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91489 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91501 | GIR_RootConstrainSelectedInstOperands, |
| 91502 | // GIR_Coverage, 11828, |
| 91503 | GIR_EraseRootFromParent_Done, |
| 91504 | // Label 5046: @284206 |
| 91505 | GIM_Try, /*On fail goto*//*Label 5047*/ GIMT_Encode4(284341), // Rule ID 11829 // |
| 91506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91511 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91512 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91514 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91515 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91516 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91517 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91518 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91519 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91520 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91521 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91522 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91523 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91524 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91525 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91526 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91527 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91539 | GIR_RootConstrainSelectedInstOperands, |
| 91540 | // GIR_Coverage, 11829, |
| 91541 | GIR_EraseRootFromParent_Done, |
| 91542 | // Label 5047: @284341 |
| 91543 | GIM_Try, /*On fail goto*//*Label 5048*/ GIMT_Encode4(284476), // Rule ID 11830 // |
| 91544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91545 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91546 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91547 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91548 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91549 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91550 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91551 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91552 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91553 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91554 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91555 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91556 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91557 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91558 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91559 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91560 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91561 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91562 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91563 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91564 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91565 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91577 | GIR_RootConstrainSelectedInstOperands, |
| 91578 | // GIR_Coverage, 11830, |
| 91579 | GIR_EraseRootFromParent_Done, |
| 91580 | // Label 5048: @284476 |
| 91581 | GIM_Try, /*On fail goto*//*Label 5049*/ GIMT_Encode4(284611), // Rule ID 11831 // |
| 91582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91584 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91585 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91586 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91587 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91588 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 91589 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91590 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91591 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91592 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 91593 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91594 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91595 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 91596 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91597 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 91598 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91599 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91600 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91601 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91602 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91603 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91615 | GIR_RootConstrainSelectedInstOperands, |
| 91616 | // GIR_Coverage, 11831, |
| 91617 | GIR_EraseRootFromParent_Done, |
| 91618 | // Label 5049: @284611 |
| 91619 | GIM_Try, /*On fail goto*//*Label 5050*/ GIMT_Encode4(284746), // Rule ID 11837 // |
| 91620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91623 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91626 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91627 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91628 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91629 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91630 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91631 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91632 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91633 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91634 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91635 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91637 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91638 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91639 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91640 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91641 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91653 | GIR_RootConstrainSelectedInstOperands, |
| 91654 | // GIR_Coverage, 11837, |
| 91655 | GIR_EraseRootFromParent_Done, |
| 91656 | // Label 5050: @284746 |
| 91657 | GIM_Try, /*On fail goto*//*Label 5051*/ GIMT_Encode4(284881), // Rule ID 11838 // |
| 91658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91662 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91663 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91664 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91665 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91666 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91667 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91668 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91669 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91670 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91671 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91672 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91673 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91674 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91675 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91676 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91677 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91678 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91679 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91691 | GIR_RootConstrainSelectedInstOperands, |
| 91692 | // GIR_Coverage, 11838, |
| 91693 | GIR_EraseRootFromParent_Done, |
| 91694 | // Label 5051: @284881 |
| 91695 | GIM_Try, /*On fail goto*//*Label 5052*/ GIMT_Encode4(285016), // Rule ID 11841 // |
| 91696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91698 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91699 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91700 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91701 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91702 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91703 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91704 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91705 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91706 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91707 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91708 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91709 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91710 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91711 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91712 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91713 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91714 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91715 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91716 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91717 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91729 | GIR_RootConstrainSelectedInstOperands, |
| 91730 | // GIR_Coverage, 11841, |
| 91731 | GIR_EraseRootFromParent_Done, |
| 91732 | // Label 5052: @285016 |
| 91733 | GIM_Try, /*On fail goto*//*Label 5053*/ GIMT_Encode4(285151), // Rule ID 11842 // |
| 91734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91736 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91737 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91738 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91739 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91740 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91741 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91742 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91743 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91744 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91745 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91746 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91747 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91748 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91749 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91750 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91751 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91752 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91753 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91754 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91755 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91767 | GIR_RootConstrainSelectedInstOperands, |
| 91768 | // GIR_Coverage, 11842, |
| 91769 | GIR_EraseRootFromParent_Done, |
| 91770 | // Label 5053: @285151 |
| 91771 | GIM_Try, /*On fail goto*//*Label 5054*/ GIMT_Encode4(285286), // Rule ID 11822 // |
| 91772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91777 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91778 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91779 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91780 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91781 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91782 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91783 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91784 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91785 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91786 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91787 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91788 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91789 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91790 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91791 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91792 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91793 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91805 | GIR_RootConstrainSelectedInstOperands, |
| 91806 | // GIR_Coverage, 11822, |
| 91807 | GIR_EraseRootFromParent_Done, |
| 91808 | // Label 5054: @285286 |
| 91809 | GIM_Try, /*On fail goto*//*Label 5055*/ GIMT_Encode4(285421), // Rule ID 11823 // |
| 91810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91815 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91816 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91817 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91818 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91819 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91820 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91821 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91822 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91823 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91824 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91825 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91826 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91827 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91828 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91829 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91830 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91831 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91843 | GIR_RootConstrainSelectedInstOperands, |
| 91844 | // GIR_Coverage, 11823, |
| 91845 | GIR_EraseRootFromParent_Done, |
| 91846 | // Label 5055: @285421 |
| 91847 | GIM_Try, /*On fail goto*//*Label 5056*/ GIMT_Encode4(285556), // Rule ID 11826 // |
| 91848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91850 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91851 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91852 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91853 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91854 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91855 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91856 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91857 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91858 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91859 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91860 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91861 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91862 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91863 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91864 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91865 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91866 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91867 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91868 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91869 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91881 | GIR_RootConstrainSelectedInstOperands, |
| 91882 | // GIR_Coverage, 11826, |
| 91883 | GIR_EraseRootFromParent_Done, |
| 91884 | // Label 5056: @285556 |
| 91885 | GIM_Try, /*On fail goto*//*Label 5057*/ GIMT_Encode4(285691), // Rule ID 11827 // |
| 91886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91889 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91892 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91893 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91894 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91895 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91896 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 91897 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 91898 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91899 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91900 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91901 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91903 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91904 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91905 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91906 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91907 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 91911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 91912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 91913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 91914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91919 | GIR_RootConstrainSelectedInstOperands, |
| 91920 | // GIR_Coverage, 11827, |
| 91921 | GIR_EraseRootFromParent_Done, |
| 91922 | // Label 5057: @285691 |
| 91923 | GIM_Try, /*On fail goto*//*Label 5058*/ GIMT_Encode4(285826), // Rule ID 7375 // |
| 91924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91928 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91929 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91930 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91931 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91932 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91933 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91934 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 91935 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91936 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91937 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91938 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91939 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91940 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91941 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91942 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91943 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91944 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91945 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91957 | GIR_RootConstrainSelectedInstOperands, |
| 91958 | // GIR_Coverage, 7375, |
| 91959 | GIR_EraseRootFromParent_Done, |
| 91960 | // Label 5058: @285826 |
| 91961 | GIM_Try, /*On fail goto*//*Label 5059*/ GIMT_Encode4(285961), // Rule ID 11836 // |
| 91962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 91963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 91964 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 91965 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 91966 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 91967 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 91968 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 91969 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 91970 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 91971 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 91972 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 91973 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 91974 | // MIs[3] VOP3Mods:src1:src1_mods |
| 91975 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 91976 | // MIs[3] VOP3Mods:src0:src0_mods |
| 91977 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 91978 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 91979 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 91980 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 91981 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 91982 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 91983 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 91984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 91985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 91986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 91987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 91988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 91989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 91990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 91991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 91992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 91995 | GIR_RootConstrainSelectedInstOperands, |
| 91996 | // GIR_Coverage, 11836, |
| 91997 | GIR_EraseRootFromParent_Done, |
| 91998 | // Label 5059: @285961 |
| 91999 | GIM_Try, /*On fail goto*//*Label 5060*/ GIMT_Encode4(286096), // Rule ID 11839 // |
| 92000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92005 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92006 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92007 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92008 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92009 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92010 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92011 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92012 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92013 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92014 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92015 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92016 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92017 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92018 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92019 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92020 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92021 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92033 | GIR_RootConstrainSelectedInstOperands, |
| 92034 | // GIR_Coverage, 11839, |
| 92035 | GIR_EraseRootFromParent_Done, |
| 92036 | // Label 5060: @286096 |
| 92037 | GIM_Try, /*On fail goto*//*Label 5061*/ GIMT_Encode4(286231), // Rule ID 11840 // |
| 92038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92041 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92042 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92043 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92044 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92045 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92046 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92047 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92048 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92049 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92050 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92051 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92052 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92053 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92054 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92055 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92056 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92057 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92058 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92059 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92071 | GIR_RootConstrainSelectedInstOperands, |
| 92072 | // GIR_Coverage, 11840, |
| 92073 | GIR_EraseRootFromParent_Done, |
| 92074 | // Label 5061: @286231 |
| 92075 | GIM_Try, /*On fail goto*//*Label 5062*/ GIMT_Encode4(286366), // Rule ID 7374 // |
| 92076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92078 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92079 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92080 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92081 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92082 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92083 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92084 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92085 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92086 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92087 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92088 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92089 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92090 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92091 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92092 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92093 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92094 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92095 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92096 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92097 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92109 | GIR_RootConstrainSelectedInstOperands, |
| 92110 | // GIR_Coverage, 7374, |
| 92111 | GIR_EraseRootFromParent_Done, |
| 92112 | // Label 5062: @286366 |
| 92113 | GIM_Try, /*On fail goto*//*Label 5063*/ GIMT_Encode4(286501), // Rule ID 11821 // |
| 92114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92121 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92122 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92123 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92124 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92125 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92126 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92127 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92128 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92129 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92130 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92131 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92132 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92133 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92134 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92135 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92147 | GIR_RootConstrainSelectedInstOperands, |
| 92148 | // GIR_Coverage, 11821, |
| 92149 | GIR_EraseRootFromParent_Done, |
| 92150 | // Label 5063: @286501 |
| 92151 | GIM_Try, /*On fail goto*//*Label 5064*/ GIMT_Encode4(286636), // Rule ID 11824 // |
| 92152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92155 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92156 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92157 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92158 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92159 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92160 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92161 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92162 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92163 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92164 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92165 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92166 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92167 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92169 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92170 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92171 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92172 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92173 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92185 | GIR_RootConstrainSelectedInstOperands, |
| 92186 | // GIR_Coverage, 11824, |
| 92187 | GIR_EraseRootFromParent_Done, |
| 92188 | // Label 5064: @286636 |
| 92189 | GIM_Try, /*On fail goto*//*Label 5065*/ GIMT_Encode4(286771), // Rule ID 11825 // |
| 92190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92191 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92193 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92194 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92195 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92196 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92197 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92198 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92199 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92200 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92201 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92202 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92203 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92204 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92205 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92206 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92207 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92208 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92209 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92210 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92211 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92223 | GIR_RootConstrainSelectedInstOperands, |
| 92224 | // GIR_Coverage, 11825, |
| 92225 | GIR_EraseRootFromParent_Done, |
| 92226 | // Label 5065: @286771 |
| 92227 | GIM_Try, /*On fail goto*//*Label 5066*/ GIMT_Encode4(286906), // Rule ID 11807 // |
| 92228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92230 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92231 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92232 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92233 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92234 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92235 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92236 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92237 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92238 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92239 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92240 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92241 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92242 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92243 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92244 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92245 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92246 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92247 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92248 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92249 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92261 | GIR_RootConstrainSelectedInstOperands, |
| 92262 | // GIR_Coverage, 11807, |
| 92263 | GIR_EraseRootFromParent_Done, |
| 92264 | // Label 5066: @286906 |
| 92265 | GIM_Try, /*On fail goto*//*Label 5067*/ GIMT_Encode4(287041), // Rule ID 11808 // |
| 92266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92272 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92273 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92274 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92275 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92276 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92277 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92278 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92279 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92280 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92281 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92282 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92283 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92284 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92285 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92286 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92287 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92299 | GIR_RootConstrainSelectedInstOperands, |
| 92300 | // GIR_Coverage, 11808, |
| 92301 | GIR_EraseRootFromParent_Done, |
| 92302 | // Label 5067: @287041 |
| 92303 | GIM_Try, /*On fail goto*//*Label 5068*/ GIMT_Encode4(287176), // Rule ID 11811 // |
| 92304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92307 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92309 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92311 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92313 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92314 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92315 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92316 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92317 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92318 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92319 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92320 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92321 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92322 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92323 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92324 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92325 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92337 | GIR_RootConstrainSelectedInstOperands, |
| 92338 | // GIR_Coverage, 11811, |
| 92339 | GIR_EraseRootFromParent_Done, |
| 92340 | // Label 5068: @287176 |
| 92341 | GIM_Try, /*On fail goto*//*Label 5069*/ GIMT_Encode4(287311), // Rule ID 11812 // |
| 92342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92344 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92345 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92346 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92347 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92348 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92349 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92350 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92351 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92352 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92353 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92354 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92355 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92356 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92357 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92358 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92359 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92360 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92361 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92362 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92363 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92375 | GIR_RootConstrainSelectedInstOperands, |
| 92376 | // GIR_Coverage, 11812, |
| 92377 | GIR_EraseRootFromParent_Done, |
| 92378 | // Label 5069: @287311 |
| 92379 | GIM_Try, /*On fail goto*//*Label 5070*/ GIMT_Encode4(287446), // Rule ID 11792 // |
| 92380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92383 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92385 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92386 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92387 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92388 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92389 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92390 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92391 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92392 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92393 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92394 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92395 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92396 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92397 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92398 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92399 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92400 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92401 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92413 | GIR_RootConstrainSelectedInstOperands, |
| 92414 | // GIR_Coverage, 11792, |
| 92415 | GIR_EraseRootFromParent_Done, |
| 92416 | // Label 5070: @287446 |
| 92417 | GIM_Try, /*On fail goto*//*Label 5071*/ GIMT_Encode4(287581), // Rule ID 11793 // |
| 92418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92420 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92421 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92422 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92423 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92424 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92425 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92426 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92427 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92428 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92429 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92430 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92431 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92432 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92433 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92434 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92435 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92436 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92437 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92438 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92439 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92451 | GIR_RootConstrainSelectedInstOperands, |
| 92452 | // GIR_Coverage, 11793, |
| 92453 | GIR_EraseRootFromParent_Done, |
| 92454 | // Label 5071: @287581 |
| 92455 | GIM_Try, /*On fail goto*//*Label 5072*/ GIMT_Encode4(287716), // Rule ID 11796 // |
| 92456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92458 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92459 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92460 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92461 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92462 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92463 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92464 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92465 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92466 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92467 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92468 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92469 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92470 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92471 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92472 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92473 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92474 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92475 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92476 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92477 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92489 | GIR_RootConstrainSelectedInstOperands, |
| 92490 | // GIR_Coverage, 11796, |
| 92491 | GIR_EraseRootFromParent_Done, |
| 92492 | // Label 5072: @287716 |
| 92493 | GIM_Try, /*On fail goto*//*Label 5073*/ GIMT_Encode4(287851), // Rule ID 11797 // |
| 92494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92496 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92497 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92498 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92500 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92501 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92502 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92503 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92504 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 92505 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92506 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92507 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92508 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92509 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92510 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92511 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92512 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92513 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92514 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92515 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92527 | GIR_RootConstrainSelectedInstOperands, |
| 92528 | // GIR_Coverage, 11797, |
| 92529 | GIR_EraseRootFromParent_Done, |
| 92530 | // Label 5073: @287851 |
| 92531 | GIM_Try, /*On fail goto*//*Label 5074*/ GIMT_Encode4(287986), // Rule ID 7373 // |
| 92532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92534 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92535 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92536 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92537 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92538 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92539 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92540 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92541 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92542 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92543 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92544 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92545 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92546 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92547 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92548 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92549 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92550 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92551 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92552 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92553 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92565 | GIR_RootConstrainSelectedInstOperands, |
| 92566 | // GIR_Coverage, 7373, |
| 92567 | GIR_EraseRootFromParent_Done, |
| 92568 | // Label 5074: @287986 |
| 92569 | GIM_Try, /*On fail goto*//*Label 5075*/ GIMT_Encode4(288121), // Rule ID 11806 // |
| 92570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92572 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92573 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92574 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92575 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92576 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92577 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92578 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92579 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92580 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92581 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92582 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92584 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92585 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92586 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92587 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92588 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92589 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92590 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92591 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92603 | GIR_RootConstrainSelectedInstOperands, |
| 92604 | // GIR_Coverage, 11806, |
| 92605 | GIR_EraseRootFromParent_Done, |
| 92606 | // Label 5075: @288121 |
| 92607 | GIM_Try, /*On fail goto*//*Label 5076*/ GIMT_Encode4(288256), // Rule ID 11809 // |
| 92608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92610 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92611 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92612 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92613 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92614 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92615 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92616 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92617 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92618 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92619 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92620 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92622 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92623 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92624 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92625 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92626 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92627 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92628 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92629 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92641 | GIR_RootConstrainSelectedInstOperands, |
| 92642 | // GIR_Coverage, 11809, |
| 92643 | GIR_EraseRootFromParent_Done, |
| 92644 | // Label 5076: @288256 |
| 92645 | GIM_Try, /*On fail goto*//*Label 5077*/ GIMT_Encode4(288391), // Rule ID 11810 // |
| 92646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92652 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92653 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92654 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92655 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92656 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92657 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92658 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92659 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92660 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92661 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92662 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92663 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92664 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92665 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92666 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92667 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92679 | GIR_RootConstrainSelectedInstOperands, |
| 92680 | // GIR_Coverage, 11810, |
| 92681 | GIR_EraseRootFromParent_Done, |
| 92682 | // Label 5077: @288391 |
| 92683 | GIM_Try, /*On fail goto*//*Label 5078*/ GIMT_Encode4(288526), // Rule ID 7372 // |
| 92684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92688 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92689 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92690 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92691 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92692 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92693 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92694 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92695 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92696 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92698 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92699 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92701 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92702 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92703 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92704 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92705 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92717 | GIR_RootConstrainSelectedInstOperands, |
| 92718 | // GIR_Coverage, 7372, |
| 92719 | GIR_EraseRootFromParent_Done, |
| 92720 | // Label 5078: @288526 |
| 92721 | GIM_Try, /*On fail goto*//*Label 5079*/ GIMT_Encode4(288661), // Rule ID 11791 // |
| 92722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92724 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92725 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92726 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92727 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92728 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92729 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92730 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92731 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92732 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92733 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92734 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92735 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92736 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92737 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92738 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92739 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92740 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92741 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92742 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92743 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 92747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 92748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92755 | GIR_RootConstrainSelectedInstOperands, |
| 92756 | // GIR_Coverage, 11791, |
| 92757 | GIR_EraseRootFromParent_Done, |
| 92758 | // Label 5079: @288661 |
| 92759 | GIM_Try, /*On fail goto*//*Label 5080*/ GIMT_Encode4(288796), // Rule ID 11794 // |
| 92760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92763 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92765 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92766 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92767 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92768 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92769 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92770 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92771 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92772 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92773 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92774 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92775 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92776 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92777 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92778 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92779 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92780 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92781 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92793 | GIR_RootConstrainSelectedInstOperands, |
| 92794 | // GIR_Coverage, 11794, |
| 92795 | GIR_EraseRootFromParent_Done, |
| 92796 | // Label 5080: @288796 |
| 92797 | GIM_Try, /*On fail goto*//*Label 5081*/ GIMT_Encode4(288931), // Rule ID 11795 // |
| 92798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92800 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92801 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92802 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92803 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92804 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 92805 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92806 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92807 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92808 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 92809 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 92810 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92811 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 92812 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92813 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 92814 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92815 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92816 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92817 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92818 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92819 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 92825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 92826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 92827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 92828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92831 | GIR_RootConstrainSelectedInstOperands, |
| 92832 | // GIR_Coverage, 11795, |
| 92833 | GIR_EraseRootFromParent_Done, |
| 92834 | // Label 5081: @288931 |
| 92835 | GIM_Try, /*On fail goto*//*Label 5082*/ GIMT_Encode4(289066), // Rule ID 11877 // |
| 92836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92839 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92841 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92842 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 92843 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92844 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92845 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92846 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 92847 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92848 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 92850 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92851 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 92852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92853 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92854 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92855 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92856 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92857 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 92863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 92864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 92865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 92866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92869 | GIR_RootConstrainSelectedInstOperands, |
| 92870 | // GIR_Coverage, 11877, |
| 92871 | GIR_EraseRootFromParent_Done, |
| 92872 | // Label 5082: @289066 |
| 92873 | GIM_Try, /*On fail goto*//*Label 5083*/ GIMT_Encode4(289201), // Rule ID 11878 // |
| 92874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92878 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92879 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 92881 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92883 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92884 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 92885 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92886 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92887 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 92888 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92889 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 92890 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92891 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92892 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92893 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92894 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92895 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 92899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 92900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 92901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 92902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 92903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 92904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92907 | GIR_RootConstrainSelectedInstOperands, |
| 92908 | // GIR_Coverage, 11878, |
| 92909 | GIR_EraseRootFromParent_Done, |
| 92910 | // Label 5083: @289201 |
| 92911 | GIM_Try, /*On fail goto*//*Label 5084*/ GIMT_Encode4(289336), // Rule ID 11879 // |
| 92912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92915 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92916 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92917 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92918 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 92919 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92920 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92921 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92922 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 92923 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92924 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92925 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 92926 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92927 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 92928 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92929 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92930 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92931 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92932 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92933 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 92937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 92938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 92941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 92942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92945 | GIR_RootConstrainSelectedInstOperands, |
| 92946 | // GIR_Coverage, 11879, |
| 92947 | GIR_EraseRootFromParent_Done, |
| 92948 | // Label 5084: @289336 |
| 92949 | GIM_Try, /*On fail goto*//*Label 5085*/ GIMT_Encode4(289471), // Rule ID 11880 // |
| 92950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92953 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92954 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92955 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92956 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 92957 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92958 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92959 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92960 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 92961 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 92962 | // MIs[3] VOP3Mods:src1:src1_mods |
| 92963 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 92964 | // MIs[3] VOP3Mods:src0:src0_mods |
| 92965 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 92966 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 92967 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 92968 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 92969 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 92970 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 92971 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 92972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 92973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 92974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 92975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 92976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 92977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 92978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 92979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 92980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 92983 | GIR_RootConstrainSelectedInstOperands, |
| 92984 | // GIR_Coverage, 11880, |
| 92985 | GIR_EraseRootFromParent_Done, |
| 92986 | // Label 5085: @289471 |
| 92987 | GIM_Try, /*On fail goto*//*Label 5086*/ GIMT_Encode4(289606), // Rule ID 11817 // |
| 92988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 92989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 92990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 92991 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 92992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 92993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 92994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 92995 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 92996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 92997 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 92998 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 92999 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93000 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93002 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93003 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93004 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93005 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93006 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93007 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93008 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93009 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93021 | GIR_RootConstrainSelectedInstOperands, |
| 93022 | // GIR_Coverage, 11817, |
| 93023 | GIR_EraseRootFromParent_Done, |
| 93024 | // Label 5086: @289606 |
| 93025 | GIM_Try, /*On fail goto*//*Label 5087*/ GIMT_Encode4(289741), // Rule ID 11818 // |
| 93026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93028 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93029 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93030 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93031 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93032 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93033 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93034 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93035 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93036 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93037 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93038 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93039 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93040 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93041 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93042 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93043 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93044 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93045 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93046 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93047 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93059 | GIR_RootConstrainSelectedInstOperands, |
| 93060 | // GIR_Coverage, 11818, |
| 93061 | GIR_EraseRootFromParent_Done, |
| 93062 | // Label 5087: @289741 |
| 93063 | GIM_Try, /*On fail goto*//*Label 5088*/ GIMT_Encode4(289876), // Rule ID 11819 // |
| 93064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93067 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93068 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93069 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93070 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93071 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93072 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93073 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93074 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93075 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93076 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93077 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93078 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93079 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93080 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93081 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93082 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93083 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93084 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93085 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93097 | GIR_RootConstrainSelectedInstOperands, |
| 93098 | // GIR_Coverage, 11819, |
| 93099 | GIR_EraseRootFromParent_Done, |
| 93100 | // Label 5088: @289876 |
| 93101 | GIM_Try, /*On fail goto*//*Label 5089*/ GIMT_Encode4(290011), // Rule ID 11820 // |
| 93102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93104 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93105 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93106 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93107 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93108 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93109 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93110 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93111 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93112 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93113 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93114 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93116 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93117 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93118 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93119 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93120 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93121 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93122 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93123 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93135 | GIR_RootConstrainSelectedInstOperands, |
| 93136 | // GIR_Coverage, 11820, |
| 93137 | GIR_EraseRootFromParent_Done, |
| 93138 | // Label 5089: @290011 |
| 93139 | GIM_Try, /*On fail goto*//*Label 5090*/ GIMT_Encode4(290146), // Rule ID 11862 // |
| 93140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93142 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93143 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93144 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93145 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93146 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93147 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93148 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93149 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93150 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93151 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93152 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93153 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93154 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93155 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93156 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93157 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93158 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93159 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93160 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93161 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93173 | GIR_RootConstrainSelectedInstOperands, |
| 93174 | // GIR_Coverage, 11862, |
| 93175 | GIR_EraseRootFromParent_Done, |
| 93176 | // Label 5090: @290146 |
| 93177 | GIM_Try, /*On fail goto*//*Label 5091*/ GIMT_Encode4(290281), // Rule ID 11863 // |
| 93178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93183 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93184 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93185 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93186 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93187 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93188 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93189 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93190 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93191 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93192 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93193 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93194 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93195 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93196 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93197 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93198 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93199 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93211 | GIR_RootConstrainSelectedInstOperands, |
| 93212 | // GIR_Coverage, 11863, |
| 93213 | GIR_EraseRootFromParent_Done, |
| 93214 | // Label 5091: @290281 |
| 93215 | GIM_Try, /*On fail goto*//*Label 5092*/ GIMT_Encode4(290416), // Rule ID 11864 // |
| 93216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93218 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93219 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93220 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93221 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93222 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93223 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93224 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93225 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93226 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93227 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93228 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93229 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93230 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93231 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93232 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93233 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93234 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93235 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93236 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93237 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93249 | GIR_RootConstrainSelectedInstOperands, |
| 93250 | // GIR_Coverage, 11864, |
| 93251 | GIR_EraseRootFromParent_Done, |
| 93252 | // Label 5092: @290416 |
| 93253 | GIM_Try, /*On fail goto*//*Label 5093*/ GIMT_Encode4(290551), // Rule ID 11865 // |
| 93254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93259 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93260 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93261 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93262 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93263 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93264 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93265 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93266 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93268 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93269 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93270 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93271 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93272 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93273 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93274 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93275 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93287 | GIR_RootConstrainSelectedInstOperands, |
| 93288 | // GIR_Coverage, 11865, |
| 93289 | GIR_EraseRootFromParent_Done, |
| 93290 | // Label 5093: @290551 |
| 93291 | GIM_Try, /*On fail goto*//*Label 5094*/ GIMT_Encode4(290686), // Rule ID 11802 // |
| 93292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93295 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93297 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93298 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93299 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93300 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93301 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93302 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93303 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93304 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93305 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93306 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93307 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93308 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93309 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93310 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93311 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93312 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93313 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93325 | GIR_RootConstrainSelectedInstOperands, |
| 93326 | // GIR_Coverage, 11802, |
| 93327 | GIR_EraseRootFromParent_Done, |
| 93328 | // Label 5094: @290686 |
| 93329 | GIM_Try, /*On fail goto*//*Label 5095*/ GIMT_Encode4(290821), // Rule ID 11803 // |
| 93330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93335 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93336 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93337 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93338 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93339 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93340 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93341 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93342 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93343 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93344 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93345 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93346 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93347 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93348 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93349 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93350 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93351 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 93357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 93358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93363 | GIR_RootConstrainSelectedInstOperands, |
| 93364 | // GIR_Coverage, 11803, |
| 93365 | GIR_EraseRootFromParent_Done, |
| 93366 | // Label 5095: @290821 |
| 93367 | GIM_Try, /*On fail goto*//*Label 5096*/ GIMT_Encode4(290956), // Rule ID 11804 // |
| 93368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93373 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93375 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93376 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93377 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93378 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93379 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93380 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93382 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93383 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93384 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93385 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93386 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93387 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93388 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93389 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93401 | GIR_RootConstrainSelectedInstOperands, |
| 93402 | // GIR_Coverage, 11804, |
| 93403 | GIR_EraseRootFromParent_Done, |
| 93404 | // Label 5096: @290956 |
| 93405 | GIM_Try, /*On fail goto*//*Label 5097*/ GIMT_Encode4(291091), // Rule ID 11805 // |
| 93406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93408 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93409 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93410 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93411 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93412 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 93413 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93414 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93415 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93416 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93417 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93418 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93419 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93420 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93421 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93422 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93423 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93424 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93425 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93426 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93427 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 93431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 93432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 93435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 93436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93439 | GIR_RootConstrainSelectedInstOperands, |
| 93440 | // GIR_Coverage, 11805, |
| 93441 | GIR_EraseRootFromParent_Done, |
| 93442 | // Label 5097: @291091 |
| 93443 | GIM_Try, /*On fail goto*//*Label 5098*/ GIMT_Encode4(291226), // Rule ID 11873 // |
| 93444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93449 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93450 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93451 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93452 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93453 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93454 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93455 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93456 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93458 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93459 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93460 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93461 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93462 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93463 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93464 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93465 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93477 | GIR_RootConstrainSelectedInstOperands, |
| 93478 | // GIR_Coverage, 11873, |
| 93479 | GIR_EraseRootFromParent_Done, |
| 93480 | // Label 5098: @291226 |
| 93481 | GIM_Try, /*On fail goto*//*Label 5099*/ GIMT_Encode4(291361), // Rule ID 11874 // |
| 93482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93484 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93485 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93486 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93487 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93488 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93489 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93490 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93491 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93492 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93493 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93494 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93495 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93496 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93497 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93498 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93499 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93500 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93501 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93502 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93503 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93515 | GIR_RootConstrainSelectedInstOperands, |
| 93516 | // GIR_Coverage, 11874, |
| 93517 | GIR_EraseRootFromParent_Done, |
| 93518 | // Label 5099: @291361 |
| 93519 | GIM_Try, /*On fail goto*//*Label 5100*/ GIMT_Encode4(291496), // Rule ID 11875 // |
| 93520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93522 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93523 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93524 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93525 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93526 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93527 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93528 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93530 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93531 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93532 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93534 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93535 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93536 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93537 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93538 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93539 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93540 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93541 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93553 | GIR_RootConstrainSelectedInstOperands, |
| 93554 | // GIR_Coverage, 11875, |
| 93555 | GIR_EraseRootFromParent_Done, |
| 93556 | // Label 5100: @291496 |
| 93557 | GIM_Try, /*On fail goto*//*Label 5101*/ GIMT_Encode4(291631), // Rule ID 11876 // |
| 93558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93564 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93565 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93566 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93567 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93568 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93569 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93570 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93571 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93572 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93573 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93574 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93575 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93576 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93577 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93578 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93579 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93591 | GIR_RootConstrainSelectedInstOperands, |
| 93592 | // GIR_Coverage, 11876, |
| 93593 | GIR_EraseRootFromParent_Done, |
| 93594 | // Label 5101: @291631 |
| 93595 | GIM_Try, /*On fail goto*//*Label 5102*/ GIMT_Encode4(291766), // Rule ID 11813 // |
| 93596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93597 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93598 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93599 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93600 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93601 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93602 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93603 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93604 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93605 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93606 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93607 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93608 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93609 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93610 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93611 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93612 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93613 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93614 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93615 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93616 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93617 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93629 | GIR_RootConstrainSelectedInstOperands, |
| 93630 | // GIR_Coverage, 11813, |
| 93631 | GIR_EraseRootFromParent_Done, |
| 93632 | // Label 5102: @291766 |
| 93633 | GIM_Try, /*On fail goto*//*Label 5103*/ GIMT_Encode4(291901), // Rule ID 11814 // |
| 93634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93639 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93641 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93644 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93645 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93646 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93648 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93649 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93650 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93651 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93652 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93653 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93654 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93655 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93667 | GIR_RootConstrainSelectedInstOperands, |
| 93668 | // GIR_Coverage, 11814, |
| 93669 | GIR_EraseRootFromParent_Done, |
| 93670 | // Label 5103: @291901 |
| 93671 | GIM_Try, /*On fail goto*//*Label 5104*/ GIMT_Encode4(292036), // Rule ID 11815 // |
| 93672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93674 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93675 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93676 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93677 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93678 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93679 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93680 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93681 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93682 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93683 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93684 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93685 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93686 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93687 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93688 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93689 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93690 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93691 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93692 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93693 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93705 | GIR_RootConstrainSelectedInstOperands, |
| 93706 | // GIR_Coverage, 11815, |
| 93707 | GIR_EraseRootFromParent_Done, |
| 93708 | // Label 5104: @292036 |
| 93709 | GIM_Try, /*On fail goto*//*Label 5105*/ GIMT_Encode4(292171), // Rule ID 11816 // |
| 93710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93715 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93716 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93717 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 93718 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93719 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93720 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93721 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93722 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93723 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93724 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93725 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93726 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93727 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93728 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93729 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93730 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93731 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93743 | GIR_RootConstrainSelectedInstOperands, |
| 93744 | // GIR_Coverage, 11816, |
| 93745 | GIR_EraseRootFromParent_Done, |
| 93746 | // Label 5105: @292171 |
| 93747 | GIM_Try, /*On fail goto*//*Label 5106*/ GIMT_Encode4(292306), // Rule ID 11858 // |
| 93748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93751 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93752 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93753 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93754 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93755 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93756 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93757 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93758 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93759 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93760 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93761 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93762 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93763 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93764 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93765 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93766 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93767 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93768 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93769 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93781 | GIR_RootConstrainSelectedInstOperands, |
| 93782 | // GIR_Coverage, 11858, |
| 93783 | GIR_EraseRootFromParent_Done, |
| 93784 | // Label 5106: @292306 |
| 93785 | GIM_Try, /*On fail goto*//*Label 5107*/ GIMT_Encode4(292441), // Rule ID 11859 // |
| 93786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93789 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93791 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93792 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93793 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93794 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93795 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93796 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93797 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93798 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93800 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93801 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93802 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93803 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93804 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93805 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93806 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93807 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93819 | GIR_RootConstrainSelectedInstOperands, |
| 93820 | // GIR_Coverage, 11859, |
| 93821 | GIR_EraseRootFromParent_Done, |
| 93822 | // Label 5107: @292441 |
| 93823 | GIM_Try, /*On fail goto*//*Label 5108*/ GIMT_Encode4(292576), // Rule ID 11860 // |
| 93824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93826 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93827 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93828 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93829 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93830 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93831 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93832 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93833 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93834 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93835 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93836 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93838 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93839 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93840 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93841 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93842 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93843 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93844 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93845 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93857 | GIR_RootConstrainSelectedInstOperands, |
| 93858 | // GIR_Coverage, 11860, |
| 93859 | GIR_EraseRootFromParent_Done, |
| 93860 | // Label 5108: @292576 |
| 93861 | GIM_Try, /*On fail goto*//*Label 5109*/ GIMT_Encode4(292711), // Rule ID 11861 // |
| 93862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93865 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93866 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93868 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93869 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93870 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93871 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93872 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93873 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 93874 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93875 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93876 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93877 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93878 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93879 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93880 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93881 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93882 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93883 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 93887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 93888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 93889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 93890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93895 | GIR_RootConstrainSelectedInstOperands, |
| 93896 | // GIR_Coverage, 11861, |
| 93897 | GIR_EraseRootFromParent_Done, |
| 93898 | // Label 5109: @292711 |
| 93899 | GIM_Try, /*On fail goto*//*Label 5110*/ GIMT_Encode4(292846), // Rule ID 11798 // |
| 93900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93903 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93904 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93905 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93906 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93907 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93908 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93909 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93910 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93911 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93912 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93914 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93915 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93916 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93917 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93918 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93919 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93920 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93921 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93933 | GIR_RootConstrainSelectedInstOperands, |
| 93934 | // GIR_Coverage, 11798, |
| 93935 | GIR_EraseRootFromParent_Done, |
| 93936 | // Label 5110: @292846 |
| 93937 | GIM_Try, /*On fail goto*//*Label 5111*/ GIMT_Encode4(292981), // Rule ID 11799 // |
| 93938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93940 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93941 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93942 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93943 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93944 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93945 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93946 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93947 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93948 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93949 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93950 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93951 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93952 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93953 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93955 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93956 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93957 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93958 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93959 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 93962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 93963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 93964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 93965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 93966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 93967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 93968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 93971 | GIR_RootConstrainSelectedInstOperands, |
| 93972 | // GIR_Coverage, 11799, |
| 93973 | GIR_EraseRootFromParent_Done, |
| 93974 | // Label 5111: @292981 |
| 93975 | GIM_Try, /*On fail goto*//*Label 5112*/ GIMT_Encode4(293116), // Rule ID 11800 // |
| 93976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 93977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 93978 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 93979 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93980 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 93981 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 93982 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 93983 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 93984 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 93985 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 93986 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 93987 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 93988 | // MIs[3] VOP3Mods:src0:src0_mods |
| 93989 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 93990 | // MIs[3] VOP3Mods:src1:src1_mods |
| 93991 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 93992 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 93993 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 93994 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 93995 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 93996 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 93997 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 93998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 93999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94009 | GIR_RootConstrainSelectedInstOperands, |
| 94010 | // GIR_Coverage, 11800, |
| 94011 | GIR_EraseRootFromParent_Done, |
| 94012 | // Label 5112: @293116 |
| 94013 | GIM_Try, /*On fail goto*//*Label 5113*/ GIMT_Encode4(293251), // Rule ID 11801 // |
| 94014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 94015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94016 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94017 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94018 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 94020 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 94021 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94022 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 94023 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 94024 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 94025 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94026 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94027 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 94028 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94029 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 94030 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94031 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94032 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94033 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94034 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94035 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 94037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94047 | GIR_RootConstrainSelectedInstOperands, |
| 94048 | // GIR_Coverage, 11801, |
| 94049 | GIR_EraseRootFromParent_Done, |
| 94050 | // Label 5113: @293251 |
| 94051 | GIM_Try, /*On fail goto*//*Label 5114*/ GIMT_Encode4(293363), // Rule ID 11946 // |
| 94052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 94055 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 94056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94057 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 94058 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94059 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 94060 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 94061 | GIM_CheckHasOneUse, /*MI*/2, |
| 94062 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 94063 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 94064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94065 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94066 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94067 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 94073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 94074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 94075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 94076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94078 | GIR_RootConstrainSelectedInstOperands, |
| 94079 | // GIR_Coverage, 11946, |
| 94080 | GIR_EraseRootFromParent_Done, |
| 94081 | // Label 5114: @293363 |
| 94082 | GIM_Try, /*On fail goto*//*Label 5115*/ GIMT_Encode4(293475), // Rule ID 11945 // |
| 94083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94085 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 94086 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 94087 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94088 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 94089 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94090 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 94091 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 94092 | GIM_CheckHasOneUse, /*MI*/2, |
| 94093 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 94094 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 94095 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94096 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94097 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94098 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94100 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 94104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 94105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 94106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 94107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94109 | GIR_RootConstrainSelectedInstOperands, |
| 94110 | // GIR_Coverage, 11945, |
| 94111 | GIR_EraseRootFromParent_Done, |
| 94112 | // Label 5115: @293475 |
| 94113 | GIM_Try, /*On fail goto*//*Label 5116*/ GIMT_Encode4(293587), // Rule ID 7415 // |
| 94114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 94118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94119 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 94120 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94121 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 94122 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 94123 | GIM_CheckHasOneUse, /*MI*/2, |
| 94124 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 94125 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 94126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94127 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94128 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94129 | // (fminnum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94140 | GIR_RootConstrainSelectedInstOperands, |
| 94141 | // GIR_Coverage, 7415, |
| 94142 | GIR_EraseRootFromParent_Done, |
| 94143 | // Label 5116: @293587 |
| 94144 | GIM_Try, /*On fail goto*//*Label 5117*/ GIMT_Encode4(293699), // Rule ID 7414 // |
| 94145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 94149 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94150 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 94151 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94152 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 94153 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 94154 | GIM_CheckHasOneUse, /*MI*/2, |
| 94155 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 94156 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 94157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94158 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94159 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94160 | // (fminnum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94171 | GIR_RootConstrainSelectedInstOperands, |
| 94172 | // GIR_Coverage, 7414, |
| 94173 | GIR_EraseRootFromParent_Done, |
| 94174 | // Label 5117: @293699 |
| 94175 | GIM_Try, /*On fail goto*//*Label 5118*/ GIMT_Encode4(293795), // Rule ID 11930 // |
| 94176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94178 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 94179 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94180 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94181 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 94182 | GIM_CheckHasOneUse, /*MI*/1, |
| 94183 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 94184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94185 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94186 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94187 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 94193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 94194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 94195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 94196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94198 | GIR_RootConstrainSelectedInstOperands, |
| 94199 | // GIR_Coverage, 11930, |
| 94200 | GIR_EraseRootFromParent_Done, |
| 94201 | // Label 5118: @293795 |
| 94202 | GIM_Try, /*On fail goto*//*Label 5119*/ GIMT_Encode4(293891), // Rule ID 11929 // |
| 94203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94205 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 94206 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94207 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94208 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 94209 | GIM_CheckHasOneUse, /*MI*/1, |
| 94210 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 94211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94212 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94213 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94214 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94215 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94216 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 94220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 94221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 94222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 94223 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94225 | GIR_RootConstrainSelectedInstOperands, |
| 94226 | // GIR_Coverage, 11929, |
| 94227 | GIR_EraseRootFromParent_Done, |
| 94228 | // Label 5119: @293891 |
| 94229 | GIM_Try, /*On fail goto*//*Label 5120*/ GIMT_Encode4(293987), // Rule ID 7399 // |
| 94230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94232 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94233 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94234 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94235 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 94236 | GIM_CheckHasOneUse, /*MI*/1, |
| 94237 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 94238 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94239 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94240 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94241 | // (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94243 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94250 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94252 | GIR_RootConstrainSelectedInstOperands, |
| 94253 | // GIR_Coverage, 7399, |
| 94254 | GIR_EraseRootFromParent_Done, |
| 94255 | // Label 5120: @293987 |
| 94256 | GIM_Try, /*On fail goto*//*Label 5121*/ GIMT_Encode4(294083), // Rule ID 7398 // |
| 94257 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 94258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94259 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94260 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94261 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 94262 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 94263 | GIM_CheckHasOneUse, /*MI*/1, |
| 94264 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 94265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94266 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94267 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94268 | // (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 94270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94279 | GIR_RootConstrainSelectedInstOperands, |
| 94280 | // GIR_Coverage, 7398, |
| 94281 | GIR_EraseRootFromParent_Done, |
| 94282 | // Label 5121: @294083 |
| 94283 | GIM_Try, /*On fail goto*//*Label 5122*/ GIMT_Encode4(294118), // Rule ID 103 // |
| 94284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 94285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 94286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 94287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 94288 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18519), |
| 94289 | // (fminnum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18519>> => (S_MIN_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 94290 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F16), |
| 94291 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 94292 | GIR_RootConstrainSelectedInstOperands, |
| 94293 | // GIR_Coverage, 103, |
| 94294 | GIR_Done, |
| 94295 | // Label 5122: @294118 |
| 94296 | GIM_Try, /*On fail goto*//*Label 5123*/ GIMT_Encode4(294181), // Rule ID 816 // |
| 94297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 94298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 94300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94301 | // (fminnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 94302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64), |
| 94303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 94305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 94307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 94309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 94310 | GIR_RootConstrainSelectedInstOperands, |
| 94311 | // GIR_Coverage, 816, |
| 94312 | GIR_EraseRootFromParent_Done, |
| 94313 | // Label 5123: @294181 |
| 94314 | GIM_Try, /*On fail goto*//*Label 5124*/ GIMT_Encode4(294244), // Rule ID 820 // |
| 94315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 94316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 94318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94319 | // (fminnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 94320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64), |
| 94321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 94323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 94325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 94327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 94328 | GIR_RootConstrainSelectedInstOperands, |
| 94329 | // GIR_Coverage, 820, |
| 94330 | GIR_EraseRootFromParent_Done, |
| 94331 | // Label 5124: @294244 |
| 94332 | GIM_Try, /*On fail goto*//*Label 5125*/ GIMT_Encode4(294307), // Rule ID 8075 // |
| 94333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 94334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94336 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 94337 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 94338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64), |
| 94339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 94341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 94343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 94345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 94346 | GIR_RootConstrainSelectedInstOperands, |
| 94347 | // GIR_Coverage, 8075, |
| 94348 | GIR_EraseRootFromParent_Done, |
| 94349 | // Label 5125: @294307 |
| 94350 | GIM_Try, /*On fail goto*//*Label 5126*/ GIMT_Encode4(294370), // Rule ID 8077 // |
| 94351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 94352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 94355 | // (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 94356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64), |
| 94357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 94359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 94361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 94363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 94364 | GIR_RootConstrainSelectedInstOperands, |
| 94365 | // GIR_Coverage, 8077, |
| 94366 | GIR_EraseRootFromParent_Done, |
| 94367 | // Label 5126: @294370 |
| 94368 | GIM_Try, /*On fail goto*//*Label 5127*/ GIMT_Encode4(294432), // Rule ID 818 // |
| 94369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 94370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 94371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 94372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 94373 | // (fminnum:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 94374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64), |
| 94375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 94377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 94379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94383 | GIR_RootConstrainSelectedInstOperands, |
| 94384 | // GIR_Coverage, 818, |
| 94385 | GIR_EraseRootFromParent_Done, |
| 94386 | // Label 5127: @294432 |
| 94387 | GIM_Reject, |
| 94388 | // Label 4985: @294433 |
| 94389 | GIM_Reject, |
| 94390 | // Label 4981: @294434 |
| 94391 | GIM_Try, /*On fail goto*//*Label 5128*/ GIMT_Encode4(311945), |
| 94392 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 94393 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 94394 | GIM_Try, /*On fail goto*//*Label 5129*/ GIMT_Encode4(294574), // Rule ID 11387 // |
| 94395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94396 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94397 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94398 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94399 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94400 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94401 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94402 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94403 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94404 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94405 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94406 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94407 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94408 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94409 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94410 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94411 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94412 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94413 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94414 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94415 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94426 | GIR_RootConstrainSelectedInstOperands, |
| 94427 | // GIR_Coverage, 11387, |
| 94428 | GIR_EraseRootFromParent_Done, |
| 94429 | // Label 5129: @294574 |
| 94430 | GIM_Try, /*On fail goto*//*Label 5130*/ GIMT_Encode4(294703), // Rule ID 11388 // |
| 94431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94433 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94435 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94437 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94438 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94439 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94440 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94441 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94442 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94443 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94444 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94445 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94446 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94447 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94448 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94449 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94450 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94451 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94462 | GIR_RootConstrainSelectedInstOperands, |
| 94463 | // GIR_Coverage, 11388, |
| 94464 | GIR_EraseRootFromParent_Done, |
| 94465 | // Label 5130: @294703 |
| 94466 | GIM_Try, /*On fail goto*//*Label 5131*/ GIMT_Encode4(294832), // Rule ID 11391 // |
| 94467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94469 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94470 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94471 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94472 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94473 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94474 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94475 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94476 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94477 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94478 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94479 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94480 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94481 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94482 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94483 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94484 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94485 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94486 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94487 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94498 | GIR_RootConstrainSelectedInstOperands, |
| 94499 | // GIR_Coverage, 11391, |
| 94500 | GIR_EraseRootFromParent_Done, |
| 94501 | // Label 5131: @294832 |
| 94502 | GIM_Try, /*On fail goto*//*Label 5132*/ GIMT_Encode4(294961), // Rule ID 11392 // |
| 94503 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94504 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94505 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94506 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94507 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94508 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94509 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94510 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94511 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94512 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94513 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94514 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94515 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94516 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94517 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94518 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94519 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94520 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94521 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94522 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94523 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94534 | GIR_RootConstrainSelectedInstOperands, |
| 94535 | // GIR_Coverage, 11392, |
| 94536 | GIR_EraseRootFromParent_Done, |
| 94537 | // Label 5132: @294961 |
| 94538 | GIM_Try, /*On fail goto*//*Label 5133*/ GIMT_Encode4(295090), // Rule ID 11372 // |
| 94539 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94540 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94541 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94542 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94543 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94544 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94545 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94546 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94547 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94548 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94549 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94550 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94551 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94552 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94553 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94554 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94555 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94556 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94557 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94558 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94559 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94570 | GIR_RootConstrainSelectedInstOperands, |
| 94571 | // GIR_Coverage, 11372, |
| 94572 | GIR_EraseRootFromParent_Done, |
| 94573 | // Label 5133: @295090 |
| 94574 | GIM_Try, /*On fail goto*//*Label 5134*/ GIMT_Encode4(295219), // Rule ID 11373 // |
| 94575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94576 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94577 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94578 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94579 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94580 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94581 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94582 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94583 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94584 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94585 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94586 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94587 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94588 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94589 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94590 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94591 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94592 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94593 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94594 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94595 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94597 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94604 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94606 | GIR_RootConstrainSelectedInstOperands, |
| 94607 | // GIR_Coverage, 11373, |
| 94608 | GIR_EraseRootFromParent_Done, |
| 94609 | // Label 5134: @295219 |
| 94610 | GIM_Try, /*On fail goto*//*Label 5135*/ GIMT_Encode4(295348), // Rule ID 11376 // |
| 94611 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94612 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94613 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94614 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94615 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94616 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94617 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94618 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94619 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94620 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94621 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94622 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94623 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94624 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94625 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94626 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94627 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94628 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94629 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94630 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94631 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94632 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94633 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94642 | GIR_RootConstrainSelectedInstOperands, |
| 94643 | // GIR_Coverage, 11376, |
| 94644 | GIR_EraseRootFromParent_Done, |
| 94645 | // Label 5135: @295348 |
| 94646 | GIM_Try, /*On fail goto*//*Label 5136*/ GIMT_Encode4(295477), // Rule ID 11377 // |
| 94647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94652 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94653 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94654 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94655 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94656 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94657 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94658 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94659 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94660 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94661 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94662 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94663 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94664 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94665 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94666 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94667 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94678 | GIR_RootConstrainSelectedInstOperands, |
| 94679 | // GIR_Coverage, 11377, |
| 94680 | GIR_EraseRootFromParent_Done, |
| 94681 | // Label 5136: @295477 |
| 94682 | GIM_Try, /*On fail goto*//*Label 5137*/ GIMT_Encode4(295606), // Rule ID 7345 // |
| 94683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94687 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94689 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94691 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94692 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94693 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94694 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94695 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94696 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94699 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94700 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94701 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94702 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94703 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94714 | GIR_RootConstrainSelectedInstOperands, |
| 94715 | // GIR_Coverage, 7345, |
| 94716 | GIR_EraseRootFromParent_Done, |
| 94717 | // Label 5137: @295606 |
| 94718 | GIM_Try, /*On fail goto*//*Label 5138*/ GIMT_Encode4(295735), // Rule ID 11386 // |
| 94719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94720 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94721 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94722 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94723 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94724 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94725 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94726 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94727 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94728 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94729 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94730 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94731 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94732 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94733 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94734 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94735 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94736 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94737 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94738 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94739 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94750 | GIR_RootConstrainSelectedInstOperands, |
| 94751 | // GIR_Coverage, 11386, |
| 94752 | GIR_EraseRootFromParent_Done, |
| 94753 | // Label 5138: @295735 |
| 94754 | GIM_Try, /*On fail goto*//*Label 5139*/ GIMT_Encode4(295864), // Rule ID 11389 // |
| 94755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94756 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94757 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94758 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94759 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94760 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94761 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94762 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94763 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94764 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94765 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94766 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94767 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94768 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94769 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94770 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94771 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94772 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94773 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94774 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94775 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94786 | GIR_RootConstrainSelectedInstOperands, |
| 94787 | // GIR_Coverage, 11389, |
| 94788 | GIR_EraseRootFromParent_Done, |
| 94789 | // Label 5139: @295864 |
| 94790 | GIM_Try, /*On fail goto*//*Label 5140*/ GIMT_Encode4(295993), // Rule ID 11390 // |
| 94791 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94792 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94793 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94794 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94795 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94796 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94797 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94798 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94799 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94800 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94801 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94802 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94803 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94804 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94805 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94806 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94807 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94808 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94809 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94810 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94811 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94813 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94820 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94822 | GIR_RootConstrainSelectedInstOperands, |
| 94823 | // GIR_Coverage, 11390, |
| 94824 | GIR_EraseRootFromParent_Done, |
| 94825 | // Label 5140: @295993 |
| 94826 | GIM_Try, /*On fail goto*//*Label 5141*/ GIMT_Encode4(296122), // Rule ID 7344 // |
| 94827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94831 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94832 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94833 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94834 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94835 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94836 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94837 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94838 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94839 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94840 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94841 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94842 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94843 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94844 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94845 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94846 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94847 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94858 | GIR_RootConstrainSelectedInstOperands, |
| 94859 | // GIR_Coverage, 7344, |
| 94860 | GIR_EraseRootFromParent_Done, |
| 94861 | // Label 5141: @296122 |
| 94862 | GIM_Try, /*On fail goto*//*Label 5142*/ GIMT_Encode4(296251), // Rule ID 11371 // |
| 94863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94865 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94866 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94868 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94869 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94870 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94871 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94872 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94873 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94874 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94875 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94876 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94877 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94878 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94879 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94880 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94881 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94882 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94883 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94894 | GIR_RootConstrainSelectedInstOperands, |
| 94895 | // GIR_Coverage, 11371, |
| 94896 | GIR_EraseRootFromParent_Done, |
| 94897 | // Label 5142: @296251 |
| 94898 | GIM_Try, /*On fail goto*//*Label 5143*/ GIMT_Encode4(296380), // Rule ID 11374 // |
| 94899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94900 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94901 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94902 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94903 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94904 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94905 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94906 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94907 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94908 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94909 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94910 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94911 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94912 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94915 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94916 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94917 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94918 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94919 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94930 | GIR_RootConstrainSelectedInstOperands, |
| 94931 | // GIR_Coverage, 11374, |
| 94932 | GIR_EraseRootFromParent_Done, |
| 94933 | // Label 5143: @296380 |
| 94934 | GIM_Try, /*On fail goto*//*Label 5144*/ GIMT_Encode4(296509), // Rule ID 11375 // |
| 94935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94936 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94937 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94938 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94939 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94940 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94941 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94942 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94943 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94944 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 94945 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 94946 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94947 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94948 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94949 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94950 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94951 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94952 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94953 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94954 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94955 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 94959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 94960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 94961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 94962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 94964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 94966 | GIR_RootConstrainSelectedInstOperands, |
| 94967 | // GIR_Coverage, 11375, |
| 94968 | GIR_EraseRootFromParent_Done, |
| 94969 | // Label 5144: @296509 |
| 94970 | GIM_Try, /*On fail goto*//*Label 5145*/ GIMT_Encode4(296638), // Rule ID 11357 // |
| 94971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 94972 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 94973 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 94974 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 94975 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 94976 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 94977 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 94978 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 94979 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 94980 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 94981 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 94982 | // MIs[3] VOP3Mods:src0:src0_mods |
| 94983 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 94984 | // MIs[3] VOP3Mods:src1:src1_mods |
| 94985 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 94986 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 94987 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 94988 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 94989 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 94990 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 94991 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 94992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 94993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 94994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 94995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 94996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 94997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 94998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 94999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95002 | GIR_RootConstrainSelectedInstOperands, |
| 95003 | // GIR_Coverage, 11357, |
| 95004 | GIR_EraseRootFromParent_Done, |
| 95005 | // Label 5145: @296638 |
| 95006 | GIM_Try, /*On fail goto*//*Label 5146*/ GIMT_Encode4(296767), // Rule ID 11358 // |
| 95007 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95008 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95009 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95010 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95011 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95012 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95013 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95014 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95015 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95016 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95017 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95018 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95019 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95020 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95021 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95022 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95023 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95024 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95025 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95026 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95027 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95038 | GIR_RootConstrainSelectedInstOperands, |
| 95039 | // GIR_Coverage, 11358, |
| 95040 | GIR_EraseRootFromParent_Done, |
| 95041 | // Label 5146: @296767 |
| 95042 | GIM_Try, /*On fail goto*//*Label 5147*/ GIMT_Encode4(296896), // Rule ID 11361 // |
| 95043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95044 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95045 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95046 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95047 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95048 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95049 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95050 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95051 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95052 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95053 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95054 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95055 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95056 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95057 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95058 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95059 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95060 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95061 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95062 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95063 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95074 | GIR_RootConstrainSelectedInstOperands, |
| 95075 | // GIR_Coverage, 11361, |
| 95076 | GIR_EraseRootFromParent_Done, |
| 95077 | // Label 5147: @296896 |
| 95078 | GIM_Try, /*On fail goto*//*Label 5148*/ GIMT_Encode4(297025), // Rule ID 11362 // |
| 95079 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95080 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95081 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95082 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95083 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95084 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95085 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95086 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95087 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95088 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95089 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95090 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95091 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95092 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95093 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95094 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95095 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95096 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95097 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95098 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95099 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95110 | GIR_RootConstrainSelectedInstOperands, |
| 95111 | // GIR_Coverage, 11362, |
| 95112 | GIR_EraseRootFromParent_Done, |
| 95113 | // Label 5148: @297025 |
| 95114 | GIM_Try, /*On fail goto*//*Label 5149*/ GIMT_Encode4(297154), // Rule ID 11342 // |
| 95115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95121 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95122 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95123 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95124 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95125 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95126 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95127 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95128 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95129 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95130 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95131 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95132 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95133 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95134 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95135 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95146 | GIR_RootConstrainSelectedInstOperands, |
| 95147 | // GIR_Coverage, 11342, |
| 95148 | GIR_EraseRootFromParent_Done, |
| 95149 | // Label 5149: @297154 |
| 95150 | GIM_Try, /*On fail goto*//*Label 5150*/ GIMT_Encode4(297283), // Rule ID 11343 // |
| 95151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95152 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95153 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95154 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95155 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95156 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95157 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95158 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95159 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95160 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95161 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95162 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95163 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95164 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95165 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95166 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95167 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95168 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95169 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95170 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95171 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95182 | GIR_RootConstrainSelectedInstOperands, |
| 95183 | // GIR_Coverage, 11343, |
| 95184 | GIR_EraseRootFromParent_Done, |
| 95185 | // Label 5150: @297283 |
| 95186 | GIM_Try, /*On fail goto*//*Label 5151*/ GIMT_Encode4(297412), // Rule ID 11346 // |
| 95187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95189 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95190 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95191 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95192 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95193 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95194 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95195 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95196 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95197 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95198 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95199 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95200 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95201 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95202 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95203 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95204 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95205 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95206 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95207 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95218 | GIR_RootConstrainSelectedInstOperands, |
| 95219 | // GIR_Coverage, 11346, |
| 95220 | GIR_EraseRootFromParent_Done, |
| 95221 | // Label 5151: @297412 |
| 95222 | GIM_Try, /*On fail goto*//*Label 5152*/ GIMT_Encode4(297541), // Rule ID 11347 // |
| 95223 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95224 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95225 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95226 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95227 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95228 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95229 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95230 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95231 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95232 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 95233 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95234 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95235 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95236 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95237 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95238 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95239 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95240 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95241 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95242 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95243 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95245 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95254 | GIR_RootConstrainSelectedInstOperands, |
| 95255 | // GIR_Coverage, 11347, |
| 95256 | GIR_EraseRootFromParent_Done, |
| 95257 | // Label 5152: @297541 |
| 95258 | GIM_Try, /*On fail goto*//*Label 5153*/ GIMT_Encode4(297670), // Rule ID 7343 // |
| 95259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95260 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95261 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95262 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95263 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95264 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95265 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95266 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95267 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95268 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95269 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95270 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95271 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95272 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95273 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95274 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95275 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95276 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95277 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95278 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95279 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95288 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95290 | GIR_RootConstrainSelectedInstOperands, |
| 95291 | // GIR_Coverage, 7343, |
| 95292 | GIR_EraseRootFromParent_Done, |
| 95293 | // Label 5153: @297670 |
| 95294 | GIM_Try, /*On fail goto*//*Label 5154*/ GIMT_Encode4(297799), // Rule ID 11356 // |
| 95295 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95296 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95297 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95298 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95299 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95300 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95301 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95302 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95303 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95304 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95305 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95306 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95307 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95308 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95309 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95310 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95311 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95312 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95313 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95314 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95315 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95326 | GIR_RootConstrainSelectedInstOperands, |
| 95327 | // GIR_Coverage, 11356, |
| 95328 | GIR_EraseRootFromParent_Done, |
| 95329 | // Label 5154: @297799 |
| 95330 | GIM_Try, /*On fail goto*//*Label 5155*/ GIMT_Encode4(297928), // Rule ID 11359 // |
| 95331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95335 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95336 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95337 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95338 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95339 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95340 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95341 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95342 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95343 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95344 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95345 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95346 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95347 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95348 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95349 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95350 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95351 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95362 | GIR_RootConstrainSelectedInstOperands, |
| 95363 | // GIR_Coverage, 11359, |
| 95364 | GIR_EraseRootFromParent_Done, |
| 95365 | // Label 5155: @297928 |
| 95366 | GIM_Try, /*On fail goto*//*Label 5156*/ GIMT_Encode4(298057), // Rule ID 11360 // |
| 95367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95371 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95372 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95373 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95374 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95375 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95376 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95377 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95378 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95379 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95380 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95382 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95383 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95384 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95385 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95386 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95387 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95398 | GIR_RootConstrainSelectedInstOperands, |
| 95399 | // GIR_Coverage, 11360, |
| 95400 | GIR_EraseRootFromParent_Done, |
| 95401 | // Label 5156: @298057 |
| 95402 | GIM_Try, /*On fail goto*//*Label 5157*/ GIMT_Encode4(298186), // Rule ID 7342 // |
| 95403 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95404 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95405 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95406 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95407 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95408 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95409 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95410 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95411 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95412 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95413 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95414 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95415 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95416 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95417 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95418 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95419 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95420 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95421 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95422 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95423 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95434 | GIR_RootConstrainSelectedInstOperands, |
| 95435 | // GIR_Coverage, 7342, |
| 95436 | GIR_EraseRootFromParent_Done, |
| 95437 | // Label 5157: @298186 |
| 95438 | GIM_Try, /*On fail goto*//*Label 5158*/ GIMT_Encode4(298315), // Rule ID 11341 // |
| 95439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95440 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95441 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95442 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95443 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95444 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95445 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95446 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95447 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95448 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95449 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95450 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95451 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95452 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95453 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95454 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95455 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95456 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95457 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95458 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95459 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 95463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 95464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95470 | GIR_RootConstrainSelectedInstOperands, |
| 95471 | // GIR_Coverage, 11341, |
| 95472 | GIR_EraseRootFromParent_Done, |
| 95473 | // Label 5158: @298315 |
| 95474 | GIM_Try, /*On fail goto*//*Label 5159*/ GIMT_Encode4(298444), // Rule ID 11344 // |
| 95475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95476 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95477 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95478 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95479 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95481 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95482 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95483 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95484 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95485 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95486 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95487 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95488 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95489 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95490 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95491 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95492 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95493 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95494 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95495 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95506 | GIR_RootConstrainSelectedInstOperands, |
| 95507 | // GIR_Coverage, 11344, |
| 95508 | GIR_EraseRootFromParent_Done, |
| 95509 | // Label 5159: @298444 |
| 95510 | GIM_Try, /*On fail goto*//*Label 5160*/ GIMT_Encode4(298573), // Rule ID 11345 // |
| 95511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95512 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95513 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95514 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95515 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95516 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 95517 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95518 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95519 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95520 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 95521 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95522 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95523 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 95524 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95525 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 95526 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95527 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95528 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95529 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95530 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95531 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95533 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 95537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 95538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 95539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 95540 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95542 | GIR_RootConstrainSelectedInstOperands, |
| 95543 | // GIR_Coverage, 11345, |
| 95544 | GIR_EraseRootFromParent_Done, |
| 95545 | // Label 5160: @298573 |
| 95546 | GIM_Try, /*On fail goto*//*Label 5161*/ GIMT_Encode4(298702), // Rule ID 11397 // |
| 95547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95548 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95549 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95550 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95551 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95552 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95553 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95554 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95555 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95556 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95557 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95558 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95559 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95560 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95561 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95562 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95563 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95564 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95565 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95566 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95567 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95578 | GIR_RootConstrainSelectedInstOperands, |
| 95579 | // GIR_Coverage, 11397, |
| 95580 | GIR_EraseRootFromParent_Done, |
| 95581 | // Label 5161: @298702 |
| 95582 | GIM_Try, /*On fail goto*//*Label 5162*/ GIMT_Encode4(298831), // Rule ID 11398 // |
| 95583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95584 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95585 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95586 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95587 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95588 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95589 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95590 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95591 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95592 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95593 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95594 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95595 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95596 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95597 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95598 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95599 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95600 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95601 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95602 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95603 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95614 | GIR_RootConstrainSelectedInstOperands, |
| 95615 | // GIR_Coverage, 11398, |
| 95616 | GIR_EraseRootFromParent_Done, |
| 95617 | // Label 5162: @298831 |
| 95618 | GIM_Try, /*On fail goto*//*Label 5163*/ GIMT_Encode4(298960), // Rule ID 11399 // |
| 95619 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95620 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95621 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95622 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95623 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95624 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95625 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95626 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95627 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95628 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95629 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95630 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95631 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95632 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95633 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95634 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95635 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95636 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95637 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95638 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95639 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95640 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95641 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95648 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95650 | GIR_RootConstrainSelectedInstOperands, |
| 95651 | // GIR_Coverage, 11399, |
| 95652 | GIR_EraseRootFromParent_Done, |
| 95653 | // Label 5163: @298960 |
| 95654 | GIM_Try, /*On fail goto*//*Label 5164*/ GIMT_Encode4(299089), // Rule ID 11400 // |
| 95655 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95656 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95657 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95658 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95659 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95660 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95661 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95662 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95663 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95664 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95665 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95666 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95667 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95668 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95669 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95670 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95671 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95672 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95673 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95674 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95675 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95686 | GIR_RootConstrainSelectedInstOperands, |
| 95687 | // GIR_Coverage, 11400, |
| 95688 | GIR_EraseRootFromParent_Done, |
| 95689 | // Label 5164: @299089 |
| 95690 | GIM_Try, /*On fail goto*//*Label 5165*/ GIMT_Encode4(299218), // Rule ID 11337 // |
| 95691 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95692 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95693 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95694 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95695 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95696 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95697 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95698 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95699 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95700 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95701 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95702 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95703 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95704 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95705 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95706 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95707 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95708 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95709 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95710 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95711 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95722 | GIR_RootConstrainSelectedInstOperands, |
| 95723 | // GIR_Coverage, 11337, |
| 95724 | GIR_EraseRootFromParent_Done, |
| 95725 | // Label 5165: @299218 |
| 95726 | GIM_Try, /*On fail goto*//*Label 5166*/ GIMT_Encode4(299347), // Rule ID 11338 // |
| 95727 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95728 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95729 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95730 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95731 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95732 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95733 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95734 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95735 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95736 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95737 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95738 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95739 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95740 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95741 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95742 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95743 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95744 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95745 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95746 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95747 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95748 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95749 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95756 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95758 | GIR_RootConstrainSelectedInstOperands, |
| 95759 | // GIR_Coverage, 11338, |
| 95760 | GIR_EraseRootFromParent_Done, |
| 95761 | // Label 5166: @299347 |
| 95762 | GIM_Try, /*On fail goto*//*Label 5167*/ GIMT_Encode4(299476), // Rule ID 11339 // |
| 95763 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95764 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95765 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95766 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95767 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95768 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95769 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95770 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95771 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95772 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95773 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95774 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95775 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95776 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95777 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95778 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95779 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95780 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95781 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95782 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95783 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95794 | GIR_RootConstrainSelectedInstOperands, |
| 95795 | // GIR_Coverage, 11339, |
| 95796 | GIR_EraseRootFromParent_Done, |
| 95797 | // Label 5167: @299476 |
| 95798 | GIM_Try, /*On fail goto*//*Label 5168*/ GIMT_Encode4(299605), // Rule ID 11340 // |
| 95799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95800 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95801 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95802 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95803 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95804 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95805 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 95806 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95807 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95808 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95809 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95810 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95811 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95812 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95813 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95814 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95815 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95816 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95817 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95818 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95819 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95830 | GIR_RootConstrainSelectedInstOperands, |
| 95831 | // GIR_Coverage, 11340, |
| 95832 | GIR_EraseRootFromParent_Done, |
| 95833 | // Label 5168: @299605 |
| 95834 | GIM_Try, /*On fail goto*//*Label 5169*/ GIMT_Encode4(299734), // Rule ID 11382 // |
| 95835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95839 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95840 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95841 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95842 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95843 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95844 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95845 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95846 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95847 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95848 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95851 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95852 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95853 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95854 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95855 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95866 | GIR_RootConstrainSelectedInstOperands, |
| 95867 | // GIR_Coverage, 11382, |
| 95868 | GIR_EraseRootFromParent_Done, |
| 95869 | // Label 5169: @299734 |
| 95870 | GIM_Try, /*On fail goto*//*Label 5170*/ GIMT_Encode4(299863), // Rule ID 11383 // |
| 95871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95872 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95873 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95874 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95875 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95876 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95877 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95878 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95879 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95880 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95881 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95882 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95883 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95884 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95885 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95886 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95887 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95888 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95889 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95890 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95891 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 95895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 95896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 95897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 95898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95900 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95902 | GIR_RootConstrainSelectedInstOperands, |
| 95903 | // GIR_Coverage, 11383, |
| 95904 | GIR_EraseRootFromParent_Done, |
| 95905 | // Label 5170: @299863 |
| 95906 | GIM_Try, /*On fail goto*//*Label 5171*/ GIMT_Encode4(299992), // Rule ID 11384 // |
| 95907 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95908 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95909 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95910 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95911 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95912 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95913 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95914 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95915 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95916 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95917 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95918 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95919 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95920 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95921 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95922 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95923 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95924 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95925 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95926 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95927 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95929 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95938 | GIR_RootConstrainSelectedInstOperands, |
| 95939 | // GIR_Coverage, 11384, |
| 95940 | GIR_EraseRootFromParent_Done, |
| 95941 | // Label 5171: @299992 |
| 95942 | GIM_Try, /*On fail goto*//*Label 5172*/ GIMT_Encode4(300121), // Rule ID 11385 // |
| 95943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95944 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95945 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95946 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95947 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95948 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95949 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95950 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95951 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95952 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95953 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95954 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95955 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95956 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95957 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95958 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95959 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95960 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95961 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95962 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95963 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 95964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 95965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 95966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 95967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 95968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 95969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 95970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 95971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 95972 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 95974 | GIR_RootConstrainSelectedInstOperands, |
| 95975 | // GIR_Coverage, 11385, |
| 95976 | GIR_EraseRootFromParent_Done, |
| 95977 | // Label 5172: @300121 |
| 95978 | GIM_Try, /*On fail goto*//*Label 5173*/ GIMT_Encode4(300250), // Rule ID 11322 // |
| 95979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 95980 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 95981 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 95982 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 95983 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 95984 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 95985 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 95986 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 95987 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 95988 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 95989 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 95990 | // MIs[3] VOP3Mods:src0:src0_mods |
| 95991 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 95992 | // MIs[3] VOP3Mods:src1:src1_mods |
| 95993 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 95994 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 95995 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 95996 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 95997 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 95998 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 95999 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 96005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 96006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 96007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 96008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96010 | GIR_RootConstrainSelectedInstOperands, |
| 96011 | // GIR_Coverage, 11322, |
| 96012 | GIR_EraseRootFromParent_Done, |
| 96013 | // Label 5173: @300250 |
| 96014 | GIM_Try, /*On fail goto*//*Label 5174*/ GIMT_Encode4(300379), // Rule ID 11323 // |
| 96015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96016 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96017 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96018 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96020 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 96021 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96022 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96023 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96024 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96025 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96026 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96027 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96028 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96029 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96030 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96031 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96032 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96033 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96034 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96035 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 96041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 96042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 96043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 96044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96046 | GIR_RootConstrainSelectedInstOperands, |
| 96047 | // GIR_Coverage, 11323, |
| 96048 | GIR_EraseRootFromParent_Done, |
| 96049 | // Label 5174: @300379 |
| 96050 | GIM_Try, /*On fail goto*//*Label 5175*/ GIMT_Encode4(300508), // Rule ID 11324 // |
| 96051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96052 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96053 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96054 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96055 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96056 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 96057 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96058 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96059 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96060 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96061 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96062 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96063 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96064 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96065 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96066 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96067 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96068 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96069 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96070 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96071 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 96075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 96076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 96079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 96080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96082 | GIR_RootConstrainSelectedInstOperands, |
| 96083 | // GIR_Coverage, 11324, |
| 96084 | GIR_EraseRootFromParent_Done, |
| 96085 | // Label 5175: @300508 |
| 96086 | GIM_Try, /*On fail goto*//*Label 5176*/ GIMT_Encode4(300637), // Rule ID 11325 // |
| 96087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96088 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96089 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96090 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96091 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96092 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 96093 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96094 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96095 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96096 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96097 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96098 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96099 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96100 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96101 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96102 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96103 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96104 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96105 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96106 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96107 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 96111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 96112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 96115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 96116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96118 | GIR_RootConstrainSelectedInstOperands, |
| 96119 | // GIR_Coverage, 11325, |
| 96120 | GIR_EraseRootFromParent_Done, |
| 96121 | // Label 5176: @300637 |
| 96122 | GIM_Try, /*On fail goto*//*Label 5177*/ GIMT_Encode4(300766), // Rule ID 11393 // |
| 96123 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96124 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96125 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96126 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96127 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96128 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96129 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96130 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96131 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96132 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96133 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96134 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96135 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96136 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96137 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96138 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96139 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96140 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96141 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96142 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96143 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96154 | GIR_RootConstrainSelectedInstOperands, |
| 96155 | // GIR_Coverage, 11393, |
| 96156 | GIR_EraseRootFromParent_Done, |
| 96157 | // Label 5177: @300766 |
| 96158 | GIM_Try, /*On fail goto*//*Label 5178*/ GIMT_Encode4(300895), // Rule ID 11394 // |
| 96159 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96160 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96161 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96162 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96163 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96164 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96165 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96166 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96167 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96168 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96169 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96170 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96171 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96172 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96173 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96174 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96175 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96176 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96177 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96178 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96179 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96180 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96181 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96190 | GIR_RootConstrainSelectedInstOperands, |
| 96191 | // GIR_Coverage, 11394, |
| 96192 | GIR_EraseRootFromParent_Done, |
| 96193 | // Label 5178: @300895 |
| 96194 | GIM_Try, /*On fail goto*//*Label 5179*/ GIMT_Encode4(301024), // Rule ID 11395 // |
| 96195 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96196 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96197 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96198 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96199 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96200 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96201 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96202 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96203 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96204 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96205 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96206 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96207 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96208 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96209 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96210 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96211 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96212 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96213 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96214 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96215 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96224 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96226 | GIR_RootConstrainSelectedInstOperands, |
| 96227 | // GIR_Coverage, 11395, |
| 96228 | GIR_EraseRootFromParent_Done, |
| 96229 | // Label 5179: @301024 |
| 96230 | GIM_Try, /*On fail goto*//*Label 5180*/ GIMT_Encode4(301153), // Rule ID 11396 // |
| 96231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96232 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96233 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96234 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96235 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96236 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96237 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96238 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96239 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96240 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96241 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96242 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96243 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96244 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96245 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96246 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96247 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96248 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96249 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96250 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96251 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96262 | GIR_RootConstrainSelectedInstOperands, |
| 96263 | // GIR_Coverage, 11396, |
| 96264 | GIR_EraseRootFromParent_Done, |
| 96265 | // Label 5180: @301153 |
| 96266 | GIM_Try, /*On fail goto*//*Label 5181*/ GIMT_Encode4(301282), // Rule ID 11333 // |
| 96267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96272 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96273 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96274 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96275 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96276 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96277 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96278 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96279 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96280 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96281 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96282 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96283 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96284 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96285 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96286 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96287 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96298 | GIR_RootConstrainSelectedInstOperands, |
| 96299 | // GIR_Coverage, 11333, |
| 96300 | GIR_EraseRootFromParent_Done, |
| 96301 | // Label 5181: @301282 |
| 96302 | GIM_Try, /*On fail goto*//*Label 5182*/ GIMT_Encode4(301411), // Rule ID 11334 // |
| 96303 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96304 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96305 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96306 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96307 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96308 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96309 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96310 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96311 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96312 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96313 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96314 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96315 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96316 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96317 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96318 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96319 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96320 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96321 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96322 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96323 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96334 | GIR_RootConstrainSelectedInstOperands, |
| 96335 | // GIR_Coverage, 11334, |
| 96336 | GIR_EraseRootFromParent_Done, |
| 96337 | // Label 5182: @301411 |
| 96338 | GIM_Try, /*On fail goto*//*Label 5183*/ GIMT_Encode4(301540), // Rule ID 11335 // |
| 96339 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96340 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96341 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96342 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96343 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96344 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96345 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96346 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96347 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96348 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96349 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96350 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96351 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96352 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96353 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96354 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96355 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96356 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96357 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96358 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96359 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96370 | GIR_RootConstrainSelectedInstOperands, |
| 96371 | // GIR_Coverage, 11335, |
| 96372 | GIR_EraseRootFromParent_Done, |
| 96373 | // Label 5183: @301540 |
| 96374 | GIM_Try, /*On fail goto*//*Label 5184*/ GIMT_Encode4(301669), // Rule ID 11336 // |
| 96375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96376 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96377 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96378 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96379 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96380 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96381 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96382 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96383 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96384 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96385 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96386 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96387 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96388 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96389 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96390 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96391 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96392 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96393 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96394 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96395 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96406 | GIR_RootConstrainSelectedInstOperands, |
| 96407 | // GIR_Coverage, 11336, |
| 96408 | GIR_EraseRootFromParent_Done, |
| 96409 | // Label 5184: @301669 |
| 96410 | GIM_Try, /*On fail goto*//*Label 5185*/ GIMT_Encode4(301798), // Rule ID 11378 // |
| 96411 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96412 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96413 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96414 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96415 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96416 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96417 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96418 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96419 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96420 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96421 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96422 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96423 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96424 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96425 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96426 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96427 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96428 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96429 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96430 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96431 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96442 | GIR_RootConstrainSelectedInstOperands, |
| 96443 | // GIR_Coverage, 11378, |
| 96444 | GIR_EraseRootFromParent_Done, |
| 96445 | // Label 5185: @301798 |
| 96446 | GIM_Try, /*On fail goto*//*Label 5186*/ GIMT_Encode4(301927), // Rule ID 11379 // |
| 96447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96448 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96449 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96450 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96451 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96452 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96453 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96454 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96455 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96456 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96457 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96458 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96459 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96460 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96461 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96462 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96463 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96464 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96465 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96466 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96467 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96478 | GIR_RootConstrainSelectedInstOperands, |
| 96479 | // GIR_Coverage, 11379, |
| 96480 | GIR_EraseRootFromParent_Done, |
| 96481 | // Label 5186: @301927 |
| 96482 | GIM_Try, /*On fail goto*//*Label 5187*/ GIMT_Encode4(302056), // Rule ID 11380 // |
| 96483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96484 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96485 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96486 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96487 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96488 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96489 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96490 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96491 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96492 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96493 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96494 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96495 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96496 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96497 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96498 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96499 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96500 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96501 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96502 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96503 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96514 | GIR_RootConstrainSelectedInstOperands, |
| 96515 | // GIR_Coverage, 11380, |
| 96516 | GIR_EraseRootFromParent_Done, |
| 96517 | // Label 5187: @302056 |
| 96518 | GIM_Try, /*On fail goto*//*Label 5188*/ GIMT_Encode4(302185), // Rule ID 11381 // |
| 96519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96520 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96521 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96523 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96524 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96525 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96526 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96527 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96528 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96529 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96530 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96531 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96532 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96534 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96535 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96536 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96537 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96538 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96539 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96550 | GIR_RootConstrainSelectedInstOperands, |
| 96551 | // GIR_Coverage, 11381, |
| 96552 | GIR_EraseRootFromParent_Done, |
| 96553 | // Label 5188: @302185 |
| 96554 | GIM_Try, /*On fail goto*//*Label 5189*/ GIMT_Encode4(302314), // Rule ID 11318 // |
| 96555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96556 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96557 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96558 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96559 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96560 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96561 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96562 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96563 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96564 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96565 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96566 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96567 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96568 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96569 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96570 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96571 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96572 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96573 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96574 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96575 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96586 | GIR_RootConstrainSelectedInstOperands, |
| 96587 | // GIR_Coverage, 11318, |
| 96588 | GIR_EraseRootFromParent_Done, |
| 96589 | // Label 5189: @302314 |
| 96590 | GIM_Try, /*On fail goto*//*Label 5190*/ GIMT_Encode4(302443), // Rule ID 11319 // |
| 96591 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96592 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96593 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96594 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96595 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96596 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96597 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96598 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96599 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96600 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96601 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96602 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96603 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96604 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96605 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96606 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96607 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96608 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96609 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96610 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96611 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96622 | GIR_RootConstrainSelectedInstOperands, |
| 96623 | // GIR_Coverage, 11319, |
| 96624 | GIR_EraseRootFromParent_Done, |
| 96625 | // Label 5190: @302443 |
| 96626 | GIM_Try, /*On fail goto*//*Label 5191*/ GIMT_Encode4(302572), // Rule ID 11320 // |
| 96627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96628 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96629 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96630 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96631 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96632 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96633 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96634 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96635 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96636 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96637 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96638 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96639 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96640 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96641 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96642 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96643 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96644 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96645 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96646 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96647 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96658 | GIR_RootConstrainSelectedInstOperands, |
| 96659 | // GIR_Coverage, 11320, |
| 96660 | GIR_EraseRootFromParent_Done, |
| 96661 | // Label 5191: @302572 |
| 96662 | GIM_Try, /*On fail goto*//*Label 5192*/ GIMT_Encode4(302701), // Rule ID 11321 // |
| 96663 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96664 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96665 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96666 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96667 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96668 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 96669 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96670 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96671 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96672 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 96673 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96674 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96675 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 96676 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96677 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 96678 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96679 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96680 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96681 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96682 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96683 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96692 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96694 | GIR_RootConstrainSelectedInstOperands, |
| 96695 | // GIR_Coverage, 11321, |
| 96696 | GIR_EraseRootFromParent_Done, |
| 96697 | // Label 5192: @302701 |
| 96698 | GIM_Try, /*On fail goto*//*Label 5193*/ GIMT_Encode4(302830), // Rule ID 11327 // |
| 96699 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96700 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96701 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96702 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96703 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96704 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96705 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96706 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96707 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96708 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96709 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96710 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96711 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96712 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96713 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96714 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96715 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96716 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96717 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96718 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96719 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96730 | GIR_RootConstrainSelectedInstOperands, |
| 96731 | // GIR_Coverage, 11327, |
| 96732 | GIR_EraseRootFromParent_Done, |
| 96733 | // Label 5193: @302830 |
| 96734 | GIM_Try, /*On fail goto*//*Label 5194*/ GIMT_Encode4(302959), // Rule ID 11328 // |
| 96735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96736 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96737 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96738 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96739 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96740 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96741 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96742 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96743 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96744 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96745 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96746 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96747 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96748 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96749 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96750 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96751 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96752 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96753 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96754 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96755 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96766 | GIR_RootConstrainSelectedInstOperands, |
| 96767 | // GIR_Coverage, 11328, |
| 96768 | GIR_EraseRootFromParent_Done, |
| 96769 | // Label 5194: @302959 |
| 96770 | GIM_Try, /*On fail goto*//*Label 5195*/ GIMT_Encode4(303088), // Rule ID 11331 // |
| 96771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96772 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96773 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96774 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96775 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96776 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96777 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96778 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96779 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96780 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96781 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96782 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96783 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96784 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96785 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96786 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96787 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96788 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96789 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96790 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96791 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96802 | GIR_RootConstrainSelectedInstOperands, |
| 96803 | // GIR_Coverage, 11331, |
| 96804 | GIR_EraseRootFromParent_Done, |
| 96805 | // Label 5195: @303088 |
| 96806 | GIM_Try, /*On fail goto*//*Label 5196*/ GIMT_Encode4(303217), // Rule ID 11332 // |
| 96807 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96808 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96809 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96810 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96811 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96812 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96813 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96814 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96815 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96816 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96817 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96818 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96819 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96820 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96821 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96822 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96823 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96824 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96825 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96826 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96827 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96838 | GIR_RootConstrainSelectedInstOperands, |
| 96839 | // GIR_Coverage, 11332, |
| 96840 | GIR_EraseRootFromParent_Done, |
| 96841 | // Label 5196: @303217 |
| 96842 | GIM_Try, /*On fail goto*//*Label 5197*/ GIMT_Encode4(303346), // Rule ID 11312 // |
| 96843 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96844 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96845 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96846 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96847 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96848 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96849 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96850 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96851 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96852 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96853 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96854 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96855 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96856 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96857 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96858 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96859 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96860 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96861 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96862 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96863 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96874 | GIR_RootConstrainSelectedInstOperands, |
| 96875 | // GIR_Coverage, 11312, |
| 96876 | GIR_EraseRootFromParent_Done, |
| 96877 | // Label 5197: @303346 |
| 96878 | GIM_Try, /*On fail goto*//*Label 5198*/ GIMT_Encode4(303475), // Rule ID 11313 // |
| 96879 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96880 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96881 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96882 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96883 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96884 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96885 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96886 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96887 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96888 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96889 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96890 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96891 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96892 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96893 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96894 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96895 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96896 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96897 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96898 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96899 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 96903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 96904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 96905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 96906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96908 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96910 | GIR_RootConstrainSelectedInstOperands, |
| 96911 | // GIR_Coverage, 11313, |
| 96912 | GIR_EraseRootFromParent_Done, |
| 96913 | // Label 5198: @303475 |
| 96914 | GIM_Try, /*On fail goto*//*Label 5199*/ GIMT_Encode4(303604), // Rule ID 11316 // |
| 96915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96916 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96917 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96918 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96919 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96920 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96921 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96922 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96923 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96924 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96925 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96926 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96927 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96928 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96929 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96930 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96931 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96932 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96933 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96934 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96935 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96946 | GIR_RootConstrainSelectedInstOperands, |
| 96947 | // GIR_Coverage, 11316, |
| 96948 | GIR_EraseRootFromParent_Done, |
| 96949 | // Label 5199: @303604 |
| 96950 | GIM_Try, /*On fail goto*//*Label 5200*/ GIMT_Encode4(303733), // Rule ID 11317 // |
| 96951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96953 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96954 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96955 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96956 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96957 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96958 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96959 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96960 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 96961 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 96962 | // MIs[3] VOP3Mods:src1:src1_mods |
| 96963 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 96964 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96965 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 96966 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 96967 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 96968 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 96969 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 96970 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 96971 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 96972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 96973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 96974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 96975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 96976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 96977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 96978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 96979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 96980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 96982 | GIR_RootConstrainSelectedInstOperands, |
| 96983 | // GIR_Coverage, 11317, |
| 96984 | GIR_EraseRootFromParent_Done, |
| 96985 | // Label 5200: @303733 |
| 96986 | GIM_Try, /*On fail goto*//*Label 5201*/ GIMT_Encode4(303862), // Rule ID 7341 // |
| 96987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 96988 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 96989 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 96990 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 96991 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 96992 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 96993 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 96994 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 96995 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 96996 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 96997 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 96998 | // MIs[3] VOP3Mods:src0:src0_mods |
| 96999 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97000 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97002 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97003 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97004 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97005 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97006 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97007 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97018 | GIR_RootConstrainSelectedInstOperands, |
| 97019 | // GIR_Coverage, 7341, |
| 97020 | GIR_EraseRootFromParent_Done, |
| 97021 | // Label 5201: @303862 |
| 97022 | GIM_Try, /*On fail goto*//*Label 5202*/ GIMT_Encode4(303991), // Rule ID 11326 // |
| 97023 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97024 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97025 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97026 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97027 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97028 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97029 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97030 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97031 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97032 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97033 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97034 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97035 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97036 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97037 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97038 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97039 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97040 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97041 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97042 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97043 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97054 | GIR_RootConstrainSelectedInstOperands, |
| 97055 | // GIR_Coverage, 11326, |
| 97056 | GIR_EraseRootFromParent_Done, |
| 97057 | // Label 5202: @303991 |
| 97058 | GIM_Try, /*On fail goto*//*Label 5203*/ GIMT_Encode4(304120), // Rule ID 11329 // |
| 97059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97060 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97061 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97062 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97063 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97064 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97065 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97066 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97067 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97068 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97069 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97070 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97071 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97072 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97073 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97074 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97075 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97076 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97077 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97078 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97079 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97090 | GIR_RootConstrainSelectedInstOperands, |
| 97091 | // GIR_Coverage, 11329, |
| 97092 | GIR_EraseRootFromParent_Done, |
| 97093 | // Label 5203: @304120 |
| 97094 | GIM_Try, /*On fail goto*//*Label 5204*/ GIMT_Encode4(304249), // Rule ID 11330 // |
| 97095 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97096 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97097 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97098 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97099 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97100 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97101 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97102 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97103 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97104 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97105 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97106 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97107 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97108 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97109 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97110 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97111 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97112 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97113 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97114 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97115 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97126 | GIR_RootConstrainSelectedInstOperands, |
| 97127 | // GIR_Coverage, 11330, |
| 97128 | GIR_EraseRootFromParent_Done, |
| 97129 | // Label 5204: @304249 |
| 97130 | GIM_Try, /*On fail goto*//*Label 5205*/ GIMT_Encode4(304378), // Rule ID 7340 // |
| 97131 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97132 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97133 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97134 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97135 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97136 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97137 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97138 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97139 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97140 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97141 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97142 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97143 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97144 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97145 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97146 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97147 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97148 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97149 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97150 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97151 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97162 | GIR_RootConstrainSelectedInstOperands, |
| 97163 | // GIR_Coverage, 7340, |
| 97164 | GIR_EraseRootFromParent_Done, |
| 97165 | // Label 5205: @304378 |
| 97166 | GIM_Try, /*On fail goto*//*Label 5206*/ GIMT_Encode4(304507), // Rule ID 11311 // |
| 97167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97170 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97171 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97172 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97173 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97174 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97175 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97176 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97177 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97178 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97179 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97180 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97181 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97182 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97183 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97184 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97185 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97186 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97187 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97198 | GIR_RootConstrainSelectedInstOperands, |
| 97199 | // GIR_Coverage, 11311, |
| 97200 | GIR_EraseRootFromParent_Done, |
| 97201 | // Label 5206: @304507 |
| 97202 | GIM_Try, /*On fail goto*//*Label 5207*/ GIMT_Encode4(304636), // Rule ID 11314 // |
| 97203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97204 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97205 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97206 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97207 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97208 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97209 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97210 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97211 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97212 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97213 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97214 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97215 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97216 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97217 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97218 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97219 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97220 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97221 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97222 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97223 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97234 | GIR_RootConstrainSelectedInstOperands, |
| 97235 | // GIR_Coverage, 11314, |
| 97236 | GIR_EraseRootFromParent_Done, |
| 97237 | // Label 5207: @304636 |
| 97238 | GIM_Try, /*On fail goto*//*Label 5208*/ GIMT_Encode4(304765), // Rule ID 11315 // |
| 97239 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97240 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97241 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97242 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97243 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97244 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97245 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97246 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97247 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97248 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97249 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97250 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97251 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97252 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97253 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97254 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97255 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97256 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97257 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97258 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97259 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97270 | GIR_RootConstrainSelectedInstOperands, |
| 97271 | // GIR_Coverage, 11315, |
| 97272 | GIR_EraseRootFromParent_Done, |
| 97273 | // Label 5208: @304765 |
| 97274 | GIM_Try, /*On fail goto*//*Label 5209*/ GIMT_Encode4(304894), // Rule ID 11297 // |
| 97275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97276 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97277 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97278 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97279 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97280 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97281 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97282 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97283 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97284 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97285 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97286 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97287 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97288 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97289 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97290 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97291 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97292 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97293 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97294 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97295 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97296 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97297 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97306 | GIR_RootConstrainSelectedInstOperands, |
| 97307 | // GIR_Coverage, 11297, |
| 97308 | GIR_EraseRootFromParent_Done, |
| 97309 | // Label 5209: @304894 |
| 97310 | GIM_Try, /*On fail goto*//*Label 5210*/ GIMT_Encode4(305023), // Rule ID 11298 // |
| 97311 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97312 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97313 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97314 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97315 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97316 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97317 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97318 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97319 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97320 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97321 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97322 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97323 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97324 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97325 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97326 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97327 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97328 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97329 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97330 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97331 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97342 | GIR_RootConstrainSelectedInstOperands, |
| 97343 | // GIR_Coverage, 11298, |
| 97344 | GIR_EraseRootFromParent_Done, |
| 97345 | // Label 5210: @305023 |
| 97346 | GIM_Try, /*On fail goto*//*Label 5211*/ GIMT_Encode4(305152), // Rule ID 11301 // |
| 97347 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97348 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97349 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97350 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97351 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97352 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97353 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97354 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97355 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97356 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97357 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97358 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97359 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97360 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97361 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97362 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97363 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97364 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97365 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97366 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97367 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97378 | GIR_RootConstrainSelectedInstOperands, |
| 97379 | // GIR_Coverage, 11301, |
| 97380 | GIR_EraseRootFromParent_Done, |
| 97381 | // Label 5211: @305152 |
| 97382 | GIM_Try, /*On fail goto*//*Label 5212*/ GIMT_Encode4(305281), // Rule ID 11302 // |
| 97383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97384 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97385 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97386 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97387 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97388 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97389 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97390 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97391 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97392 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97393 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97394 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97395 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97396 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97397 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97398 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97399 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97400 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97401 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97402 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97403 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97414 | GIR_RootConstrainSelectedInstOperands, |
| 97415 | // GIR_Coverage, 11302, |
| 97416 | GIR_EraseRootFromParent_Done, |
| 97417 | // Label 5212: @305281 |
| 97418 | GIM_Try, /*On fail goto*//*Label 5213*/ GIMT_Encode4(305410), // Rule ID 11282 // |
| 97419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97420 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97421 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97422 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97423 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97424 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97425 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97426 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97427 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97428 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97429 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97430 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97431 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97432 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97433 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97434 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97435 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97436 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97437 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97438 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97439 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97450 | GIR_RootConstrainSelectedInstOperands, |
| 97451 | // GIR_Coverage, 11282, |
| 97452 | GIR_EraseRootFromParent_Done, |
| 97453 | // Label 5213: @305410 |
| 97454 | GIM_Try, /*On fail goto*//*Label 5214*/ GIMT_Encode4(305539), // Rule ID 11283 // |
| 97455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97456 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97457 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97458 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97459 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97460 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97461 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97462 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97463 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97464 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97465 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97466 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97467 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97468 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97469 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97470 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97471 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97472 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97473 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97474 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97475 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97486 | GIR_RootConstrainSelectedInstOperands, |
| 97487 | // GIR_Coverage, 11283, |
| 97488 | GIR_EraseRootFromParent_Done, |
| 97489 | // Label 5214: @305539 |
| 97490 | GIM_Try, /*On fail goto*//*Label 5215*/ GIMT_Encode4(305668), // Rule ID 11286 // |
| 97491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97492 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97493 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97494 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97495 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97496 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97497 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97498 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97499 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97500 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97501 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97502 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97503 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97504 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97505 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97506 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97507 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97508 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97509 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97510 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97511 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97522 | GIR_RootConstrainSelectedInstOperands, |
| 97523 | // GIR_Coverage, 11286, |
| 97524 | GIR_EraseRootFromParent_Done, |
| 97525 | // Label 5215: @305668 |
| 97526 | GIM_Try, /*On fail goto*//*Label 5216*/ GIMT_Encode4(305797), // Rule ID 11287 // |
| 97527 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97528 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97529 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97530 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97531 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97532 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97533 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97534 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97535 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97536 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 97537 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97538 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97539 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97540 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97541 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97542 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97543 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97544 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97545 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97546 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97547 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97558 | GIR_RootConstrainSelectedInstOperands, |
| 97559 | // GIR_Coverage, 11287, |
| 97560 | GIR_EraseRootFromParent_Done, |
| 97561 | // Label 5216: @305797 |
| 97562 | GIM_Try, /*On fail goto*//*Label 5217*/ GIMT_Encode4(305926), // Rule ID 7339 // |
| 97563 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97564 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97565 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97566 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97567 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97568 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97569 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97570 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97571 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97572 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97573 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97574 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97575 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97576 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97577 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97578 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97579 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97580 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97581 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97582 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97583 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97594 | GIR_RootConstrainSelectedInstOperands, |
| 97595 | // GIR_Coverage, 7339, |
| 97596 | GIR_EraseRootFromParent_Done, |
| 97597 | // Label 5217: @305926 |
| 97598 | GIM_Try, /*On fail goto*//*Label 5218*/ GIMT_Encode4(306055), // Rule ID 11296 // |
| 97599 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97600 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97601 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97602 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97603 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97604 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97605 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97606 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97607 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97608 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97609 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97610 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97611 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97612 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97613 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97614 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97615 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97616 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97617 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97618 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97619 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97630 | GIR_RootConstrainSelectedInstOperands, |
| 97631 | // GIR_Coverage, 11296, |
| 97632 | GIR_EraseRootFromParent_Done, |
| 97633 | // Label 5218: @306055 |
| 97634 | GIM_Try, /*On fail goto*//*Label 5219*/ GIMT_Encode4(306184), // Rule ID 11299 // |
| 97635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97639 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97641 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97644 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97645 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97646 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97648 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97649 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97650 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97651 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97652 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97653 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97654 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97655 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97666 | GIR_RootConstrainSelectedInstOperands, |
| 97667 | // GIR_Coverage, 11299, |
| 97668 | GIR_EraseRootFromParent_Done, |
| 97669 | // Label 5219: @306184 |
| 97670 | GIM_Try, /*On fail goto*//*Label 5220*/ GIMT_Encode4(306313), // Rule ID 11300 // |
| 97671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97676 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97677 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97678 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97679 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97680 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97681 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97682 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97683 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97684 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97685 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97686 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97687 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97688 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97689 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97690 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97691 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97702 | GIR_RootConstrainSelectedInstOperands, |
| 97703 | // GIR_Coverage, 11300, |
| 97704 | GIR_EraseRootFromParent_Done, |
| 97705 | // Label 5220: @306313 |
| 97706 | GIM_Try, /*On fail goto*//*Label 5221*/ GIMT_Encode4(306442), // Rule ID 7338 // |
| 97707 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97708 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97709 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97710 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97711 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97712 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97713 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97714 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97715 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97716 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97717 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97718 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97719 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97720 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97721 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97722 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97723 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97724 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97725 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97726 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97727 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97738 | GIR_RootConstrainSelectedInstOperands, |
| 97739 | // GIR_Coverage, 7338, |
| 97740 | GIR_EraseRootFromParent_Done, |
| 97741 | // Label 5221: @306442 |
| 97742 | GIM_Try, /*On fail goto*//*Label 5222*/ GIMT_Encode4(306571), // Rule ID 11281 // |
| 97743 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97744 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97745 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97746 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97747 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97748 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97749 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97750 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97751 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97752 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97753 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97754 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97755 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97756 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97757 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97758 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97759 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97760 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97761 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97762 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97763 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 97767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 97768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97774 | GIR_RootConstrainSelectedInstOperands, |
| 97775 | // GIR_Coverage, 11281, |
| 97776 | GIR_EraseRootFromParent_Done, |
| 97777 | // Label 5222: @306571 |
| 97778 | GIM_Try, /*On fail goto*//*Label 5223*/ GIMT_Encode4(306700), // Rule ID 11284 // |
| 97779 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97780 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97781 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97782 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97783 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97784 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97785 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97786 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97787 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97788 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97789 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97790 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97791 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97792 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97793 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97794 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97795 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97796 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97797 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97798 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97799 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97810 | GIR_RootConstrainSelectedInstOperands, |
| 97811 | // GIR_Coverage, 11284, |
| 97812 | GIR_EraseRootFromParent_Done, |
| 97813 | // Label 5223: @306700 |
| 97814 | GIM_Try, /*On fail goto*//*Label 5224*/ GIMT_Encode4(306829), // Rule ID 11285 // |
| 97815 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97816 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97817 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97818 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97819 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97820 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 97821 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97822 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97823 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97824 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 97825 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 97826 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97827 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 97828 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97829 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 97830 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97831 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97832 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97833 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97834 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97835 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97837 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 97841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 97842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 97843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 97844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97846 | GIR_RootConstrainSelectedInstOperands, |
| 97847 | // GIR_Coverage, 11285, |
| 97848 | GIR_EraseRootFromParent_Done, |
| 97849 | // Label 5224: @306829 |
| 97850 | GIM_Try, /*On fail goto*//*Label 5225*/ GIMT_Encode4(306958), // Rule ID 11367 // |
| 97851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97852 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97853 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97854 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97855 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97856 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 97857 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97858 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97859 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97860 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 97861 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97862 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97863 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 97864 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97865 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 97866 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97867 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97868 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97869 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97870 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97871 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 97877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 97878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 97879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 97880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97882 | GIR_RootConstrainSelectedInstOperands, |
| 97883 | // GIR_Coverage, 11367, |
| 97884 | GIR_EraseRootFromParent_Done, |
| 97885 | // Label 5225: @306958 |
| 97886 | GIM_Try, /*On fail goto*//*Label 5226*/ GIMT_Encode4(307087), // Rule ID 11368 // |
| 97887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97889 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97892 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 97893 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97894 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97895 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97896 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 97897 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97898 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97899 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 97900 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97901 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 97902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97903 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97904 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97905 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97906 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97907 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 97911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 97912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 97913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 97914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 97915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 97916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97918 | GIR_RootConstrainSelectedInstOperands, |
| 97919 | // GIR_Coverage, 11368, |
| 97920 | GIR_EraseRootFromParent_Done, |
| 97921 | // Label 5226: @307087 |
| 97922 | GIM_Try, /*On fail goto*//*Label 5227*/ GIMT_Encode4(307216), // Rule ID 11369 // |
| 97923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97924 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97925 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97926 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97927 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97928 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 97929 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97930 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97931 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97932 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 97933 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97934 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97935 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 97936 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97937 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 97938 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97939 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97940 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97941 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97942 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97943 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 97947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 97948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 97951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 97952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97954 | GIR_RootConstrainSelectedInstOperands, |
| 97955 | // GIR_Coverage, 11369, |
| 97956 | GIR_EraseRootFromParent_Done, |
| 97957 | // Label 5227: @307216 |
| 97958 | GIM_Try, /*On fail goto*//*Label 5228*/ GIMT_Encode4(307345), // Rule ID 11370 // |
| 97959 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97960 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97961 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97962 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97963 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 97964 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 97965 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 97966 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 97967 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 97968 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 97969 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 97970 | // MIs[3] VOP3Mods:src1:src1_mods |
| 97971 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 97972 | // MIs[3] VOP3Mods:src0:src0_mods |
| 97973 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 97974 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 97975 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 97976 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 97977 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 97978 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 97979 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 97980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 97981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 97982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 97983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 97984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 97985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 97986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 97987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 97988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 97990 | GIR_RootConstrainSelectedInstOperands, |
| 97991 | // GIR_Coverage, 11370, |
| 97992 | GIR_EraseRootFromParent_Done, |
| 97993 | // Label 5228: @307345 |
| 97994 | GIM_Try, /*On fail goto*//*Label 5229*/ GIMT_Encode4(307474), // Rule ID 11307 // |
| 97995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 97996 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 97997 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 97998 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 97999 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98000 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98001 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98002 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98003 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98004 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98005 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98006 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98007 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98008 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98009 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98010 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98011 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98012 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98013 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98014 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98015 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98016 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98017 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98026 | GIR_RootConstrainSelectedInstOperands, |
| 98027 | // GIR_Coverage, 11307, |
| 98028 | GIR_EraseRootFromParent_Done, |
| 98029 | // Label 5229: @307474 |
| 98030 | GIM_Try, /*On fail goto*//*Label 5230*/ GIMT_Encode4(307603), // Rule ID 11308 // |
| 98031 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98032 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98033 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98034 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98035 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98036 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98037 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98038 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98039 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98040 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98041 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98042 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98043 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98044 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98045 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98046 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98047 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98048 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98049 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98050 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98051 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98052 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98053 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98062 | GIR_RootConstrainSelectedInstOperands, |
| 98063 | // GIR_Coverage, 11308, |
| 98064 | GIR_EraseRootFromParent_Done, |
| 98065 | // Label 5230: @307603 |
| 98066 | GIM_Try, /*On fail goto*//*Label 5231*/ GIMT_Encode4(307732), // Rule ID 11309 // |
| 98067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98068 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98069 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98070 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98071 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98072 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98073 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98074 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98075 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98076 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98077 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98078 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98079 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98080 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98081 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98082 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98083 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98084 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98085 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98086 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98087 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98098 | GIR_RootConstrainSelectedInstOperands, |
| 98099 | // GIR_Coverage, 11309, |
| 98100 | GIR_EraseRootFromParent_Done, |
| 98101 | // Label 5231: @307732 |
| 98102 | GIM_Try, /*On fail goto*//*Label 5232*/ GIMT_Encode4(307861), // Rule ID 11310 // |
| 98103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98104 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98105 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98106 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98107 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98108 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98109 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98110 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98111 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98112 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98113 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98114 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98116 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98117 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98118 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98119 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98120 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98121 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98122 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98123 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98134 | GIR_RootConstrainSelectedInstOperands, |
| 98135 | // GIR_Coverage, 11310, |
| 98136 | GIR_EraseRootFromParent_Done, |
| 98137 | // Label 5232: @307861 |
| 98138 | GIM_Try, /*On fail goto*//*Label 5233*/ GIMT_Encode4(307990), // Rule ID 11352 // |
| 98139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98143 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98145 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98146 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98147 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98148 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98149 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98150 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98151 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98152 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98153 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98154 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98155 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98156 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98157 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98158 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98159 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98170 | GIR_RootConstrainSelectedInstOperands, |
| 98171 | // GIR_Coverage, 11352, |
| 98172 | GIR_EraseRootFromParent_Done, |
| 98173 | // Label 5233: @307990 |
| 98174 | GIM_Try, /*On fail goto*//*Label 5234*/ GIMT_Encode4(308119), // Rule ID 11353 // |
| 98175 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98176 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98177 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98178 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98179 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98180 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98181 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98182 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98183 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98184 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98185 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98186 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98187 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98188 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98189 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98190 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98191 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98192 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98193 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98194 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98195 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98206 | GIR_RootConstrainSelectedInstOperands, |
| 98207 | // GIR_Coverage, 11353, |
| 98208 | GIR_EraseRootFromParent_Done, |
| 98209 | // Label 5234: @308119 |
| 98210 | GIM_Try, /*On fail goto*//*Label 5235*/ GIMT_Encode4(308248), // Rule ID 11354 // |
| 98211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98212 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98213 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98214 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98215 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98216 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98217 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98218 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98219 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98220 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98221 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98222 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98223 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98224 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98225 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98226 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98227 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98228 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98229 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98230 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98231 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98233 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98242 | GIR_RootConstrainSelectedInstOperands, |
| 98243 | // GIR_Coverage, 11354, |
| 98244 | GIR_EraseRootFromParent_Done, |
| 98245 | // Label 5235: @308248 |
| 98246 | GIM_Try, /*On fail goto*//*Label 5236*/ GIMT_Encode4(308377), // Rule ID 11355 // |
| 98247 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98248 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98249 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98250 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98251 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98252 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98253 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98254 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98255 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98256 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98257 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98258 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98259 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98260 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98261 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98262 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98263 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98264 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98265 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98266 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98267 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98278 | GIR_RootConstrainSelectedInstOperands, |
| 98279 | // GIR_Coverage, 11355, |
| 98280 | GIR_EraseRootFromParent_Done, |
| 98281 | // Label 5236: @308377 |
| 98282 | GIM_Try, /*On fail goto*//*Label 5237*/ GIMT_Encode4(308506), // Rule ID 11292 // |
| 98283 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98287 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98288 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98289 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98290 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98291 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98292 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98293 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98294 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98295 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98296 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98297 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98298 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98299 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98300 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98301 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98302 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98303 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98313 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98314 | GIR_RootConstrainSelectedInstOperands, |
| 98315 | // GIR_Coverage, 11292, |
| 98316 | GIR_EraseRootFromParent_Done, |
| 98317 | // Label 5237: @308506 |
| 98318 | GIM_Try, /*On fail goto*//*Label 5238*/ GIMT_Encode4(308635), // Rule ID 11293 // |
| 98319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98320 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98321 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98322 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98323 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98325 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98326 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98327 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98328 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98329 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98330 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98332 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98333 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98335 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98336 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98337 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98338 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98339 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 98345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 98346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98350 | GIR_RootConstrainSelectedInstOperands, |
| 98351 | // GIR_Coverage, 11293, |
| 98352 | GIR_EraseRootFromParent_Done, |
| 98353 | // Label 5238: @308635 |
| 98354 | GIM_Try, /*On fail goto*//*Label 5239*/ GIMT_Encode4(308764), // Rule ID 11294 // |
| 98355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98360 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98361 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98362 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98363 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98364 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98365 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98366 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98367 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98368 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98369 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98370 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98371 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98372 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98373 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98374 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98375 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98386 | GIR_RootConstrainSelectedInstOperands, |
| 98387 | // GIR_Coverage, 11294, |
| 98388 | GIR_EraseRootFromParent_Done, |
| 98389 | // Label 5239: @308764 |
| 98390 | GIM_Try, /*On fail goto*//*Label 5240*/ GIMT_Encode4(308893), // Rule ID 11295 // |
| 98391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98392 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98393 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98394 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98395 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98396 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 98397 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98398 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98399 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98400 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98401 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98402 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98403 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98404 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98405 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98406 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98407 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98408 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98409 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98410 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98411 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 98415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 98416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 98419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 98420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98421 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98422 | GIR_RootConstrainSelectedInstOperands, |
| 98423 | // GIR_Coverage, 11295, |
| 98424 | GIR_EraseRootFromParent_Done, |
| 98425 | // Label 5240: @308893 |
| 98426 | GIM_Try, /*On fail goto*//*Label 5241*/ GIMT_Encode4(309022), // Rule ID 11363 // |
| 98427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98428 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98429 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98430 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98431 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98432 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98433 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98434 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98435 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98436 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98437 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98438 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98439 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98440 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98441 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98442 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98443 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98444 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98445 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98446 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98447 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98458 | GIR_RootConstrainSelectedInstOperands, |
| 98459 | // GIR_Coverage, 11363, |
| 98460 | GIR_EraseRootFromParent_Done, |
| 98461 | // Label 5241: @309022 |
| 98462 | GIM_Try, /*On fail goto*//*Label 5242*/ GIMT_Encode4(309151), // Rule ID 11364 // |
| 98463 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98464 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98465 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98466 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98467 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98468 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98469 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98470 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98471 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98472 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98473 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98474 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98475 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98476 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98477 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98478 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98479 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98480 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98481 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98482 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98483 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98494 | GIR_RootConstrainSelectedInstOperands, |
| 98495 | // GIR_Coverage, 11364, |
| 98496 | GIR_EraseRootFromParent_Done, |
| 98497 | // Label 5242: @309151 |
| 98498 | GIM_Try, /*On fail goto*//*Label 5243*/ GIMT_Encode4(309280), // Rule ID 11365 // |
| 98499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98500 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98501 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98502 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98503 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98504 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98505 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98506 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98507 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98508 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98509 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98510 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98511 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98512 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98513 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98514 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98515 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98516 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98517 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98518 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98519 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98530 | GIR_RootConstrainSelectedInstOperands, |
| 98531 | // GIR_Coverage, 11365, |
| 98532 | GIR_EraseRootFromParent_Done, |
| 98533 | // Label 5243: @309280 |
| 98534 | GIM_Try, /*On fail goto*//*Label 5244*/ GIMT_Encode4(309409), // Rule ID 11366 // |
| 98535 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98536 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98537 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98538 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98539 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98540 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98541 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98542 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98543 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98544 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98545 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98546 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98547 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98548 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98549 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98550 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98551 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98552 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98553 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98554 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98555 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98566 | GIR_RootConstrainSelectedInstOperands, |
| 98567 | // GIR_Coverage, 11366, |
| 98568 | GIR_EraseRootFromParent_Done, |
| 98569 | // Label 5244: @309409 |
| 98570 | GIM_Try, /*On fail goto*//*Label 5245*/ GIMT_Encode4(309538), // Rule ID 11303 // |
| 98571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98572 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98573 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98574 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98575 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98576 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98577 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98578 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98579 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98580 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98581 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98582 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98584 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98585 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98586 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98587 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98588 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98589 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98590 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98591 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98602 | GIR_RootConstrainSelectedInstOperands, |
| 98603 | // GIR_Coverage, 11303, |
| 98604 | GIR_EraseRootFromParent_Done, |
| 98605 | // Label 5245: @309538 |
| 98606 | GIM_Try, /*On fail goto*//*Label 5246*/ GIMT_Encode4(309667), // Rule ID 11304 // |
| 98607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98609 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98612 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98613 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98614 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98615 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98616 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98617 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98618 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98619 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98620 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98622 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98623 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98624 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98625 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98626 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98627 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98638 | GIR_RootConstrainSelectedInstOperands, |
| 98639 | // GIR_Coverage, 11304, |
| 98640 | GIR_EraseRootFromParent_Done, |
| 98641 | // Label 5246: @309667 |
| 98642 | GIM_Try, /*On fail goto*//*Label 5247*/ GIMT_Encode4(309796), // Rule ID 11305 // |
| 98643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98644 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98645 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98646 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98647 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98648 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98649 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98650 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98651 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98652 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98653 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98654 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98655 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98656 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98657 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98658 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98659 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98660 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98661 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98662 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98663 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98664 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98665 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98674 | GIR_RootConstrainSelectedInstOperands, |
| 98675 | // GIR_Coverage, 11305, |
| 98676 | GIR_EraseRootFromParent_Done, |
| 98677 | // Label 5247: @309796 |
| 98678 | GIM_Try, /*On fail goto*//*Label 5248*/ GIMT_Encode4(309925), // Rule ID 11306 // |
| 98679 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98680 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98681 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98682 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98683 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98684 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98685 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 98686 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98687 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98688 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98689 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98690 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98691 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98692 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98693 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98694 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98695 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98696 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98697 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98698 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98699 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98701 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98710 | GIR_RootConstrainSelectedInstOperands, |
| 98711 | // GIR_Coverage, 11306, |
| 98712 | GIR_EraseRootFromParent_Done, |
| 98713 | // Label 5248: @309925 |
| 98714 | GIM_Try, /*On fail goto*//*Label 5249*/ GIMT_Encode4(310054), // Rule ID 11348 // |
| 98715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98720 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98721 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98722 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98723 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98724 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98725 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98726 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98727 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98728 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98729 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98730 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98731 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98732 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98733 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98734 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98735 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98746 | GIR_RootConstrainSelectedInstOperands, |
| 98747 | // GIR_Coverage, 11348, |
| 98748 | GIR_EraseRootFromParent_Done, |
| 98749 | // Label 5249: @310054 |
| 98750 | GIM_Try, /*On fail goto*//*Label 5250*/ GIMT_Encode4(310183), // Rule ID 11349 // |
| 98751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98752 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98753 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98754 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98755 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98756 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98757 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98758 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98759 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98760 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98761 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98762 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98763 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98764 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98765 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98766 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98767 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98768 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98769 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98770 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98771 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98772 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98773 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98782 | GIR_RootConstrainSelectedInstOperands, |
| 98783 | // GIR_Coverage, 11349, |
| 98784 | GIR_EraseRootFromParent_Done, |
| 98785 | // Label 5250: @310183 |
| 98786 | GIM_Try, /*On fail goto*//*Label 5251*/ GIMT_Encode4(310312), // Rule ID 11350 // |
| 98787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98789 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98791 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98792 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98793 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98794 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98795 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98796 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98797 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98798 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98800 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98801 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98802 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98803 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98804 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98805 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98806 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98807 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98818 | GIR_RootConstrainSelectedInstOperands, |
| 98819 | // GIR_Coverage, 11350, |
| 98820 | GIR_EraseRootFromParent_Done, |
| 98821 | // Label 5251: @310312 |
| 98822 | GIM_Try, /*On fail goto*//*Label 5252*/ GIMT_Encode4(310441), // Rule ID 11351 // |
| 98823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98827 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98828 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98829 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98830 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98831 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98832 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98833 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 98834 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98835 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98836 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98839 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98840 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98841 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98842 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98843 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98854 | GIR_RootConstrainSelectedInstOperands, |
| 98855 | // GIR_Coverage, 11351, |
| 98856 | GIR_EraseRootFromParent_Done, |
| 98857 | // Label 5252: @310441 |
| 98858 | GIM_Try, /*On fail goto*//*Label 5253*/ GIMT_Encode4(310570), // Rule ID 11288 // |
| 98859 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98860 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98861 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98862 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98863 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98864 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98865 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98866 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98867 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98868 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98869 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98870 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98871 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98872 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98873 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98874 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98875 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98876 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98877 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98878 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98879 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98889 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98890 | GIR_RootConstrainSelectedInstOperands, |
| 98891 | // GIR_Coverage, 11288, |
| 98892 | GIR_EraseRootFromParent_Done, |
| 98893 | // Label 5253: @310570 |
| 98894 | GIM_Try, /*On fail goto*//*Label 5254*/ GIMT_Encode4(310699), // Rule ID 11289 // |
| 98895 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98896 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98897 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98898 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98899 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98900 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98901 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98902 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98903 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98904 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98905 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98906 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98907 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98908 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98909 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98910 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98911 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98912 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98913 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98914 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98915 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 98919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 98920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 98921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 98922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98926 | GIR_RootConstrainSelectedInstOperands, |
| 98927 | // GIR_Coverage, 11289, |
| 98928 | GIR_EraseRootFromParent_Done, |
| 98929 | // Label 5254: @310699 |
| 98930 | GIM_Try, /*On fail goto*//*Label 5255*/ GIMT_Encode4(310828), // Rule ID 11290 // |
| 98931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98932 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98933 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98934 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98935 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98936 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98937 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98938 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98939 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98940 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98941 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98942 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98943 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98944 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98945 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98946 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98947 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98948 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98949 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98950 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98951 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98962 | GIR_RootConstrainSelectedInstOperands, |
| 98963 | // GIR_Coverage, 11290, |
| 98964 | GIR_EraseRootFromParent_Done, |
| 98965 | // Label 5255: @310828 |
| 98966 | GIM_Try, /*On fail goto*//*Label 5256*/ GIMT_Encode4(310957), // Rule ID 11291 // |
| 98967 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 98968 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 98969 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98970 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 98971 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 98972 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 98973 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 98974 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 98975 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 98976 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 98977 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 98978 | // MIs[3] VOP3Mods:src1:src1_mods |
| 98979 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 98980 | // MIs[3] VOP3Mods:src0:src0_mods |
| 98981 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 98982 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 98983 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 98984 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 98985 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 98986 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 98987 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 98988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 98989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 98990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 98991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 98992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 98993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 98994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 98995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 98996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 98998 | GIR_RootConstrainSelectedInstOperands, |
| 98999 | // GIR_Coverage, 11291, |
| 99000 | GIR_EraseRootFromParent_Done, |
| 99001 | // Label 5256: @310957 |
| 99002 | GIM_Try, /*On fail goto*//*Label 5257*/ GIMT_Encode4(311069), // Rule ID 11938 // |
| 99003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99004 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99005 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99006 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 99007 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99008 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 99009 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99010 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 99011 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 99012 | GIM_CheckHasOneUse, /*MI*/2, |
| 99013 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 99014 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 99015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99016 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99017 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99018 | // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 99024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 99025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 99026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 99027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99028 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99029 | GIR_RootConstrainSelectedInstOperands, |
| 99030 | // GIR_Coverage, 11938, |
| 99031 | GIR_EraseRootFromParent_Done, |
| 99032 | // Label 5257: @311069 |
| 99033 | GIM_Try, /*On fail goto*//*Label 5258*/ GIMT_Encode4(311181), // Rule ID 11937 // |
| 99034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99035 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99036 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99037 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 99038 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99039 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 99040 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99041 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 99042 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 99043 | GIM_CheckHasOneUse, /*MI*/2, |
| 99044 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 99045 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 99046 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99047 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99048 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99049 | // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 99055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 99056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 99057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 99058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99060 | GIR_RootConstrainSelectedInstOperands, |
| 99061 | // GIR_Coverage, 11937, |
| 99062 | GIR_EraseRootFromParent_Done, |
| 99063 | // Label 5258: @311181 |
| 99064 | GIM_Try, /*On fail goto*//*Label 5259*/ GIMT_Encode4(311293), // Rule ID 7407 // |
| 99065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99068 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 99069 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99070 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 99071 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99072 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 99073 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 99074 | GIM_CheckHasOneUse, /*MI*/2, |
| 99075 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 99076 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 99077 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99078 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99079 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99080 | // (fminnum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99091 | GIR_RootConstrainSelectedInstOperands, |
| 99092 | // GIR_Coverage, 7407, |
| 99093 | GIR_EraseRootFromParent_Done, |
| 99094 | // Label 5259: @311293 |
| 99095 | GIM_Try, /*On fail goto*//*Label 5260*/ GIMT_Encode4(311405), // Rule ID 7406 // |
| 99096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99098 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99099 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 99100 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99101 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 99102 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99103 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 99104 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 99105 | GIM_CheckHasOneUse, /*MI*/2, |
| 99106 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 99107 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 99108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99109 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99110 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99111 | // (fminnum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99122 | GIR_RootConstrainSelectedInstOperands, |
| 99123 | // GIR_Coverage, 7406, |
| 99124 | GIR_EraseRootFromParent_Done, |
| 99125 | // Label 5260: @311405 |
| 99126 | GIM_Try, /*On fail goto*//*Label 5261*/ GIMT_Encode4(311501), // Rule ID 11922 // |
| 99127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99128 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99129 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99130 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99131 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99132 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 99133 | GIM_CheckHasOneUse, /*MI*/1, |
| 99134 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99136 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99137 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99138 | // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 99144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 99145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 99146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 99147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99149 | GIR_RootConstrainSelectedInstOperands, |
| 99150 | // GIR_Coverage, 11922, |
| 99151 | GIR_EraseRootFromParent_Done, |
| 99152 | // Label 5261: @311501 |
| 99153 | GIM_Try, /*On fail goto*//*Label 5262*/ GIMT_Encode4(311597), // Rule ID 11921 // |
| 99154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99155 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99156 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 99157 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99158 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99159 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 99160 | GIM_CheckHasOneUse, /*MI*/1, |
| 99161 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99163 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99164 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99165 | // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 99171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 99172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 99173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 99174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99176 | GIR_RootConstrainSelectedInstOperands, |
| 99177 | // GIR_Coverage, 11921, |
| 99178 | GIR_EraseRootFromParent_Done, |
| 99179 | // Label 5262: @311597 |
| 99180 | GIM_Try, /*On fail goto*//*Label 5263*/ GIMT_Encode4(311693), // Rule ID 7391 // |
| 99181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99183 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99184 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99185 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99186 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 99187 | GIM_CheckHasOneUse, /*MI*/1, |
| 99188 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99189 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99190 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99191 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99192 | // (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99203 | GIR_RootConstrainSelectedInstOperands, |
| 99204 | // GIR_Coverage, 7391, |
| 99205 | GIR_EraseRootFromParent_Done, |
| 99206 | // Label 5263: @311693 |
| 99207 | GIM_Try, /*On fail goto*//*Label 5264*/ GIMT_Encode4(311789), // Rule ID 7390 // |
| 99208 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 99209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99211 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 99213 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 99214 | GIM_CheckHasOneUse, /*MI*/1, |
| 99215 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 99216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99217 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99218 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99219 | // (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 99221 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99230 | GIR_RootConstrainSelectedInstOperands, |
| 99231 | // GIR_Coverage, 7390, |
| 99232 | GIR_EraseRootFromParent_Done, |
| 99233 | // Label 5264: @311789 |
| 99234 | GIM_Try, /*On fail goto*//*Label 5265*/ GIMT_Encode4(311824), // Rule ID 93 // |
| 99235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 99236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 99237 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 99238 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 99239 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18519), |
| 99240 | // (fminnum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18519>> => (S_MIN_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 99241 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F32), |
| 99242 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 99243 | GIR_RootConstrainSelectedInstOperands, |
| 99244 | // GIR_Coverage, 93, |
| 99245 | GIR_Done, |
| 99246 | // Label 5265: @311824 |
| 99247 | GIM_Try, /*On fail goto*//*Label 5266*/ GIMT_Encode4(311884), // Rule ID 738 // |
| 99248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99249 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99251 | // (fminnum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99252 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64), |
| 99253 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 99255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 99257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 99259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 99260 | GIR_RootConstrainSelectedInstOperands, |
| 99261 | // GIR_Coverage, 738, |
| 99262 | GIR_EraseRootFromParent_Done, |
| 99263 | // Label 5266: @311884 |
| 99264 | GIM_Try, /*On fail goto*//*Label 5267*/ GIMT_Encode4(311944), // Rule ID 8058 // |
| 99265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99266 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99268 | // (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64), |
| 99270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 99272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 99274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 99276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 99277 | GIR_RootConstrainSelectedInstOperands, |
| 99278 | // GIR_Coverage, 8058, |
| 99279 | GIR_EraseRootFromParent_Done, |
| 99280 | // Label 5267: @311944 |
| 99281 | GIM_Reject, |
| 99282 | // Label 5128: @311945 |
| 99283 | GIM_Reject, |
| 99284 | // Label 4982: @311946 |
| 99285 | GIM_Try, /*On fail goto*//*Label 5268*/ GIMT_Encode4(312198), |
| 99286 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 99287 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 99288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 99289 | GIM_Try, /*On fail goto*//*Label 5269*/ GIMT_Encode4(312020), // Rule ID 839 // |
| 99290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 99291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99293 | // (fminnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64), |
| 99295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 99297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 99299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 99301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 99302 | GIR_RootConstrainSelectedInstOperands, |
| 99303 | // GIR_Coverage, 839, |
| 99304 | GIR_EraseRootFromParent_Done, |
| 99305 | // Label 5269: @312020 |
| 99306 | GIM_Try, /*On fail goto*//*Label 5270*/ GIMT_Encode4(312079), // Rule ID 858 // |
| 99307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 99308 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99309 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99310 | // (fminnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64), |
| 99312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 99314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 99316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 99318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 99319 | GIR_RootConstrainSelectedInstOperands, |
| 99320 | // GIR_Coverage, 858, |
| 99321 | GIR_EraseRootFromParent_Done, |
| 99322 | // Label 5270: @312079 |
| 99323 | GIM_Try, /*On fail goto*//*Label 5271*/ GIMT_Encode4(312138), // Rule ID 8084 // |
| 99324 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 99325 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99327 | // (fminnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64), |
| 99329 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 99331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 99333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 99335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 99336 | GIR_RootConstrainSelectedInstOperands, |
| 99337 | // GIR_Coverage, 8084, |
| 99338 | GIR_EraseRootFromParent_Done, |
| 99339 | // Label 5271: @312138 |
| 99340 | GIM_Try, /*On fail goto*//*Label 5272*/ GIMT_Encode4(312197), // Rule ID 8098 // |
| 99341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 99342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99343 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 99344 | // (fminnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 99345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64), |
| 99346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 99348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 99350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 99352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 99353 | GIR_RootConstrainSelectedInstOperands, |
| 99354 | // GIR_Coverage, 8098, |
| 99355 | GIR_EraseRootFromParent_Done, |
| 99356 | // Label 5272: @312197 |
| 99357 | GIM_Reject, |
| 99358 | // Label 5268: @312198 |
| 99359 | GIM_Reject, |
| 99360 | // Label 4983: @312199 |
| 99361 | GIM_Try, /*On fail goto*//*Label 5273*/ GIMT_Encode4(312270), // Rule ID 964 // |
| 99362 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 99363 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 99364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99365 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 99366 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 99367 | // (fminnum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MIN_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 99368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_F16), |
| 99369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 99371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 99373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99379 | GIR_RootConstrainSelectedInstOperands, |
| 99380 | // GIR_Coverage, 964, |
| 99381 | GIR_EraseRootFromParent_Done, |
| 99382 | // Label 5273: @312270 |
| 99383 | GIM_Reject, |
| 99384 | // Label 4984: @312271 |
| 99385 | GIM_Reject, |
| 99386 | // Label 81: @312272 |
| 99387 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5278*/ GIMT_Encode4(348610), |
| 99388 | /*GILLT_s16*//*Label 5274*/ GIMT_Encode4(312299), |
| 99389 | /*GILLT_s32*//*Label 5275*/ GIMT_Encode4(330773), |
| 99390 | /*GILLT_s64*//*Label 5276*/ GIMT_Encode4(348285), |
| 99391 | /*GILLT_v2s16*//*Label 5277*/ GIMT_Encode4(348538), |
| 99392 | // Label 5274: @312299 |
| 99393 | GIM_Try, /*On fail goto*//*Label 5279*/ GIMT_Encode4(330772), |
| 99394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 99395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 99396 | GIM_Try, /*On fail goto*//*Label 5280*/ GIMT_Encode4(312445), // Rule ID 11657 // |
| 99397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99399 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99400 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99401 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99402 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99403 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99404 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99405 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99406 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99407 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99408 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99409 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99410 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99411 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99412 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99413 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99414 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99415 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99416 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99417 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99418 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99430 | GIR_RootConstrainSelectedInstOperands, |
| 99431 | // GIR_Coverage, 11657, |
| 99432 | GIR_EraseRootFromParent_Done, |
| 99433 | // Label 5280: @312445 |
| 99434 | GIM_Try, /*On fail goto*//*Label 5281*/ GIMT_Encode4(312580), // Rule ID 11658 // |
| 99435 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99436 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99437 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99438 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99439 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99440 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99441 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99442 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99443 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99444 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99445 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99446 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99447 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99448 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99449 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99450 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99451 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99452 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99453 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99454 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99455 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99456 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99468 | GIR_RootConstrainSelectedInstOperands, |
| 99469 | // GIR_Coverage, 11658, |
| 99470 | GIR_EraseRootFromParent_Done, |
| 99471 | // Label 5281: @312580 |
| 99472 | GIM_Try, /*On fail goto*//*Label 5282*/ GIMT_Encode4(312715), // Rule ID 11661 // |
| 99473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99475 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99476 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99477 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99478 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99479 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99480 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99481 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99482 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99483 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99484 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99485 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99486 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99487 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99488 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99489 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99490 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99491 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99492 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99493 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99494 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99506 | GIR_RootConstrainSelectedInstOperands, |
| 99507 | // GIR_Coverage, 11661, |
| 99508 | GIR_EraseRootFromParent_Done, |
| 99509 | // Label 5282: @312715 |
| 99510 | GIM_Try, /*On fail goto*//*Label 5283*/ GIMT_Encode4(312850), // Rule ID 11662 // |
| 99511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99513 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99514 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99515 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99516 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99517 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99518 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99519 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99520 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99521 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99522 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99523 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99524 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99525 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99526 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99527 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99528 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99529 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99530 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99531 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99532 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99544 | GIR_RootConstrainSelectedInstOperands, |
| 99545 | // GIR_Coverage, 11662, |
| 99546 | GIR_EraseRootFromParent_Done, |
| 99547 | // Label 5283: @312850 |
| 99548 | GIM_Try, /*On fail goto*//*Label 5284*/ GIMT_Encode4(312985), // Rule ID 11642 // |
| 99549 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99551 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99552 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99553 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99554 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99556 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99557 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99558 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99559 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99560 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99561 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99562 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99563 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99564 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99565 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99566 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99567 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99568 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99569 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99570 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99582 | GIR_RootConstrainSelectedInstOperands, |
| 99583 | // GIR_Coverage, 11642, |
| 99584 | GIR_EraseRootFromParent_Done, |
| 99585 | // Label 5284: @312985 |
| 99586 | GIM_Try, /*On fail goto*//*Label 5285*/ GIMT_Encode4(313120), // Rule ID 11643 // |
| 99587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99589 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99590 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99591 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99592 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99593 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99594 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99595 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99596 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99597 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99598 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99599 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99600 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99601 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99602 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99603 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99604 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99605 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99606 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99607 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99608 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99617 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99618 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99620 | GIR_RootConstrainSelectedInstOperands, |
| 99621 | // GIR_Coverage, 11643, |
| 99622 | GIR_EraseRootFromParent_Done, |
| 99623 | // Label 5285: @313120 |
| 99624 | GIM_Try, /*On fail goto*//*Label 5286*/ GIMT_Encode4(313255), // Rule ID 11646 // |
| 99625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99627 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99628 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99629 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99630 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99631 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99632 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99633 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99634 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99635 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99636 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99637 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99638 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99639 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99640 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99641 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99642 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99643 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99644 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99645 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99646 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99658 | GIR_RootConstrainSelectedInstOperands, |
| 99659 | // GIR_Coverage, 11646, |
| 99660 | GIR_EraseRootFromParent_Done, |
| 99661 | // Label 5286: @313255 |
| 99662 | GIM_Try, /*On fail goto*//*Label 5287*/ GIMT_Encode4(313390), // Rule ID 11647 // |
| 99663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99665 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99666 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99667 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99668 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99669 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99670 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99671 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99672 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99673 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 99674 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99675 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99676 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99677 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99678 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99679 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99680 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99681 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99682 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99683 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99684 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99696 | GIR_RootConstrainSelectedInstOperands, |
| 99697 | // GIR_Coverage, 11647, |
| 99698 | GIR_EraseRootFromParent_Done, |
| 99699 | // Label 5287: @313390 |
| 99700 | GIM_Try, /*On fail goto*//*Label 5288*/ GIMT_Encode4(313525), // Rule ID 7363 // |
| 99701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99703 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99704 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99705 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99706 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99707 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99708 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99709 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99710 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99711 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99712 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99713 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99714 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99715 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99716 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99717 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99718 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99719 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99720 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99721 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99722 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99732 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99734 | GIR_RootConstrainSelectedInstOperands, |
| 99735 | // GIR_Coverage, 7363, |
| 99736 | GIR_EraseRootFromParent_Done, |
| 99737 | // Label 5288: @313525 |
| 99738 | GIM_Try, /*On fail goto*//*Label 5289*/ GIMT_Encode4(313660), // Rule ID 11656 // |
| 99739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99740 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99741 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99742 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99743 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99744 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99745 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99746 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99747 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99748 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99749 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99750 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99751 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99752 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99753 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99754 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99755 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99756 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99757 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99758 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99759 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99760 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99762 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99769 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99770 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99772 | GIR_RootConstrainSelectedInstOperands, |
| 99773 | // GIR_Coverage, 11656, |
| 99774 | GIR_EraseRootFromParent_Done, |
| 99775 | // Label 5289: @313660 |
| 99776 | GIM_Try, /*On fail goto*//*Label 5290*/ GIMT_Encode4(313795), // Rule ID 11659 // |
| 99777 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99779 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99780 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99781 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99782 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99783 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99784 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99785 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99786 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99787 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99788 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99789 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99790 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99791 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99792 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99794 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99795 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99796 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99797 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99798 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99810 | GIR_RootConstrainSelectedInstOperands, |
| 99811 | // GIR_Coverage, 11659, |
| 99812 | GIR_EraseRootFromParent_Done, |
| 99813 | // Label 5290: @313795 |
| 99814 | GIM_Try, /*On fail goto*//*Label 5291*/ GIMT_Encode4(313930), // Rule ID 11660 // |
| 99815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99817 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99818 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99819 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99820 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99821 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99822 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99823 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99824 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99825 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99826 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 99827 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99828 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99829 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99832 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99833 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99834 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99835 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99836 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99848 | GIR_RootConstrainSelectedInstOperands, |
| 99849 | // GIR_Coverage, 11660, |
| 99850 | GIR_EraseRootFromParent_Done, |
| 99851 | // Label 5291: @313930 |
| 99852 | GIM_Try, /*On fail goto*//*Label 5292*/ GIMT_Encode4(314065), // Rule ID 7362 // |
| 99853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99855 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99856 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99857 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99858 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99859 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99860 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99861 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99862 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99863 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99864 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99865 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99866 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99867 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99869 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99870 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99871 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99872 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99873 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99874 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99886 | GIR_RootConstrainSelectedInstOperands, |
| 99887 | // GIR_Coverage, 7362, |
| 99888 | GIR_EraseRootFromParent_Done, |
| 99889 | // Label 5292: @314065 |
| 99890 | GIM_Try, /*On fail goto*//*Label 5293*/ GIMT_Encode4(314200), // Rule ID 11641 // |
| 99891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99894 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99896 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99897 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99898 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99899 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99900 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99901 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99902 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99903 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99904 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99905 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99908 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99909 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99910 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99911 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99912 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 99916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 99917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 99918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 99919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99924 | GIR_RootConstrainSelectedInstOperands, |
| 99925 | // GIR_Coverage, 11641, |
| 99926 | GIR_EraseRootFromParent_Done, |
| 99927 | // Label 5293: @314200 |
| 99928 | GIM_Try, /*On fail goto*//*Label 5294*/ GIMT_Encode4(314335), // Rule ID 11644 // |
| 99929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99934 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99935 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99936 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99937 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99938 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99939 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99940 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99941 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99942 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99943 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99945 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99946 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99948 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99949 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99950 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99962 | GIR_RootConstrainSelectedInstOperands, |
| 99963 | // GIR_Coverage, 11644, |
| 99964 | GIR_EraseRootFromParent_Done, |
| 99965 | // Label 5294: @314335 |
| 99966 | GIM_Try, /*On fail goto*//*Label 5295*/ GIMT_Encode4(314470), // Rule ID 11645 // |
| 99967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 99968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 99969 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 99970 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99971 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 99972 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 99973 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 99974 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 99975 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 99976 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 99977 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 99978 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 99979 | // MIs[3] VOP3Mods:src1:src1_mods |
| 99980 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 99981 | // MIs[3] VOP3Mods:src0:src0_mods |
| 99982 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 99983 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 99984 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 99985 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 99986 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 99987 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 99988 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 99989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 99990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 99991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 99992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 99993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 99994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 99995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 99996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 99997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 99999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100000 | GIR_RootConstrainSelectedInstOperands, |
| 100001 | // GIR_Coverage, 11645, |
| 100002 | GIR_EraseRootFromParent_Done, |
| 100003 | // Label 5295: @314470 |
| 100004 | GIM_Try, /*On fail goto*//*Label 5296*/ GIMT_Encode4(314605), // Rule ID 11627 // |
| 100005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100010 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100011 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100012 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100013 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100014 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100015 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100016 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100017 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100018 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100019 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100020 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100021 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100022 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100023 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100024 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100025 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100026 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100038 | GIR_RootConstrainSelectedInstOperands, |
| 100039 | // GIR_Coverage, 11627, |
| 100040 | GIR_EraseRootFromParent_Done, |
| 100041 | // Label 5296: @314605 |
| 100042 | GIM_Try, /*On fail goto*//*Label 5297*/ GIMT_Encode4(314740), // Rule ID 11628 // |
| 100043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100045 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100046 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100047 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100048 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100049 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100050 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100051 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100052 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100053 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100054 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100055 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100056 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100057 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100059 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100060 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100061 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100062 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100063 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100064 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100076 | GIR_RootConstrainSelectedInstOperands, |
| 100077 | // GIR_Coverage, 11628, |
| 100078 | GIR_EraseRootFromParent_Done, |
| 100079 | // Label 5297: @314740 |
| 100080 | GIM_Try, /*On fail goto*//*Label 5298*/ GIMT_Encode4(314875), // Rule ID 11631 // |
| 100081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100084 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100086 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100087 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100088 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100089 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100090 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100091 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100092 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100093 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100094 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100095 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100096 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100097 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100098 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100099 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100100 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100101 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100102 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100114 | GIR_RootConstrainSelectedInstOperands, |
| 100115 | // GIR_Coverage, 11631, |
| 100116 | GIR_EraseRootFromParent_Done, |
| 100117 | // Label 5298: @314875 |
| 100118 | GIM_Try, /*On fail goto*//*Label 5299*/ GIMT_Encode4(315010), // Rule ID 11632 // |
| 100119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100121 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100122 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100123 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100124 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100125 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100126 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100127 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100128 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100129 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100130 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100131 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100132 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100133 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100134 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100135 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100136 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100137 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100138 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100139 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100140 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100152 | GIR_RootConstrainSelectedInstOperands, |
| 100153 | // GIR_Coverage, 11632, |
| 100154 | GIR_EraseRootFromParent_Done, |
| 100155 | // Label 5299: @315010 |
| 100156 | GIM_Try, /*On fail goto*//*Label 5300*/ GIMT_Encode4(315145), // Rule ID 11612 // |
| 100157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100159 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100160 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100161 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100162 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100163 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100164 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100165 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100166 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100167 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100168 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100169 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100170 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100171 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100172 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100173 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100174 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100175 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100176 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100177 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100178 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100190 | GIR_RootConstrainSelectedInstOperands, |
| 100191 | // GIR_Coverage, 11612, |
| 100192 | GIR_EraseRootFromParent_Done, |
| 100193 | // Label 5300: @315145 |
| 100194 | GIM_Try, /*On fail goto*//*Label 5301*/ GIMT_Encode4(315280), // Rule ID 11613 // |
| 100195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100197 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100198 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100199 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100200 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100201 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100202 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100203 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100204 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100205 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100206 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100207 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100208 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100209 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100211 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100212 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100213 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100214 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100215 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100216 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100228 | GIR_RootConstrainSelectedInstOperands, |
| 100229 | // GIR_Coverage, 11613, |
| 100230 | GIR_EraseRootFromParent_Done, |
| 100231 | // Label 5301: @315280 |
| 100232 | GIM_Try, /*On fail goto*//*Label 5302*/ GIMT_Encode4(315415), // Rule ID 11616 // |
| 100233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100235 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100236 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100237 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100238 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100239 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100240 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100241 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100242 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100243 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100244 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100245 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100246 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100247 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100248 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100249 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100250 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100251 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100252 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100253 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100254 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100266 | GIR_RootConstrainSelectedInstOperands, |
| 100267 | // GIR_Coverage, 11616, |
| 100268 | GIR_EraseRootFromParent_Done, |
| 100269 | // Label 5302: @315415 |
| 100270 | GIM_Try, /*On fail goto*//*Label 5303*/ GIMT_Encode4(315550), // Rule ID 11617 // |
| 100271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100273 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100274 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100275 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100276 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100277 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100278 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100279 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100280 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100281 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 100282 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100283 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100284 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100285 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100286 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100287 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100288 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100289 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100290 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100291 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100292 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100304 | GIR_RootConstrainSelectedInstOperands, |
| 100305 | // GIR_Coverage, 11617, |
| 100306 | GIR_EraseRootFromParent_Done, |
| 100307 | // Label 5303: @315550 |
| 100308 | GIM_Try, /*On fail goto*//*Label 5304*/ GIMT_Encode4(315685), // Rule ID 7361 // |
| 100309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100312 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100314 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100315 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100316 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100317 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100318 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100319 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100320 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100321 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100322 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100323 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100325 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100326 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100327 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100328 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100329 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100330 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100342 | GIR_RootConstrainSelectedInstOperands, |
| 100343 | // GIR_Coverage, 7361, |
| 100344 | GIR_EraseRootFromParent_Done, |
| 100345 | // Label 5304: @315685 |
| 100346 | GIM_Try, /*On fail goto*//*Label 5305*/ GIMT_Encode4(315820), // Rule ID 11626 // |
| 100347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100353 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100354 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100355 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100356 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100357 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100358 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100359 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100360 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100361 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100363 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100364 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100365 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100366 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100367 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100368 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100380 | GIR_RootConstrainSelectedInstOperands, |
| 100381 | // GIR_Coverage, 11626, |
| 100382 | GIR_EraseRootFromParent_Done, |
| 100383 | // Label 5305: @315820 |
| 100384 | GIM_Try, /*On fail goto*//*Label 5306*/ GIMT_Encode4(315955), // Rule ID 11629 // |
| 100385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100387 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100388 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100389 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100390 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100391 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100392 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100393 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100394 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100395 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100396 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100397 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100398 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100399 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100400 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100401 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100402 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100403 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100404 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100405 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100406 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100418 | GIR_RootConstrainSelectedInstOperands, |
| 100419 | // GIR_Coverage, 11629, |
| 100420 | GIR_EraseRootFromParent_Done, |
| 100421 | // Label 5306: @315955 |
| 100422 | GIM_Try, /*On fail goto*//*Label 5307*/ GIMT_Encode4(316090), // Rule ID 11630 // |
| 100423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100425 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100426 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100427 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100428 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100429 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100430 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100431 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100432 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100433 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100434 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100435 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100436 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100437 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100438 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100439 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100440 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100441 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100442 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100443 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100444 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100456 | GIR_RootConstrainSelectedInstOperands, |
| 100457 | // GIR_Coverage, 11630, |
| 100458 | GIR_EraseRootFromParent_Done, |
| 100459 | // Label 5307: @316090 |
| 100460 | GIM_Try, /*On fail goto*//*Label 5308*/ GIMT_Encode4(316225), // Rule ID 7360 // |
| 100461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100463 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100464 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100465 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100466 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100467 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100468 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100469 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100470 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100471 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100472 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100473 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100474 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100475 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100476 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100477 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100478 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100479 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100480 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100481 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100482 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100494 | GIR_RootConstrainSelectedInstOperands, |
| 100495 | // GIR_Coverage, 7360, |
| 100496 | GIR_EraseRootFromParent_Done, |
| 100497 | // Label 5308: @316225 |
| 100498 | GIM_Try, /*On fail goto*//*Label 5309*/ GIMT_Encode4(316360), // Rule ID 11611 // |
| 100499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100501 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100502 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100503 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100504 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100505 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100506 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100507 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100508 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100509 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100510 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100511 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100512 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100513 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100514 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100515 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100516 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100517 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100518 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100519 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100520 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 100524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 100525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100532 | GIR_RootConstrainSelectedInstOperands, |
| 100533 | // GIR_Coverage, 11611, |
| 100534 | GIR_EraseRootFromParent_Done, |
| 100535 | // Label 5309: @316360 |
| 100536 | GIM_Try, /*On fail goto*//*Label 5310*/ GIMT_Encode4(316495), // Rule ID 11614 // |
| 100537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100539 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100540 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100541 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100542 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100543 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100544 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100545 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100546 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100547 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100548 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100549 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100550 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100551 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100553 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100554 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100555 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100556 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100557 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100558 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100570 | GIR_RootConstrainSelectedInstOperands, |
| 100571 | // GIR_Coverage, 11614, |
| 100572 | GIR_EraseRootFromParent_Done, |
| 100573 | // Label 5310: @316495 |
| 100574 | GIM_Try, /*On fail goto*//*Label 5311*/ GIMT_Encode4(316630), // Rule ID 11615 // |
| 100575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100580 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 100582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100584 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100585 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 100586 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100587 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100588 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 100589 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 100591 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100592 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100593 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100594 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100595 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100596 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 100602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 100603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 100604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 100605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100608 | GIR_RootConstrainSelectedInstOperands, |
| 100609 | // GIR_Coverage, 11615, |
| 100610 | GIR_EraseRootFromParent_Done, |
| 100611 | // Label 5311: @316630 |
| 100612 | GIM_Try, /*On fail goto*//*Label 5312*/ GIMT_Encode4(316765), // Rule ID 11667 // |
| 100613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100616 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100617 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100618 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100619 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100620 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100621 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100622 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100623 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100624 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100625 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100626 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100627 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100629 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100630 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100631 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100632 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100633 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100634 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100646 | GIR_RootConstrainSelectedInstOperands, |
| 100647 | // GIR_Coverage, 11667, |
| 100648 | GIR_EraseRootFromParent_Done, |
| 100649 | // Label 5312: @316765 |
| 100650 | GIM_Try, /*On fail goto*//*Label 5313*/ GIMT_Encode4(316900), // Rule ID 11668 // |
| 100651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100653 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100654 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100655 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100656 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100657 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100658 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100659 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100660 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100661 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100662 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100663 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100664 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100665 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100666 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100667 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100668 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100669 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100670 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100671 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100672 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100684 | GIR_RootConstrainSelectedInstOperands, |
| 100685 | // GIR_Coverage, 11668, |
| 100686 | GIR_EraseRootFromParent_Done, |
| 100687 | // Label 5313: @316900 |
| 100688 | GIM_Try, /*On fail goto*//*Label 5314*/ GIMT_Encode4(317035), // Rule ID 11669 // |
| 100689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100692 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100693 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100694 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100695 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100696 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100697 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100698 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100699 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100700 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100701 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100702 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100703 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100705 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100706 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100707 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100708 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100709 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100710 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 100714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 100715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100722 | GIR_RootConstrainSelectedInstOperands, |
| 100723 | // GIR_Coverage, 11669, |
| 100724 | GIR_EraseRootFromParent_Done, |
| 100725 | // Label 5314: @317035 |
| 100726 | GIM_Try, /*On fail goto*//*Label 5315*/ GIMT_Encode4(317170), // Rule ID 11670 // |
| 100727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100730 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100731 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100732 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100733 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100734 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100735 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100736 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100737 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100738 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100739 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100740 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100741 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100743 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100744 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100745 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100746 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100747 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100748 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 100752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 100753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100760 | GIR_RootConstrainSelectedInstOperands, |
| 100761 | // GIR_Coverage, 11670, |
| 100762 | GIR_EraseRootFromParent_Done, |
| 100763 | // Label 5315: @317170 |
| 100764 | GIM_Try, /*On fail goto*//*Label 5316*/ GIMT_Encode4(317305), // Rule ID 11607 // |
| 100765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100768 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100770 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100771 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100772 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100773 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100774 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100775 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100776 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100777 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100778 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100779 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100780 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100781 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100782 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100783 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100784 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100785 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100786 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100798 | GIR_RootConstrainSelectedInstOperands, |
| 100799 | // GIR_Coverage, 11607, |
| 100800 | GIR_EraseRootFromParent_Done, |
| 100801 | // Label 5316: @317305 |
| 100802 | GIM_Try, /*On fail goto*//*Label 5317*/ GIMT_Encode4(317440), // Rule ID 11608 // |
| 100803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100806 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100808 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100809 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100810 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100811 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100812 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100813 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100814 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100815 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100816 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100817 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100818 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100819 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100820 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100821 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100822 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100823 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100824 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100836 | GIR_RootConstrainSelectedInstOperands, |
| 100837 | // GIR_Coverage, 11608, |
| 100838 | GIR_EraseRootFromParent_Done, |
| 100839 | // Label 5317: @317440 |
| 100840 | GIM_Try, /*On fail goto*//*Label 5318*/ GIMT_Encode4(317575), // Rule ID 11609 // |
| 100841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100843 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100844 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100845 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100846 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100847 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100848 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100849 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100850 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100851 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100852 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100853 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100854 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100855 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100856 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100857 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100858 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100859 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100860 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100861 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100862 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 100866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 100867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100874 | GIR_RootConstrainSelectedInstOperands, |
| 100875 | // GIR_Coverage, 11609, |
| 100876 | GIR_EraseRootFromParent_Done, |
| 100877 | // Label 5318: @317575 |
| 100878 | GIM_Try, /*On fail goto*//*Label 5319*/ GIMT_Encode4(317710), // Rule ID 11610 // |
| 100879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100882 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100883 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100884 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100886 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 100887 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100888 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100889 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100890 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 100891 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100892 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100893 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100894 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100895 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100896 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100897 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100898 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100899 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100900 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 100904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 100905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 100906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 100907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100912 | GIR_RootConstrainSelectedInstOperands, |
| 100913 | // GIR_Coverage, 11610, |
| 100914 | GIR_EraseRootFromParent_Done, |
| 100915 | // Label 5319: @317710 |
| 100916 | GIM_Try, /*On fail goto*//*Label 5320*/ GIMT_Encode4(317845), // Rule ID 11652 // |
| 100917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100921 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100922 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100923 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100924 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100925 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100926 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100927 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100928 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100929 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100930 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100931 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100932 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100934 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100935 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100936 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100937 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100938 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100950 | GIR_RootConstrainSelectedInstOperands, |
| 100951 | // GIR_Coverage, 11652, |
| 100952 | GIR_EraseRootFromParent_Done, |
| 100953 | // Label 5320: @317845 |
| 100954 | GIM_Try, /*On fail goto*//*Label 5321*/ GIMT_Encode4(317980), // Rule ID 11653 // |
| 100955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100959 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100960 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100961 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 100962 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 100963 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 100964 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 100965 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 100966 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100967 | // MIs[3] VOP3Mods:src1:src1_mods |
| 100968 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 100969 | // MIs[3] VOP3Mods:src0:src0_mods |
| 100970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 100971 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 100972 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 100973 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 100974 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 100975 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 100976 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 100977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 100978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 100979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 100980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 100981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 100982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 100983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 100984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 100985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 100988 | GIR_RootConstrainSelectedInstOperands, |
| 100989 | // GIR_Coverage, 11653, |
| 100990 | GIR_EraseRootFromParent_Done, |
| 100991 | // Label 5321: @317980 |
| 100992 | GIM_Try, /*On fail goto*//*Label 5322*/ GIMT_Encode4(318115), // Rule ID 11654 // |
| 100993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 100994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 100995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 100996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 100997 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 100998 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 100999 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101000 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101001 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101002 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101003 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101004 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101005 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101006 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101007 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101010 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101011 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101012 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101013 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101014 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 101018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 101019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101026 | GIR_RootConstrainSelectedInstOperands, |
| 101027 | // GIR_Coverage, 11654, |
| 101028 | GIR_EraseRootFromParent_Done, |
| 101029 | // Label 5322: @318115 |
| 101030 | GIM_Try, /*On fail goto*//*Label 5323*/ GIMT_Encode4(318250), // Rule ID 11655 // |
| 101031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101040 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101041 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101042 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101043 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101044 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101045 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101046 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101047 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101048 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101049 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101050 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101051 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101052 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 101056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 101057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101064 | GIR_RootConstrainSelectedInstOperands, |
| 101065 | // GIR_Coverage, 11655, |
| 101066 | GIR_EraseRootFromParent_Done, |
| 101067 | // Label 5323: @318250 |
| 101068 | GIM_Try, /*On fail goto*//*Label 5324*/ GIMT_Encode4(318385), // Rule ID 11592 // |
| 101069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101074 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101075 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101076 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101077 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101078 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101079 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101080 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101081 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101082 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101083 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101085 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101086 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101087 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101088 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101089 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101090 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 101096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 101097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101102 | GIR_RootConstrainSelectedInstOperands, |
| 101103 | // GIR_Coverage, 11592, |
| 101104 | GIR_EraseRootFromParent_Done, |
| 101105 | // Label 5324: @318385 |
| 101106 | GIM_Try, /*On fail goto*//*Label 5325*/ GIMT_Encode4(318520), // Rule ID 11593 // |
| 101107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101109 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101110 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101111 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101112 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101113 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101114 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101115 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101116 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101117 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101118 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101119 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101120 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101121 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101123 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101124 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101125 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101126 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101127 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101128 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 101134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 101135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101140 | GIR_RootConstrainSelectedInstOperands, |
| 101141 | // GIR_Coverage, 11593, |
| 101142 | GIR_EraseRootFromParent_Done, |
| 101143 | // Label 5325: @318520 |
| 101144 | GIM_Try, /*On fail goto*//*Label 5326*/ GIMT_Encode4(318655), // Rule ID 11594 // |
| 101145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101149 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101150 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101151 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101152 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101153 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101154 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101155 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101156 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101157 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101158 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101159 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101160 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101161 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101162 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101163 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101164 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101165 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101166 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 101170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 101171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101178 | GIR_RootConstrainSelectedInstOperands, |
| 101179 | // GIR_Coverage, 11594, |
| 101180 | GIR_EraseRootFromParent_Done, |
| 101181 | // Label 5326: @318655 |
| 101182 | GIM_Try, /*On fail goto*//*Label 5327*/ GIMT_Encode4(318790), // Rule ID 11595 // |
| 101183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101186 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101187 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101188 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101189 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 101190 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101191 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101192 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101193 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101194 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101195 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101196 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101197 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101198 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101199 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101200 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101201 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101202 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101203 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101204 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 101208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 101209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 101212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 101213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101216 | GIR_RootConstrainSelectedInstOperands, |
| 101217 | // GIR_Coverage, 11595, |
| 101218 | GIR_EraseRootFromParent_Done, |
| 101219 | // Label 5327: @318790 |
| 101220 | GIM_Try, /*On fail goto*//*Label 5328*/ GIMT_Encode4(318925), // Rule ID 11663 // |
| 101221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101224 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101226 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101228 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101230 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101231 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101232 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101233 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101234 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101235 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101237 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101238 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101239 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101240 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101241 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101242 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101254 | GIR_RootConstrainSelectedInstOperands, |
| 101255 | // GIR_Coverage, 11663, |
| 101256 | GIR_EraseRootFromParent_Done, |
| 101257 | // Label 5328: @318925 |
| 101258 | GIM_Try, /*On fail goto*//*Label 5329*/ GIMT_Encode4(319060), // Rule ID 11664 // |
| 101259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101264 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101266 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101267 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101268 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101269 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101270 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101271 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101272 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101273 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101274 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101275 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101276 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101277 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101278 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101279 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101280 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101292 | GIR_RootConstrainSelectedInstOperands, |
| 101293 | // GIR_Coverage, 11664, |
| 101294 | GIR_EraseRootFromParent_Done, |
| 101295 | // Label 5329: @319060 |
| 101296 | GIM_Try, /*On fail goto*//*Label 5330*/ GIMT_Encode4(319195), // Rule ID 11665 // |
| 101297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101299 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101300 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101301 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101302 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101303 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101304 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101305 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101306 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101307 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101308 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101309 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101310 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101311 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101312 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101314 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101315 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101316 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101317 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101318 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101330 | GIR_RootConstrainSelectedInstOperands, |
| 101331 | // GIR_Coverage, 11665, |
| 101332 | GIR_EraseRootFromParent_Done, |
| 101333 | // Label 5330: @319195 |
| 101334 | GIM_Try, /*On fail goto*//*Label 5331*/ GIMT_Encode4(319330), // Rule ID 11666 // |
| 101335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101337 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101338 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101339 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101340 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101341 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101342 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101343 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101344 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101345 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101346 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101347 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101348 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101349 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101350 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101351 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101352 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101353 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101354 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101355 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101356 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101368 | GIR_RootConstrainSelectedInstOperands, |
| 101369 | // GIR_Coverage, 11666, |
| 101370 | GIR_EraseRootFromParent_Done, |
| 101371 | // Label 5331: @319330 |
| 101372 | GIM_Try, /*On fail goto*//*Label 5332*/ GIMT_Encode4(319465), // Rule ID 11603 // |
| 101373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101375 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101376 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101377 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101378 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101379 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101380 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101381 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101382 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101383 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101384 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101385 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101386 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101387 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101388 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101389 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101390 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101391 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101392 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101393 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101394 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101406 | GIR_RootConstrainSelectedInstOperands, |
| 101407 | // GIR_Coverage, 11603, |
| 101408 | GIR_EraseRootFromParent_Done, |
| 101409 | // Label 5332: @319465 |
| 101410 | GIM_Try, /*On fail goto*//*Label 5333*/ GIMT_Encode4(319600), // Rule ID 11604 // |
| 101411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101417 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101418 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101419 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101420 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101421 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101422 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101423 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101424 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101425 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101427 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101428 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101429 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101430 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101431 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101432 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101444 | GIR_RootConstrainSelectedInstOperands, |
| 101445 | // GIR_Coverage, 11604, |
| 101446 | GIR_EraseRootFromParent_Done, |
| 101447 | // Label 5333: @319600 |
| 101448 | GIM_Try, /*On fail goto*//*Label 5334*/ GIMT_Encode4(319735), // Rule ID 11605 // |
| 101449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101456 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101457 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101458 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101459 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101460 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101461 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101462 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101463 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101464 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101465 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101466 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101467 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101468 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101469 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101470 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101482 | GIR_RootConstrainSelectedInstOperands, |
| 101483 | // GIR_Coverage, 11605, |
| 101484 | GIR_EraseRootFromParent_Done, |
| 101485 | // Label 5334: @319735 |
| 101486 | GIM_Try, /*On fail goto*//*Label 5335*/ GIMT_Encode4(319870), // Rule ID 11606 // |
| 101487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101489 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101490 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101491 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101492 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101493 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101494 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101495 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101496 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101497 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101498 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101499 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101500 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101501 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101502 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101503 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101504 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101505 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101506 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101507 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101508 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101520 | GIR_RootConstrainSelectedInstOperands, |
| 101521 | // GIR_Coverage, 11606, |
| 101522 | GIR_EraseRootFromParent_Done, |
| 101523 | // Label 5335: @319870 |
| 101524 | GIM_Try, /*On fail goto*//*Label 5336*/ GIMT_Encode4(320005), // Rule ID 11648 // |
| 101525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101530 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101531 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101532 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101533 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101534 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101535 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101536 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101537 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101538 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101539 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101542 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101543 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101544 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101545 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101546 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101558 | GIR_RootConstrainSelectedInstOperands, |
| 101559 | // GIR_Coverage, 11648, |
| 101560 | GIR_EraseRootFromParent_Done, |
| 101561 | // Label 5336: @320005 |
| 101562 | GIM_Try, /*On fail goto*//*Label 5337*/ GIMT_Encode4(320140), // Rule ID 11649 // |
| 101563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101568 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101570 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101572 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101573 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101574 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101575 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101576 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101577 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101578 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101579 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101580 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101581 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101582 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101583 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101584 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101596 | GIR_RootConstrainSelectedInstOperands, |
| 101597 | // GIR_Coverage, 11649, |
| 101598 | GIR_EraseRootFromParent_Done, |
| 101599 | // Label 5337: @320140 |
| 101600 | GIM_Try, /*On fail goto*//*Label 5338*/ GIMT_Encode4(320275), // Rule ID 11650 // |
| 101601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101606 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101607 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101608 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101609 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101610 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101611 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101612 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101613 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101614 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101615 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101616 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101617 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101618 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101619 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101620 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101621 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101622 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101634 | GIR_RootConstrainSelectedInstOperands, |
| 101635 | // GIR_Coverage, 11650, |
| 101636 | GIR_EraseRootFromParent_Done, |
| 101637 | // Label 5338: @320275 |
| 101638 | GIM_Try, /*On fail goto*//*Label 5339*/ GIMT_Encode4(320410), // Rule ID 11651 // |
| 101639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101641 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101642 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101643 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101644 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101645 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101646 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101647 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101648 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101649 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101650 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101651 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101652 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101653 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101654 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101655 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101656 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101657 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101658 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101659 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101660 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101672 | GIR_RootConstrainSelectedInstOperands, |
| 101673 | // GIR_Coverage, 11651, |
| 101674 | GIR_EraseRootFromParent_Done, |
| 101675 | // Label 5339: @320410 |
| 101676 | GIM_Try, /*On fail goto*//*Label 5340*/ GIMT_Encode4(320545), // Rule ID 11588 // |
| 101677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101679 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101680 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101681 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101682 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101683 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101684 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101685 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101686 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101687 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101688 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101689 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101690 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101691 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101692 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101693 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101694 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101695 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101696 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101697 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101698 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101710 | GIR_RootConstrainSelectedInstOperands, |
| 101711 | // GIR_Coverage, 11588, |
| 101712 | GIR_EraseRootFromParent_Done, |
| 101713 | // Label 5340: @320545 |
| 101714 | GIM_Try, /*On fail goto*//*Label 5341*/ GIMT_Encode4(320680), // Rule ID 11589 // |
| 101715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101717 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101718 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101719 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101720 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101721 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101722 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101723 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101724 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101725 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101726 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101727 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101728 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101729 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101730 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101731 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101732 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101733 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101734 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101735 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101736 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101748 | GIR_RootConstrainSelectedInstOperands, |
| 101749 | // GIR_Coverage, 11589, |
| 101750 | GIR_EraseRootFromParent_Done, |
| 101751 | // Label 5341: @320680 |
| 101752 | GIM_Try, /*On fail goto*//*Label 5342*/ GIMT_Encode4(320815), // Rule ID 11590 // |
| 101753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101755 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101756 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101757 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101758 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101759 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101760 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101761 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101762 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101763 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101764 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101765 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101766 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101767 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101768 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101769 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101770 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101771 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101772 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101773 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101774 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101786 | GIR_RootConstrainSelectedInstOperands, |
| 101787 | // GIR_Coverage, 11590, |
| 101788 | GIR_EraseRootFromParent_Done, |
| 101789 | // Label 5342: @320815 |
| 101790 | GIM_Try, /*On fail goto*//*Label 5343*/ GIMT_Encode4(320950), // Rule ID 11591 // |
| 101791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101797 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 101798 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101799 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101800 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101801 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 101802 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101803 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101804 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 101805 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101806 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 101807 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101808 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101809 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101810 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101811 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101812 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101824 | GIR_RootConstrainSelectedInstOperands, |
| 101825 | // GIR_Coverage, 11591, |
| 101826 | GIR_EraseRootFromParent_Done, |
| 101827 | // Label 5343: @320950 |
| 101828 | GIM_Try, /*On fail goto*//*Label 5344*/ GIMT_Encode4(321085), // Rule ID 11597 // |
| 101829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101834 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101835 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 101836 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101837 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101838 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101839 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 101840 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101841 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101842 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 101843 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101844 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 101845 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101846 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101847 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101848 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101849 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101850 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101862 | GIR_RootConstrainSelectedInstOperands, |
| 101863 | // GIR_Coverage, 11597, |
| 101864 | GIR_EraseRootFromParent_Done, |
| 101865 | // Label 5344: @321085 |
| 101866 | GIM_Try, /*On fail goto*//*Label 5345*/ GIMT_Encode4(321220), // Rule ID 11598 // |
| 101867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101869 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101870 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101871 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101872 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101873 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 101874 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101875 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101876 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101877 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 101878 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101879 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101880 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 101881 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101882 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 101883 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101884 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101885 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101886 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101887 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101888 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 101892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 101893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 101894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 101895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101900 | GIR_RootConstrainSelectedInstOperands, |
| 101901 | // GIR_Coverage, 11598, |
| 101902 | GIR_EraseRootFromParent_Done, |
| 101903 | // Label 5345: @321220 |
| 101904 | GIM_Try, /*On fail goto*//*Label 5346*/ GIMT_Encode4(321355), // Rule ID 11601 // |
| 101905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101907 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101908 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101909 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101910 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101911 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 101912 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101913 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101914 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101915 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 101916 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101917 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101918 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 101919 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101920 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 101921 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101922 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101923 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101924 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101925 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101926 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101938 | GIR_RootConstrainSelectedInstOperands, |
| 101939 | // GIR_Coverage, 11601, |
| 101940 | GIR_EraseRootFromParent_Done, |
| 101941 | // Label 5346: @321355 |
| 101942 | GIM_Try, /*On fail goto*//*Label 5347*/ GIMT_Encode4(321490), // Rule ID 11602 // |
| 101943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101945 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101946 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101947 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101948 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101949 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 101950 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101951 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101952 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101953 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 101954 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 101955 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101956 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 101957 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101958 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 101959 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101960 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101961 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 101962 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 101963 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 101964 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 101965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 101966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 101967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 101968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 101969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 101970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 101971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 101972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 101973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 101976 | GIR_RootConstrainSelectedInstOperands, |
| 101977 | // GIR_Coverage, 11602, |
| 101978 | GIR_EraseRootFromParent_Done, |
| 101979 | // Label 5347: @321490 |
| 101980 | GIM_Try, /*On fail goto*//*Label 5348*/ GIMT_Encode4(321625), // Rule ID 11582 // |
| 101981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 101982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 101983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 101984 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 101985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 101986 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 101987 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 101988 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 101989 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 101990 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 101991 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 101992 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 101993 | // MIs[3] VOP3Mods:src0:src0_mods |
| 101994 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 101995 | // MIs[3] VOP3Mods:src1:src1_mods |
| 101996 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 101997 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 101998 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 101999 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102000 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102001 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102002 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102014 | GIR_RootConstrainSelectedInstOperands, |
| 102015 | // GIR_Coverage, 11582, |
| 102016 | GIR_EraseRootFromParent_Done, |
| 102017 | // Label 5348: @321625 |
| 102018 | GIM_Try, /*On fail goto*//*Label 5349*/ GIMT_Encode4(321760), // Rule ID 11583 // |
| 102019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102021 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102022 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102023 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102024 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102025 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102026 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102027 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102028 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102029 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102030 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102031 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102032 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102033 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102034 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102035 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102036 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102037 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102038 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102039 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102040 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102052 | GIR_RootConstrainSelectedInstOperands, |
| 102053 | // GIR_Coverage, 11583, |
| 102054 | GIR_EraseRootFromParent_Done, |
| 102055 | // Label 5349: @321760 |
| 102056 | GIM_Try, /*On fail goto*//*Label 5350*/ GIMT_Encode4(321895), // Rule ID 11586 // |
| 102057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102060 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102061 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102062 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102063 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102064 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102065 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102066 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102067 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102068 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102069 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102070 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102071 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102072 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102073 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102074 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102075 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102076 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102077 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102078 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102090 | GIR_RootConstrainSelectedInstOperands, |
| 102091 | // GIR_Coverage, 11586, |
| 102092 | GIR_EraseRootFromParent_Done, |
| 102093 | // Label 5350: @321895 |
| 102094 | GIM_Try, /*On fail goto*//*Label 5351*/ GIMT_Encode4(322030), // Rule ID 11587 // |
| 102095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102098 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102099 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102100 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102101 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102102 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102103 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102104 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102105 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102106 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102107 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102108 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102109 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102110 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102111 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102112 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102113 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102114 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102115 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102116 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102128 | GIR_RootConstrainSelectedInstOperands, |
| 102129 | // GIR_Coverage, 11587, |
| 102130 | GIR_EraseRootFromParent_Done, |
| 102131 | // Label 5351: @322030 |
| 102132 | GIM_Try, /*On fail goto*//*Label 5352*/ GIMT_Encode4(322165), // Rule ID 7359 // |
| 102133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102135 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102136 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102137 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102138 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102139 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102140 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102141 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102142 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102143 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102144 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102145 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102146 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102147 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102148 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102149 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102150 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102151 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102152 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102153 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102154 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102166 | GIR_RootConstrainSelectedInstOperands, |
| 102167 | // GIR_Coverage, 7359, |
| 102168 | GIR_EraseRootFromParent_Done, |
| 102169 | // Label 5352: @322165 |
| 102170 | GIM_Try, /*On fail goto*//*Label 5353*/ GIMT_Encode4(322300), // Rule ID 11596 // |
| 102171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102174 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102175 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102176 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102177 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102178 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102179 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102180 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102181 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102182 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102183 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102184 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102185 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102186 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102187 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102188 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102189 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102190 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102191 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102192 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102204 | GIR_RootConstrainSelectedInstOperands, |
| 102205 | // GIR_Coverage, 11596, |
| 102206 | GIR_EraseRootFromParent_Done, |
| 102207 | // Label 5353: @322300 |
| 102208 | GIM_Try, /*On fail goto*//*Label 5354*/ GIMT_Encode4(322435), // Rule ID 11599 // |
| 102209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102211 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102212 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102213 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102214 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102215 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102216 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102217 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102218 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102219 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102220 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102221 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102222 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102223 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102224 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102226 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102227 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102228 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102229 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102230 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102242 | GIR_RootConstrainSelectedInstOperands, |
| 102243 | // GIR_Coverage, 11599, |
| 102244 | GIR_EraseRootFromParent_Done, |
| 102245 | // Label 5354: @322435 |
| 102246 | GIM_Try, /*On fail goto*//*Label 5355*/ GIMT_Encode4(322570), // Rule ID 11600 // |
| 102247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102249 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102250 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102251 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102252 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102253 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102254 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102255 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102256 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102257 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102258 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102259 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102260 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102261 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102262 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102263 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102264 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102265 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102266 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102267 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102268 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102280 | GIR_RootConstrainSelectedInstOperands, |
| 102281 | // GIR_Coverage, 11600, |
| 102282 | GIR_EraseRootFromParent_Done, |
| 102283 | // Label 5355: @322570 |
| 102284 | GIM_Try, /*On fail goto*//*Label 5356*/ GIMT_Encode4(322705), // Rule ID 7358 // |
| 102285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102287 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102288 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102289 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102290 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102292 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102293 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102294 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102295 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102296 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102297 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102298 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102299 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102300 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102301 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102302 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102303 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102304 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102305 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102306 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102318 | GIR_RootConstrainSelectedInstOperands, |
| 102319 | // GIR_Coverage, 7358, |
| 102320 | GIR_EraseRootFromParent_Done, |
| 102321 | // Label 5356: @322705 |
| 102322 | GIM_Try, /*On fail goto*//*Label 5357*/ GIMT_Encode4(322840), // Rule ID 11581 // |
| 102323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102326 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102328 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102329 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102330 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102331 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102332 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102333 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102334 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102335 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102336 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102337 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102338 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102339 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102340 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102341 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102342 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102343 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102344 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102356 | GIR_RootConstrainSelectedInstOperands, |
| 102357 | // GIR_Coverage, 11581, |
| 102358 | GIR_EraseRootFromParent_Done, |
| 102359 | // Label 5357: @322840 |
| 102360 | GIM_Try, /*On fail goto*//*Label 5358*/ GIMT_Encode4(322975), // Rule ID 11584 // |
| 102361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102363 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102364 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102365 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102366 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102367 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102368 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102369 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102370 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102371 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102372 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102373 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102374 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102375 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102376 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102377 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102378 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102379 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102380 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102381 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102382 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102394 | GIR_RootConstrainSelectedInstOperands, |
| 102395 | // GIR_Coverage, 11584, |
| 102396 | GIR_EraseRootFromParent_Done, |
| 102397 | // Label 5358: @322975 |
| 102398 | GIM_Try, /*On fail goto*//*Label 5359*/ GIMT_Encode4(323110), // Rule ID 11585 // |
| 102399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102402 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102403 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102404 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102405 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102406 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 102407 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102408 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102409 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102410 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102411 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102412 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102413 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102414 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102415 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102416 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102417 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102418 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102419 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102420 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102432 | GIR_RootConstrainSelectedInstOperands, |
| 102433 | // GIR_Coverage, 11585, |
| 102434 | GIR_EraseRootFromParent_Done, |
| 102435 | // Label 5359: @323110 |
| 102436 | GIM_Try, /*On fail goto*//*Label 5360*/ GIMT_Encode4(323245), // Rule ID 11567 // |
| 102437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102439 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102440 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102441 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102442 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102443 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102444 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102446 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102447 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102448 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102449 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102450 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102451 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102452 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102453 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102454 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102455 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102456 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102457 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102458 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102470 | GIR_RootConstrainSelectedInstOperands, |
| 102471 | // GIR_Coverage, 11567, |
| 102472 | GIR_EraseRootFromParent_Done, |
| 102473 | // Label 5360: @323245 |
| 102474 | GIM_Try, /*On fail goto*//*Label 5361*/ GIMT_Encode4(323380), // Rule ID 11568 // |
| 102475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102477 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102478 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102479 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102480 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102481 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102482 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102483 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102484 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102485 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102486 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102487 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102488 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102489 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102490 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102491 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102492 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102493 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102494 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102495 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102496 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102508 | GIR_RootConstrainSelectedInstOperands, |
| 102509 | // GIR_Coverage, 11568, |
| 102510 | GIR_EraseRootFromParent_Done, |
| 102511 | // Label 5361: @323380 |
| 102512 | GIM_Try, /*On fail goto*//*Label 5362*/ GIMT_Encode4(323515), // Rule ID 11571 // |
| 102513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102520 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102521 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102522 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102523 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102524 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102525 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102526 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102527 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102528 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102529 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102530 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102531 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102532 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102533 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102534 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102546 | GIR_RootConstrainSelectedInstOperands, |
| 102547 | // GIR_Coverage, 11571, |
| 102548 | GIR_EraseRootFromParent_Done, |
| 102549 | // Label 5362: @323515 |
| 102550 | GIM_Try, /*On fail goto*//*Label 5363*/ GIMT_Encode4(323650), // Rule ID 11572 // |
| 102551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102553 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102554 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102555 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102556 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102557 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102558 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102559 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102560 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102561 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102562 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102563 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102564 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102565 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102566 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102567 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102568 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102569 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102570 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102571 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102572 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102584 | GIR_RootConstrainSelectedInstOperands, |
| 102585 | // GIR_Coverage, 11572, |
| 102586 | GIR_EraseRootFromParent_Done, |
| 102587 | // Label 5363: @323650 |
| 102588 | GIM_Try, /*On fail goto*//*Label 5364*/ GIMT_Encode4(323785), // Rule ID 11552 // |
| 102589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102591 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102592 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102593 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102594 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102595 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102596 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102597 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102598 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102599 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102600 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102601 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102602 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102603 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102604 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102605 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102606 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102607 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102608 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102609 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102610 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102622 | GIR_RootConstrainSelectedInstOperands, |
| 102623 | // GIR_Coverage, 11552, |
| 102624 | GIR_EraseRootFromParent_Done, |
| 102625 | // Label 5364: @323785 |
| 102626 | GIM_Try, /*On fail goto*//*Label 5365*/ GIMT_Encode4(323920), // Rule ID 11553 // |
| 102627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102629 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102630 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102631 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102632 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102633 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102634 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102635 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102636 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102637 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102638 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102639 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102640 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102641 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102642 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102643 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102644 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102645 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102646 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102647 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102648 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102660 | GIR_RootConstrainSelectedInstOperands, |
| 102661 | // GIR_Coverage, 11553, |
| 102662 | GIR_EraseRootFromParent_Done, |
| 102663 | // Label 5365: @323920 |
| 102664 | GIM_Try, /*On fail goto*//*Label 5366*/ GIMT_Encode4(324055), // Rule ID 11556 // |
| 102665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102668 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102669 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102670 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102671 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102672 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102673 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102674 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102675 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102676 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102677 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102678 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102679 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102680 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102681 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102682 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102683 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102684 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102685 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102686 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102698 | GIR_RootConstrainSelectedInstOperands, |
| 102699 | // GIR_Coverage, 11556, |
| 102700 | GIR_EraseRootFromParent_Done, |
| 102701 | // Label 5366: @324055 |
| 102702 | GIM_Try, /*On fail goto*//*Label 5367*/ GIMT_Encode4(324190), // Rule ID 11557 // |
| 102703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102705 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102706 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102707 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102708 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102709 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102710 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102711 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102712 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102713 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 102714 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102715 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102716 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102717 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102718 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102719 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102720 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102721 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102722 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102723 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102724 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102736 | GIR_RootConstrainSelectedInstOperands, |
| 102737 | // GIR_Coverage, 11557, |
| 102738 | GIR_EraseRootFromParent_Done, |
| 102739 | // Label 5367: @324190 |
| 102740 | GIM_Try, /*On fail goto*//*Label 5368*/ GIMT_Encode4(324325), // Rule ID 7357 // |
| 102741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102748 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102749 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102750 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102751 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102752 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102753 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102754 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102755 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102756 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102757 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102758 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102759 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102760 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102761 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102762 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102774 | GIR_RootConstrainSelectedInstOperands, |
| 102775 | // GIR_Coverage, 7357, |
| 102776 | GIR_EraseRootFromParent_Done, |
| 102777 | // Label 5368: @324325 |
| 102778 | GIM_Try, /*On fail goto*//*Label 5369*/ GIMT_Encode4(324460), // Rule ID 11566 // |
| 102779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102781 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102782 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102783 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102784 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102785 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102786 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102787 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102788 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102789 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102790 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102791 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102792 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102793 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102794 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102795 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102796 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102797 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102798 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102799 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102800 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102812 | GIR_RootConstrainSelectedInstOperands, |
| 102813 | // GIR_Coverage, 11566, |
| 102814 | GIR_EraseRootFromParent_Done, |
| 102815 | // Label 5369: @324460 |
| 102816 | GIM_Try, /*On fail goto*//*Label 5370*/ GIMT_Encode4(324595), // Rule ID 11569 // |
| 102817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102819 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102820 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102821 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102822 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102823 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102824 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102825 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102826 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102827 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102828 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102829 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102831 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102832 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102833 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102834 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102835 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102836 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102837 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102838 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102850 | GIR_RootConstrainSelectedInstOperands, |
| 102851 | // GIR_Coverage, 11569, |
| 102852 | GIR_EraseRootFromParent_Done, |
| 102853 | // Label 5370: @324595 |
| 102854 | GIM_Try, /*On fail goto*//*Label 5371*/ GIMT_Encode4(324730), // Rule ID 11570 // |
| 102855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102858 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102861 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102862 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102863 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102864 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102865 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102866 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 102867 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102869 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102870 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102871 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102872 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102873 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102874 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102875 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102876 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102888 | GIR_RootConstrainSelectedInstOperands, |
| 102889 | // GIR_Coverage, 11570, |
| 102890 | GIR_EraseRootFromParent_Done, |
| 102891 | // Label 5371: @324730 |
| 102892 | GIM_Try, /*On fail goto*//*Label 5372*/ GIMT_Encode4(324865), // Rule ID 7356 // |
| 102893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102898 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102899 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102900 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102901 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102902 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102903 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102904 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102905 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102907 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102908 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102909 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102910 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102911 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102912 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102913 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102914 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102926 | GIR_RootConstrainSelectedInstOperands, |
| 102927 | // GIR_Coverage, 7356, |
| 102928 | GIR_EraseRootFromParent_Done, |
| 102929 | // Label 5372: @324865 |
| 102930 | GIM_Try, /*On fail goto*//*Label 5373*/ GIMT_Encode4(325000), // Rule ID 11551 // |
| 102931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102936 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102937 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102938 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102939 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102940 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102941 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102942 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102943 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102945 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102946 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102947 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102948 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102949 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102950 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102951 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102952 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 102956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 102957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 102958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 102959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 102964 | GIR_RootConstrainSelectedInstOperands, |
| 102965 | // GIR_Coverage, 11551, |
| 102966 | GIR_EraseRootFromParent_Done, |
| 102967 | // Label 5373: @325000 |
| 102968 | GIM_Try, /*On fail goto*//*Label 5374*/ GIMT_Encode4(325135), // Rule ID 11554 // |
| 102969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 102970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 102971 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 102972 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102973 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 102974 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 102975 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 102976 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 102977 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 102978 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 102979 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 102980 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 102981 | // MIs[3] VOP3Mods:src0:src0_mods |
| 102982 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 102983 | // MIs[3] VOP3Mods:src1:src1_mods |
| 102984 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 102985 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 102986 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 102987 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 102988 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 102989 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 102990 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 102991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 102992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 102993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 102994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 102995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 102996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 102997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 102998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 102999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103002 | GIR_RootConstrainSelectedInstOperands, |
| 103003 | // GIR_Coverage, 11554, |
| 103004 | GIR_EraseRootFromParent_Done, |
| 103005 | // Label 5374: @325135 |
| 103006 | GIM_Try, /*On fail goto*//*Label 5375*/ GIMT_Encode4(325270), // Rule ID 11555 // |
| 103007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103009 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103010 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103011 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103012 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103013 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 103014 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103015 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103016 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103017 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 103018 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103019 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103020 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 103021 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103022 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 103023 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103024 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103025 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103026 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103027 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103028 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 103034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 103035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103040 | GIR_RootConstrainSelectedInstOperands, |
| 103041 | // GIR_Coverage, 11555, |
| 103042 | GIR_EraseRootFromParent_Done, |
| 103043 | // Label 5375: @325270 |
| 103044 | GIM_Try, /*On fail goto*//*Label 5376*/ GIMT_Encode4(325405), // Rule ID 11637 // |
| 103045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103050 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103051 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103055 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103056 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103057 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103059 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103060 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103061 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103062 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103063 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103064 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103065 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103066 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103078 | GIR_RootConstrainSelectedInstOperands, |
| 103079 | // GIR_Coverage, 11637, |
| 103080 | GIR_EraseRootFromParent_Done, |
| 103081 | // Label 5376: @325405 |
| 103082 | GIM_Try, /*On fail goto*//*Label 5377*/ GIMT_Encode4(325540), // Rule ID 11638 // |
| 103083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103085 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103086 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103087 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103088 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103089 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103090 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103091 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103092 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103093 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103094 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103095 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103096 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103097 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103098 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103099 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103100 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103101 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103102 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103103 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103104 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103116 | GIR_RootConstrainSelectedInstOperands, |
| 103117 | // GIR_Coverage, 11638, |
| 103118 | GIR_EraseRootFromParent_Done, |
| 103119 | // Label 5377: @325540 |
| 103120 | GIM_Try, /*On fail goto*//*Label 5378*/ GIMT_Encode4(325675), // Rule ID 11639 // |
| 103121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103123 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103124 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103125 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103126 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103127 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103128 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103129 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103130 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103131 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103132 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103133 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103134 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103135 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103136 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103137 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103138 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103139 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103140 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103141 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103142 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103154 | GIR_RootConstrainSelectedInstOperands, |
| 103155 | // GIR_Coverage, 11639, |
| 103156 | GIR_EraseRootFromParent_Done, |
| 103157 | // Label 5378: @325675 |
| 103158 | GIM_Try, /*On fail goto*//*Label 5379*/ GIMT_Encode4(325810), // Rule ID 11640 // |
| 103159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103161 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103162 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103163 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103164 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103166 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103167 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103168 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103169 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103170 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103171 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103172 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103173 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103174 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103175 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103176 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103177 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103178 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103179 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103180 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103192 | GIR_RootConstrainSelectedInstOperands, |
| 103193 | // GIR_Coverage, 11640, |
| 103194 | GIR_EraseRootFromParent_Done, |
| 103195 | // Label 5379: @325810 |
| 103196 | GIM_Try, /*On fail goto*//*Label 5380*/ GIMT_Encode4(325945), // Rule ID 11577 // |
| 103197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103202 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103203 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103204 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103205 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103206 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103207 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103208 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103209 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103211 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103212 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103213 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103214 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103215 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103216 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103217 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103218 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103230 | GIR_RootConstrainSelectedInstOperands, |
| 103231 | // GIR_Coverage, 11577, |
| 103232 | GIR_EraseRootFromParent_Done, |
| 103233 | // Label 5380: @325945 |
| 103234 | GIM_Try, /*On fail goto*//*Label 5381*/ GIMT_Encode4(326080), // Rule ID 11578 // |
| 103235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103237 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103238 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103239 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103240 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103241 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103242 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103243 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103244 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103245 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103246 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103247 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103248 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103249 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103250 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103251 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103252 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103253 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103254 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103255 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103256 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103268 | GIR_RootConstrainSelectedInstOperands, |
| 103269 | // GIR_Coverage, 11578, |
| 103270 | GIR_EraseRootFromParent_Done, |
| 103271 | // Label 5381: @326080 |
| 103272 | GIM_Try, /*On fail goto*//*Label 5382*/ GIMT_Encode4(326215), // Rule ID 11579 // |
| 103273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103275 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103276 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103277 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103278 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103279 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103280 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103281 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103282 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103283 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103284 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103285 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103286 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103287 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103288 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103289 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103290 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103291 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103292 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103293 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103294 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103306 | GIR_RootConstrainSelectedInstOperands, |
| 103307 | // GIR_Coverage, 11579, |
| 103308 | GIR_EraseRootFromParent_Done, |
| 103309 | // Label 5382: @326215 |
| 103310 | GIM_Try, /*On fail goto*//*Label 5383*/ GIMT_Encode4(326350), // Rule ID 11580 // |
| 103311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103316 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103317 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103318 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103319 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103320 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103321 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103322 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103323 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103325 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103326 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103327 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103328 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103329 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103330 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103331 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103332 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103344 | GIR_RootConstrainSelectedInstOperands, |
| 103345 | // GIR_Coverage, 11580, |
| 103346 | GIR_EraseRootFromParent_Done, |
| 103347 | // Label 5383: @326350 |
| 103348 | GIM_Try, /*On fail goto*//*Label 5384*/ GIMT_Encode4(326485), // Rule ID 11622 // |
| 103349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103354 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103355 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103356 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103357 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103358 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103359 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103360 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103361 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103363 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103364 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103365 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103366 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103367 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103368 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103369 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103370 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103382 | GIR_RootConstrainSelectedInstOperands, |
| 103383 | // GIR_Coverage, 11622, |
| 103384 | GIR_EraseRootFromParent_Done, |
| 103385 | // Label 5384: @326485 |
| 103386 | GIM_Try, /*On fail goto*//*Label 5385*/ GIMT_Encode4(326620), // Rule ID 11623 // |
| 103387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103389 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103390 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103391 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103392 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103393 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103394 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103395 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103396 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103397 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103398 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103399 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103400 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103401 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103402 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103403 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103404 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103405 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103406 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103407 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103408 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103420 | GIR_RootConstrainSelectedInstOperands, |
| 103421 | // GIR_Coverage, 11623, |
| 103422 | GIR_EraseRootFromParent_Done, |
| 103423 | // Label 5385: @326620 |
| 103424 | GIM_Try, /*On fail goto*//*Label 5386*/ GIMT_Encode4(326755), // Rule ID 11624 // |
| 103425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103427 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103428 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103429 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103430 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103431 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103432 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103433 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103434 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103435 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103436 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103437 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103438 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103439 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103440 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103441 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103442 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103443 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103444 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103445 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103446 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103458 | GIR_RootConstrainSelectedInstOperands, |
| 103459 | // GIR_Coverage, 11624, |
| 103460 | GIR_EraseRootFromParent_Done, |
| 103461 | // Label 5386: @326755 |
| 103462 | GIM_Try, /*On fail goto*//*Label 5387*/ GIMT_Encode4(326890), // Rule ID 11625 // |
| 103463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103465 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103466 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103467 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103468 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103469 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103470 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103471 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103472 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103473 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103474 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103475 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103476 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103477 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103478 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103479 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103480 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103481 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103482 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103483 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103484 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103496 | GIR_RootConstrainSelectedInstOperands, |
| 103497 | // GIR_Coverage, 11625, |
| 103498 | GIR_EraseRootFromParent_Done, |
| 103499 | // Label 5387: @326890 |
| 103500 | GIM_Try, /*On fail goto*//*Label 5388*/ GIMT_Encode4(327025), // Rule ID 11562 // |
| 103501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103505 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103506 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103507 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103508 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103509 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103510 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103511 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103512 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103513 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103514 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103515 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103516 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103517 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103518 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103519 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103520 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103521 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103522 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103534 | GIR_RootConstrainSelectedInstOperands, |
| 103535 | // GIR_Coverage, 11562, |
| 103536 | GIR_EraseRootFromParent_Done, |
| 103537 | // Label 5388: @327025 |
| 103538 | GIM_Try, /*On fail goto*//*Label 5389*/ GIMT_Encode4(327160), // Rule ID 11563 // |
| 103539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103542 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103543 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103544 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103545 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103546 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103547 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103548 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103549 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103550 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103551 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103553 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103554 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103555 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103556 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103557 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103558 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103559 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103560 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 103566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 103567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103572 | GIR_RootConstrainSelectedInstOperands, |
| 103573 | // GIR_Coverage, 11563, |
| 103574 | GIR_EraseRootFromParent_Done, |
| 103575 | // Label 5389: @327160 |
| 103576 | GIM_Try, /*On fail goto*//*Label 5390*/ GIMT_Encode4(327295), // Rule ID 11564 // |
| 103577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103581 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103582 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103583 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103584 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103585 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103586 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103587 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103588 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103589 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103591 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103592 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103593 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103594 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103595 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103596 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103597 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103598 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103610 | GIR_RootConstrainSelectedInstOperands, |
| 103611 | // GIR_Coverage, 11564, |
| 103612 | GIR_EraseRootFromParent_Done, |
| 103613 | // Label 5390: @327295 |
| 103614 | GIM_Try, /*On fail goto*//*Label 5391*/ GIMT_Encode4(327430), // Rule ID 11565 // |
| 103615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103617 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103618 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103619 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103620 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103621 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 103622 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103623 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103624 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103625 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103626 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103627 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103629 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103630 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103631 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103632 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103633 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103634 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103635 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103636 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 103640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 103641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 103644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 103645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103648 | GIR_RootConstrainSelectedInstOperands, |
| 103649 | // GIR_Coverage, 11565, |
| 103650 | GIR_EraseRootFromParent_Done, |
| 103651 | // Label 5391: @327430 |
| 103652 | GIM_Try, /*On fail goto*//*Label 5392*/ GIMT_Encode4(327565), // Rule ID 11633 // |
| 103653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103655 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103656 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103657 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103658 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103659 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103660 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103661 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103662 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103663 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103664 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103665 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103666 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103667 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103668 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103669 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103670 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103671 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103672 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103673 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103674 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 103678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 103679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103686 | GIR_RootConstrainSelectedInstOperands, |
| 103687 | // GIR_Coverage, 11633, |
| 103688 | GIR_EraseRootFromParent_Done, |
| 103689 | // Label 5392: @327565 |
| 103690 | GIM_Try, /*On fail goto*//*Label 5393*/ GIMT_Encode4(327700), // Rule ID 11634 // |
| 103691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103700 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103702 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103703 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103705 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103706 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103707 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103708 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103709 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103710 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103711 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103712 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 103716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 103717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103724 | GIR_RootConstrainSelectedInstOperands, |
| 103725 | // GIR_Coverage, 11634, |
| 103726 | GIR_EraseRootFromParent_Done, |
| 103727 | // Label 5393: @327700 |
| 103728 | GIM_Try, /*On fail goto*//*Label 5394*/ GIMT_Encode4(327835), // Rule ID 11635 // |
| 103729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103735 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103736 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103739 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103740 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103741 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103743 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103744 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103745 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103746 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103747 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103748 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103749 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103750 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 103756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 103757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103762 | GIR_RootConstrainSelectedInstOperands, |
| 103763 | // GIR_Coverage, 11635, |
| 103764 | GIR_EraseRootFromParent_Done, |
| 103765 | // Label 5394: @327835 |
| 103766 | GIM_Try, /*On fail goto*//*Label 5395*/ GIMT_Encode4(327970), // Rule ID 11636 // |
| 103767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103772 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103773 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103774 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103775 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103776 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103777 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103778 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103779 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103780 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103781 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103782 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103783 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103784 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103785 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103786 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103787 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103788 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 103794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 103795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103800 | GIR_RootConstrainSelectedInstOperands, |
| 103801 | // GIR_Coverage, 11636, |
| 103802 | GIR_EraseRootFromParent_Done, |
| 103803 | // Label 5395: @327970 |
| 103804 | GIM_Try, /*On fail goto*//*Label 5396*/ GIMT_Encode4(328105), // Rule ID 11573 // |
| 103805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103807 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103808 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103809 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103810 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103811 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103812 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103813 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103814 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103815 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103816 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103817 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103818 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103819 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103820 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103821 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103822 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103823 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103824 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103825 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103826 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 103830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 103831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103838 | GIR_RootConstrainSelectedInstOperands, |
| 103839 | // GIR_Coverage, 11573, |
| 103840 | GIR_EraseRootFromParent_Done, |
| 103841 | // Label 5396: @328105 |
| 103842 | GIM_Try, /*On fail goto*//*Label 5397*/ GIMT_Encode4(328240), // Rule ID 11574 // |
| 103843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103846 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103848 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103849 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103850 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103851 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103852 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103853 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103854 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103855 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103856 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103857 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103858 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103859 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103860 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103861 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103862 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103863 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103864 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 103868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 103869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103876 | GIR_RootConstrainSelectedInstOperands, |
| 103877 | // GIR_Coverage, 11574, |
| 103878 | GIR_EraseRootFromParent_Done, |
| 103879 | // Label 5397: @328240 |
| 103880 | GIM_Try, /*On fail goto*//*Label 5398*/ GIMT_Encode4(328375), // Rule ID 11575 // |
| 103881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103884 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103885 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103886 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103887 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103888 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103889 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103890 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103891 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103892 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103893 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103894 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103895 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103896 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103897 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103898 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103899 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103900 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103901 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103902 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 103908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 103909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103914 | GIR_RootConstrainSelectedInstOperands, |
| 103915 | // GIR_Coverage, 11575, |
| 103916 | GIR_EraseRootFromParent_Done, |
| 103917 | // Label 5398: @328375 |
| 103918 | GIM_Try, /*On fail goto*//*Label 5399*/ GIMT_Encode4(328510), // Rule ID 11576 // |
| 103919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103921 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103922 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103923 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103924 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103925 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103926 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 103927 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103928 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103929 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103930 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103931 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103932 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103933 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103934 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103935 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103936 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103937 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103938 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103939 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103940 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 103944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 103945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 103946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 103947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103952 | GIR_RootConstrainSelectedInstOperands, |
| 103953 | // GIR_Coverage, 11576, |
| 103954 | GIR_EraseRootFromParent_Done, |
| 103955 | // Label 5399: @328510 |
| 103956 | GIM_Try, /*On fail goto*//*Label 5400*/ GIMT_Encode4(328645), // Rule ID 11618 // |
| 103957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 103962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 103963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 103964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 103965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 103966 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 103967 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 103968 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 103969 | // MIs[3] VOP3Mods:src0:src0_mods |
| 103970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 103971 | // MIs[3] VOP3Mods:src1:src1_mods |
| 103972 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 103973 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 103974 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 103975 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 103976 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 103977 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 103978 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 103979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 103980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 103981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 103982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 103983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 103984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 103985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 103986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 103987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 103990 | GIR_RootConstrainSelectedInstOperands, |
| 103991 | // GIR_Coverage, 11618, |
| 103992 | GIR_EraseRootFromParent_Done, |
| 103993 | // Label 5400: @328645 |
| 103994 | GIM_Try, /*On fail goto*//*Label 5401*/ GIMT_Encode4(328780), // Rule ID 11619 // |
| 103995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 103996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 103997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 103998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 103999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104000 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104001 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104003 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104004 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104005 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104006 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104007 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104009 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104010 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104011 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104012 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104013 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104014 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104015 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104016 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104028 | GIR_RootConstrainSelectedInstOperands, |
| 104029 | // GIR_Coverage, 11619, |
| 104030 | GIR_EraseRootFromParent_Done, |
| 104031 | // Label 5401: @328780 |
| 104032 | GIM_Try, /*On fail goto*//*Label 5402*/ GIMT_Encode4(328915), // Rule ID 11620 // |
| 104033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104038 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104039 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104040 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104041 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104042 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104043 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104044 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104045 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104046 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104047 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104048 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104049 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104050 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104051 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104052 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104053 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104054 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104066 | GIR_RootConstrainSelectedInstOperands, |
| 104067 | // GIR_Coverage, 11620, |
| 104068 | GIR_EraseRootFromParent_Done, |
| 104069 | // Label 5402: @328915 |
| 104070 | GIM_Try, /*On fail goto*//*Label 5403*/ GIMT_Encode4(329050), // Rule ID 11621 // |
| 104071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104073 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104074 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104075 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104076 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104077 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104078 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104079 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104080 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104081 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104082 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104083 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104085 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104086 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104087 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104088 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104089 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104090 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104091 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104092 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104104 | GIR_RootConstrainSelectedInstOperands, |
| 104105 | // GIR_Coverage, 11621, |
| 104106 | GIR_EraseRootFromParent_Done, |
| 104107 | // Label 5403: @329050 |
| 104108 | GIM_Try, /*On fail goto*//*Label 5404*/ GIMT_Encode4(329185), // Rule ID 11558 // |
| 104109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104112 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104114 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104115 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104116 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104117 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104118 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104119 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104120 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104121 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104123 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104124 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104125 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104126 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104127 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104128 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104129 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104130 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104142 | GIR_RootConstrainSelectedInstOperands, |
| 104143 | // GIR_Coverage, 11558, |
| 104144 | GIR_EraseRootFromParent_Done, |
| 104145 | // Label 5404: @329185 |
| 104146 | GIM_Try, /*On fail goto*//*Label 5405*/ GIMT_Encode4(329320), // Rule ID 11559 // |
| 104147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104149 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104150 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104151 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104152 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104153 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104154 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104155 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104156 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104157 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104158 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104159 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104160 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104161 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104162 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104163 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104164 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104165 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104166 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104167 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104168 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104180 | GIR_RootConstrainSelectedInstOperands, |
| 104181 | // GIR_Coverage, 11559, |
| 104182 | GIR_EraseRootFromParent_Done, |
| 104183 | // Label 5405: @329320 |
| 104184 | GIM_Try, /*On fail goto*//*Label 5406*/ GIMT_Encode4(329455), // Rule ID 11560 // |
| 104185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104188 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104189 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104190 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104191 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104192 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104193 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104194 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104195 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104196 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104197 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104198 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104199 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104200 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104201 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104202 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104203 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104204 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104205 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104206 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104218 | GIR_RootConstrainSelectedInstOperands, |
| 104219 | // GIR_Coverage, 11560, |
| 104220 | GIR_EraseRootFromParent_Done, |
| 104221 | // Label 5406: @329455 |
| 104222 | GIM_Try, /*On fail goto*//*Label 5407*/ GIMT_Encode4(329590), // Rule ID 11561 // |
| 104223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 104224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104225 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104226 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104227 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104228 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104229 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104230 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104231 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104232 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104233 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 104234 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104235 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 104237 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104238 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 104239 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104240 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104241 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104242 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104243 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104244 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 104246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104256 | GIR_RootConstrainSelectedInstOperands, |
| 104257 | // GIR_Coverage, 11561, |
| 104258 | GIR_EraseRootFromParent_Done, |
| 104259 | // Label 5407: @329590 |
| 104260 | GIM_Try, /*On fail goto*//*Label 5408*/ GIMT_Encode4(329702), // Rule ID 11942 // |
| 104261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 104264 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 104265 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104267 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104269 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104270 | GIM_CheckHasOneUse, /*MI*/2, |
| 104271 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 104272 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 104273 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104274 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104275 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104276 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 104282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 104283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 104284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 104285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104287 | GIR_RootConstrainSelectedInstOperands, |
| 104288 | // GIR_Coverage, 11942, |
| 104289 | GIR_EraseRootFromParent_Done, |
| 104290 | // Label 5408: @329702 |
| 104291 | GIM_Try, /*On fail goto*//*Label 5409*/ GIMT_Encode4(329814), // Rule ID 11941 // |
| 104292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 104295 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 104296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104297 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104298 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104299 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104300 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104301 | GIM_CheckHasOneUse, /*MI*/2, |
| 104302 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 104303 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 104304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104305 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104306 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104307 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 104313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 104314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 104315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 104316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104318 | GIR_RootConstrainSelectedInstOperands, |
| 104319 | // GIR_Coverage, 11941, |
| 104320 | GIR_EraseRootFromParent_Done, |
| 104321 | // Label 5409: @329814 |
| 104322 | GIM_Try, /*On fail goto*//*Label 5410*/ GIMT_Encode4(329926), // Rule ID 7411 // |
| 104323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104326 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 104327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104328 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104329 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104330 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104331 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104332 | GIM_CheckHasOneUse, /*MI*/2, |
| 104333 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 104334 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 104335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104336 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104337 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104338 | // (fmaxnum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104349 | GIR_RootConstrainSelectedInstOperands, |
| 104350 | // GIR_Coverage, 7411, |
| 104351 | GIR_EraseRootFromParent_Done, |
| 104352 | // Label 5410: @329926 |
| 104353 | GIM_Try, /*On fail goto*//*Label 5411*/ GIMT_Encode4(330038), // Rule ID 7410 // |
| 104354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 104358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104359 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 104360 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104361 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 104362 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 104363 | GIM_CheckHasOneUse, /*MI*/2, |
| 104364 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 104365 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 104366 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104367 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104368 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104369 | // (fmaxnum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104380 | GIR_RootConstrainSelectedInstOperands, |
| 104381 | // GIR_Coverage, 7410, |
| 104382 | GIR_EraseRootFromParent_Done, |
| 104383 | // Label 5411: @330038 |
| 104384 | GIM_Try, /*On fail goto*//*Label 5412*/ GIMT_Encode4(330134), // Rule ID 11926 // |
| 104385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104387 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 104388 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104389 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104390 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104391 | GIM_CheckHasOneUse, /*MI*/1, |
| 104392 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 104393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104394 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104395 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104396 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 104402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 104403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 104404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 104405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104407 | GIR_RootConstrainSelectedInstOperands, |
| 104408 | // GIR_Coverage, 11926, |
| 104409 | GIR_EraseRootFromParent_Done, |
| 104410 | // Label 5412: @330134 |
| 104411 | GIM_Try, /*On fail goto*//*Label 5413*/ GIMT_Encode4(330230), // Rule ID 11925 // |
| 104412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104414 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 104415 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104416 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104417 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104418 | GIM_CheckHasOneUse, /*MI*/1, |
| 104419 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 104420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104421 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104422 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104423 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 104429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 104430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 104431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 104432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104434 | GIR_RootConstrainSelectedInstOperands, |
| 104435 | // GIR_Coverage, 11925, |
| 104436 | GIR_EraseRootFromParent_Done, |
| 104437 | // Label 5413: @330230 |
| 104438 | GIM_Try, /*On fail goto*//*Label 5414*/ GIMT_Encode4(330326), // Rule ID 7395 // |
| 104439 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104442 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104443 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104444 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104445 | GIM_CheckHasOneUse, /*MI*/1, |
| 104446 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 104447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104448 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104449 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104450 | // (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104452 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104459 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104461 | GIR_RootConstrainSelectedInstOperands, |
| 104462 | // GIR_Coverage, 7395, |
| 104463 | GIR_EraseRootFromParent_Done, |
| 104464 | // Label 5414: @330326 |
| 104465 | GIM_Try, /*On fail goto*//*Label 5415*/ GIMT_Encode4(330422), // Rule ID 7394 // |
| 104466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 104467 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104468 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104469 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 104470 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 104471 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 104472 | GIM_CheckHasOneUse, /*MI*/1, |
| 104473 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 104474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104475 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104476 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104477 | // (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 104479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104488 | GIR_RootConstrainSelectedInstOperands, |
| 104489 | // GIR_Coverage, 7394, |
| 104490 | GIR_EraseRootFromParent_Done, |
| 104491 | // Label 5415: @330422 |
| 104492 | GIM_Try, /*On fail goto*//*Label 5416*/ GIMT_Encode4(330457), // Rule ID 105 // |
| 104493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 104494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 104495 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 104496 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 104497 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18520), |
| 104498 | // (fmaxnum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18520>> => (S_MAX_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 104499 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F16), |
| 104500 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 104501 | GIR_RootConstrainSelectedInstOperands, |
| 104502 | // GIR_Coverage, 105, |
| 104503 | GIR_Done, |
| 104504 | // Label 5416: @330457 |
| 104505 | GIM_Try, /*On fail goto*//*Label 5417*/ GIMT_Encode4(330520), // Rule ID 810 // |
| 104506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 104507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 104509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104510 | // (fmaxnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 104511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 104512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 104514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 104516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 104518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 104519 | GIR_RootConstrainSelectedInstOperands, |
| 104520 | // GIR_Coverage, 810, |
| 104521 | GIR_EraseRootFromParent_Done, |
| 104522 | // Label 5417: @330520 |
| 104523 | GIM_Try, /*On fail goto*//*Label 5418*/ GIMT_Encode4(330583), // Rule ID 814 // |
| 104524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 104525 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 104527 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104528 | // (fmaxnum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 104529 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 104530 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 104532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 104534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 104536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 104537 | GIR_RootConstrainSelectedInstOperands, |
| 104538 | // GIR_Coverage, 814, |
| 104539 | GIR_EraseRootFromParent_Done, |
| 104540 | // Label 5418: @330583 |
| 104541 | GIM_Try, /*On fail goto*//*Label 5419*/ GIMT_Encode4(330646), // Rule ID 8071 // |
| 104542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 104543 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104545 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 104546 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 104547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 104548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 104550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 104552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 104554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 104555 | GIR_RootConstrainSelectedInstOperands, |
| 104556 | // GIR_Coverage, 8071, |
| 104557 | GIR_EraseRootFromParent_Done, |
| 104558 | // Label 5419: @330646 |
| 104559 | GIM_Try, /*On fail goto*//*Label 5420*/ GIMT_Encode4(330709), // Rule ID 8073 // |
| 104560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 104561 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 104564 | // (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 104565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 104566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 104568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 104570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 104572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 104573 | GIR_RootConstrainSelectedInstOperands, |
| 104574 | // GIR_Coverage, 8073, |
| 104575 | GIR_EraseRootFromParent_Done, |
| 104576 | // Label 5420: @330709 |
| 104577 | GIM_Try, /*On fail goto*//*Label 5421*/ GIMT_Encode4(330771), // Rule ID 812 // |
| 104578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 104579 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 104580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 104581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 104582 | // (fmaxnum:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 104583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64), |
| 104584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 104586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 104588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104592 | GIR_RootConstrainSelectedInstOperands, |
| 104593 | // GIR_Coverage, 812, |
| 104594 | GIR_EraseRootFromParent_Done, |
| 104595 | // Label 5421: @330771 |
| 104596 | GIM_Reject, |
| 104597 | // Label 5279: @330772 |
| 104598 | GIM_Reject, |
| 104599 | // Label 5275: @330773 |
| 104600 | GIM_Try, /*On fail goto*//*Label 5422*/ GIMT_Encode4(348284), |
| 104601 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 104602 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 104603 | GIM_Try, /*On fail goto*//*Label 5423*/ GIMT_Encode4(330913), // Rule ID 11147 // |
| 104604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104605 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104606 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104607 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104608 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104609 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104610 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104611 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104612 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104613 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104614 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104615 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104616 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104617 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104618 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104619 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104620 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104621 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104622 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104623 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104624 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104635 | GIR_RootConstrainSelectedInstOperands, |
| 104636 | // GIR_Coverage, 11147, |
| 104637 | GIR_EraseRootFromParent_Done, |
| 104638 | // Label 5423: @330913 |
| 104639 | GIM_Try, /*On fail goto*//*Label 5424*/ GIMT_Encode4(331042), // Rule ID 11148 // |
| 104640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104641 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104642 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104643 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104644 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104645 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104646 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104647 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104648 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104649 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104650 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104651 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104652 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104653 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104654 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104655 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104656 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104657 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104658 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104659 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104660 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104671 | GIR_RootConstrainSelectedInstOperands, |
| 104672 | // GIR_Coverage, 11148, |
| 104673 | GIR_EraseRootFromParent_Done, |
| 104674 | // Label 5424: @331042 |
| 104675 | GIM_Try, /*On fail goto*//*Label 5425*/ GIMT_Encode4(331171), // Rule ID 11151 // |
| 104676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104680 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104681 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104682 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104683 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104684 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104685 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104686 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104687 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104688 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104689 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104690 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104691 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104692 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104693 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104694 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104695 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104696 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104705 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104707 | GIR_RootConstrainSelectedInstOperands, |
| 104708 | // GIR_Coverage, 11151, |
| 104709 | GIR_EraseRootFromParent_Done, |
| 104710 | // Label 5425: @331171 |
| 104711 | GIM_Try, /*On fail goto*//*Label 5426*/ GIMT_Encode4(331300), // Rule ID 11152 // |
| 104712 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104713 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104714 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104715 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104716 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104717 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104718 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104719 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104720 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104721 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104722 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104723 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104724 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104725 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104726 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104727 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104728 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104729 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104730 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104731 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104732 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104743 | GIR_RootConstrainSelectedInstOperands, |
| 104744 | // GIR_Coverage, 11152, |
| 104745 | GIR_EraseRootFromParent_Done, |
| 104746 | // Label 5426: @331300 |
| 104747 | GIM_Try, /*On fail goto*//*Label 5427*/ GIMT_Encode4(331429), // Rule ID 11132 // |
| 104748 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104749 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104750 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104751 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104752 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104753 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104754 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104755 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104756 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104757 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104758 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104759 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104760 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104761 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104762 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104763 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104764 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104765 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104766 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104767 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104768 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104779 | GIR_RootConstrainSelectedInstOperands, |
| 104780 | // GIR_Coverage, 11132, |
| 104781 | GIR_EraseRootFromParent_Done, |
| 104782 | // Label 5427: @331429 |
| 104783 | GIM_Try, /*On fail goto*//*Label 5428*/ GIMT_Encode4(331558), // Rule ID 11133 // |
| 104784 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104785 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104786 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104787 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104788 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104789 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104790 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104791 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104792 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104793 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104794 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104795 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104796 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104797 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104798 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104799 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104800 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104801 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104802 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104803 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104804 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104805 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104806 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104813 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104815 | GIR_RootConstrainSelectedInstOperands, |
| 104816 | // GIR_Coverage, 11133, |
| 104817 | GIR_EraseRootFromParent_Done, |
| 104818 | // Label 5428: @331558 |
| 104819 | GIM_Try, /*On fail goto*//*Label 5429*/ GIMT_Encode4(331687), // Rule ID 11136 // |
| 104820 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104821 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104822 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104823 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104824 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104825 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104826 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104827 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104828 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104829 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104830 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104831 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104832 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104833 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104834 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104835 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104836 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104837 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104838 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104839 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104840 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104842 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104851 | GIR_RootConstrainSelectedInstOperands, |
| 104852 | // GIR_Coverage, 11136, |
| 104853 | GIR_EraseRootFromParent_Done, |
| 104854 | // Label 5429: @331687 |
| 104855 | GIM_Try, /*On fail goto*//*Label 5430*/ GIMT_Encode4(331816), // Rule ID 11137 // |
| 104856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104858 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104861 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104862 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104863 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104864 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104865 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 104866 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 104867 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104869 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104870 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104871 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104872 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104873 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104874 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104875 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104876 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104887 | GIR_RootConstrainSelectedInstOperands, |
| 104888 | // GIR_Coverage, 11137, |
| 104889 | GIR_EraseRootFromParent_Done, |
| 104890 | // Label 5430: @331816 |
| 104891 | GIM_Try, /*On fail goto*//*Label 5431*/ GIMT_Encode4(331945), // Rule ID 7329 // |
| 104892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104894 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104896 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104897 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104898 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104899 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104900 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104901 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 104902 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104903 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104904 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104905 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104908 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104909 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104910 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104911 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104912 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104923 | GIR_RootConstrainSelectedInstOperands, |
| 104924 | // GIR_Coverage, 7329, |
| 104925 | GIR_EraseRootFromParent_Done, |
| 104926 | // Label 5431: @331945 |
| 104927 | GIM_Try, /*On fail goto*//*Label 5432*/ GIMT_Encode4(332074), // Rule ID 11146 // |
| 104928 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104929 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104930 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104931 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104932 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104933 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104934 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104935 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104936 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104937 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 104938 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104939 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104940 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104941 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104942 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104943 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104944 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104945 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104946 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104947 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104948 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 104952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 104953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 104954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 104955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104957 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104959 | GIR_RootConstrainSelectedInstOperands, |
| 104960 | // GIR_Coverage, 11146, |
| 104961 | GIR_EraseRootFromParent_Done, |
| 104962 | // Label 5432: @332074 |
| 104963 | GIM_Try, /*On fail goto*//*Label 5433*/ GIMT_Encode4(332203), // Rule ID 11149 // |
| 104964 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 104965 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 104966 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104967 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 104968 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 104969 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 104970 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 104971 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 104972 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 104973 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 104974 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 104975 | // MIs[3] VOP3Mods:src0:src0_mods |
| 104976 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 104977 | // MIs[3] VOP3Mods:src1:src1_mods |
| 104978 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 104979 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 104980 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 104981 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 104982 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 104983 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 104984 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 104985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 104986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 104987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 104988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 104989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 104990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 104991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 104992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 104993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 104995 | GIR_RootConstrainSelectedInstOperands, |
| 104996 | // GIR_Coverage, 11149, |
| 104997 | GIR_EraseRootFromParent_Done, |
| 104998 | // Label 5433: @332203 |
| 104999 | GIM_Try, /*On fail goto*//*Label 5434*/ GIMT_Encode4(332332), // Rule ID 11150 // |
| 105000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105001 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105002 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105003 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105004 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105005 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105006 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105007 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105008 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105009 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105010 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105011 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105012 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105013 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105014 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105015 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105016 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105017 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105018 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105019 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105020 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105029 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105031 | GIR_RootConstrainSelectedInstOperands, |
| 105032 | // GIR_Coverage, 11150, |
| 105033 | GIR_EraseRootFromParent_Done, |
| 105034 | // Label 5434: @332332 |
| 105035 | GIM_Try, /*On fail goto*//*Label 5435*/ GIMT_Encode4(332461), // Rule ID 7328 // |
| 105036 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105037 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105038 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105039 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105040 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105041 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105042 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105043 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105044 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105045 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105046 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105047 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105048 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105049 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105050 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105051 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105052 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105053 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105054 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105055 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105056 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105067 | GIR_RootConstrainSelectedInstOperands, |
| 105068 | // GIR_Coverage, 7328, |
| 105069 | GIR_EraseRootFromParent_Done, |
| 105070 | // Label 5435: @332461 |
| 105071 | GIM_Try, /*On fail goto*//*Label 5436*/ GIMT_Encode4(332590), // Rule ID 11131 // |
| 105072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105073 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105074 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105075 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105076 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105077 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105078 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105079 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105080 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105081 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105082 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105083 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105085 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105086 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105087 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105088 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105089 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105090 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105091 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105092 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105103 | GIR_RootConstrainSelectedInstOperands, |
| 105104 | // GIR_Coverage, 11131, |
| 105105 | GIR_EraseRootFromParent_Done, |
| 105106 | // Label 5436: @332590 |
| 105107 | GIM_Try, /*On fail goto*//*Label 5437*/ GIMT_Encode4(332719), // Rule ID 11134 // |
| 105108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105109 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105110 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105111 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105112 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105113 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105114 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105115 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105116 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105117 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105118 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105119 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105120 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105121 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105123 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105124 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105125 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105126 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105127 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105128 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105139 | GIR_RootConstrainSelectedInstOperands, |
| 105140 | // GIR_Coverage, 11134, |
| 105141 | GIR_EraseRootFromParent_Done, |
| 105142 | // Label 5437: @332719 |
| 105143 | GIM_Try, /*On fail goto*//*Label 5438*/ GIMT_Encode4(332848), // Rule ID 11135 // |
| 105144 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105145 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105146 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105147 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105148 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105149 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105150 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105151 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105152 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105153 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105154 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105155 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105156 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105157 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105158 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105159 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105160 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105161 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105162 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105163 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105164 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105175 | GIR_RootConstrainSelectedInstOperands, |
| 105176 | // GIR_Coverage, 11135, |
| 105177 | GIR_EraseRootFromParent_Done, |
| 105178 | // Label 5438: @332848 |
| 105179 | GIM_Try, /*On fail goto*//*Label 5439*/ GIMT_Encode4(332977), // Rule ID 11117 // |
| 105180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105181 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105182 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105184 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105185 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105186 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105187 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105188 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105189 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105190 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105191 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105192 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105193 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105194 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105195 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105196 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105197 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105198 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105199 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105200 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105211 | GIR_RootConstrainSelectedInstOperands, |
| 105212 | // GIR_Coverage, 11117, |
| 105213 | GIR_EraseRootFromParent_Done, |
| 105214 | // Label 5439: @332977 |
| 105215 | GIM_Try, /*On fail goto*//*Label 5440*/ GIMT_Encode4(333106), // Rule ID 11118 // |
| 105216 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105217 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105218 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105219 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105220 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105221 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105222 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105223 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105224 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105225 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105226 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105227 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105228 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105229 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105230 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105231 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105232 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105233 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105234 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105235 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105236 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105237 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105238 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105247 | GIR_RootConstrainSelectedInstOperands, |
| 105248 | // GIR_Coverage, 11118, |
| 105249 | GIR_EraseRootFromParent_Done, |
| 105250 | // Label 5440: @333106 |
| 105251 | GIM_Try, /*On fail goto*//*Label 5441*/ GIMT_Encode4(333235), // Rule ID 11121 // |
| 105252 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105253 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105254 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105255 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105256 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105257 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105258 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105259 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105260 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105261 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105262 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105263 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105264 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105265 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105266 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105267 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105268 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105269 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105270 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105271 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105272 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105281 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105283 | GIR_RootConstrainSelectedInstOperands, |
| 105284 | // GIR_Coverage, 11121, |
| 105285 | GIR_EraseRootFromParent_Done, |
| 105286 | // Label 5441: @333235 |
| 105287 | GIM_Try, /*On fail goto*//*Label 5442*/ GIMT_Encode4(333364), // Rule ID 11122 // |
| 105288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105289 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105290 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105291 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105292 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105293 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105294 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105295 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105296 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105297 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105298 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105299 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105300 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105301 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105302 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105303 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105304 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105305 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105306 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105307 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105308 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105319 | GIR_RootConstrainSelectedInstOperands, |
| 105320 | // GIR_Coverage, 11122, |
| 105321 | GIR_EraseRootFromParent_Done, |
| 105322 | // Label 5442: @333364 |
| 105323 | GIM_Try, /*On fail goto*//*Label 5443*/ GIMT_Encode4(333493), // Rule ID 11102 // |
| 105324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105326 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105328 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105329 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105330 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105331 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105332 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105333 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105334 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105335 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105336 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105337 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105338 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105339 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105340 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105341 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105342 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105343 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105344 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105355 | GIR_RootConstrainSelectedInstOperands, |
| 105356 | // GIR_Coverage, 11102, |
| 105357 | GIR_EraseRootFromParent_Done, |
| 105358 | // Label 5443: @333493 |
| 105359 | GIM_Try, /*On fail goto*//*Label 5444*/ GIMT_Encode4(333622), // Rule ID 11103 // |
| 105360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105361 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105362 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105363 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105364 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105365 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105366 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105367 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105368 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105369 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105370 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105371 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105372 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105373 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105374 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105375 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105376 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105377 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105378 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105379 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105380 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105381 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105382 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105389 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105391 | GIR_RootConstrainSelectedInstOperands, |
| 105392 | // GIR_Coverage, 11103, |
| 105393 | GIR_EraseRootFromParent_Done, |
| 105394 | // Label 5444: @333622 |
| 105395 | GIM_Try, /*On fail goto*//*Label 5445*/ GIMT_Encode4(333751), // Rule ID 11106 // |
| 105396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105397 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105398 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105399 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105400 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105401 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105402 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105403 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105404 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105405 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105406 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105407 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105408 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105409 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105410 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105411 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105412 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105413 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105414 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105415 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105416 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105427 | GIR_RootConstrainSelectedInstOperands, |
| 105428 | // GIR_Coverage, 11106, |
| 105429 | GIR_EraseRootFromParent_Done, |
| 105430 | // Label 5445: @333751 |
| 105431 | GIM_Try, /*On fail goto*//*Label 5446*/ GIMT_Encode4(333880), // Rule ID 11107 // |
| 105432 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105433 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105434 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105435 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105436 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105437 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105438 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105439 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105440 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105441 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 105442 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105443 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105444 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105445 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105446 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105447 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105448 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105449 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105450 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105451 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105452 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105463 | GIR_RootConstrainSelectedInstOperands, |
| 105464 | // GIR_Coverage, 11107, |
| 105465 | GIR_EraseRootFromParent_Done, |
| 105466 | // Label 5446: @333880 |
| 105467 | GIM_Try, /*On fail goto*//*Label 5447*/ GIMT_Encode4(334009), // Rule ID 7327 // |
| 105468 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105469 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105470 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105471 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105472 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105473 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105474 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105475 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105476 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105477 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105478 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105479 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105480 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105481 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105482 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105483 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105484 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105485 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105486 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105487 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105488 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105490 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105499 | GIR_RootConstrainSelectedInstOperands, |
| 105500 | // GIR_Coverage, 7327, |
| 105501 | GIR_EraseRootFromParent_Done, |
| 105502 | // Label 5447: @334009 |
| 105503 | GIM_Try, /*On fail goto*//*Label 5448*/ GIMT_Encode4(334138), // Rule ID 11116 // |
| 105504 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105505 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105506 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105507 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105508 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105509 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105510 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105511 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105512 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105513 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105514 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105515 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105516 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105517 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105518 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105519 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105520 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105521 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105522 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105523 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105524 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105535 | GIR_RootConstrainSelectedInstOperands, |
| 105536 | // GIR_Coverage, 11116, |
| 105537 | GIR_EraseRootFromParent_Done, |
| 105538 | // Label 5448: @334138 |
| 105539 | GIM_Try, /*On fail goto*//*Label 5449*/ GIMT_Encode4(334267), // Rule ID 11119 // |
| 105540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105542 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105543 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105544 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105545 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105546 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105547 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105548 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105549 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105550 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105551 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105553 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105554 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105555 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105556 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105557 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105558 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105559 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105560 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105571 | GIR_RootConstrainSelectedInstOperands, |
| 105572 | // GIR_Coverage, 11119, |
| 105573 | GIR_EraseRootFromParent_Done, |
| 105574 | // Label 5449: @334267 |
| 105575 | GIM_Try, /*On fail goto*//*Label 5450*/ GIMT_Encode4(334396), // Rule ID 11120 // |
| 105576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105580 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105584 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105585 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105586 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105587 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105588 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105589 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105591 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105592 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105593 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105594 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105595 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105596 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105607 | GIR_RootConstrainSelectedInstOperands, |
| 105608 | // GIR_Coverage, 11120, |
| 105609 | GIR_EraseRootFromParent_Done, |
| 105610 | // Label 5450: @334396 |
| 105611 | GIM_Try, /*On fail goto*//*Label 5451*/ GIMT_Encode4(334525), // Rule ID 7326 // |
| 105612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105613 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105614 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105615 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105616 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105617 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105618 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105619 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105620 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105621 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105622 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105623 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105624 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105625 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105626 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105627 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105628 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105629 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105630 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105631 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105632 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105643 | GIR_RootConstrainSelectedInstOperands, |
| 105644 | // GIR_Coverage, 7326, |
| 105645 | GIR_EraseRootFromParent_Done, |
| 105646 | // Label 5451: @334525 |
| 105647 | GIM_Try, /*On fail goto*//*Label 5452*/ GIMT_Encode4(334654), // Rule ID 11101 // |
| 105648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105649 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105650 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105651 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105652 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105653 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105654 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105655 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105656 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105657 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105658 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105659 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105660 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105661 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105662 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105663 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105664 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105665 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105666 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105667 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105668 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 105672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 105673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105679 | GIR_RootConstrainSelectedInstOperands, |
| 105680 | // GIR_Coverage, 11101, |
| 105681 | GIR_EraseRootFromParent_Done, |
| 105682 | // Label 5452: @334654 |
| 105683 | GIM_Try, /*On fail goto*//*Label 5453*/ GIMT_Encode4(334783), // Rule ID 11104 // |
| 105684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105685 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105686 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105687 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105688 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105689 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105690 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105691 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105692 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105693 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105694 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105695 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105696 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105697 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105698 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105699 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105700 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105701 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105702 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105703 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105704 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105715 | GIR_RootConstrainSelectedInstOperands, |
| 105716 | // GIR_Coverage, 11104, |
| 105717 | GIR_EraseRootFromParent_Done, |
| 105718 | // Label 5453: @334783 |
| 105719 | GIM_Try, /*On fail goto*//*Label 5454*/ GIMT_Encode4(334912), // Rule ID 11105 // |
| 105720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105721 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105722 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105723 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105724 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105725 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 105726 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105727 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105728 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105729 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 105730 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 105731 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105732 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 105733 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105734 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 105735 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105736 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105737 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105738 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105739 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105740 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105741 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105742 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 105746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 105747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 105748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 105749 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105751 | GIR_RootConstrainSelectedInstOperands, |
| 105752 | // GIR_Coverage, 11105, |
| 105753 | GIR_EraseRootFromParent_Done, |
| 105754 | // Label 5454: @334912 |
| 105755 | GIM_Try, /*On fail goto*//*Label 5455*/ GIMT_Encode4(335041), // Rule ID 11157 // |
| 105756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105757 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105758 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105759 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105760 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105761 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105762 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105763 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105764 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105765 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105766 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105767 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105768 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105769 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105770 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105771 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105772 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105773 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105774 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105775 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105776 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 105782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 105783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105787 | GIR_RootConstrainSelectedInstOperands, |
| 105788 | // GIR_Coverage, 11157, |
| 105789 | GIR_EraseRootFromParent_Done, |
| 105790 | // Label 5455: @335041 |
| 105791 | GIM_Try, /*On fail goto*//*Label 5456*/ GIMT_Encode4(335170), // Rule ID 11158 // |
| 105792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105797 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105798 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105799 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105800 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105801 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105802 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105803 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105804 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105805 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105806 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105807 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105808 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105809 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105810 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105811 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105812 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 105818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 105819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105823 | GIR_RootConstrainSelectedInstOperands, |
| 105824 | // GIR_Coverage, 11158, |
| 105825 | GIR_EraseRootFromParent_Done, |
| 105826 | // Label 5456: @335170 |
| 105827 | GIM_Try, /*On fail goto*//*Label 5457*/ GIMT_Encode4(335299), // Rule ID 11159 // |
| 105828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105829 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105830 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105831 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105832 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105833 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105834 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105835 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105836 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105837 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105838 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105839 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105840 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105841 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105842 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105843 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105844 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105845 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105846 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105847 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105848 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 105852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 105853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105857 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105859 | GIR_RootConstrainSelectedInstOperands, |
| 105860 | // GIR_Coverage, 11159, |
| 105861 | GIR_EraseRootFromParent_Done, |
| 105862 | // Label 5457: @335299 |
| 105863 | GIM_Try, /*On fail goto*//*Label 5458*/ GIMT_Encode4(335428), // Rule ID 11160 // |
| 105864 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105865 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105866 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105867 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105868 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105869 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105870 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105871 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105872 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105873 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105874 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105875 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105876 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105877 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105878 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105879 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105880 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105881 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105882 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105883 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105884 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 105888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 105889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105895 | GIR_RootConstrainSelectedInstOperands, |
| 105896 | // GIR_Coverage, 11160, |
| 105897 | GIR_EraseRootFromParent_Done, |
| 105898 | // Label 5458: @335428 |
| 105899 | GIM_Try, /*On fail goto*//*Label 5459*/ GIMT_Encode4(335557), // Rule ID 11097 // |
| 105900 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105901 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105902 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105903 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105904 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105905 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105906 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105907 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105908 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105909 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105910 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105911 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105912 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105913 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105914 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105915 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105916 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105917 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105918 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105919 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105920 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 105926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 105927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105931 | GIR_RootConstrainSelectedInstOperands, |
| 105932 | // GIR_Coverage, 11097, |
| 105933 | GIR_EraseRootFromParent_Done, |
| 105934 | // Label 5459: @335557 |
| 105935 | GIM_Try, /*On fail goto*//*Label 5460*/ GIMT_Encode4(335686), // Rule ID 11098 // |
| 105936 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105937 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105938 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105939 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105940 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105941 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105942 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105943 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105944 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105945 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105946 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105947 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105948 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105949 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105950 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105951 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105952 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105953 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105954 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105955 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105956 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 105960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 105961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 105962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 105963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 105964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 105965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 105967 | GIR_RootConstrainSelectedInstOperands, |
| 105968 | // GIR_Coverage, 11098, |
| 105969 | GIR_EraseRootFromParent_Done, |
| 105970 | // Label 5460: @335686 |
| 105971 | GIM_Try, /*On fail goto*//*Label 5461*/ GIMT_Encode4(335815), // Rule ID 11099 // |
| 105972 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 105973 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 105974 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 105975 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 105976 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 105977 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 105978 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 105979 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 105980 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 105981 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 105982 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 105983 | // MIs[3] VOP3Mods:src0:src0_mods |
| 105984 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 105985 | // MIs[3] VOP3Mods:src1:src1_mods |
| 105986 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 105987 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 105988 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 105989 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 105990 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 105991 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 105992 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 105993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 105994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 105995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 105996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 105997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 105998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 105999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106003 | GIR_RootConstrainSelectedInstOperands, |
| 106004 | // GIR_Coverage, 11099, |
| 106005 | GIR_EraseRootFromParent_Done, |
| 106006 | // Label 5461: @335815 |
| 106007 | GIM_Try, /*On fail goto*//*Label 5462*/ GIMT_Encode4(335944), // Rule ID 11100 // |
| 106008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106009 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106010 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106011 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106012 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106013 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106014 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106015 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106016 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106017 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106018 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106019 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106020 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106021 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106022 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106023 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106024 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106025 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106026 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106027 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106028 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 106032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 106033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106039 | GIR_RootConstrainSelectedInstOperands, |
| 106040 | // GIR_Coverage, 11100, |
| 106041 | GIR_EraseRootFromParent_Done, |
| 106042 | // Label 5462: @335944 |
| 106043 | GIM_Try, /*On fail goto*//*Label 5463*/ GIMT_Encode4(336073), // Rule ID 11142 // |
| 106044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106045 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106046 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106047 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106048 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106049 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106050 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106051 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106052 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106053 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106054 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106055 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106056 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106057 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106059 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106060 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106061 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106062 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106063 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106064 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 106070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 106071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106075 | GIR_RootConstrainSelectedInstOperands, |
| 106076 | // GIR_Coverage, 11142, |
| 106077 | GIR_EraseRootFromParent_Done, |
| 106078 | // Label 5463: @336073 |
| 106079 | GIM_Try, /*On fail goto*//*Label 5464*/ GIMT_Encode4(336202), // Rule ID 11143 // |
| 106080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106081 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106082 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106083 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106084 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106085 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106086 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106087 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106088 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106089 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106090 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106091 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106092 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106093 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106094 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106095 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106096 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106097 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106098 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106099 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106100 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 106106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 106107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106111 | GIR_RootConstrainSelectedInstOperands, |
| 106112 | // GIR_Coverage, 11143, |
| 106113 | GIR_EraseRootFromParent_Done, |
| 106114 | // Label 5464: @336202 |
| 106115 | GIM_Try, /*On fail goto*//*Label 5465*/ GIMT_Encode4(336331), // Rule ID 11144 // |
| 106116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106117 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106118 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106119 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106120 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106121 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106122 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106123 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106124 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106125 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106126 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106127 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106128 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106129 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106130 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106131 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106132 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106133 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106134 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106135 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106136 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 106140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 106141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106147 | GIR_RootConstrainSelectedInstOperands, |
| 106148 | // GIR_Coverage, 11144, |
| 106149 | GIR_EraseRootFromParent_Done, |
| 106150 | // Label 5465: @336331 |
| 106151 | GIM_Try, /*On fail goto*//*Label 5466*/ GIMT_Encode4(336460), // Rule ID 11145 // |
| 106152 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106153 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106154 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106155 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106156 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106157 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106158 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106159 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106160 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106161 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106162 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106163 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106164 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106165 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106166 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106167 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106168 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106169 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106170 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106171 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106172 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 106176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 106177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106183 | GIR_RootConstrainSelectedInstOperands, |
| 106184 | // GIR_Coverage, 11145, |
| 106185 | GIR_EraseRootFromParent_Done, |
| 106186 | // Label 5466: @336460 |
| 106187 | GIM_Try, /*On fail goto*//*Label 5467*/ GIMT_Encode4(336589), // Rule ID 11082 // |
| 106188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106189 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106190 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106191 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106192 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106193 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106194 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106195 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106196 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106197 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106198 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106199 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106200 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106201 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106202 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106203 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106204 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106205 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106206 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106207 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106208 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106210 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 106214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 106215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106219 | GIR_RootConstrainSelectedInstOperands, |
| 106220 | // GIR_Coverage, 11082, |
| 106221 | GIR_EraseRootFromParent_Done, |
| 106222 | // Label 5467: @336589 |
| 106223 | GIM_Try, /*On fail goto*//*Label 5468*/ GIMT_Encode4(336718), // Rule ID 11083 // |
| 106224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106225 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106226 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106227 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106228 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106229 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106230 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106231 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106232 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106233 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106234 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106235 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106237 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106238 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106239 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106240 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106241 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106242 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106243 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106244 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 106250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 106251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106255 | GIR_RootConstrainSelectedInstOperands, |
| 106256 | // GIR_Coverage, 11083, |
| 106257 | GIR_EraseRootFromParent_Done, |
| 106258 | // Label 5468: @336718 |
| 106259 | GIM_Try, /*On fail goto*//*Label 5469*/ GIMT_Encode4(336847), // Rule ID 11084 // |
| 106260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106264 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106266 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106267 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106268 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106269 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106270 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106271 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106272 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106273 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106274 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106275 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106276 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106277 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106278 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106279 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106280 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 106284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 106285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106291 | GIR_RootConstrainSelectedInstOperands, |
| 106292 | // GIR_Coverage, 11084, |
| 106293 | GIR_EraseRootFromParent_Done, |
| 106294 | // Label 5469: @336847 |
| 106295 | GIM_Try, /*On fail goto*//*Label 5470*/ GIMT_Encode4(336976), // Rule ID 11085 // |
| 106296 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106297 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106298 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106299 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106300 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106301 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 106302 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106303 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106304 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106305 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106306 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106307 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106308 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106309 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106310 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106311 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106312 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106313 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106314 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106315 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106316 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 106320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 106321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 106324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 106325 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106327 | GIR_RootConstrainSelectedInstOperands, |
| 106328 | // GIR_Coverage, 11085, |
| 106329 | GIR_EraseRootFromParent_Done, |
| 106330 | // Label 5470: @336976 |
| 106331 | GIM_Try, /*On fail goto*//*Label 5471*/ GIMT_Encode4(337105), // Rule ID 11153 // |
| 106332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106333 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106334 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106335 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106336 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106337 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106338 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106339 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106340 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106341 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106342 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106343 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106344 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106345 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106346 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106347 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106348 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106349 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106350 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106351 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106352 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106363 | GIR_RootConstrainSelectedInstOperands, |
| 106364 | // GIR_Coverage, 11153, |
| 106365 | GIR_EraseRootFromParent_Done, |
| 106366 | // Label 5471: @337105 |
| 106367 | GIM_Try, /*On fail goto*//*Label 5472*/ GIMT_Encode4(337234), // Rule ID 11154 // |
| 106368 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106369 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106370 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106371 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106372 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106373 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106374 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106375 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106376 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106377 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106378 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106379 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106380 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106381 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106382 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106383 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106384 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106385 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106386 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106387 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106388 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106399 | GIR_RootConstrainSelectedInstOperands, |
| 106400 | // GIR_Coverage, 11154, |
| 106401 | GIR_EraseRootFromParent_Done, |
| 106402 | // Label 5472: @337234 |
| 106403 | GIM_Try, /*On fail goto*//*Label 5473*/ GIMT_Encode4(337363), // Rule ID 11155 // |
| 106404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106405 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106406 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106407 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106408 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106409 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106410 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106411 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106412 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106413 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106414 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106415 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106416 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106417 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106418 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106419 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106420 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106421 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106422 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106423 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106424 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106426 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106435 | GIR_RootConstrainSelectedInstOperands, |
| 106436 | // GIR_Coverage, 11155, |
| 106437 | GIR_EraseRootFromParent_Done, |
| 106438 | // Label 5473: @337363 |
| 106439 | GIM_Try, /*On fail goto*//*Label 5474*/ GIMT_Encode4(337492), // Rule ID 11156 // |
| 106440 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106441 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106442 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106443 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106444 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106445 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106446 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106447 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106448 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106449 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106450 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106451 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106452 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106453 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106454 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106455 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106456 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106457 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106458 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106459 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106460 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106471 | GIR_RootConstrainSelectedInstOperands, |
| 106472 | // GIR_Coverage, 11156, |
| 106473 | GIR_EraseRootFromParent_Done, |
| 106474 | // Label 5474: @337492 |
| 106475 | GIM_Try, /*On fail goto*//*Label 5475*/ GIMT_Encode4(337621), // Rule ID 11093 // |
| 106476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106477 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106478 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106479 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106480 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106481 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106482 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106483 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106484 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106485 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106486 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106487 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106488 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106489 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106490 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106491 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106492 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106493 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106494 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106495 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106496 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106507 | GIR_RootConstrainSelectedInstOperands, |
| 106508 | // GIR_Coverage, 11093, |
| 106509 | GIR_EraseRootFromParent_Done, |
| 106510 | // Label 5475: @337621 |
| 106511 | GIM_Try, /*On fail goto*//*Label 5476*/ GIMT_Encode4(337750), // Rule ID 11094 // |
| 106512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106513 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106514 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106515 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106516 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106517 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106518 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106519 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106520 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106521 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106522 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106523 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106524 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106525 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106526 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106527 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106528 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106529 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106530 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106531 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106532 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106534 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106541 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106543 | GIR_RootConstrainSelectedInstOperands, |
| 106544 | // GIR_Coverage, 11094, |
| 106545 | GIR_EraseRootFromParent_Done, |
| 106546 | // Label 5476: @337750 |
| 106547 | GIM_Try, /*On fail goto*//*Label 5477*/ GIMT_Encode4(337879), // Rule ID 11095 // |
| 106548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106549 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106550 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106551 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106552 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106553 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106554 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106555 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106556 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106557 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106558 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106559 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106560 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106561 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106562 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106563 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106564 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106565 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106566 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106567 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106568 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106577 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106579 | GIR_RootConstrainSelectedInstOperands, |
| 106580 | // GIR_Coverage, 11095, |
| 106581 | GIR_EraseRootFromParent_Done, |
| 106582 | // Label 5477: @337879 |
| 106583 | GIM_Try, /*On fail goto*//*Label 5478*/ GIMT_Encode4(338008), // Rule ID 11096 // |
| 106584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106585 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106586 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106587 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106588 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106589 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106590 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106591 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106592 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106593 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106594 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106595 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106596 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106597 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106598 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106599 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106600 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106601 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106602 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106603 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106604 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106605 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106606 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106615 | GIR_RootConstrainSelectedInstOperands, |
| 106616 | // GIR_Coverage, 11096, |
| 106617 | GIR_EraseRootFromParent_Done, |
| 106618 | // Label 5478: @338008 |
| 106619 | GIM_Try, /*On fail goto*//*Label 5479*/ GIMT_Encode4(338137), // Rule ID 11138 // |
| 106620 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106621 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106622 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106623 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106624 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106625 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106626 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106627 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106628 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106629 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106630 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106631 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106632 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106633 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106634 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106635 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106636 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106637 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106638 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106639 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106640 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106641 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106642 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106649 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106651 | GIR_RootConstrainSelectedInstOperands, |
| 106652 | // GIR_Coverage, 11138, |
| 106653 | GIR_EraseRootFromParent_Done, |
| 106654 | // Label 5479: @338137 |
| 106655 | GIM_Try, /*On fail goto*//*Label 5480*/ GIMT_Encode4(338266), // Rule ID 11139 // |
| 106656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106657 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106658 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106659 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106660 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106661 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106662 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106663 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106664 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106665 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106666 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106667 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106668 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106669 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106670 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106671 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106672 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106673 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106674 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106675 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106676 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106687 | GIR_RootConstrainSelectedInstOperands, |
| 106688 | // GIR_Coverage, 11139, |
| 106689 | GIR_EraseRootFromParent_Done, |
| 106690 | // Label 5480: @338266 |
| 106691 | GIM_Try, /*On fail goto*//*Label 5481*/ GIMT_Encode4(338395), // Rule ID 11140 // |
| 106692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106700 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106702 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106703 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106705 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106706 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106707 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106708 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106709 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106710 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106711 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106712 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106723 | GIR_RootConstrainSelectedInstOperands, |
| 106724 | // GIR_Coverage, 11140, |
| 106725 | GIR_EraseRootFromParent_Done, |
| 106726 | // Label 5481: @338395 |
| 106727 | GIM_Try, /*On fail goto*//*Label 5482*/ GIMT_Encode4(338524), // Rule ID 11141 // |
| 106728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106730 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106731 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106732 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106733 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106734 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106735 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106736 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106737 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106738 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106739 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106740 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106741 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106743 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106744 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106745 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106746 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106747 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106748 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106759 | GIR_RootConstrainSelectedInstOperands, |
| 106760 | // GIR_Coverage, 11141, |
| 106761 | GIR_EraseRootFromParent_Done, |
| 106762 | // Label 5482: @338524 |
| 106763 | GIM_Try, /*On fail goto*//*Label 5483*/ GIMT_Encode4(338653), // Rule ID 11078 // |
| 106764 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106765 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106766 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106767 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106768 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106769 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106770 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106771 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106772 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106773 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106774 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106775 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106776 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106777 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106778 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106779 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106780 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106781 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106782 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106783 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106784 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106795 | GIR_RootConstrainSelectedInstOperands, |
| 106796 | // GIR_Coverage, 11078, |
| 106797 | GIR_EraseRootFromParent_Done, |
| 106798 | // Label 5483: @338653 |
| 106799 | GIM_Try, /*On fail goto*//*Label 5484*/ GIMT_Encode4(338782), // Rule ID 11079 // |
| 106800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106802 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106803 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106804 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106805 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106806 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106807 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106808 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106809 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106810 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106811 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106812 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106813 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106814 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106815 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106816 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106817 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106818 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106819 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106820 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106831 | GIR_RootConstrainSelectedInstOperands, |
| 106832 | // GIR_Coverage, 11079, |
| 106833 | GIR_EraseRootFromParent_Done, |
| 106834 | // Label 5484: @338782 |
| 106835 | GIM_Try, /*On fail goto*//*Label 5485*/ GIMT_Encode4(338911), // Rule ID 11080 // |
| 106836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106837 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106838 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106839 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106840 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106841 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106842 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106843 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106844 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106845 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106846 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106847 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106848 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106849 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106850 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106851 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106852 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106853 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106854 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106855 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106856 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106867 | GIR_RootConstrainSelectedInstOperands, |
| 106868 | // GIR_Coverage, 11080, |
| 106869 | GIR_EraseRootFromParent_Done, |
| 106870 | // Label 5485: @338911 |
| 106871 | GIM_Try, /*On fail goto*//*Label 5486*/ GIMT_Encode4(339040), // Rule ID 11081 // |
| 106872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106873 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106874 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106875 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106876 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106877 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 106878 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 106879 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106880 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106881 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 106882 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106883 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106884 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 106885 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106886 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 106887 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106888 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106889 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106890 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106891 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106892 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 106896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 106897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 106898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 106899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106901 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106903 | GIR_RootConstrainSelectedInstOperands, |
| 106904 | // GIR_Coverage, 11081, |
| 106905 | GIR_EraseRootFromParent_Done, |
| 106906 | // Label 5486: @339040 |
| 106907 | GIM_Try, /*On fail goto*//*Label 5487*/ GIMT_Encode4(339169), // Rule ID 11087 // |
| 106908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106909 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106910 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106911 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106912 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106913 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 106914 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106915 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106916 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106917 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 106918 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106919 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106920 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 106921 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106922 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 106923 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106924 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106925 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106926 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106927 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106928 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106939 | GIR_RootConstrainSelectedInstOperands, |
| 106940 | // GIR_Coverage, 11087, |
| 106941 | GIR_EraseRootFromParent_Done, |
| 106942 | // Label 5487: @339169 |
| 106943 | GIM_Try, /*On fail goto*//*Label 5488*/ GIMT_Encode4(339298), // Rule ID 11088 // |
| 106944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106945 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106946 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106947 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106948 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106949 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 106950 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106951 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106952 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106953 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 106954 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106955 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106956 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 106957 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106958 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 106959 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106960 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106961 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106962 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106963 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 106964 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 106965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 106966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 106967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 106968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 106969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 106970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 106971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 106972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 106973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 106975 | GIR_RootConstrainSelectedInstOperands, |
| 106976 | // GIR_Coverage, 11088, |
| 106977 | GIR_EraseRootFromParent_Done, |
| 106978 | // Label 5488: @339298 |
| 106979 | GIM_Try, /*On fail goto*//*Label 5489*/ GIMT_Encode4(339427), // Rule ID 11091 // |
| 106980 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 106981 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 106982 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 106983 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 106984 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 106985 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 106986 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 106987 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 106988 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 106989 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 106990 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 106991 | // MIs[3] VOP3Mods:src0:src0_mods |
| 106992 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 106993 | // MIs[3] VOP3Mods:src1:src1_mods |
| 106994 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 106995 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 106996 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 106997 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 106998 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 106999 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107000 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107011 | GIR_RootConstrainSelectedInstOperands, |
| 107012 | // GIR_Coverage, 11091, |
| 107013 | GIR_EraseRootFromParent_Done, |
| 107014 | // Label 5489: @339427 |
| 107015 | GIM_Try, /*On fail goto*//*Label 5490*/ GIMT_Encode4(339556), // Rule ID 11092 // |
| 107016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107019 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107020 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107021 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107022 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107023 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107024 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107025 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107026 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107027 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107028 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107029 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107030 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107031 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107032 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107033 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107034 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107035 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107036 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107038 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107047 | GIR_RootConstrainSelectedInstOperands, |
| 107048 | // GIR_Coverage, 11092, |
| 107049 | GIR_EraseRootFromParent_Done, |
| 107050 | // Label 5490: @339556 |
| 107051 | GIM_Try, /*On fail goto*//*Label 5491*/ GIMT_Encode4(339685), // Rule ID 11072 // |
| 107052 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107053 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107054 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107055 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107056 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107057 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107058 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107059 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107060 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107061 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107062 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107063 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107064 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107065 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107066 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107067 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107068 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107069 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107070 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107071 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107072 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107083 | GIR_RootConstrainSelectedInstOperands, |
| 107084 | // GIR_Coverage, 11072, |
| 107085 | GIR_EraseRootFromParent_Done, |
| 107086 | // Label 5491: @339685 |
| 107087 | GIM_Try, /*On fail goto*//*Label 5492*/ GIMT_Encode4(339814), // Rule ID 11073 // |
| 107088 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107089 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107090 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107091 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107092 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107093 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107094 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107095 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107096 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107097 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107098 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107099 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107100 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107101 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107102 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107103 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107104 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107105 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107106 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107107 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107108 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107110 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107117 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107119 | GIR_RootConstrainSelectedInstOperands, |
| 107120 | // GIR_Coverage, 11073, |
| 107121 | GIR_EraseRootFromParent_Done, |
| 107122 | // Label 5492: @339814 |
| 107123 | GIM_Try, /*On fail goto*//*Label 5493*/ GIMT_Encode4(339943), // Rule ID 11076 // |
| 107124 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107125 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107126 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107127 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107128 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107129 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107130 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107131 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107132 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107133 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107134 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107135 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107136 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107137 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107138 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107139 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107140 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107141 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107142 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107143 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107144 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107155 | GIR_RootConstrainSelectedInstOperands, |
| 107156 | // GIR_Coverage, 11076, |
| 107157 | GIR_EraseRootFromParent_Done, |
| 107158 | // Label 5493: @339943 |
| 107159 | GIM_Try, /*On fail goto*//*Label 5494*/ GIMT_Encode4(340072), // Rule ID 11077 // |
| 107160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107161 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107162 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107163 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107164 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107166 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107167 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107168 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107169 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107170 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107171 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107172 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107173 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107174 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107175 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107176 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107177 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107178 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107179 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107180 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107191 | GIR_RootConstrainSelectedInstOperands, |
| 107192 | // GIR_Coverage, 11077, |
| 107193 | GIR_EraseRootFromParent_Done, |
| 107194 | // Label 5494: @340072 |
| 107195 | GIM_Try, /*On fail goto*//*Label 5495*/ GIMT_Encode4(340201), // Rule ID 7325 // |
| 107196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107197 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107198 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107199 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107200 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107201 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107202 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107203 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107204 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107205 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107206 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107207 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107208 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107209 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107211 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107212 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107213 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107214 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107215 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107216 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107227 | GIR_RootConstrainSelectedInstOperands, |
| 107228 | // GIR_Coverage, 7325, |
| 107229 | GIR_EraseRootFromParent_Done, |
| 107230 | // Label 5495: @340201 |
| 107231 | GIM_Try, /*On fail goto*//*Label 5496*/ GIMT_Encode4(340330), // Rule ID 11086 // |
| 107232 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107233 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107234 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107235 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107236 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107237 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107238 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107239 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107240 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107241 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107242 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107243 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107244 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107245 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107246 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107247 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107248 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107249 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107250 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107251 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107252 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107254 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107261 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107263 | GIR_RootConstrainSelectedInstOperands, |
| 107264 | // GIR_Coverage, 11086, |
| 107265 | GIR_EraseRootFromParent_Done, |
| 107266 | // Label 5496: @340330 |
| 107267 | GIM_Try, /*On fail goto*//*Label 5497*/ GIMT_Encode4(340459), // Rule ID 11089 // |
| 107268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107269 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107270 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107271 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107272 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107273 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107274 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107275 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107276 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107277 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107278 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107279 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107280 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107281 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107282 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107283 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107284 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107285 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107286 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107287 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107288 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107299 | GIR_RootConstrainSelectedInstOperands, |
| 107300 | // GIR_Coverage, 11089, |
| 107301 | GIR_EraseRootFromParent_Done, |
| 107302 | // Label 5497: @340459 |
| 107303 | GIM_Try, /*On fail goto*//*Label 5498*/ GIMT_Encode4(340588), // Rule ID 11090 // |
| 107304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107305 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107306 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107307 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107308 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107309 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107310 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107311 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107312 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107313 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107314 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107315 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107316 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107317 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107318 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107319 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107320 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107321 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107322 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107323 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107324 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107335 | GIR_RootConstrainSelectedInstOperands, |
| 107336 | // GIR_Coverage, 11090, |
| 107337 | GIR_EraseRootFromParent_Done, |
| 107338 | // Label 5498: @340588 |
| 107339 | GIM_Try, /*On fail goto*//*Label 5499*/ GIMT_Encode4(340717), // Rule ID 7324 // |
| 107340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107341 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107342 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107343 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107344 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107345 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107346 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107347 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107348 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107349 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107350 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107351 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107352 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107353 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107354 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107355 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107356 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107357 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107358 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107359 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107360 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107371 | GIR_RootConstrainSelectedInstOperands, |
| 107372 | // GIR_Coverage, 7324, |
| 107373 | GIR_EraseRootFromParent_Done, |
| 107374 | // Label 5499: @340717 |
| 107375 | GIM_Try, /*On fail goto*//*Label 5500*/ GIMT_Encode4(340846), // Rule ID 11071 // |
| 107376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107377 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107378 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107379 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107380 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107381 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107382 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107383 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107384 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107385 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107386 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107387 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107388 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107389 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107390 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107391 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107392 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107393 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107394 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107395 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107396 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107407 | GIR_RootConstrainSelectedInstOperands, |
| 107408 | // GIR_Coverage, 11071, |
| 107409 | GIR_EraseRootFromParent_Done, |
| 107410 | // Label 5500: @340846 |
| 107411 | GIM_Try, /*On fail goto*//*Label 5501*/ GIMT_Encode4(340975), // Rule ID 11074 // |
| 107412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107417 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107418 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107419 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107420 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107421 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107422 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107423 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107424 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107425 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107427 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107428 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107429 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107430 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107431 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107432 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107443 | GIR_RootConstrainSelectedInstOperands, |
| 107444 | // GIR_Coverage, 11074, |
| 107445 | GIR_EraseRootFromParent_Done, |
| 107446 | // Label 5501: @340975 |
| 107447 | GIM_Try, /*On fail goto*//*Label 5502*/ GIMT_Encode4(341104), // Rule ID 11075 // |
| 107448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107449 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107450 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107451 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107452 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107453 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107454 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 107455 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107456 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107457 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107458 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107459 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107460 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107461 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107462 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107463 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107464 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107465 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107466 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107467 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107468 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107479 | GIR_RootConstrainSelectedInstOperands, |
| 107480 | // GIR_Coverage, 11075, |
| 107481 | GIR_EraseRootFromParent_Done, |
| 107482 | // Label 5502: @341104 |
| 107483 | GIM_Try, /*On fail goto*//*Label 5503*/ GIMT_Encode4(341233), // Rule ID 11057 // |
| 107484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107486 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107487 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107488 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107489 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107490 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107491 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107492 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107493 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107494 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107495 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107496 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107497 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107498 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107499 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107500 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107501 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107502 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107503 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107504 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107515 | GIR_RootConstrainSelectedInstOperands, |
| 107516 | // GIR_Coverage, 11057, |
| 107517 | GIR_EraseRootFromParent_Done, |
| 107518 | // Label 5503: @341233 |
| 107519 | GIM_Try, /*On fail goto*//*Label 5504*/ GIMT_Encode4(341362), // Rule ID 11058 // |
| 107520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107521 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107522 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107523 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107524 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107525 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107526 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107527 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107528 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107529 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107530 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107531 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107532 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107533 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107534 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107535 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107536 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107537 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107538 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107539 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107540 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107551 | GIR_RootConstrainSelectedInstOperands, |
| 107552 | // GIR_Coverage, 11058, |
| 107553 | GIR_EraseRootFromParent_Done, |
| 107554 | // Label 5504: @341362 |
| 107555 | GIM_Try, /*On fail goto*//*Label 5505*/ GIMT_Encode4(341491), // Rule ID 11061 // |
| 107556 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107557 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107558 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107559 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107560 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107561 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107562 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107563 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107564 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107565 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107566 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107567 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107568 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107569 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107570 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107571 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107572 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107573 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107574 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107575 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107576 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107587 | GIR_RootConstrainSelectedInstOperands, |
| 107588 | // GIR_Coverage, 11061, |
| 107589 | GIR_EraseRootFromParent_Done, |
| 107590 | // Label 5505: @341491 |
| 107591 | GIM_Try, /*On fail goto*//*Label 5506*/ GIMT_Encode4(341620), // Rule ID 11062 // |
| 107592 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107593 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107594 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107595 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107596 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107597 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107598 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107599 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107600 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107601 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107602 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107603 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107604 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107605 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107606 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107607 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107608 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107609 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107610 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107611 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107612 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107623 | GIR_RootConstrainSelectedInstOperands, |
| 107624 | // GIR_Coverage, 11062, |
| 107625 | GIR_EraseRootFromParent_Done, |
| 107626 | // Label 5506: @341620 |
| 107627 | GIM_Try, /*On fail goto*//*Label 5507*/ GIMT_Encode4(341749), // Rule ID 11042 // |
| 107628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107629 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107630 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107631 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107632 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107633 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107634 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107635 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107636 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107637 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107638 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107639 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107640 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107641 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107642 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107643 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107644 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107645 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107646 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107647 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107648 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107659 | GIR_RootConstrainSelectedInstOperands, |
| 107660 | // GIR_Coverage, 11042, |
| 107661 | GIR_EraseRootFromParent_Done, |
| 107662 | // Label 5507: @341749 |
| 107663 | GIM_Try, /*On fail goto*//*Label 5508*/ GIMT_Encode4(341878), // Rule ID 11043 // |
| 107664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107665 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107666 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107667 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107668 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107669 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107670 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107671 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107672 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107673 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107674 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107675 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107676 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107677 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107678 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107679 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107680 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107681 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107682 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107683 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107684 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107686 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107695 | GIR_RootConstrainSelectedInstOperands, |
| 107696 | // GIR_Coverage, 11043, |
| 107697 | GIR_EraseRootFromParent_Done, |
| 107698 | // Label 5508: @341878 |
| 107699 | GIM_Try, /*On fail goto*//*Label 5509*/ GIMT_Encode4(342007), // Rule ID 11046 // |
| 107700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107701 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107702 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107703 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107704 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107705 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107706 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107707 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107708 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107709 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107710 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107711 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107712 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107713 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107714 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107715 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107716 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107717 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107718 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107719 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107720 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107731 | GIR_RootConstrainSelectedInstOperands, |
| 107732 | // GIR_Coverage, 11046, |
| 107733 | GIR_EraseRootFromParent_Done, |
| 107734 | // Label 5509: @342007 |
| 107735 | GIM_Try, /*On fail goto*//*Label 5510*/ GIMT_Encode4(342136), // Rule ID 11047 // |
| 107736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107737 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107738 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107739 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107740 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107741 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107742 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107743 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107744 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107745 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 107746 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107747 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107748 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107749 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107750 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107751 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107752 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107753 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107754 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107755 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107756 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107767 | GIR_RootConstrainSelectedInstOperands, |
| 107768 | // GIR_Coverage, 11047, |
| 107769 | GIR_EraseRootFromParent_Done, |
| 107770 | // Label 5510: @342136 |
| 107771 | GIM_Try, /*On fail goto*//*Label 5511*/ GIMT_Encode4(342265), // Rule ID 7323 // |
| 107772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107773 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107774 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107775 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107776 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107777 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107778 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107779 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107780 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107781 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107782 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107783 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107784 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107785 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107786 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107787 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107788 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107789 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107790 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107791 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107792 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107803 | GIR_RootConstrainSelectedInstOperands, |
| 107804 | // GIR_Coverage, 7323, |
| 107805 | GIR_EraseRootFromParent_Done, |
| 107806 | // Label 5511: @342265 |
| 107807 | GIM_Try, /*On fail goto*//*Label 5512*/ GIMT_Encode4(342394), // Rule ID 11056 // |
| 107808 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107809 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107810 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107811 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107812 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107813 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107814 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107815 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107816 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107817 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107818 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107819 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107820 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107821 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107822 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107823 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107824 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107825 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107826 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107827 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107828 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107839 | GIR_RootConstrainSelectedInstOperands, |
| 107840 | // GIR_Coverage, 11056, |
| 107841 | GIR_EraseRootFromParent_Done, |
| 107842 | // Label 5512: @342394 |
| 107843 | GIM_Try, /*On fail goto*//*Label 5513*/ GIMT_Encode4(342523), // Rule ID 11059 // |
| 107844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107846 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107848 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107849 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107850 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107851 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107852 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107853 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107854 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107855 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107856 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107857 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107858 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107859 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107860 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107861 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107862 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107863 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107864 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107875 | GIR_RootConstrainSelectedInstOperands, |
| 107876 | // GIR_Coverage, 11059, |
| 107877 | GIR_EraseRootFromParent_Done, |
| 107878 | // Label 5513: @342523 |
| 107879 | GIM_Try, /*On fail goto*//*Label 5514*/ GIMT_Encode4(342652), // Rule ID 11060 // |
| 107880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107882 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107883 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107884 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107886 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107887 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107888 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107889 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107890 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 107891 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107892 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107893 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107894 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107895 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107896 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107897 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107898 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107899 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107900 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 107904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 107905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 107906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 107907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107911 | GIR_RootConstrainSelectedInstOperands, |
| 107912 | // GIR_Coverage, 11060, |
| 107913 | GIR_EraseRootFromParent_Done, |
| 107914 | // Label 5514: @342652 |
| 107915 | GIM_Try, /*On fail goto*//*Label 5515*/ GIMT_Encode4(342781), // Rule ID 7322 // |
| 107916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107917 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107918 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107919 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107920 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107921 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107922 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107923 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107924 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107925 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107926 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107927 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107928 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107929 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107930 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107931 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107932 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107933 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107934 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107935 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107936 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107937 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107938 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107945 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107947 | GIR_RootConstrainSelectedInstOperands, |
| 107948 | // GIR_Coverage, 7322, |
| 107949 | GIR_EraseRootFromParent_Done, |
| 107950 | // Label 5515: @342781 |
| 107951 | GIM_Try, /*On fail goto*//*Label 5516*/ GIMT_Encode4(342910), // Rule ID 11041 // |
| 107952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107953 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107954 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107955 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107956 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107957 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107958 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107959 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107960 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107961 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107962 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107963 | // MIs[3] VOP3Mods:src1:src1_mods |
| 107964 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 107965 | // MIs[3] VOP3Mods:src0:src0_mods |
| 107966 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 107967 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 107968 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 107969 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 107970 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 107971 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 107972 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 107973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 107974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 107975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 107976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 107977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 107978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 107979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 107980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 107981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 107983 | GIR_RootConstrainSelectedInstOperands, |
| 107984 | // GIR_Coverage, 11041, |
| 107985 | GIR_EraseRootFromParent_Done, |
| 107986 | // Label 5516: @342910 |
| 107987 | GIM_Try, /*On fail goto*//*Label 5517*/ GIMT_Encode4(343039), // Rule ID 11044 // |
| 107988 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 107989 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 107990 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107991 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 107992 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 107993 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 107994 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 107995 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 107996 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 107997 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 107998 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 107999 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108000 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 108001 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108002 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 108003 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108004 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108005 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108006 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108007 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108008 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108019 | GIR_RootConstrainSelectedInstOperands, |
| 108020 | // GIR_Coverage, 11044, |
| 108021 | GIR_EraseRootFromParent_Done, |
| 108022 | // Label 5517: @343039 |
| 108023 | GIM_Try, /*On fail goto*//*Label 5518*/ GIMT_Encode4(343168), // Rule ID 11045 // |
| 108024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108025 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108026 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108027 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108028 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108029 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 108030 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108031 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108032 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108033 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 108034 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108035 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108036 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 108037 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108038 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 108039 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108040 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108041 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108042 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108043 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108044 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108053 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108055 | GIR_RootConstrainSelectedInstOperands, |
| 108056 | // GIR_Coverage, 11045, |
| 108057 | GIR_EraseRootFromParent_Done, |
| 108058 | // Label 5518: @343168 |
| 108059 | GIM_Try, /*On fail goto*//*Label 5519*/ GIMT_Encode4(343297), // Rule ID 11127 // |
| 108060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108061 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108062 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108063 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108064 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108065 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108066 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108067 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108068 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108069 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108070 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108071 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108072 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108073 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108074 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108075 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108076 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108077 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108078 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108079 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108080 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108081 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108082 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108091 | GIR_RootConstrainSelectedInstOperands, |
| 108092 | // GIR_Coverage, 11127, |
| 108093 | GIR_EraseRootFromParent_Done, |
| 108094 | // Label 5519: @343297 |
| 108095 | GIM_Try, /*On fail goto*//*Label 5520*/ GIMT_Encode4(343426), // Rule ID 11128 // |
| 108096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108098 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108099 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108100 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108101 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108102 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108103 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108104 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108105 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108106 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108107 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108108 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108109 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108110 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108111 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108112 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108113 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108114 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108115 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108116 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108127 | GIR_RootConstrainSelectedInstOperands, |
| 108128 | // GIR_Coverage, 11128, |
| 108129 | GIR_EraseRootFromParent_Done, |
| 108130 | // Label 5520: @343426 |
| 108131 | GIM_Try, /*On fail goto*//*Label 5521*/ GIMT_Encode4(343555), // Rule ID 11129 // |
| 108132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108133 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108134 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108135 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108136 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108137 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108138 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108139 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108140 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108141 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108142 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108143 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108144 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108145 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108146 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108147 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108148 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108149 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108150 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108151 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108152 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108161 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108163 | GIR_RootConstrainSelectedInstOperands, |
| 108164 | // GIR_Coverage, 11129, |
| 108165 | GIR_EraseRootFromParent_Done, |
| 108166 | // Label 5521: @343555 |
| 108167 | GIM_Try, /*On fail goto*//*Label 5522*/ GIMT_Encode4(343684), // Rule ID 11130 // |
| 108168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108169 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108170 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108171 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108172 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108173 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108174 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108175 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108176 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108177 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108178 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108179 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108180 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108181 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108182 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108183 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108184 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108185 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108186 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108187 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108188 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108199 | GIR_RootConstrainSelectedInstOperands, |
| 108200 | // GIR_Coverage, 11130, |
| 108201 | GIR_EraseRootFromParent_Done, |
| 108202 | // Label 5522: @343684 |
| 108203 | GIM_Try, /*On fail goto*//*Label 5523*/ GIMT_Encode4(343813), // Rule ID 11067 // |
| 108204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108205 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108206 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108207 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108208 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108209 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108210 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108211 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108212 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108213 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108214 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108215 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108216 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108217 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108218 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108219 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108220 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108221 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108222 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108223 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108224 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108235 | GIR_RootConstrainSelectedInstOperands, |
| 108236 | // GIR_Coverage, 11067, |
| 108237 | GIR_EraseRootFromParent_Done, |
| 108238 | // Label 5523: @343813 |
| 108239 | GIM_Try, /*On fail goto*//*Label 5524*/ GIMT_Encode4(343942), // Rule ID 11068 // |
| 108240 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108241 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108242 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108243 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108244 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108245 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108246 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108247 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108248 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108249 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108250 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108251 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108252 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108253 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108254 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108255 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108256 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108257 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108258 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108259 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108260 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108261 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108262 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108271 | GIR_RootConstrainSelectedInstOperands, |
| 108272 | // GIR_Coverage, 11068, |
| 108273 | GIR_EraseRootFromParent_Done, |
| 108274 | // Label 5524: @343942 |
| 108275 | GIM_Try, /*On fail goto*//*Label 5525*/ GIMT_Encode4(344071), // Rule ID 11069 // |
| 108276 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108277 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108278 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108279 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108280 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108281 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108282 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108283 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108284 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108285 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108286 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108287 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108288 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108289 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108290 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108291 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108292 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108293 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108294 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108295 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108296 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108307 | GIR_RootConstrainSelectedInstOperands, |
| 108308 | // GIR_Coverage, 11069, |
| 108309 | GIR_EraseRootFromParent_Done, |
| 108310 | // Label 5525: @344071 |
| 108311 | GIM_Try, /*On fail goto*//*Label 5526*/ GIMT_Encode4(344200), // Rule ID 11070 // |
| 108312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108316 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108317 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108318 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108319 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108320 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108321 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108322 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108323 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108325 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108326 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108327 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108328 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108329 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108330 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108331 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108332 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108343 | GIR_RootConstrainSelectedInstOperands, |
| 108344 | // GIR_Coverage, 11070, |
| 108345 | GIR_EraseRootFromParent_Done, |
| 108346 | // Label 5526: @344200 |
| 108347 | GIM_Try, /*On fail goto*//*Label 5527*/ GIMT_Encode4(344329), // Rule ID 11112 // |
| 108348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108353 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108354 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108355 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108356 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108357 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108358 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108359 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108360 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108361 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108363 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108364 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108365 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108366 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108367 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108368 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108379 | GIR_RootConstrainSelectedInstOperands, |
| 108380 | // GIR_Coverage, 11112, |
| 108381 | GIR_EraseRootFromParent_Done, |
| 108382 | // Label 5527: @344329 |
| 108383 | GIM_Try, /*On fail goto*//*Label 5528*/ GIMT_Encode4(344458), // Rule ID 11113 // |
| 108384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108385 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108386 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108387 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108388 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108389 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108390 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108391 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108392 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108393 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108394 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108395 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108396 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108397 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108398 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108399 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108400 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108401 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108402 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108403 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108404 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108413 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108415 | GIR_RootConstrainSelectedInstOperands, |
| 108416 | // GIR_Coverage, 11113, |
| 108417 | GIR_EraseRootFromParent_Done, |
| 108418 | // Label 5528: @344458 |
| 108419 | GIM_Try, /*On fail goto*//*Label 5529*/ GIMT_Encode4(344587), // Rule ID 11114 // |
| 108420 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108421 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108422 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108423 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108424 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108425 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108426 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108427 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108428 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108429 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108430 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108431 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108432 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108433 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108434 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108435 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108436 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108437 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108438 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108439 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108440 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108451 | GIR_RootConstrainSelectedInstOperands, |
| 108452 | // GIR_Coverage, 11114, |
| 108453 | GIR_EraseRootFromParent_Done, |
| 108454 | // Label 5529: @344587 |
| 108455 | GIM_Try, /*On fail goto*//*Label 5530*/ GIMT_Encode4(344716), // Rule ID 11115 // |
| 108456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108457 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108458 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108459 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108460 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108461 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108462 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108463 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108464 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108465 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108466 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108467 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108468 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108469 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108470 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108471 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108472 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108473 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108474 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108475 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108476 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108485 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108487 | GIR_RootConstrainSelectedInstOperands, |
| 108488 | // GIR_Coverage, 11115, |
| 108489 | GIR_EraseRootFromParent_Done, |
| 108490 | // Label 5530: @344716 |
| 108491 | GIM_Try, /*On fail goto*//*Label 5531*/ GIMT_Encode4(344845), // Rule ID 11052 // |
| 108492 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108493 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108494 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108495 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108496 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108497 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108498 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108499 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108500 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108501 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108502 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108503 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108504 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108505 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108506 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108507 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108508 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108509 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108510 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108511 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108512 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108522 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108523 | GIR_RootConstrainSelectedInstOperands, |
| 108524 | // GIR_Coverage, 11052, |
| 108525 | GIR_EraseRootFromParent_Done, |
| 108526 | // Label 5531: @344845 |
| 108527 | GIM_Try, /*On fail goto*//*Label 5532*/ GIMT_Encode4(344974), // Rule ID 11053 // |
| 108528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108529 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108530 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108531 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108532 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108533 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108534 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108535 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108536 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108537 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108538 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108539 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108541 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108542 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108543 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108544 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108545 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108546 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108547 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108548 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 108554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 108555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108559 | GIR_RootConstrainSelectedInstOperands, |
| 108560 | // GIR_Coverage, 11053, |
| 108561 | GIR_EraseRootFromParent_Done, |
| 108562 | // Label 5532: @344974 |
| 108563 | GIM_Try, /*On fail goto*//*Label 5533*/ GIMT_Encode4(345103), // Rule ID 11054 // |
| 108564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108568 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108570 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108572 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108573 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108574 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108575 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108576 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108577 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108578 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108579 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108580 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108581 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108582 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108583 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108584 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108595 | GIR_RootConstrainSelectedInstOperands, |
| 108596 | // GIR_Coverage, 11054, |
| 108597 | GIR_EraseRootFromParent_Done, |
| 108598 | // Label 5533: @345103 |
| 108599 | GIM_Try, /*On fail goto*//*Label 5534*/ GIMT_Encode4(345232), // Rule ID 11055 // |
| 108600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108601 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108605 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 108606 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108607 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108608 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108609 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108610 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108611 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108612 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108613 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108614 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108615 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108616 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108617 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108618 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108619 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108620 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108622 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 108624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 108625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 108628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 108629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108630 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108631 | GIR_RootConstrainSelectedInstOperands, |
| 108632 | // GIR_Coverage, 11055, |
| 108633 | GIR_EraseRootFromParent_Done, |
| 108634 | // Label 5534: @345232 |
| 108635 | GIM_Try, /*On fail goto*//*Label 5535*/ GIMT_Encode4(345361), // Rule ID 11123 // |
| 108636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108637 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108638 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108639 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108640 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108641 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108642 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108643 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108644 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108645 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108646 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108647 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108648 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108649 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108650 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108651 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108652 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108653 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108654 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108655 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108656 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108667 | GIR_RootConstrainSelectedInstOperands, |
| 108668 | // GIR_Coverage, 11123, |
| 108669 | GIR_EraseRootFromParent_Done, |
| 108670 | // Label 5535: @345361 |
| 108671 | GIM_Try, /*On fail goto*//*Label 5536*/ GIMT_Encode4(345490), // Rule ID 11124 // |
| 108672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108673 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108674 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108675 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108676 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108677 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108678 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108679 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108680 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108681 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108682 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108683 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108684 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108685 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108686 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108687 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108688 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108689 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108690 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108691 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108692 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108703 | GIR_RootConstrainSelectedInstOperands, |
| 108704 | // GIR_Coverage, 11124, |
| 108705 | GIR_EraseRootFromParent_Done, |
| 108706 | // Label 5536: @345490 |
| 108707 | GIM_Try, /*On fail goto*//*Label 5537*/ GIMT_Encode4(345619), // Rule ID 11125 // |
| 108708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108709 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108710 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108711 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108712 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108713 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108714 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108715 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108716 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108717 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108718 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108719 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108720 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108721 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108722 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108723 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108724 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108725 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108726 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108727 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108728 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108737 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108739 | GIR_RootConstrainSelectedInstOperands, |
| 108740 | // GIR_Coverage, 11125, |
| 108741 | GIR_EraseRootFromParent_Done, |
| 108742 | // Label 5537: @345619 |
| 108743 | GIM_Try, /*On fail goto*//*Label 5538*/ GIMT_Encode4(345748), // Rule ID 11126 // |
| 108744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108745 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108746 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108747 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108748 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108749 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108750 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108751 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108752 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108753 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108754 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108755 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108756 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108757 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108758 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108759 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108760 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108761 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108762 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108763 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108764 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108765 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108766 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108775 | GIR_RootConstrainSelectedInstOperands, |
| 108776 | // GIR_Coverage, 11126, |
| 108777 | GIR_EraseRootFromParent_Done, |
| 108778 | // Label 5538: @345748 |
| 108779 | GIM_Try, /*On fail goto*//*Label 5539*/ GIMT_Encode4(345877), // Rule ID 11063 // |
| 108780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108781 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108782 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108783 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108784 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108785 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108786 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108787 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108788 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108789 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108790 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108791 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108792 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108793 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108794 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108795 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108796 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108797 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108798 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108799 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108800 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108811 | GIR_RootConstrainSelectedInstOperands, |
| 108812 | // GIR_Coverage, 11063, |
| 108813 | GIR_EraseRootFromParent_Done, |
| 108814 | // Label 5539: @345877 |
| 108815 | GIM_Try, /*On fail goto*//*Label 5540*/ GIMT_Encode4(346006), // Rule ID 11064 // |
| 108816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108817 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108818 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108819 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108820 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108821 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108822 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108823 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108824 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108825 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108826 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108827 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108828 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108829 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108832 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108833 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108834 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108835 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108836 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108847 | GIR_RootConstrainSelectedInstOperands, |
| 108848 | // GIR_Coverage, 11064, |
| 108849 | GIR_EraseRootFromParent_Done, |
| 108850 | // Label 5540: @346006 |
| 108851 | GIM_Try, /*On fail goto*//*Label 5541*/ GIMT_Encode4(346135), // Rule ID 11065 // |
| 108852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108853 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108854 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108855 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108856 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108857 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108858 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108859 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108860 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108861 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108862 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108863 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108864 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108865 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108866 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108867 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108868 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108869 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108870 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108871 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108872 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108873 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108874 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108881 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108882 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108883 | GIR_RootConstrainSelectedInstOperands, |
| 108884 | // GIR_Coverage, 11065, |
| 108885 | GIR_EraseRootFromParent_Done, |
| 108886 | // Label 5541: @346135 |
| 108887 | GIM_Try, /*On fail goto*//*Label 5542*/ GIMT_Encode4(346264), // Rule ID 11066 // |
| 108888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108889 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108890 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108891 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108892 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108893 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108894 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 108895 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108896 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108897 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108898 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108899 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108900 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108901 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108902 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108903 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108904 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108905 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108906 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108907 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108908 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 108912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 108913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 108914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 108915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108919 | GIR_RootConstrainSelectedInstOperands, |
| 108920 | // GIR_Coverage, 11066, |
| 108921 | GIR_EraseRootFromParent_Done, |
| 108922 | // Label 5542: @346264 |
| 108923 | GIM_Try, /*On fail goto*//*Label 5543*/ GIMT_Encode4(346393), // Rule ID 11108 // |
| 108924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108925 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108926 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108927 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108928 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108929 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108930 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108931 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108932 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108933 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108934 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108935 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108936 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108937 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108938 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108939 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108940 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108941 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108942 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108943 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108944 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108953 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108955 | GIR_RootConstrainSelectedInstOperands, |
| 108956 | // GIR_Coverage, 11108, |
| 108957 | GIR_EraseRootFromParent_Done, |
| 108958 | // Label 5543: @346393 |
| 108959 | GIM_Try, /*On fail goto*//*Label 5544*/ GIMT_Encode4(346522), // Rule ID 11109 // |
| 108960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108961 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108962 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108963 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 108964 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 108965 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 108966 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 108967 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 108968 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 108969 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 108970 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 108971 | // MIs[3] VOP3Mods:src1:src1_mods |
| 108972 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 108973 | // MIs[3] VOP3Mods:src0:src0_mods |
| 108974 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 108975 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 108976 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 108977 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 108978 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 108979 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 108980 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 108981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 108982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 108983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 108984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 108985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 108986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 108987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 108988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 108989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108990 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 108991 | GIR_RootConstrainSelectedInstOperands, |
| 108992 | // GIR_Coverage, 11109, |
| 108993 | GIR_EraseRootFromParent_Done, |
| 108994 | // Label 5544: @346522 |
| 108995 | GIM_Try, /*On fail goto*//*Label 5545*/ GIMT_Encode4(346651), // Rule ID 11110 // |
| 108996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 108997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 108998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 108999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109000 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109001 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109003 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109004 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109005 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109006 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109007 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109009 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109010 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109011 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109012 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109013 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109014 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109015 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109016 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109027 | GIR_RootConstrainSelectedInstOperands, |
| 109028 | // GIR_Coverage, 11110, |
| 109029 | GIR_EraseRootFromParent_Done, |
| 109030 | // Label 5545: @346651 |
| 109031 | GIM_Try, /*On fail goto*//*Label 5546*/ GIMT_Encode4(346780), // Rule ID 11111 // |
| 109032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109040 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109041 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109042 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109043 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109044 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109045 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109046 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109047 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109048 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109049 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109050 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109051 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109052 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109063 | GIR_RootConstrainSelectedInstOperands, |
| 109064 | // GIR_Coverage, 11111, |
| 109065 | GIR_EraseRootFromParent_Done, |
| 109066 | // Label 5546: @346780 |
| 109067 | GIM_Try, /*On fail goto*//*Label 5547*/ GIMT_Encode4(346909), // Rule ID 11048 // |
| 109068 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109069 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109070 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109071 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109072 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109073 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109074 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109075 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109076 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109077 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109078 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109079 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109080 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109081 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109082 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109083 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109084 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109085 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109086 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109087 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109088 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109097 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109098 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109099 | GIR_RootConstrainSelectedInstOperands, |
| 109100 | // GIR_Coverage, 11048, |
| 109101 | GIR_EraseRootFromParent_Done, |
| 109102 | // Label 5547: @346909 |
| 109103 | GIM_Try, /*On fail goto*//*Label 5548*/ GIMT_Encode4(347038), // Rule ID 11049 // |
| 109104 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109105 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109106 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109107 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109108 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109109 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109110 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109111 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109112 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109113 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109114 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109115 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109116 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109117 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109118 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109119 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109120 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109121 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109122 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109123 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109124 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109126 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109135 | GIR_RootConstrainSelectedInstOperands, |
| 109136 | // GIR_Coverage, 11049, |
| 109137 | GIR_EraseRootFromParent_Done, |
| 109138 | // Label 5548: @347038 |
| 109139 | GIM_Try, /*On fail goto*//*Label 5549*/ GIMT_Encode4(347167), // Rule ID 11050 // |
| 109140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109141 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109142 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109143 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109144 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109145 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109146 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109147 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109148 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109149 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109150 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109151 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109152 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109153 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109154 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109155 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109156 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109157 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109158 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109159 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109160 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109171 | GIR_RootConstrainSelectedInstOperands, |
| 109172 | // GIR_Coverage, 11050, |
| 109173 | GIR_EraseRootFromParent_Done, |
| 109174 | // Label 5549: @347167 |
| 109175 | GIM_Try, /*On fail goto*//*Label 5550*/ GIMT_Encode4(347296), // Rule ID 11051 // |
| 109176 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109177 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109178 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109179 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109180 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109181 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109182 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 109183 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109184 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109185 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 109186 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109187 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109188 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 109189 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109190 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 109191 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 109192 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109193 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109194 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109195 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109196 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 109198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109207 | GIR_RootConstrainSelectedInstOperands, |
| 109208 | // GIR_Coverage, 11051, |
| 109209 | GIR_EraseRootFromParent_Done, |
| 109210 | // Label 5550: @347296 |
| 109211 | GIM_Try, /*On fail goto*//*Label 5551*/ GIMT_Encode4(347408), // Rule ID 11934 // |
| 109212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109213 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109214 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 109215 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 109216 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109217 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109218 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109219 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109220 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109221 | GIM_CheckHasOneUse, /*MI*/2, |
| 109222 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 109223 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 109224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109225 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109226 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109227 | // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109229 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 109233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 109234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 109235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 109236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109238 | GIR_RootConstrainSelectedInstOperands, |
| 109239 | // GIR_Coverage, 11934, |
| 109240 | GIR_EraseRootFromParent_Done, |
| 109241 | // Label 5551: @347408 |
| 109242 | GIM_Try, /*On fail goto*//*Label 5552*/ GIMT_Encode4(347520), // Rule ID 11933 // |
| 109243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109244 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109245 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 109246 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 109247 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109248 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109249 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109250 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109251 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109252 | GIM_CheckHasOneUse, /*MI*/2, |
| 109253 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 109254 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 109255 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109256 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109257 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109258 | // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 109264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 109265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 109266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 109267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109269 | GIR_RootConstrainSelectedInstOperands, |
| 109270 | // GIR_Coverage, 11933, |
| 109271 | GIR_EraseRootFromParent_Done, |
| 109272 | // Label 5552: @347520 |
| 109273 | GIM_Try, /*On fail goto*//*Label 5553*/ GIMT_Encode4(347632), // Rule ID 7403 // |
| 109274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109275 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109276 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109277 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 109278 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109279 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109280 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109281 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109282 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109283 | GIM_CheckHasOneUse, /*MI*/2, |
| 109284 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 109285 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 109286 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109287 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109288 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109289 | // (fmaxnum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109300 | GIR_RootConstrainSelectedInstOperands, |
| 109301 | // GIR_Coverage, 7403, |
| 109302 | GIR_EraseRootFromParent_Done, |
| 109303 | // Label 5553: @347632 |
| 109304 | GIM_Try, /*On fail goto*//*Label 5554*/ GIMT_Encode4(347744), // Rule ID 7402 // |
| 109305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109308 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 109309 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 109311 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 109313 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 109314 | GIM_CheckHasOneUse, /*MI*/2, |
| 109315 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 109316 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 109317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109318 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109319 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109320 | // (fmaxnum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109331 | GIR_RootConstrainSelectedInstOperands, |
| 109332 | // GIR_Coverage, 7402, |
| 109333 | GIR_EraseRootFromParent_Done, |
| 109334 | // Label 5554: @347744 |
| 109335 | GIM_Try, /*On fail goto*//*Label 5555*/ GIMT_Encode4(347840), // Rule ID 11918 // |
| 109336 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109337 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109338 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 109339 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109340 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109341 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109342 | GIM_CheckHasOneUse, /*MI*/1, |
| 109343 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109345 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109346 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109347 | // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109348 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109349 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 109353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 109354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 109355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 109356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109357 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109358 | GIR_RootConstrainSelectedInstOperands, |
| 109359 | // GIR_Coverage, 11918, |
| 109360 | GIR_EraseRootFromParent_Done, |
| 109361 | // Label 5555: @347840 |
| 109362 | GIM_Try, /*On fail goto*//*Label 5556*/ GIMT_Encode4(347936), // Rule ID 11917 // |
| 109363 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109365 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 109366 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109367 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109368 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109369 | GIM_CheckHasOneUse, /*MI*/1, |
| 109370 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109372 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109373 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109374 | // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 109380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 109381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 109382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 109383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109385 | GIR_RootConstrainSelectedInstOperands, |
| 109386 | // GIR_Coverage, 11917, |
| 109387 | GIR_EraseRootFromParent_Done, |
| 109388 | // Label 5556: @347936 |
| 109389 | GIM_Try, /*On fail goto*//*Label 5557*/ GIMT_Encode4(348032), // Rule ID 7387 // |
| 109390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109391 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109392 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109393 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109394 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109395 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109396 | GIM_CheckHasOneUse, /*MI*/1, |
| 109397 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109399 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109400 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109401 | // (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109412 | GIR_RootConstrainSelectedInstOperands, |
| 109413 | // GIR_Coverage, 7387, |
| 109414 | GIR_EraseRootFromParent_Done, |
| 109415 | // Label 5557: @348032 |
| 109416 | GIM_Try, /*On fail goto*//*Label 5558*/ GIMT_Encode4(348128), // Rule ID 7386 // |
| 109417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 109418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109419 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109420 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109421 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 109422 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 109423 | GIM_CheckHasOneUse, /*MI*/1, |
| 109424 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 109425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109426 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109427 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109428 | // (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 109430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109439 | GIR_RootConstrainSelectedInstOperands, |
| 109440 | // GIR_Coverage, 7386, |
| 109441 | GIR_EraseRootFromParent_Done, |
| 109442 | // Label 5558: @348128 |
| 109443 | GIM_Try, /*On fail goto*//*Label 5559*/ GIMT_Encode4(348163), // Rule ID 95 // |
| 109444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 109445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 109446 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 109447 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 109448 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18520), |
| 109449 | // (fmaxnum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18520>> => (S_MAX_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 109450 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F32), |
| 109451 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 109452 | GIR_RootConstrainSelectedInstOperands, |
| 109453 | // GIR_Coverage, 95, |
| 109454 | GIR_Done, |
| 109455 | // Label 5559: @348163 |
| 109456 | GIM_Try, /*On fail goto*//*Label 5560*/ GIMT_Encode4(348223), // Rule ID 740 // |
| 109457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109460 | // (fmaxnum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 109462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 109464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 109466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 109468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 109469 | GIR_RootConstrainSelectedInstOperands, |
| 109470 | // GIR_Coverage, 740, |
| 109471 | GIR_EraseRootFromParent_Done, |
| 109472 | // Label 5560: @348223 |
| 109473 | GIM_Try, /*On fail goto*//*Label 5561*/ GIMT_Encode4(348283), // Rule ID 8060 // |
| 109474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109477 | // (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 109479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 109481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 109483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 109485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 109486 | GIR_RootConstrainSelectedInstOperands, |
| 109487 | // GIR_Coverage, 8060, |
| 109488 | GIR_EraseRootFromParent_Done, |
| 109489 | // Label 5561: @348283 |
| 109490 | GIM_Reject, |
| 109491 | // Label 5422: @348284 |
| 109492 | GIM_Reject, |
| 109493 | // Label 5276: @348285 |
| 109494 | GIM_Try, /*On fail goto*//*Label 5562*/ GIMT_Encode4(348537), |
| 109495 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 109496 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 109497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 109498 | GIM_Try, /*On fail goto*//*Label 5563*/ GIMT_Encode4(348359), // Rule ID 841 // |
| 109499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 109500 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109501 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109502 | // (fmaxnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 109504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 109506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 109508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 109510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 109511 | GIR_RootConstrainSelectedInstOperands, |
| 109512 | // GIR_Coverage, 841, |
| 109513 | GIR_EraseRootFromParent_Done, |
| 109514 | // Label 5563: @348359 |
| 109515 | GIM_Try, /*On fail goto*//*Label 5564*/ GIMT_Encode4(348418), // Rule ID 860 // |
| 109516 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 109517 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109519 | // (fmaxnum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 109521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 109523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 109525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 109527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 109528 | GIR_RootConstrainSelectedInstOperands, |
| 109529 | // GIR_Coverage, 860, |
| 109530 | GIR_EraseRootFromParent_Done, |
| 109531 | // Label 5564: @348418 |
| 109532 | GIM_Try, /*On fail goto*//*Label 5565*/ GIMT_Encode4(348477), // Rule ID 8086 // |
| 109533 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 109534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109536 | // (fmaxnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 109538 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 109540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 109542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 109544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 109545 | GIR_RootConstrainSelectedInstOperands, |
| 109546 | // GIR_Coverage, 8086, |
| 109547 | GIR_EraseRootFromParent_Done, |
| 109548 | // Label 5565: @348477 |
| 109549 | GIM_Try, /*On fail goto*//*Label 5566*/ GIMT_Encode4(348536), // Rule ID 8100 // |
| 109550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 109551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109552 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 109553 | // (fmaxnum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 109554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 109555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 109557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 109559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 109561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 109562 | GIR_RootConstrainSelectedInstOperands, |
| 109563 | // GIR_Coverage, 8100, |
| 109564 | GIR_EraseRootFromParent_Done, |
| 109565 | // Label 5566: @348536 |
| 109566 | GIM_Reject, |
| 109567 | // Label 5562: @348537 |
| 109568 | GIM_Reject, |
| 109569 | // Label 5277: @348538 |
| 109570 | GIM_Try, /*On fail goto*//*Label 5567*/ GIMT_Encode4(348609), // Rule ID 962 // |
| 109571 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 109572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 109573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 109575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 109576 | // (fmaxnum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MAX_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 109577 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16), |
| 109578 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 109580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 109582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109584 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109585 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109588 | GIR_RootConstrainSelectedInstOperands, |
| 109589 | // GIR_Coverage, 962, |
| 109590 | GIR_EraseRootFromParent_Done, |
| 109591 | // Label 5567: @348609 |
| 109592 | GIM_Reject, |
| 109593 | // Label 5278: @348610 |
| 109594 | GIM_Reject, |
| 109595 | // Label 82: @348611 |
| 109596 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5572*/ GIMT_Encode4(384949), |
| 109597 | /*GILLT_s16*//*Label 5568*/ GIMT_Encode4(348638), |
| 109598 | /*GILLT_s32*//*Label 5569*/ GIMT_Encode4(367112), |
| 109599 | /*GILLT_s64*//*Label 5570*/ GIMT_Encode4(384624), |
| 109600 | /*GILLT_v2s16*//*Label 5571*/ GIMT_Encode4(384877), |
| 109601 | // Label 5568: @348638 |
| 109602 | GIM_Try, /*On fail goto*//*Label 5573*/ GIMT_Encode4(367111), |
| 109603 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 109604 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 109605 | GIM_Try, /*On fail goto*//*Label 5574*/ GIMT_Encode4(348784), // Rule ID 11777 // |
| 109606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109609 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109612 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109613 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109614 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109615 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109616 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109617 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109618 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109619 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109620 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109622 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109623 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109624 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109625 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109626 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109627 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109628 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109629 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109637 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109639 | GIR_RootConstrainSelectedInstOperands, |
| 109640 | // GIR_Coverage, 11777, |
| 109641 | GIR_EraseRootFromParent_Done, |
| 109642 | // Label 5574: @348784 |
| 109643 | GIM_Try, /*On fail goto*//*Label 5575*/ GIMT_Encode4(348919), // Rule ID 11778 // |
| 109644 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109645 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109646 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109647 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109648 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109649 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109650 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109651 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109652 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109653 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109654 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109655 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109656 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109657 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109658 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109659 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109660 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109661 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109662 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109663 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109664 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109665 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109674 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109677 | GIR_RootConstrainSelectedInstOperands, |
| 109678 | // GIR_Coverage, 11778, |
| 109679 | GIR_EraseRootFromParent_Done, |
| 109680 | // Label 5575: @348919 |
| 109681 | GIM_Try, /*On fail goto*//*Label 5576*/ GIMT_Encode4(349054), // Rule ID 11781 // |
| 109682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109684 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109685 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109686 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109687 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109688 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109689 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109690 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109691 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109692 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109693 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109694 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109695 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109696 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109698 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109699 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109700 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109701 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109702 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109703 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109712 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109713 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109715 | GIR_RootConstrainSelectedInstOperands, |
| 109716 | // GIR_Coverage, 11781, |
| 109717 | GIR_EraseRootFromParent_Done, |
| 109718 | // Label 5576: @349054 |
| 109719 | GIM_Try, /*On fail goto*//*Label 5577*/ GIMT_Encode4(349189), // Rule ID 11782 // |
| 109720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109724 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109725 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109726 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109727 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109728 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109729 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109730 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109731 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109732 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109733 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109734 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109735 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109737 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109738 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109739 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109740 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109741 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109753 | GIR_RootConstrainSelectedInstOperands, |
| 109754 | // GIR_Coverage, 11782, |
| 109755 | GIR_EraseRootFromParent_Done, |
| 109756 | // Label 5577: @349189 |
| 109757 | GIM_Try, /*On fail goto*//*Label 5578*/ GIMT_Encode4(349324), // Rule ID 11762 // |
| 109758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109760 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109761 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109762 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109763 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109764 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109765 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109766 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109767 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109768 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109769 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109770 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109771 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109772 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109773 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109774 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109775 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109776 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109777 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109778 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109779 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109780 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109781 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109789 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109791 | GIR_RootConstrainSelectedInstOperands, |
| 109792 | // GIR_Coverage, 11762, |
| 109793 | GIR_EraseRootFromParent_Done, |
| 109794 | // Label 5578: @349324 |
| 109795 | GIM_Try, /*On fail goto*//*Label 5579*/ GIMT_Encode4(349459), // Rule ID 11763 // |
| 109796 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109797 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109798 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109799 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109800 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109801 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109802 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109803 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109804 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109805 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109806 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109807 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109808 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109809 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109810 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109811 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109812 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109813 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109814 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109815 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109816 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109817 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109819 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109826 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109827 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109829 | GIR_RootConstrainSelectedInstOperands, |
| 109830 | // GIR_Coverage, 11763, |
| 109831 | GIR_EraseRootFromParent_Done, |
| 109832 | // Label 5579: @349459 |
| 109833 | GIM_Try, /*On fail goto*//*Label 5580*/ GIMT_Encode4(349594), // Rule ID 11766 // |
| 109834 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109835 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109836 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109837 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109838 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109839 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109840 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109841 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109842 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109843 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109844 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109845 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109846 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109847 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109848 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109850 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109851 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109852 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109853 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109854 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109855 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109864 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109865 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109867 | GIR_RootConstrainSelectedInstOperands, |
| 109868 | // GIR_Coverage, 11766, |
| 109869 | GIR_EraseRootFromParent_Done, |
| 109870 | // Label 5580: @349594 |
| 109871 | GIM_Try, /*On fail goto*//*Label 5581*/ GIMT_Encode4(349729), // Rule ID 11767 // |
| 109872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109874 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109875 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109876 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109877 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109878 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109879 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109880 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109881 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109882 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 109883 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 109884 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109885 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109886 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109887 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109889 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109890 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109891 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109892 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109893 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 109897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 109898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 109899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 109900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109905 | GIR_RootConstrainSelectedInstOperands, |
| 109906 | // GIR_Coverage, 11767, |
| 109907 | GIR_EraseRootFromParent_Done, |
| 109908 | // Label 5581: @349729 |
| 109909 | GIM_Try, /*On fail goto*//*Label 5582*/ GIMT_Encode4(349864), // Rule ID 7371 // |
| 109910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109911 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109912 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109913 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109914 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109915 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109916 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109917 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109918 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109919 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109920 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 109921 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109922 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109923 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109924 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109925 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109926 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109927 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109928 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109929 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109930 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109931 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109933 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109943 | GIR_RootConstrainSelectedInstOperands, |
| 109944 | // GIR_Coverage, 7371, |
| 109945 | GIR_EraseRootFromParent_Done, |
| 109946 | // Label 5582: @349864 |
| 109947 | GIM_Try, /*On fail goto*//*Label 5583*/ GIMT_Encode4(349999), // Rule ID 11776 // |
| 109948 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109950 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109951 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109952 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109953 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109954 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109955 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109956 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109957 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109958 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 109959 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109960 | // MIs[3] VOP3Mods:src1:src1_mods |
| 109961 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 109962 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109963 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 109964 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 109965 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 109966 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 109967 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 109968 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 109969 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 109970 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 109971 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 109972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 109973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 109974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 109975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 109976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 109977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 109978 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109979 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 109981 | GIR_RootConstrainSelectedInstOperands, |
| 109982 | // GIR_Coverage, 11776, |
| 109983 | GIR_EraseRootFromParent_Done, |
| 109984 | // Label 5583: @349999 |
| 109985 | GIM_Try, /*On fail goto*//*Label 5584*/ GIMT_Encode4(350134), // Rule ID 11779 // |
| 109986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 109987 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 109988 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 109989 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109990 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 109991 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 109992 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 109993 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 109994 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 109995 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 109996 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 109997 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 109998 | // MIs[3] VOP3Mods:src0:src0_mods |
| 109999 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110000 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110002 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110003 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110004 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110005 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110006 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110007 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110019 | GIR_RootConstrainSelectedInstOperands, |
| 110020 | // GIR_Coverage, 11779, |
| 110021 | GIR_EraseRootFromParent_Done, |
| 110022 | // Label 5584: @350134 |
| 110023 | GIM_Try, /*On fail goto*//*Label 5585*/ GIMT_Encode4(350269), // Rule ID 11780 // |
| 110024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110029 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110030 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110031 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110032 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110033 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110034 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110035 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110036 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110037 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110038 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110039 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110040 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110041 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110042 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110043 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110044 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110045 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110057 | GIR_RootConstrainSelectedInstOperands, |
| 110058 | // GIR_Coverage, 11780, |
| 110059 | GIR_EraseRootFromParent_Done, |
| 110060 | // Label 5585: @350269 |
| 110061 | GIM_Try, /*On fail goto*//*Label 5586*/ GIMT_Encode4(350404), // Rule ID 7370 // |
| 110062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110064 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110065 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110066 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110067 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110068 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110069 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110070 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110071 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110072 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110073 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110074 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110075 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110076 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110077 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110078 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110079 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110080 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110081 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110082 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110083 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110092 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110093 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110095 | GIR_RootConstrainSelectedInstOperands, |
| 110096 | // GIR_Coverage, 7370, |
| 110097 | GIR_EraseRootFromParent_Done, |
| 110098 | // Label 5586: @350404 |
| 110099 | GIM_Try, /*On fail goto*//*Label 5587*/ GIMT_Encode4(350539), // Rule ID 11761 // |
| 110100 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110103 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110106 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110107 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110108 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110109 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110110 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110111 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110112 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110113 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110114 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110116 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110117 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110118 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110119 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110120 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110121 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110133 | GIR_RootConstrainSelectedInstOperands, |
| 110134 | // GIR_Coverage, 11761, |
| 110135 | GIR_EraseRootFromParent_Done, |
| 110136 | // Label 5587: @350539 |
| 110137 | GIM_Try, /*On fail goto*//*Label 5588*/ GIMT_Encode4(350674), // Rule ID 11764 // |
| 110138 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110139 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110140 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110141 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110142 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110143 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110144 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110145 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110146 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110147 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110148 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110149 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110150 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110151 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110152 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110153 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110154 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110155 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110156 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110157 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110158 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110159 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110169 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110171 | GIR_RootConstrainSelectedInstOperands, |
| 110172 | // GIR_Coverage, 11764, |
| 110173 | GIR_EraseRootFromParent_Done, |
| 110174 | // Label 5588: @350674 |
| 110175 | GIM_Try, /*On fail goto*//*Label 5589*/ GIMT_Encode4(350809), // Rule ID 11765 // |
| 110176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110178 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110179 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110180 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110181 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110182 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110183 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110184 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110185 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110186 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110187 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110188 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110189 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110190 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110191 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110192 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110193 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110194 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110195 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110196 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110197 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110209 | GIR_RootConstrainSelectedInstOperands, |
| 110210 | // GIR_Coverage, 11765, |
| 110211 | GIR_EraseRootFromParent_Done, |
| 110212 | // Label 5589: @350809 |
| 110213 | GIM_Try, /*On fail goto*//*Label 5590*/ GIMT_Encode4(350944), // Rule ID 11747 // |
| 110214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110215 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110216 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110217 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110218 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110219 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110220 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110221 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110222 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110223 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110224 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110225 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110226 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110227 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110228 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110229 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110230 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110231 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110232 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110233 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110234 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110235 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110247 | GIR_RootConstrainSelectedInstOperands, |
| 110248 | // GIR_Coverage, 11747, |
| 110249 | GIR_EraseRootFromParent_Done, |
| 110250 | // Label 5590: @350944 |
| 110251 | GIM_Try, /*On fail goto*//*Label 5591*/ GIMT_Encode4(351079), // Rule ID 11748 // |
| 110252 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110255 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110259 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110261 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110262 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110263 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110264 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110265 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110266 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110268 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110269 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110270 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110271 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110272 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110273 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110285 | GIR_RootConstrainSelectedInstOperands, |
| 110286 | // GIR_Coverage, 11748, |
| 110287 | GIR_EraseRootFromParent_Done, |
| 110288 | // Label 5591: @351079 |
| 110289 | GIM_Try, /*On fail goto*//*Label 5592*/ GIMT_Encode4(351214), // Rule ID 11751 // |
| 110290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110291 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110292 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110293 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110294 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110295 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110296 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110297 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110298 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110299 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110300 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110301 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110302 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110303 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110304 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110305 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110306 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110307 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110308 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110309 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110310 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110311 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110323 | GIR_RootConstrainSelectedInstOperands, |
| 110324 | // GIR_Coverage, 11751, |
| 110325 | GIR_EraseRootFromParent_Done, |
| 110326 | // Label 5592: @351214 |
| 110327 | GIM_Try, /*On fail goto*//*Label 5593*/ GIMT_Encode4(351349), // Rule ID 11752 // |
| 110328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110330 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110331 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110332 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110333 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110334 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110335 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110336 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110337 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110338 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110339 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110340 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110341 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110342 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110343 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110344 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110345 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110346 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110347 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110348 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110349 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110358 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110359 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110361 | GIR_RootConstrainSelectedInstOperands, |
| 110362 | // GIR_Coverage, 11752, |
| 110363 | GIR_EraseRootFromParent_Done, |
| 110364 | // Label 5593: @351349 |
| 110365 | GIM_Try, /*On fail goto*//*Label 5594*/ GIMT_Encode4(351484), // Rule ID 11732 // |
| 110366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110367 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110368 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110369 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110370 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110371 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110372 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110373 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110374 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110375 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110376 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110377 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110378 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110379 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110380 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110382 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110383 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110384 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110385 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110386 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110387 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110396 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110399 | GIR_RootConstrainSelectedInstOperands, |
| 110400 | // GIR_Coverage, 11732, |
| 110401 | GIR_EraseRootFromParent_Done, |
| 110402 | // Label 5594: @351484 |
| 110403 | GIM_Try, /*On fail goto*//*Label 5595*/ GIMT_Encode4(351619), // Rule ID 11733 // |
| 110404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110406 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110407 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110408 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110409 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110410 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110411 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110412 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110413 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110414 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110415 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110416 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110417 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110418 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110419 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110420 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110421 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110422 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110423 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110424 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110425 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110437 | GIR_RootConstrainSelectedInstOperands, |
| 110438 | // GIR_Coverage, 11733, |
| 110439 | GIR_EraseRootFromParent_Done, |
| 110440 | // Label 5595: @351619 |
| 110441 | GIM_Try, /*On fail goto*//*Label 5596*/ GIMT_Encode4(351754), // Rule ID 11736 // |
| 110442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110443 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110445 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110446 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110447 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110448 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110449 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110450 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110451 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110452 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110453 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110454 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110455 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110456 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110458 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110459 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110460 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110461 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110462 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110463 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110473 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110475 | GIR_RootConstrainSelectedInstOperands, |
| 110476 | // GIR_Coverage, 11736, |
| 110477 | GIR_EraseRootFromParent_Done, |
| 110478 | // Label 5596: @351754 |
| 110479 | GIM_Try, /*On fail goto*//*Label 5597*/ GIMT_Encode4(351889), // Rule ID 11737 // |
| 110480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110481 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110482 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110483 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110484 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110485 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110486 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110487 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110488 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110489 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110490 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 110491 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110492 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110493 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110494 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110495 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110496 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110497 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110498 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110499 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110500 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110501 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110503 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110510 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110511 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110513 | GIR_RootConstrainSelectedInstOperands, |
| 110514 | // GIR_Coverage, 11737, |
| 110515 | GIR_EraseRootFromParent_Done, |
| 110516 | // Label 5597: @351889 |
| 110517 | GIM_Try, /*On fail goto*//*Label 5598*/ GIMT_Encode4(352024), // Rule ID 7369 // |
| 110518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110519 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110520 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110521 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110522 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110523 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110524 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110525 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110526 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110527 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110528 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110529 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110530 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110531 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110532 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110534 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110535 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110536 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110537 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110538 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110539 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110551 | GIR_RootConstrainSelectedInstOperands, |
| 110552 | // GIR_Coverage, 7369, |
| 110553 | GIR_EraseRootFromParent_Done, |
| 110554 | // Label 5598: @352024 |
| 110555 | GIM_Try, /*On fail goto*//*Label 5599*/ GIMT_Encode4(352159), // Rule ID 11746 // |
| 110556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110558 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110559 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110560 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110561 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110562 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110563 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110564 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110565 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110566 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110567 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110568 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110569 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110570 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110571 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110572 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110573 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110574 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110575 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110576 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110577 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110589 | GIR_RootConstrainSelectedInstOperands, |
| 110590 | // GIR_Coverage, 11746, |
| 110591 | GIR_EraseRootFromParent_Done, |
| 110592 | // Label 5599: @352159 |
| 110593 | GIM_Try, /*On fail goto*//*Label 5600*/ GIMT_Encode4(352294), // Rule ID 11749 // |
| 110594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110600 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110601 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110602 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110603 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110604 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110605 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110606 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110607 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110608 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110609 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110610 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110611 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110612 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110613 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110614 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110615 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110627 | GIR_RootConstrainSelectedInstOperands, |
| 110628 | // GIR_Coverage, 11749, |
| 110629 | GIR_EraseRootFromParent_Done, |
| 110630 | // Label 5600: @352294 |
| 110631 | GIM_Try, /*On fail goto*//*Label 5601*/ GIMT_Encode4(352429), // Rule ID 11750 // |
| 110632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110634 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110635 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110636 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110637 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110638 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110639 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110640 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110641 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110642 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110643 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110644 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110645 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110646 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110648 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110649 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110650 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110651 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110652 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110653 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110662 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110665 | GIR_RootConstrainSelectedInstOperands, |
| 110666 | // GIR_Coverage, 11750, |
| 110667 | GIR_EraseRootFromParent_Done, |
| 110668 | // Label 5601: @352429 |
| 110669 | GIM_Try, /*On fail goto*//*Label 5602*/ GIMT_Encode4(352564), // Rule ID 7368 // |
| 110670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110675 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110676 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110677 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110678 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110679 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110680 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110681 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110682 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110683 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110684 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110685 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110686 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110687 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110688 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110689 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110690 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110691 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110701 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110703 | GIR_RootConstrainSelectedInstOperands, |
| 110704 | // GIR_Coverage, 7368, |
| 110705 | GIR_EraseRootFromParent_Done, |
| 110706 | // Label 5602: @352564 |
| 110707 | GIM_Try, /*On fail goto*//*Label 5603*/ GIMT_Encode4(352699), // Rule ID 11731 // |
| 110708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110709 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110710 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110711 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110712 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110713 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110714 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110715 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110716 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110717 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110718 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110719 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110720 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110721 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110722 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110723 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110724 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110725 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110726 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110727 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110728 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110729 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 110733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 110734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110738 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110741 | GIR_RootConstrainSelectedInstOperands, |
| 110742 | // GIR_Coverage, 11731, |
| 110743 | GIR_EraseRootFromParent_Done, |
| 110744 | // Label 5603: @352699 |
| 110745 | GIM_Try, /*On fail goto*//*Label 5604*/ GIMT_Encode4(352834), // Rule ID 11734 // |
| 110746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110747 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110748 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110749 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110750 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110751 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110752 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110753 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110754 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110755 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110756 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110757 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110758 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110759 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110760 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110761 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110762 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110763 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110764 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110765 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110766 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110767 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110776 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110777 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110779 | GIR_RootConstrainSelectedInstOperands, |
| 110780 | // GIR_Coverage, 11734, |
| 110781 | GIR_EraseRootFromParent_Done, |
| 110782 | // Label 5604: @352834 |
| 110783 | GIM_Try, /*On fail goto*//*Label 5605*/ GIMT_Encode4(352969), // Rule ID 11735 // |
| 110784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110787 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110790 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 110791 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110792 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110793 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 110795 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 110796 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110797 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 110798 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 110800 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110801 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110802 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110803 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110804 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110805 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 110811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 110812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 110813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 110814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110817 | GIR_RootConstrainSelectedInstOperands, |
| 110818 | // GIR_Coverage, 11735, |
| 110819 | GIR_EraseRootFromParent_Done, |
| 110820 | // Label 5605: @352969 |
| 110821 | GIM_Try, /*On fail goto*//*Label 5606*/ GIMT_Encode4(353104), // Rule ID 11787 // |
| 110822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110827 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110828 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 110829 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110830 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110831 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110832 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 110833 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110834 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110835 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 110836 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 110838 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110839 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110840 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110841 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110842 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110843 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 110849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 110850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 110851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 110852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110853 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110855 | GIR_RootConstrainSelectedInstOperands, |
| 110856 | // GIR_Coverage, 11787, |
| 110857 | GIR_EraseRootFromParent_Done, |
| 110858 | // Label 5606: @353104 |
| 110859 | GIM_Try, /*On fail goto*//*Label 5607*/ GIMT_Encode4(353239), // Rule ID 11788 // |
| 110860 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110861 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110862 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110863 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110864 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110865 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110866 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 110867 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110868 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110869 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110870 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 110871 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110872 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110873 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 110874 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110875 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 110876 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110877 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110878 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110879 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110880 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110881 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 110886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 110887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 110888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 110889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 110890 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110891 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110893 | GIR_RootConstrainSelectedInstOperands, |
| 110894 | // GIR_Coverage, 11788, |
| 110895 | GIR_EraseRootFromParent_Done, |
| 110896 | // Label 5607: @353239 |
| 110897 | GIM_Try, /*On fail goto*//*Label 5608*/ GIMT_Encode4(353374), // Rule ID 11789 // |
| 110898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110899 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110900 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110901 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110902 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110903 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110904 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 110905 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110906 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110907 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110908 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 110909 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110910 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110911 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 110912 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 110914 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110915 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110916 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110917 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110918 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110919 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 110923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 110924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 110927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 110928 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110929 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110931 | GIR_RootConstrainSelectedInstOperands, |
| 110932 | // GIR_Coverage, 11789, |
| 110933 | GIR_EraseRootFromParent_Done, |
| 110934 | // Label 5608: @353374 |
| 110935 | GIM_Try, /*On fail goto*//*Label 5609*/ GIMT_Encode4(353509), // Rule ID 11790 // |
| 110936 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110941 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110942 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 110943 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110944 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110945 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110946 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 110947 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110948 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110949 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 110950 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110951 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 110952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110953 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110954 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110955 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110956 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110957 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 110961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 110962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 110963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 110964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 110965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 110966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 110969 | GIR_RootConstrainSelectedInstOperands, |
| 110970 | // GIR_Coverage, 11790, |
| 110971 | GIR_EraseRootFromParent_Done, |
| 110972 | // Label 5609: @353509 |
| 110973 | GIM_Try, /*On fail goto*//*Label 5610*/ GIMT_Encode4(353644), // Rule ID 11727 // |
| 110974 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 110975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 110976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 110977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 110978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 110979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 110980 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 110981 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 110982 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 110983 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 110984 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 110985 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 110986 | // MIs[3] VOP3Mods:src0:src0_mods |
| 110987 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 110988 | // MIs[3] VOP3Mods:src1:src1_mods |
| 110989 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 110990 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 110991 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 110992 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 110993 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 110994 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 110995 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 110996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 110997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 110998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 110999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111007 | GIR_RootConstrainSelectedInstOperands, |
| 111008 | // GIR_Coverage, 11727, |
| 111009 | GIR_EraseRootFromParent_Done, |
| 111010 | // Label 5610: @353644 |
| 111011 | GIM_Try, /*On fail goto*//*Label 5611*/ GIMT_Encode4(353779), // Rule ID 11728 // |
| 111012 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111014 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111015 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111016 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111017 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111018 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111019 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111020 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111021 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111022 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111023 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111024 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111025 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111026 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111027 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111028 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111029 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111030 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111031 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111032 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111033 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111042 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111043 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111045 | GIR_RootConstrainSelectedInstOperands, |
| 111046 | // GIR_Coverage, 11728, |
| 111047 | GIR_EraseRootFromParent_Done, |
| 111048 | // Label 5611: @353779 |
| 111049 | GIM_Try, /*On fail goto*//*Label 5612*/ GIMT_Encode4(353914), // Rule ID 11729 // |
| 111050 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111051 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111052 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111053 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111054 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111055 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111056 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111057 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111058 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111059 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111060 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111061 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111062 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111063 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111064 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111065 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111066 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111067 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111068 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111069 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111070 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111071 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111083 | GIR_RootConstrainSelectedInstOperands, |
| 111084 | // GIR_Coverage, 11729, |
| 111085 | GIR_EraseRootFromParent_Done, |
| 111086 | // Label 5612: @353914 |
| 111087 | GIM_Try, /*On fail goto*//*Label 5613*/ GIMT_Encode4(354049), // Rule ID 11730 // |
| 111088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111091 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111092 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111093 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111094 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111095 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111096 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111097 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111098 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111099 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111100 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111101 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111102 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111103 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111104 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111105 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111106 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111107 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111108 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111109 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111121 | GIR_RootConstrainSelectedInstOperands, |
| 111122 | // GIR_Coverage, 11730, |
| 111123 | GIR_EraseRootFromParent_Done, |
| 111124 | // Label 5613: @354049 |
| 111125 | GIM_Try, /*On fail goto*//*Label 5614*/ GIMT_Encode4(354184), // Rule ID 11772 // |
| 111126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111128 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111129 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111130 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111131 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111132 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111133 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111134 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111135 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111136 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111137 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111138 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111139 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111140 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111141 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111142 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111143 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111144 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111145 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111146 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111147 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111159 | GIR_RootConstrainSelectedInstOperands, |
| 111160 | // GIR_Coverage, 11772, |
| 111161 | GIR_EraseRootFromParent_Done, |
| 111162 | // Label 5614: @354184 |
| 111163 | GIM_Try, /*On fail goto*//*Label 5615*/ GIMT_Encode4(354319), // Rule ID 11773 // |
| 111164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111166 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111167 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111168 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111169 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111170 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111171 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111172 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111173 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111174 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111175 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111176 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111177 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111178 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111179 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111180 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111181 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111182 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111183 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111184 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111185 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111194 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111197 | GIR_RootConstrainSelectedInstOperands, |
| 111198 | // GIR_Coverage, 11773, |
| 111199 | GIR_EraseRootFromParent_Done, |
| 111200 | // Label 5615: @354319 |
| 111201 | GIM_Try, /*On fail goto*//*Label 5616*/ GIMT_Encode4(354454), // Rule ID 11774 // |
| 111202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111203 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111204 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111205 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111206 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111207 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111208 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111209 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111210 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111211 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111212 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111213 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111214 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111215 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111216 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111217 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111218 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111219 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111220 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111221 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111222 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111223 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111233 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111235 | GIR_RootConstrainSelectedInstOperands, |
| 111236 | // GIR_Coverage, 11774, |
| 111237 | GIR_EraseRootFromParent_Done, |
| 111238 | // Label 5616: @354454 |
| 111239 | GIM_Try, /*On fail goto*//*Label 5617*/ GIMT_Encode4(354589), // Rule ID 11775 // |
| 111240 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111242 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111243 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111244 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111245 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111246 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111247 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111248 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111249 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111250 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111251 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111252 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111253 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111254 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111255 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111256 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111257 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111258 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111259 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111260 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111261 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111273 | GIR_RootConstrainSelectedInstOperands, |
| 111274 | // GIR_Coverage, 11775, |
| 111275 | GIR_EraseRootFromParent_Done, |
| 111276 | // Label 5617: @354589 |
| 111277 | GIM_Try, /*On fail goto*//*Label 5618*/ GIMT_Encode4(354724), // Rule ID 11712 // |
| 111278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111280 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111281 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111282 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111283 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111284 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111285 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111286 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111287 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111288 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111289 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111290 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111291 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111292 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111293 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111294 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111295 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111296 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111297 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111298 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111299 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111311 | GIR_RootConstrainSelectedInstOperands, |
| 111312 | // GIR_Coverage, 11712, |
| 111313 | GIR_EraseRootFromParent_Done, |
| 111314 | // Label 5618: @354724 |
| 111315 | GIM_Try, /*On fail goto*//*Label 5619*/ GIMT_Encode4(354859), // Rule ID 11713 // |
| 111316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111322 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111323 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111324 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111325 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111326 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111327 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111328 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111329 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111330 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111332 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111333 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111334 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111335 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111336 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111337 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 111343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 111344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111349 | GIR_RootConstrainSelectedInstOperands, |
| 111350 | // GIR_Coverage, 11713, |
| 111351 | GIR_EraseRootFromParent_Done, |
| 111352 | // Label 5619: @354859 |
| 111353 | GIM_Try, /*On fail goto*//*Label 5620*/ GIMT_Encode4(354994), // Rule ID 11714 // |
| 111354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111355 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111356 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111357 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111358 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111359 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111360 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111361 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111362 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111363 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111364 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111365 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111366 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111367 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111368 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111369 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111370 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111371 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111372 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111373 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111374 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111375 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111385 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111387 | GIR_RootConstrainSelectedInstOperands, |
| 111388 | // GIR_Coverage, 11714, |
| 111389 | GIR_EraseRootFromParent_Done, |
| 111390 | // Label 5620: @354994 |
| 111391 | GIM_Try, /*On fail goto*//*Label 5621*/ GIMT_Encode4(355129), // Rule ID 11715 // |
| 111392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111393 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111394 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111395 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111396 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111397 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111398 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 111399 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111400 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111401 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111402 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111403 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111404 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111405 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111406 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111407 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111408 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111409 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111410 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111411 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111412 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111413 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 111417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 111418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 111421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 111422 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111423 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111425 | GIR_RootConstrainSelectedInstOperands, |
| 111426 | // GIR_Coverage, 11715, |
| 111427 | GIR_EraseRootFromParent_Done, |
| 111428 | // Label 5621: @355129 |
| 111429 | GIM_Try, /*On fail goto*//*Label 5622*/ GIMT_Encode4(355264), // Rule ID 11783 // |
| 111430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111431 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111432 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111433 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111434 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111435 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111436 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111437 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111438 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111439 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111440 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111441 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111442 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111443 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111444 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111445 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111446 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111447 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111448 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111449 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111450 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111451 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111460 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111463 | GIR_RootConstrainSelectedInstOperands, |
| 111464 | // GIR_Coverage, 11783, |
| 111465 | GIR_EraseRootFromParent_Done, |
| 111466 | // Label 5622: @355264 |
| 111467 | GIM_Try, /*On fail goto*//*Label 5623*/ GIMT_Encode4(355399), // Rule ID 11784 // |
| 111468 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111470 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111471 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111472 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111473 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111474 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111475 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111476 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111477 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111478 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111479 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111480 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111481 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111482 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111483 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111484 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111485 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111486 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111487 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111488 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111489 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111501 | GIR_RootConstrainSelectedInstOperands, |
| 111502 | // GIR_Coverage, 11784, |
| 111503 | GIR_EraseRootFromParent_Done, |
| 111504 | // Label 5623: @355399 |
| 111505 | GIM_Try, /*On fail goto*//*Label 5624*/ GIMT_Encode4(355534), // Rule ID 11785 // |
| 111506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111511 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111512 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111514 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111515 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111516 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111517 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111518 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111519 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111520 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111521 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111522 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111523 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111524 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111525 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111526 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111527 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111539 | GIR_RootConstrainSelectedInstOperands, |
| 111540 | // GIR_Coverage, 11785, |
| 111541 | GIR_EraseRootFromParent_Done, |
| 111542 | // Label 5624: @355534 |
| 111543 | GIM_Try, /*On fail goto*//*Label 5625*/ GIMT_Encode4(355669), // Rule ID 11786 // |
| 111544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111545 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111546 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111547 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111548 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111549 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111550 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111551 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111552 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111553 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111554 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111555 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111556 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111557 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111558 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111559 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111560 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111561 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111562 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111563 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111564 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111565 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111576 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111577 | GIR_RootConstrainSelectedInstOperands, |
| 111578 | // GIR_Coverage, 11786, |
| 111579 | GIR_EraseRootFromParent_Done, |
| 111580 | // Label 5625: @355669 |
| 111581 | GIM_Try, /*On fail goto*//*Label 5626*/ GIMT_Encode4(355804), // Rule ID 11723 // |
| 111582 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111583 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111584 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111585 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111586 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111587 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111588 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111589 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111590 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111591 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111592 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111593 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111594 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111595 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111596 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111597 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111598 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111599 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111600 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111601 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111602 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111603 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111605 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111612 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111613 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111615 | GIR_RootConstrainSelectedInstOperands, |
| 111616 | // GIR_Coverage, 11723, |
| 111617 | GIR_EraseRootFromParent_Done, |
| 111618 | // Label 5626: @355804 |
| 111619 | GIM_Try, /*On fail goto*//*Label 5627*/ GIMT_Encode4(355939), // Rule ID 11724 // |
| 111620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111623 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111626 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111627 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111628 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111629 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111630 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111631 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111632 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111633 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111634 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111635 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111637 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111638 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111639 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111640 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111641 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111653 | GIR_RootConstrainSelectedInstOperands, |
| 111654 | // GIR_Coverage, 11724, |
| 111655 | GIR_EraseRootFromParent_Done, |
| 111656 | // Label 5627: @355939 |
| 111657 | GIM_Try, /*On fail goto*//*Label 5628*/ GIMT_Encode4(356074), // Rule ID 11725 // |
| 111658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111659 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111660 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111661 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111662 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111663 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111664 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111665 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111666 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111667 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111668 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111669 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111670 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111671 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111672 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111673 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111674 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111675 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111676 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111677 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111678 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111679 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111690 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111691 | GIR_RootConstrainSelectedInstOperands, |
| 111692 | // GIR_Coverage, 11725, |
| 111693 | GIR_EraseRootFromParent_Done, |
| 111694 | // Label 5628: @356074 |
| 111695 | GIM_Try, /*On fail goto*//*Label 5629*/ GIMT_Encode4(356209), // Rule ID 11726 // |
| 111696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111697 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111698 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111699 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111700 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111701 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111702 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111703 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 111704 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111705 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111706 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111707 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111708 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111709 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111710 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111711 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111712 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111713 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111714 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111715 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111716 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111717 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111726 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111729 | GIR_RootConstrainSelectedInstOperands, |
| 111730 | // GIR_Coverage, 11726, |
| 111731 | GIR_EraseRootFromParent_Done, |
| 111732 | // Label 5629: @356209 |
| 111733 | GIM_Try, /*On fail goto*//*Label 5630*/ GIMT_Encode4(356344), // Rule ID 11768 // |
| 111734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111735 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111736 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111737 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111738 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111739 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111740 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111741 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111742 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111743 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111744 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111745 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111746 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111747 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111748 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111749 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111750 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111751 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111752 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111753 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111754 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111755 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111764 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111767 | GIR_RootConstrainSelectedInstOperands, |
| 111768 | // GIR_Coverage, 11768, |
| 111769 | GIR_EraseRootFromParent_Done, |
| 111770 | // Label 5630: @356344 |
| 111771 | GIM_Try, /*On fail goto*//*Label 5631*/ GIMT_Encode4(356479), // Rule ID 11769 // |
| 111772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111777 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111778 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111779 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111780 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111781 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111782 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111783 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111784 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111785 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111786 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111787 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111788 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111789 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111790 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111791 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111792 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111793 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111804 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111805 | GIR_RootConstrainSelectedInstOperands, |
| 111806 | // GIR_Coverage, 11769, |
| 111807 | GIR_EraseRootFromParent_Done, |
| 111808 | // Label 5631: @356479 |
| 111809 | GIM_Try, /*On fail goto*//*Label 5632*/ GIMT_Encode4(356614), // Rule ID 11770 // |
| 111810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111812 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111813 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111814 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111815 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111816 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111817 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111818 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111819 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111820 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111821 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111822 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111823 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111824 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111825 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111826 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111827 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111828 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111829 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111830 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111831 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111840 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111841 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111843 | GIR_RootConstrainSelectedInstOperands, |
| 111844 | // GIR_Coverage, 11770, |
| 111845 | GIR_EraseRootFromParent_Done, |
| 111846 | // Label 5632: @356614 |
| 111847 | GIM_Try, /*On fail goto*//*Label 5633*/ GIMT_Encode4(356749), // Rule ID 11771 // |
| 111848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111850 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111851 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111852 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111853 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111854 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111855 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111856 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111857 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111858 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111859 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111860 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111861 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111862 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111863 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111864 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111865 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111866 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111867 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111868 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111869 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111881 | GIR_RootConstrainSelectedInstOperands, |
| 111882 | // GIR_Coverage, 11771, |
| 111883 | GIR_EraseRootFromParent_Done, |
| 111884 | // Label 5633: @356749 |
| 111885 | GIM_Try, /*On fail goto*//*Label 5634*/ GIMT_Encode4(356884), // Rule ID 11708 // |
| 111886 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111887 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111888 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111889 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111890 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111891 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111892 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111893 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111894 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111895 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111896 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111897 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111898 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111899 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111900 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111901 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111902 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111903 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111904 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111905 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111906 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111907 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111917 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111918 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111919 | GIR_RootConstrainSelectedInstOperands, |
| 111920 | // GIR_Coverage, 11708, |
| 111921 | GIR_EraseRootFromParent_Done, |
| 111922 | // Label 5634: @356884 |
| 111923 | GIM_Try, /*On fail goto*//*Label 5635*/ GIMT_Encode4(357019), // Rule ID 11709 // |
| 111924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111926 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111927 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111928 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111929 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111930 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111931 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111932 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111933 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111934 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111935 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111936 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111937 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111938 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111939 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111940 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111941 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111942 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111943 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111944 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111945 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111947 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 111949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 111950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 111951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 111952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111954 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111955 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111956 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111957 | GIR_RootConstrainSelectedInstOperands, |
| 111958 | // GIR_Coverage, 11709, |
| 111959 | GIR_EraseRootFromParent_Done, |
| 111960 | // Label 5635: @357019 |
| 111961 | GIM_Try, /*On fail goto*//*Label 5636*/ GIMT_Encode4(357154), // Rule ID 11710 // |
| 111962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 111963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 111964 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 111965 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 111966 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 111967 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 111968 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 111969 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 111970 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 111971 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 111972 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 111973 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 111974 | // MIs[3] VOP3Mods:src0:src0_mods |
| 111975 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 111976 | // MIs[3] VOP3Mods:src1:src1_mods |
| 111977 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 111978 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 111979 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 111980 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 111981 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 111982 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 111983 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 111984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 111985 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 111986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 111987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 111988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 111989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 111990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 111991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 111992 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 111995 | GIR_RootConstrainSelectedInstOperands, |
| 111996 | // GIR_Coverage, 11710, |
| 111997 | GIR_EraseRootFromParent_Done, |
| 111998 | // Label 5636: @357154 |
| 111999 | GIM_Try, /*On fail goto*//*Label 5637*/ GIMT_Encode4(357289), // Rule ID 11711 // |
| 112000 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112005 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112006 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 112007 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112008 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112009 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112010 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 112011 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112012 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112013 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 112014 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112015 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 112016 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112017 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112018 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112019 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112020 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112021 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112033 | GIR_RootConstrainSelectedInstOperands, |
| 112034 | // GIR_Coverage, 11711, |
| 112035 | GIR_EraseRootFromParent_Done, |
| 112036 | // Label 5637: @357289 |
| 112037 | GIM_Try, /*On fail goto*//*Label 5638*/ GIMT_Encode4(357424), // Rule ID 11717 // |
| 112038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112039 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112040 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112041 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112042 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112043 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112044 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112045 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112046 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112047 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112048 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112049 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112050 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112051 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112052 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112053 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112054 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112055 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112056 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112057 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112058 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112059 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112070 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112071 | GIR_RootConstrainSelectedInstOperands, |
| 112072 | // GIR_Coverage, 11717, |
| 112073 | GIR_EraseRootFromParent_Done, |
| 112074 | // Label 5638: @357424 |
| 112075 | GIM_Try, /*On fail goto*//*Label 5639*/ GIMT_Encode4(357559), // Rule ID 11718 // |
| 112076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112077 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112078 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112079 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112080 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112081 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112082 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112083 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112084 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112085 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112086 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112087 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112088 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112089 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112090 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112091 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112092 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112093 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112094 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112095 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112096 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112097 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112106 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112109 | GIR_RootConstrainSelectedInstOperands, |
| 112110 | // GIR_Coverage, 11718, |
| 112111 | GIR_EraseRootFromParent_Done, |
| 112112 | // Label 5639: @357559 |
| 112113 | GIM_Try, /*On fail goto*//*Label 5640*/ GIMT_Encode4(357694), // Rule ID 11721 // |
| 112114 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112115 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112116 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112117 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112118 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112119 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112120 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112121 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112122 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112123 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112124 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112125 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112126 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112127 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112128 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112129 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112130 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112131 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112132 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112133 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112134 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112135 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112147 | GIR_RootConstrainSelectedInstOperands, |
| 112148 | // GIR_Coverage, 11721, |
| 112149 | GIR_EraseRootFromParent_Done, |
| 112150 | // Label 5640: @357694 |
| 112151 | GIM_Try, /*On fail goto*//*Label 5641*/ GIMT_Encode4(357829), // Rule ID 11722 // |
| 112152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112155 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112156 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112157 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112158 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112159 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112160 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112161 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112162 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112163 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112164 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112165 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112166 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112167 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112169 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112170 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112171 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112172 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112173 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112185 | GIR_RootConstrainSelectedInstOperands, |
| 112186 | // GIR_Coverage, 11722, |
| 112187 | GIR_EraseRootFromParent_Done, |
| 112188 | // Label 5641: @357829 |
| 112189 | GIM_Try, /*On fail goto*//*Label 5642*/ GIMT_Encode4(357964), // Rule ID 11702 // |
| 112190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112191 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112192 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112193 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112194 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112195 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112196 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112197 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112198 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112199 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112200 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112201 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112202 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112203 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112204 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112205 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112206 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112207 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112208 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112209 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112210 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112211 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112221 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112222 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112223 | GIR_RootConstrainSelectedInstOperands, |
| 112224 | // GIR_Coverage, 11702, |
| 112225 | GIR_EraseRootFromParent_Done, |
| 112226 | // Label 5642: @357964 |
| 112227 | GIM_Try, /*On fail goto*//*Label 5643*/ GIMT_Encode4(358099), // Rule ID 11703 // |
| 112228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112230 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112231 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112232 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112233 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112234 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112235 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112236 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112237 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112238 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112239 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112240 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112241 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112242 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112243 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112244 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112245 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112246 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112247 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112248 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112249 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112258 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112259 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112260 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112261 | GIR_RootConstrainSelectedInstOperands, |
| 112262 | // GIR_Coverage, 11703, |
| 112263 | GIR_EraseRootFromParent_Done, |
| 112264 | // Label 5643: @358099 |
| 112265 | GIM_Try, /*On fail goto*//*Label 5644*/ GIMT_Encode4(358234), // Rule ID 11706 // |
| 112266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112267 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112268 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112269 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112270 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112271 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112272 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112273 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112274 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112275 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112276 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112277 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112278 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112279 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112280 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112281 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112282 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112283 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112284 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112285 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112286 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112287 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112289 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112291 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112296 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112297 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112299 | GIR_RootConstrainSelectedInstOperands, |
| 112300 | // GIR_Coverage, 11706, |
| 112301 | GIR_EraseRootFromParent_Done, |
| 112302 | // Label 5644: @358234 |
| 112303 | GIM_Try, /*On fail goto*//*Label 5645*/ GIMT_Encode4(358369), // Rule ID 11707 // |
| 112304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112307 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112309 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112311 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112313 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112314 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112315 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112316 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112317 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112318 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112319 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112320 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112321 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112322 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112323 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112324 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112325 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112337 | GIR_RootConstrainSelectedInstOperands, |
| 112338 | // GIR_Coverage, 11707, |
| 112339 | GIR_EraseRootFromParent_Done, |
| 112340 | // Label 5645: @358369 |
| 112341 | GIM_Try, /*On fail goto*//*Label 5646*/ GIMT_Encode4(358504), // Rule ID 7367 // |
| 112342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112343 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112344 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112345 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112346 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112347 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112348 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112349 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112350 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112351 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112352 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112353 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112354 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112355 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112356 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112357 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112358 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112359 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112360 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112361 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112362 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112363 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112375 | GIR_RootConstrainSelectedInstOperands, |
| 112376 | // GIR_Coverage, 7367, |
| 112377 | GIR_EraseRootFromParent_Done, |
| 112378 | // Label 5646: @358504 |
| 112379 | GIM_Try, /*On fail goto*//*Label 5647*/ GIMT_Encode4(358639), // Rule ID 11716 // |
| 112380 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112383 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112385 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112386 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112387 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112388 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112389 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112390 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112391 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112392 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112393 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112394 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112395 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112396 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112397 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112398 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112399 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112400 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112401 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112410 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112413 | GIR_RootConstrainSelectedInstOperands, |
| 112414 | // GIR_Coverage, 11716, |
| 112415 | GIR_EraseRootFromParent_Done, |
| 112416 | // Label 5647: @358639 |
| 112417 | GIM_Try, /*On fail goto*//*Label 5648*/ GIMT_Encode4(358774), // Rule ID 11719 // |
| 112418 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112419 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112420 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112421 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112422 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112423 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112424 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112425 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112426 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112427 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112428 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112429 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112430 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112431 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112432 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112433 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112434 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112435 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112436 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112437 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112438 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112439 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112449 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112450 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112451 | GIR_RootConstrainSelectedInstOperands, |
| 112452 | // GIR_Coverage, 11719, |
| 112453 | GIR_EraseRootFromParent_Done, |
| 112454 | // Label 5648: @358774 |
| 112455 | GIM_Try, /*On fail goto*//*Label 5649*/ GIMT_Encode4(358909), // Rule ID 11720 // |
| 112456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112457 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112458 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112459 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112460 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112461 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112462 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112463 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112464 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112465 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112466 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112467 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112468 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112469 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112470 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112471 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112472 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112473 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112474 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112475 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112476 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112477 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112486 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112487 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112488 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112489 | GIR_RootConstrainSelectedInstOperands, |
| 112490 | // GIR_Coverage, 11720, |
| 112491 | GIR_EraseRootFromParent_Done, |
| 112492 | // Label 5649: @358909 |
| 112493 | GIM_Try, /*On fail goto*//*Label 5650*/ GIMT_Encode4(359044), // Rule ID 7366 // |
| 112494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112495 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112496 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112497 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112498 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112499 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112500 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112501 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112502 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112503 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112504 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112505 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112506 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112507 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112508 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112509 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112510 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112511 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112512 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112513 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112514 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112515 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112524 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112527 | GIR_RootConstrainSelectedInstOperands, |
| 112528 | // GIR_Coverage, 7366, |
| 112529 | GIR_EraseRootFromParent_Done, |
| 112530 | // Label 5650: @359044 |
| 112531 | GIM_Try, /*On fail goto*//*Label 5651*/ GIMT_Encode4(359179), // Rule ID 11701 // |
| 112532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112534 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112535 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112536 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112537 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112538 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112539 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112540 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112541 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112542 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112543 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112544 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112545 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112546 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112547 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112548 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112549 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112550 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112551 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112552 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112553 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112565 | GIR_RootConstrainSelectedInstOperands, |
| 112566 | // GIR_Coverage, 11701, |
| 112567 | GIR_EraseRootFromParent_Done, |
| 112568 | // Label 5651: @359179 |
| 112569 | GIM_Try, /*On fail goto*//*Label 5652*/ GIMT_Encode4(359314), // Rule ID 11704 // |
| 112570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112572 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112573 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112574 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112575 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112576 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112577 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112578 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112579 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112580 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112581 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112582 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112584 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112585 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112586 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112587 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112588 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112589 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112590 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112591 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112601 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112602 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112603 | GIR_RootConstrainSelectedInstOperands, |
| 112604 | // GIR_Coverage, 11704, |
| 112605 | GIR_EraseRootFromParent_Done, |
| 112606 | // Label 5652: @359314 |
| 112607 | GIM_Try, /*On fail goto*//*Label 5653*/ GIMT_Encode4(359449), // Rule ID 11705 // |
| 112608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112610 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112611 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112612 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112613 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112614 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112615 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 112616 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112617 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112618 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112619 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112620 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112622 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112623 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112624 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112625 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112626 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112627 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112628 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112629 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112630 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112631 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112638 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112639 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112641 | GIR_RootConstrainSelectedInstOperands, |
| 112642 | // GIR_Coverage, 11705, |
| 112643 | GIR_EraseRootFromParent_Done, |
| 112644 | // Label 5653: @359449 |
| 112645 | GIM_Try, /*On fail goto*//*Label 5654*/ GIMT_Encode4(359584), // Rule ID 11687 // |
| 112646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112647 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112648 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112649 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112650 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112651 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112652 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112653 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112654 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112655 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112656 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112657 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112658 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112659 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112660 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112661 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112662 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112663 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112664 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112665 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112666 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112667 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112676 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112677 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112679 | GIR_RootConstrainSelectedInstOperands, |
| 112680 | // GIR_Coverage, 11687, |
| 112681 | GIR_EraseRootFromParent_Done, |
| 112682 | // Label 5654: @359584 |
| 112683 | GIM_Try, /*On fail goto*//*Label 5655*/ GIMT_Encode4(359719), // Rule ID 11688 // |
| 112684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112688 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112689 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112690 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112691 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112692 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112693 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112694 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112695 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112696 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112698 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112699 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112701 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112702 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112703 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112704 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112705 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112717 | GIR_RootConstrainSelectedInstOperands, |
| 112718 | // GIR_Coverage, 11688, |
| 112719 | GIR_EraseRootFromParent_Done, |
| 112720 | // Label 5655: @359719 |
| 112721 | GIM_Try, /*On fail goto*//*Label 5656*/ GIMT_Encode4(359854), // Rule ID 11691 // |
| 112722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112724 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112725 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112726 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112727 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112728 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112729 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112730 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112731 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112732 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112733 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112734 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112735 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112736 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112737 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112738 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112739 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112740 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112741 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112742 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112743 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112745 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112753 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112754 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112755 | GIR_RootConstrainSelectedInstOperands, |
| 112756 | // GIR_Coverage, 11691, |
| 112757 | GIR_EraseRootFromParent_Done, |
| 112758 | // Label 5656: @359854 |
| 112759 | GIM_Try, /*On fail goto*//*Label 5657*/ GIMT_Encode4(359989), // Rule ID 11692 // |
| 112760 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112762 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112763 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112764 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112765 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112766 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112767 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112768 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112769 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112770 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112771 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112772 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112773 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112774 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112775 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112776 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112777 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112778 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112779 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112780 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112781 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112790 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112793 | GIR_RootConstrainSelectedInstOperands, |
| 112794 | // GIR_Coverage, 11692, |
| 112795 | GIR_EraseRootFromParent_Done, |
| 112796 | // Label 5657: @359989 |
| 112797 | GIM_Try, /*On fail goto*//*Label 5658*/ GIMT_Encode4(360124), // Rule ID 11672 // |
| 112798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112800 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112801 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112802 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112803 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112804 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112805 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112806 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112807 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112808 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112809 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112810 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112811 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112812 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112813 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112814 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112815 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112816 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112817 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112818 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112819 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112831 | GIR_RootConstrainSelectedInstOperands, |
| 112832 | // GIR_Coverage, 11672, |
| 112833 | GIR_EraseRootFromParent_Done, |
| 112834 | // Label 5658: @360124 |
| 112835 | GIM_Try, /*On fail goto*//*Label 5659*/ GIMT_Encode4(360259), // Rule ID 11673 // |
| 112836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112839 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112841 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112842 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112843 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112844 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112845 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112846 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112847 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112848 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112850 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112851 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112853 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112854 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112855 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112856 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112857 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112869 | GIR_RootConstrainSelectedInstOperands, |
| 112870 | // GIR_Coverage, 11673, |
| 112871 | GIR_EraseRootFromParent_Done, |
| 112872 | // Label 5659: @360259 |
| 112873 | GIM_Try, /*On fail goto*//*Label 5660*/ GIMT_Encode4(360394), // Rule ID 11676 // |
| 112874 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112876 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112877 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112878 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112879 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112880 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112881 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112882 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112883 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112884 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112885 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112886 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112887 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112888 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112889 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112890 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112891 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112892 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112893 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112894 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112895 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112906 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112907 | GIR_RootConstrainSelectedInstOperands, |
| 112908 | // GIR_Coverage, 11676, |
| 112909 | GIR_EraseRootFromParent_Done, |
| 112910 | // Label 5660: @360394 |
| 112911 | GIM_Try, /*On fail goto*//*Label 5661*/ GIMT_Encode4(360529), // Rule ID 11677 // |
| 112912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112914 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112915 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112916 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112917 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112918 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112919 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112920 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112921 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112922 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 112923 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 112924 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112925 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112926 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112927 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112928 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112929 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112930 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112931 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112932 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112933 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 112937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 112938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 112939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 112940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112942 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112943 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112944 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112945 | GIR_RootConstrainSelectedInstOperands, |
| 112946 | // GIR_Coverage, 11677, |
| 112947 | GIR_EraseRootFromParent_Done, |
| 112948 | // Label 5661: @360529 |
| 112949 | GIM_Try, /*On fail goto*//*Label 5662*/ GIMT_Encode4(360664), // Rule ID 7365 // |
| 112950 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112951 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112952 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112953 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112954 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112955 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112956 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112957 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112958 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112959 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112960 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112961 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 112962 | // MIs[3] VOP3Mods:src0:src0_mods |
| 112963 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 112964 | // MIs[3] VOP3Mods:src1:src1_mods |
| 112965 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 112966 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 112967 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 112968 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 112969 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 112970 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 112971 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 112972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 112973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 112974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 112975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 112976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 112977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 112978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 112979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 112980 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 112983 | GIR_RootConstrainSelectedInstOperands, |
| 112984 | // GIR_Coverage, 7365, |
| 112985 | GIR_EraseRootFromParent_Done, |
| 112986 | // Label 5662: @360664 |
| 112987 | GIM_Try, /*On fail goto*//*Label 5663*/ GIMT_Encode4(360799), // Rule ID 11686 // |
| 112988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 112989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 112990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 112991 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 112993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 112994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 112995 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 112996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 112997 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 112998 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 112999 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113000 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113002 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113003 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113004 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113005 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113006 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113007 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113008 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113009 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 113013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 113014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113021 | GIR_RootConstrainSelectedInstOperands, |
| 113022 | // GIR_Coverage, 11686, |
| 113023 | GIR_EraseRootFromParent_Done, |
| 113024 | // Label 5663: @360799 |
| 113025 | GIM_Try, /*On fail goto*//*Label 5664*/ GIMT_Encode4(360934), // Rule ID 11689 // |
| 113026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113028 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113029 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113030 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113031 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113032 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113033 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113034 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113035 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113036 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113037 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113038 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113039 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113040 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113041 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113042 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113043 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113044 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113045 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113046 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113047 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 113053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 113054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113056 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113059 | GIR_RootConstrainSelectedInstOperands, |
| 113060 | // GIR_Coverage, 11689, |
| 113061 | GIR_EraseRootFromParent_Done, |
| 113062 | // Label 5664: @360934 |
| 113063 | GIM_Try, /*On fail goto*//*Label 5665*/ GIMT_Encode4(361069), // Rule ID 11690 // |
| 113064 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113067 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113068 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113069 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113070 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113071 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113072 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113073 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113074 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113075 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113076 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113077 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113078 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113079 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113080 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113081 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113082 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113083 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113084 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113085 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 113091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 113092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113097 | GIR_RootConstrainSelectedInstOperands, |
| 113098 | // GIR_Coverage, 11690, |
| 113099 | GIR_EraseRootFromParent_Done, |
| 113100 | // Label 5665: @361069 |
| 113101 | GIM_Try, /*On fail goto*//*Label 5666*/ GIMT_Encode4(361204), // Rule ID 7364 // |
| 113102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113104 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113105 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113106 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113107 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113108 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113109 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113110 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113111 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113112 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113113 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113114 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113116 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113117 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113118 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113119 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113120 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113121 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113122 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113123 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 113127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 113128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113135 | GIR_RootConstrainSelectedInstOperands, |
| 113136 | // GIR_Coverage, 7364, |
| 113137 | GIR_EraseRootFromParent_Done, |
| 113138 | // Label 5666: @361204 |
| 113139 | GIM_Try, /*On fail goto*//*Label 5667*/ GIMT_Encode4(361339), // Rule ID 11671 // |
| 113140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113141 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113142 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113143 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113144 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113145 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113146 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113147 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113148 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113149 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113150 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113151 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113152 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113153 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113154 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113155 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113156 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113157 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113158 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113159 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113160 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113161 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 113165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 113166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113170 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113171 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113172 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113173 | GIR_RootConstrainSelectedInstOperands, |
| 113174 | // GIR_Coverage, 11671, |
| 113175 | GIR_EraseRootFromParent_Done, |
| 113176 | // Label 5667: @361339 |
| 113177 | GIM_Try, /*On fail goto*//*Label 5668*/ GIMT_Encode4(361474), // Rule ID 11674 // |
| 113178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113182 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113183 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113184 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113185 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113186 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113187 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113188 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113189 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113190 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113191 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113192 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113193 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113194 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113195 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113196 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113197 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113198 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113199 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113203 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 113205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 113206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113211 | GIR_RootConstrainSelectedInstOperands, |
| 113212 | // GIR_Coverage, 11674, |
| 113213 | GIR_EraseRootFromParent_Done, |
| 113214 | // Label 5668: @361474 |
| 113215 | GIM_Try, /*On fail goto*//*Label 5669*/ GIMT_Encode4(361609), // Rule ID 11675 // |
| 113216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113218 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113219 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113220 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113221 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113222 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 113223 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113224 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113225 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113226 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 113227 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113228 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113229 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 113230 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113231 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 113232 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113233 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113234 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113235 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113236 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113237 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 113243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 113244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113249 | GIR_RootConstrainSelectedInstOperands, |
| 113250 | // GIR_Coverage, 11675, |
| 113251 | GIR_EraseRootFromParent_Done, |
| 113252 | // Label 5669: @361609 |
| 113253 | GIM_Try, /*On fail goto*//*Label 5670*/ GIMT_Encode4(361744), // Rule ID 11757 // |
| 113254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113256 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113257 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113258 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113259 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113260 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113261 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113262 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113263 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113264 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113265 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113266 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113268 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113269 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113270 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113271 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113272 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113273 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113274 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113275 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113285 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113286 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113287 | GIR_RootConstrainSelectedInstOperands, |
| 113288 | // GIR_Coverage, 11757, |
| 113289 | GIR_EraseRootFromParent_Done, |
| 113290 | // Label 5670: @361744 |
| 113291 | GIM_Try, /*On fail goto*//*Label 5671*/ GIMT_Encode4(361879), // Rule ID 11758 // |
| 113292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113294 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113295 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113296 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113297 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113298 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113299 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113300 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113301 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113302 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113303 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113304 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113305 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113306 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113307 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113308 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113309 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113310 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113311 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113312 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113313 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113323 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113324 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113325 | GIR_RootConstrainSelectedInstOperands, |
| 113326 | // GIR_Coverage, 11758, |
| 113327 | GIR_EraseRootFromParent_Done, |
| 113328 | // Label 5671: @361879 |
| 113329 | GIM_Try, /*On fail goto*//*Label 5672*/ GIMT_Encode4(362014), // Rule ID 11759 // |
| 113330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113331 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113332 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113333 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113334 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113335 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113336 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113337 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113338 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113339 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113340 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113341 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113342 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113343 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113344 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113345 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113346 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113347 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113348 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113349 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113350 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113351 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113360 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113363 | GIR_RootConstrainSelectedInstOperands, |
| 113364 | // GIR_Coverage, 11759, |
| 113365 | GIR_EraseRootFromParent_Done, |
| 113366 | // Label 5672: @362014 |
| 113367 | GIM_Try, /*On fail goto*//*Label 5673*/ GIMT_Encode4(362149), // Rule ID 11760 // |
| 113368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113373 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113375 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113376 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113377 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113378 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113379 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113380 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113382 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113383 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113384 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113385 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113386 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113387 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113388 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113389 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113401 | GIR_RootConstrainSelectedInstOperands, |
| 113402 | // GIR_Coverage, 11760, |
| 113403 | GIR_EraseRootFromParent_Done, |
| 113404 | // Label 5673: @362149 |
| 113405 | GIM_Try, /*On fail goto*//*Label 5674*/ GIMT_Encode4(362284), // Rule ID 11697 // |
| 113406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113407 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113408 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113409 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113410 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113411 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113412 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113413 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113414 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113415 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113416 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113417 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113418 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113419 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113420 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113421 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113422 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113423 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113424 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113425 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113426 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113427 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113439 | GIR_RootConstrainSelectedInstOperands, |
| 113440 | // GIR_Coverage, 11697, |
| 113441 | GIR_EraseRootFromParent_Done, |
| 113442 | // Label 5674: @362284 |
| 113443 | GIM_Try, /*On fail goto*//*Label 5675*/ GIMT_Encode4(362419), // Rule ID 11698 // |
| 113444 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113449 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113450 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113451 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113452 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113453 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113454 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113455 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113456 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113458 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113459 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113460 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113461 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113462 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113463 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113464 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113465 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113466 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113467 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113474 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113477 | GIR_RootConstrainSelectedInstOperands, |
| 113478 | // GIR_Coverage, 11698, |
| 113479 | GIR_EraseRootFromParent_Done, |
| 113480 | // Label 5675: @362419 |
| 113481 | GIM_Try, /*On fail goto*//*Label 5676*/ GIMT_Encode4(362554), // Rule ID 11699 // |
| 113482 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113483 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113484 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113485 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113486 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113487 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113488 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113489 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113490 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113491 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113492 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113493 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113494 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113495 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113496 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113497 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113498 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113499 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113500 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113501 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113502 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113503 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113512 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113513 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113515 | GIR_RootConstrainSelectedInstOperands, |
| 113516 | // GIR_Coverage, 11699, |
| 113517 | GIR_EraseRootFromParent_Done, |
| 113518 | // Label 5676: @362554 |
| 113519 | GIM_Try, /*On fail goto*//*Label 5677*/ GIMT_Encode4(362689), // Rule ID 11700 // |
| 113520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113522 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113523 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113524 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113525 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113526 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113527 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113528 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113530 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113531 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113532 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113534 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113535 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113536 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113537 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113538 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113539 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113540 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113541 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113553 | GIR_RootConstrainSelectedInstOperands, |
| 113554 | // GIR_Coverage, 11700, |
| 113555 | GIR_EraseRootFromParent_Done, |
| 113556 | // Label 5677: @362689 |
| 113557 | GIM_Try, /*On fail goto*//*Label 5678*/ GIMT_Encode4(362824), // Rule ID 11742 // |
| 113558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113559 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113560 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113561 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113562 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113563 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113564 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113565 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113566 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113567 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113568 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113569 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113570 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113571 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113572 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113573 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113574 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113575 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113576 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113577 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113578 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113579 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113580 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113581 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113589 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113591 | GIR_RootConstrainSelectedInstOperands, |
| 113592 | // GIR_Coverage, 11742, |
| 113593 | GIR_EraseRootFromParent_Done, |
| 113594 | // Label 5678: @362824 |
| 113595 | GIM_Try, /*On fail goto*//*Label 5679*/ GIMT_Encode4(362959), // Rule ID 11743 // |
| 113596 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113597 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113598 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113599 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113600 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113601 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113602 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113603 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113604 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113605 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113606 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113607 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113608 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113609 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113610 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113611 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113612 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113613 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113614 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113615 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113616 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113617 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113629 | GIR_RootConstrainSelectedInstOperands, |
| 113630 | // GIR_Coverage, 11743, |
| 113631 | GIR_EraseRootFromParent_Done, |
| 113632 | // Label 5679: @362959 |
| 113633 | GIM_Try, /*On fail goto*//*Label 5680*/ GIMT_Encode4(363094), // Rule ID 11744 // |
| 113634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113639 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113641 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113644 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113645 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113646 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113648 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113649 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113650 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113651 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113652 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113653 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113654 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113655 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113656 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113657 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113665 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113666 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113667 | GIR_RootConstrainSelectedInstOperands, |
| 113668 | // GIR_Coverage, 11744, |
| 113669 | GIR_EraseRootFromParent_Done, |
| 113670 | // Label 5680: @363094 |
| 113671 | GIM_Try, /*On fail goto*//*Label 5681*/ GIMT_Encode4(363229), // Rule ID 11745 // |
| 113672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113674 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113675 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113676 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113677 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113678 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113679 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113680 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113681 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113682 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113683 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113684 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113685 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113686 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113687 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113688 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113689 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113690 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113691 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113692 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113693 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113702 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113705 | GIR_RootConstrainSelectedInstOperands, |
| 113706 | // GIR_Coverage, 11745, |
| 113707 | GIR_EraseRootFromParent_Done, |
| 113708 | // Label 5681: @363229 |
| 113709 | GIM_Try, /*On fail goto*//*Label 5682*/ GIMT_Encode4(363364), // Rule ID 11682 // |
| 113710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113715 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113716 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113717 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113718 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113719 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113720 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113721 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113722 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113723 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113724 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113725 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113726 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113727 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113728 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113729 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113730 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113731 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113740 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113741 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113743 | GIR_RootConstrainSelectedInstOperands, |
| 113744 | // GIR_Coverage, 11682, |
| 113745 | GIR_EraseRootFromParent_Done, |
| 113746 | // Label 5682: @363364 |
| 113747 | GIM_Try, /*On fail goto*//*Label 5683*/ GIMT_Encode4(363499), // Rule ID 11683 // |
| 113748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113751 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113752 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113753 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113754 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113755 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113756 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113757 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113758 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113759 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113760 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113761 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113762 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113763 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113764 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113765 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113766 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113767 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113768 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113769 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 113775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 113776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113781 | GIR_RootConstrainSelectedInstOperands, |
| 113782 | // GIR_Coverage, 11683, |
| 113783 | GIR_EraseRootFromParent_Done, |
| 113784 | // Label 5683: @363499 |
| 113785 | GIM_Try, /*On fail goto*//*Label 5684*/ GIMT_Encode4(363634), // Rule ID 11684 // |
| 113786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113788 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113789 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113790 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113791 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113792 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113793 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113794 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113795 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113796 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113797 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113798 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113800 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113801 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113802 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113803 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113804 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113805 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113806 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113807 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113817 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113819 | GIR_RootConstrainSelectedInstOperands, |
| 113820 | // GIR_Coverage, 11684, |
| 113821 | GIR_EraseRootFromParent_Done, |
| 113822 | // Label 5684: @363634 |
| 113823 | GIM_Try, /*On fail goto*//*Label 5685*/ GIMT_Encode4(363769), // Rule ID 11685 // |
| 113824 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113826 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113827 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113828 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113829 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113830 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 113831 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 113832 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113833 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113834 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113835 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113836 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113838 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113839 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113840 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113841 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113842 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113843 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113844 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113845 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 113849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 113850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 113853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 113854 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113857 | GIR_RootConstrainSelectedInstOperands, |
| 113858 | // GIR_Coverage, 11685, |
| 113859 | GIR_EraseRootFromParent_Done, |
| 113860 | // Label 5685: @363769 |
| 113861 | GIM_Try, /*On fail goto*//*Label 5686*/ GIMT_Encode4(363904), // Rule ID 11753 // |
| 113862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113864 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113865 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113866 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113867 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113868 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 113869 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113870 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113871 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113872 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113873 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113874 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113875 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113876 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113877 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113878 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113879 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113880 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113881 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113882 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113883 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 113887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 113888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113892 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113893 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113895 | GIR_RootConstrainSelectedInstOperands, |
| 113896 | // GIR_Coverage, 11753, |
| 113897 | GIR_EraseRootFromParent_Done, |
| 113898 | // Label 5686: @363904 |
| 113899 | GIM_Try, /*On fail goto*//*Label 5687*/ GIMT_Encode4(364039), // Rule ID 11754 // |
| 113900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113903 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113904 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113905 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113906 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 113907 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113908 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113909 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113910 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113911 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113912 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113914 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113915 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113916 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113917 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113918 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113919 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113920 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113921 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 113925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 113926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 113927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 113928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113933 | GIR_RootConstrainSelectedInstOperands, |
| 113934 | // GIR_Coverage, 11754, |
| 113935 | GIR_EraseRootFromParent_Done, |
| 113936 | // Label 5687: @364039 |
| 113937 | GIM_Try, /*On fail goto*//*Label 5688*/ GIMT_Encode4(364174), // Rule ID 11755 // |
| 113938 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113939 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113940 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113941 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113942 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113943 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113944 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 113945 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113946 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113947 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113948 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113949 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113950 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113951 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113952 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113953 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113955 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113956 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113957 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113958 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113959 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 113962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 113963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 113964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 113965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 113966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 113967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 113968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113970 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 113971 | GIR_RootConstrainSelectedInstOperands, |
| 113972 | // GIR_Coverage, 11755, |
| 113973 | GIR_EraseRootFromParent_Done, |
| 113974 | // Label 5688: @364174 |
| 113975 | GIM_Try, /*On fail goto*//*Label 5689*/ GIMT_Encode4(364309), // Rule ID 11756 // |
| 113976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 113977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 113978 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 113979 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 113980 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 113981 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 113982 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 113983 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 113984 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 113985 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 113986 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 113987 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 113988 | // MIs[3] VOP3Mods:src1:src1_mods |
| 113989 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 113990 | // MIs[3] VOP3Mods:src0:src0_mods |
| 113991 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 113992 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 113993 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 113994 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 113995 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 113996 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 113997 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 113998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 113999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114009 | GIR_RootConstrainSelectedInstOperands, |
| 114010 | // GIR_Coverage, 11756, |
| 114011 | GIR_EraseRootFromParent_Done, |
| 114012 | // Label 5689: @364309 |
| 114013 | GIM_Try, /*On fail goto*//*Label 5690*/ GIMT_Encode4(364444), // Rule ID 11693 // |
| 114014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114015 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114016 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114017 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114018 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114019 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114020 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114021 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114022 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114023 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114024 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114025 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114026 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114027 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114028 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114029 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114030 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114031 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114032 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114033 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114034 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114035 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114044 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114047 | GIR_RootConstrainSelectedInstOperands, |
| 114048 | // GIR_Coverage, 11693, |
| 114049 | GIR_EraseRootFromParent_Done, |
| 114050 | // Label 5690: @364444 |
| 114051 | GIM_Try, /*On fail goto*//*Label 5691*/ GIMT_Encode4(364579), // Rule ID 11694 // |
| 114052 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114055 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114057 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114059 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114060 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114061 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114062 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114063 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114064 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114065 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114066 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114067 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114068 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114069 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114070 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114071 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114072 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114073 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114085 | GIR_RootConstrainSelectedInstOperands, |
| 114086 | // GIR_Coverage, 11694, |
| 114087 | GIR_EraseRootFromParent_Done, |
| 114088 | // Label 5691: @364579 |
| 114089 | GIM_Try, /*On fail goto*//*Label 5692*/ GIMT_Encode4(364714), // Rule ID 11695 // |
| 114090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114092 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114093 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114094 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114095 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114096 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114097 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114098 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114099 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114100 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114101 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114102 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114103 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114104 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114105 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114106 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114107 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114108 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114109 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114110 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114111 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114122 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114123 | GIR_RootConstrainSelectedInstOperands, |
| 114124 | // GIR_Coverage, 11695, |
| 114125 | GIR_EraseRootFromParent_Done, |
| 114126 | // Label 5692: @364714 |
| 114127 | GIM_Try, /*On fail goto*//*Label 5693*/ GIMT_Encode4(364849), // Rule ID 11696 // |
| 114128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114129 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114130 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114131 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114132 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114133 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114134 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114135 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114136 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114137 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114138 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114139 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114140 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114141 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114142 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114143 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114144 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114145 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114146 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114147 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114148 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114149 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114158 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114161 | GIR_RootConstrainSelectedInstOperands, |
| 114162 | // GIR_Coverage, 11696, |
| 114163 | GIR_EraseRootFromParent_Done, |
| 114164 | // Label 5693: @364849 |
| 114165 | GIM_Try, /*On fail goto*//*Label 5694*/ GIMT_Encode4(364984), // Rule ID 11738 // |
| 114166 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114167 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114168 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114169 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114170 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114171 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114172 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114173 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114174 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114175 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114176 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114177 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114178 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114179 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114180 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114181 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114182 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114183 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114184 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114185 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114186 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114187 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114199 | GIR_RootConstrainSelectedInstOperands, |
| 114200 | // GIR_Coverage, 11738, |
| 114201 | GIR_EraseRootFromParent_Done, |
| 114202 | // Label 5694: @364984 |
| 114203 | GIM_Try, /*On fail goto*//*Label 5695*/ GIMT_Encode4(365119), // Rule ID 11739 // |
| 114204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114206 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114207 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114208 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114209 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114210 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114211 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114212 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114213 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114214 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114215 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114216 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114217 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114218 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114219 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114220 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114221 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114222 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114223 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114224 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114225 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114236 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114237 | GIR_RootConstrainSelectedInstOperands, |
| 114238 | // GIR_Coverage, 11739, |
| 114239 | GIR_EraseRootFromParent_Done, |
| 114240 | // Label 5695: @365119 |
| 114241 | GIM_Try, /*On fail goto*//*Label 5696*/ GIMT_Encode4(365254), // Rule ID 11740 // |
| 114242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114244 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114245 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114246 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114247 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114248 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114249 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114250 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114251 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114252 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114253 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114254 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114255 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114256 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114257 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114258 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114259 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114260 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114261 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114262 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114263 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114275 | GIR_RootConstrainSelectedInstOperands, |
| 114276 | // GIR_Coverage, 11740, |
| 114277 | GIR_EraseRootFromParent_Done, |
| 114278 | // Label 5696: @365254 |
| 114279 | GIM_Try, /*On fail goto*//*Label 5697*/ GIMT_Encode4(365389), // Rule ID 11741 // |
| 114280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114283 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114284 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114285 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114286 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114287 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114288 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114289 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114290 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114291 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114292 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114293 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114294 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114295 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114296 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114297 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114298 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114299 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114300 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114301 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114313 | GIR_RootConstrainSelectedInstOperands, |
| 114314 | // GIR_Coverage, 11741, |
| 114315 | GIR_EraseRootFromParent_Done, |
| 114316 | // Label 5697: @365389 |
| 114317 | GIM_Try, /*On fail goto*//*Label 5698*/ GIMT_Encode4(365524), // Rule ID 11678 // |
| 114318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114320 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114321 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114322 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114323 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114324 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114325 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114326 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114327 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114328 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114329 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114330 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114332 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114333 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114334 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114335 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114336 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114337 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114338 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114339 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114349 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114350 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114351 | GIR_RootConstrainSelectedInstOperands, |
| 114352 | // GIR_Coverage, 11678, |
| 114353 | GIR_EraseRootFromParent_Done, |
| 114354 | // Label 5698: @365524 |
| 114355 | GIM_Try, /*On fail goto*//*Label 5699*/ GIMT_Encode4(365659), // Rule ID 11679 // |
| 114356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114358 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114359 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114360 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114361 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114362 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114363 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114364 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114365 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114366 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114367 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114368 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114369 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114370 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114371 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114372 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114373 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114374 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114375 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114376 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114377 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114379 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114386 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114387 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114388 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114389 | GIR_RootConstrainSelectedInstOperands, |
| 114390 | // GIR_Coverage, 11679, |
| 114391 | GIR_EraseRootFromParent_Done, |
| 114392 | // Label 5699: @365659 |
| 114393 | GIM_Try, /*On fail goto*//*Label 5700*/ GIMT_Encode4(365794), // Rule ID 11680 // |
| 114394 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114395 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114396 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114397 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114398 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114399 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114400 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114401 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114402 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114403 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114404 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114405 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114406 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114407 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114408 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114409 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114410 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114411 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114412 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114413 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114414 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114415 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114424 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114425 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114427 | GIR_RootConstrainSelectedInstOperands, |
| 114428 | // GIR_Coverage, 11680, |
| 114429 | GIR_EraseRootFromParent_Done, |
| 114430 | // Label 5700: @365794 |
| 114431 | GIM_Try, /*On fail goto*//*Label 5701*/ GIMT_Encode4(365929), // Rule ID 11681 // |
| 114432 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 114433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114434 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114435 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114436 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114437 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114438 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114439 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114440 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114441 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114442 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 114443 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114444 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114445 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 114446 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114447 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 114448 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114449 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114450 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114451 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114452 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114453 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 114455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114465 | GIR_RootConstrainSelectedInstOperands, |
| 114466 | // GIR_Coverage, 11681, |
| 114467 | GIR_EraseRootFromParent_Done, |
| 114468 | // Label 5701: @365929 |
| 114469 | GIM_Try, /*On fail goto*//*Label 5702*/ GIMT_Encode4(366041), // Rule ID 11944 // |
| 114470 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114472 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 114473 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 114474 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114475 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114476 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114477 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114478 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114479 | GIM_CheckHasOneUse, /*MI*/2, |
| 114480 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 114481 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 114482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114483 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114484 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114485 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 114491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 114492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 114493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 114494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114496 | GIR_RootConstrainSelectedInstOperands, |
| 114497 | // GIR_Coverage, 11944, |
| 114498 | GIR_EraseRootFromParent_Done, |
| 114499 | // Label 5702: @366041 |
| 114500 | GIM_Try, /*On fail goto*//*Label 5703*/ GIMT_Encode4(366153), // Rule ID 11943 // |
| 114501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 114504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 114505 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114506 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114507 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114508 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114509 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114510 | GIM_CheckHasOneUse, /*MI*/2, |
| 114511 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 114512 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 114513 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114514 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114515 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114516 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 114522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 114523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 114524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 114525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114527 | GIR_RootConstrainSelectedInstOperands, |
| 114528 | // GIR_Coverage, 11943, |
| 114529 | GIR_EraseRootFromParent_Done, |
| 114530 | // Label 5703: @366153 |
| 114531 | GIM_Try, /*On fail goto*//*Label 5704*/ GIMT_Encode4(366265), // Rule ID 7413 // |
| 114532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114534 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114535 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 114536 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114537 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114538 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114539 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114540 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114541 | GIM_CheckHasOneUse, /*MI*/2, |
| 114542 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 114543 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 114544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114545 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114546 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114547 | // (fminnum_ieee:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114558 | GIR_RootConstrainSelectedInstOperands, |
| 114559 | // GIR_Coverage, 7413, |
| 114560 | GIR_EraseRootFromParent_Done, |
| 114561 | // Label 5704: @366265 |
| 114562 | GIM_Try, /*On fail goto*//*Label 5705*/ GIMT_Encode4(366377), // Rule ID 7412 // |
| 114563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 114567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114568 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 114569 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114570 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 114571 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 114572 | GIM_CheckHasOneUse, /*MI*/2, |
| 114573 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 114574 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 114575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114576 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114577 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114578 | // (fminnum_ieee:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114589 | GIR_RootConstrainSelectedInstOperands, |
| 114590 | // GIR_Coverage, 7412, |
| 114591 | GIR_EraseRootFromParent_Done, |
| 114592 | // Label 5705: @366377 |
| 114593 | GIM_Try, /*On fail goto*//*Label 5706*/ GIMT_Encode4(366473), // Rule ID 11928 // |
| 114594 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114596 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 114597 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114598 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114599 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114600 | GIM_CheckHasOneUse, /*MI*/1, |
| 114601 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 114602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114603 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114604 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114605 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 114611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 114612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 114613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 114614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114616 | GIR_RootConstrainSelectedInstOperands, |
| 114617 | // GIR_Coverage, 11928, |
| 114618 | GIR_EraseRootFromParent_Done, |
| 114619 | // Label 5706: @366473 |
| 114620 | GIM_Try, /*On fail goto*//*Label 5707*/ GIMT_Encode4(366569), // Rule ID 11927 // |
| 114621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 114624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114626 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114627 | GIM_CheckHasOneUse, /*MI*/1, |
| 114628 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 114629 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114630 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114631 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114632 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 114638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 114639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 114640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 114641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114643 | GIR_RootConstrainSelectedInstOperands, |
| 114644 | // GIR_Coverage, 11927, |
| 114645 | GIR_EraseRootFromParent_Done, |
| 114646 | // Label 5707: @366569 |
| 114647 | GIM_Try, /*On fail goto*//*Label 5708*/ GIMT_Encode4(366665), // Rule ID 7397 // |
| 114648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114650 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114651 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114652 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114653 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114654 | GIM_CheckHasOneUse, /*MI*/1, |
| 114655 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 114656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114657 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114658 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114659 | // (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114668 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114670 | GIR_RootConstrainSelectedInstOperands, |
| 114671 | // GIR_Coverage, 7397, |
| 114672 | GIR_EraseRootFromParent_Done, |
| 114673 | // Label 5708: @366665 |
| 114674 | GIM_Try, /*On fail goto*//*Label 5709*/ GIMT_Encode4(366761), // Rule ID 7396 // |
| 114675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 114676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114677 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114678 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 114679 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 114680 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 114681 | GIM_CheckHasOneUse, /*MI*/1, |
| 114682 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 114683 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114684 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114685 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114686 | // (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F16_e64), |
| 114688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114697 | GIR_RootConstrainSelectedInstOperands, |
| 114698 | // GIR_Coverage, 7396, |
| 114699 | GIR_EraseRootFromParent_Done, |
| 114700 | // Label 5709: @366761 |
| 114701 | GIM_Try, /*On fail goto*//*Label 5710*/ GIMT_Encode4(366796), // Rule ID 102 // |
| 114702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 114703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 114704 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 114705 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 114706 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18519), |
| 114707 | // (fminnum_ieee:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18519>> => (S_MIN_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 114708 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F16), |
| 114709 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 114710 | GIR_RootConstrainSelectedInstOperands, |
| 114711 | // GIR_Coverage, 102, |
| 114712 | GIR_Done, |
| 114713 | // Label 5710: @366796 |
| 114714 | GIM_Try, /*On fail goto*//*Label 5711*/ GIMT_Encode4(366859), // Rule ID 815 // |
| 114715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 114716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 114718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114719 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 114720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64), |
| 114721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 114723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 114725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 114727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 114728 | GIR_RootConstrainSelectedInstOperands, |
| 114729 | // GIR_Coverage, 815, |
| 114730 | GIR_EraseRootFromParent_Done, |
| 114731 | // Label 5711: @366859 |
| 114732 | GIM_Try, /*On fail goto*//*Label 5712*/ GIMT_Encode4(366922), // Rule ID 819 // |
| 114733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 114734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 114736 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114737 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 114738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64), |
| 114739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 114741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 114743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 114745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 114746 | GIR_RootConstrainSelectedInstOperands, |
| 114747 | // GIR_Coverage, 819, |
| 114748 | GIR_EraseRootFromParent_Done, |
| 114749 | // Label 5712: @366922 |
| 114750 | GIM_Try, /*On fail goto*//*Label 5713*/ GIMT_Encode4(366985), // Rule ID 8074 // |
| 114751 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 114752 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 114755 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 114756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_e64), |
| 114757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 114759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 114761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 114763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 114764 | GIR_RootConstrainSelectedInstOperands, |
| 114765 | // GIR_Coverage, 8074, |
| 114766 | GIR_EraseRootFromParent_Done, |
| 114767 | // Label 5713: @366985 |
| 114768 | GIM_Try, /*On fail goto*//*Label 5714*/ GIMT_Encode4(367048), // Rule ID 8076 // |
| 114769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 114770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 114773 | // (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 114774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_fake16_e64), |
| 114775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 114777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 114779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 114781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 114782 | GIR_RootConstrainSelectedInstOperands, |
| 114783 | // GIR_Coverage, 8076, |
| 114784 | GIR_EraseRootFromParent_Done, |
| 114785 | // Label 5714: @367048 |
| 114786 | GIM_Try, /*On fail goto*//*Label 5715*/ GIMT_Encode4(367110), // Rule ID 817 // |
| 114787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 114788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 114789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 114790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 114791 | // (fminnum_ieee:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 114792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F16_t16_e64), |
| 114793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 114795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 114797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114800 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114801 | GIR_RootConstrainSelectedInstOperands, |
| 114802 | // GIR_Coverage, 817, |
| 114803 | GIR_EraseRootFromParent_Done, |
| 114804 | // Label 5715: @367110 |
| 114805 | GIM_Reject, |
| 114806 | // Label 5573: @367111 |
| 114807 | GIM_Reject, |
| 114808 | // Label 5569: @367112 |
| 114809 | GIM_Try, /*On fail goto*//*Label 5716*/ GIMT_Encode4(384623), |
| 114810 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 114811 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 114812 | GIM_Try, /*On fail goto*//*Label 5717*/ GIMT_Encode4(367252), // Rule ID 11267 // |
| 114813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114814 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114815 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114816 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114817 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114818 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114819 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114820 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 114821 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 114822 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 114823 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114824 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114825 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 114826 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114827 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 114828 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114829 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114830 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114831 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114832 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114833 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 114835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114844 | GIR_RootConstrainSelectedInstOperands, |
| 114845 | // GIR_Coverage, 11267, |
| 114846 | GIR_EraseRootFromParent_Done, |
| 114847 | // Label 5717: @367252 |
| 114848 | GIM_Try, /*On fail goto*//*Label 5718*/ GIMT_Encode4(367381), // Rule ID 11268 // |
| 114849 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114850 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114851 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114852 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114853 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114854 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114855 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114856 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 114857 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 114858 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 114859 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114860 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114861 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 114862 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114863 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 114864 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114865 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114866 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114867 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114868 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114869 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114870 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 114871 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114880 | GIR_RootConstrainSelectedInstOperands, |
| 114881 | // GIR_Coverage, 11268, |
| 114882 | GIR_EraseRootFromParent_Done, |
| 114883 | // Label 5718: @367381 |
| 114884 | GIM_Try, /*On fail goto*//*Label 5719*/ GIMT_Encode4(367510), // Rule ID 11271 // |
| 114885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114887 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114889 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114890 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114891 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114892 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 114893 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 114894 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 114895 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114896 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114897 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 114898 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114899 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 114900 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114901 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114902 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114903 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114904 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114905 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 114907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114914 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114916 | GIR_RootConstrainSelectedInstOperands, |
| 114917 | // GIR_Coverage, 11271, |
| 114918 | GIR_EraseRootFromParent_Done, |
| 114919 | // Label 5719: @367510 |
| 114920 | GIM_Try, /*On fail goto*//*Label 5720*/ GIMT_Encode4(367639), // Rule ID 11272 // |
| 114921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114922 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114923 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114924 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114925 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114926 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114927 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114928 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 114929 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 114930 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 114931 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 114932 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114933 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 114934 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114935 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 114936 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114937 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114938 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114939 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114940 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114941 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 114943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 114945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 114946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 114947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 114948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114952 | GIR_RootConstrainSelectedInstOperands, |
| 114953 | // GIR_Coverage, 11272, |
| 114954 | GIR_EraseRootFromParent_Done, |
| 114955 | // Label 5720: @367639 |
| 114956 | GIM_Try, /*On fail goto*//*Label 5721*/ GIMT_Encode4(367768), // Rule ID 11252 // |
| 114957 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114958 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114959 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114960 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114961 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114962 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114963 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114964 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 114965 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 114966 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 114967 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 114968 | // MIs[3] VOP3Mods:src0:src0_mods |
| 114969 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 114970 | // MIs[3] VOP3Mods:src1:src1_mods |
| 114971 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 114972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 114973 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 114974 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 114975 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 114976 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 114977 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 114978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 114979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 114980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 114981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 114982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 114983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 114984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 114985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 114986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 114988 | GIR_RootConstrainSelectedInstOperands, |
| 114989 | // GIR_Coverage, 11252, |
| 114990 | GIR_EraseRootFromParent_Done, |
| 114991 | // Label 5721: @367768 |
| 114992 | GIM_Try, /*On fail goto*//*Label 5722*/ GIMT_Encode4(367897), // Rule ID 11253 // |
| 114993 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 114994 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 114995 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 114996 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 114997 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 114998 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 114999 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115000 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115001 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115002 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115003 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115004 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115005 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115006 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115007 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115008 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115009 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115010 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115011 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115012 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115013 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115022 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115024 | GIR_RootConstrainSelectedInstOperands, |
| 115025 | // GIR_Coverage, 11253, |
| 115026 | GIR_EraseRootFromParent_Done, |
| 115027 | // Label 5722: @367897 |
| 115028 | GIM_Try, /*On fail goto*//*Label 5723*/ GIMT_Encode4(368026), // Rule ID 11256 // |
| 115029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115030 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115031 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115032 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115033 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115034 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115035 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115036 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115037 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115038 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115039 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115040 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115041 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115042 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115043 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115044 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115045 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115046 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115047 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115048 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115049 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115058 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115060 | GIR_RootConstrainSelectedInstOperands, |
| 115061 | // GIR_Coverage, 11256, |
| 115062 | GIR_EraseRootFromParent_Done, |
| 115063 | // Label 5723: @368026 |
| 115064 | GIM_Try, /*On fail goto*//*Label 5724*/ GIMT_Encode4(368155), // Rule ID 11257 // |
| 115065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115066 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115067 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115068 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115069 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115070 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115071 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115072 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115073 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115074 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115075 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115076 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115077 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115078 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115079 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115080 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115081 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115082 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115083 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115084 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115085 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115094 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115096 | GIR_RootConstrainSelectedInstOperands, |
| 115097 | // GIR_Coverage, 11257, |
| 115098 | GIR_EraseRootFromParent_Done, |
| 115099 | // Label 5724: @368155 |
| 115100 | GIM_Try, /*On fail goto*//*Label 5725*/ GIMT_Encode4(368284), // Rule ID 7337 // |
| 115101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115102 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115103 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115104 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115105 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115106 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115107 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115108 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115109 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115110 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115111 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115112 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115113 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115114 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115115 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115116 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115117 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115118 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115119 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115120 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115121 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115130 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115132 | GIR_RootConstrainSelectedInstOperands, |
| 115133 | // GIR_Coverage, 7337, |
| 115134 | GIR_EraseRootFromParent_Done, |
| 115135 | // Label 5725: @368284 |
| 115136 | GIM_Try, /*On fail goto*//*Label 5726*/ GIMT_Encode4(368413), // Rule ID 11266 // |
| 115137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115138 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115139 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115140 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115141 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115142 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115143 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115144 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115145 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115146 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115147 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115148 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115149 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115150 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115151 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115152 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115153 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115154 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115155 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115156 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115157 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115159 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115168 | GIR_RootConstrainSelectedInstOperands, |
| 115169 | // GIR_Coverage, 11266, |
| 115170 | GIR_EraseRootFromParent_Done, |
| 115171 | // Label 5726: @368413 |
| 115172 | GIM_Try, /*On fail goto*//*Label 5727*/ GIMT_Encode4(368542), // Rule ID 11269 // |
| 115173 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115174 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115175 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115176 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115177 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115178 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115179 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115180 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115181 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115182 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115183 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115184 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115185 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115186 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115187 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115188 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115189 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115190 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115191 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115192 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115193 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115195 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115204 | GIR_RootConstrainSelectedInstOperands, |
| 115205 | // GIR_Coverage, 11269, |
| 115206 | GIR_EraseRootFromParent_Done, |
| 115207 | // Label 5727: @368542 |
| 115208 | GIM_Try, /*On fail goto*//*Label 5728*/ GIMT_Encode4(368671), // Rule ID 11270 // |
| 115209 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115210 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115211 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115212 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115213 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115214 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115215 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115216 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115217 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115218 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115219 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115220 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115221 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115222 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115223 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115224 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115225 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115226 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115227 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115228 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115229 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115240 | GIR_RootConstrainSelectedInstOperands, |
| 115241 | // GIR_Coverage, 11270, |
| 115242 | GIR_EraseRootFromParent_Done, |
| 115243 | // Label 5728: @368671 |
| 115244 | GIM_Try, /*On fail goto*//*Label 5729*/ GIMT_Encode4(368800), // Rule ID 7336 // |
| 115245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115246 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115247 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115249 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115250 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115251 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115252 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115253 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115254 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115255 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115256 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115257 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115258 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115259 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115260 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115261 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115262 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115263 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115264 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115265 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115276 | GIR_RootConstrainSelectedInstOperands, |
| 115277 | // GIR_Coverage, 7336, |
| 115278 | GIR_EraseRootFromParent_Done, |
| 115279 | // Label 5729: @368800 |
| 115280 | GIM_Try, /*On fail goto*//*Label 5730*/ GIMT_Encode4(368929), // Rule ID 11251 // |
| 115281 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115282 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115283 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115284 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115285 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115286 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115287 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115288 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115289 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115290 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115291 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115292 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115293 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115294 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115295 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115296 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115297 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115298 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115299 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115300 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115301 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115312 | GIR_RootConstrainSelectedInstOperands, |
| 115313 | // GIR_Coverage, 11251, |
| 115314 | GIR_EraseRootFromParent_Done, |
| 115315 | // Label 5730: @368929 |
| 115316 | GIM_Try, /*On fail goto*//*Label 5731*/ GIMT_Encode4(369058), // Rule ID 11254 // |
| 115317 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115322 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115323 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115324 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115325 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115326 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115327 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115328 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115329 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115330 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115332 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115333 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115334 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115335 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115336 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115337 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115346 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115348 | GIR_RootConstrainSelectedInstOperands, |
| 115349 | // GIR_Coverage, 11254, |
| 115350 | GIR_EraseRootFromParent_Done, |
| 115351 | // Label 5731: @369058 |
| 115352 | GIM_Try, /*On fail goto*//*Label 5732*/ GIMT_Encode4(369187), // Rule ID 11255 // |
| 115353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115354 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115355 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115356 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115357 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115358 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115359 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115360 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115361 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115362 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115363 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115364 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115365 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115366 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115367 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115368 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115369 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115370 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115371 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115372 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115373 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115384 | GIR_RootConstrainSelectedInstOperands, |
| 115385 | // GIR_Coverage, 11255, |
| 115386 | GIR_EraseRootFromParent_Done, |
| 115387 | // Label 5732: @369187 |
| 115388 | GIM_Try, /*On fail goto*//*Label 5733*/ GIMT_Encode4(369316), // Rule ID 11237 // |
| 115389 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115390 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115391 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115392 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115393 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115394 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115395 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115396 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115397 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115398 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115399 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115400 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115401 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115402 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115403 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115404 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115405 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115406 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115407 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115408 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115409 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115420 | GIR_RootConstrainSelectedInstOperands, |
| 115421 | // GIR_Coverage, 11237, |
| 115422 | GIR_EraseRootFromParent_Done, |
| 115423 | // Label 5733: @369316 |
| 115424 | GIM_Try, /*On fail goto*//*Label 5734*/ GIMT_Encode4(369445), // Rule ID 11238 // |
| 115425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115426 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115427 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115428 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115429 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115430 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115431 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115432 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115433 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115434 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115435 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115436 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115437 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115438 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115439 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115440 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115441 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115442 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115443 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115444 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115445 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115446 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115447 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115456 | GIR_RootConstrainSelectedInstOperands, |
| 115457 | // GIR_Coverage, 11238, |
| 115458 | GIR_EraseRootFromParent_Done, |
| 115459 | // Label 5734: @369445 |
| 115460 | GIM_Try, /*On fail goto*//*Label 5735*/ GIMT_Encode4(369574), // Rule ID 11241 // |
| 115461 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115462 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115463 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115464 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115465 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115466 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115467 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115468 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115469 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115470 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115471 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115472 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115473 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115474 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115475 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115476 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115477 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115478 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115479 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115480 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115481 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115482 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115483 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115490 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115492 | GIR_RootConstrainSelectedInstOperands, |
| 115493 | // GIR_Coverage, 11241, |
| 115494 | GIR_EraseRootFromParent_Done, |
| 115495 | // Label 5735: @369574 |
| 115496 | GIM_Try, /*On fail goto*//*Label 5736*/ GIMT_Encode4(369703), // Rule ID 11242 // |
| 115497 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115498 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115499 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115500 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115501 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115502 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115503 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115504 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115505 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115506 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115507 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115508 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115509 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115510 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115511 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115512 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115513 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115514 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115515 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115516 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115517 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115528 | GIR_RootConstrainSelectedInstOperands, |
| 115529 | // GIR_Coverage, 11242, |
| 115530 | GIR_EraseRootFromParent_Done, |
| 115531 | // Label 5736: @369703 |
| 115532 | GIM_Try, /*On fail goto*//*Label 5737*/ GIMT_Encode4(369832), // Rule ID 11222 // |
| 115533 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115534 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115535 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115536 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115537 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115538 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115539 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115540 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115541 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115542 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115543 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115544 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115545 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115546 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115547 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115548 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115549 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115550 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115551 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115552 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115553 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115554 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115555 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115564 | GIR_RootConstrainSelectedInstOperands, |
| 115565 | // GIR_Coverage, 11222, |
| 115566 | GIR_EraseRootFromParent_Done, |
| 115567 | // Label 5737: @369832 |
| 115568 | GIM_Try, /*On fail goto*//*Label 5738*/ GIMT_Encode4(369961), // Rule ID 11223 // |
| 115569 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115570 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115571 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115572 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115573 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115574 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115575 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115576 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115577 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115578 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115579 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115580 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115581 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115582 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115584 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115585 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115586 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115587 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115588 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115589 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115600 | GIR_RootConstrainSelectedInstOperands, |
| 115601 | // GIR_Coverage, 11223, |
| 115602 | GIR_EraseRootFromParent_Done, |
| 115603 | // Label 5738: @369961 |
| 115604 | GIM_Try, /*On fail goto*//*Label 5739*/ GIMT_Encode4(370090), // Rule ID 11226 // |
| 115605 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115606 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115607 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115608 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115609 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115610 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115611 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115612 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115613 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115614 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115615 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115616 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115617 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115618 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115619 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115620 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115621 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115622 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115623 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115624 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115625 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115636 | GIR_RootConstrainSelectedInstOperands, |
| 115637 | // GIR_Coverage, 11226, |
| 115638 | GIR_EraseRootFromParent_Done, |
| 115639 | // Label 5739: @370090 |
| 115640 | GIM_Try, /*On fail goto*//*Label 5740*/ GIMT_Encode4(370219), // Rule ID 11227 // |
| 115641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115642 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115643 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115644 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115645 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115646 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115647 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115648 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115649 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115650 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 115651 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115652 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115653 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115654 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115655 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115656 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115657 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115658 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115659 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115660 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115661 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115663 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115672 | GIR_RootConstrainSelectedInstOperands, |
| 115673 | // GIR_Coverage, 11227, |
| 115674 | GIR_EraseRootFromParent_Done, |
| 115675 | // Label 5740: @370219 |
| 115676 | GIM_Try, /*On fail goto*//*Label 5741*/ GIMT_Encode4(370348), // Rule ID 7335 // |
| 115677 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115678 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115679 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115680 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115681 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115682 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115683 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115684 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115685 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115686 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115687 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115688 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115689 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115690 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115691 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115692 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115693 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115694 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115695 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115696 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115697 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115698 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115699 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115706 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115708 | GIR_RootConstrainSelectedInstOperands, |
| 115709 | // GIR_Coverage, 7335, |
| 115710 | GIR_EraseRootFromParent_Done, |
| 115711 | // Label 5741: @370348 |
| 115712 | GIM_Try, /*On fail goto*//*Label 5742*/ GIMT_Encode4(370477), // Rule ID 11236 // |
| 115713 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115714 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115715 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115716 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115717 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115718 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115719 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115720 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115721 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115722 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115723 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115724 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115725 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115726 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115727 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115728 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115729 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115730 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115731 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115732 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115733 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115742 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115744 | GIR_RootConstrainSelectedInstOperands, |
| 115745 | // GIR_Coverage, 11236, |
| 115746 | GIR_EraseRootFromParent_Done, |
| 115747 | // Label 5742: @370477 |
| 115748 | GIM_Try, /*On fail goto*//*Label 5743*/ GIMT_Encode4(370606), // Rule ID 11239 // |
| 115749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115750 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115751 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115752 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115753 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115754 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115755 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115756 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115757 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115758 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115759 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115760 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115761 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115762 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115763 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115764 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115765 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115766 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115767 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115768 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115769 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115778 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115780 | GIR_RootConstrainSelectedInstOperands, |
| 115781 | // GIR_Coverage, 11239, |
| 115782 | GIR_EraseRootFromParent_Done, |
| 115783 | // Label 5743: @370606 |
| 115784 | GIM_Try, /*On fail goto*//*Label 5744*/ GIMT_Encode4(370735), // Rule ID 11240 // |
| 115785 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115786 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115787 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115788 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115789 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115790 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115791 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115792 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115793 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115794 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115795 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115796 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115797 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115798 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115799 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115800 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115801 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115802 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115803 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115804 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115805 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115814 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115816 | GIR_RootConstrainSelectedInstOperands, |
| 115817 | // GIR_Coverage, 11240, |
| 115818 | GIR_EraseRootFromParent_Done, |
| 115819 | // Label 5744: @370735 |
| 115820 | GIM_Try, /*On fail goto*//*Label 5745*/ GIMT_Encode4(370864), // Rule ID 7334 // |
| 115821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115822 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115823 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115824 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115825 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115826 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115827 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115828 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115829 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115830 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115831 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115832 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115833 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115834 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115835 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115836 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115837 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115838 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115839 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115840 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115841 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115852 | GIR_RootConstrainSelectedInstOperands, |
| 115853 | // GIR_Coverage, 7334, |
| 115854 | GIR_EraseRootFromParent_Done, |
| 115855 | // Label 5745: @370864 |
| 115856 | GIM_Try, /*On fail goto*//*Label 5746*/ GIMT_Encode4(370993), // Rule ID 11221 // |
| 115857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115858 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115859 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115860 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115861 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115862 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115863 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115864 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115865 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115866 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115867 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115868 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115869 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115870 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115871 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115872 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115873 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115874 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115875 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115876 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115877 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115878 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115879 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 115881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 115882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 115883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 115884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115888 | GIR_RootConstrainSelectedInstOperands, |
| 115889 | // GIR_Coverage, 11221, |
| 115890 | GIR_EraseRootFromParent_Done, |
| 115891 | // Label 5746: @370993 |
| 115892 | GIM_Try, /*On fail goto*//*Label 5747*/ GIMT_Encode4(371122), // Rule ID 11224 // |
| 115893 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115894 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115895 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115896 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115897 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115898 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115899 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115900 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115901 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115902 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115903 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115904 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115905 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115906 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115907 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115908 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115909 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115910 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115911 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115912 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115913 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115914 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115915 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115924 | GIR_RootConstrainSelectedInstOperands, |
| 115925 | // GIR_Coverage, 11224, |
| 115926 | GIR_EraseRootFromParent_Done, |
| 115927 | // Label 5747: @371122 |
| 115928 | GIM_Try, /*On fail goto*//*Label 5748*/ GIMT_Encode4(371251), // Rule ID 11225 // |
| 115929 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115930 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115931 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115932 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115933 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115934 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 115935 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 115936 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115937 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115938 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 115939 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 115940 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115941 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 115942 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115943 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 115944 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115945 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115946 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115948 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115949 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 115955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 115956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 115957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 115958 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115960 | GIR_RootConstrainSelectedInstOperands, |
| 115961 | // GIR_Coverage, 11225, |
| 115962 | GIR_EraseRootFromParent_Done, |
| 115963 | // Label 5748: @371251 |
| 115964 | GIM_Try, /*On fail goto*//*Label 5749*/ GIMT_Encode4(371380), // Rule ID 11277 // |
| 115965 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 115966 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 115967 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115968 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 115969 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 115970 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 115971 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 115972 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 115973 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 115974 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 115975 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 115976 | // MIs[3] VOP3Mods:src0:src0_mods |
| 115977 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 115978 | // MIs[3] VOP3Mods:src1:src1_mods |
| 115979 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 115980 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 115981 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 115982 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 115983 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 115984 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 115985 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 115986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 115987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 115988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 115989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 115990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 115991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 115992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 115993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 115994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 115996 | GIR_RootConstrainSelectedInstOperands, |
| 115997 | // GIR_Coverage, 11277, |
| 115998 | GIR_EraseRootFromParent_Done, |
| 115999 | // Label 5749: @371380 |
| 116000 | GIM_Try, /*On fail goto*//*Label 5750*/ GIMT_Encode4(371509), // Rule ID 11278 // |
| 116001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116002 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116003 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116004 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116005 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116006 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116007 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116008 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116009 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116010 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116011 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116012 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116013 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116014 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116015 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116016 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116017 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116018 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116019 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116020 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116021 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116023 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116030 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116032 | GIR_RootConstrainSelectedInstOperands, |
| 116033 | // GIR_Coverage, 11278, |
| 116034 | GIR_EraseRootFromParent_Done, |
| 116035 | // Label 5750: @371509 |
| 116036 | GIM_Try, /*On fail goto*//*Label 5751*/ GIMT_Encode4(371638), // Rule ID 11279 // |
| 116037 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116038 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116039 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116040 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116041 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116042 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116043 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116044 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116045 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116046 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116047 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116048 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116049 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116050 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116051 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116052 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116053 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116054 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116055 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116056 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116057 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116068 | GIR_RootConstrainSelectedInstOperands, |
| 116069 | // GIR_Coverage, 11279, |
| 116070 | GIR_EraseRootFromParent_Done, |
| 116071 | // Label 5751: @371638 |
| 116072 | GIM_Try, /*On fail goto*//*Label 5752*/ GIMT_Encode4(371767), // Rule ID 11280 // |
| 116073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116074 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116075 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116076 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116077 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116078 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116079 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116080 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116081 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116082 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116083 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116084 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116085 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116086 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116087 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116088 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116089 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116090 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116091 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116092 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116093 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116104 | GIR_RootConstrainSelectedInstOperands, |
| 116105 | // GIR_Coverage, 11280, |
| 116106 | GIR_EraseRootFromParent_Done, |
| 116107 | // Label 5752: @371767 |
| 116108 | GIM_Try, /*On fail goto*//*Label 5753*/ GIMT_Encode4(371896), // Rule ID 11217 // |
| 116109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116110 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116111 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116112 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116113 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116114 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116115 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116116 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116117 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116118 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116119 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116120 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116121 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116122 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116123 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116124 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116125 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116126 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116127 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116128 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116129 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116131 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116140 | GIR_RootConstrainSelectedInstOperands, |
| 116141 | // GIR_Coverage, 11217, |
| 116142 | GIR_EraseRootFromParent_Done, |
| 116143 | // Label 5753: @371896 |
| 116144 | GIM_Try, /*On fail goto*//*Label 5754*/ GIMT_Encode4(372025), // Rule ID 11218 // |
| 116145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116146 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116147 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116148 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116149 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116150 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116151 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116152 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116153 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116154 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116155 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116156 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116157 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116158 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116159 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116160 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116161 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116162 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116163 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116164 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116165 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116176 | GIR_RootConstrainSelectedInstOperands, |
| 116177 | // GIR_Coverage, 11218, |
| 116178 | GIR_EraseRootFromParent_Done, |
| 116179 | // Label 5754: @372025 |
| 116180 | GIM_Try, /*On fail goto*//*Label 5755*/ GIMT_Encode4(372154), // Rule ID 11219 // |
| 116181 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116182 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116183 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116184 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116185 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116186 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116187 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116188 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116189 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116190 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116191 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116192 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116193 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116194 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116195 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116196 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116197 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116198 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116199 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116200 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116201 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116203 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116212 | GIR_RootConstrainSelectedInstOperands, |
| 116213 | // GIR_Coverage, 11219, |
| 116214 | GIR_EraseRootFromParent_Done, |
| 116215 | // Label 5755: @372154 |
| 116216 | GIM_Try, /*On fail goto*//*Label 5756*/ GIMT_Encode4(372283), // Rule ID 11220 // |
| 116217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116218 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116219 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116220 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116221 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116222 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116223 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116224 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116225 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116226 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116227 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116228 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116229 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116230 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116231 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116232 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116233 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116234 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116235 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116236 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116237 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116248 | GIR_RootConstrainSelectedInstOperands, |
| 116249 | // GIR_Coverage, 11220, |
| 116250 | GIR_EraseRootFromParent_Done, |
| 116251 | // Label 5756: @372283 |
| 116252 | GIM_Try, /*On fail goto*//*Label 5757*/ GIMT_Encode4(372412), // Rule ID 11262 // |
| 116253 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116255 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116259 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116261 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116262 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116263 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116264 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116265 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116266 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116268 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116269 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116270 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116271 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116272 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116273 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116282 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116284 | GIR_RootConstrainSelectedInstOperands, |
| 116285 | // GIR_Coverage, 11262, |
| 116286 | GIR_EraseRootFromParent_Done, |
| 116287 | // Label 5757: @372412 |
| 116288 | GIM_Try, /*On fail goto*//*Label 5758*/ GIMT_Encode4(372541), // Rule ID 11263 // |
| 116289 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116290 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116291 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116292 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116293 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116294 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116295 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116296 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116297 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116298 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116299 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116300 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116301 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116302 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116303 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116304 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116305 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116306 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116307 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116308 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116309 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116320 | GIR_RootConstrainSelectedInstOperands, |
| 116321 | // GIR_Coverage, 11263, |
| 116322 | GIR_EraseRootFromParent_Done, |
| 116323 | // Label 5758: @372541 |
| 116324 | GIM_Try, /*On fail goto*//*Label 5759*/ GIMT_Encode4(372670), // Rule ID 11264 // |
| 116325 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116326 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116327 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116328 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116329 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116330 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116331 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116332 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116333 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116334 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116335 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116336 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116337 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116338 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116339 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116340 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116341 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116342 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116343 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116344 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116345 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116347 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116356 | GIR_RootConstrainSelectedInstOperands, |
| 116357 | // GIR_Coverage, 11264, |
| 116358 | GIR_EraseRootFromParent_Done, |
| 116359 | // Label 5759: @372670 |
| 116360 | GIM_Try, /*On fail goto*//*Label 5760*/ GIMT_Encode4(372799), // Rule ID 11265 // |
| 116361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116362 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116363 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116364 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116365 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116366 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116367 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116368 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116369 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116370 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116371 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116372 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116373 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116374 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116375 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116376 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116377 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116378 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116379 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116380 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116381 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116383 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116384 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116390 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116392 | GIR_RootConstrainSelectedInstOperands, |
| 116393 | // GIR_Coverage, 11265, |
| 116394 | GIR_EraseRootFromParent_Done, |
| 116395 | // Label 5760: @372799 |
| 116396 | GIM_Try, /*On fail goto*//*Label 5761*/ GIMT_Encode4(372928), // Rule ID 11202 // |
| 116397 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116398 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116399 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116400 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116401 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116402 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116403 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116404 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116405 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116406 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116407 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116408 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116409 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116410 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116411 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116412 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116413 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116414 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116415 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116416 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116417 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116426 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116428 | GIR_RootConstrainSelectedInstOperands, |
| 116429 | // GIR_Coverage, 11202, |
| 116430 | GIR_EraseRootFromParent_Done, |
| 116431 | // Label 5761: @372928 |
| 116432 | GIM_Try, /*On fail goto*//*Label 5762*/ GIMT_Encode4(373057), // Rule ID 11203 // |
| 116433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116434 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116435 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116436 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116437 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116438 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116439 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116440 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116441 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116442 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116443 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116444 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116445 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116446 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116447 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116448 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116449 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116450 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116451 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116452 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116453 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 116459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 116460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116464 | GIR_RootConstrainSelectedInstOperands, |
| 116465 | // GIR_Coverage, 11203, |
| 116466 | GIR_EraseRootFromParent_Done, |
| 116467 | // Label 5762: @373057 |
| 116468 | GIM_Try, /*On fail goto*//*Label 5763*/ GIMT_Encode4(373186), // Rule ID 11204 // |
| 116469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116470 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116471 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116472 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116473 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116474 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116475 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116476 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116477 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116478 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116479 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116480 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116481 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116482 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116483 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116484 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116485 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116486 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116487 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116488 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116489 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116490 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116491 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116500 | GIR_RootConstrainSelectedInstOperands, |
| 116501 | // GIR_Coverage, 11204, |
| 116502 | GIR_EraseRootFromParent_Done, |
| 116503 | // Label 5763: @373186 |
| 116504 | GIM_Try, /*On fail goto*//*Label 5764*/ GIMT_Encode4(373315), // Rule ID 11205 // |
| 116505 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116506 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116507 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116508 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116509 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116510 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 116511 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116512 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116513 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116514 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116515 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116516 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116517 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116518 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116519 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116520 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116521 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116522 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116523 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116524 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116525 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 116529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 116530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 116533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 116534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116536 | GIR_RootConstrainSelectedInstOperands, |
| 116537 | // GIR_Coverage, 11205, |
| 116538 | GIR_EraseRootFromParent_Done, |
| 116539 | // Label 5764: @373315 |
| 116540 | GIM_Try, /*On fail goto*//*Label 5765*/ GIMT_Encode4(373444), // Rule ID 11273 // |
| 116541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116542 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116543 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116544 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116545 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116546 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116547 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116548 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116549 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116550 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116551 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116552 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116553 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116554 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116555 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116556 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116557 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116558 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116559 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116560 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116561 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116563 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116572 | GIR_RootConstrainSelectedInstOperands, |
| 116573 | // GIR_Coverage, 11273, |
| 116574 | GIR_EraseRootFromParent_Done, |
| 116575 | // Label 5765: @373444 |
| 116576 | GIM_Try, /*On fail goto*//*Label 5766*/ GIMT_Encode4(373573), // Rule ID 11274 // |
| 116577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116578 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116579 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116580 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116581 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116582 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116583 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116584 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116585 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116586 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116587 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116588 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116589 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116590 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116591 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116592 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116593 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116594 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116595 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116596 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116597 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116608 | GIR_RootConstrainSelectedInstOperands, |
| 116609 | // GIR_Coverage, 11274, |
| 116610 | GIR_EraseRootFromParent_Done, |
| 116611 | // Label 5766: @373573 |
| 116612 | GIM_Try, /*On fail goto*//*Label 5767*/ GIMT_Encode4(373702), // Rule ID 11275 // |
| 116613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116614 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116615 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116616 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116617 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116618 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116619 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116620 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116621 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116622 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116623 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116624 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116625 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116626 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116627 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116628 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116629 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116630 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116631 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116632 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116633 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116644 | GIR_RootConstrainSelectedInstOperands, |
| 116645 | // GIR_Coverage, 11275, |
| 116646 | GIR_EraseRootFromParent_Done, |
| 116647 | // Label 5767: @373702 |
| 116648 | GIM_Try, /*On fail goto*//*Label 5768*/ GIMT_Encode4(373831), // Rule ID 11276 // |
| 116649 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116650 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116651 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116652 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116653 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116654 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116655 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116656 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116657 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116658 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116659 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116660 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116661 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116662 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116663 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116664 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116665 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116666 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116667 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116668 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116669 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116678 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116680 | GIR_RootConstrainSelectedInstOperands, |
| 116681 | // GIR_Coverage, 11276, |
| 116682 | GIR_EraseRootFromParent_Done, |
| 116683 | // Label 5768: @373831 |
| 116684 | GIM_Try, /*On fail goto*//*Label 5769*/ GIMT_Encode4(373960), // Rule ID 11213 // |
| 116685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116686 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116687 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116688 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116689 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116690 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116691 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116692 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116693 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116694 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116695 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116696 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116697 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116698 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116699 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116700 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116701 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116702 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116703 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116704 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116705 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116714 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116716 | GIR_RootConstrainSelectedInstOperands, |
| 116717 | // GIR_Coverage, 11213, |
| 116718 | GIR_EraseRootFromParent_Done, |
| 116719 | // Label 5769: @373960 |
| 116720 | GIM_Try, /*On fail goto*//*Label 5770*/ GIMT_Encode4(374089), // Rule ID 11214 // |
| 116721 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116722 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116723 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116724 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116725 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116726 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116727 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116728 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116729 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116730 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116731 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116732 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116733 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116734 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116735 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116736 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116737 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116738 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116739 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116740 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116741 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116750 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116752 | GIR_RootConstrainSelectedInstOperands, |
| 116753 | // GIR_Coverage, 11214, |
| 116754 | GIR_EraseRootFromParent_Done, |
| 116755 | // Label 5770: @374089 |
| 116756 | GIM_Try, /*On fail goto*//*Label 5771*/ GIMT_Encode4(374218), // Rule ID 11215 // |
| 116757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116758 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116759 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116760 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116761 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116762 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116763 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116764 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116765 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116766 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116767 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116768 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116769 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116770 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116771 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116772 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116773 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116774 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116775 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116776 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116777 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116786 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116788 | GIR_RootConstrainSelectedInstOperands, |
| 116789 | // GIR_Coverage, 11215, |
| 116790 | GIR_EraseRootFromParent_Done, |
| 116791 | // Label 5771: @374218 |
| 116792 | GIM_Try, /*On fail goto*//*Label 5772*/ GIMT_Encode4(374347), // Rule ID 11216 // |
| 116793 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116794 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116795 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116796 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116797 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116798 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116799 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 116800 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116801 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116802 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116803 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116804 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116805 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116806 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116807 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116808 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116809 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116810 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116811 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116812 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116813 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116824 | GIR_RootConstrainSelectedInstOperands, |
| 116825 | // GIR_Coverage, 11216, |
| 116826 | GIR_EraseRootFromParent_Done, |
| 116827 | // Label 5772: @374347 |
| 116828 | GIM_Try, /*On fail goto*//*Label 5773*/ GIMT_Encode4(374476), // Rule ID 11258 // |
| 116829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116830 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116831 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116832 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116833 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116834 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116835 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116836 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116837 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116838 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116839 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116840 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116841 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116842 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116843 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116844 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116845 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116846 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116847 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116848 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116849 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116851 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116858 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116860 | GIR_RootConstrainSelectedInstOperands, |
| 116861 | // GIR_Coverage, 11258, |
| 116862 | GIR_EraseRootFromParent_Done, |
| 116863 | // Label 5773: @374476 |
| 116864 | GIM_Try, /*On fail goto*//*Label 5774*/ GIMT_Encode4(374605), // Rule ID 11259 // |
| 116865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116866 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116867 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116868 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116869 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116870 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116871 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116872 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116873 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116874 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116875 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116876 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116877 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116878 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116879 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116880 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116881 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116882 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116883 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116884 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116885 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 116892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116894 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116896 | GIR_RootConstrainSelectedInstOperands, |
| 116897 | // GIR_Coverage, 11259, |
| 116898 | GIR_EraseRootFromParent_Done, |
| 116899 | // Label 5774: @374605 |
| 116900 | GIM_Try, /*On fail goto*//*Label 5775*/ GIMT_Encode4(374734), // Rule ID 11260 // |
| 116901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116902 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116903 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116904 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116905 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116906 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116907 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116908 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116909 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116910 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116911 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116912 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116913 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116914 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116915 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116916 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116917 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116918 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116919 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116920 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116921 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116922 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116923 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116930 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116932 | GIR_RootConstrainSelectedInstOperands, |
| 116933 | // GIR_Coverage, 11260, |
| 116934 | GIR_EraseRootFromParent_Done, |
| 116935 | // Label 5775: @374734 |
| 116936 | GIM_Try, /*On fail goto*//*Label 5776*/ GIMT_Encode4(374863), // Rule ID 11261 // |
| 116937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116938 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116939 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116940 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116941 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116942 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116943 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116944 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116945 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116946 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116947 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116948 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116949 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116950 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116951 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116952 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116953 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116954 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116955 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116956 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116957 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 116961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 116962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 116963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 116964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 116965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 116966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 116968 | GIR_RootConstrainSelectedInstOperands, |
| 116969 | // GIR_Coverage, 11261, |
| 116970 | GIR_EraseRootFromParent_Done, |
| 116971 | // Label 5776: @374863 |
| 116972 | GIM_Try, /*On fail goto*//*Label 5777*/ GIMT_Encode4(374992), // Rule ID 11198 // |
| 116973 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 116974 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 116975 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 116976 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 116977 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 116978 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 116979 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 116980 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 116981 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 116982 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 116983 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 116984 | // MIs[3] VOP3Mods:src0:src0_mods |
| 116985 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 116986 | // MIs[3] VOP3Mods:src1:src1_mods |
| 116987 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 116988 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 116989 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 116990 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 116991 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 116992 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 116993 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 116994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 116995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 116996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 116997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 116998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 116999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117004 | GIR_RootConstrainSelectedInstOperands, |
| 117005 | // GIR_Coverage, 11198, |
| 117006 | GIR_EraseRootFromParent_Done, |
| 117007 | // Label 5777: @374992 |
| 117008 | GIM_Try, /*On fail goto*//*Label 5778*/ GIMT_Encode4(375121), // Rule ID 11199 // |
| 117009 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117010 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117011 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117012 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117013 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117014 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 117015 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117016 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117017 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117018 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 117019 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117020 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117021 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 117022 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117023 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 117024 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117025 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117026 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117027 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117028 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117029 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117040 | GIR_RootConstrainSelectedInstOperands, |
| 117041 | // GIR_Coverage, 11199, |
| 117042 | GIR_EraseRootFromParent_Done, |
| 117043 | // Label 5778: @375121 |
| 117044 | GIM_Try, /*On fail goto*//*Label 5779*/ GIMT_Encode4(375250), // Rule ID 11200 // |
| 117045 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117046 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117047 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117048 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117049 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117050 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 117051 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117052 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117053 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117054 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 117055 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117056 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117057 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 117058 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117059 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 117060 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117061 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117062 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117063 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117064 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117065 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117076 | GIR_RootConstrainSelectedInstOperands, |
| 117077 | // GIR_Coverage, 11200, |
| 117078 | GIR_EraseRootFromParent_Done, |
| 117079 | // Label 5779: @375250 |
| 117080 | GIM_Try, /*On fail goto*//*Label 5780*/ GIMT_Encode4(375379), // Rule ID 11201 // |
| 117081 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117082 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117083 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117084 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117085 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117086 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 117087 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117088 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117089 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117090 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 117091 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117092 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117093 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 117094 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117095 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 117096 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117097 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117098 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117099 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117100 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117101 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117110 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117112 | GIR_RootConstrainSelectedInstOperands, |
| 117113 | // GIR_Coverage, 11201, |
| 117114 | GIR_EraseRootFromParent_Done, |
| 117115 | // Label 5780: @375379 |
| 117116 | GIM_Try, /*On fail goto*//*Label 5781*/ GIMT_Encode4(375508), // Rule ID 11207 // |
| 117117 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117118 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117119 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117120 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117121 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117122 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117123 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117124 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117125 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117126 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117127 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117128 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117129 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117130 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117131 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117132 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117133 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117134 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117135 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117136 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117137 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117148 | GIR_RootConstrainSelectedInstOperands, |
| 117149 | // GIR_Coverage, 11207, |
| 117150 | GIR_EraseRootFromParent_Done, |
| 117151 | // Label 5781: @375508 |
| 117152 | GIM_Try, /*On fail goto*//*Label 5782*/ GIMT_Encode4(375637), // Rule ID 11208 // |
| 117153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117154 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117155 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117156 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117157 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117158 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117159 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117160 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117161 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117162 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117163 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117164 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117165 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117166 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117167 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117168 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117169 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117170 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117171 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117172 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117173 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117184 | GIR_RootConstrainSelectedInstOperands, |
| 117185 | // GIR_Coverage, 11208, |
| 117186 | GIR_EraseRootFromParent_Done, |
| 117187 | // Label 5782: @375637 |
| 117188 | GIM_Try, /*On fail goto*//*Label 5783*/ GIMT_Encode4(375766), // Rule ID 11211 // |
| 117189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117190 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117191 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117192 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117193 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117195 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117196 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117197 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117198 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117199 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117200 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117201 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117202 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117203 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117204 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117205 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117206 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117207 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117208 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117209 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117218 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117220 | GIR_RootConstrainSelectedInstOperands, |
| 117221 | // GIR_Coverage, 11211, |
| 117222 | GIR_EraseRootFromParent_Done, |
| 117223 | // Label 5783: @375766 |
| 117224 | GIM_Try, /*On fail goto*//*Label 5784*/ GIMT_Encode4(375895), // Rule ID 11212 // |
| 117225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117226 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117227 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117228 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117229 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117230 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117231 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117232 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117233 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117234 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117235 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117236 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117237 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117238 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117239 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117240 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117241 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117242 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117243 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117244 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117245 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117256 | GIR_RootConstrainSelectedInstOperands, |
| 117257 | // GIR_Coverage, 11212, |
| 117258 | GIR_EraseRootFromParent_Done, |
| 117259 | // Label 5784: @375895 |
| 117260 | GIM_Try, /*On fail goto*//*Label 5785*/ GIMT_Encode4(376024), // Rule ID 11192 // |
| 117261 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117262 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117263 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117264 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117265 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117266 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117267 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117268 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117269 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117270 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117271 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117272 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117273 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117274 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117275 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117276 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117277 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117278 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117279 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117280 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117281 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117292 | GIR_RootConstrainSelectedInstOperands, |
| 117293 | // GIR_Coverage, 11192, |
| 117294 | GIR_EraseRootFromParent_Done, |
| 117295 | // Label 5785: @376024 |
| 117296 | GIM_Try, /*On fail goto*//*Label 5786*/ GIMT_Encode4(376153), // Rule ID 11193 // |
| 117297 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117298 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117299 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117300 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117301 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117302 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117303 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117304 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117305 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117306 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117307 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117308 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117309 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117310 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117311 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117312 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117313 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117314 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117315 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117316 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117317 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117326 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117328 | GIR_RootConstrainSelectedInstOperands, |
| 117329 | // GIR_Coverage, 11193, |
| 117330 | GIR_EraseRootFromParent_Done, |
| 117331 | // Label 5786: @376153 |
| 117332 | GIM_Try, /*On fail goto*//*Label 5787*/ GIMT_Encode4(376282), // Rule ID 11196 // |
| 117333 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117334 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117335 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117336 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117337 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117338 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117339 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117340 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117341 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117342 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117343 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117344 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117345 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117346 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117347 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117348 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117349 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117350 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117351 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117352 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117353 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117354 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117355 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117364 | GIR_RootConstrainSelectedInstOperands, |
| 117365 | // GIR_Coverage, 11196, |
| 117366 | GIR_EraseRootFromParent_Done, |
| 117367 | // Label 5787: @376282 |
| 117368 | GIM_Try, /*On fail goto*//*Label 5788*/ GIMT_Encode4(376411), // Rule ID 11197 // |
| 117369 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117370 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117371 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117372 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117373 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117374 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117375 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117376 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117377 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117378 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117379 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117380 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117381 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117382 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117383 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117384 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117385 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117386 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117387 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117388 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117389 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117400 | GIR_RootConstrainSelectedInstOperands, |
| 117401 | // GIR_Coverage, 11197, |
| 117402 | GIR_EraseRootFromParent_Done, |
| 117403 | // Label 5788: @376411 |
| 117404 | GIM_Try, /*On fail goto*//*Label 5789*/ GIMT_Encode4(376540), // Rule ID 7333 // |
| 117405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117406 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117407 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117408 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117409 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117410 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117411 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117412 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117413 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117414 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117415 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117416 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117417 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117418 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117419 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117420 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117421 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117422 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117423 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117424 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117425 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117436 | GIR_RootConstrainSelectedInstOperands, |
| 117437 | // GIR_Coverage, 7333, |
| 117438 | GIR_EraseRootFromParent_Done, |
| 117439 | // Label 5789: @376540 |
| 117440 | GIM_Try, /*On fail goto*//*Label 5790*/ GIMT_Encode4(376669), // Rule ID 11206 // |
| 117441 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117442 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117443 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117444 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117445 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117446 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117447 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117448 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117449 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117450 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117451 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117452 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117453 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117454 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117455 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117456 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117457 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117458 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117459 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117460 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117461 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117472 | GIR_RootConstrainSelectedInstOperands, |
| 117473 | // GIR_Coverage, 11206, |
| 117474 | GIR_EraseRootFromParent_Done, |
| 117475 | // Label 5790: @376669 |
| 117476 | GIM_Try, /*On fail goto*//*Label 5791*/ GIMT_Encode4(376798), // Rule ID 11209 // |
| 117477 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117480 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117481 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117482 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117483 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117484 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117485 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117486 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117487 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117488 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117489 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117490 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117491 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117492 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117493 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117494 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117495 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117496 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117497 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117499 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117508 | GIR_RootConstrainSelectedInstOperands, |
| 117509 | // GIR_Coverage, 11209, |
| 117510 | GIR_EraseRootFromParent_Done, |
| 117511 | // Label 5791: @376798 |
| 117512 | GIM_Try, /*On fail goto*//*Label 5792*/ GIMT_Encode4(376927), // Rule ID 11210 // |
| 117513 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117514 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117515 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117516 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117517 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117518 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117519 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117520 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117521 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117522 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117523 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117524 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117525 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117526 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117527 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117528 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117529 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117530 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117531 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117532 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117533 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117534 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117535 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117542 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117544 | GIR_RootConstrainSelectedInstOperands, |
| 117545 | // GIR_Coverage, 11210, |
| 117546 | GIR_EraseRootFromParent_Done, |
| 117547 | // Label 5792: @376927 |
| 117548 | GIM_Try, /*On fail goto*//*Label 5793*/ GIMT_Encode4(377056), // Rule ID 7332 // |
| 117549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117550 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117551 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117552 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117553 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117554 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117555 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117556 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117557 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117558 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117559 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117560 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117561 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117562 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117563 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117564 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117565 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117566 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117567 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117568 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117569 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117578 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117580 | GIR_RootConstrainSelectedInstOperands, |
| 117581 | // GIR_Coverage, 7332, |
| 117582 | GIR_EraseRootFromParent_Done, |
| 117583 | // Label 5793: @377056 |
| 117584 | GIM_Try, /*On fail goto*//*Label 5794*/ GIMT_Encode4(377185), // Rule ID 11191 // |
| 117585 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117586 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117587 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117588 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117589 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117590 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117591 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117592 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117593 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117594 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117595 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117596 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117597 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117598 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117599 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117600 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117601 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117602 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117603 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117604 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117605 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117607 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117608 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117614 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117616 | GIR_RootConstrainSelectedInstOperands, |
| 117617 | // GIR_Coverage, 11191, |
| 117618 | GIR_EraseRootFromParent_Done, |
| 117619 | // Label 5794: @377185 |
| 117620 | GIM_Try, /*On fail goto*//*Label 5795*/ GIMT_Encode4(377314), // Rule ID 11194 // |
| 117621 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117622 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117623 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117624 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117625 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117626 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117627 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117628 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117629 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117630 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117631 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117632 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117633 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117634 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117635 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117636 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117637 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117638 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117639 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117640 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117641 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117650 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117652 | GIR_RootConstrainSelectedInstOperands, |
| 117653 | // GIR_Coverage, 11194, |
| 117654 | GIR_EraseRootFromParent_Done, |
| 117655 | // Label 5795: @377314 |
| 117656 | GIM_Try, /*On fail goto*//*Label 5796*/ GIMT_Encode4(377443), // Rule ID 11195 // |
| 117657 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117658 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117659 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117660 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117661 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117662 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117663 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 117664 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117665 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117666 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117667 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117668 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117669 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117670 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117671 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117672 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117673 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117674 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117675 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117676 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117677 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117688 | GIR_RootConstrainSelectedInstOperands, |
| 117689 | // GIR_Coverage, 11195, |
| 117690 | GIR_EraseRootFromParent_Done, |
| 117691 | // Label 5796: @377443 |
| 117692 | GIM_Try, /*On fail goto*//*Label 5797*/ GIMT_Encode4(377572), // Rule ID 11177 // |
| 117693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117697 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117698 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117699 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117700 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117701 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117702 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117703 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117704 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117705 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117706 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117707 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117708 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117709 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117710 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117711 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117712 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117713 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117714 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117715 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117724 | GIR_RootConstrainSelectedInstOperands, |
| 117725 | // GIR_Coverage, 11177, |
| 117726 | GIR_EraseRootFromParent_Done, |
| 117727 | // Label 5797: @377572 |
| 117728 | GIM_Try, /*On fail goto*//*Label 5798*/ GIMT_Encode4(377701), // Rule ID 11178 // |
| 117729 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117730 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117731 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117732 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117733 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117734 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117735 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117736 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117737 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117738 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117739 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117740 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117741 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117742 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117743 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117744 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117745 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117746 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117747 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117748 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117749 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117751 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117760 | GIR_RootConstrainSelectedInstOperands, |
| 117761 | // GIR_Coverage, 11178, |
| 117762 | GIR_EraseRootFromParent_Done, |
| 117763 | // Label 5798: @377701 |
| 117764 | GIM_Try, /*On fail goto*//*Label 5799*/ GIMT_Encode4(377830), // Rule ID 11181 // |
| 117765 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117766 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117767 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117768 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117769 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117770 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117771 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117772 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117773 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117774 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117775 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117776 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117777 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117778 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117779 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117780 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117781 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117782 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117783 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117784 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117785 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117796 | GIR_RootConstrainSelectedInstOperands, |
| 117797 | // GIR_Coverage, 11181, |
| 117798 | GIR_EraseRootFromParent_Done, |
| 117799 | // Label 5799: @377830 |
| 117800 | GIM_Try, /*On fail goto*//*Label 5800*/ GIMT_Encode4(377959), // Rule ID 11182 // |
| 117801 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117802 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117803 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117804 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117805 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117806 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117807 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117808 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117809 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117810 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117811 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117812 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117813 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117814 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117815 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117816 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117817 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117818 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117819 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117820 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117821 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117830 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117832 | GIR_RootConstrainSelectedInstOperands, |
| 117833 | // GIR_Coverage, 11182, |
| 117834 | GIR_EraseRootFromParent_Done, |
| 117835 | // Label 5800: @377959 |
| 117836 | GIM_Try, /*On fail goto*//*Label 5801*/ GIMT_Encode4(378088), // Rule ID 11162 // |
| 117837 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117838 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117839 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117840 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117841 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117842 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117843 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117844 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117845 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117846 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117847 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117848 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117849 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117850 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117851 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117852 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117853 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117854 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117855 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117856 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117857 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117859 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117866 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117868 | GIR_RootConstrainSelectedInstOperands, |
| 117869 | // GIR_Coverage, 11162, |
| 117870 | GIR_EraseRootFromParent_Done, |
| 117871 | // Label 5801: @378088 |
| 117872 | GIM_Try, /*On fail goto*//*Label 5802*/ GIMT_Encode4(378217), // Rule ID 11163 // |
| 117873 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117874 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117875 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117876 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117877 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117878 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117879 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117880 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117881 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117882 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117883 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117884 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117885 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117886 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117887 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117888 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117889 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117890 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117891 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117892 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117893 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 117897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 117898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 117899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 117900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117902 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117904 | GIR_RootConstrainSelectedInstOperands, |
| 117905 | // GIR_Coverage, 11163, |
| 117906 | GIR_EraseRootFromParent_Done, |
| 117907 | // Label 5802: @378217 |
| 117908 | GIM_Try, /*On fail goto*//*Label 5803*/ GIMT_Encode4(378346), // Rule ID 11166 // |
| 117909 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117910 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117911 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117912 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117913 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117914 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117915 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117916 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117917 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117918 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117919 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117920 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117921 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117922 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117923 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117924 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117925 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117926 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117927 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117928 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117929 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117940 | GIR_RootConstrainSelectedInstOperands, |
| 117941 | // GIR_Coverage, 11166, |
| 117942 | GIR_EraseRootFromParent_Done, |
| 117943 | // Label 5803: @378346 |
| 117944 | GIM_Try, /*On fail goto*//*Label 5804*/ GIMT_Encode4(378475), // Rule ID 11167 // |
| 117945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117946 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117947 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117948 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117949 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117950 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117951 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117952 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117953 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117954 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 117955 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 117956 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117957 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117958 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117959 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117960 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117961 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117962 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117963 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 117964 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 117965 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 117966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 117967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 117968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 117969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 117970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 117971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 117972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 117973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 117974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 117976 | GIR_RootConstrainSelectedInstOperands, |
| 117977 | // GIR_Coverage, 11167, |
| 117978 | GIR_EraseRootFromParent_Done, |
| 117979 | // Label 5804: @378475 |
| 117980 | GIM_Try, /*On fail goto*//*Label 5805*/ GIMT_Encode4(378604), // Rule ID 7331 // |
| 117981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 117982 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 117983 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117984 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 117985 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 117986 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 117987 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 117988 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 117989 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 117990 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 117991 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 117992 | // MIs[3] VOP3Mods:src0:src0_mods |
| 117993 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 117994 | // MIs[3] VOP3Mods:src1:src1_mods |
| 117995 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 117996 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 117997 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 117998 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 117999 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118000 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118001 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118012 | GIR_RootConstrainSelectedInstOperands, |
| 118013 | // GIR_Coverage, 7331, |
| 118014 | GIR_EraseRootFromParent_Done, |
| 118015 | // Label 5805: @378604 |
| 118016 | GIM_Try, /*On fail goto*//*Label 5806*/ GIMT_Encode4(378733), // Rule ID 11176 // |
| 118017 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118018 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118019 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118020 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118021 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118022 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118023 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118024 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118025 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118026 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118027 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118028 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118029 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118030 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118031 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118032 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118033 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118034 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118035 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118036 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118037 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118038 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118039 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118046 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118048 | GIR_RootConstrainSelectedInstOperands, |
| 118049 | // GIR_Coverage, 11176, |
| 118050 | GIR_EraseRootFromParent_Done, |
| 118051 | // Label 5806: @378733 |
| 118052 | GIM_Try, /*On fail goto*//*Label 5807*/ GIMT_Encode4(378862), // Rule ID 11179 // |
| 118053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118054 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118055 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118056 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118057 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118058 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118059 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118060 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118061 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118062 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118063 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118064 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118065 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118066 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118067 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118068 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118069 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118070 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118071 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118072 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118073 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118084 | GIR_RootConstrainSelectedInstOperands, |
| 118085 | // GIR_Coverage, 11179, |
| 118086 | GIR_EraseRootFromParent_Done, |
| 118087 | // Label 5807: @378862 |
| 118088 | GIM_Try, /*On fail goto*//*Label 5808*/ GIMT_Encode4(378991), // Rule ID 11180 // |
| 118089 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118090 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118091 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118092 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118093 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118094 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118095 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118096 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118097 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118098 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118099 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118100 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118101 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118102 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118103 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118104 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118105 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118106 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118107 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118108 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118109 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118120 | GIR_RootConstrainSelectedInstOperands, |
| 118121 | // GIR_Coverage, 11180, |
| 118122 | GIR_EraseRootFromParent_Done, |
| 118123 | // Label 5808: @378991 |
| 118124 | GIM_Try, /*On fail goto*//*Label 5809*/ GIMT_Encode4(379120), // Rule ID 7330 // |
| 118125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118126 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118127 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118128 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118129 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118130 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118131 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118132 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118133 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118134 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118135 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118136 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118137 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118138 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118139 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118140 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118141 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118142 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118143 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118144 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118145 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118154 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118156 | GIR_RootConstrainSelectedInstOperands, |
| 118157 | // GIR_Coverage, 7330, |
| 118158 | GIR_EraseRootFromParent_Done, |
| 118159 | // Label 5809: @379120 |
| 118160 | GIM_Try, /*On fail goto*//*Label 5810*/ GIMT_Encode4(379249), // Rule ID 11161 // |
| 118161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118162 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118163 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118164 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118165 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118166 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118167 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118168 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118169 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118170 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118171 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118172 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118173 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118174 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118175 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118176 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118177 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118178 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118179 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118180 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118181 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118192 | GIR_RootConstrainSelectedInstOperands, |
| 118193 | // GIR_Coverage, 11161, |
| 118194 | GIR_EraseRootFromParent_Done, |
| 118195 | // Label 5810: @379249 |
| 118196 | GIM_Try, /*On fail goto*//*Label 5811*/ GIMT_Encode4(379378), // Rule ID 11164 // |
| 118197 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118198 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118199 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118200 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118201 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118202 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118203 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118204 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118205 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118206 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118207 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118208 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118209 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118210 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118211 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118212 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118213 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118214 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118215 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118216 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118217 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118219 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118228 | GIR_RootConstrainSelectedInstOperands, |
| 118229 | // GIR_Coverage, 11164, |
| 118230 | GIR_EraseRootFromParent_Done, |
| 118231 | // Label 5811: @379378 |
| 118232 | GIM_Try, /*On fail goto*//*Label 5812*/ GIMT_Encode4(379507), // Rule ID 11165 // |
| 118233 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118234 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118235 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118236 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118237 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118238 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 118239 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118240 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118241 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118242 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 118243 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118244 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118245 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 118246 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118247 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 118248 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118249 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118250 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118251 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118252 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118253 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118264 | GIR_RootConstrainSelectedInstOperands, |
| 118265 | // GIR_Coverage, 11165, |
| 118266 | GIR_EraseRootFromParent_Done, |
| 118267 | // Label 5812: @379507 |
| 118268 | GIM_Try, /*On fail goto*//*Label 5813*/ GIMT_Encode4(379636), // Rule ID 11247 // |
| 118269 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118270 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118271 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118272 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118273 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118274 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118275 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118276 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118277 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118278 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118279 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118280 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118281 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118282 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118283 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118284 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118285 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118286 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118287 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118288 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118289 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118298 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118300 | GIR_RootConstrainSelectedInstOperands, |
| 118301 | // GIR_Coverage, 11247, |
| 118302 | GIR_EraseRootFromParent_Done, |
| 118303 | // Label 5813: @379636 |
| 118304 | GIM_Try, /*On fail goto*//*Label 5814*/ GIMT_Encode4(379765), // Rule ID 11248 // |
| 118305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118306 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118307 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118308 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118309 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118310 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118311 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118312 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118313 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118314 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118315 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118316 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118317 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118318 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118319 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118320 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118321 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118322 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118323 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118324 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118325 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118327 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118336 | GIR_RootConstrainSelectedInstOperands, |
| 118337 | // GIR_Coverage, 11248, |
| 118338 | GIR_EraseRootFromParent_Done, |
| 118339 | // Label 5814: @379765 |
| 118340 | GIM_Try, /*On fail goto*//*Label 5815*/ GIMT_Encode4(379894), // Rule ID 11249 // |
| 118341 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118342 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118343 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118344 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118345 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118346 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118347 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118348 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118349 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118350 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118351 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118352 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118353 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118354 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118355 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118356 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118357 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118358 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118359 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118360 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118361 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118372 | GIR_RootConstrainSelectedInstOperands, |
| 118373 | // GIR_Coverage, 11249, |
| 118374 | GIR_EraseRootFromParent_Done, |
| 118375 | // Label 5815: @379894 |
| 118376 | GIM_Try, /*On fail goto*//*Label 5816*/ GIMT_Encode4(380023), // Rule ID 11250 // |
| 118377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118378 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118379 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118380 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118381 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118382 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118383 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118384 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118385 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118386 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118387 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118388 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118389 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118390 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118391 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118392 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118393 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118394 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118395 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118396 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118397 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118408 | GIR_RootConstrainSelectedInstOperands, |
| 118409 | // GIR_Coverage, 11250, |
| 118410 | GIR_EraseRootFromParent_Done, |
| 118411 | // Label 5816: @380023 |
| 118412 | GIM_Try, /*On fail goto*//*Label 5817*/ GIMT_Encode4(380152), // Rule ID 11187 // |
| 118413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118414 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118415 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118416 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118417 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118418 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118419 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118420 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118421 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118422 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118423 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118424 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118425 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118426 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118427 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118428 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118429 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118430 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118431 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118432 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118433 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118444 | GIR_RootConstrainSelectedInstOperands, |
| 118445 | // GIR_Coverage, 11187, |
| 118446 | GIR_EraseRootFromParent_Done, |
| 118447 | // Label 5817: @380152 |
| 118448 | GIM_Try, /*On fail goto*//*Label 5818*/ GIMT_Encode4(380281), // Rule ID 11188 // |
| 118449 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118450 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118451 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118452 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118453 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118454 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118455 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118456 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118457 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118458 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118459 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118460 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118461 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118462 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118463 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118464 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118465 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118466 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118467 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118468 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118469 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118478 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118480 | GIR_RootConstrainSelectedInstOperands, |
| 118481 | // GIR_Coverage, 11188, |
| 118482 | GIR_EraseRootFromParent_Done, |
| 118483 | // Label 5818: @380281 |
| 118484 | GIM_Try, /*On fail goto*//*Label 5819*/ GIMT_Encode4(380410), // Rule ID 11189 // |
| 118485 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118486 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118487 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118488 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118489 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118490 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118491 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118492 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118493 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118494 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118495 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118496 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118497 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118498 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118499 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118500 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118501 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118502 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118503 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118504 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118505 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118514 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118516 | GIR_RootConstrainSelectedInstOperands, |
| 118517 | // GIR_Coverage, 11189, |
| 118518 | GIR_EraseRootFromParent_Done, |
| 118519 | // Label 5819: @380410 |
| 118520 | GIM_Try, /*On fail goto*//*Label 5820*/ GIMT_Encode4(380539), // Rule ID 11190 // |
| 118521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118522 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118523 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118524 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118525 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118526 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118527 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118528 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118529 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118530 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118531 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118532 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118533 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118534 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118535 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118536 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118537 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118538 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118539 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118540 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118541 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118550 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118552 | GIR_RootConstrainSelectedInstOperands, |
| 118553 | // GIR_Coverage, 11190, |
| 118554 | GIR_EraseRootFromParent_Done, |
| 118555 | // Label 5820: @380539 |
| 118556 | GIM_Try, /*On fail goto*//*Label 5821*/ GIMT_Encode4(380668), // Rule ID 11232 // |
| 118557 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118558 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118559 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118560 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118561 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118562 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118563 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118564 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118565 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118566 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118567 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118568 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118569 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118570 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118571 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118572 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118573 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118574 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118575 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118576 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118577 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118586 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118588 | GIR_RootConstrainSelectedInstOperands, |
| 118589 | // GIR_Coverage, 11232, |
| 118590 | GIR_EraseRootFromParent_Done, |
| 118591 | // Label 5821: @380668 |
| 118592 | GIM_Try, /*On fail goto*//*Label 5822*/ GIMT_Encode4(380797), // Rule ID 11233 // |
| 118593 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118594 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118595 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118596 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118597 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118598 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118599 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118600 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118601 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118602 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118603 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118604 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118605 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118606 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118607 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118608 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118609 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118610 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118611 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118612 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118613 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118624 | GIR_RootConstrainSelectedInstOperands, |
| 118625 | // GIR_Coverage, 11233, |
| 118626 | GIR_EraseRootFromParent_Done, |
| 118627 | // Label 5822: @380797 |
| 118628 | GIM_Try, /*On fail goto*//*Label 5823*/ GIMT_Encode4(380926), // Rule ID 11234 // |
| 118629 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118630 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118631 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118632 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118633 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118634 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118635 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118636 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118637 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118638 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118639 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118640 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118641 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118642 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118643 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118644 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118645 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118646 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118647 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118648 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118649 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118660 | GIR_RootConstrainSelectedInstOperands, |
| 118661 | // GIR_Coverage, 11234, |
| 118662 | GIR_EraseRootFromParent_Done, |
| 118663 | // Label 5823: @380926 |
| 118664 | GIM_Try, /*On fail goto*//*Label 5824*/ GIMT_Encode4(381055), // Rule ID 11235 // |
| 118665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118666 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118667 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118668 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118669 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118670 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118671 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118672 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118673 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118674 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118675 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118676 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118677 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118678 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118679 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118680 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118681 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118682 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118683 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118684 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118685 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118696 | GIR_RootConstrainSelectedInstOperands, |
| 118697 | // GIR_Coverage, 11235, |
| 118698 | GIR_EraseRootFromParent_Done, |
| 118699 | // Label 5824: @381055 |
| 118700 | GIM_Try, /*On fail goto*//*Label 5825*/ GIMT_Encode4(381184), // Rule ID 11172 // |
| 118701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118702 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118703 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118704 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118705 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118706 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118707 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118708 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118709 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118710 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118711 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118712 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118713 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118714 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118715 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118716 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118717 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118718 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118719 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118720 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118721 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118730 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118731 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118732 | GIR_RootConstrainSelectedInstOperands, |
| 118733 | // GIR_Coverage, 11172, |
| 118734 | GIR_EraseRootFromParent_Done, |
| 118735 | // Label 5825: @381184 |
| 118736 | GIM_Try, /*On fail goto*//*Label 5826*/ GIMT_Encode4(381313), // Rule ID 11173 // |
| 118737 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118738 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118739 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118740 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118741 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118742 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118743 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118744 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118745 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118746 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118747 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118748 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118749 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118750 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118751 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118752 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118753 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118754 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118755 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118756 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118757 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118759 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 118763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 118764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118767 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118768 | GIR_RootConstrainSelectedInstOperands, |
| 118769 | // GIR_Coverage, 11173, |
| 118770 | GIR_EraseRootFromParent_Done, |
| 118771 | // Label 5826: @381313 |
| 118772 | GIM_Try, /*On fail goto*//*Label 5827*/ GIMT_Encode4(381442), // Rule ID 11174 // |
| 118773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118777 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118778 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118779 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118780 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118781 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118782 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118783 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118784 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118785 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118786 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118787 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118788 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118789 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118790 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118791 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118792 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118793 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118803 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118804 | GIR_RootConstrainSelectedInstOperands, |
| 118805 | // GIR_Coverage, 11174, |
| 118806 | GIR_EraseRootFromParent_Done, |
| 118807 | // Label 5827: @381442 |
| 118808 | GIM_Try, /*On fail goto*//*Label 5828*/ GIMT_Encode4(381571), // Rule ID 11175 // |
| 118809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118810 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118811 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118812 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118813 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118814 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 118815 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 118816 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118817 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118818 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118819 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118820 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118821 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118822 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118823 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118824 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118825 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118826 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118827 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118828 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118829 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 118833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 118834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 118837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 118838 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118839 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118840 | GIR_RootConstrainSelectedInstOperands, |
| 118841 | // GIR_Coverage, 11175, |
| 118842 | GIR_EraseRootFromParent_Done, |
| 118843 | // Label 5828: @381571 |
| 118844 | GIM_Try, /*On fail goto*//*Label 5829*/ GIMT_Encode4(381700), // Rule ID 11243 // |
| 118845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118846 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118847 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118848 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118849 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118850 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 118851 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118852 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118853 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118854 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118855 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118856 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118857 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118858 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118859 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118860 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118861 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118862 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118863 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118864 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118865 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118876 | GIR_RootConstrainSelectedInstOperands, |
| 118877 | // GIR_Coverage, 11243, |
| 118878 | GIR_EraseRootFromParent_Done, |
| 118879 | // Label 5829: @381700 |
| 118880 | GIM_Try, /*On fail goto*//*Label 5830*/ GIMT_Encode4(381829), // Rule ID 11244 // |
| 118881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118883 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118884 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118885 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118886 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 118887 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118888 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118889 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118890 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118891 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118892 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118893 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118894 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118895 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118896 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118897 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118898 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118899 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118900 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118901 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 118905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 118906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 118907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 118908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118912 | GIR_RootConstrainSelectedInstOperands, |
| 118913 | // GIR_Coverage, 11244, |
| 118914 | GIR_EraseRootFromParent_Done, |
| 118915 | // Label 5830: @381829 |
| 118916 | GIM_Try, /*On fail goto*//*Label 5831*/ GIMT_Encode4(381958), // Rule ID 11245 // |
| 118917 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118918 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118919 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118920 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118921 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118922 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 118923 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118924 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118925 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118926 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118927 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118928 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118929 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118930 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118931 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118932 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118933 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118934 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118935 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118936 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118937 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118946 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118948 | GIR_RootConstrainSelectedInstOperands, |
| 118949 | // GIR_Coverage, 11245, |
| 118950 | GIR_EraseRootFromParent_Done, |
| 118951 | // Label 5831: @381958 |
| 118952 | GIM_Try, /*On fail goto*//*Label 5832*/ GIMT_Encode4(382087), // Rule ID 11246 // |
| 118953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118954 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118955 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118956 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118957 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118958 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 118959 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118960 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118961 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118962 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118963 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 118964 | // MIs[3] VOP3Mods:src1:src1_mods |
| 118965 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 118966 | // MIs[3] VOP3Mods:src0:src0_mods |
| 118967 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 118968 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 118969 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 118970 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 118971 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 118972 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 118973 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 118974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 118975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 118976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 118977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 118978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 118979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 118980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 118981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 118982 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 118984 | GIR_RootConstrainSelectedInstOperands, |
| 118985 | // GIR_Coverage, 11246, |
| 118986 | GIR_EraseRootFromParent_Done, |
| 118987 | // Label 5832: @382087 |
| 118988 | GIM_Try, /*On fail goto*//*Label 5833*/ GIMT_Encode4(382216), // Rule ID 11183 // |
| 118989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 118990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 118991 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 118992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 118993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 118994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 118995 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 118996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 118997 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 118998 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 118999 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119000 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119002 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119003 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119004 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119005 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119006 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119007 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119008 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119009 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119020 | GIR_RootConstrainSelectedInstOperands, |
| 119021 | // GIR_Coverage, 11183, |
| 119022 | GIR_EraseRootFromParent_Done, |
| 119023 | // Label 5833: @382216 |
| 119024 | GIM_Try, /*On fail goto*//*Label 5834*/ GIMT_Encode4(382345), // Rule ID 11184 // |
| 119025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119029 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119030 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119031 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119032 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119033 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119034 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119035 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119036 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119037 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119038 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119039 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119040 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119041 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119042 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119043 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119044 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119045 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119056 | GIR_RootConstrainSelectedInstOperands, |
| 119057 | // GIR_Coverage, 11184, |
| 119058 | GIR_EraseRootFromParent_Done, |
| 119059 | // Label 5834: @382345 |
| 119060 | GIM_Try, /*On fail goto*//*Label 5835*/ GIMT_Encode4(382474), // Rule ID 11185 // |
| 119061 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119062 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119063 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119064 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119065 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119066 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119067 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119068 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119069 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119070 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119071 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119072 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119073 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119074 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119075 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119076 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119077 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119078 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119079 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119080 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119081 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119092 | GIR_RootConstrainSelectedInstOperands, |
| 119093 | // GIR_Coverage, 11185, |
| 119094 | GIR_EraseRootFromParent_Done, |
| 119095 | // Label 5835: @382474 |
| 119096 | GIM_Try, /*On fail goto*//*Label 5836*/ GIMT_Encode4(382603), // Rule ID 11186 // |
| 119097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119098 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119099 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119100 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119101 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119102 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119103 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119104 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119105 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119106 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119107 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119108 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119109 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119110 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119111 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119112 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119113 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119114 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119115 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119116 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119117 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119128 | GIR_RootConstrainSelectedInstOperands, |
| 119129 | // GIR_Coverage, 11186, |
| 119130 | GIR_EraseRootFromParent_Done, |
| 119131 | // Label 5836: @382603 |
| 119132 | GIM_Try, /*On fail goto*//*Label 5837*/ GIMT_Encode4(382732), // Rule ID 11228 // |
| 119133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119134 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119135 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119136 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119137 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119138 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119139 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119140 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119141 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119142 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119143 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119144 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119145 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119146 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119147 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119148 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119149 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119150 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119151 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119152 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119153 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119162 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119164 | GIR_RootConstrainSelectedInstOperands, |
| 119165 | // GIR_Coverage, 11228, |
| 119166 | GIR_EraseRootFromParent_Done, |
| 119167 | // Label 5837: @382732 |
| 119168 | GIM_Try, /*On fail goto*//*Label 5838*/ GIMT_Encode4(382861), // Rule ID 11229 // |
| 119169 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119170 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119171 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119172 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119173 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119174 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119175 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119176 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119177 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119178 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119179 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119180 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119181 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119182 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119183 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119184 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119185 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119186 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119187 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119188 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119189 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119190 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119191 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119198 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119200 | GIR_RootConstrainSelectedInstOperands, |
| 119201 | // GIR_Coverage, 11229, |
| 119202 | GIR_EraseRootFromParent_Done, |
| 119203 | // Label 5838: @382861 |
| 119204 | GIM_Try, /*On fail goto*//*Label 5839*/ GIMT_Encode4(382990), // Rule ID 11230 // |
| 119205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119206 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119207 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119208 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119209 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119210 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119211 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119212 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119213 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119214 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119215 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119216 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119217 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119218 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119219 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119220 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119221 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119222 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119223 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119224 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119225 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119226 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119227 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119234 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119236 | GIR_RootConstrainSelectedInstOperands, |
| 119237 | // GIR_Coverage, 11230, |
| 119238 | GIR_EraseRootFromParent_Done, |
| 119239 | // Label 5839: @382990 |
| 119240 | GIM_Try, /*On fail goto*//*Label 5840*/ GIMT_Encode4(383119), // Rule ID 11231 // |
| 119241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119242 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119243 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119244 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119245 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119246 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119247 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119248 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119249 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119250 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119251 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119252 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119253 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119254 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119255 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119256 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119257 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119258 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119259 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119260 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119261 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119272 | GIR_RootConstrainSelectedInstOperands, |
| 119273 | // GIR_Coverage, 11231, |
| 119274 | GIR_EraseRootFromParent_Done, |
| 119275 | // Label 5840: @383119 |
| 119276 | GIM_Try, /*On fail goto*//*Label 5841*/ GIMT_Encode4(383248), // Rule ID 11168 // |
| 119277 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119278 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119279 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119280 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119281 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119282 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119283 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119284 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119285 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119286 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119287 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119288 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119289 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119290 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119291 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119292 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119293 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119294 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119295 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119296 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119297 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119308 | GIR_RootConstrainSelectedInstOperands, |
| 119309 | // GIR_Coverage, 11168, |
| 119310 | GIR_EraseRootFromParent_Done, |
| 119311 | // Label 5841: @383248 |
| 119312 | GIM_Try, /*On fail goto*//*Label 5842*/ GIMT_Encode4(383377), // Rule ID 11169 // |
| 119313 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119314 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119315 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119316 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119317 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119318 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119319 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119320 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119321 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119322 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119323 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119324 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119325 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119326 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119327 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119328 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119329 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119330 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119331 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119332 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119333 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119344 | GIR_RootConstrainSelectedInstOperands, |
| 119345 | // GIR_Coverage, 11169, |
| 119346 | GIR_EraseRootFromParent_Done, |
| 119347 | // Label 5842: @383377 |
| 119348 | GIM_Try, /*On fail goto*//*Label 5843*/ GIMT_Encode4(383506), // Rule ID 11170 // |
| 119349 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119350 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119351 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119352 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119353 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119354 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119355 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119356 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119357 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119358 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119359 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119360 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119361 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119362 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119363 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119364 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119365 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119366 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119367 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119368 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119369 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119380 | GIR_RootConstrainSelectedInstOperands, |
| 119381 | // GIR_Coverage, 11170, |
| 119382 | GIR_EraseRootFromParent_Done, |
| 119383 | // Label 5843: @383506 |
| 119384 | GIM_Try, /*On fail goto*//*Label 5844*/ GIMT_Encode4(383635), // Rule ID 11171 // |
| 119385 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119386 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119387 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119388 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119389 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119390 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119391 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 119392 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119393 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119394 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 119395 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119396 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119397 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 119398 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119399 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 119400 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fminnum_like_nnan), |
| 119401 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119402 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119403 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119404 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119405 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fminnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119406 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 119407 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119414 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119416 | GIR_RootConstrainSelectedInstOperands, |
| 119417 | // GIR_Coverage, 11171, |
| 119418 | GIR_EraseRootFromParent_Done, |
| 119419 | // Label 5844: @383635 |
| 119420 | GIM_Try, /*On fail goto*//*Label 5845*/ GIMT_Encode4(383747), // Rule ID 11936 // |
| 119421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119423 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119424 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 119425 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119426 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119427 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119428 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119429 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119430 | GIM_CheckHasOneUse, /*MI*/2, |
| 119431 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 119432 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119433 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119434 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119435 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119436 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 119442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 119443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 119444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 119445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119446 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119447 | GIR_RootConstrainSelectedInstOperands, |
| 119448 | // GIR_Coverage, 11936, |
| 119449 | GIR_EraseRootFromParent_Done, |
| 119450 | // Label 5845: @383747 |
| 119451 | GIM_Try, /*On fail goto*//*Label 5846*/ GIMT_Encode4(383859), // Rule ID 11935 // |
| 119452 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119453 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119454 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119455 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 119456 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119458 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119460 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119461 | GIM_CheckHasOneUse, /*MI*/2, |
| 119462 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 119463 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119464 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119465 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119466 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119467 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119472 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 119473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 119474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 119475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 119476 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119477 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119478 | GIR_RootConstrainSelectedInstOperands, |
| 119479 | // GIR_Coverage, 11935, |
| 119480 | GIR_EraseRootFromParent_Done, |
| 119481 | // Label 5846: @383859 |
| 119482 | GIM_Try, /*On fail goto*//*Label 5847*/ GIMT_Encode4(383971), // Rule ID 7405 // |
| 119483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119485 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119486 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 119487 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119488 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119489 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119490 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119491 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119492 | GIM_CheckHasOneUse, /*MI*/2, |
| 119493 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 119494 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119495 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119496 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119497 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119498 | // (fminnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119509 | GIR_RootConstrainSelectedInstOperands, |
| 119510 | // GIR_Coverage, 7405, |
| 119511 | GIR_EraseRootFromParent_Done, |
| 119512 | // Label 5847: @383971 |
| 119513 | GIM_Try, /*On fail goto*//*Label 5848*/ GIMT_Encode4(384083), // Rule ID 7404 // |
| 119514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119516 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119517 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 119518 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 119520 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119521 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 119522 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 119523 | GIM_CheckHasOneUse, /*MI*/2, |
| 119524 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 119525 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 119526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119527 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119528 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119529 | // (fminnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119539 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119540 | GIR_RootConstrainSelectedInstOperands, |
| 119541 | // GIR_Coverage, 7404, |
| 119542 | GIR_EraseRootFromParent_Done, |
| 119543 | // Label 5848: @384083 |
| 119544 | GIM_Try, /*On fail goto*//*Label 5849*/ GIMT_Encode4(384179), // Rule ID 11920 // |
| 119545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119547 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119548 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119549 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119550 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119551 | GIM_CheckHasOneUse, /*MI*/1, |
| 119552 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119554 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119555 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119556 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 119562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 119563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 119564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 119565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119566 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119567 | GIR_RootConstrainSelectedInstOperands, |
| 119568 | // GIR_Coverage, 11920, |
| 119569 | GIR_EraseRootFromParent_Done, |
| 119570 | // Label 5849: @384179 |
| 119571 | GIM_Try, /*On fail goto*//*Label 5850*/ GIMT_Encode4(384275), // Rule ID 11919 // |
| 119572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119574 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 119575 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119576 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119577 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119578 | GIM_CheckHasOneUse, /*MI*/1, |
| 119579 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119581 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119582 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119583 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 119589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 119590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 119591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 119592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119594 | GIR_RootConstrainSelectedInstOperands, |
| 119595 | // GIR_Coverage, 11919, |
| 119596 | GIR_EraseRootFromParent_Done, |
| 119597 | // Label 5850: @384275 |
| 119598 | GIM_Try, /*On fail goto*//*Label 5851*/ GIMT_Encode4(384371), // Rule ID 7389 // |
| 119599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119600 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119601 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119602 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119603 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119604 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119605 | GIM_CheckHasOneUse, /*MI*/1, |
| 119606 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119607 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119608 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119609 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119610 | // (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119621 | GIR_RootConstrainSelectedInstOperands, |
| 119622 | // GIR_Coverage, 7389, |
| 119623 | GIR_EraseRootFromParent_Done, |
| 119624 | // Label 5851: @384371 |
| 119625 | GIM_Try, /*On fail goto*//*Label 5852*/ GIMT_Encode4(384467), // Rule ID 7388 // |
| 119626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 119627 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119628 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119629 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119630 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 119631 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 119632 | GIM_CheckHasOneUse, /*MI*/1, |
| 119633 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 119634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119635 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119636 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119637 | // (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaxnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MAXMIN_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_F32_e64), |
| 119639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119648 | GIR_RootConstrainSelectedInstOperands, |
| 119649 | // GIR_Coverage, 7388, |
| 119650 | GIR_EraseRootFromParent_Done, |
| 119651 | // Label 5852: @384467 |
| 119652 | GIM_Try, /*On fail goto*//*Label 5853*/ GIMT_Encode4(384502), // Rule ID 92 // |
| 119653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 119654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 119655 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 119656 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 119657 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18519), |
| 119658 | // (fminnum_ieee:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18519>> => (S_MIN_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 119659 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_F32), |
| 119660 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 119661 | GIR_RootConstrainSelectedInstOperands, |
| 119662 | // GIR_Coverage, 92, |
| 119663 | GIR_Done, |
| 119664 | // Label 5853: @384502 |
| 119665 | GIM_Try, /*On fail goto*//*Label 5854*/ GIMT_Encode4(384562), // Rule ID 737 // |
| 119666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119667 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119669 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64), |
| 119671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 119673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 119675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 119677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 119678 | GIR_RootConstrainSelectedInstOperands, |
| 119679 | // GIR_Coverage, 737, |
| 119680 | GIR_EraseRootFromParent_Done, |
| 119681 | // Label 5854: @384562 |
| 119682 | GIM_Try, /*On fail goto*//*Label 5855*/ GIMT_Encode4(384622), // Rule ID 8057 // |
| 119683 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119686 | // (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F32_e64), |
| 119688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 119690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 119692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 119694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 119695 | GIR_RootConstrainSelectedInstOperands, |
| 119696 | // GIR_Coverage, 8057, |
| 119697 | GIR_EraseRootFromParent_Done, |
| 119698 | // Label 5855: @384622 |
| 119699 | GIM_Reject, |
| 119700 | // Label 5716: @384623 |
| 119701 | GIM_Reject, |
| 119702 | // Label 5570: @384624 |
| 119703 | GIM_Try, /*On fail goto*//*Label 5856*/ GIMT_Encode4(384876), |
| 119704 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 119705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 119706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 119707 | GIM_Try, /*On fail goto*//*Label 5857*/ GIMT_Encode4(384698), // Rule ID 838 // |
| 119708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 119709 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119710 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119711 | // (fminnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119712 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64), |
| 119713 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 119715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 119717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 119719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 119720 | GIR_RootConstrainSelectedInstOperands, |
| 119721 | // GIR_Coverage, 838, |
| 119722 | GIR_EraseRootFromParent_Done, |
| 119723 | // Label 5857: @384698 |
| 119724 | GIM_Try, /*On fail goto*//*Label 5858*/ GIMT_Encode4(384757), // Rule ID 857 // |
| 119725 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 119726 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119727 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119728 | // (fminnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64), |
| 119730 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 119732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 119734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 119736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 119737 | GIR_RootConstrainSelectedInstOperands, |
| 119738 | // GIR_Coverage, 857, |
| 119739 | GIR_EraseRootFromParent_Done, |
| 119740 | // Label 5858: @384757 |
| 119741 | GIM_Try, /*On fail goto*//*Label 5859*/ GIMT_Encode4(384816), // Rule ID 8083 // |
| 119742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 119743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119745 | // (fminnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_NUM_F64_e64), |
| 119747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 119749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 119751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 119753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 119754 | GIR_RootConstrainSelectedInstOperands, |
| 119755 | // GIR_Coverage, 8083, |
| 119756 | GIR_EraseRootFromParent_Done, |
| 119757 | // Label 5859: @384816 |
| 119758 | GIM_Try, /*On fail goto*//*Label 5860*/ GIMT_Encode4(384875), // Rule ID 8097 // |
| 119759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 119760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119761 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 119762 | // (fminnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MIN_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 119763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64), |
| 119764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 119766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 119768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 119770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 119771 | GIR_RootConstrainSelectedInstOperands, |
| 119772 | // GIR_Coverage, 8097, |
| 119773 | GIR_EraseRootFromParent_Done, |
| 119774 | // Label 5860: @384875 |
| 119775 | GIM_Reject, |
| 119776 | // Label 5856: @384876 |
| 119777 | GIM_Reject, |
| 119778 | // Label 5571: @384877 |
| 119779 | GIM_Try, /*On fail goto*//*Label 5861*/ GIMT_Encode4(384948), // Rule ID 963 // |
| 119780 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 119781 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 119782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119783 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 119784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 119785 | // (fminnum_ieee:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MIN_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 119786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_F16), |
| 119787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 119789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 119791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119792 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119793 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119794 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119797 | GIR_RootConstrainSelectedInstOperands, |
| 119798 | // GIR_Coverage, 963, |
| 119799 | GIR_EraseRootFromParent_Done, |
| 119800 | // Label 5861: @384948 |
| 119801 | GIM_Reject, |
| 119802 | // Label 5572: @384949 |
| 119803 | GIM_Reject, |
| 119804 | // Label 83: @384950 |
| 119805 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 5866*/ GIMT_Encode4(421288), |
| 119806 | /*GILLT_s16*//*Label 5862*/ GIMT_Encode4(384977), |
| 119807 | /*GILLT_s32*//*Label 5863*/ GIMT_Encode4(403451), |
| 119808 | /*GILLT_s64*//*Label 5864*/ GIMT_Encode4(420963), |
| 119809 | /*GILLT_v2s16*//*Label 5865*/ GIMT_Encode4(421216), |
| 119810 | // Label 5862: @384977 |
| 119811 | GIM_Try, /*On fail goto*//*Label 5867*/ GIMT_Encode4(403450), |
| 119812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 119813 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 119814 | GIM_Try, /*On fail goto*//*Label 5868*/ GIMT_Encode4(385123), // Rule ID 11537 // |
| 119815 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 119816 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119817 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119818 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119819 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119820 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 119821 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 119822 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119823 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 119824 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 119825 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 119826 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119827 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119828 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 119829 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 119831 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 119832 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119833 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119834 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119835 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119836 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 119838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119845 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119846 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119848 | GIR_RootConstrainSelectedInstOperands, |
| 119849 | // GIR_Coverage, 11537, |
| 119850 | GIR_EraseRootFromParent_Done, |
| 119851 | // Label 5868: @385123 |
| 119852 | GIM_Try, /*On fail goto*//*Label 5869*/ GIMT_Encode4(385258), // Rule ID 11538 // |
| 119853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 119854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119855 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119856 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119857 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119858 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 119859 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 119860 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119861 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 119862 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 119863 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 119864 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119865 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119866 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 119867 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 119869 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 119870 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119871 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119872 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119873 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119874 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 119876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119883 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119886 | GIR_RootConstrainSelectedInstOperands, |
| 119887 | // GIR_Coverage, 11538, |
| 119888 | GIR_EraseRootFromParent_Done, |
| 119889 | // Label 5869: @385258 |
| 119890 | GIM_Try, /*On fail goto*//*Label 5870*/ GIMT_Encode4(385393), // Rule ID 11541 // |
| 119891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 119892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119894 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119895 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119896 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 119897 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 119898 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119899 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 119900 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 119901 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 119902 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119903 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119904 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 119905 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 119907 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 119908 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119909 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119910 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119911 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119912 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 119914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119922 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119924 | GIR_RootConstrainSelectedInstOperands, |
| 119925 | // GIR_Coverage, 11541, |
| 119926 | GIR_EraseRootFromParent_Done, |
| 119927 | // Label 5870: @385393 |
| 119928 | GIM_Try, /*On fail goto*//*Label 5871*/ GIMT_Encode4(385528), // Rule ID 11542 // |
| 119929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 119930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119934 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 119935 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 119936 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119937 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 119938 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 119939 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 119940 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 119941 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119942 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 119943 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 119945 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 119946 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119948 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119949 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119950 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 119952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 119954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 119955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 119956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 119957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119962 | GIR_RootConstrainSelectedInstOperands, |
| 119963 | // GIR_Coverage, 11542, |
| 119964 | GIR_EraseRootFromParent_Done, |
| 119965 | // Label 5871: @385528 |
| 119966 | GIM_Try, /*On fail goto*//*Label 5872*/ GIMT_Encode4(385663), // Rule ID 11522 // |
| 119967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 119968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 119969 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 119970 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119971 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 119972 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 119973 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 119974 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 119975 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 119976 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 119977 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 119978 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 119979 | // MIs[3] VOP3Mods:src0:src0_mods |
| 119980 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 119981 | // MIs[3] VOP3Mods:src1:src1_mods |
| 119982 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 119983 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 119984 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 119985 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 119986 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 119987 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 119988 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 119989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 119990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 119991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 119992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 119993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 119994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 119995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 119996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 119997 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 119999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120000 | GIR_RootConstrainSelectedInstOperands, |
| 120001 | // GIR_Coverage, 11522, |
| 120002 | GIR_EraseRootFromParent_Done, |
| 120003 | // Label 5872: @385663 |
| 120004 | GIM_Try, /*On fail goto*//*Label 5873*/ GIMT_Encode4(385798), // Rule ID 11523 // |
| 120005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120007 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120008 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120009 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120010 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120011 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120012 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120013 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120014 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120015 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120016 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120017 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120018 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120019 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120020 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120021 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120022 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120023 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120024 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120025 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120026 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120035 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120036 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120038 | GIR_RootConstrainSelectedInstOperands, |
| 120039 | // GIR_Coverage, 11523, |
| 120040 | GIR_EraseRootFromParent_Done, |
| 120041 | // Label 5873: @385798 |
| 120042 | GIM_Try, /*On fail goto*//*Label 5874*/ GIMT_Encode4(385933), // Rule ID 11526 // |
| 120043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120045 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120046 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120047 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120048 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120049 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120050 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120051 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120052 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120053 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120054 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120055 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120056 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120057 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120059 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120060 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120061 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120062 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120063 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120064 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120067 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120074 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120076 | GIR_RootConstrainSelectedInstOperands, |
| 120077 | // GIR_Coverage, 11526, |
| 120078 | GIR_EraseRootFromParent_Done, |
| 120079 | // Label 5874: @385933 |
| 120080 | GIM_Try, /*On fail goto*//*Label 5875*/ GIMT_Encode4(386068), // Rule ID 11527 // |
| 120081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120084 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120086 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120087 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120088 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120089 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120090 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120091 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120092 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120093 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120094 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120095 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120096 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120097 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120098 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120099 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120100 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120101 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120102 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120114 | GIR_RootConstrainSelectedInstOperands, |
| 120115 | // GIR_Coverage, 11527, |
| 120116 | GIR_EraseRootFromParent_Done, |
| 120117 | // Label 5875: @386068 |
| 120118 | GIM_Try, /*On fail goto*//*Label 5876*/ GIMT_Encode4(386203), // Rule ID 7355 // |
| 120119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120121 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120122 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120123 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120124 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120125 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120126 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120127 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120128 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120129 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120130 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120131 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120132 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120133 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120134 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120135 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120136 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120137 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120138 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120139 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120140 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120152 | GIR_RootConstrainSelectedInstOperands, |
| 120153 | // GIR_Coverage, 7355, |
| 120154 | GIR_EraseRootFromParent_Done, |
| 120155 | // Label 5876: @386203 |
| 120156 | GIM_Try, /*On fail goto*//*Label 5877*/ GIMT_Encode4(386338), // Rule ID 11536 // |
| 120157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120158 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120159 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120160 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120161 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120162 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120163 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120164 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120165 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120166 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120167 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120168 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120169 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120170 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120171 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120172 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120173 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120174 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120175 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120176 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120177 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120178 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120187 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120188 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120190 | GIR_RootConstrainSelectedInstOperands, |
| 120191 | // GIR_Coverage, 11536, |
| 120192 | GIR_EraseRootFromParent_Done, |
| 120193 | // Label 5877: @386338 |
| 120194 | GIM_Try, /*On fail goto*//*Label 5878*/ GIMT_Encode4(386473), // Rule ID 11539 // |
| 120195 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120197 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120198 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120199 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120200 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120201 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120202 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120203 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120204 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120205 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120206 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120207 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120208 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120209 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120211 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120212 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120213 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120214 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120215 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120216 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120218 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120219 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120225 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120226 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120228 | GIR_RootConstrainSelectedInstOperands, |
| 120229 | // GIR_Coverage, 11539, |
| 120230 | GIR_EraseRootFromParent_Done, |
| 120231 | // Label 5878: @386473 |
| 120232 | GIM_Try, /*On fail goto*//*Label 5879*/ GIMT_Encode4(386608), // Rule ID 11540 // |
| 120233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120235 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120236 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120237 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120238 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120239 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120240 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120241 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120242 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120243 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120244 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120245 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120246 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120247 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120248 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120249 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120250 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120251 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120252 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120253 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120254 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120266 | GIR_RootConstrainSelectedInstOperands, |
| 120267 | // GIR_Coverage, 11540, |
| 120268 | GIR_EraseRootFromParent_Done, |
| 120269 | // Label 5879: @386608 |
| 120270 | GIM_Try, /*On fail goto*//*Label 5880*/ GIMT_Encode4(386743), // Rule ID 7354 // |
| 120271 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120273 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120274 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120275 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120276 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120277 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120278 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120279 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120280 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120281 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120282 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120283 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120284 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120285 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120286 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120287 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120288 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120289 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120290 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120291 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120292 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120304 | GIR_RootConstrainSelectedInstOperands, |
| 120305 | // GIR_Coverage, 7354, |
| 120306 | GIR_EraseRootFromParent_Done, |
| 120307 | // Label 5880: @386743 |
| 120308 | GIM_Try, /*On fail goto*//*Label 5881*/ GIMT_Encode4(386878), // Rule ID 11521 // |
| 120309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120312 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120314 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120315 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120316 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120317 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120318 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120319 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120320 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120321 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120322 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120323 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120325 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120326 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120327 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120328 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120329 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120330 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120342 | GIR_RootConstrainSelectedInstOperands, |
| 120343 | // GIR_Coverage, 11521, |
| 120344 | GIR_EraseRootFromParent_Done, |
| 120345 | // Label 5881: @386878 |
| 120346 | GIM_Try, /*On fail goto*//*Label 5882*/ GIMT_Encode4(387013), // Rule ID 11524 // |
| 120347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120349 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120350 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120351 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120352 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120353 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120354 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120355 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120356 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120357 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120358 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120359 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120360 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120361 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120363 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120364 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120365 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120366 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120367 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120368 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120377 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120380 | GIR_RootConstrainSelectedInstOperands, |
| 120381 | // GIR_Coverage, 11524, |
| 120382 | GIR_EraseRootFromParent_Done, |
| 120383 | // Label 5882: @387013 |
| 120384 | GIM_Try, /*On fail goto*//*Label 5883*/ GIMT_Encode4(387148), // Rule ID 11525 // |
| 120385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120386 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120387 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120388 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120389 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120390 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120391 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120392 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120393 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120394 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120395 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120396 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120397 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120398 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120399 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120400 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120401 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120402 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120403 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120404 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120405 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120406 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120408 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120415 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120416 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120418 | GIR_RootConstrainSelectedInstOperands, |
| 120419 | // GIR_Coverage, 11525, |
| 120420 | GIR_EraseRootFromParent_Done, |
| 120421 | // Label 5883: @387148 |
| 120422 | GIM_Try, /*On fail goto*//*Label 5884*/ GIMT_Encode4(387283), // Rule ID 11507 // |
| 120423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120425 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120426 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120427 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120428 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120429 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120430 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120431 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120432 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120433 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120434 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120435 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120436 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120437 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120438 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120439 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120440 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120441 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120442 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120443 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120444 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120445 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120446 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120453 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120454 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120456 | GIR_RootConstrainSelectedInstOperands, |
| 120457 | // GIR_Coverage, 11507, |
| 120458 | GIR_EraseRootFromParent_Done, |
| 120459 | // Label 5884: @387283 |
| 120460 | GIM_Try, /*On fail goto*//*Label 5885*/ GIMT_Encode4(387418), // Rule ID 11508 // |
| 120461 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120463 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120464 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120465 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120466 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120467 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120468 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120469 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120470 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120471 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120472 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120473 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120474 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120475 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120476 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120477 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120478 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120479 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120480 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120481 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120482 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120494 | GIR_RootConstrainSelectedInstOperands, |
| 120495 | // GIR_Coverage, 11508, |
| 120496 | GIR_EraseRootFromParent_Done, |
| 120497 | // Label 5885: @387418 |
| 120498 | GIM_Try, /*On fail goto*//*Label 5886*/ GIMT_Encode4(387553), // Rule ID 11511 // |
| 120499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120501 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120502 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120503 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120504 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120505 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120506 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120507 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120508 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120509 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120510 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120511 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120512 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120513 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120514 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120515 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120516 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120517 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120518 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120519 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120520 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120532 | GIR_RootConstrainSelectedInstOperands, |
| 120533 | // GIR_Coverage, 11511, |
| 120534 | GIR_EraseRootFromParent_Done, |
| 120535 | // Label 5886: @387553 |
| 120536 | GIM_Try, /*On fail goto*//*Label 5887*/ GIMT_Encode4(387688), // Rule ID 11512 // |
| 120537 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120539 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120540 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120541 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120542 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120543 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120544 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120545 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120546 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120547 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120548 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120549 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120550 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120551 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120553 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120554 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120555 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120556 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120557 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120558 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120570 | GIR_RootConstrainSelectedInstOperands, |
| 120571 | // GIR_Coverage, 11512, |
| 120572 | GIR_EraseRootFromParent_Done, |
| 120573 | // Label 5887: @387688 |
| 120574 | GIM_Try, /*On fail goto*//*Label 5888*/ GIMT_Encode4(387823), // Rule ID 11492 // |
| 120575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120577 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120578 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120579 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120580 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120581 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120582 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120583 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120584 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120585 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120586 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120587 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120588 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120589 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120591 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120592 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120593 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120594 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120595 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120596 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120605 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120606 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120608 | GIR_RootConstrainSelectedInstOperands, |
| 120609 | // GIR_Coverage, 11492, |
| 120610 | GIR_EraseRootFromParent_Done, |
| 120611 | // Label 5888: @387823 |
| 120612 | GIM_Try, /*On fail goto*//*Label 5889*/ GIMT_Encode4(387958), // Rule ID 11493 // |
| 120613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120616 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120617 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120618 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120619 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120620 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120621 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120622 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120623 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120624 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120625 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120626 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120627 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120629 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120630 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120631 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120632 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120633 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120634 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120646 | GIR_RootConstrainSelectedInstOperands, |
| 120647 | // GIR_Coverage, 11493, |
| 120648 | GIR_EraseRootFromParent_Done, |
| 120649 | // Label 5889: @387958 |
| 120650 | GIM_Try, /*On fail goto*//*Label 5890*/ GIMT_Encode4(388093), // Rule ID 11496 // |
| 120651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120653 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120654 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120655 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120656 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120657 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120658 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120659 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120660 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120661 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120662 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120663 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120664 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120665 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120666 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120667 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120668 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120669 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120670 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120671 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120672 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120681 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120682 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120684 | GIR_RootConstrainSelectedInstOperands, |
| 120685 | // GIR_Coverage, 11496, |
| 120686 | GIR_EraseRootFromParent_Done, |
| 120687 | // Label 5890: @388093 |
| 120688 | GIM_Try, /*On fail goto*//*Label 5891*/ GIMT_Encode4(388228), // Rule ID 11497 // |
| 120689 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120690 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120691 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120692 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120693 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120694 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120695 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120696 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120697 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120698 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120699 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 120700 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120701 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120702 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120703 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120705 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120706 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120707 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120708 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120709 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120710 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120712 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120719 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120720 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120722 | GIR_RootConstrainSelectedInstOperands, |
| 120723 | // GIR_Coverage, 11497, |
| 120724 | GIR_EraseRootFromParent_Done, |
| 120725 | // Label 5891: @388228 |
| 120726 | GIM_Try, /*On fail goto*//*Label 5892*/ GIMT_Encode4(388363), // Rule ID 7353 // |
| 120727 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120728 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120729 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120730 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120731 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120732 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120733 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120734 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120735 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120736 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120737 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120738 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120739 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120740 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120741 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120743 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120744 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120745 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120746 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120747 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120748 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120752 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120757 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120758 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120760 | GIR_RootConstrainSelectedInstOperands, |
| 120761 | // GIR_Coverage, 7353, |
| 120762 | GIR_EraseRootFromParent_Done, |
| 120763 | // Label 5892: @388363 |
| 120764 | GIM_Try, /*On fail goto*//*Label 5893*/ GIMT_Encode4(388498), // Rule ID 11506 // |
| 120765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120768 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120770 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120771 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120772 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120773 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120774 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120775 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120776 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120777 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120778 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120779 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120780 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120781 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120782 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120783 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120784 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120785 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120786 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120798 | GIR_RootConstrainSelectedInstOperands, |
| 120799 | // GIR_Coverage, 11506, |
| 120800 | GIR_EraseRootFromParent_Done, |
| 120801 | // Label 5893: @388498 |
| 120802 | GIM_Try, /*On fail goto*//*Label 5894*/ GIMT_Encode4(388633), // Rule ID 11509 // |
| 120803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120806 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120808 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120809 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120810 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120811 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120812 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120813 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120814 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120815 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120816 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120817 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120818 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120819 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120820 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120821 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120822 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120823 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120824 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120825 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120826 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120833 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120834 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120836 | GIR_RootConstrainSelectedInstOperands, |
| 120837 | // GIR_Coverage, 11509, |
| 120838 | GIR_EraseRootFromParent_Done, |
| 120839 | // Label 5894: @388633 |
| 120840 | GIM_Try, /*On fail goto*//*Label 5895*/ GIMT_Encode4(388768), // Rule ID 11510 // |
| 120841 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120843 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120844 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120845 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120846 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120847 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120848 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120849 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120850 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120851 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120852 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 120853 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120854 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120855 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120856 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120857 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120858 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120859 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120860 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120861 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120862 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120872 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120874 | GIR_RootConstrainSelectedInstOperands, |
| 120875 | // GIR_Coverage, 11510, |
| 120876 | GIR_EraseRootFromParent_Done, |
| 120877 | // Label 5895: @388768 |
| 120878 | GIM_Try, /*On fail goto*//*Label 5896*/ GIMT_Encode4(388903), // Rule ID 7352 // |
| 120879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120881 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120882 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120883 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120884 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120885 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120886 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120887 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120888 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120889 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120890 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120891 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120892 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120893 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120894 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120895 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120896 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120897 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120898 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120899 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120900 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120909 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120912 | GIR_RootConstrainSelectedInstOperands, |
| 120913 | // GIR_Coverage, 7352, |
| 120914 | GIR_EraseRootFromParent_Done, |
| 120915 | // Label 5896: @388903 |
| 120916 | GIM_Try, /*On fail goto*//*Label 5897*/ GIMT_Encode4(389038), // Rule ID 11491 // |
| 120917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120918 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120921 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120922 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120923 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120924 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120925 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120926 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120927 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120928 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120929 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120930 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120931 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120932 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120933 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120934 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120935 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120936 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120937 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120938 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 120942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 120943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 120944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 120945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120947 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120948 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120950 | GIR_RootConstrainSelectedInstOperands, |
| 120951 | // GIR_Coverage, 11491, |
| 120952 | GIR_EraseRootFromParent_Done, |
| 120953 | // Label 5897: @389038 |
| 120954 | GIM_Try, /*On fail goto*//*Label 5898*/ GIMT_Encode4(389173), // Rule ID 11494 // |
| 120955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120956 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120957 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120958 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120959 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120960 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120961 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 120962 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 120963 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 120964 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 120965 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 120966 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 120967 | // MIs[3] VOP3Mods:src0:src0_mods |
| 120968 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 120969 | // MIs[3] VOP3Mods:src1:src1_mods |
| 120970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 120971 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 120972 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 120973 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 120974 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 120975 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 120976 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 120977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 120978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 120979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 120980 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 120981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 120982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 120983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 120984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 120985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120986 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 120988 | GIR_RootConstrainSelectedInstOperands, |
| 120989 | // GIR_Coverage, 11494, |
| 120990 | GIR_EraseRootFromParent_Done, |
| 120991 | // Label 5898: @389173 |
| 120992 | GIM_Try, /*On fail goto*//*Label 5899*/ GIMT_Encode4(389308), // Rule ID 11495 // |
| 120993 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 120994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 120995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 120996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 120997 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 120998 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 120999 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 121000 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121001 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121002 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121003 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 121004 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121005 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121006 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 121007 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 121009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121010 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121011 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121012 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121013 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121014 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 121020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 121021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121026 | GIR_RootConstrainSelectedInstOperands, |
| 121027 | // GIR_Coverage, 11495, |
| 121028 | GIR_EraseRootFromParent_Done, |
| 121029 | // Label 5899: @389308 |
| 121030 | GIM_Try, /*On fail goto*//*Label 5900*/ GIMT_Encode4(389443), // Rule ID 11547 // |
| 121031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121032 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121033 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121034 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121035 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121036 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121037 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121038 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121039 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121040 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121041 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121042 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121043 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121044 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121045 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121046 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121047 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121048 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121049 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121050 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121051 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121052 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121061 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121062 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121064 | GIR_RootConstrainSelectedInstOperands, |
| 121065 | // GIR_Coverage, 11547, |
| 121066 | GIR_EraseRootFromParent_Done, |
| 121067 | // Label 5900: @389443 |
| 121068 | GIM_Try, /*On fail goto*//*Label 5901*/ GIMT_Encode4(389578), // Rule ID 11548 // |
| 121069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121074 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121075 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121076 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121077 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121078 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121079 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121080 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121081 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121082 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121083 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121085 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121086 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121087 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121088 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121089 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121090 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121099 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121102 | GIR_RootConstrainSelectedInstOperands, |
| 121103 | // GIR_Coverage, 11548, |
| 121104 | GIR_EraseRootFromParent_Done, |
| 121105 | // Label 5901: @389578 |
| 121106 | GIM_Try, /*On fail goto*//*Label 5902*/ GIMT_Encode4(389713), // Rule ID 11549 // |
| 121107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121108 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121109 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121110 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121111 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121112 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121113 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121114 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121115 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121116 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121117 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121118 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121119 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121120 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121121 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121123 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121124 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121125 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121126 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121127 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121128 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121130 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121137 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121138 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121140 | GIR_RootConstrainSelectedInstOperands, |
| 121141 | // GIR_Coverage, 11549, |
| 121142 | GIR_EraseRootFromParent_Done, |
| 121143 | // Label 5902: @389713 |
| 121144 | GIM_Try, /*On fail goto*//*Label 5903*/ GIMT_Encode4(389848), // Rule ID 11550 // |
| 121145 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121149 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121150 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121151 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121152 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121153 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121154 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121155 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121156 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121157 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121158 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121159 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121160 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121161 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121162 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121163 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121164 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121165 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121166 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121178 | GIR_RootConstrainSelectedInstOperands, |
| 121179 | // GIR_Coverage, 11550, |
| 121180 | GIR_EraseRootFromParent_Done, |
| 121181 | // Label 5903: @389848 |
| 121182 | GIM_Try, /*On fail goto*//*Label 5904*/ GIMT_Encode4(389983), // Rule ID 11487 // |
| 121183 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121184 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121185 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121186 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121187 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121188 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121189 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121190 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121191 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121192 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121193 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121194 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121195 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121196 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121197 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121198 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121199 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121200 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121201 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121202 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121203 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121204 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121205 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121206 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121216 | GIR_RootConstrainSelectedInstOperands, |
| 121217 | // GIR_Coverage, 11487, |
| 121218 | GIR_EraseRootFromParent_Done, |
| 121219 | // Label 5904: @389983 |
| 121220 | GIM_Try, /*On fail goto*//*Label 5905*/ GIMT_Encode4(390118), // Rule ID 11488 // |
| 121221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121222 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121224 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121226 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121228 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121230 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121231 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121232 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121233 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121234 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121235 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121237 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121238 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121239 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121240 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121241 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121242 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121251 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121252 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121254 | GIR_RootConstrainSelectedInstOperands, |
| 121255 | // GIR_Coverage, 11488, |
| 121256 | GIR_EraseRootFromParent_Done, |
| 121257 | // Label 5905: @390118 |
| 121258 | GIM_Try, /*On fail goto*//*Label 5906*/ GIMT_Encode4(390253), // Rule ID 11489 // |
| 121259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121260 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121261 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121262 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121263 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121264 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121265 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121266 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121267 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121268 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121269 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121270 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121271 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121272 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121273 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121274 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121275 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121276 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121277 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121278 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121279 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121280 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121282 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121289 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121292 | GIR_RootConstrainSelectedInstOperands, |
| 121293 | // GIR_Coverage, 11489, |
| 121294 | GIR_EraseRootFromParent_Done, |
| 121295 | // Label 5906: @390253 |
| 121296 | GIM_Try, /*On fail goto*//*Label 5907*/ GIMT_Encode4(390388), // Rule ID 11490 // |
| 121297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121299 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121300 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121301 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121302 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121303 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121304 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121305 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121306 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121307 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121308 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121309 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121310 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121311 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121312 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121314 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121315 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121316 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121317 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121318 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121330 | GIR_RootConstrainSelectedInstOperands, |
| 121331 | // GIR_Coverage, 11490, |
| 121332 | GIR_EraseRootFromParent_Done, |
| 121333 | // Label 5907: @390388 |
| 121334 | GIM_Try, /*On fail goto*//*Label 5908*/ GIMT_Encode4(390523), // Rule ID 11532 // |
| 121335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121337 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121338 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121339 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121340 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121341 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121342 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121343 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121344 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121345 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121346 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121347 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121348 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121349 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121350 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121351 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121352 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121353 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121354 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121355 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121356 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121357 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121358 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121368 | GIR_RootConstrainSelectedInstOperands, |
| 121369 | // GIR_Coverage, 11532, |
| 121370 | GIR_EraseRootFromParent_Done, |
| 121371 | // Label 5908: @390523 |
| 121372 | GIM_Try, /*On fail goto*//*Label 5909*/ GIMT_Encode4(390658), // Rule ID 11533 // |
| 121373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121375 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121376 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121377 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121378 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121379 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121380 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121381 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121382 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121383 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121384 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121385 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121386 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121387 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121388 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121389 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121390 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121391 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121392 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121393 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121394 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121406 | GIR_RootConstrainSelectedInstOperands, |
| 121407 | // GIR_Coverage, 11533, |
| 121408 | GIR_EraseRootFromParent_Done, |
| 121409 | // Label 5909: @390658 |
| 121410 | GIM_Try, /*On fail goto*//*Label 5910*/ GIMT_Encode4(390793), // Rule ID 11534 // |
| 121411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121412 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121413 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121414 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121415 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121416 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121417 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121418 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121419 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121420 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121421 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121422 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121423 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121424 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121425 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121427 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121428 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121429 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121430 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121431 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121432 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121441 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121442 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121444 | GIR_RootConstrainSelectedInstOperands, |
| 121445 | // GIR_Coverage, 11534, |
| 121446 | GIR_EraseRootFromParent_Done, |
| 121447 | // Label 5910: @390793 |
| 121448 | GIM_Try, /*On fail goto*//*Label 5911*/ GIMT_Encode4(390928), // Rule ID 11535 // |
| 121449 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121456 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121457 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121458 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121459 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121460 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121461 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121462 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121463 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121464 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121465 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121466 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121467 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121468 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121469 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121470 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121482 | GIR_RootConstrainSelectedInstOperands, |
| 121483 | // GIR_Coverage, 11535, |
| 121484 | GIR_EraseRootFromParent_Done, |
| 121485 | // Label 5911: @390928 |
| 121486 | GIM_Try, /*On fail goto*//*Label 5912*/ GIMT_Encode4(391063), // Rule ID 11472 // |
| 121487 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121489 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121490 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121491 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121492 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121493 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121494 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121495 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121496 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121497 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121498 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121499 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121500 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121501 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121502 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121503 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121504 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121505 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121506 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121507 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121508 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121509 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121510 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121518 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121520 | GIR_RootConstrainSelectedInstOperands, |
| 121521 | // GIR_Coverage, 11472, |
| 121522 | GIR_EraseRootFromParent_Done, |
| 121523 | // Label 5912: @391063 |
| 121524 | GIM_Try, /*On fail goto*//*Label 5913*/ GIMT_Encode4(391198), // Rule ID 11473 // |
| 121525 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121530 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121531 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121532 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121533 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121534 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121535 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121536 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121537 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121538 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121539 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121542 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121543 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121544 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121545 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121546 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 121552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 121553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121558 | GIR_RootConstrainSelectedInstOperands, |
| 121559 | // GIR_Coverage, 11473, |
| 121560 | GIR_EraseRootFromParent_Done, |
| 121561 | // Label 5913: @391198 |
| 121562 | GIM_Try, /*On fail goto*//*Label 5914*/ GIMT_Encode4(391333), // Rule ID 11474 // |
| 121563 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121564 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121565 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121566 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121567 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121568 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121569 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121570 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121571 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121572 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121573 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121574 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121575 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121576 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121577 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121578 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121579 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121580 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121581 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121582 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121583 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121584 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121586 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121596 | GIR_RootConstrainSelectedInstOperands, |
| 121597 | // GIR_Coverage, 11474, |
| 121598 | GIR_EraseRootFromParent_Done, |
| 121599 | // Label 5914: @391333 |
| 121600 | GIM_Try, /*On fail goto*//*Label 5915*/ GIMT_Encode4(391468), // Rule ID 11475 // |
| 121601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121603 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121604 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121605 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121606 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121607 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 121608 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121609 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121610 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121611 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121612 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121613 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121614 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121615 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121616 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121617 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121618 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121619 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121620 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121621 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121622 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 121626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 121627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 121630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 121631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121634 | GIR_RootConstrainSelectedInstOperands, |
| 121635 | // GIR_Coverage, 11475, |
| 121636 | GIR_EraseRootFromParent_Done, |
| 121637 | // Label 5915: @391468 |
| 121638 | GIM_Try, /*On fail goto*//*Label 5916*/ GIMT_Encode4(391603), // Rule ID 11543 // |
| 121639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121641 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121642 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121643 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121644 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121645 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121646 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121647 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121648 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121649 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121650 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121651 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121652 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121653 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121654 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121655 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121656 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121657 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121658 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121659 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121660 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 121664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 121665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121669 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121670 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121672 | GIR_RootConstrainSelectedInstOperands, |
| 121673 | // GIR_Coverage, 11543, |
| 121674 | GIR_EraseRootFromParent_Done, |
| 121675 | // Label 5916: @391603 |
| 121676 | GIM_Try, /*On fail goto*//*Label 5917*/ GIMT_Encode4(391738), // Rule ID 11544 // |
| 121677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121679 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121680 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121681 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121682 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121683 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121684 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121685 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121686 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121687 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121688 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121689 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121690 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121691 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121692 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121693 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121694 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121695 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121696 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121697 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121698 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 121702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 121703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121709 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121710 | GIR_RootConstrainSelectedInstOperands, |
| 121711 | // GIR_Coverage, 11544, |
| 121712 | GIR_EraseRootFromParent_Done, |
| 121713 | // Label 5917: @391738 |
| 121714 | GIM_Try, /*On fail goto*//*Label 5918*/ GIMT_Encode4(391873), // Rule ID 11545 // |
| 121715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121716 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121717 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121718 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121719 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121720 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121721 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121722 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121723 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121724 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121725 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121726 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121727 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121728 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121729 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121730 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121731 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121732 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121733 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121734 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121735 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121736 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 121742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 121743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121745 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121748 | GIR_RootConstrainSelectedInstOperands, |
| 121749 | // GIR_Coverage, 11545, |
| 121750 | GIR_EraseRootFromParent_Done, |
| 121751 | // Label 5918: @391873 |
| 121752 | GIM_Try, /*On fail goto*//*Label 5919*/ GIMT_Encode4(392008), // Rule ID 11546 // |
| 121753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121754 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121755 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121756 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121757 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121758 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121759 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121760 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121761 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121762 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121763 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121764 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121765 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121766 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121767 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121768 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121769 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121770 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121771 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121772 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121773 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121774 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121775 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121776 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 121780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 121781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121783 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121785 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121786 | GIR_RootConstrainSelectedInstOperands, |
| 121787 | // GIR_Coverage, 11546, |
| 121788 | GIR_EraseRootFromParent_Done, |
| 121789 | // Label 5919: @392008 |
| 121790 | GIM_Try, /*On fail goto*//*Label 5920*/ GIMT_Encode4(392143), // Rule ID 11483 // |
| 121791 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121792 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121793 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121794 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121795 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121796 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121797 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121798 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121799 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121800 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121801 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121802 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121803 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121804 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121805 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121806 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121807 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121808 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121809 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121810 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121811 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121812 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 121816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 121817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121821 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121822 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121824 | GIR_RootConstrainSelectedInstOperands, |
| 121825 | // GIR_Coverage, 11483, |
| 121826 | GIR_EraseRootFromParent_Done, |
| 121827 | // Label 5920: @392143 |
| 121828 | GIM_Try, /*On fail goto*//*Label 5921*/ GIMT_Encode4(392278), // Rule ID 11484 // |
| 121829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121834 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121835 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121836 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121837 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121838 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121839 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121840 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121841 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121842 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121843 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121844 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121845 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121846 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121847 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121848 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121849 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121850 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 121854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 121855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121861 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121862 | GIR_RootConstrainSelectedInstOperands, |
| 121863 | // GIR_Coverage, 11484, |
| 121864 | GIR_EraseRootFromParent_Done, |
| 121865 | // Label 5921: @392278 |
| 121866 | GIM_Try, /*On fail goto*//*Label 5922*/ GIMT_Encode4(392413), // Rule ID 11485 // |
| 121867 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121868 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121869 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121870 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121871 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121872 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121873 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121874 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121875 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121876 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121877 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121878 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121879 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121880 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121881 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121882 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121883 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121884 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121885 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121886 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121887 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121888 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 121894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 121895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121897 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121898 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121899 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121900 | GIR_RootConstrainSelectedInstOperands, |
| 121901 | // GIR_Coverage, 11485, |
| 121902 | GIR_EraseRootFromParent_Done, |
| 121903 | // Label 5922: @392413 |
| 121904 | GIM_Try, /*On fail goto*//*Label 5923*/ GIMT_Encode4(392548), // Rule ID 11486 // |
| 121905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121907 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121908 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121909 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121910 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121911 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121912 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 121913 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121914 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121915 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121916 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 121917 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121918 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121919 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121920 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121921 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121922 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121923 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121924 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121925 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121926 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 121930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 121931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 121932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 121933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121935 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121937 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121938 | GIR_RootConstrainSelectedInstOperands, |
| 121939 | // GIR_Coverage, 11486, |
| 121940 | GIR_EraseRootFromParent_Done, |
| 121941 | // Label 5923: @392548 |
| 121942 | GIM_Try, /*On fail goto*//*Label 5924*/ GIMT_Encode4(392683), // Rule ID 11528 // |
| 121943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121945 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121946 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121947 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121948 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121949 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121950 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121951 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121952 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121953 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121954 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121955 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121956 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121957 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121958 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121959 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121960 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121961 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 121962 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 121963 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 121964 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 121965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 121966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 121967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 121968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 121969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 121970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 121971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 121972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 121973 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121974 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 121976 | GIR_RootConstrainSelectedInstOperands, |
| 121977 | // GIR_Coverage, 11528, |
| 121978 | GIR_EraseRootFromParent_Done, |
| 121979 | // Label 5924: @392683 |
| 121980 | GIM_Try, /*On fail goto*//*Label 5925*/ GIMT_Encode4(392818), // Rule ID 11529 // |
| 121981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 121982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 121983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 121984 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 121986 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 121987 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 121988 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 121989 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 121990 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 121991 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 121992 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 121993 | // MIs[3] VOP3Mods:src1:src1_mods |
| 121994 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 121995 | // MIs[3] VOP3Mods:src0:src0_mods |
| 121996 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 121997 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 121998 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 121999 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122000 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122001 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122002 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122014 | GIR_RootConstrainSelectedInstOperands, |
| 122015 | // GIR_Coverage, 11529, |
| 122016 | GIR_EraseRootFromParent_Done, |
| 122017 | // Label 5925: @392818 |
| 122018 | GIM_Try, /*On fail goto*//*Label 5926*/ GIMT_Encode4(392953), // Rule ID 11530 // |
| 122019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122021 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122022 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122023 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122024 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122025 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122026 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122027 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122028 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122029 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122030 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122031 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122032 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122033 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122034 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122035 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122036 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122037 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122038 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122039 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122040 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122052 | GIR_RootConstrainSelectedInstOperands, |
| 122053 | // GIR_Coverage, 11530, |
| 122054 | GIR_EraseRootFromParent_Done, |
| 122055 | // Label 5926: @392953 |
| 122056 | GIM_Try, /*On fail goto*//*Label 5927*/ GIMT_Encode4(393088), // Rule ID 11531 // |
| 122057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122060 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122061 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122062 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122063 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122064 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122065 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122066 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122067 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122068 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122069 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122070 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122071 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122072 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122073 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122074 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122075 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122076 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122077 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122078 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122090 | GIR_RootConstrainSelectedInstOperands, |
| 122091 | // GIR_Coverage, 11531, |
| 122092 | GIR_EraseRootFromParent_Done, |
| 122093 | // Label 5927: @393088 |
| 122094 | GIM_Try, /*On fail goto*//*Label 5928*/ GIMT_Encode4(393223), // Rule ID 11468 // |
| 122095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122097 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122098 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122099 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122100 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122101 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122102 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122103 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122104 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122105 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122106 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122107 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122108 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122109 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122110 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122111 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122112 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122113 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122114 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122115 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122116 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122118 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122125 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122126 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122127 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122128 | GIR_RootConstrainSelectedInstOperands, |
| 122129 | // GIR_Coverage, 11468, |
| 122130 | GIR_EraseRootFromParent_Done, |
| 122131 | // Label 5928: @393223 |
| 122132 | GIM_Try, /*On fail goto*//*Label 5929*/ GIMT_Encode4(393358), // Rule ID 11469 // |
| 122133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122135 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122136 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122137 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122138 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122139 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122140 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122141 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122142 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122143 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122144 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122145 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122146 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122147 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122148 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122149 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122150 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122151 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122152 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122153 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122154 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122163 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122164 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122166 | GIR_RootConstrainSelectedInstOperands, |
| 122167 | // GIR_Coverage, 11469, |
| 122168 | GIR_EraseRootFromParent_Done, |
| 122169 | // Label 5929: @393358 |
| 122170 | GIM_Try, /*On fail goto*//*Label 5930*/ GIMT_Encode4(393493), // Rule ID 11470 // |
| 122171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122173 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122174 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122175 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122176 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122177 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122178 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122179 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122180 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122181 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122182 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122183 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122184 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122185 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122186 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122187 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122188 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122189 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122190 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122191 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122192 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122204 | GIR_RootConstrainSelectedInstOperands, |
| 122205 | // GIR_Coverage, 11470, |
| 122206 | GIR_EraseRootFromParent_Done, |
| 122207 | // Label 5930: @393493 |
| 122208 | GIM_Try, /*On fail goto*//*Label 5931*/ GIMT_Encode4(393628), // Rule ID 11471 // |
| 122209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122211 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122212 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122213 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122214 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122215 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 122216 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122217 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122218 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122219 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 122220 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122221 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122222 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 122223 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122224 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 122225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122226 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122227 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122228 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122229 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122230 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122242 | GIR_RootConstrainSelectedInstOperands, |
| 122243 | // GIR_Coverage, 11471, |
| 122244 | GIR_EraseRootFromParent_Done, |
| 122245 | // Label 5931: @393628 |
| 122246 | GIM_Try, /*On fail goto*//*Label 5932*/ GIMT_Encode4(393763), // Rule ID 11477 // |
| 122247 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122248 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122249 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122250 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122251 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122252 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122253 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122254 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122255 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122256 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122257 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122258 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122259 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122260 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122261 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122262 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122263 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122264 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122265 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122266 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122267 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122268 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122280 | GIR_RootConstrainSelectedInstOperands, |
| 122281 | // GIR_Coverage, 11477, |
| 122282 | GIR_EraseRootFromParent_Done, |
| 122283 | // Label 5932: @393763 |
| 122284 | GIM_Try, /*On fail goto*//*Label 5933*/ GIMT_Encode4(393898), // Rule ID 11478 // |
| 122285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122286 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122287 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122288 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122289 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122290 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122292 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122293 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122294 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122295 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122296 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122297 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122298 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122299 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122300 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122301 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122302 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122303 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122304 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122305 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122306 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122315 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122316 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122317 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122318 | GIR_RootConstrainSelectedInstOperands, |
| 122319 | // GIR_Coverage, 11478, |
| 122320 | GIR_EraseRootFromParent_Done, |
| 122321 | // Label 5933: @393898 |
| 122322 | GIM_Try, /*On fail goto*//*Label 5934*/ GIMT_Encode4(394033), // Rule ID 11481 // |
| 122323 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122324 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122325 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122326 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122327 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122328 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122329 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122330 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122331 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122332 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122333 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122334 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122335 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122336 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122337 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122338 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122339 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122340 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122341 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122342 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122343 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122344 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122353 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122354 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122356 | GIR_RootConstrainSelectedInstOperands, |
| 122357 | // GIR_Coverage, 11481, |
| 122358 | GIR_EraseRootFromParent_Done, |
| 122359 | // Label 5934: @394033 |
| 122360 | GIM_Try, /*On fail goto*//*Label 5935*/ GIMT_Encode4(394168), // Rule ID 11482 // |
| 122361 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122363 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122364 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122365 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122366 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122367 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122368 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122369 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122370 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122371 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122372 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122373 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122374 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122375 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122376 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122377 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122378 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122379 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122380 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122381 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122382 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122393 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122394 | GIR_RootConstrainSelectedInstOperands, |
| 122395 | // GIR_Coverage, 11482, |
| 122396 | GIR_EraseRootFromParent_Done, |
| 122397 | // Label 5935: @394168 |
| 122398 | GIM_Try, /*On fail goto*//*Label 5936*/ GIMT_Encode4(394303), // Rule ID 11462 // |
| 122399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122400 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122401 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122402 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122403 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122404 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122405 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122406 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122407 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122408 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122409 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122410 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122411 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122412 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122413 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122414 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122415 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122416 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122417 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122418 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122419 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122420 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122421 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122422 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122428 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122432 | GIR_RootConstrainSelectedInstOperands, |
| 122433 | // GIR_Coverage, 11462, |
| 122434 | GIR_EraseRootFromParent_Done, |
| 122435 | // Label 5936: @394303 |
| 122436 | GIM_Try, /*On fail goto*//*Label 5937*/ GIMT_Encode4(394438), // Rule ID 11463 // |
| 122437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122438 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122439 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122440 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122441 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122442 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122443 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122444 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122445 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122446 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122447 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122448 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122449 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122450 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122451 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122452 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122453 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122454 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122455 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122456 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122457 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122458 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122470 | GIR_RootConstrainSelectedInstOperands, |
| 122471 | // GIR_Coverage, 11463, |
| 122472 | GIR_EraseRootFromParent_Done, |
| 122473 | // Label 5937: @394438 |
| 122474 | GIM_Try, /*On fail goto*//*Label 5938*/ GIMT_Encode4(394573), // Rule ID 11466 // |
| 122475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122477 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122478 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122479 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122480 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122481 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122482 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122483 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122484 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122485 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122486 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122487 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122488 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122489 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122490 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122491 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122492 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122493 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122494 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122495 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122496 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122505 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122506 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122508 | GIR_RootConstrainSelectedInstOperands, |
| 122509 | // GIR_Coverage, 11466, |
| 122510 | GIR_EraseRootFromParent_Done, |
| 122511 | // Label 5938: @394573 |
| 122512 | GIM_Try, /*On fail goto*//*Label 5939*/ GIMT_Encode4(394708), // Rule ID 11467 // |
| 122513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122520 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122521 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122522 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122523 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122524 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122525 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122526 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122527 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122528 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122529 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122530 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122531 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122532 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122533 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122534 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122546 | GIR_RootConstrainSelectedInstOperands, |
| 122547 | // GIR_Coverage, 11467, |
| 122548 | GIR_EraseRootFromParent_Done, |
| 122549 | // Label 5939: @394708 |
| 122550 | GIM_Try, /*On fail goto*//*Label 5940*/ GIMT_Encode4(394843), // Rule ID 7351 // |
| 122551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122553 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122554 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122555 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122556 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122557 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122558 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122559 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122560 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122561 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122562 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122563 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122564 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122565 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122566 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122567 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122568 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122569 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122570 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122571 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122572 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122582 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122583 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122584 | GIR_RootConstrainSelectedInstOperands, |
| 122585 | // GIR_Coverage, 7351, |
| 122586 | GIR_EraseRootFromParent_Done, |
| 122587 | // Label 5940: @394843 |
| 122588 | GIM_Try, /*On fail goto*//*Label 5941*/ GIMT_Encode4(394978), // Rule ID 11476 // |
| 122589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122591 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122592 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122593 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122594 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122595 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122596 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122597 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122598 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122599 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122600 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122601 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122602 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122603 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122604 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122605 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122606 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122607 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122608 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122609 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122610 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122619 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122620 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122621 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122622 | GIR_RootConstrainSelectedInstOperands, |
| 122623 | // GIR_Coverage, 11476, |
| 122624 | GIR_EraseRootFromParent_Done, |
| 122625 | // Label 5941: @394978 |
| 122626 | GIM_Try, /*On fail goto*//*Label 5942*/ GIMT_Encode4(395113), // Rule ID 11479 // |
| 122627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122629 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122630 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122631 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122632 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122633 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122634 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122635 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122636 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122637 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122638 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122639 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122640 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122641 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122642 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122643 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122644 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122645 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122646 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122647 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122648 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122649 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122650 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122656 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122660 | GIR_RootConstrainSelectedInstOperands, |
| 122661 | // GIR_Coverage, 11479, |
| 122662 | GIR_EraseRootFromParent_Done, |
| 122663 | // Label 5942: @395113 |
| 122664 | GIM_Try, /*On fail goto*//*Label 5943*/ GIMT_Encode4(395248), // Rule ID 11480 // |
| 122665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122666 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122667 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122668 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122669 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122670 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122671 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122672 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122673 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122674 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122675 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122676 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122677 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122678 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122679 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122680 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122681 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122682 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122683 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122684 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122685 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122686 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122697 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122698 | GIR_RootConstrainSelectedInstOperands, |
| 122699 | // GIR_Coverage, 11480, |
| 122700 | GIR_EraseRootFromParent_Done, |
| 122701 | // Label 5943: @395248 |
| 122702 | GIM_Try, /*On fail goto*//*Label 5944*/ GIMT_Encode4(395383), // Rule ID 7350 // |
| 122703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122704 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122705 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122706 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122707 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122708 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122709 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122710 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122711 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122712 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122713 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122714 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122715 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122716 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122717 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122718 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122719 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122720 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122721 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122722 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122723 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122724 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122727 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122733 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122736 | GIR_RootConstrainSelectedInstOperands, |
| 122737 | // GIR_Coverage, 7350, |
| 122738 | GIR_EraseRootFromParent_Done, |
| 122739 | // Label 5944: @395383 |
| 122740 | GIM_Try, /*On fail goto*//*Label 5945*/ GIMT_Encode4(395518), // Rule ID 11461 // |
| 122741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122748 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122749 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122750 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122751 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122752 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122753 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122754 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122755 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122756 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122757 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122758 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122759 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122760 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122761 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122762 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122773 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122774 | GIR_RootConstrainSelectedInstOperands, |
| 122775 | // GIR_Coverage, 11461, |
| 122776 | GIR_EraseRootFromParent_Done, |
| 122777 | // Label 5945: @395518 |
| 122778 | GIM_Try, /*On fail goto*//*Label 5946*/ GIMT_Encode4(395653), // Rule ID 11464 // |
| 122779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122780 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122781 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122782 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122783 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122784 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122785 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122786 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122787 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122788 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122789 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122790 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122791 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122792 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122793 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122794 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122795 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122796 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122797 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122798 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122799 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122800 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122807 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122808 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122809 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122810 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122811 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122812 | GIR_RootConstrainSelectedInstOperands, |
| 122813 | // GIR_Coverage, 11464, |
| 122814 | GIR_EraseRootFromParent_Done, |
| 122815 | // Label 5946: @395653 |
| 122816 | GIM_Try, /*On fail goto*//*Label 5947*/ GIMT_Encode4(395788), // Rule ID 11465 // |
| 122817 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122819 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122820 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122821 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122822 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122823 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122824 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 122825 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122826 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122827 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 122828 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 122829 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122831 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122832 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122833 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122834 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122835 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122836 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122837 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122838 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122847 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122848 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122849 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122850 | GIR_RootConstrainSelectedInstOperands, |
| 122851 | // GIR_Coverage, 11465, |
| 122852 | GIR_EraseRootFromParent_Done, |
| 122853 | // Label 5947: @395788 |
| 122854 | GIM_Try, /*On fail goto*//*Label 5948*/ GIMT_Encode4(395923), // Rule ID 11447 // |
| 122855 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122857 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122858 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122859 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122860 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122861 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122862 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122863 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122864 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122865 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122866 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122867 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122869 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122870 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122871 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122872 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122873 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122874 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122875 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122876 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122879 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122885 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122888 | GIR_RootConstrainSelectedInstOperands, |
| 122889 | // GIR_Coverage, 11447, |
| 122890 | GIR_EraseRootFromParent_Done, |
| 122891 | // Label 5948: @395923 |
| 122892 | GIM_Try, /*On fail goto*//*Label 5949*/ GIMT_Encode4(396058), // Rule ID 11448 // |
| 122893 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122898 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122899 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122900 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122901 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122902 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122903 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122904 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122905 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122907 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122908 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122909 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122910 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122911 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122912 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122913 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122914 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 122918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 122919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 122920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 122921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122925 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122926 | GIR_RootConstrainSelectedInstOperands, |
| 122927 | // GIR_Coverage, 11448, |
| 122928 | GIR_EraseRootFromParent_Done, |
| 122929 | // Label 5949: @396058 |
| 122930 | GIM_Try, /*On fail goto*//*Label 5950*/ GIMT_Encode4(396193), // Rule ID 11451 // |
| 122931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122936 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122937 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122938 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122939 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122940 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122941 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122942 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122943 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122945 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122946 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122947 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122948 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122949 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122950 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122951 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122952 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122961 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122962 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122963 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 122964 | GIR_RootConstrainSelectedInstOperands, |
| 122965 | // GIR_Coverage, 11451, |
| 122966 | GIR_EraseRootFromParent_Done, |
| 122967 | // Label 5950: @396193 |
| 122968 | GIM_Try, /*On fail goto*//*Label 5951*/ GIMT_Encode4(396328), // Rule ID 11452 // |
| 122969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 122970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 122971 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 122972 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122973 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 122974 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 122975 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 122976 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 122977 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 122978 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 122979 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 122980 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 122981 | // MIs[3] VOP3Mods:src1:src1_mods |
| 122982 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 122983 | // MIs[3] VOP3Mods:src0:src0_mods |
| 122984 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 122985 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 122986 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 122987 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 122988 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 122989 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 122990 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 122991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 122992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 122993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 122994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 122995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 122996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 122997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 122998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 122999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123000 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123002 | GIR_RootConstrainSelectedInstOperands, |
| 123003 | // GIR_Coverage, 11452, |
| 123004 | GIR_EraseRootFromParent_Done, |
| 123005 | // Label 5951: @396328 |
| 123006 | GIM_Try, /*On fail goto*//*Label 5952*/ GIMT_Encode4(396463), // Rule ID 11432 // |
| 123007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123009 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123010 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123011 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123012 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123013 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123014 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123015 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123016 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123017 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 123018 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123019 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123020 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123021 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123022 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123023 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123024 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123025 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123026 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123027 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123028 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123037 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123038 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123040 | GIR_RootConstrainSelectedInstOperands, |
| 123041 | // GIR_Coverage, 11432, |
| 123042 | GIR_EraseRootFromParent_Done, |
| 123043 | // Label 5952: @396463 |
| 123044 | GIM_Try, /*On fail goto*//*Label 5953*/ GIMT_Encode4(396598), // Rule ID 11433 // |
| 123045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123050 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123051 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123055 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 123056 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123057 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123059 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123060 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123061 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123062 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123063 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123064 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123065 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123066 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123078 | GIR_RootConstrainSelectedInstOperands, |
| 123079 | // GIR_Coverage, 11433, |
| 123080 | GIR_EraseRootFromParent_Done, |
| 123081 | // Label 5953: @396598 |
| 123082 | GIM_Try, /*On fail goto*//*Label 5954*/ GIMT_Encode4(396733), // Rule ID 11436 // |
| 123083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123085 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123086 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123087 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123088 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123089 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123090 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123091 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123092 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123093 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 123094 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123095 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123096 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123097 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123098 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123099 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123100 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123101 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123102 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123103 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123104 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123116 | GIR_RootConstrainSelectedInstOperands, |
| 123117 | // GIR_Coverage, 11436, |
| 123118 | GIR_EraseRootFromParent_Done, |
| 123119 | // Label 5954: @396733 |
| 123120 | GIM_Try, /*On fail goto*//*Label 5955*/ GIMT_Encode4(396868), // Rule ID 11437 // |
| 123121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123123 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123124 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123125 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123126 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123127 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123128 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123129 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123130 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123131 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 123132 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123133 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123134 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123135 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123136 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123137 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123138 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123139 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123140 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123141 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123142 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123152 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123153 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123154 | GIR_RootConstrainSelectedInstOperands, |
| 123155 | // GIR_Coverage, 11437, |
| 123156 | GIR_EraseRootFromParent_Done, |
| 123157 | // Label 5955: @396868 |
| 123158 | GIM_Try, /*On fail goto*//*Label 5956*/ GIMT_Encode4(397003), // Rule ID 7349 // |
| 123159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123161 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123162 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123163 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123164 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123165 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123166 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123167 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123168 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123169 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123170 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123171 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123172 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123173 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123174 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123175 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123176 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123177 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123178 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123179 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123180 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123184 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123189 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123190 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123192 | GIR_RootConstrainSelectedInstOperands, |
| 123193 | // GIR_Coverage, 7349, |
| 123194 | GIR_EraseRootFromParent_Done, |
| 123195 | // Label 5956: @397003 |
| 123196 | GIM_Try, /*On fail goto*//*Label 5957*/ GIMT_Encode4(397138), // Rule ID 11446 // |
| 123197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123202 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123203 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123204 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123205 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123206 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123207 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123208 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123209 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123211 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123212 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123213 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123214 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123215 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123216 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123217 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123218 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123229 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123230 | GIR_RootConstrainSelectedInstOperands, |
| 123231 | // GIR_Coverage, 11446, |
| 123232 | GIR_EraseRootFromParent_Done, |
| 123233 | // Label 5957: @397138 |
| 123234 | GIM_Try, /*On fail goto*//*Label 5958*/ GIMT_Encode4(397273), // Rule ID 11449 // |
| 123235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123237 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123238 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123239 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123240 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123241 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123242 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123243 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123244 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123245 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123246 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123247 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123248 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123249 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123250 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123251 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123252 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123253 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123254 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123255 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123256 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123265 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123268 | GIR_RootConstrainSelectedInstOperands, |
| 123269 | // GIR_Coverage, 11449, |
| 123270 | GIR_EraseRootFromParent_Done, |
| 123271 | // Label 5958: @397273 |
| 123272 | GIM_Try, /*On fail goto*//*Label 5959*/ GIMT_Encode4(397408), // Rule ID 11450 // |
| 123273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123275 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123276 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123277 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123278 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123279 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123280 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123281 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123282 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123283 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123284 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123285 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123286 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123287 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123288 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123289 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123290 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123291 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123292 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123293 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123294 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123306 | GIR_RootConstrainSelectedInstOperands, |
| 123307 | // GIR_Coverage, 11450, |
| 123308 | GIR_EraseRootFromParent_Done, |
| 123309 | // Label 5959: @397408 |
| 123310 | GIM_Try, /*On fail goto*//*Label 5960*/ GIMT_Encode4(397543), // Rule ID 7348 // |
| 123311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123313 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123314 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123315 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123316 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123317 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123318 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123319 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123320 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123321 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123322 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123323 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123325 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123326 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123327 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123328 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123329 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123330 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123331 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123332 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123333 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123334 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123344 | GIR_RootConstrainSelectedInstOperands, |
| 123345 | // GIR_Coverage, 7348, |
| 123346 | GIR_EraseRootFromParent_Done, |
| 123347 | // Label 5960: @397543 |
| 123348 | GIM_Try, /*On fail goto*//*Label 5961*/ GIMT_Encode4(397678), // Rule ID 11431 // |
| 123349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123350 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123354 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123355 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123356 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123357 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123358 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123359 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123360 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123361 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123363 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123364 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123365 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123366 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123367 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123368 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123369 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123370 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 123374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 123375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123379 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123382 | GIR_RootConstrainSelectedInstOperands, |
| 123383 | // GIR_Coverage, 11431, |
| 123384 | GIR_EraseRootFromParent_Done, |
| 123385 | // Label 5961: @397678 |
| 123386 | GIM_Try, /*On fail goto*//*Label 5962*/ GIMT_Encode4(397813), // Rule ID 11434 // |
| 123387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123388 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123389 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123390 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123391 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123392 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123393 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123394 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123395 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123396 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123397 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123398 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123399 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123400 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123401 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123402 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123403 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123404 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123405 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123406 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123407 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123408 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123410 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123417 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123418 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123420 | GIR_RootConstrainSelectedInstOperands, |
| 123421 | // GIR_Coverage, 11434, |
| 123422 | GIR_EraseRootFromParent_Done, |
| 123423 | // Label 5962: @397813 |
| 123424 | GIM_Try, /*On fail goto*//*Label 5963*/ GIMT_Encode4(397948), // Rule ID 11435 // |
| 123425 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123427 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123428 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123429 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123430 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123431 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 123432 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123433 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123434 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123435 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 123436 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123437 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123438 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 123439 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123440 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 123441 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123442 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123443 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123444 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123445 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123446 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 123452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 123453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 123454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 123455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123457 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123458 | GIR_RootConstrainSelectedInstOperands, |
| 123459 | // GIR_Coverage, 11435, |
| 123460 | GIR_EraseRootFromParent_Done, |
| 123461 | // Label 5963: @397948 |
| 123462 | GIM_Try, /*On fail goto*//*Label 5964*/ GIMT_Encode4(398083), // Rule ID 11517 // |
| 123463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123465 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123466 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123467 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123468 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123469 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123470 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123471 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123472 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123473 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123474 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123475 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123476 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123477 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123478 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123479 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123480 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123481 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123482 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123483 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123484 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123493 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123495 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123496 | GIR_RootConstrainSelectedInstOperands, |
| 123497 | // GIR_Coverage, 11517, |
| 123498 | GIR_EraseRootFromParent_Done, |
| 123499 | // Label 5964: @398083 |
| 123500 | GIM_Try, /*On fail goto*//*Label 5965*/ GIMT_Encode4(398218), // Rule ID 11518 // |
| 123501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123502 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123503 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123504 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123505 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123506 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123507 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123508 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123509 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123510 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123511 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123512 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123513 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123514 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123515 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123516 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123517 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123518 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123519 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123520 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123521 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123522 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123534 | GIR_RootConstrainSelectedInstOperands, |
| 123535 | // GIR_Coverage, 11518, |
| 123536 | GIR_EraseRootFromParent_Done, |
| 123537 | // Label 5965: @398218 |
| 123538 | GIM_Try, /*On fail goto*//*Label 5966*/ GIMT_Encode4(398353), // Rule ID 11519 // |
| 123539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123541 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123542 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123543 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123544 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123545 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123546 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123547 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123548 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123549 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123550 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123551 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123552 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123553 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123554 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123555 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123556 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123557 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123558 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123559 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123560 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123569 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123570 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123572 | GIR_RootConstrainSelectedInstOperands, |
| 123573 | // GIR_Coverage, 11519, |
| 123574 | GIR_EraseRootFromParent_Done, |
| 123575 | // Label 5966: @398353 |
| 123576 | GIM_Try, /*On fail goto*//*Label 5967*/ GIMT_Encode4(398488), // Rule ID 11520 // |
| 123577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123581 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123582 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123583 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123584 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123585 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123586 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123587 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123588 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123589 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123591 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123592 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123593 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123594 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123595 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123596 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123597 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123598 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123609 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123610 | GIR_RootConstrainSelectedInstOperands, |
| 123611 | // GIR_Coverage, 11520, |
| 123612 | GIR_EraseRootFromParent_Done, |
| 123613 | // Label 5967: @398488 |
| 123614 | GIM_Try, /*On fail goto*//*Label 5968*/ GIMT_Encode4(398623), // Rule ID 11457 // |
| 123615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123616 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123617 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123618 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123619 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123620 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123621 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123622 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123623 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123624 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123625 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123626 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123627 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123629 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123630 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123631 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123632 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123633 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123634 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123635 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123636 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123645 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123648 | GIR_RootConstrainSelectedInstOperands, |
| 123649 | // GIR_Coverage, 11457, |
| 123650 | GIR_EraseRootFromParent_Done, |
| 123651 | // Label 5968: @398623 |
| 123652 | GIM_Try, /*On fail goto*//*Label 5969*/ GIMT_Encode4(398758), // Rule ID 11458 // |
| 123653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123654 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123655 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123656 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123657 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123658 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123659 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123660 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123661 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123662 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123663 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123664 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123665 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123666 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123667 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123668 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123669 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123670 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123671 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123672 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123673 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123674 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123683 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123684 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123686 | GIR_RootConstrainSelectedInstOperands, |
| 123687 | // GIR_Coverage, 11458, |
| 123688 | GIR_EraseRootFromParent_Done, |
| 123689 | // Label 5969: @398758 |
| 123690 | GIM_Try, /*On fail goto*//*Label 5970*/ GIMT_Encode4(398893), // Rule ID 11459 // |
| 123691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123700 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123702 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123703 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123705 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123706 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123707 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123708 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123709 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123710 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123711 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123712 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123714 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123722 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123724 | GIR_RootConstrainSelectedInstOperands, |
| 123725 | // GIR_Coverage, 11459, |
| 123726 | GIR_EraseRootFromParent_Done, |
| 123727 | // Label 5970: @398893 |
| 123728 | GIM_Try, /*On fail goto*//*Label 5971*/ GIMT_Encode4(399028), // Rule ID 11460 // |
| 123729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123735 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123736 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 123737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123739 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123740 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123741 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123743 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123744 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123745 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123746 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123747 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123748 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123749 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123750 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123761 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123762 | GIR_RootConstrainSelectedInstOperands, |
| 123763 | // GIR_Coverage, 11460, |
| 123764 | GIR_EraseRootFromParent_Done, |
| 123765 | // Label 5971: @399028 |
| 123766 | GIM_Try, /*On fail goto*//*Label 5972*/ GIMT_Encode4(399163), // Rule ID 11502 // |
| 123767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123769 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123770 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123771 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123772 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123773 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123774 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123775 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123776 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123777 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123778 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123779 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123780 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123781 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123782 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123783 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123784 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123785 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123786 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123787 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123788 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123800 | GIR_RootConstrainSelectedInstOperands, |
| 123801 | // GIR_Coverage, 11502, |
| 123802 | GIR_EraseRootFromParent_Done, |
| 123803 | // Label 5972: @399163 |
| 123804 | GIM_Try, /*On fail goto*//*Label 5973*/ GIMT_Encode4(399298), // Rule ID 11503 // |
| 123805 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123807 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123808 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123809 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123810 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123811 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123812 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123813 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123814 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123815 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123816 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123817 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123818 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123819 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123820 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123821 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123822 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123823 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123824 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123825 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123826 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123827 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123828 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123835 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123836 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123837 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123838 | GIR_RootConstrainSelectedInstOperands, |
| 123839 | // GIR_Coverage, 11503, |
| 123840 | GIR_EraseRootFromParent_Done, |
| 123841 | // Label 5973: @399298 |
| 123842 | GIM_Try, /*On fail goto*//*Label 5974*/ GIMT_Encode4(399433), // Rule ID 11504 // |
| 123843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123844 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123845 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123846 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123847 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123848 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123849 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123850 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123851 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123852 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123853 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123854 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123855 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123856 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123857 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123858 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123859 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123860 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123861 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123862 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123863 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123864 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123873 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123874 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123875 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123876 | GIR_RootConstrainSelectedInstOperands, |
| 123877 | // GIR_Coverage, 11504, |
| 123878 | GIR_EraseRootFromParent_Done, |
| 123879 | // Label 5974: @399433 |
| 123880 | GIM_Try, /*On fail goto*//*Label 5975*/ GIMT_Encode4(399568), // Rule ID 11505 // |
| 123881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123883 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123884 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123885 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123886 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123887 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123888 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123889 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123890 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123891 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123892 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 123893 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123894 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123895 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123896 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123897 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123898 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123899 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123900 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123901 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123902 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 123906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 123907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 123908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 123909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123911 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123914 | GIR_RootConstrainSelectedInstOperands, |
| 123915 | // GIR_Coverage, 11505, |
| 123916 | GIR_EraseRootFromParent_Done, |
| 123917 | // Label 5975: @399568 |
| 123918 | GIM_Try, /*On fail goto*//*Label 5976*/ GIMT_Encode4(399703), // Rule ID 11442 // |
| 123919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123920 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123921 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123922 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123923 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123924 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123925 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123926 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123927 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123928 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123929 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123930 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123931 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123932 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123933 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123934 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123935 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123936 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123937 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123938 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123939 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123940 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123949 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123950 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123952 | GIR_RootConstrainSelectedInstOperands, |
| 123953 | // GIR_Coverage, 11442, |
| 123954 | GIR_EraseRootFromParent_Done, |
| 123955 | // Label 5976: @399703 |
| 123956 | GIM_Try, /*On fail goto*//*Label 5977*/ GIMT_Encode4(399838), // Rule ID 11443 // |
| 123957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 123962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 123963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 123964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 123965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 123966 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 123967 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 123968 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123969 | // MIs[3] VOP3Mods:src1:src1_mods |
| 123970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 123971 | // MIs[3] VOP3Mods:src0:src0_mods |
| 123972 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 123973 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 123974 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 123975 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 123976 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 123977 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 123978 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 123979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 123980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 123981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 123982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 123983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 123984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 123985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 123986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 123987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 123990 | GIR_RootConstrainSelectedInstOperands, |
| 123991 | // GIR_Coverage, 11443, |
| 123992 | GIR_EraseRootFromParent_Done, |
| 123993 | // Label 5977: @399838 |
| 123994 | GIM_Try, /*On fail goto*//*Label 5978*/ GIMT_Encode4(399973), // Rule ID 11444 // |
| 123995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 123996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 123997 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 123998 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 123999 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124000 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124001 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 124002 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124003 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124004 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124005 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124006 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124007 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124009 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124010 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124011 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124012 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124013 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124014 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124015 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124016 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 124020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 124021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124023 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124025 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124026 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124027 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124028 | GIR_RootConstrainSelectedInstOperands, |
| 124029 | // GIR_Coverage, 11444, |
| 124030 | GIR_EraseRootFromParent_Done, |
| 124031 | // Label 5978: @399973 |
| 124032 | GIM_Try, /*On fail goto*//*Label 5979*/ GIMT_Encode4(400108), // Rule ID 11445 // |
| 124033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124038 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124039 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 124040 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124041 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124042 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124043 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124044 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124045 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124046 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124047 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124048 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124049 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124050 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124051 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124052 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124053 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124054 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 124058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 124059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124063 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124064 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124065 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124066 | GIR_RootConstrainSelectedInstOperands, |
| 124067 | // GIR_Coverage, 11445, |
| 124068 | GIR_EraseRootFromParent_Done, |
| 124069 | // Label 5979: @400108 |
| 124070 | GIM_Try, /*On fail goto*//*Label 5980*/ GIMT_Encode4(400243), // Rule ID 11513 // |
| 124071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124072 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124073 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124074 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124075 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124076 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124077 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124078 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124079 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124080 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124081 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124082 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124083 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124085 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124086 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124087 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124088 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124089 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124090 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124091 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124092 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124094 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124104 | GIR_RootConstrainSelectedInstOperands, |
| 124105 | // GIR_Coverage, 11513, |
| 124106 | GIR_EraseRootFromParent_Done, |
| 124107 | // Label 5980: @400243 |
| 124108 | GIM_Try, /*On fail goto*//*Label 5981*/ GIMT_Encode4(400378), // Rule ID 11514 // |
| 124109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124112 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124114 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124115 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124116 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124117 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124118 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124119 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124120 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124121 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124123 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124124 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124125 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124126 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124127 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124128 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124129 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124130 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124142 | GIR_RootConstrainSelectedInstOperands, |
| 124143 | // GIR_Coverage, 11514, |
| 124144 | GIR_EraseRootFromParent_Done, |
| 124145 | // Label 5981: @400378 |
| 124146 | GIM_Try, /*On fail goto*//*Label 5982*/ GIMT_Encode4(400513), // Rule ID 11515 // |
| 124147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124149 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124150 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124151 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124152 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124153 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124154 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124155 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124156 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124157 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124158 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124159 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124160 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124161 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124162 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124163 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124164 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124165 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124166 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124167 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124168 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124170 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124180 | GIR_RootConstrainSelectedInstOperands, |
| 124181 | // GIR_Coverage, 11515, |
| 124182 | GIR_EraseRootFromParent_Done, |
| 124183 | // Label 5982: @400513 |
| 124184 | GIM_Try, /*On fail goto*//*Label 5983*/ GIMT_Encode4(400648), // Rule ID 11516 // |
| 124185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124186 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124188 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124189 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124190 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124191 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124192 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124193 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124194 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124195 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124196 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124197 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124198 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124199 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124200 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124201 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124202 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124203 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124204 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124205 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124206 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124216 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124217 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124218 | GIR_RootConstrainSelectedInstOperands, |
| 124219 | // GIR_Coverage, 11516, |
| 124220 | GIR_EraseRootFromParent_Done, |
| 124221 | // Label 5983: @400648 |
| 124222 | GIM_Try, /*On fail goto*//*Label 5984*/ GIMT_Encode4(400783), // Rule ID 11453 // |
| 124223 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124224 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124225 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124226 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124227 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124228 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124229 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124230 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124231 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124232 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124233 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124234 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124235 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124237 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124238 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124239 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124240 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124241 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124242 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124243 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124244 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124253 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124254 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124256 | GIR_RootConstrainSelectedInstOperands, |
| 124257 | // GIR_Coverage, 11453, |
| 124258 | GIR_EraseRootFromParent_Done, |
| 124259 | // Label 5984: @400783 |
| 124260 | GIM_Try, /*On fail goto*//*Label 5985*/ GIMT_Encode4(400918), // Rule ID 11454 // |
| 124261 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124264 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124265 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124266 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124267 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124268 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124269 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124270 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124271 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124272 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124273 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124274 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124275 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124276 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124277 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124278 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124279 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124280 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124281 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124282 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124293 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124294 | GIR_RootConstrainSelectedInstOperands, |
| 124295 | // GIR_Coverage, 11454, |
| 124296 | GIR_EraseRootFromParent_Done, |
| 124297 | // Label 5985: @400918 |
| 124298 | GIM_Try, /*On fail goto*//*Label 5986*/ GIMT_Encode4(401053), // Rule ID 11455 // |
| 124299 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124300 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124301 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124302 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124303 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124304 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124305 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124306 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124307 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124308 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124309 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124310 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124311 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124312 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124313 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124314 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124315 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124316 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124317 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124318 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124319 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124320 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124329 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124330 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124331 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124332 | GIR_RootConstrainSelectedInstOperands, |
| 124333 | // GIR_Coverage, 11455, |
| 124334 | GIR_EraseRootFromParent_Done, |
| 124335 | // Label 5986: @401053 |
| 124336 | GIM_Try, /*On fail goto*//*Label 5987*/ GIMT_Encode4(401188), // Rule ID 11456 // |
| 124337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124339 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124340 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124341 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124342 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124343 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124344 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 124345 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124346 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124347 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124348 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124349 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124350 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124351 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124352 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124353 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124354 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124355 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124356 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124357 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124358 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124370 | GIR_RootConstrainSelectedInstOperands, |
| 124371 | // GIR_Coverage, 11456, |
| 124372 | GIR_EraseRootFromParent_Done, |
| 124373 | // Label 5987: @401188 |
| 124374 | GIM_Try, /*On fail goto*//*Label 5988*/ GIMT_Encode4(401323), // Rule ID 11498 // |
| 124375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124376 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124377 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124378 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124379 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124380 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124381 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124382 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124383 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124384 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124385 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124386 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124387 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124388 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124389 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124390 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124391 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124392 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124393 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124394 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124395 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124396 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124400 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124408 | GIR_RootConstrainSelectedInstOperands, |
| 124409 | // GIR_Coverage, 11498, |
| 124410 | GIR_EraseRootFromParent_Done, |
| 124411 | // Label 5988: @401323 |
| 124412 | GIM_Try, /*On fail goto*//*Label 5989*/ GIMT_Encode4(401458), // Rule ID 11499 // |
| 124413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124416 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124417 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124418 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124419 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124420 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124421 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124422 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124423 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124424 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124425 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124427 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124428 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124429 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124430 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124431 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124432 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124433 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124434 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124445 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124446 | GIR_RootConstrainSelectedInstOperands, |
| 124447 | // GIR_Coverage, 11499, |
| 124448 | GIR_EraseRootFromParent_Done, |
| 124449 | // Label 5989: @401458 |
| 124450 | GIM_Try, /*On fail goto*//*Label 5990*/ GIMT_Encode4(401593), // Rule ID 11500 // |
| 124451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124452 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124453 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124454 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124455 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124456 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124457 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124458 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124459 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124460 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124461 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124462 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124463 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124464 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124465 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124466 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124467 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124468 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124469 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124470 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124471 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124472 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124481 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124484 | GIR_RootConstrainSelectedInstOperands, |
| 124485 | // GIR_Coverage, 11500, |
| 124486 | GIR_EraseRootFromParent_Done, |
| 124487 | // Label 5990: @401593 |
| 124488 | GIM_Try, /*On fail goto*//*Label 5991*/ GIMT_Encode4(401728), // Rule ID 11501 // |
| 124489 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124491 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124492 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124493 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124494 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124495 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124496 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124497 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124498 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124499 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124500 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124501 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124502 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124503 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124504 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124505 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124506 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124507 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124508 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124509 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124510 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124521 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124522 | GIR_RootConstrainSelectedInstOperands, |
| 124523 | // GIR_Coverage, 11501, |
| 124524 | GIR_EraseRootFromParent_Done, |
| 124525 | // Label 5991: @401728 |
| 124526 | GIM_Try, /*On fail goto*//*Label 5992*/ GIMT_Encode4(401863), // Rule ID 11438 // |
| 124527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124529 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124530 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124531 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124532 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124533 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124534 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124535 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124536 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124537 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124538 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124539 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124541 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124542 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124543 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124544 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124545 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124546 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124547 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124548 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124557 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124560 | GIR_RootConstrainSelectedInstOperands, |
| 124561 | // GIR_Coverage, 11438, |
| 124562 | GIR_EraseRootFromParent_Done, |
| 124563 | // Label 5992: @401863 |
| 124564 | GIM_Try, /*On fail goto*//*Label 5993*/ GIMT_Encode4(401998), // Rule ID 11439 // |
| 124565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124570 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124571 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124572 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124573 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124574 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124575 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124576 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124577 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124578 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124579 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124580 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124581 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124582 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124583 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124584 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124585 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124586 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124598 | GIR_RootConstrainSelectedInstOperands, |
| 124599 | // GIR_Coverage, 11439, |
| 124600 | GIR_EraseRootFromParent_Done, |
| 124601 | // Label 5993: @401998 |
| 124602 | GIM_Try, /*On fail goto*//*Label 5994*/ GIMT_Encode4(402133), // Rule ID 11440 // |
| 124603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124605 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124606 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124607 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124608 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124609 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124610 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124611 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124612 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124613 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124614 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124615 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124616 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124617 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124618 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124619 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124620 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124621 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124622 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124623 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124624 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124626 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124634 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124636 | GIR_RootConstrainSelectedInstOperands, |
| 124637 | // GIR_Coverage, 11440, |
| 124638 | GIR_EraseRootFromParent_Done, |
| 124639 | // Label 5994: @402133 |
| 124640 | GIM_Try, /*On fail goto*//*Label 5995*/ GIMT_Encode4(402268), // Rule ID 11441 // |
| 124641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMed3_16), |
| 124642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124643 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124644 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124645 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124646 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124647 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124648 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 124649 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124650 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124651 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 124652 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124653 | // MIs[3] VOP3Mods:src1:src1_mods |
| 124654 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 124655 | // MIs[3] VOP3Mods:src0:src0_mods |
| 124656 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 124657 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 124658 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 124659 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124660 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124661 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124662 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 124664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 124668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124673 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124674 | GIR_RootConstrainSelectedInstOperands, |
| 124675 | // GIR_Coverage, 11441, |
| 124676 | GIR_EraseRootFromParent_Done, |
| 124677 | // Label 5995: @402268 |
| 124678 | GIM_Try, /*On fail goto*//*Label 5996*/ GIMT_Encode4(402380), // Rule ID 11940 // |
| 124679 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124681 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124682 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 124683 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124684 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124685 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124686 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124687 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124688 | GIM_CheckHasOneUse, /*MI*/2, |
| 124689 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 124690 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124692 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124693 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124694 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 124700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 124701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124703 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124704 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124705 | GIR_RootConstrainSelectedInstOperands, |
| 124706 | // GIR_Coverage, 11940, |
| 124707 | GIR_EraseRootFromParent_Done, |
| 124708 | // Label 5996: @402380 |
| 124709 | GIM_Try, /*On fail goto*//*Label 5997*/ GIMT_Encode4(402492), // Rule ID 11939 // |
| 124710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124711 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124712 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124713 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 124714 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124715 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124716 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124717 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124718 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124719 | GIM_CheckHasOneUse, /*MI*/2, |
| 124720 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 124721 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124723 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124724 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124725 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124727 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 124731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 124732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124734 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124736 | GIR_RootConstrainSelectedInstOperands, |
| 124737 | // GIR_Coverage, 11939, |
| 124738 | GIR_EraseRootFromParent_Done, |
| 124739 | // Label 5997: @402492 |
| 124740 | GIM_Try, /*On fail goto*//*Label 5998*/ GIMT_Encode4(402604), // Rule ID 7409 // |
| 124741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 124745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124746 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124747 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124748 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124749 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124750 | GIM_CheckHasOneUse, /*MI*/2, |
| 124751 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 124752 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124754 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124755 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124756 | // (fmaxnum_ieee:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124757 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124758 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124765 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124766 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124767 | GIR_RootConstrainSelectedInstOperands, |
| 124768 | // GIR_Coverage, 7409, |
| 124769 | GIR_EraseRootFromParent_Done, |
| 124770 | // Label 5998: @402604 |
| 124771 | GIM_Try, /*On fail goto*//*Label 5999*/ GIMT_Encode4(402716), // Rule ID 7408 // |
| 124772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 124776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124777 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 124778 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124779 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 124780 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 124781 | GIM_CheckHasOneUse, /*MI*/2, |
| 124782 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 124783 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 124784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124785 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124786 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124787 | // (fmaxnum_ieee:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124788 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124789 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124798 | GIR_RootConstrainSelectedInstOperands, |
| 124799 | // GIR_Coverage, 7408, |
| 124800 | GIR_EraseRootFromParent_Done, |
| 124801 | // Label 5999: @402716 |
| 124802 | GIM_Try, /*On fail goto*//*Label 6000*/ GIMT_Encode4(402812), // Rule ID 11924 // |
| 124803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124804 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124805 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124806 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124807 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124808 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124809 | GIM_CheckHasOneUse, /*MI*/1, |
| 124810 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124812 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124813 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124814 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 124820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 124821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124825 | GIR_RootConstrainSelectedInstOperands, |
| 124826 | // GIR_Coverage, 11924, |
| 124827 | GIR_EraseRootFromParent_Done, |
| 124828 | // Label 6000: @402812 |
| 124829 | GIM_Try, /*On fail goto*//*Label 6001*/ GIMT_Encode4(402908), // Rule ID 11923 // |
| 124830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124831 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124832 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 124833 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124834 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124835 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124836 | GIM_CheckHasOneUse, /*MI*/1, |
| 124837 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124838 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124839 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124840 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124841 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 124845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 124847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 124848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 124849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 124850 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124852 | GIR_RootConstrainSelectedInstOperands, |
| 124853 | // GIR_Coverage, 11923, |
| 124854 | GIR_EraseRootFromParent_Done, |
| 124855 | // Label 6001: @402908 |
| 124856 | GIM_Try, /*On fail goto*//*Label 6002*/ GIMT_Encode4(403004), // Rule ID 7393 // |
| 124857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124859 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124860 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 124861 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124862 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124863 | GIM_CheckHasOneUse, /*MI*/1, |
| 124864 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124865 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124866 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124867 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124868 | // (fmaxnum_ieee:{ *:[f16] } (fminnum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124877 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124878 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124879 | GIR_RootConstrainSelectedInstOperands, |
| 124880 | // GIR_Coverage, 7393, |
| 124881 | GIR_EraseRootFromParent_Done, |
| 124882 | // Label 6002: @403004 |
| 124883 | GIM_Try, /*On fail goto*//*Label 6003*/ GIMT_Encode4(403100), // Rule ID 7392 // |
| 124884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 124885 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124886 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 124887 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 124888 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 124889 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 124890 | GIM_CheckHasOneUse, /*MI*/1, |
| 124891 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 124892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 124893 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124894 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124895 | // (fmaxnum_ieee:{ *:[f16] } (fminnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 124896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F16_e64), |
| 124897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 124899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 124901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 124903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 124904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124905 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 124906 | GIR_RootConstrainSelectedInstOperands, |
| 124907 | // GIR_Coverage, 7392, |
| 124908 | GIR_EraseRootFromParent_Done, |
| 124909 | // Label 6003: @403100 |
| 124910 | GIM_Try, /*On fail goto*//*Label 6004*/ GIMT_Encode4(403135), // Rule ID 104 // |
| 124911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 124912 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 124913 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 124914 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 124915 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18520), |
| 124916 | // (fmaxnum_ieee:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18520>> => (S_MAX_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 124917 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F16), |
| 124918 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 124919 | GIR_RootConstrainSelectedInstOperands, |
| 124920 | // GIR_Coverage, 104, |
| 124921 | GIR_Done, |
| 124922 | // Label 6004: @403135 |
| 124923 | GIM_Try, /*On fail goto*//*Label 6005*/ GIMT_Encode4(403198), // Rule ID 809 // |
| 124924 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 124925 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 124927 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124928 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 124929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 124930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 124932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 124934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 124936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 124937 | GIR_RootConstrainSelectedInstOperands, |
| 124938 | // GIR_Coverage, 809, |
| 124939 | GIR_EraseRootFromParent_Done, |
| 124940 | // Label 6005: @403198 |
| 124941 | GIM_Try, /*On fail goto*//*Label 6006*/ GIMT_Encode4(403261), // Rule ID 813 // |
| 124942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 124943 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 124945 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 124946 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 124947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 124948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 124950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 124951 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 124952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 124953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 124954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 124955 | GIR_RootConstrainSelectedInstOperands, |
| 124956 | // GIR_Coverage, 813, |
| 124957 | GIR_EraseRootFromParent_Done, |
| 124958 | // Label 6006: @403261 |
| 124959 | GIM_Try, /*On fail goto*//*Label 6007*/ GIMT_Encode4(403324), // Rule ID 8070 // |
| 124960 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 124961 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 124964 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 124965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 124966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 124968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 124970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 124972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 124973 | GIR_RootConstrainSelectedInstOperands, |
| 124974 | // GIR_Coverage, 8070, |
| 124975 | GIR_EraseRootFromParent_Done, |
| 124976 | // Label 6007: @403324 |
| 124977 | GIM_Try, /*On fail goto*//*Label 6008*/ GIMT_Encode4(403387), // Rule ID 8072 // |
| 124978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 124979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 124980 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 124981 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 124982 | // (fmaxnum_ieee:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 124983 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 124984 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 124985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 124986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 124987 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 124988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 124989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 124990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 124991 | GIR_RootConstrainSelectedInstOperands, |
| 124992 | // GIR_Coverage, 8072, |
| 124993 | GIR_EraseRootFromParent_Done, |
| 124994 | // Label 6008: @403387 |
| 124995 | GIM_Try, /*On fail goto*//*Label 6009*/ GIMT_Encode4(403449), // Rule ID 811 // |
| 124996 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 124997 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 124998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 124999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 125000 | // (fmaxnum_ieee:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 125001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64), |
| 125002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 125004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 125006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125010 | GIR_RootConstrainSelectedInstOperands, |
| 125011 | // GIR_Coverage, 811, |
| 125012 | GIR_EraseRootFromParent_Done, |
| 125013 | // Label 6009: @403449 |
| 125014 | GIM_Reject, |
| 125015 | // Label 5867: @403450 |
| 125016 | GIM_Reject, |
| 125017 | // Label 5863: @403451 |
| 125018 | GIM_Try, /*On fail goto*//*Label 6010*/ GIMT_Encode4(420962), |
| 125019 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 125020 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 125021 | GIM_Try, /*On fail goto*//*Label 6011*/ GIMT_Encode4(403591), // Rule ID 11027 // |
| 125022 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125023 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125024 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125025 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125026 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125027 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125028 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125029 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125030 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125031 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125032 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125033 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125034 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125035 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125036 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125037 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125038 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125039 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125040 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125041 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125042 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125053 | GIR_RootConstrainSelectedInstOperands, |
| 125054 | // GIR_Coverage, 11027, |
| 125055 | GIR_EraseRootFromParent_Done, |
| 125056 | // Label 6011: @403591 |
| 125057 | GIM_Try, /*On fail goto*//*Label 6012*/ GIMT_Encode4(403720), // Rule ID 11028 // |
| 125058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125060 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125061 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125062 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125063 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125064 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125065 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125066 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125067 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125068 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125069 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125070 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125071 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125072 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125073 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125074 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125075 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125076 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125077 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125078 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125079 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125080 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125088 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125089 | GIR_RootConstrainSelectedInstOperands, |
| 125090 | // GIR_Coverage, 11028, |
| 125091 | GIR_EraseRootFromParent_Done, |
| 125092 | // Label 6012: @403720 |
| 125093 | GIM_Try, /*On fail goto*//*Label 6013*/ GIMT_Encode4(403849), // Rule ID 11031 // |
| 125094 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125095 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125096 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125097 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125098 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125099 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125100 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125101 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125102 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125103 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125104 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125105 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125106 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125107 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125108 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125109 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125110 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125111 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125112 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125113 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125114 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125123 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125124 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125125 | GIR_RootConstrainSelectedInstOperands, |
| 125126 | // GIR_Coverage, 11031, |
| 125127 | GIR_EraseRootFromParent_Done, |
| 125128 | // Label 6013: @403849 |
| 125129 | GIM_Try, /*On fail goto*//*Label 6014*/ GIMT_Encode4(403978), // Rule ID 11032 // |
| 125130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125131 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125132 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125133 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125134 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125135 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125136 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125137 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125138 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125139 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125140 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125141 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125142 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125143 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125144 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125145 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125146 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125147 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125148 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125149 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125150 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125157 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125159 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125160 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125161 | GIR_RootConstrainSelectedInstOperands, |
| 125162 | // GIR_Coverage, 11032, |
| 125163 | GIR_EraseRootFromParent_Done, |
| 125164 | // Label 6014: @403978 |
| 125165 | GIM_Try, /*On fail goto*//*Label 6015*/ GIMT_Encode4(404107), // Rule ID 11012 // |
| 125166 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125167 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125168 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125169 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125170 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125171 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125172 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125173 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125174 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125175 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125176 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125177 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125178 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125179 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125180 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125181 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125182 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125183 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125184 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125185 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125186 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125197 | GIR_RootConstrainSelectedInstOperands, |
| 125198 | // GIR_Coverage, 11012, |
| 125199 | GIR_EraseRootFromParent_Done, |
| 125200 | // Label 6015: @404107 |
| 125201 | GIM_Try, /*On fail goto*//*Label 6016*/ GIMT_Encode4(404236), // Rule ID 11013 // |
| 125202 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125203 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125204 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125205 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125206 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125207 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125208 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125209 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125210 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125211 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125212 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125213 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125214 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125215 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125216 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125217 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125218 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125219 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125220 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125221 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125222 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125232 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125233 | GIR_RootConstrainSelectedInstOperands, |
| 125234 | // GIR_Coverage, 11013, |
| 125235 | GIR_EraseRootFromParent_Done, |
| 125236 | // Label 6016: @404236 |
| 125237 | GIM_Try, /*On fail goto*//*Label 6017*/ GIMT_Encode4(404365), // Rule ID 11016 // |
| 125238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125239 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125240 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125241 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125242 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125243 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125244 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125245 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125246 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125247 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125248 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125249 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125250 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125251 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125252 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125253 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125254 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125255 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125256 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125257 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125258 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125269 | GIR_RootConstrainSelectedInstOperands, |
| 125270 | // GIR_Coverage, 11016, |
| 125271 | GIR_EraseRootFromParent_Done, |
| 125272 | // Label 6017: @404365 |
| 125273 | GIM_Try, /*On fail goto*//*Label 6018*/ GIMT_Encode4(404494), // Rule ID 11017 // |
| 125274 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125275 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125276 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125277 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125278 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125279 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125280 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125281 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125282 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125283 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125284 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125285 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125286 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125287 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125288 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125289 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125290 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125291 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125292 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125293 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125294 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125305 | GIR_RootConstrainSelectedInstOperands, |
| 125306 | // GIR_Coverage, 11017, |
| 125307 | GIR_EraseRootFromParent_Done, |
| 125308 | // Label 6018: @404494 |
| 125309 | GIM_Try, /*On fail goto*//*Label 6019*/ GIMT_Encode4(404623), // Rule ID 7321 // |
| 125310 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125311 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125312 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125313 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125314 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125315 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125316 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125317 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125318 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125319 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125320 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125321 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125322 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125323 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125324 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125325 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125326 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125327 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125328 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125329 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125330 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125335 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125337 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125338 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125341 | GIR_RootConstrainSelectedInstOperands, |
| 125342 | // GIR_Coverage, 7321, |
| 125343 | GIR_EraseRootFromParent_Done, |
| 125344 | // Label 6019: @404623 |
| 125345 | GIM_Try, /*On fail goto*//*Label 6020*/ GIMT_Encode4(404752), // Rule ID 11026 // |
| 125346 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125347 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125348 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125349 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125350 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125351 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125352 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125353 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125354 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125355 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125356 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125357 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125358 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125359 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125360 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125361 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125362 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125363 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125364 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125365 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125366 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125377 | GIR_RootConstrainSelectedInstOperands, |
| 125378 | // GIR_Coverage, 11026, |
| 125379 | GIR_EraseRootFromParent_Done, |
| 125380 | // Label 6020: @404752 |
| 125381 | GIM_Try, /*On fail goto*//*Label 6021*/ GIMT_Encode4(404881), // Rule ID 11029 // |
| 125382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125383 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125384 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125385 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125386 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125387 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125388 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125389 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125390 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125391 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125392 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125393 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125394 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125395 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125396 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125397 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125398 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125399 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125400 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125401 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125402 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125404 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125411 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125412 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125413 | GIR_RootConstrainSelectedInstOperands, |
| 125414 | // GIR_Coverage, 11029, |
| 125415 | GIR_EraseRootFromParent_Done, |
| 125416 | // Label 6021: @404881 |
| 125417 | GIM_Try, /*On fail goto*//*Label 6022*/ GIMT_Encode4(405010), // Rule ID 11030 // |
| 125418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125419 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125420 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125421 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125422 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125423 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125424 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125425 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125426 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125427 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125428 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125429 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125430 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125431 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125432 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125433 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125434 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125435 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125436 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125437 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125438 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125440 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125447 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125448 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125449 | GIR_RootConstrainSelectedInstOperands, |
| 125450 | // GIR_Coverage, 11030, |
| 125451 | GIR_EraseRootFromParent_Done, |
| 125452 | // Label 6022: @405010 |
| 125453 | GIM_Try, /*On fail goto*//*Label 6023*/ GIMT_Encode4(405139), // Rule ID 7320 // |
| 125454 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125455 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125456 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125457 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125458 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125459 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125460 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125461 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125462 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125463 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125464 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125465 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125466 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125467 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125468 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125469 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125470 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125471 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125472 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125473 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125474 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125485 | GIR_RootConstrainSelectedInstOperands, |
| 125486 | // GIR_Coverage, 7320, |
| 125487 | GIR_EraseRootFromParent_Done, |
| 125488 | // Label 6023: @405139 |
| 125489 | GIM_Try, /*On fail goto*//*Label 6024*/ GIMT_Encode4(405268), // Rule ID 11011 // |
| 125490 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125491 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125492 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125493 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125494 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125495 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125496 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125497 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125498 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125499 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125500 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125501 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125502 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125503 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125504 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125505 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125506 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125507 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125508 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125509 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125510 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125519 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125520 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125521 | GIR_RootConstrainSelectedInstOperands, |
| 125522 | // GIR_Coverage, 11011, |
| 125523 | GIR_EraseRootFromParent_Done, |
| 125524 | // Label 6024: @405268 |
| 125525 | GIM_Try, /*On fail goto*//*Label 6025*/ GIMT_Encode4(405397), // Rule ID 11014 // |
| 125526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125530 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125531 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125532 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125533 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125534 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125535 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125536 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125537 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125538 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125539 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125541 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125542 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125543 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125544 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125545 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125546 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125555 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125556 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125557 | GIR_RootConstrainSelectedInstOperands, |
| 125558 | // GIR_Coverage, 11014, |
| 125559 | GIR_EraseRootFromParent_Done, |
| 125560 | // Label 6025: @405397 |
| 125561 | GIM_Try, /*On fail goto*//*Label 6026*/ GIMT_Encode4(405526), // Rule ID 11015 // |
| 125562 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125563 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125564 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125565 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125566 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125567 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125568 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125569 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125570 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125571 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125572 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125573 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125574 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125575 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125576 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125577 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125578 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125579 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125580 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125581 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125582 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125591 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125593 | GIR_RootConstrainSelectedInstOperands, |
| 125594 | // GIR_Coverage, 11015, |
| 125595 | GIR_EraseRootFromParent_Done, |
| 125596 | // Label 6026: @405526 |
| 125597 | GIM_Try, /*On fail goto*//*Label 6027*/ GIMT_Encode4(405655), // Rule ID 10997 // |
| 125598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125599 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125600 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125601 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125602 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125603 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125604 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125605 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125606 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125607 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125608 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125609 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125610 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125611 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125612 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125613 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125614 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125615 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125616 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125617 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125618 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125620 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125629 | GIR_RootConstrainSelectedInstOperands, |
| 125630 | // GIR_Coverage, 10997, |
| 125631 | GIR_EraseRootFromParent_Done, |
| 125632 | // Label 6027: @405655 |
| 125633 | GIM_Try, /*On fail goto*//*Label 6028*/ GIMT_Encode4(405784), // Rule ID 10998 // |
| 125634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125635 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125636 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125637 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125638 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125639 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125640 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125641 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125642 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125643 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125644 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125645 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125646 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125647 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125648 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125649 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125650 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125651 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125652 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125653 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125654 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125665 | GIR_RootConstrainSelectedInstOperands, |
| 125666 | // GIR_Coverage, 10998, |
| 125667 | GIR_EraseRootFromParent_Done, |
| 125668 | // Label 6028: @405784 |
| 125669 | GIM_Try, /*On fail goto*//*Label 6029*/ GIMT_Encode4(405913), // Rule ID 11001 // |
| 125670 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125671 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125672 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125673 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125674 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125676 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125678 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125679 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125680 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125681 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125682 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125683 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125684 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125685 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125686 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125687 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125688 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125689 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125690 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125698 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125699 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125700 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125701 | GIR_RootConstrainSelectedInstOperands, |
| 125702 | // GIR_Coverage, 11001, |
| 125703 | GIR_EraseRootFromParent_Done, |
| 125704 | // Label 6029: @405913 |
| 125705 | GIM_Try, /*On fail goto*//*Label 6030*/ GIMT_Encode4(406042), // Rule ID 11002 // |
| 125706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125710 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125711 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125712 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125713 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125714 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125715 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125716 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125717 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125718 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125719 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125720 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125721 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125722 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125723 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125724 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125725 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125726 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125730 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125731 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125735 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125736 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125737 | GIR_RootConstrainSelectedInstOperands, |
| 125738 | // GIR_Coverage, 11002, |
| 125739 | GIR_EraseRootFromParent_Done, |
| 125740 | // Label 6030: @406042 |
| 125741 | GIM_Try, /*On fail goto*//*Label 6031*/ GIMT_Encode4(406171), // Rule ID 10982 // |
| 125742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125748 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125749 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125750 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125751 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125752 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125753 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125754 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125755 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125756 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125757 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125758 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125759 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125760 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125761 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125762 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125767 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125771 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125772 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125773 | GIR_RootConstrainSelectedInstOperands, |
| 125774 | // GIR_Coverage, 10982, |
| 125775 | GIR_EraseRootFromParent_Done, |
| 125776 | // Label 6031: @406171 |
| 125777 | GIM_Try, /*On fail goto*//*Label 6032*/ GIMT_Encode4(406300), // Rule ID 10983 // |
| 125778 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125779 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125780 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125781 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125782 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125783 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125784 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125785 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125786 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125787 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125788 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125789 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125790 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125791 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125792 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125793 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125794 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125795 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125796 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125797 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125798 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125806 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125807 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125808 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125809 | GIR_RootConstrainSelectedInstOperands, |
| 125810 | // GIR_Coverage, 10983, |
| 125811 | GIR_EraseRootFromParent_Done, |
| 125812 | // Label 6032: @406300 |
| 125813 | GIM_Try, /*On fail goto*//*Label 6033*/ GIMT_Encode4(406429), // Rule ID 10986 // |
| 125814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125815 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125816 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125817 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125818 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125819 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125820 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125821 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125822 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125823 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125824 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125825 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125826 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125827 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125828 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125829 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125830 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125831 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125832 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125833 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125834 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125843 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125844 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125845 | GIR_RootConstrainSelectedInstOperands, |
| 125846 | // GIR_Coverage, 10986, |
| 125847 | GIR_EraseRootFromParent_Done, |
| 125848 | // Label 6033: @406429 |
| 125849 | GIM_Try, /*On fail goto*//*Label 6034*/ GIMT_Encode4(406558), // Rule ID 10987 // |
| 125850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125851 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125852 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125853 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125854 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125855 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125856 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125857 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125858 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125859 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 125860 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 125861 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125862 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125863 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125864 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125865 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125866 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125867 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125868 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125869 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125870 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125877 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125879 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125880 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125881 | GIR_RootConstrainSelectedInstOperands, |
| 125882 | // GIR_Coverage, 10987, |
| 125883 | GIR_EraseRootFromParent_Done, |
| 125884 | // Label 6034: @406558 |
| 125885 | GIM_Try, /*On fail goto*//*Label 6035*/ GIMT_Encode4(406687), // Rule ID 7319 // |
| 125886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125887 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125888 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125889 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125890 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125891 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125892 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125893 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125894 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125895 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125896 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125897 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125898 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125899 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125900 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125901 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125902 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125903 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125904 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125905 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125906 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125912 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125915 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125916 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125917 | GIR_RootConstrainSelectedInstOperands, |
| 125918 | // GIR_Coverage, 7319, |
| 125919 | GIR_EraseRootFromParent_Done, |
| 125920 | // Label 6035: @406687 |
| 125921 | GIM_Try, /*On fail goto*//*Label 6036*/ GIMT_Encode4(406816), // Rule ID 10996 // |
| 125922 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125923 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125924 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125925 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125926 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125927 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125928 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125929 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125930 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125931 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125932 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125933 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125934 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125935 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125936 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125937 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125938 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125939 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125940 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125941 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125942 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125943 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125944 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 125946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 125947 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 125948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 125949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125951 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125952 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125953 | GIR_RootConstrainSelectedInstOperands, |
| 125954 | // GIR_Coverage, 10996, |
| 125955 | GIR_EraseRootFromParent_Done, |
| 125956 | // Label 6036: @406816 |
| 125957 | GIM_Try, /*On fail goto*//*Label 6037*/ GIMT_Encode4(406945), // Rule ID 10999 // |
| 125958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 125964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 125965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 125966 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 125967 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 125968 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 125969 | // MIs[3] VOP3Mods:src0:src0_mods |
| 125970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 125971 | // MIs[3] VOP3Mods:src1:src1_mods |
| 125972 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 125973 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 125974 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 125975 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 125976 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 125977 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 125978 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 125979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 125980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 125981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 125982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 125983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 125984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 125985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 125986 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 125987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 125989 | GIR_RootConstrainSelectedInstOperands, |
| 125990 | // GIR_Coverage, 10999, |
| 125991 | GIR_EraseRootFromParent_Done, |
| 125992 | // Label 6037: @406945 |
| 125993 | GIM_Try, /*On fail goto*//*Label 6038*/ GIMT_Encode4(407074), // Rule ID 11000 // |
| 125994 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 125995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 125996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 125997 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 125998 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 125999 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 126000 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126001 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126002 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126003 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 126004 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126005 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126006 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 126007 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 126009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126010 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126011 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126012 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126013 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126014 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126015 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126016 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126019 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126022 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126023 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126024 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126025 | GIR_RootConstrainSelectedInstOperands, |
| 126026 | // GIR_Coverage, 11000, |
| 126027 | GIR_EraseRootFromParent_Done, |
| 126028 | // Label 6038: @407074 |
| 126029 | GIM_Try, /*On fail goto*//*Label 6039*/ GIMT_Encode4(407203), // Rule ID 7318 // |
| 126030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126031 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126032 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126033 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126034 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126035 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 126036 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126037 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126038 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126039 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 126040 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126041 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126042 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 126043 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126044 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 126045 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126046 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126047 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126048 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126049 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126050 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126051 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126052 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126056 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126059 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126060 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126061 | GIR_RootConstrainSelectedInstOperands, |
| 126062 | // GIR_Coverage, 7318, |
| 126063 | GIR_EraseRootFromParent_Done, |
| 126064 | // Label 6039: @407203 |
| 126065 | GIM_Try, /*On fail goto*//*Label 6040*/ GIMT_Encode4(407332), // Rule ID 10981 // |
| 126066 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126067 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126068 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126069 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126070 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126071 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 126072 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126073 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126074 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126075 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 126076 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126077 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126078 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 126079 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126080 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 126081 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126082 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126083 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126084 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126085 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126086 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126095 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126096 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126097 | GIR_RootConstrainSelectedInstOperands, |
| 126098 | // GIR_Coverage, 10981, |
| 126099 | GIR_EraseRootFromParent_Done, |
| 126100 | // Label 6040: @407332 |
| 126101 | GIM_Try, /*On fail goto*//*Label 6041*/ GIMT_Encode4(407461), // Rule ID 10984 // |
| 126102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126103 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126104 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126105 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126106 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126107 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 126108 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126109 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126110 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126111 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 126112 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126113 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126114 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 126115 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126116 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 126117 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126118 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126119 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126120 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126121 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126122 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126131 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126133 | GIR_RootConstrainSelectedInstOperands, |
| 126134 | // GIR_Coverage, 10984, |
| 126135 | GIR_EraseRootFromParent_Done, |
| 126136 | // Label 6041: @407461 |
| 126137 | GIM_Try, /*On fail goto*//*Label 6042*/ GIMT_Encode4(407590), // Rule ID 10985 // |
| 126138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126139 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126140 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126141 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126142 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126143 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 126144 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126145 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126146 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126147 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 126148 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126149 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126150 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 126151 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126152 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 126153 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126154 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126155 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126156 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126157 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126158 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126167 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126168 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126169 | GIR_RootConstrainSelectedInstOperands, |
| 126170 | // GIR_Coverage, 10985, |
| 126171 | GIR_EraseRootFromParent_Done, |
| 126172 | // Label 6042: @407590 |
| 126173 | GIM_Try, /*On fail goto*//*Label 6043*/ GIMT_Encode4(407719), // Rule ID 11037 // |
| 126174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126175 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126176 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126177 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126178 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126179 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126180 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126181 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126182 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126183 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126184 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126185 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126186 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126187 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126188 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126189 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126190 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126191 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126192 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126193 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126194 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126195 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126196 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126199 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126205 | GIR_RootConstrainSelectedInstOperands, |
| 126206 | // GIR_Coverage, 11037, |
| 126207 | GIR_EraseRootFromParent_Done, |
| 126208 | // Label 6043: @407719 |
| 126209 | GIM_Try, /*On fail goto*//*Label 6044*/ GIMT_Encode4(407848), // Rule ID 11038 // |
| 126210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126211 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126212 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126213 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126214 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126215 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126216 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126217 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126218 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126219 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126220 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126221 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126222 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126223 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126224 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126225 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126226 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126227 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126228 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126229 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126230 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126232 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126241 | GIR_RootConstrainSelectedInstOperands, |
| 126242 | // GIR_Coverage, 11038, |
| 126243 | GIR_EraseRootFromParent_Done, |
| 126244 | // Label 6044: @407848 |
| 126245 | GIM_Try, /*On fail goto*//*Label 6045*/ GIMT_Encode4(407977), // Rule ID 11039 // |
| 126246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126247 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126248 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126249 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126250 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126251 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126252 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126253 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126254 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126255 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126256 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126257 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126258 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126259 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126260 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126261 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126262 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126263 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126264 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126265 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126266 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126277 | GIR_RootConstrainSelectedInstOperands, |
| 126278 | // GIR_Coverage, 11039, |
| 126279 | GIR_EraseRootFromParent_Done, |
| 126280 | // Label 6045: @407977 |
| 126281 | GIM_Try, /*On fail goto*//*Label 6046*/ GIMT_Encode4(408106), // Rule ID 11040 // |
| 126282 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126283 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126284 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126285 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126286 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126287 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126288 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126289 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126290 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126291 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126292 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126293 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126294 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126295 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126296 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126297 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126298 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126299 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126300 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126301 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126302 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126313 | GIR_RootConstrainSelectedInstOperands, |
| 126314 | // GIR_Coverage, 11040, |
| 126315 | GIR_EraseRootFromParent_Done, |
| 126316 | // Label 6046: @408106 |
| 126317 | GIM_Try, /*On fail goto*//*Label 6047*/ GIMT_Encode4(408235), // Rule ID 10977 // |
| 126318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126323 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126324 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126325 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126326 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126327 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126328 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126329 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126330 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126331 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126332 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126333 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126334 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126335 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126336 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126337 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126338 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126347 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126348 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126349 | GIR_RootConstrainSelectedInstOperands, |
| 126350 | // GIR_Coverage, 10977, |
| 126351 | GIR_EraseRootFromParent_Done, |
| 126352 | // Label 6047: @408235 |
| 126353 | GIM_Try, /*On fail goto*//*Label 6048*/ GIMT_Encode4(408364), // Rule ID 10978 // |
| 126354 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126355 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126356 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126357 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126358 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126359 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126360 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126361 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126362 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126363 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126364 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126365 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126366 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126367 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126368 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126369 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126370 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126371 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126372 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126373 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126374 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126383 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126384 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126385 | GIR_RootConstrainSelectedInstOperands, |
| 126386 | // GIR_Coverage, 10978, |
| 126387 | GIR_EraseRootFromParent_Done, |
| 126388 | // Label 6048: @408364 |
| 126389 | GIM_Try, /*On fail goto*//*Label 6049*/ GIMT_Encode4(408493), // Rule ID 10979 // |
| 126390 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126391 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126392 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126393 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126394 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126395 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126396 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126397 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126398 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126399 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126400 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126401 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126402 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126403 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126404 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126405 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126406 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126407 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126408 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126409 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126410 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126419 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126420 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126421 | GIR_RootConstrainSelectedInstOperands, |
| 126422 | // GIR_Coverage, 10979, |
| 126423 | GIR_EraseRootFromParent_Done, |
| 126424 | // Label 6049: @408493 |
| 126425 | GIM_Try, /*On fail goto*//*Label 6050*/ GIMT_Encode4(408622), // Rule ID 10980 // |
| 126426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126427 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126428 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126429 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126430 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126431 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126432 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126433 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126434 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126435 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126436 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126437 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126438 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126439 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126440 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126441 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126442 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126443 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126444 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126445 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126446 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126449 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126455 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126456 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126457 | GIR_RootConstrainSelectedInstOperands, |
| 126458 | // GIR_Coverage, 10980, |
| 126459 | GIR_EraseRootFromParent_Done, |
| 126460 | // Label 6050: @408622 |
| 126461 | GIM_Try, /*On fail goto*//*Label 6051*/ GIMT_Encode4(408751), // Rule ID 11022 // |
| 126462 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126463 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126464 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126465 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126466 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126467 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126468 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126469 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126470 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126471 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126472 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126473 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126474 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126475 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126476 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126477 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126478 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126479 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126480 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126481 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126482 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126491 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126492 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126493 | GIR_RootConstrainSelectedInstOperands, |
| 126494 | // GIR_Coverage, 11022, |
| 126495 | GIR_EraseRootFromParent_Done, |
| 126496 | // Label 6051: @408751 |
| 126497 | GIM_Try, /*On fail goto*//*Label 6052*/ GIMT_Encode4(408880), // Rule ID 11023 // |
| 126498 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126499 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126500 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126501 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126502 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126503 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126504 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126505 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126506 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126507 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126508 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126509 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126510 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126511 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126512 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126513 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126514 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126515 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126516 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126517 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126518 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126527 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126529 | GIR_RootConstrainSelectedInstOperands, |
| 126530 | // GIR_Coverage, 11023, |
| 126531 | GIR_EraseRootFromParent_Done, |
| 126532 | // Label 6052: @408880 |
| 126533 | GIM_Try, /*On fail goto*//*Label 6053*/ GIMT_Encode4(409009), // Rule ID 11024 // |
| 126534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126535 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126536 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126537 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126538 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126539 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126540 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126541 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126542 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126543 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126544 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126545 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126546 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126547 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126548 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126549 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126550 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126551 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126552 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126553 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126554 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126561 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126565 | GIR_RootConstrainSelectedInstOperands, |
| 126566 | // GIR_Coverage, 11024, |
| 126567 | GIR_EraseRootFromParent_Done, |
| 126568 | // Label 6053: @409009 |
| 126569 | GIM_Try, /*On fail goto*//*Label 6054*/ GIMT_Encode4(409138), // Rule ID 11025 // |
| 126570 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126571 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126572 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126573 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126574 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126575 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126576 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126577 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126578 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126579 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126580 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126581 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126582 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126583 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126584 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126585 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126586 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126587 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126588 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126589 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126590 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126601 | GIR_RootConstrainSelectedInstOperands, |
| 126602 | // GIR_Coverage, 11025, |
| 126603 | GIR_EraseRootFromParent_Done, |
| 126604 | // Label 6054: @409138 |
| 126605 | GIM_Try, /*On fail goto*//*Label 6055*/ GIMT_Encode4(409267), // Rule ID 10962 // |
| 126606 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126607 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126608 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126609 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126610 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126611 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126612 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126613 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126614 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126615 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126616 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126617 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126618 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126619 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126620 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126621 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126622 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126623 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126624 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126625 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126626 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126634 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126635 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126636 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126637 | GIR_RootConstrainSelectedInstOperands, |
| 126638 | // GIR_Coverage, 10962, |
| 126639 | GIR_EraseRootFromParent_Done, |
| 126640 | // Label 6055: @409267 |
| 126641 | GIM_Try, /*On fail goto*//*Label 6056*/ GIMT_Encode4(409396), // Rule ID 10963 // |
| 126642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126643 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126644 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126645 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126646 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126647 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126648 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126649 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126650 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126651 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126652 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126653 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126654 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126655 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126656 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126657 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126658 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126659 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126660 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126661 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126662 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126664 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 126668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 126669 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126671 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126672 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126673 | GIR_RootConstrainSelectedInstOperands, |
| 126674 | // GIR_Coverage, 10963, |
| 126675 | GIR_EraseRootFromParent_Done, |
| 126676 | // Label 6056: @409396 |
| 126677 | GIM_Try, /*On fail goto*//*Label 6057*/ GIMT_Encode4(409525), // Rule ID 10964 // |
| 126678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126679 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126680 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126681 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126682 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126683 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126684 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126685 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126686 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126687 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126688 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126689 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126690 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126691 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126692 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126693 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126694 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126695 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126696 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126697 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126698 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126706 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126707 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126708 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126709 | GIR_RootConstrainSelectedInstOperands, |
| 126710 | // GIR_Coverage, 10964, |
| 126711 | GIR_EraseRootFromParent_Done, |
| 126712 | // Label 6057: @409525 |
| 126713 | GIM_Try, /*On fail goto*//*Label 6058*/ GIMT_Encode4(409654), // Rule ID 10965 // |
| 126714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126715 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126716 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126717 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126718 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126719 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 126720 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 126721 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126722 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126723 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126724 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126725 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126726 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126727 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126728 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126729 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126730 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126731 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126732 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126733 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126734 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 126738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 126739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 126742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 126743 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126744 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126745 | GIR_RootConstrainSelectedInstOperands, |
| 126746 | // GIR_Coverage, 10965, |
| 126747 | GIR_EraseRootFromParent_Done, |
| 126748 | // Label 6058: @409654 |
| 126749 | GIM_Try, /*On fail goto*//*Label 6059*/ GIMT_Encode4(409783), // Rule ID 11033 // |
| 126750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126751 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126752 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126753 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126754 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126755 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126756 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126757 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126758 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126759 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126760 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126761 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126762 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126763 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126764 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126765 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126766 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126767 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126768 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126769 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126770 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126771 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126772 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126774 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126779 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126780 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126781 | GIR_RootConstrainSelectedInstOperands, |
| 126782 | // GIR_Coverage, 11033, |
| 126783 | GIR_EraseRootFromParent_Done, |
| 126784 | // Label 6059: @409783 |
| 126785 | GIM_Try, /*On fail goto*//*Label 6060*/ GIMT_Encode4(409912), // Rule ID 11034 // |
| 126786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126787 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126788 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126789 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126790 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126791 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126792 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126793 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126794 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126795 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126796 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126797 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126798 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126799 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126800 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126801 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126802 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126803 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126804 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126805 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126806 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126809 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126815 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126816 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126817 | GIR_RootConstrainSelectedInstOperands, |
| 126818 | // GIR_Coverage, 11034, |
| 126819 | GIR_EraseRootFromParent_Done, |
| 126820 | // Label 6060: @409912 |
| 126821 | GIM_Try, /*On fail goto*//*Label 6061*/ GIMT_Encode4(410041), // Rule ID 11035 // |
| 126822 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126823 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126824 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126825 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126826 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126827 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126828 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126829 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126830 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126831 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126832 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126833 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126834 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126835 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126836 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126837 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126838 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126839 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126840 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126841 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126842 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126851 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126852 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126853 | GIR_RootConstrainSelectedInstOperands, |
| 126854 | // GIR_Coverage, 11035, |
| 126855 | GIR_EraseRootFromParent_Done, |
| 126856 | // Label 6061: @410041 |
| 126857 | GIM_Try, /*On fail goto*//*Label 6062*/ GIMT_Encode4(410170), // Rule ID 11036 // |
| 126858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126859 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126860 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126861 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126862 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126863 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126864 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126865 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126866 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126867 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126868 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126869 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126870 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126871 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126872 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126873 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126874 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126875 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126876 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126877 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126878 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126888 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126889 | GIR_RootConstrainSelectedInstOperands, |
| 126890 | // GIR_Coverage, 11036, |
| 126891 | GIR_EraseRootFromParent_Done, |
| 126892 | // Label 6062: @410170 |
| 126893 | GIM_Try, /*On fail goto*//*Label 6063*/ GIMT_Encode4(410299), // Rule ID 10973 // |
| 126894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126898 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126899 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126900 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126901 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126902 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126903 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126904 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126905 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126907 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126908 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126909 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126910 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126911 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126912 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126913 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126914 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126916 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126923 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126924 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126925 | GIR_RootConstrainSelectedInstOperands, |
| 126926 | // GIR_Coverage, 10973, |
| 126927 | GIR_EraseRootFromParent_Done, |
| 126928 | // Label 6063: @410299 |
| 126929 | GIM_Try, /*On fail goto*//*Label 6064*/ GIMT_Encode4(410428), // Rule ID 10974 // |
| 126930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126934 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126935 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126936 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126937 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126938 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126939 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126940 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126941 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126942 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126943 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126945 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126946 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126947 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126948 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126949 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126950 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126951 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126952 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 126954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 126955 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 126956 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 126957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126959 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126960 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126961 | GIR_RootConstrainSelectedInstOperands, |
| 126962 | // GIR_Coverage, 10974, |
| 126963 | GIR_EraseRootFromParent_Done, |
| 126964 | // Label 6064: @410428 |
| 126965 | GIM_Try, /*On fail goto*//*Label 6065*/ GIMT_Encode4(410557), // Rule ID 10975 // |
| 126966 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 126967 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 126968 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 126969 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 126970 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 126971 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 126972 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 126973 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 126974 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 126975 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 126976 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 126977 | // MIs[3] VOP3Mods:src0:src0_mods |
| 126978 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 126979 | // MIs[3] VOP3Mods:src1:src1_mods |
| 126980 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 126981 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 126982 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 126983 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 126984 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 126985 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 126986 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 126987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 126988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 126989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 126990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 126991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 126992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 126993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 126994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 126995 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126996 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 126997 | GIR_RootConstrainSelectedInstOperands, |
| 126998 | // GIR_Coverage, 10975, |
| 126999 | GIR_EraseRootFromParent_Done, |
| 127000 | // Label 6065: @410557 |
| 127001 | GIM_Try, /*On fail goto*//*Label 6066*/ GIMT_Encode4(410686), // Rule ID 10976 // |
| 127002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127003 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127004 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127005 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127006 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127007 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127008 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127009 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127010 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127011 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127012 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127013 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127014 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127015 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127016 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127017 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127018 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127019 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127020 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127021 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127022 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127023 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127024 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127027 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127029 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127031 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127032 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127033 | GIR_RootConstrainSelectedInstOperands, |
| 127034 | // GIR_Coverage, 10976, |
| 127035 | GIR_EraseRootFromParent_Done, |
| 127036 | // Label 6066: @410686 |
| 127037 | GIM_Try, /*On fail goto*//*Label 6067*/ GIMT_Encode4(410815), // Rule ID 11018 // |
| 127038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127039 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127040 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127041 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127042 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127043 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127044 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127045 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127046 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127047 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127048 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127049 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127050 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127051 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127052 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127053 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127054 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127055 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127056 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127057 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127058 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127061 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127069 | GIR_RootConstrainSelectedInstOperands, |
| 127070 | // GIR_Coverage, 11018, |
| 127071 | GIR_EraseRootFromParent_Done, |
| 127072 | // Label 6067: @410815 |
| 127073 | GIM_Try, /*On fail goto*//*Label 6068*/ GIMT_Encode4(410944), // Rule ID 11019 // |
| 127074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127075 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127076 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127077 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127078 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127079 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127080 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127081 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127082 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127083 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127084 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127085 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127086 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127087 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127088 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127089 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127090 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127091 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127092 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127093 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127094 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127096 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127105 | GIR_RootConstrainSelectedInstOperands, |
| 127106 | // GIR_Coverage, 11019, |
| 127107 | GIR_EraseRootFromParent_Done, |
| 127108 | // Label 6068: @410944 |
| 127109 | GIM_Try, /*On fail goto*//*Label 6069*/ GIMT_Encode4(411073), // Rule ID 11020 // |
| 127110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127112 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127114 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127115 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127116 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127117 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127118 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127119 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127120 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127121 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127123 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127124 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127125 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127126 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127127 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127128 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127129 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127130 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127132 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127133 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127141 | GIR_RootConstrainSelectedInstOperands, |
| 127142 | // GIR_Coverage, 11020, |
| 127143 | GIR_EraseRootFromParent_Done, |
| 127144 | // Label 6069: @411073 |
| 127145 | GIM_Try, /*On fail goto*//*Label 6070*/ GIMT_Encode4(411202), // Rule ID 11021 // |
| 127146 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127147 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127148 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127149 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127150 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127151 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127152 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127153 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127154 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127155 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127156 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127157 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127158 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127159 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127160 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127161 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127162 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127163 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127164 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127165 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127166 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127167 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127168 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127177 | GIR_RootConstrainSelectedInstOperands, |
| 127178 | // GIR_Coverage, 11021, |
| 127179 | GIR_EraseRootFromParent_Done, |
| 127180 | // Label 6070: @411202 |
| 127181 | GIM_Try, /*On fail goto*//*Label 6071*/ GIMT_Encode4(411331), // Rule ID 10958 // |
| 127182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127183 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127184 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127185 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127186 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127187 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127188 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127189 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127190 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127191 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127192 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127193 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127194 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127195 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127196 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127197 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127198 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127199 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127200 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127201 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127202 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127213 | GIR_RootConstrainSelectedInstOperands, |
| 127214 | // GIR_Coverage, 10958, |
| 127215 | GIR_EraseRootFromParent_Done, |
| 127216 | // Label 6071: @411331 |
| 127217 | GIM_Try, /*On fail goto*//*Label 6072*/ GIMT_Encode4(411460), // Rule ID 10959 // |
| 127218 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127219 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127220 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127221 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127222 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127223 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127224 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127225 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127226 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127227 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127228 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127229 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127230 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127231 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127232 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127233 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127234 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127235 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127236 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127237 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127238 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127249 | GIR_RootConstrainSelectedInstOperands, |
| 127250 | // GIR_Coverage, 10959, |
| 127251 | GIR_EraseRootFromParent_Done, |
| 127252 | // Label 6072: @411460 |
| 127253 | GIM_Try, /*On fail goto*//*Label 6073*/ GIMT_Encode4(411589), // Rule ID 10960 // |
| 127254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127255 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127256 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127257 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127258 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127259 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127260 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127261 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127262 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127263 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127264 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127265 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127266 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127267 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127268 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127269 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127270 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127271 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127272 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127273 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127274 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127275 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127276 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127277 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127283 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127284 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127285 | GIR_RootConstrainSelectedInstOperands, |
| 127286 | // GIR_Coverage, 10960, |
| 127287 | GIR_EraseRootFromParent_Done, |
| 127288 | // Label 6073: @411589 |
| 127289 | GIM_Try, /*On fail goto*//*Label 6074*/ GIMT_Encode4(411718), // Rule ID 10961 // |
| 127290 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127291 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127292 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127293 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127294 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127295 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 127296 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127297 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127298 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127299 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 127300 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127301 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127302 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 127303 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127304 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 127305 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127306 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127307 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127308 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127309 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127310 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127311 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127312 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127321 | GIR_RootConstrainSelectedInstOperands, |
| 127322 | // GIR_Coverage, 10961, |
| 127323 | GIR_EraseRootFromParent_Done, |
| 127324 | // Label 6074: @411718 |
| 127325 | GIM_Try, /*On fail goto*//*Label 6075*/ GIMT_Encode4(411847), // Rule ID 10967 // |
| 127326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127327 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127328 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127329 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127330 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127331 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127332 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127333 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127334 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127335 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127336 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127337 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127338 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127339 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127340 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127341 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127342 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127343 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127344 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127345 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127346 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127351 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127352 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127353 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127355 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127356 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127357 | GIR_RootConstrainSelectedInstOperands, |
| 127358 | // GIR_Coverage, 10967, |
| 127359 | GIR_EraseRootFromParent_Done, |
| 127360 | // Label 6075: @411847 |
| 127361 | GIM_Try, /*On fail goto*//*Label 6076*/ GIMT_Encode4(411976), // Rule ID 10968 // |
| 127362 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127363 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127364 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127365 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127366 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127367 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127368 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127369 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127370 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127371 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127372 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127373 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127374 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127375 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127376 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127377 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127378 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127379 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127380 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127381 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127382 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127383 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127384 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127386 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127387 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127391 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127392 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127393 | GIR_RootConstrainSelectedInstOperands, |
| 127394 | // GIR_Coverage, 10968, |
| 127395 | GIR_EraseRootFromParent_Done, |
| 127396 | // Label 6076: @411976 |
| 127397 | GIM_Try, /*On fail goto*//*Label 6077*/ GIMT_Encode4(412105), // Rule ID 10971 // |
| 127398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127399 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127400 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127401 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127402 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127403 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127404 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127405 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127406 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127407 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127408 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127409 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127410 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127411 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127412 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127413 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127414 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127415 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127416 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127417 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127418 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127419 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127420 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127423 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127424 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127425 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127426 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127427 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127428 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127429 | GIR_RootConstrainSelectedInstOperands, |
| 127430 | // GIR_Coverage, 10971, |
| 127431 | GIR_EraseRootFromParent_Done, |
| 127432 | // Label 6077: @412105 |
| 127433 | GIM_Try, /*On fail goto*//*Label 6078*/ GIMT_Encode4(412234), // Rule ID 10972 // |
| 127434 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127435 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127436 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127437 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127438 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127439 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127440 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127441 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127442 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127443 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127444 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127445 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127446 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127447 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127448 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127449 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127450 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127451 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127452 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127453 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127454 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127455 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127456 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127465 | GIR_RootConstrainSelectedInstOperands, |
| 127466 | // GIR_Coverage, 10972, |
| 127467 | GIR_EraseRootFromParent_Done, |
| 127468 | // Label 6078: @412234 |
| 127469 | GIM_Try, /*On fail goto*//*Label 6079*/ GIMT_Encode4(412363), // Rule ID 10952 // |
| 127470 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127471 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127472 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127473 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127474 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127475 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127476 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127477 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127478 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127479 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127480 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127481 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127482 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127483 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127484 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127485 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127486 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127487 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127488 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127489 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127490 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127492 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127501 | GIR_RootConstrainSelectedInstOperands, |
| 127502 | // GIR_Coverage, 10952, |
| 127503 | GIR_EraseRootFromParent_Done, |
| 127504 | // Label 6079: @412363 |
| 127505 | GIM_Try, /*On fail goto*//*Label 6080*/ GIMT_Encode4(412492), // Rule ID 10953 // |
| 127506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127507 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127508 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127509 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127510 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127511 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127512 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127513 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127514 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127515 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127516 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127517 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127518 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127519 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127520 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127521 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127522 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127523 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127524 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127525 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127526 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127534 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127537 | GIR_RootConstrainSelectedInstOperands, |
| 127538 | // GIR_Coverage, 10953, |
| 127539 | GIR_EraseRootFromParent_Done, |
| 127540 | // Label 6080: @412492 |
| 127541 | GIM_Try, /*On fail goto*//*Label 6081*/ GIMT_Encode4(412621), // Rule ID 10956 // |
| 127542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127543 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127544 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127545 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127546 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127547 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127548 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127549 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127550 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127551 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127552 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127553 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127554 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127555 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127556 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127557 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127558 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127559 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127560 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127561 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127562 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127571 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127572 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127573 | GIR_RootConstrainSelectedInstOperands, |
| 127574 | // GIR_Coverage, 10956, |
| 127575 | GIR_EraseRootFromParent_Done, |
| 127576 | // Label 6081: @412621 |
| 127577 | GIM_Try, /*On fail goto*//*Label 6082*/ GIMT_Encode4(412750), // Rule ID 10957 // |
| 127578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127579 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127580 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127581 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127582 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127583 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127584 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127585 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127586 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127587 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127588 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127589 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127590 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127591 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127592 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127593 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127594 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127595 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127596 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127597 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127598 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127607 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127608 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127609 | GIR_RootConstrainSelectedInstOperands, |
| 127610 | // GIR_Coverage, 10957, |
| 127611 | GIR_EraseRootFromParent_Done, |
| 127612 | // Label 6082: @412750 |
| 127613 | GIM_Try, /*On fail goto*//*Label 6083*/ GIMT_Encode4(412879), // Rule ID 7317 // |
| 127614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127615 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127616 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127617 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127618 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127619 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127620 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127621 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127622 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127623 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127624 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127625 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127626 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127627 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127628 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127629 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127630 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127631 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127632 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127633 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127634 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127643 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127644 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127645 | GIR_RootConstrainSelectedInstOperands, |
| 127646 | // GIR_Coverage, 7317, |
| 127647 | GIR_EraseRootFromParent_Done, |
| 127648 | // Label 6083: @412879 |
| 127649 | GIM_Try, /*On fail goto*//*Label 6084*/ GIMT_Encode4(413008), // Rule ID 10966 // |
| 127650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127651 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127652 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127653 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127654 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127655 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127656 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127657 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127658 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127659 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127660 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127661 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127662 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127663 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127664 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127665 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127666 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127667 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127668 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127669 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127670 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127672 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127679 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127680 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127681 | GIR_RootConstrainSelectedInstOperands, |
| 127682 | // GIR_Coverage, 10966, |
| 127683 | GIR_EraseRootFromParent_Done, |
| 127684 | // Label 6084: @413008 |
| 127685 | GIM_Try, /*On fail goto*//*Label 6085*/ GIMT_Encode4(413137), // Rule ID 10969 // |
| 127686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127687 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127688 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127689 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127690 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127691 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127692 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127693 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127694 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127695 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127696 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127697 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127698 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127699 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127700 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127701 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127702 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127703 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127704 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127705 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127706 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127715 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127717 | GIR_RootConstrainSelectedInstOperands, |
| 127718 | // GIR_Coverage, 10969, |
| 127719 | GIR_EraseRootFromParent_Done, |
| 127720 | // Label 6085: @413137 |
| 127721 | GIM_Try, /*On fail goto*//*Label 6086*/ GIMT_Encode4(413266), // Rule ID 10970 // |
| 127722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127723 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127724 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127725 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127726 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127727 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127728 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127729 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127730 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127731 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127732 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127733 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127734 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127735 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127736 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127737 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127738 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127739 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127740 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127741 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127742 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127753 | GIR_RootConstrainSelectedInstOperands, |
| 127754 | // GIR_Coverage, 10970, |
| 127755 | GIR_EraseRootFromParent_Done, |
| 127756 | // Label 6086: @413266 |
| 127757 | GIM_Try, /*On fail goto*//*Label 6087*/ GIMT_Encode4(413395), // Rule ID 7316 // |
| 127758 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127759 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127760 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127761 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127762 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127763 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127764 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127765 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127766 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127767 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127768 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127769 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127770 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127771 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127772 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127773 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127774 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127775 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127776 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127777 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127778 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127784 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127787 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127788 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127789 | GIR_RootConstrainSelectedInstOperands, |
| 127790 | // GIR_Coverage, 7316, |
| 127791 | GIR_EraseRootFromParent_Done, |
| 127792 | // Label 6087: @413395 |
| 127793 | GIM_Try, /*On fail goto*//*Label 6088*/ GIMT_Encode4(413524), // Rule ID 10951 // |
| 127794 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127795 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127796 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127797 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127798 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127799 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127800 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127801 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127802 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127803 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127804 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127805 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127806 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127807 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127808 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127809 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127810 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127811 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127812 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127813 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127814 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127823 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127825 | GIR_RootConstrainSelectedInstOperands, |
| 127826 | // GIR_Coverage, 10951, |
| 127827 | GIR_EraseRootFromParent_Done, |
| 127828 | // Label 6088: @413524 |
| 127829 | GIM_Try, /*On fail goto*//*Label 6089*/ GIMT_Encode4(413653), // Rule ID 10954 // |
| 127830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127831 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127832 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127833 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127834 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127835 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127836 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127837 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127838 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127839 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127840 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127841 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127842 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127843 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127844 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127845 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127846 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127847 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127848 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127849 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127850 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127852 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127859 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127860 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127861 | GIR_RootConstrainSelectedInstOperands, |
| 127862 | // GIR_Coverage, 10954, |
| 127863 | GIR_EraseRootFromParent_Done, |
| 127864 | // Label 6089: @413653 |
| 127865 | GIM_Try, /*On fail goto*//*Label 6090*/ GIMT_Encode4(413782), // Rule ID 10955 // |
| 127866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127868 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127869 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127870 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127871 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127872 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 127873 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127874 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127875 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 127876 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 127877 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127878 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127879 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127880 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127881 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127882 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127883 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127884 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127885 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127886 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127888 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 127892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 127893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127895 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127896 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127897 | GIR_RootConstrainSelectedInstOperands, |
| 127898 | // GIR_Coverage, 10955, |
| 127899 | GIR_EraseRootFromParent_Done, |
| 127900 | // Label 6090: @413782 |
| 127901 | GIM_Try, /*On fail goto*//*Label 6091*/ GIMT_Encode4(413911), // Rule ID 10937 // |
| 127902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127903 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127904 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127905 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127906 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127907 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127908 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127909 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127910 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127911 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127912 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127913 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127914 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127915 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127916 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127917 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127918 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127919 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127920 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127921 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127922 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127931 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127932 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127933 | GIR_RootConstrainSelectedInstOperands, |
| 127934 | // GIR_Coverage, 10937, |
| 127935 | GIR_EraseRootFromParent_Done, |
| 127936 | // Label 6091: @413911 |
| 127937 | GIM_Try, /*On fail goto*//*Label 6092*/ GIMT_Encode4(414040), // Rule ID 10938 // |
| 127938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127939 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127940 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127941 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127942 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127943 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127944 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127945 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127946 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127947 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127948 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127949 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127950 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127951 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127952 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127953 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127954 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127955 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127956 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127957 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127958 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 127962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 127963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 127964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 127965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 127966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 127967 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 127969 | GIR_RootConstrainSelectedInstOperands, |
| 127970 | // GIR_Coverage, 10938, |
| 127971 | GIR_EraseRootFromParent_Done, |
| 127972 | // Label 6092: @414040 |
| 127973 | GIM_Try, /*On fail goto*//*Label 6093*/ GIMT_Encode4(414169), // Rule ID 10941 // |
| 127974 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 127975 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 127976 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127977 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 127978 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 127979 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 127980 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 127981 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 127982 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 127983 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 127984 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 127985 | // MIs[3] VOP3Mods:src0:src0_mods |
| 127986 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 127987 | // MIs[3] VOP3Mods:src1:src1_mods |
| 127988 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 127989 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 127990 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 127991 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 127992 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 127993 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 127994 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 127995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 127996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 127997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 127998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 127999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128005 | GIR_RootConstrainSelectedInstOperands, |
| 128006 | // GIR_Coverage, 10941, |
| 128007 | GIR_EraseRootFromParent_Done, |
| 128008 | // Label 6093: @414169 |
| 128009 | GIM_Try, /*On fail goto*//*Label 6094*/ GIMT_Encode4(414298), // Rule ID 10942 // |
| 128010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128011 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128012 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128013 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128014 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128015 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128016 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128017 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128018 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128019 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 128020 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128021 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128022 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128023 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128024 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128025 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128026 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128027 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128028 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128029 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128030 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128031 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128032 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128039 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128040 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128041 | GIR_RootConstrainSelectedInstOperands, |
| 128042 | // GIR_Coverage, 10942, |
| 128043 | GIR_EraseRootFromParent_Done, |
| 128044 | // Label 6094: @414298 |
| 128045 | GIM_Try, /*On fail goto*//*Label 6095*/ GIMT_Encode4(414427), // Rule ID 10922 // |
| 128046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128047 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128048 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128049 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128050 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128051 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128052 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128053 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128054 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128055 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 128056 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128057 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128058 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128059 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128060 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128061 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128062 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128063 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128064 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128065 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128066 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128077 | GIR_RootConstrainSelectedInstOperands, |
| 128078 | // GIR_Coverage, 10922, |
| 128079 | GIR_EraseRootFromParent_Done, |
| 128080 | // Label 6095: @414427 |
| 128081 | GIM_Try, /*On fail goto*//*Label 6096*/ GIMT_Encode4(414556), // Rule ID 10923 // |
| 128082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128083 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128084 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128085 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128086 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128087 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128088 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128089 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128090 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128091 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 128092 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128093 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128094 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128095 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128096 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128097 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128098 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128099 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128100 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128101 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128102 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128113 | GIR_RootConstrainSelectedInstOperands, |
| 128114 | // GIR_Coverage, 10923, |
| 128115 | GIR_EraseRootFromParent_Done, |
| 128116 | // Label 6096: @414556 |
| 128117 | GIM_Try, /*On fail goto*//*Label 6097*/ GIMT_Encode4(414685), // Rule ID 10926 // |
| 128118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128119 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128120 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128121 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128122 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128123 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128124 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128125 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128126 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128127 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 128128 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128129 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128130 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128131 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128132 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128133 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128134 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128135 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128136 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128137 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128138 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128149 | GIR_RootConstrainSelectedInstOperands, |
| 128150 | // GIR_Coverage, 10926, |
| 128151 | GIR_EraseRootFromParent_Done, |
| 128152 | // Label 6097: @414685 |
| 128153 | GIM_Try, /*On fail goto*//*Label 6098*/ GIMT_Encode4(414814), // Rule ID 10927 // |
| 128154 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128155 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128156 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128157 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128158 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128159 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128160 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128161 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128162 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128163 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 128164 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128165 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128166 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128167 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128168 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128169 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128170 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128171 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128172 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128173 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128174 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128182 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128184 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128185 | GIR_RootConstrainSelectedInstOperands, |
| 128186 | // GIR_Coverage, 10927, |
| 128187 | GIR_EraseRootFromParent_Done, |
| 128188 | // Label 6098: @414814 |
| 128189 | GIM_Try, /*On fail goto*//*Label 6099*/ GIMT_Encode4(414943), // Rule ID 7315 // |
| 128190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128191 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128192 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128193 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128194 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128195 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128196 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128197 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128198 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128199 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128200 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128201 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128202 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128203 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128204 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128205 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128206 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128207 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128208 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128209 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128210 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128219 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128220 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128221 | GIR_RootConstrainSelectedInstOperands, |
| 128222 | // GIR_Coverage, 7315, |
| 128223 | GIR_EraseRootFromParent_Done, |
| 128224 | // Label 6099: @414943 |
| 128225 | GIM_Try, /*On fail goto*//*Label 6100*/ GIMT_Encode4(415072), // Rule ID 10936 // |
| 128226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128227 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128228 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128229 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128230 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128231 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128232 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128233 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128234 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128235 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128236 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128237 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128238 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128239 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128240 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128241 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128242 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128243 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128244 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128245 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128246 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128250 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128255 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128256 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128257 | GIR_RootConstrainSelectedInstOperands, |
| 128258 | // GIR_Coverage, 10936, |
| 128259 | GIR_EraseRootFromParent_Done, |
| 128260 | // Label 6100: @415072 |
| 128261 | GIM_Try, /*On fail goto*//*Label 6101*/ GIMT_Encode4(415201), // Rule ID 10939 // |
| 128262 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128263 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128264 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128265 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128266 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128267 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128268 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128269 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128270 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128271 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128272 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128273 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128274 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128275 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128276 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128277 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128278 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128279 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128280 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128281 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128282 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128284 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128292 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128293 | GIR_RootConstrainSelectedInstOperands, |
| 128294 | // GIR_Coverage, 10939, |
| 128295 | GIR_EraseRootFromParent_Done, |
| 128296 | // Label 6101: @415201 |
| 128297 | GIM_Try, /*On fail goto*//*Label 6102*/ GIMT_Encode4(415330), // Rule ID 10940 // |
| 128298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128299 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128300 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128301 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128302 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128303 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128304 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128305 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128306 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128307 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128308 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128309 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128310 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128311 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128312 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128314 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128315 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128316 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128317 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128318 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128327 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128328 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128329 | GIR_RootConstrainSelectedInstOperands, |
| 128330 | // GIR_Coverage, 10940, |
| 128331 | GIR_EraseRootFromParent_Done, |
| 128332 | // Label 6102: @415330 |
| 128333 | GIM_Try, /*On fail goto*//*Label 6103*/ GIMT_Encode4(415459), // Rule ID 7314 // |
| 128334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128335 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128336 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128337 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128338 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128339 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128340 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128341 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128342 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128343 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128344 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128345 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128346 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128347 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128348 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128349 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128350 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128351 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128352 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128353 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128354 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128365 | GIR_RootConstrainSelectedInstOperands, |
| 128366 | // GIR_Coverage, 7314, |
| 128367 | GIR_EraseRootFromParent_Done, |
| 128368 | // Label 6103: @415459 |
| 128369 | GIM_Try, /*On fail goto*//*Label 6104*/ GIMT_Encode4(415588), // Rule ID 10921 // |
| 128370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128371 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128372 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128373 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128374 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128375 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128376 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128377 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128378 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128379 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128380 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128381 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128382 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128383 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128384 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128385 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128386 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128387 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128388 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128389 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128390 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 128394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 128395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128401 | GIR_RootConstrainSelectedInstOperands, |
| 128402 | // GIR_Coverage, 10921, |
| 128403 | GIR_EraseRootFromParent_Done, |
| 128404 | // Label 6104: @415588 |
| 128405 | GIM_Try, /*On fail goto*//*Label 6105*/ GIMT_Encode4(415717), // Rule ID 10924 // |
| 128406 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128407 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128408 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128409 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128410 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128411 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128412 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128413 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128414 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128415 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128416 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128417 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128418 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128419 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128420 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128421 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128422 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128423 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128424 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128425 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128426 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128437 | GIR_RootConstrainSelectedInstOperands, |
| 128438 | // GIR_Coverage, 10924, |
| 128439 | GIR_EraseRootFromParent_Done, |
| 128440 | // Label 6105: @415717 |
| 128441 | GIM_Try, /*On fail goto*//*Label 6106*/ GIMT_Encode4(415846), // Rule ID 10925 // |
| 128442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128443 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128444 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128445 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128446 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128447 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 128448 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128449 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128450 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128451 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 128452 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128453 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128454 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 128455 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128456 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 128457 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128458 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128459 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128460 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128461 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128462 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 128468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 128469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 128470 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 128471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128473 | GIR_RootConstrainSelectedInstOperands, |
| 128474 | // GIR_Coverage, 10925, |
| 128475 | GIR_EraseRootFromParent_Done, |
| 128476 | // Label 6106: @415846 |
| 128477 | GIM_Try, /*On fail goto*//*Label 6107*/ GIMT_Encode4(415975), // Rule ID 11007 // |
| 128478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128479 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128480 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128481 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128482 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128483 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128484 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128485 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128486 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128487 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128488 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128489 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128490 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128491 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128492 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128493 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128494 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128495 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128496 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128497 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128498 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128502 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128507 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128508 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128509 | GIR_RootConstrainSelectedInstOperands, |
| 128510 | // GIR_Coverage, 11007, |
| 128511 | GIR_EraseRootFromParent_Done, |
| 128512 | // Label 6107: @415975 |
| 128513 | GIM_Try, /*On fail goto*//*Label 6108*/ GIMT_Encode4(416104), // Rule ID 11008 // |
| 128514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128515 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128516 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128517 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128518 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128519 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128520 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128521 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128522 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128523 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128524 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128525 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128526 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128527 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128528 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128529 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128530 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128531 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128532 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128533 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128534 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128543 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128545 | GIR_RootConstrainSelectedInstOperands, |
| 128546 | // GIR_Coverage, 11008, |
| 128547 | GIR_EraseRootFromParent_Done, |
| 128548 | // Label 6108: @416104 |
| 128549 | GIM_Try, /*On fail goto*//*Label 6109*/ GIMT_Encode4(416233), // Rule ID 11009 // |
| 128550 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128551 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128552 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128553 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128554 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128555 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128556 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128557 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128558 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128559 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128560 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128561 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128562 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128563 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128564 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128565 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128566 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128567 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128568 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128569 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128570 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128571 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128572 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128579 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128581 | GIR_RootConstrainSelectedInstOperands, |
| 128582 | // GIR_Coverage, 11009, |
| 128583 | GIR_EraseRootFromParent_Done, |
| 128584 | // Label 6109: @416233 |
| 128585 | GIM_Try, /*On fail goto*//*Label 6110*/ GIMT_Encode4(416362), // Rule ID 11010 // |
| 128586 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128587 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128588 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128589 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128590 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128591 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128592 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128593 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128594 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128595 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128596 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128597 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128598 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128599 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128600 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128601 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128602 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128603 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128604 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128605 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128606 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128609 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128612 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128615 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128616 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128617 | GIR_RootConstrainSelectedInstOperands, |
| 128618 | // GIR_Coverage, 11010, |
| 128619 | GIR_EraseRootFromParent_Done, |
| 128620 | // Label 6110: @416362 |
| 128621 | GIM_Try, /*On fail goto*//*Label 6111*/ GIMT_Encode4(416491), // Rule ID 10947 // |
| 128622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128626 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128627 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128628 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128629 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128630 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128631 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128632 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128633 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128634 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128635 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128636 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128637 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128638 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128639 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128640 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128641 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128642 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128651 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128652 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128653 | GIR_RootConstrainSelectedInstOperands, |
| 128654 | // GIR_Coverage, 10947, |
| 128655 | GIR_EraseRootFromParent_Done, |
| 128656 | // Label 6111: @416491 |
| 128657 | GIM_Try, /*On fail goto*//*Label 6112*/ GIMT_Encode4(416620), // Rule ID 10948 // |
| 128658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128659 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128660 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128661 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128662 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128663 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128664 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128665 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128666 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128667 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128668 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128669 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128670 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128671 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128672 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128673 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128674 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128675 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128676 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128677 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128678 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128679 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128680 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128687 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128688 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128689 | GIR_RootConstrainSelectedInstOperands, |
| 128690 | // GIR_Coverage, 10948, |
| 128691 | GIR_EraseRootFromParent_Done, |
| 128692 | // Label 6112: @416620 |
| 128693 | GIM_Try, /*On fail goto*//*Label 6113*/ GIMT_Encode4(416749), // Rule ID 10949 // |
| 128694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128695 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128696 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128697 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128698 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128699 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128700 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128701 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128702 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128703 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128704 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128705 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128706 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128707 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128708 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128709 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128710 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128711 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128712 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128713 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128714 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128725 | GIR_RootConstrainSelectedInstOperands, |
| 128726 | // GIR_Coverage, 10949, |
| 128727 | GIR_EraseRootFromParent_Done, |
| 128728 | // Label 6113: @416749 |
| 128729 | GIM_Try, /*On fail goto*//*Label 6114*/ GIMT_Encode4(416878), // Rule ID 10950 // |
| 128730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128731 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128732 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128733 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128734 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128735 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128736 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 128737 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128738 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128739 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128740 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128741 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128742 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128743 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128744 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128745 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128746 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128747 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128748 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128749 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128750 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128759 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128760 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128761 | GIR_RootConstrainSelectedInstOperands, |
| 128762 | // GIR_Coverage, 10950, |
| 128763 | GIR_EraseRootFromParent_Done, |
| 128764 | // Label 6114: @416878 |
| 128765 | GIM_Try, /*On fail goto*//*Label 6115*/ GIMT_Encode4(417007), // Rule ID 10992 // |
| 128766 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128767 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128768 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128769 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128770 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128771 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128772 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128773 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128774 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128775 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128776 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128777 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128778 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128779 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128780 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128781 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128782 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128783 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128784 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128785 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128786 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128792 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128795 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128796 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128797 | GIR_RootConstrainSelectedInstOperands, |
| 128798 | // GIR_Coverage, 10992, |
| 128799 | GIR_EraseRootFromParent_Done, |
| 128800 | // Label 6115: @417007 |
| 128801 | GIM_Try, /*On fail goto*//*Label 6116*/ GIMT_Encode4(417136), // Rule ID 10993 // |
| 128802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128803 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128804 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128805 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128806 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128807 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128808 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128809 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128810 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128811 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128812 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128813 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128814 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128815 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128816 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128817 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128818 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128819 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128820 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128821 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128822 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128824 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128828 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128831 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128832 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128833 | GIR_RootConstrainSelectedInstOperands, |
| 128834 | // GIR_Coverage, 10993, |
| 128835 | GIR_EraseRootFromParent_Done, |
| 128836 | // Label 6116: @417136 |
| 128837 | GIM_Try, /*On fail goto*//*Label 6117*/ GIMT_Encode4(417265), // Rule ID 10994 // |
| 128838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128839 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128840 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128841 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128842 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128843 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128844 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128845 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128846 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128847 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128848 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128849 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128850 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128851 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128852 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128853 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128854 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128855 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128856 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128857 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128858 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128869 | GIR_RootConstrainSelectedInstOperands, |
| 128870 | // GIR_Coverage, 10994, |
| 128871 | GIR_EraseRootFromParent_Done, |
| 128872 | // Label 6117: @417265 |
| 128873 | GIM_Try, /*On fail goto*//*Label 6118*/ GIMT_Encode4(417394), // Rule ID 10995 // |
| 128874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128875 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128876 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128877 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128878 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128879 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128880 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128881 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128882 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128883 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128884 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 128885 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128886 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128887 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128888 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128889 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128890 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128891 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128892 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128893 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128894 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128895 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128896 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 128898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 128899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 128900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 128901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128903 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128904 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128905 | GIR_RootConstrainSelectedInstOperands, |
| 128906 | // GIR_Coverage, 10995, |
| 128907 | GIR_EraseRootFromParent_Done, |
| 128908 | // Label 6118: @417394 |
| 128909 | GIM_Try, /*On fail goto*//*Label 6119*/ GIMT_Encode4(417523), // Rule ID 10932 // |
| 128910 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128911 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128912 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128913 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128914 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128915 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128916 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128917 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128918 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128919 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128920 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128921 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128922 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128923 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128924 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128925 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128926 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128927 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128928 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128929 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128930 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128932 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128941 | GIR_RootConstrainSelectedInstOperands, |
| 128942 | // GIR_Coverage, 10932, |
| 128943 | GIR_EraseRootFromParent_Done, |
| 128944 | // Label 6119: @417523 |
| 128945 | GIM_Try, /*On fail goto*//*Label 6120*/ GIMT_Encode4(417652), // Rule ID 10933 // |
| 128946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128949 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128950 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128951 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128952 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128953 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128954 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128955 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128956 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128957 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128958 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128959 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128960 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128961 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128962 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128963 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 128964 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 128965 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 128966 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 128967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 128968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 128969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 128970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 128971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 128972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 128973 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 128974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 128975 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128976 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 128977 | GIR_RootConstrainSelectedInstOperands, |
| 128978 | // GIR_Coverage, 10933, |
| 128979 | GIR_EraseRootFromParent_Done, |
| 128980 | // Label 6120: @417652 |
| 128981 | GIM_Try, /*On fail goto*//*Label 6121*/ GIMT_Encode4(417781), // Rule ID 10934 // |
| 128982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 128983 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 128984 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128985 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 128986 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 128987 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 128988 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 128989 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 128990 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 128991 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 128992 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 128993 | // MIs[3] VOP3Mods:src0:src0_mods |
| 128994 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 128995 | // MIs[3] VOP3Mods:src1:src1_mods |
| 128996 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 128997 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 128998 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 128999 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129000 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129001 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129002 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 129006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 129007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129008 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129009 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129011 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129012 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129013 | GIR_RootConstrainSelectedInstOperands, |
| 129014 | // GIR_Coverage, 10934, |
| 129015 | GIR_EraseRootFromParent_Done, |
| 129016 | // Label 6121: @417781 |
| 129017 | GIM_Try, /*On fail goto*//*Label 6122*/ GIMT_Encode4(417910), // Rule ID 10935 // |
| 129018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129019 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129020 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129021 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129022 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129023 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 129024 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129025 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129026 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129027 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129028 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129029 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129030 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129031 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129032 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129033 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129034 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129035 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129036 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129037 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129038 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods))), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src0_mods |
| 129042 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src0 |
| 129043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129049 | GIR_RootConstrainSelectedInstOperands, |
| 129050 | // GIR_Coverage, 10935, |
| 129051 | GIR_EraseRootFromParent_Done, |
| 129052 | // Label 6122: @417910 |
| 129053 | GIM_Try, /*On fail goto*//*Label 6123*/ GIMT_Encode4(418039), // Rule ID 11003 // |
| 129054 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129055 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129056 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129057 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129058 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129059 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129060 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129061 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129062 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129063 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129064 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129065 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129066 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129067 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129068 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129069 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129070 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129071 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129072 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129073 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129074 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129085 | GIR_RootConstrainSelectedInstOperands, |
| 129086 | // GIR_Coverage, 11003, |
| 129087 | GIR_EraseRootFromParent_Done, |
| 129088 | // Label 6123: @418039 |
| 129089 | GIM_Try, /*On fail goto*//*Label 6124*/ GIMT_Encode4(418168), // Rule ID 11004 // |
| 129090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129091 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129092 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129093 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129094 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129095 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129096 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129097 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129098 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129099 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129100 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129101 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129102 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129103 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129104 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129105 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129106 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129107 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129108 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129109 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129110 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129114 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129116 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129120 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129121 | GIR_RootConstrainSelectedInstOperands, |
| 129122 | // GIR_Coverage, 11004, |
| 129123 | GIR_EraseRootFromParent_Done, |
| 129124 | // Label 6124: @418168 |
| 129125 | GIM_Try, /*On fail goto*//*Label 6125*/ GIMT_Encode4(418297), // Rule ID 11005 // |
| 129126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129127 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129128 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129129 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129130 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129131 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129132 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129133 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129134 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129135 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129136 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129137 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129138 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129139 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129140 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129141 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129142 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129143 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129144 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129145 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129146 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129157 | GIR_RootConstrainSelectedInstOperands, |
| 129158 | // GIR_Coverage, 11005, |
| 129159 | GIR_EraseRootFromParent_Done, |
| 129160 | // Label 6125: @418297 |
| 129161 | GIM_Try, /*On fail goto*//*Label 6126*/ GIMT_Encode4(418426), // Rule ID 11006 // |
| 129162 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129163 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129164 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129165 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129166 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129167 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129168 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129169 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129170 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129171 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129172 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129173 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129174 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129175 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129176 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129177 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129178 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129179 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129180 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129181 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129182 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129191 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129192 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129193 | GIR_RootConstrainSelectedInstOperands, |
| 129194 | // GIR_Coverage, 11006, |
| 129195 | GIR_EraseRootFromParent_Done, |
| 129196 | // Label 6126: @418426 |
| 129197 | GIM_Try, /*On fail goto*//*Label 6127*/ GIMT_Encode4(418555), // Rule ID 10943 // |
| 129198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129199 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129200 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129201 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129202 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129203 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129204 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129205 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129206 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129207 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129208 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129209 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129210 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129211 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129212 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129213 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129214 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129215 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129216 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129217 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129218 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129220 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129227 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129228 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129229 | GIR_RootConstrainSelectedInstOperands, |
| 129230 | // GIR_Coverage, 10943, |
| 129231 | GIR_EraseRootFromParent_Done, |
| 129232 | // Label 6127: @418555 |
| 129233 | GIM_Try, /*On fail goto*//*Label 6128*/ GIMT_Encode4(418684), // Rule ID 10944 // |
| 129234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129235 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129236 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129237 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129238 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129239 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129240 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129241 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129242 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129243 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129244 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129245 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129246 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129247 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129248 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129249 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129250 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129251 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129252 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129253 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129254 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129256 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129264 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129265 | GIR_RootConstrainSelectedInstOperands, |
| 129266 | // GIR_Coverage, 10944, |
| 129267 | GIR_EraseRootFromParent_Done, |
| 129268 | // Label 6128: @418684 |
| 129269 | GIM_Try, /*On fail goto*//*Label 6129*/ GIMT_Encode4(418813), // Rule ID 10945 // |
| 129270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129271 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129272 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129273 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129274 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129275 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129276 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129277 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129278 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129279 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129280 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129281 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129282 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129283 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129284 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129285 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129286 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129287 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129288 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129289 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129290 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129299 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129301 | GIR_RootConstrainSelectedInstOperands, |
| 129302 | // GIR_Coverage, 10945, |
| 129303 | GIR_EraseRootFromParent_Done, |
| 129304 | // Label 6129: @418813 |
| 129305 | GIM_Try, /*On fail goto*//*Label 6130*/ GIMT_Encode4(418942), // Rule ID 10946 // |
| 129306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129307 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129308 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129309 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129310 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129311 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129312 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM), |
| 129313 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129314 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129315 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129316 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129317 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129318 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129319 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129320 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129321 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129322 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129323 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129324 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129325 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129326 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129337 | GIR_RootConstrainSelectedInstOperands, |
| 129338 | // GIR_Coverage, 10946, |
| 129339 | GIR_EraseRootFromParent_Done, |
| 129340 | // Label 6130: @418942 |
| 129341 | GIM_Try, /*On fail goto*//*Label 6131*/ GIMT_Encode4(419071), // Rule ID 10988 // |
| 129342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129343 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129344 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129345 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129346 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129347 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129348 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129349 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129350 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129351 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129352 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129353 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129354 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129355 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129356 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129357 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129358 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129359 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129360 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129361 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129362 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129373 | GIR_RootConstrainSelectedInstOperands, |
| 129374 | // GIR_Coverage, 10988, |
| 129375 | GIR_EraseRootFromParent_Done, |
| 129376 | // Label 6131: @419071 |
| 129377 | GIM_Try, /*On fail goto*//*Label 6132*/ GIMT_Encode4(419200), // Rule ID 10989 // |
| 129378 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129379 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129380 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129381 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129382 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129383 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129384 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129385 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129386 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129387 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129388 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129389 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129390 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129391 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129392 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129393 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129394 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129395 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129396 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129397 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129398 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129409 | GIR_RootConstrainSelectedInstOperands, |
| 129410 | // GIR_Coverage, 10989, |
| 129411 | GIR_EraseRootFromParent_Done, |
| 129412 | // Label 6132: @419200 |
| 129413 | GIM_Try, /*On fail goto*//*Label 6133*/ GIMT_Encode4(419329), // Rule ID 10990 // |
| 129414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129416 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129417 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129418 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129419 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129420 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129421 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129422 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129423 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129424 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129425 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129427 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129428 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129429 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129430 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129431 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129432 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129433 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129434 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129435 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129436 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129443 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129444 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129445 | GIR_RootConstrainSelectedInstOperands, |
| 129446 | // GIR_Coverage, 10990, |
| 129447 | GIR_EraseRootFromParent_Done, |
| 129448 | // Label 6133: @419329 |
| 129449 | GIM_Try, /*On fail goto*//*Label 6134*/ GIMT_Encode4(419458), // Rule ID 10991 // |
| 129450 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129451 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129452 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129453 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129454 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129455 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129456 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129457 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129458 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129459 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129460 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129461 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129462 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129463 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129464 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129465 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129466 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129467 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129468 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129469 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129470 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129479 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129480 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129481 | GIR_RootConstrainSelectedInstOperands, |
| 129482 | // GIR_Coverage, 10991, |
| 129483 | GIR_EraseRootFromParent_Done, |
| 129484 | // Label 6134: @419458 |
| 129485 | GIM_Try, /*On fail goto*//*Label 6135*/ GIMT_Encode4(419587), // Rule ID 10928 // |
| 129486 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129487 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129488 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129489 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129490 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129491 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129492 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129493 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129494 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129495 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129496 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129497 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129498 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129499 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129500 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129501 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129502 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129503 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129504 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129505 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129506 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129517 | GIR_RootConstrainSelectedInstOperands, |
| 129518 | // GIR_Coverage, 10928, |
| 129519 | GIR_EraseRootFromParent_Done, |
| 129520 | // Label 6135: @419587 |
| 129521 | GIM_Try, /*On fail goto*//*Label 6136*/ GIMT_Encode4(419716), // Rule ID 10929 // |
| 129522 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129523 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129524 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129525 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129526 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129527 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129528 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129529 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129530 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129531 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129532 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129533 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129534 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129535 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129536 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129537 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129538 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129539 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129540 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129541 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129542 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129551 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129552 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129553 | GIR_RootConstrainSelectedInstOperands, |
| 129554 | // GIR_Coverage, 10929, |
| 129555 | GIR_EraseRootFromParent_Done, |
| 129556 | // Label 6136: @419716 |
| 129557 | GIM_Try, /*On fail goto*//*Label 6137*/ GIMT_Encode4(419845), // Rule ID 10930 // |
| 129558 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129559 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129560 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129561 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129562 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129563 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129564 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129565 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129566 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129567 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129568 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129569 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129570 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129571 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129572 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129573 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129574 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129575 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129576 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129577 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129578 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129579 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129580 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129581 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129583 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129584 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129585 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129587 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129588 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129589 | GIR_RootConstrainSelectedInstOperands, |
| 129590 | // GIR_Coverage, 10930, |
| 129591 | GIR_EraseRootFromParent_Done, |
| 129592 | // Label 6137: @419845 |
| 129593 | GIM_Try, /*On fail goto*//*Label 6138*/ GIMT_Encode4(419974), // Rule ID 10931 // |
| 129594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129596 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129597 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129598 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129599 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129600 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXNUM_IEEE), |
| 129601 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129602 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129603 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 129604 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129605 | // MIs[3] VOP3Mods:src1:src1_mods |
| 129606 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 129607 | // MIs[3] VOP3Mods:src0:src0_mods |
| 129608 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 129609 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_fmaxnum_like_nnan), |
| 129610 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 129611 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129612 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129613 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129614 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods)))<<P:Predicate_fmaxnum_like_nnan>> => (V_MED3_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 129616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_mods |
| 129620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129623 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129625 | GIR_RootConstrainSelectedInstOperands, |
| 129626 | // GIR_Coverage, 10931, |
| 129627 | GIR_EraseRootFromParent_Done, |
| 129628 | // Label 6138: @419974 |
| 129629 | GIM_Try, /*On fail goto*//*Label 6139*/ GIMT_Encode4(420086), // Rule ID 11932 // |
| 129630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129632 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 129633 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 129634 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129635 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129636 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129637 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129638 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129639 | GIM_CheckHasOneUse, /*MI*/2, |
| 129640 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 129641 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 129642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129643 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129644 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129645 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129646 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129647 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 129651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 129652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129655 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129656 | GIR_RootConstrainSelectedInstOperands, |
| 129657 | // GIR_Coverage, 11932, |
| 129658 | GIR_EraseRootFromParent_Done, |
| 129659 | // Label 6139: @420086 |
| 129660 | GIM_Try, /*On fail goto*//*Label 6140*/ GIMT_Encode4(420198), // Rule ID 11931 // |
| 129661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129662 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129663 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 129664 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 129665 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129666 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129667 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129668 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129669 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129670 | GIM_CheckHasOneUse, /*MI*/2, |
| 129671 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 129672 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 129673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129674 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129675 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129676 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 129682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 129683 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129685 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129687 | GIR_RootConstrainSelectedInstOperands, |
| 129688 | // GIR_Coverage, 11931, |
| 129689 | GIR_EraseRootFromParent_Done, |
| 129690 | // Label 6140: @420198 |
| 129691 | GIM_Try, /*On fail goto*//*Label 6141*/ GIMT_Encode4(420310), // Rule ID 7401 // |
| 129692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129694 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129695 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 129696 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129700 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129701 | GIM_CheckHasOneUse, /*MI*/2, |
| 129702 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 129703 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 129704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129705 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129706 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129707 | // (fmaxnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129716 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129717 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129718 | GIR_RootConstrainSelectedInstOperands, |
| 129719 | // GIR_Coverage, 7401, |
| 129720 | GIR_EraseRootFromParent_Done, |
| 129721 | // Label 6141: @420310 |
| 129722 | GIM_Try, /*On fail goto*//*Label 6142*/ GIMT_Encode4(420422), // Rule ID 7400 // |
| 129723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129725 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129726 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 129727 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129728 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 129729 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129730 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 129731 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 129732 | GIM_CheckHasOneUse, /*MI*/2, |
| 129733 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 129734 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 129735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129736 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129737 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129738 | // (fmaxnum_ieee:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129747 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129748 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129749 | GIR_RootConstrainSelectedInstOperands, |
| 129750 | // GIR_Coverage, 7400, |
| 129751 | GIR_EraseRootFromParent_Done, |
| 129752 | // Label 6142: @420422 |
| 129753 | GIM_Try, /*On fail goto*//*Label 6143*/ GIMT_Encode4(420518), // Rule ID 11916 // |
| 129754 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129755 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129756 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 129757 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129758 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129759 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129760 | GIM_CheckHasOneUse, /*MI*/1, |
| 129761 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 129762 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129763 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129764 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129765 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 129771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 129772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129774 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129775 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129776 | GIR_RootConstrainSelectedInstOperands, |
| 129777 | // GIR_Coverage, 11916, |
| 129778 | GIR_EraseRootFromParent_Done, |
| 129779 | // Label 6143: @420518 |
| 129780 | GIM_Try, /*On fail goto*//*Label 6144*/ GIMT_Encode4(420614), // Rule ID 11915 // |
| 129781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129783 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 129784 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129785 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129786 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129787 | GIM_CheckHasOneUse, /*MI*/1, |
| 129788 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 129789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129790 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129791 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129792 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 129796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 129798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 129799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 129800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 129801 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129802 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129803 | GIR_RootConstrainSelectedInstOperands, |
| 129804 | // GIR_Coverage, 11915, |
| 129805 | GIR_EraseRootFromParent_Done, |
| 129806 | // Label 6144: @420614 |
| 129807 | GIM_Try, /*On fail goto*//*Label 6145*/ GIMT_Encode4(420710), // Rule ID 7385 // |
| 129808 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129809 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129810 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129811 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM), |
| 129812 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129813 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129814 | GIM_CheckHasOneUse, /*MI*/1, |
| 129815 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 129816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129817 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129818 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129819 | // (fmaxnum_ieee:{ *:[f32] } (fminnum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129828 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129829 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129830 | GIR_RootConstrainSelectedInstOperands, |
| 129831 | // GIR_Coverage, 7385, |
| 129832 | GIR_EraseRootFromParent_Done, |
| 129833 | // Label 6145: @420710 |
| 129834 | GIM_Try, /*On fail goto*//*Label 6146*/ GIMT_Encode4(420806), // Rule ID 7384 // |
| 129835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 129836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129837 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 129838 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINNUM_IEEE), |
| 129839 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 129840 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 129841 | GIM_CheckHasOneUse, /*MI*/1, |
| 129842 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 129843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 129844 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129845 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129846 | // (fmaxnum_ieee:{ *:[f32] } (fminnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminnum_ieee_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods)) => (V_MINMAX_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 129847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_F32_e64), |
| 129848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 129850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 129852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 129854 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 129855 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129856 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 129857 | GIR_RootConstrainSelectedInstOperands, |
| 129858 | // GIR_Coverage, 7384, |
| 129859 | GIR_EraseRootFromParent_Done, |
| 129860 | // Label 6146: @420806 |
| 129861 | GIM_Try, /*On fail goto*//*Label 6147*/ GIMT_Encode4(420841), // Rule ID 94 // |
| 129862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 129863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 129864 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 129865 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 129866 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18520), |
| 129867 | // (fmaxnum_ieee:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18520>> => (S_MAX_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 129868 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_F32), |
| 129869 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 129870 | GIR_RootConstrainSelectedInstOperands, |
| 129871 | // GIR_Coverage, 94, |
| 129872 | GIR_Done, |
| 129873 | // Label 6147: @420841 |
| 129874 | GIM_Try, /*On fail goto*//*Label 6148*/ GIMT_Encode4(420901), // Rule ID 739 // |
| 129875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129876 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129878 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 129880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 129882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 129884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 129886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 129887 | GIR_RootConstrainSelectedInstOperands, |
| 129888 | // GIR_Coverage, 739, |
| 129889 | GIR_EraseRootFromParent_Done, |
| 129890 | // Label 6148: @420901 |
| 129891 | GIM_Try, /*On fail goto*//*Label 6149*/ GIMT_Encode4(420961), // Rule ID 8059 // |
| 129892 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129894 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129895 | // (fmaxnum_ieee:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 129897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 129899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129900 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 129901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129902 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 129903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 129904 | GIR_RootConstrainSelectedInstOperands, |
| 129905 | // GIR_Coverage, 8059, |
| 129906 | GIR_EraseRootFromParent_Done, |
| 129907 | // Label 6149: @420961 |
| 129908 | GIM_Reject, |
| 129909 | // Label 6010: @420962 |
| 129910 | GIM_Reject, |
| 129911 | // Label 5864: @420963 |
| 129912 | GIM_Try, /*On fail goto*//*Label 6150*/ GIMT_Encode4(421215), |
| 129913 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 129914 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 129915 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 129916 | GIM_Try, /*On fail goto*//*Label 6151*/ GIMT_Encode4(421037), // Rule ID 840 // |
| 129917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 129918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129920 | // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 129922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 129924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 129926 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129927 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 129928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 129929 | GIR_RootConstrainSelectedInstOperands, |
| 129930 | // GIR_Coverage, 840, |
| 129931 | GIR_EraseRootFromParent_Done, |
| 129932 | // Label 6151: @421037 |
| 129933 | GIM_Try, /*On fail goto*//*Label 6152*/ GIMT_Encode4(421096), // Rule ID 859 // |
| 129934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 129935 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 129937 | // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 129939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 129941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 129943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 129944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 129945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 129946 | GIR_RootConstrainSelectedInstOperands, |
| 129947 | // GIR_Coverage, 859, |
| 129948 | GIR_EraseRootFromParent_Done, |
| 129949 | // Label 6152: @421096 |
| 129950 | GIM_Try, /*On fail goto*//*Label 6153*/ GIMT_Encode4(421155), // Rule ID 8085 // |
| 129951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 129952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129954 | // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 129956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 129958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 129960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 129962 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 129963 | GIR_RootConstrainSelectedInstOperands, |
| 129964 | // GIR_Coverage, 8085, |
| 129965 | GIR_EraseRootFromParent_Done, |
| 129966 | // Label 6153: @421155 |
| 129967 | GIM_Try, /*On fail goto*//*Label 6154*/ GIMT_Encode4(421214), // Rule ID 8099 // |
| 129968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 129969 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 129970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 129971 | // (fmaxnum_ieee:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 129972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 129973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129974 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 129975 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 129976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 129977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 129978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 129979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 129980 | GIR_RootConstrainSelectedInstOperands, |
| 129981 | // GIR_Coverage, 8099, |
| 129982 | GIR_EraseRootFromParent_Done, |
| 129983 | // Label 6154: @421214 |
| 129984 | GIM_Reject, |
| 129985 | // Label 6150: @421215 |
| 129986 | GIM_Reject, |
| 129987 | // Label 5865: @421216 |
| 129988 | GIM_Try, /*On fail goto*//*Label 6155*/ GIMT_Encode4(421287), // Rule ID 961 // |
| 129989 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 129990 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 129991 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 129992 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 129993 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 129994 | // (fmaxnum_ieee:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MAX_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 129995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16), |
| 129996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 129997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 129998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 129999 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130000 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130001 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130002 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130003 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130004 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130005 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130006 | GIR_RootConstrainSelectedInstOperands, |
| 130007 | // GIR_Coverage, 961, |
| 130008 | GIR_EraseRootFromParent_Done, |
| 130009 | // Label 6155: @421287 |
| 130010 | GIM_Reject, |
| 130011 | // Label 5866: @421288 |
| 130012 | GIM_Reject, |
| 130013 | // Label 84: @421289 |
| 130014 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6160*/ GIMT_Encode4(422758), |
| 130015 | /*GILLT_s16*//*Label 6156*/ GIMT_Encode4(421316), |
| 130016 | /*GILLT_s32*//*Label 6157*/ GIMT_Encode4(421938), |
| 130017 | /*GILLT_s64*//*Label 6158*/ GIMT_Encode4(422548), |
| 130018 | /*GILLT_v2s16*//*Label 6159*/ GIMT_Encode4(422683), |
| 130019 | // Label 6156: @421316 |
| 130020 | GIM_Try, /*On fail goto*//*Label 6161*/ GIMT_Encode4(421937), |
| 130021 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 130022 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 130023 | GIM_Try, /*On fail goto*//*Label 6162*/ GIMT_Encode4(421446), // Rule ID 11984 // |
| 130024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130026 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130027 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130028 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130029 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130030 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130031 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 130032 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 130033 | GIM_CheckHasOneUse, /*MI*/2, |
| 130034 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130035 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130036 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130037 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130038 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130039 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130040 | // (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_36291>>)<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64), |
| 130042 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130052 | GIR_RootConstrainSelectedInstOperands, |
| 130053 | // GIR_Coverage, 11984, |
| 130054 | GIR_EraseRootFromParent_Done, |
| 130055 | // Label 6162: @421446 |
| 130056 | GIM_Try, /*On fail goto*//*Label 6163*/ GIMT_Encode4(421565), // Rule ID 7425 // |
| 130057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130060 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130061 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130062 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130063 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130064 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 130065 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 130066 | GIM_CheckHasOneUse, /*MI*/2, |
| 130067 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130068 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130069 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130070 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130071 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130072 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130073 | // (fminimum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64), |
| 130075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130080 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130085 | GIR_RootConstrainSelectedInstOperands, |
| 130086 | // GIR_Coverage, 7425, |
| 130087 | GIR_EraseRootFromParent_Done, |
| 130088 | // Label 6163: @421565 |
| 130089 | GIM_Try, /*On fail goto*//*Label 6164*/ GIMT_Encode4(421668), // Rule ID 11980 // |
| 130090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130091 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130092 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130093 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130094 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130095 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130096 | GIM_CheckHasOneUse, /*MI*/1, |
| 130097 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130098 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130099 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130100 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130101 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130102 | // (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64), |
| 130104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130114 | GIR_RootConstrainSelectedInstOperands, |
| 130115 | // GIR_Coverage, 11980, |
| 130116 | GIR_EraseRootFromParent_Done, |
| 130117 | // Label 6164: @421668 |
| 130118 | GIM_Try, /*On fail goto*//*Label 6165*/ GIMT_Encode4(421771), // Rule ID 7421 // |
| 130119 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130120 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130121 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130122 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130123 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130124 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130125 | GIM_CheckHasOneUse, /*MI*/1, |
| 130126 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130127 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130128 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130129 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130130 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130131 | // (fminimum:{ *:[f16] } (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F16_e64), |
| 130133 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130137 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130140 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130142 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130143 | GIR_RootConstrainSelectedInstOperands, |
| 130144 | // GIR_Coverage, 7421, |
| 130145 | GIR_EraseRootFromParent_Done, |
| 130146 | // Label 6165: @421771 |
| 130147 | GIM_Try, /*On fail goto*//*Label 6166*/ GIMT_Encode4(421802), // Rule ID 118 // |
| 130148 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130149 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130150 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130151 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130152 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18525), |
| 130153 | // (fminimum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18525>> => (S_MINIMUM_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 130154 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MINIMUM_F16), |
| 130155 | GIR_RootConstrainSelectedInstOperands, |
| 130156 | // GIR_Coverage, 118, |
| 130157 | GIR_Done, |
| 130158 | // Label 6166: @421802 |
| 130159 | GIM_Try, /*On fail goto*//*Label 6167*/ GIMT_Encode4(421869), // Rule ID 866 // |
| 130160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130162 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130165 | // (fminimum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23648>> => (V_MINIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F16_e64), |
| 130167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130174 | GIR_RootConstrainSelectedInstOperands, |
| 130175 | // GIR_Coverage, 866, |
| 130176 | GIR_EraseRootFromParent_Done, |
| 130177 | // Label 6167: @421869 |
| 130178 | GIM_Try, /*On fail goto*//*Label 6168*/ GIMT_Encode4(421936), // Rule ID 8106 // |
| 130179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130181 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130184 | // (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23648>> => (V_MINIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F16_e64), |
| 130186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130193 | GIR_RootConstrainSelectedInstOperands, |
| 130194 | // GIR_Coverage, 8106, |
| 130195 | GIR_EraseRootFromParent_Done, |
| 130196 | // Label 6168: @421936 |
| 130197 | GIM_Reject, |
| 130198 | // Label 6161: @421937 |
| 130199 | GIM_Reject, |
| 130200 | // Label 6157: @421938 |
| 130201 | GIM_Try, /*On fail goto*//*Label 6169*/ GIMT_Encode4(422547), |
| 130202 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 130203 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 130204 | GIM_Try, /*On fail goto*//*Label 6170*/ GIMT_Encode4(422065), // Rule ID 11982 // |
| 130205 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130206 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130207 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130208 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130209 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130210 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130211 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130212 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 130213 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 130214 | GIM_CheckHasOneUse, /*MI*/2, |
| 130215 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130216 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130217 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130219 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130220 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130221 | // (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_36291>>)<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64), |
| 130223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130230 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130232 | GIR_RootConstrainSelectedInstOperands, |
| 130233 | // GIR_Coverage, 11982, |
| 130234 | GIR_EraseRootFromParent_Done, |
| 130235 | // Label 6170: @422065 |
| 130236 | GIM_Try, /*On fail goto*//*Label 6171*/ GIMT_Encode4(422181), // Rule ID 7423 // |
| 130237 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130238 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130239 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130240 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130241 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130242 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130243 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130244 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 130245 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 130246 | GIM_CheckHasOneUse, /*MI*/2, |
| 130247 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130248 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130249 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130251 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130252 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130253 | // (fminimum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64), |
| 130255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130262 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130263 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130264 | GIR_RootConstrainSelectedInstOperands, |
| 130265 | // GIR_Coverage, 7423, |
| 130266 | GIR_EraseRootFromParent_Done, |
| 130267 | // Label 6171: @422181 |
| 130268 | GIM_Try, /*On fail goto*//*Label 6172*/ GIMT_Encode4(422281), // Rule ID 11978 // |
| 130269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130271 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130272 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130273 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130274 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 130275 | GIM_CheckHasOneUse, /*MI*/1, |
| 130276 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130277 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130279 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130280 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130281 | // (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>)<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64), |
| 130283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130289 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130290 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130291 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130292 | GIR_RootConstrainSelectedInstOperands, |
| 130293 | // GIR_Coverage, 11978, |
| 130294 | GIR_EraseRootFromParent_Done, |
| 130295 | // Label 6172: @422281 |
| 130296 | GIM_Try, /*On fail goto*//*Label 6173*/ GIMT_Encode4(422381), // Rule ID 7419 // |
| 130297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130299 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130300 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMAXIMUM), |
| 130301 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130302 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 130303 | GIM_CheckHasOneUse, /*MI*/1, |
| 130304 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130305 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130307 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130308 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130309 | // (fminimum:{ *:[f32] } (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fmaximum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23648>> => (V_MAXIMUMMINIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUMMINIMUM_F32_e64), |
| 130311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130320 | GIR_RootConstrainSelectedInstOperands, |
| 130321 | // GIR_Coverage, 7419, |
| 130322 | GIR_EraseRootFromParent_Done, |
| 130323 | // Label 6173: @422381 |
| 130324 | GIM_Try, /*On fail goto*//*Label 6174*/ GIMT_Encode4(422412), // Rule ID 116 // |
| 130325 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130327 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130328 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130329 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18525), |
| 130330 | // (fminimum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18525>> => (S_MINIMUM_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 130331 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MINIMUM_F32), |
| 130332 | GIR_RootConstrainSelectedInstOperands, |
| 130333 | // GIR_Coverage, 116, |
| 130334 | GIR_Done, |
| 130335 | // Label 6174: @422412 |
| 130336 | GIM_Try, /*On fail goto*//*Label 6175*/ GIMT_Encode4(422479), // Rule ID 864 // |
| 130337 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130338 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130339 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130342 | // (fminimum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23648>> => (V_MINIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F32_e64), |
| 130344 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130351 | GIR_RootConstrainSelectedInstOperands, |
| 130352 | // GIR_Coverage, 864, |
| 130353 | GIR_EraseRootFromParent_Done, |
| 130354 | // Label 6175: @422479 |
| 130355 | GIM_Try, /*On fail goto*//*Label 6176*/ GIMT_Encode4(422546), // Rule ID 8104 // |
| 130356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130357 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130358 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23648), |
| 130359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130361 | // (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23648>> => (V_MINIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F32_e64), |
| 130363 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130370 | GIR_RootConstrainSelectedInstOperands, |
| 130371 | // GIR_Coverage, 8104, |
| 130372 | GIR_EraseRootFromParent_Done, |
| 130373 | // Label 6176: @422546 |
| 130374 | GIM_Reject, |
| 130375 | // Label 6169: @422547 |
| 130376 | GIM_Reject, |
| 130377 | // Label 6158: @422548 |
| 130378 | GIM_Try, /*On fail goto*//*Label 6177*/ GIMT_Encode4(422682), |
| 130379 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 130380 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 130381 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 130382 | GIM_Try, /*On fail goto*//*Label 6178*/ GIMT_Encode4(422622), // Rule ID 868 // |
| 130383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130386 | // (fminimum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MINIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F64_e64), |
| 130388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130395 | GIR_RootConstrainSelectedInstOperands, |
| 130396 | // GIR_Coverage, 868, |
| 130397 | GIR_EraseRootFromParent_Done, |
| 130398 | // Label 6178: @422622 |
| 130399 | GIM_Try, /*On fail goto*//*Label 6179*/ GIMT_Encode4(422681), // Rule ID 8108 // |
| 130400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130403 | // (fminimum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MINIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUM_F64_e64), |
| 130405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130412 | GIR_RootConstrainSelectedInstOperands, |
| 130413 | // GIR_Coverage, 8108, |
| 130414 | GIR_EraseRootFromParent_Done, |
| 130415 | // Label 6179: @422681 |
| 130416 | GIM_Reject, |
| 130417 | // Label 6177: @422682 |
| 130418 | GIM_Reject, |
| 130419 | // Label 6159: @422683 |
| 130420 | GIM_Try, /*On fail goto*//*Label 6180*/ GIMT_Encode4(422757), // Rule ID 972 // |
| 130421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130422 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 130423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 130424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 130426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 130427 | // (fminimum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MINIMUM_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 130428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MINIMUM_F16), |
| 130429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130439 | GIR_RootConstrainSelectedInstOperands, |
| 130440 | // GIR_Coverage, 972, |
| 130441 | GIR_EraseRootFromParent_Done, |
| 130442 | // Label 6180: @422757 |
| 130443 | GIM_Reject, |
| 130444 | // Label 6160: @422758 |
| 130445 | GIM_Reject, |
| 130446 | // Label 85: @422759 |
| 130447 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6185*/ GIMT_Encode4(424228), |
| 130448 | /*GILLT_s16*//*Label 6181*/ GIMT_Encode4(422786), |
| 130449 | /*GILLT_s32*//*Label 6182*/ GIMT_Encode4(423408), |
| 130450 | /*GILLT_s64*//*Label 6183*/ GIMT_Encode4(424018), |
| 130451 | /*GILLT_v2s16*//*Label 6184*/ GIMT_Encode4(424153), |
| 130452 | // Label 6181: @422786 |
| 130453 | GIM_Try, /*On fail goto*//*Label 6186*/ GIMT_Encode4(423407), |
| 130454 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 130455 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 130456 | GIM_Try, /*On fail goto*//*Label 6187*/ GIMT_Encode4(422916), // Rule ID 11983 // |
| 130457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130459 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130460 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130461 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130462 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130463 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130464 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 130465 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 130466 | GIM_CheckHasOneUse, /*MI*/2, |
| 130467 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130468 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130469 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130471 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130472 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130473 | // (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f16] } (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_36291>>)<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64), |
| 130475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130482 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130483 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130485 | GIR_RootConstrainSelectedInstOperands, |
| 130486 | // GIR_Coverage, 11983, |
| 130487 | GIR_EraseRootFromParent_Done, |
| 130488 | // Label 6187: @422916 |
| 130489 | GIM_Try, /*On fail goto*//*Label 6188*/ GIMT_Encode4(423035), // Rule ID 7424 // |
| 130490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130491 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130492 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130493 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130494 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130495 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130496 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130497 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 130498 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 130499 | GIM_CheckHasOneUse, /*MI*/2, |
| 130500 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130501 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130502 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130504 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130505 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130506 | // (fmaximum:{ *:[f16] } (fcanonicalize:{ *:[f16] } (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130507 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64), |
| 130508 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130515 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130516 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130517 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130518 | GIR_RootConstrainSelectedInstOperands, |
| 130519 | // GIR_Coverage, 7424, |
| 130520 | GIR_EraseRootFromParent_Done, |
| 130521 | // Label 6188: @423035 |
| 130522 | GIM_Try, /*On fail goto*//*Label 6189*/ GIMT_Encode4(423138), // Rule ID 11979 // |
| 130523 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130525 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130526 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130527 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130528 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130529 | GIM_CheckHasOneUse, /*MI*/1, |
| 130530 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130531 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130532 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130533 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130534 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130535 | // (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64), |
| 130537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130538 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130544 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130545 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130546 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130547 | GIR_RootConstrainSelectedInstOperands, |
| 130548 | // GIR_Coverage, 11979, |
| 130549 | GIR_EraseRootFromParent_Done, |
| 130550 | // Label 6189: @423138 |
| 130551 | GIM_Try, /*On fail goto*//*Label 6190*/ GIMT_Encode4(423241), // Rule ID 7420 // |
| 130552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130554 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130555 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130556 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130557 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130558 | GIM_CheckHasOneUse, /*MI*/1, |
| 130559 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130560 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130562 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130563 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130564 | // (fmaximum:{ *:[f16] } (fminimum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>, (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f16] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f16] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F16_e64), |
| 130566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130573 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130574 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130575 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130576 | GIR_RootConstrainSelectedInstOperands, |
| 130577 | // GIR_Coverage, 7420, |
| 130578 | GIR_EraseRootFromParent_Done, |
| 130579 | // Label 6190: @423241 |
| 130580 | GIM_Try, /*On fail goto*//*Label 6191*/ GIMT_Encode4(423272), // Rule ID 119 // |
| 130581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130582 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130583 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130584 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130585 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18526), |
| 130586 | // (fmaximum:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18526>> => (S_MAXIMUM_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 130587 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAXIMUM_F16), |
| 130588 | GIR_RootConstrainSelectedInstOperands, |
| 130589 | // GIR_Coverage, 119, |
| 130590 | GIR_Done, |
| 130591 | // Label 6191: @423272 |
| 130592 | GIM_Try, /*On fail goto*//*Label 6192*/ GIMT_Encode4(423339), // Rule ID 867 // |
| 130593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130595 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130598 | // (fmaximum:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23651>> => (V_MAXIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130599 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F16_e64), |
| 130600 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130606 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130607 | GIR_RootConstrainSelectedInstOperands, |
| 130608 | // GIR_Coverage, 867, |
| 130609 | GIR_EraseRootFromParent_Done, |
| 130610 | // Label 6192: @423339 |
| 130611 | GIM_Try, /*On fail goto*//*Label 6193*/ GIMT_Encode4(423406), // Rule ID 8107 // |
| 130612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130613 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130614 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130617 | // (fmaximum:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23651>> => (V_MAXIMUM_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F16_e64), |
| 130619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130626 | GIR_RootConstrainSelectedInstOperands, |
| 130627 | // GIR_Coverage, 8107, |
| 130628 | GIR_EraseRootFromParent_Done, |
| 130629 | // Label 6193: @423406 |
| 130630 | GIM_Reject, |
| 130631 | // Label 6186: @423407 |
| 130632 | GIM_Reject, |
| 130633 | // Label 6182: @423408 |
| 130634 | GIM_Try, /*On fail goto*//*Label 6194*/ GIMT_Encode4(424017), |
| 130635 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 130636 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 130637 | GIM_Try, /*On fail goto*//*Label 6195*/ GIMT_Encode4(423535), // Rule ID 11981 // |
| 130638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130639 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130640 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130641 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130642 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130643 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130644 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130645 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 130646 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 130647 | GIM_CheckHasOneUse, /*MI*/2, |
| 130648 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130649 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130650 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130652 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130653 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130654 | // (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fcanonicalize:{ *:[f32] } (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_36291>>)<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64), |
| 130656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130659 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130660 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130665 | GIR_RootConstrainSelectedInstOperands, |
| 130666 | // GIR_Coverage, 11981, |
| 130667 | GIR_EraseRootFromParent_Done, |
| 130668 | // Label 6195: @423535 |
| 130669 | GIM_Try, /*On fail goto*//*Label 6196*/ GIMT_Encode4(423651), // Rule ID 7422 // |
| 130670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130671 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130672 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130673 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCANONICALIZE), |
| 130674 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130676 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 130678 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 130679 | GIM_CheckHasOneUse, /*MI*/2, |
| 130680 | GIM_CheckCxxInsnPredicate, /*MI*/1, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36291), |
| 130681 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130682 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 130683 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130684 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130685 | GIM_CheckComplexPattern, /*MI*/2, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130686 | // (fmaximum:{ *:[f32] } (fcanonicalize:{ *:[f32] } (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_36291>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64), |
| 130688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130697 | GIR_RootConstrainSelectedInstOperands, |
| 130698 | // GIR_Coverage, 7422, |
| 130699 | GIR_EraseRootFromParent_Done, |
| 130700 | // Label 6196: @423651 |
| 130701 | GIM_Try, /*On fail goto*//*Label 6197*/ GIMT_Encode4(423751), // Rule ID 11977 // |
| 130702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130703 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130704 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 130705 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130706 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130707 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 130708 | GIM_CheckHasOneUse, /*MI*/1, |
| 130709 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130710 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130711 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130712 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130713 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130714 | // (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods), (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>)<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64), |
| 130716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130717 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_mods |
| 130718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src1_mods |
| 130720 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src1 |
| 130721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src2_mods |
| 130722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src2 |
| 130723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130724 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130725 | GIR_RootConstrainSelectedInstOperands, |
| 130726 | // GIR_Coverage, 11977, |
| 130727 | GIR_EraseRootFromParent_Done, |
| 130728 | // Label 6197: @423751 |
| 130729 | GIM_Try, /*On fail goto*//*Label 6198*/ GIMT_Encode4(423851), // Rule ID 7418 // |
| 130730 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130731 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130732 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130733 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FMINIMUM), |
| 130734 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 130735 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 130736 | GIM_CheckHasOneUse, /*MI*/1, |
| 130737 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130738 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130739 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 130740 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130741 | GIM_CheckComplexPattern, /*MI*/1, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130742 | // (fmaximum:{ *:[f32] } (fminimum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_mods), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_mods))<<P:Predicate_fminimum_oneuse>>, (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_mods))<<P:Predicate_anonymous_23651>> => (V_MINIMUMMAXIMUM_F32_e64:{ *:[f32] } ?:{ *:[i32] }:$src0_mods, ?:{ *:[f32] }:$src0, ?:{ *:[i32] }:$src1_mods, ?:{ *:[f32] }:$src1, ?:{ *:[i32] }:$src2_mods, ?:{ *:[f32] }:$src2, 0:{ *:[i1] }, 0:{ *:[i32] }) |
| 130743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINIMUMMAXIMUM_F32_e64), |
| 130744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 130746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_mods |
| 130748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_mods |
| 130750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 130751 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130752 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130753 | GIR_RootConstrainSelectedInstOperands, |
| 130754 | // GIR_Coverage, 7418, |
| 130755 | GIR_EraseRootFromParent_Done, |
| 130756 | // Label 6198: @423851 |
| 130757 | GIM_Try, /*On fail goto*//*Label 6199*/ GIMT_Encode4(423882), // Rule ID 117 // |
| 130758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130760 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130761 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130762 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18526), |
| 130763 | // (fmaximum:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18526>> => (S_MAXIMUM_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 130764 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAXIMUM_F32), |
| 130765 | GIR_RootConstrainSelectedInstOperands, |
| 130766 | // GIR_Coverage, 117, |
| 130767 | GIR_Done, |
| 130768 | // Label 6199: @423882 |
| 130769 | GIM_Try, /*On fail goto*//*Label 6200*/ GIMT_Encode4(423949), // Rule ID 865 // |
| 130770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130772 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130773 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130775 | // (fmaximum:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers))<<P:Predicate_anonymous_23651>> => (V_MAXIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F32_e64), |
| 130777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130782 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130784 | GIR_RootConstrainSelectedInstOperands, |
| 130785 | // GIR_Coverage, 865, |
| 130786 | GIR_EraseRootFromParent_Done, |
| 130787 | // Label 6200: @423949 |
| 130788 | GIM_Try, /*On fail goto*//*Label 6201*/ GIMT_Encode4(424016), // Rule ID 8105 // |
| 130789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130791 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_23651), |
| 130792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130794 | // (fmaximum:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_23651>> => (V_MAXIMUM_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F32_e64), |
| 130796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130803 | GIR_RootConstrainSelectedInstOperands, |
| 130804 | // GIR_Coverage, 8105, |
| 130805 | GIR_EraseRootFromParent_Done, |
| 130806 | // Label 6201: @424016 |
| 130807 | GIM_Reject, |
| 130808 | // Label 6194: @424017 |
| 130809 | GIM_Reject, |
| 130810 | // Label 6183: @424018 |
| 130811 | GIM_Try, /*On fail goto*//*Label 6202*/ GIMT_Encode4(424152), |
| 130812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 130813 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 130814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 130815 | GIM_Try, /*On fail goto*//*Label 6203*/ GIMT_Encode4(424092), // Rule ID 869 // |
| 130816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130817 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130818 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 130819 | // (fmaximum:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAXIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F64_e64), |
| 130821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 130827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 130828 | GIR_RootConstrainSelectedInstOperands, |
| 130829 | // GIR_Coverage, 869, |
| 130830 | GIR_EraseRootFromParent_Done, |
| 130831 | // Label 6203: @424092 |
| 130832 | GIM_Try, /*On fail goto*//*Label 6204*/ GIMT_Encode4(424151), // Rule ID 8109 // |
| 130833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130834 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 130835 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 130836 | // (fmaximum:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MAXIMUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 130837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXIMUM_F64_e64), |
| 130838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 130840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 130841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 130842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 130843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 130844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 130845 | GIR_RootConstrainSelectedInstOperands, |
| 130846 | // GIR_Coverage, 8109, |
| 130847 | GIR_EraseRootFromParent_Done, |
| 130848 | // Label 6204: @424151 |
| 130849 | GIM_Reject, |
| 130850 | // Label 6202: @424152 |
| 130851 | GIM_Reject, |
| 130852 | // Label 6184: @424153 |
| 130853 | GIM_Try, /*On fail goto*//*Label 6205*/ GIMT_Encode4(424227), // Rule ID 971 // |
| 130854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 130855 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 130856 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 130857 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 130859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 130860 | // (fmaximum:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MAXIMUM_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 130861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAXIMUM_F16), |
| 130862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 130864 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 130865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 130866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 130867 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130868 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130869 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130870 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130871 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130872 | GIR_RootConstrainSelectedInstOperands, |
| 130873 | // GIR_Coverage, 971, |
| 130874 | GIR_EraseRootFromParent_Done, |
| 130875 | // Label 6205: @424227 |
| 130876 | GIM_Reject, |
| 130877 | // Label 6185: @424228 |
| 130878 | GIM_Reject, |
| 130879 | // Label 86: @424229 |
| 130880 | GIM_Try, /*On fail goto*//*Label 6206*/ GIMT_Encode4(424352), |
| 130881 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 130882 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 130883 | GIM_Try, /*On fail goto*//*Label 6207*/ GIMT_Encode4(424296), // Rule ID 1648 // |
| 130884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 130885 | // (get_fpmode:{ *:[i32] }) => (S_AND_B32:{ *:[i32] }:{ *:[i1] } 8909823:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 47105:{ *:[i32] })) |
| 130886 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 130887 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32), |
| 130888 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 130889 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(47105), |
| 130890 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 130891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 130892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 130893 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(8909823), |
| 130894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 130895 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 130896 | GIR_RootConstrainSelectedInstOperands, |
| 130897 | // GIR_Coverage, 1648, |
| 130898 | GIR_EraseRootFromParent_Done, |
| 130899 | // Label 6207: @424296 |
| 130900 | GIM_Try, /*On fail goto*//*Label 6208*/ GIMT_Encode4(424351), // Rule ID 1649 // |
| 130901 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 130902 | // (get_fpmode:{ *:[i32] }) => (S_AND_B32:{ *:[i32] }:{ *:[i1] } 521215:{ *:[i32] }, (S_GETREG_B32:{ *:[i1] } 36865:{ *:[i32] })) |
| 130903 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s1, |
| 130904 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_GETREG_B32), |
| 130905 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 130906 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(36865), |
| 130907 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 130908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_AND_B32), |
| 130909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 130910 | GIR_AddImm, /*InsnID*/0, /*Imm*/GIMT_Encode8(521215), |
| 130911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 130912 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 130913 | GIR_RootConstrainSelectedInstOperands, |
| 130914 | // GIR_Coverage, 1649, |
| 130915 | GIR_EraseRootFromParent_Done, |
| 130916 | // Label 6208: @424351 |
| 130917 | GIM_Reject, |
| 130918 | // Label 6206: @424352 |
| 130919 | GIM_Reject, |
| 130920 | // Label 87: @424353 |
| 130921 | GIM_Try, /*On fail goto*//*Label 6209*/ GIMT_Encode4(424429), // Rule ID 2225 // |
| 130922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 130923 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 130924 | // MIs[0] DstI[vdst] |
| 130925 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/0, /*SizeInBits*/32, |
| 130926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130927 | // MIs[0] Operand 1 |
| 130928 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/32, |
| 130929 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130930 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_PTR_ADD), |
| 130931 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 130932 | GIM_CheckHasOneUse, /*MI*/1, |
| 130933 | // MIs[1] src0 |
| 130934 | GIM_CheckPointerToAny, /*MI*/1, /*Op*/1, /*SizeInBits*/32, |
| 130935 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/1, /*StoreIdx*/0, // Name : pred:4:x |
| 130936 | GIM_RecordNamedOperand, /*MI*/1, /*Op*/2, /*StoreIdx*/1, // Name : pred:4:y |
| 130937 | GIM_RecordNamedOperand, /*MI*/0, /*Op*/2, /*StoreIdx*/2, // Name : pred:4:z |
| 130938 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24030), |
| 130939 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 130940 | // (ptradd:{ *:[i32] } (ptradd:{ *:[i32] } i32:{ *:[i32] }:$src0:$pred:4:x, i32:{ *:[i32] }:$src1:$pred:4:y)<<P:Predicate_anonymous_24031>>, i32:{ *:[i32] }:$src2:$pred:4:z)<<P:4:Predicate_anonymous_24030>> => (V_ADD3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 130941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD3_U32_e64), |
| 130942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 130944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 130945 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 130946 | GIR_RootConstrainSelectedInstOperands, |
| 130947 | // GIR_Coverage, 2225, |
| 130948 | GIR_EraseRootFromParent_Done, |
| 130949 | // Label 6209: @424429 |
| 130950 | GIM_Reject, |
| 130951 | // Label 88: @424430 |
| 130952 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6213*/ GIMT_Encode4(427533), |
| 130953 | /*GILLT_s16*//*Label 6210*/ GIMT_Encode4(424457), |
| 130954 | /*GILLT_s32*//*Label 6211*/ GIMT_Encode4(426016), GIMT_Encode4(0), |
| 130955 | /*GILLT_v2s16*//*Label 6212*/ GIMT_Encode4(427461), |
| 130956 | // Label 6210: @424457 |
| 130957 | GIM_Try, /*On fail goto*//*Label 6214*/ GIMT_Encode4(426015), |
| 130958 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 130959 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 130960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 130961 | GIM_Try, /*On fail goto*//*Label 6215*/ GIMT_Encode4(424566), // Rule ID 11423 // |
| 130962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 130963 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130964 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 130965 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130966 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130967 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 130968 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 130969 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 130970 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 130971 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 130972 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 130973 | // MIs[3] src0 |
| 130974 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 130975 | // MIs[3] src1 |
| 130976 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 130977 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 130978 | // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 130979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 130980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 130981 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 130983 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130984 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 130985 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130986 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 130987 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130988 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 130989 | GIR_RootConstrainSelectedInstOperands, |
| 130990 | // GIR_Coverage, 11423, |
| 130991 | GIR_EraseRootFromParent_Done, |
| 130992 | // Label 6215: @424566 |
| 130993 | GIM_Try, /*On fail goto*//*Label 6216*/ GIMT_Encode4(424660), // Rule ID 11424 // |
| 130994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 130995 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 130996 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 130997 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 130998 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 130999 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131000 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131001 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131002 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131003 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131004 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131005 | // MIs[3] src1 |
| 131006 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131007 | // MIs[3] src0 |
| 131008 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131009 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131010 | // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131013 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131014 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131016 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131017 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131018 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131020 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131021 | GIR_RootConstrainSelectedInstOperands, |
| 131022 | // GIR_Coverage, 11424, |
| 131023 | GIR_EraseRootFromParent_Done, |
| 131024 | // Label 6216: @424660 |
| 131025 | GIM_Try, /*On fail goto*//*Label 6217*/ GIMT_Encode4(424754), // Rule ID 11425 // |
| 131026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131027 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131028 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131029 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131030 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131031 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131032 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131033 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131034 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131035 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131036 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131037 | // MIs[3] src0 |
| 131038 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131039 | // MIs[3] src1 |
| 131040 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131041 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131042 | // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131045 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131046 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131047 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131049 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131053 | GIR_RootConstrainSelectedInstOperands, |
| 131054 | // GIR_Coverage, 11425, |
| 131055 | GIR_EraseRootFromParent_Done, |
| 131056 | // Label 6217: @424754 |
| 131057 | GIM_Try, /*On fail goto*//*Label 6218*/ GIMT_Encode4(424848), // Rule ID 11426 // |
| 131058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131059 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131060 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131061 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131062 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131063 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131064 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131065 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131066 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131067 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131068 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131069 | // MIs[3] src1 |
| 131070 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131071 | // MIs[3] src0 |
| 131072 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131073 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131074 | // (smin:{ *:[i16] } (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131075 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131076 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131078 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131080 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131081 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131082 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131083 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131085 | GIR_RootConstrainSelectedInstOperands, |
| 131086 | // GIR_Coverage, 11426, |
| 131087 | GIR_EraseRootFromParent_Done, |
| 131088 | // Label 6218: @424848 |
| 131089 | GIM_Try, /*On fail goto*//*Label 6219*/ GIMT_Encode4(424942), // Rule ID 11427 // |
| 131090 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131091 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131092 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131093 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131094 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131095 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131096 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131097 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131098 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131099 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131100 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131101 | // MIs[3] src0 |
| 131102 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131103 | // MIs[3] src1 |
| 131104 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131105 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131106 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131109 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131110 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131111 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131112 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131113 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131114 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131115 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131117 | GIR_RootConstrainSelectedInstOperands, |
| 131118 | // GIR_Coverage, 11427, |
| 131119 | GIR_EraseRootFromParent_Done, |
| 131120 | // Label 6219: @424942 |
| 131121 | GIM_Try, /*On fail goto*//*Label 6220*/ GIMT_Encode4(425036), // Rule ID 11428 // |
| 131122 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131123 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131124 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131125 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131126 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131127 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131128 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131129 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131130 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131131 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131132 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131133 | // MIs[3] src1 |
| 131134 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131135 | // MIs[3] src0 |
| 131136 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131137 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131138 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131141 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131142 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131143 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131144 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131145 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131146 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131147 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131149 | GIR_RootConstrainSelectedInstOperands, |
| 131150 | // GIR_Coverage, 11428, |
| 131151 | GIR_EraseRootFromParent_Done, |
| 131152 | // Label 6220: @425036 |
| 131153 | GIM_Try, /*On fail goto*//*Label 6221*/ GIMT_Encode4(425130), // Rule ID 11429 // |
| 131154 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131155 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131156 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131157 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131158 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131159 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131160 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131161 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131162 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131163 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131164 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131165 | // MIs[3] src0 |
| 131166 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131167 | // MIs[3] src1 |
| 131168 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131169 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131170 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131173 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131174 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131175 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131176 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131177 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131178 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131179 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131181 | GIR_RootConstrainSelectedInstOperands, |
| 131182 | // GIR_Coverage, 11429, |
| 131183 | GIR_EraseRootFromParent_Done, |
| 131184 | // Label 6221: @425130 |
| 131185 | GIM_Try, /*On fail goto*//*Label 6222*/ GIMT_Encode4(425224), // Rule ID 11430 // |
| 131186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131187 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131188 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131189 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131190 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131191 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131192 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131193 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131194 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131195 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131196 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131197 | // MIs[3] src1 |
| 131198 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131199 | // MIs[3] src0 |
| 131200 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131201 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131202 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131205 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131206 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131207 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131208 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131209 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131210 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131211 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131213 | GIR_RootConstrainSelectedInstOperands, |
| 131214 | // GIR_Coverage, 11430, |
| 131215 | GIR_EraseRootFromParent_Done, |
| 131216 | // Label 6222: @425224 |
| 131217 | GIM_Try, /*On fail goto*//*Label 6223*/ GIMT_Encode4(425318), // Rule ID 7347 // |
| 131218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131219 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131220 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131221 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131222 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131223 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131224 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131225 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131226 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131227 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131228 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131229 | // MIs[3] src0 |
| 131230 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131231 | // MIs[3] src1 |
| 131232 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131233 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131234 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131236 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131238 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131239 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131240 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131245 | GIR_RootConstrainSelectedInstOperands, |
| 131246 | // GIR_Coverage, 7347, |
| 131247 | GIR_EraseRootFromParent_Done, |
| 131248 | // Label 6223: @425318 |
| 131249 | GIM_Try, /*On fail goto*//*Label 6224*/ GIMT_Encode4(425412), // Rule ID 11416 // |
| 131250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131251 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131252 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131253 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131254 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131255 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131256 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131257 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131258 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131259 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131260 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131261 | // MIs[3] src1 |
| 131262 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131263 | // MIs[3] src0 |
| 131264 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131265 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131266 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131268 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131270 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131271 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131272 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131277 | GIR_RootConstrainSelectedInstOperands, |
| 131278 | // GIR_Coverage, 11416, |
| 131279 | GIR_EraseRootFromParent_Done, |
| 131280 | // Label 6224: @425412 |
| 131281 | GIM_Try, /*On fail goto*//*Label 6225*/ GIMT_Encode4(425506), // Rule ID 11419 // |
| 131282 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131283 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131284 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131285 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131286 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131287 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131288 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131289 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131290 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131291 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131292 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131293 | // MIs[3] src0 |
| 131294 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131295 | // MIs[3] src1 |
| 131296 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131297 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131298 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131301 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131302 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131304 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131309 | GIR_RootConstrainSelectedInstOperands, |
| 131310 | // GIR_Coverage, 11419, |
| 131311 | GIR_EraseRootFromParent_Done, |
| 131312 | // Label 6225: @425506 |
| 131313 | GIM_Try, /*On fail goto*//*Label 6226*/ GIMT_Encode4(425600), // Rule ID 11420 // |
| 131314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131315 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131316 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131317 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131318 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131319 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131320 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131321 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131322 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131323 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131324 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131325 | // MIs[3] src1 |
| 131326 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131327 | // MIs[3] src0 |
| 131328 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131329 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131330 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131331 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131332 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131334 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131336 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131341 | GIR_RootConstrainSelectedInstOperands, |
| 131342 | // GIR_Coverage, 11420, |
| 131343 | GIR_EraseRootFromParent_Done, |
| 131344 | // Label 6226: @425600 |
| 131345 | GIM_Try, /*On fail goto*//*Label 6227*/ GIMT_Encode4(425694), // Rule ID 11417 // |
| 131346 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131347 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131348 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131349 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131350 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131351 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131352 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131353 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131354 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131355 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131356 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131357 | // MIs[3] src0 |
| 131358 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131359 | // MIs[3] src1 |
| 131360 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131361 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131362 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131366 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131367 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131368 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131373 | GIR_RootConstrainSelectedInstOperands, |
| 131374 | // GIR_Coverage, 11417, |
| 131375 | GIR_EraseRootFromParent_Done, |
| 131376 | // Label 6227: @425694 |
| 131377 | GIM_Try, /*On fail goto*//*Label 6228*/ GIMT_Encode4(425788), // Rule ID 11418 // |
| 131378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131379 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131380 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131381 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131382 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131383 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131384 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131385 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131386 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131387 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131388 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131389 | // MIs[3] src1 |
| 131390 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131391 | // MIs[3] src0 |
| 131392 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131393 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131394 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131396 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131397 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131398 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131399 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131400 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131402 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131405 | GIR_RootConstrainSelectedInstOperands, |
| 131406 | // GIR_Coverage, 11418, |
| 131407 | GIR_EraseRootFromParent_Done, |
| 131408 | // Label 6228: @425788 |
| 131409 | GIM_Try, /*On fail goto*//*Label 6229*/ GIMT_Encode4(425882), // Rule ID 11421 // |
| 131410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131411 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131412 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131413 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131414 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131415 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131416 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131417 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131418 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131419 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131420 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131421 | // MIs[3] src0 |
| 131422 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131423 | // MIs[3] src1 |
| 131424 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131425 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131426 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131429 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131430 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131431 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131432 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131437 | GIR_RootConstrainSelectedInstOperands, |
| 131438 | // GIR_Coverage, 11421, |
| 131439 | GIR_EraseRootFromParent_Done, |
| 131440 | // Label 6229: @425882 |
| 131441 | GIM_Try, /*On fail goto*//*Label 6230*/ GIMT_Encode4(425976), // Rule ID 11422 // |
| 131442 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 131443 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131444 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131445 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 131446 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 131447 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131448 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131449 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 131450 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 131451 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131452 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131453 | // MIs[3] src1 |
| 131454 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131455 | // MIs[3] src0 |
| 131456 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131457 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131458 | // (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smax:{ *:[i16] } i16:{ *:[i16] }:$src2, (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 131459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 131460 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131461 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131462 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131463 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131464 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 131469 | GIR_RootConstrainSelectedInstOperands, |
| 131470 | // GIR_Coverage, 11422, |
| 131471 | GIR_EraseRootFromParent_Done, |
| 131472 | // Label 6230: @425976 |
| 131473 | GIM_Try, /*On fail goto*//*Label 6231*/ GIMT_Encode4(425995), // Rule ID 827 // |
| 131474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 131475 | // (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MIN_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 131476 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_e64), |
| 131477 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 131478 | GIR_RootConstrainSelectedInstOperands, |
| 131479 | // GIR_Coverage, 827, |
| 131480 | GIR_Done, |
| 131481 | // Label 6231: @425995 |
| 131482 | GIM_Try, /*On fail goto*//*Label 6232*/ GIMT_Encode4(426014), // Rule ID 828 // |
| 131483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 131484 | // (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MIN_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 131485 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I16_t16_e64), |
| 131486 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 131487 | GIR_RootConstrainSelectedInstOperands, |
| 131488 | // GIR_Coverage, 828, |
| 131489 | GIR_Done, |
| 131490 | // Label 6232: @426014 |
| 131491 | GIM_Reject, |
| 131492 | // Label 6214: @426015 |
| 131493 | GIM_Reject, |
| 131494 | // Label 6211: @426016 |
| 131495 | GIM_Try, /*On fail goto*//*Label 6233*/ GIMT_Encode4(427460), |
| 131496 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 131497 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 131498 | GIM_Try, /*On fail goto*//*Label 6234*/ GIMT_Encode4(426107), // Rule ID 10868 // |
| 131499 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131500 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131501 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131502 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131503 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131504 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131505 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131506 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131507 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131508 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131509 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131510 | // MIs[3] src0 |
| 131511 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131512 | // MIs[3] src1 |
| 131513 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131514 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131515 | // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131517 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131518 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131519 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131520 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131521 | GIR_RootConstrainSelectedInstOperands, |
| 131522 | // GIR_Coverage, 10868, |
| 131523 | GIR_EraseRootFromParent_Done, |
| 131524 | // Label 6234: @426107 |
| 131525 | GIM_Try, /*On fail goto*//*Label 6235*/ GIMT_Encode4(426187), // Rule ID 10869 // |
| 131526 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131527 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131528 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131529 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131530 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131531 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131532 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131533 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131534 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131535 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131536 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131537 | // MIs[3] src1 |
| 131538 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131539 | // MIs[3] src0 |
| 131540 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131541 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131542 | // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131545 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131546 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131547 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131548 | GIR_RootConstrainSelectedInstOperands, |
| 131549 | // GIR_Coverage, 10869, |
| 131550 | GIR_EraseRootFromParent_Done, |
| 131551 | // Label 6235: @426187 |
| 131552 | GIM_Try, /*On fail goto*//*Label 6236*/ GIMT_Encode4(426267), // Rule ID 10870 // |
| 131553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131554 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131555 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131556 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131557 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131558 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131559 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131560 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131561 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131562 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131563 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131564 | // MIs[3] src0 |
| 131565 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131566 | // MIs[3] src1 |
| 131567 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131568 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131569 | // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131572 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131573 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131574 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131575 | GIR_RootConstrainSelectedInstOperands, |
| 131576 | // GIR_Coverage, 10870, |
| 131577 | GIR_EraseRootFromParent_Done, |
| 131578 | // Label 6236: @426267 |
| 131579 | GIM_Try, /*On fail goto*//*Label 6237*/ GIMT_Encode4(426347), // Rule ID 10871 // |
| 131580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131581 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131582 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131583 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131584 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131585 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 131586 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131587 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131588 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131589 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131590 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131591 | // MIs[3] src1 |
| 131592 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131593 | // MIs[3] src0 |
| 131594 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131595 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131596 | // (smin:{ *:[i32] } (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131598 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131599 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131600 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131601 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 131602 | GIR_RootConstrainSelectedInstOperands, |
| 131603 | // GIR_Coverage, 10871, |
| 131604 | GIR_EraseRootFromParent_Done, |
| 131605 | // Label 6237: @426347 |
| 131606 | GIM_Try, /*On fail goto*//*Label 6238*/ GIMT_Encode4(426427), // Rule ID 10872 // |
| 131607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131608 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131609 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131610 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131611 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131612 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131613 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131614 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131615 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131616 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131617 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131618 | // MIs[3] src0 |
| 131619 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131620 | // MIs[3] src1 |
| 131621 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131622 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131623 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131625 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131629 | GIR_RootConstrainSelectedInstOperands, |
| 131630 | // GIR_Coverage, 10872, |
| 131631 | GIR_EraseRootFromParent_Done, |
| 131632 | // Label 6238: @426427 |
| 131633 | GIM_Try, /*On fail goto*//*Label 6239*/ GIMT_Encode4(426507), // Rule ID 10873 // |
| 131634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131635 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131636 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131637 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131638 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131639 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131640 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131641 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131642 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131643 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131644 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131645 | // MIs[3] src1 |
| 131646 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131647 | // MIs[3] src0 |
| 131648 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131649 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131650 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131653 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 131654 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 131655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131656 | GIR_RootConstrainSelectedInstOperands, |
| 131657 | // GIR_Coverage, 10873, |
| 131658 | GIR_EraseRootFromParent_Done, |
| 131659 | // Label 6239: @426507 |
| 131660 | GIM_Try, /*On fail goto*//*Label 6240*/ GIMT_Encode4(426587), // Rule ID 10874 // |
| 131661 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131662 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131663 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131664 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131665 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131666 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131667 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131668 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131669 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131670 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131671 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131672 | // MIs[3] src0 |
| 131673 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131674 | // MIs[3] src1 |
| 131675 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131676 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131677 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131680 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131681 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131682 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131683 | GIR_RootConstrainSelectedInstOperands, |
| 131684 | // GIR_Coverage, 10874, |
| 131685 | GIR_EraseRootFromParent_Done, |
| 131686 | // Label 6240: @426587 |
| 131687 | GIM_Try, /*On fail goto*//*Label 6241*/ GIMT_Encode4(426667), // Rule ID 10875 // |
| 131688 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131689 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131690 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131691 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131692 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131693 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 131694 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131695 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131696 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131697 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 131698 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131699 | // MIs[3] src1 |
| 131700 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 131701 | // MIs[3] src0 |
| 131702 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 131703 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131704 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131706 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131707 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 131708 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 131709 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 131710 | GIR_RootConstrainSelectedInstOperands, |
| 131711 | // GIR_Coverage, 10875, |
| 131712 | GIR_EraseRootFromParent_Done, |
| 131713 | // Label 6241: @426667 |
| 131714 | GIM_Try, /*On fail goto*//*Label 6242*/ GIMT_Encode4(426747), // Rule ID 7310 // |
| 131715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131716 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131717 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131718 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131719 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131720 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131721 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131722 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131723 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131724 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131725 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131726 | // MIs[3] src0 |
| 131727 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131728 | // MIs[3] src1 |
| 131729 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131730 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131731 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131734 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131735 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131736 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131737 | GIR_RootConstrainSelectedInstOperands, |
| 131738 | // GIR_Coverage, 7310, |
| 131739 | GIR_EraseRootFromParent_Done, |
| 131740 | // Label 6242: @426747 |
| 131741 | GIM_Try, /*On fail goto*//*Label 6243*/ GIMT_Encode4(426827), // Rule ID 10861 // |
| 131742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131743 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131744 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131745 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131746 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131747 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131748 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131749 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131750 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131751 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131752 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131753 | // MIs[3] src1 |
| 131754 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131755 | // MIs[3] src0 |
| 131756 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131757 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131758 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131761 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131762 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131763 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131764 | GIR_RootConstrainSelectedInstOperands, |
| 131765 | // GIR_Coverage, 10861, |
| 131766 | GIR_EraseRootFromParent_Done, |
| 131767 | // Label 6243: @426827 |
| 131768 | GIM_Try, /*On fail goto*//*Label 6244*/ GIMT_Encode4(426907), // Rule ID 10864 // |
| 131769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131770 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131771 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131772 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131773 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131774 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131775 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131776 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131777 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131778 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131779 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131780 | // MIs[3] src0 |
| 131781 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131782 | // MIs[3] src1 |
| 131783 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131784 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131785 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131788 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131789 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131790 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131791 | GIR_RootConstrainSelectedInstOperands, |
| 131792 | // GIR_Coverage, 10864, |
| 131793 | GIR_EraseRootFromParent_Done, |
| 131794 | // Label 6244: @426907 |
| 131795 | GIM_Try, /*On fail goto*//*Label 6245*/ GIMT_Encode4(426987), // Rule ID 10865 // |
| 131796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131797 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131798 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131799 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131800 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131801 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131802 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131803 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131804 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131805 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 131806 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131807 | // MIs[3] src1 |
| 131808 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131809 | // MIs[3] src0 |
| 131810 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131811 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131812 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131815 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131816 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131817 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 131818 | GIR_RootConstrainSelectedInstOperands, |
| 131819 | // GIR_Coverage, 10865, |
| 131820 | GIR_EraseRootFromParent_Done, |
| 131821 | // Label 6245: @426987 |
| 131822 | GIM_Try, /*On fail goto*//*Label 6246*/ GIMT_Encode4(427067), // Rule ID 10862 // |
| 131823 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131824 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131825 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131826 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131827 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131828 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131829 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131830 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131831 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131832 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131833 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131834 | // MIs[3] src0 |
| 131835 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131836 | // MIs[3] src1 |
| 131837 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131838 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131839 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131841 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131842 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131843 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131844 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131845 | GIR_RootConstrainSelectedInstOperands, |
| 131846 | // GIR_Coverage, 10862, |
| 131847 | GIR_EraseRootFromParent_Done, |
| 131848 | // Label 6246: @427067 |
| 131849 | GIM_Try, /*On fail goto*//*Label 6247*/ GIMT_Encode4(427147), // Rule ID 10863 // |
| 131850 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131851 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131852 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131853 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131854 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131855 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131856 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131857 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131858 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131859 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131860 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131861 | // MIs[3] src1 |
| 131862 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131863 | // MIs[3] src0 |
| 131864 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131865 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131866 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131869 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131870 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131871 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131872 | GIR_RootConstrainSelectedInstOperands, |
| 131873 | // GIR_Coverage, 10863, |
| 131874 | GIR_EraseRootFromParent_Done, |
| 131875 | // Label 6247: @427147 |
| 131876 | GIM_Try, /*On fail goto*//*Label 6248*/ GIMT_Encode4(427227), // Rule ID 10866 // |
| 131877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131878 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131879 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131880 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131881 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131882 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131883 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131884 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131885 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131886 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131887 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131888 | // MIs[3] src0 |
| 131889 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131890 | // MIs[3] src1 |
| 131891 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131892 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131893 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131896 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131897 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131898 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131899 | GIR_RootConstrainSelectedInstOperands, |
| 131900 | // GIR_Coverage, 10866, |
| 131901 | GIR_EraseRootFromParent_Done, |
| 131902 | // Label 6248: @427227 |
| 131903 | GIM_Try, /*On fail goto*//*Label 6249*/ GIMT_Encode4(427307), // Rule ID 10867 // |
| 131904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131905 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131906 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131907 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131908 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131909 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 131910 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131911 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 131912 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 131913 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 131914 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 131915 | // MIs[3] src1 |
| 131916 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 131917 | // MIs[3] src0 |
| 131918 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 131919 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 131920 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 131922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 131924 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 131925 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 131926 | GIR_RootConstrainSelectedInstOperands, |
| 131927 | // GIR_Coverage, 10867, |
| 131928 | GIR_EraseRootFromParent_Done, |
| 131929 | // Label 6249: @427307 |
| 131930 | GIM_Try, /*On fail goto*//*Label 6250*/ GIMT_Encode4(427360), // Rule ID 7380 // |
| 131931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 131932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131933 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 131934 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131935 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131936 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131937 | GIM_CheckHasOneUse, /*MI*/1, |
| 131938 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36293), |
| 131939 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 131940 | // (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smax_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_36293>> => (V_MAXMIN_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_I32_e64), |
| 131942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131943 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131944 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131945 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 131946 | GIR_RootConstrainSelectedInstOperands, |
| 131947 | // GIR_Coverage, 7380, |
| 131948 | GIR_EraseRootFromParent_Done, |
| 131949 | // Label 6250: @427360 |
| 131950 | GIM_Try, /*On fail goto*//*Label 6251*/ GIMT_Encode4(427413), // Rule ID 11911 // |
| 131951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 131952 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131953 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 131954 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 131955 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 131956 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 131957 | GIM_CheckHasOneUse, /*MI*/1, |
| 131958 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36293), |
| 131959 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 131960 | // (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smax_oneuse>>)<<P:Predicate_anonymous_36293>> => (V_MAXMIN_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 131961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_I32_e64), |
| 131962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 131963 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 131964 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 131965 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 131966 | GIR_RootConstrainSelectedInstOperands, |
| 131967 | // GIR_Coverage, 11911, |
| 131968 | GIR_EraseRootFromParent_Done, |
| 131969 | // Label 6251: @427413 |
| 131970 | GIM_Try, /*On fail goto*//*Label 6252*/ GIMT_Encode4(427439), // Rule ID 49 // |
| 131971 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 131972 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18501), |
| 131973 | // (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18501>> => (S_MIN_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 131974 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_I32), |
| 131975 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 131976 | GIR_RootConstrainSelectedInstOperands, |
| 131977 | // GIR_Coverage, 49, |
| 131978 | GIR_Done, |
| 131979 | // Label 6252: @427439 |
| 131980 | GIM_Try, /*On fail goto*//*Label 6253*/ GIMT_Encode4(427459), // Rule ID 741 // |
| 131981 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131982 | // (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MIN_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 131983 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_I32_e64), |
| 131984 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 131985 | GIR_RootConstrainSelectedInstOperands, |
| 131986 | // GIR_Coverage, 741, |
| 131987 | GIR_Done, |
| 131988 | // Label 6253: @427459 |
| 131989 | GIM_Reject, |
| 131990 | // Label 6233: @427460 |
| 131991 | GIM_Reject, |
| 131992 | // Label 6212: @427461 |
| 131993 | GIM_Try, /*On fail goto*//*Label 6254*/ GIMT_Encode4(427532), // Rule ID 967 // |
| 131994 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 131995 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 131996 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 131997 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 131998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 131999 | // (smin:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MIN_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 132000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_I16), |
| 132001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 132003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 132004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 132005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 132006 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132007 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132008 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132009 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132010 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132011 | GIR_RootConstrainSelectedInstOperands, |
| 132012 | // GIR_Coverage, 967, |
| 132013 | GIR_EraseRootFromParent_Done, |
| 132014 | // Label 6254: @427532 |
| 132015 | GIM_Reject, |
| 132016 | // Label 6213: @427533 |
| 132017 | GIM_Reject, |
| 132018 | // Label 89: @427534 |
| 132019 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6258*/ GIMT_Encode4(430799), |
| 132020 | /*GILLT_s16*//*Label 6255*/ GIMT_Encode4(427561), |
| 132021 | /*GILLT_s32*//*Label 6256*/ GIMT_Encode4(429120), GIMT_Encode4(0), |
| 132022 | /*GILLT_v2s16*//*Label 6257*/ GIMT_Encode4(430727), |
| 132023 | // Label 6255: @427561 |
| 132024 | GIM_Try, /*On fail goto*//*Label 6259*/ GIMT_Encode4(429119), |
| 132025 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 132026 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 132027 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132028 | GIM_Try, /*On fail goto*//*Label 6260*/ GIMT_Encode4(427670), // Rule ID 11408 // |
| 132029 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132030 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132031 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132032 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132033 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132034 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132035 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132036 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132037 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132038 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132039 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132040 | // MIs[3] src0 |
| 132041 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132042 | // MIs[3] src1 |
| 132043 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132044 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132045 | // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132048 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132050 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132051 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132052 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132053 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132054 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132055 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132056 | GIR_RootConstrainSelectedInstOperands, |
| 132057 | // GIR_Coverage, 11408, |
| 132058 | GIR_EraseRootFromParent_Done, |
| 132059 | // Label 6260: @427670 |
| 132060 | GIM_Try, /*On fail goto*//*Label 6261*/ GIMT_Encode4(427764), // Rule ID 11409 // |
| 132061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132062 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132063 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132064 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132065 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132066 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132067 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132068 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132069 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132070 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132071 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132072 | // MIs[3] src1 |
| 132073 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132074 | // MIs[3] src0 |
| 132075 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132076 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132077 | // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132080 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132081 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132082 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132083 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132085 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132087 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132088 | GIR_RootConstrainSelectedInstOperands, |
| 132089 | // GIR_Coverage, 11409, |
| 132090 | GIR_EraseRootFromParent_Done, |
| 132091 | // Label 6261: @427764 |
| 132092 | GIM_Try, /*On fail goto*//*Label 6262*/ GIMT_Encode4(427858), // Rule ID 11410 // |
| 132093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132094 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132095 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132096 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132097 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132098 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132099 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132100 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132101 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132102 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132103 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132104 | // MIs[3] src0 |
| 132105 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132106 | // MIs[3] src1 |
| 132107 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132108 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132109 | // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132110 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132111 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132112 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132113 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132114 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132115 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132116 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132118 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132119 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132120 | GIR_RootConstrainSelectedInstOperands, |
| 132121 | // GIR_Coverage, 11410, |
| 132122 | GIR_EraseRootFromParent_Done, |
| 132123 | // Label 6262: @427858 |
| 132124 | GIM_Try, /*On fail goto*//*Label 6263*/ GIMT_Encode4(427952), // Rule ID 11411 // |
| 132125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132126 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132127 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132128 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132129 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132130 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132131 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132132 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132133 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132134 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132135 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132136 | // MIs[3] src1 |
| 132137 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132138 | // MIs[3] src0 |
| 132139 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132140 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132141 | // (smax:{ *:[i16] } (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132144 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132145 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132146 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132147 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132148 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132149 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132151 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132152 | GIR_RootConstrainSelectedInstOperands, |
| 132153 | // GIR_Coverage, 11411, |
| 132154 | GIR_EraseRootFromParent_Done, |
| 132155 | // Label 6263: @427952 |
| 132156 | GIM_Try, /*On fail goto*//*Label 6264*/ GIMT_Encode4(428046), // Rule ID 11412 // |
| 132157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132158 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132159 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132160 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132161 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132162 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132163 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132164 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132165 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132166 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132167 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132168 | // MIs[3] src0 |
| 132169 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132170 | // MIs[3] src1 |
| 132171 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132172 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132173 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132181 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132182 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132183 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132184 | GIR_RootConstrainSelectedInstOperands, |
| 132185 | // GIR_Coverage, 11412, |
| 132186 | GIR_EraseRootFromParent_Done, |
| 132187 | // Label 6264: @428046 |
| 132188 | GIM_Try, /*On fail goto*//*Label 6265*/ GIMT_Encode4(428140), // Rule ID 11413 // |
| 132189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132190 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132191 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132192 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132193 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132194 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132195 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132196 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132197 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132198 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132199 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132200 | // MIs[3] src1 |
| 132201 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132202 | // MIs[3] src0 |
| 132203 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132204 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132205 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132213 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132214 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132215 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132216 | GIR_RootConstrainSelectedInstOperands, |
| 132217 | // GIR_Coverage, 11413, |
| 132218 | GIR_EraseRootFromParent_Done, |
| 132219 | // Label 6265: @428140 |
| 132220 | GIM_Try, /*On fail goto*//*Label 6266*/ GIMT_Encode4(428234), // Rule ID 11414 // |
| 132221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132222 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132223 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132224 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132225 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132226 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132227 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132228 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132229 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132230 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132231 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132232 | // MIs[3] src0 |
| 132233 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132234 | // MIs[3] src1 |
| 132235 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132236 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132237 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132245 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132246 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132248 | GIR_RootConstrainSelectedInstOperands, |
| 132249 | // GIR_Coverage, 11414, |
| 132250 | GIR_EraseRootFromParent_Done, |
| 132251 | // Label 6266: @428234 |
| 132252 | GIM_Try, /*On fail goto*//*Label 6267*/ GIMT_Encode4(428328), // Rule ID 11415 // |
| 132253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132254 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132255 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132256 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132257 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132258 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132259 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132260 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132261 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132262 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132263 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132264 | // MIs[3] src1 |
| 132265 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132266 | // MIs[3] src0 |
| 132267 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132268 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132269 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132277 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132278 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132280 | GIR_RootConstrainSelectedInstOperands, |
| 132281 | // GIR_Coverage, 11415, |
| 132282 | GIR_EraseRootFromParent_Done, |
| 132283 | // Label 6267: @428328 |
| 132284 | GIM_Try, /*On fail goto*//*Label 6268*/ GIMT_Encode4(428422), // Rule ID 7346 // |
| 132285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132286 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132287 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132288 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132289 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132290 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132291 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132292 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132293 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132294 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132295 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132296 | // MIs[3] src0 |
| 132297 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132298 | // MIs[3] src1 |
| 132299 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132300 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132301 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132309 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132310 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132312 | GIR_RootConstrainSelectedInstOperands, |
| 132313 | // GIR_Coverage, 7346, |
| 132314 | GIR_EraseRootFromParent_Done, |
| 132315 | // Label 6268: @428422 |
| 132316 | GIM_Try, /*On fail goto*//*Label 6269*/ GIMT_Encode4(428516), // Rule ID 11401 // |
| 132317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132318 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132319 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132320 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132321 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132322 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132323 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132324 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132325 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132326 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132327 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132328 | // MIs[3] src1 |
| 132329 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132330 | // MIs[3] src0 |
| 132331 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132332 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132333 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132341 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132342 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132344 | GIR_RootConstrainSelectedInstOperands, |
| 132345 | // GIR_Coverage, 11401, |
| 132346 | GIR_EraseRootFromParent_Done, |
| 132347 | // Label 6269: @428516 |
| 132348 | GIM_Try, /*On fail goto*//*Label 6270*/ GIMT_Encode4(428610), // Rule ID 11404 // |
| 132349 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132350 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132351 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132352 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132353 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132354 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132355 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132356 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132357 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132358 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132359 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132360 | // MIs[3] src0 |
| 132361 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132362 | // MIs[3] src1 |
| 132363 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132364 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132365 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132367 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132373 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132374 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132376 | GIR_RootConstrainSelectedInstOperands, |
| 132377 | // GIR_Coverage, 11404, |
| 132378 | GIR_EraseRootFromParent_Done, |
| 132379 | // Label 6270: @428610 |
| 132380 | GIM_Try, /*On fail goto*//*Label 6271*/ GIMT_Encode4(428704), // Rule ID 11405 // |
| 132381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132382 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132383 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132384 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132385 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132386 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132387 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132388 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132389 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132390 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132391 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132392 | // MIs[3] src1 |
| 132393 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132394 | // MIs[3] src0 |
| 132395 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132396 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132397 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132405 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132406 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132408 | GIR_RootConstrainSelectedInstOperands, |
| 132409 | // GIR_Coverage, 11405, |
| 132410 | GIR_EraseRootFromParent_Done, |
| 132411 | // Label 6271: @428704 |
| 132412 | GIM_Try, /*On fail goto*//*Label 6272*/ GIMT_Encode4(428798), // Rule ID 11402 // |
| 132413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132414 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132415 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132416 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132417 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132418 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132419 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132420 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132421 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132422 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132423 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132424 | // MIs[3] src0 |
| 132425 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132426 | // MIs[3] src1 |
| 132427 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132428 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132429 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132437 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132438 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132440 | GIR_RootConstrainSelectedInstOperands, |
| 132441 | // GIR_Coverage, 11402, |
| 132442 | GIR_EraseRootFromParent_Done, |
| 132443 | // Label 6272: @428798 |
| 132444 | GIM_Try, /*On fail goto*//*Label 6273*/ GIMT_Encode4(428892), // Rule ID 11403 // |
| 132445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132446 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132447 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132448 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132449 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132450 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132451 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132452 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132453 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132454 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132455 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132456 | // MIs[3] src1 |
| 132457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132458 | // MIs[3] src0 |
| 132459 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132460 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132461 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132469 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132470 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132472 | GIR_RootConstrainSelectedInstOperands, |
| 132473 | // GIR_Coverage, 11403, |
| 132474 | GIR_EraseRootFromParent_Done, |
| 132475 | // Label 6273: @428892 |
| 132476 | GIM_Try, /*On fail goto*//*Label 6274*/ GIMT_Encode4(428986), // Rule ID 11406 // |
| 132477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132478 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132479 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132480 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132481 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132482 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132483 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132484 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132485 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132486 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132487 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132488 | // MIs[3] src0 |
| 132489 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132490 | // MIs[3] src1 |
| 132491 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132492 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132493 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132501 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132504 | GIR_RootConstrainSelectedInstOperands, |
| 132505 | // GIR_Coverage, 11406, |
| 132506 | GIR_EraseRootFromParent_Done, |
| 132507 | // Label 6274: @428986 |
| 132508 | GIM_Try, /*On fail goto*//*Label 6275*/ GIMT_Encode4(429080), // Rule ID 11407 // |
| 132509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 132510 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132511 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132512 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 132513 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 132514 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132515 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132516 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 132517 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 132518 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132519 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132520 | // MIs[3] src1 |
| 132521 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132522 | // MIs[3] src0 |
| 132523 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132524 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132525 | // (smax:{ *:[i16] } (smin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (smin:{ *:[i16] } i16:{ *:[i16] }:$src2, (smax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_I16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 132526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 132527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132533 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 132536 | GIR_RootConstrainSelectedInstOperands, |
| 132537 | // GIR_Coverage, 11407, |
| 132538 | GIR_EraseRootFromParent_Done, |
| 132539 | // Label 6275: @429080 |
| 132540 | GIM_Try, /*On fail goto*//*Label 6276*/ GIMT_Encode4(429099), // Rule ID 823 // |
| 132541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 132542 | // (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MAX_I16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 132543 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_e64), |
| 132544 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 132545 | GIR_RootConstrainSelectedInstOperands, |
| 132546 | // GIR_Coverage, 823, |
| 132547 | GIR_Done, |
| 132548 | // Label 6276: @429099 |
| 132549 | GIM_Try, /*On fail goto*//*Label 6277*/ GIMT_Encode4(429118), // Rule ID 824 // |
| 132550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 132551 | // (smax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MAX_I16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 132552 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I16_t16_e64), |
| 132553 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 132554 | GIR_RootConstrainSelectedInstOperands, |
| 132555 | // GIR_Coverage, 824, |
| 132556 | GIR_Done, |
| 132557 | // Label 6277: @429118 |
| 132558 | GIM_Reject, |
| 132559 | // Label 6259: @429119 |
| 132560 | GIM_Reject, |
| 132561 | // Label 6256: @429120 |
| 132562 | GIM_Try, /*On fail goto*//*Label 6278*/ GIMT_Encode4(430726), |
| 132563 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 132564 | GIM_Try, /*On fail goto*//*Label 6279*/ GIMT_Encode4(429211), // Rule ID 10883 // |
| 132565 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132566 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132567 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132568 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132569 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132570 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132571 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132572 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132573 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132574 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132575 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132576 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132577 | // MIs[3] src0 |
| 132578 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132579 | // MIs[3] src1 |
| 132580 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132581 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132582 | // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132585 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132586 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132587 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132588 | GIR_RootConstrainSelectedInstOperands, |
| 132589 | // GIR_Coverage, 10883, |
| 132590 | GIR_EraseRootFromParent_Done, |
| 132591 | // Label 6279: @429211 |
| 132592 | GIM_Try, /*On fail goto*//*Label 6280*/ GIMT_Encode4(429294), // Rule ID 10884 // |
| 132593 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132595 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132596 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132597 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132598 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132599 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132600 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132601 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132602 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132603 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132604 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132605 | // MIs[3] src1 |
| 132606 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132607 | // MIs[3] src0 |
| 132608 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132609 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132610 | // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132613 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132614 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132615 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132616 | GIR_RootConstrainSelectedInstOperands, |
| 132617 | // GIR_Coverage, 10884, |
| 132618 | GIR_EraseRootFromParent_Done, |
| 132619 | // Label 6280: @429294 |
| 132620 | GIM_Try, /*On fail goto*//*Label 6281*/ GIMT_Encode4(429377), // Rule ID 10885 // |
| 132621 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132623 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132624 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132625 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132626 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132627 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132628 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132629 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132630 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132631 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132632 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132633 | // MIs[3] src0 |
| 132634 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132635 | // MIs[3] src1 |
| 132636 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132637 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132638 | // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132641 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132642 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132643 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132644 | GIR_RootConstrainSelectedInstOperands, |
| 132645 | // GIR_Coverage, 10885, |
| 132646 | GIR_EraseRootFromParent_Done, |
| 132647 | // Label 6281: @429377 |
| 132648 | GIM_Try, /*On fail goto*//*Label 6282*/ GIMT_Encode4(429460), // Rule ID 10886 // |
| 132649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132650 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132651 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132652 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132653 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132654 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132655 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 132656 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132657 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132658 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132659 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132660 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132661 | // MIs[3] src1 |
| 132662 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132663 | // MIs[3] src0 |
| 132664 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132665 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132666 | // (smax:{ *:[i32] } (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132669 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132670 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132671 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 132672 | GIR_RootConstrainSelectedInstOperands, |
| 132673 | // GIR_Coverage, 10886, |
| 132674 | GIR_EraseRootFromParent_Done, |
| 132675 | // Label 6282: @429460 |
| 132676 | GIM_Try, /*On fail goto*//*Label 6283*/ GIMT_Encode4(429543), // Rule ID 10887 // |
| 132677 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132678 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132679 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132680 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132681 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132682 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132683 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132684 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132685 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132686 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132687 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132688 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132689 | // MIs[3] src0 |
| 132690 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132691 | // MIs[3] src1 |
| 132692 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132693 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132694 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132697 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132698 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132699 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132700 | GIR_RootConstrainSelectedInstOperands, |
| 132701 | // GIR_Coverage, 10887, |
| 132702 | GIR_EraseRootFromParent_Done, |
| 132703 | // Label 6283: @429543 |
| 132704 | GIM_Try, /*On fail goto*//*Label 6284*/ GIMT_Encode4(429626), // Rule ID 10888 // |
| 132705 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132706 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132707 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132708 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132709 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132710 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132711 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132712 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132713 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132714 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132715 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132716 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132717 | // MIs[3] src1 |
| 132718 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132719 | // MIs[3] src0 |
| 132720 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132721 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132722 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132725 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 132726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 132727 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132728 | GIR_RootConstrainSelectedInstOperands, |
| 132729 | // GIR_Coverage, 10888, |
| 132730 | GIR_EraseRootFromParent_Done, |
| 132731 | // Label 6284: @429626 |
| 132732 | GIM_Try, /*On fail goto*//*Label 6285*/ GIMT_Encode4(429709), // Rule ID 10889 // |
| 132733 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132734 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132735 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132736 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132737 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132738 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132739 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132740 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132741 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132742 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132743 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132744 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132745 | // MIs[3] src0 |
| 132746 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132747 | // MIs[3] src1 |
| 132748 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132749 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132750 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132752 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132753 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132754 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132755 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132756 | GIR_RootConstrainSelectedInstOperands, |
| 132757 | // GIR_Coverage, 10889, |
| 132758 | GIR_EraseRootFromParent_Done, |
| 132759 | // Label 6285: @429709 |
| 132760 | GIM_Try, /*On fail goto*//*Label 6286*/ GIMT_Encode4(429792), // Rule ID 10890 // |
| 132761 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132762 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132763 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132764 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132765 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132766 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132767 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 132768 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132769 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132770 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132771 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 132772 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132773 | // MIs[3] src1 |
| 132774 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 132775 | // MIs[3] src0 |
| 132776 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 132777 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132778 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132779 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132780 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132781 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 132782 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 132783 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 132784 | GIR_RootConstrainSelectedInstOperands, |
| 132785 | // GIR_Coverage, 10890, |
| 132786 | GIR_EraseRootFromParent_Done, |
| 132787 | // Label 6286: @429792 |
| 132788 | GIM_Try, /*On fail goto*//*Label 6287*/ GIMT_Encode4(429875), // Rule ID 7311 // |
| 132789 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132791 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132792 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132793 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132794 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132795 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132796 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132797 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132798 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132799 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132800 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132801 | // MIs[3] src0 |
| 132802 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132803 | // MIs[3] src1 |
| 132804 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132805 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132806 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132809 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132810 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132811 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132812 | GIR_RootConstrainSelectedInstOperands, |
| 132813 | // GIR_Coverage, 7311, |
| 132814 | GIR_EraseRootFromParent_Done, |
| 132815 | // Label 6287: @429875 |
| 132816 | GIM_Try, /*On fail goto*//*Label 6288*/ GIMT_Encode4(429958), // Rule ID 10876 // |
| 132817 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132818 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132819 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132820 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132821 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132822 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132823 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132824 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132825 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132826 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132827 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132828 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132829 | // MIs[3] src1 |
| 132830 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132831 | // MIs[3] src0 |
| 132832 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132833 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132834 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132836 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132837 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132838 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132839 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132840 | GIR_RootConstrainSelectedInstOperands, |
| 132841 | // GIR_Coverage, 10876, |
| 132842 | GIR_EraseRootFromParent_Done, |
| 132843 | // Label 6288: @429958 |
| 132844 | GIM_Try, /*On fail goto*//*Label 6289*/ GIMT_Encode4(430041), // Rule ID 10879 // |
| 132845 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132847 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132848 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132849 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132850 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132851 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132852 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132853 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132854 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132855 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132856 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132857 | // MIs[3] src0 |
| 132858 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132859 | // MIs[3] src1 |
| 132860 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132861 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132862 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132865 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132866 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132867 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132868 | GIR_RootConstrainSelectedInstOperands, |
| 132869 | // GIR_Coverage, 10879, |
| 132870 | GIR_EraseRootFromParent_Done, |
| 132871 | // Label 6289: @430041 |
| 132872 | GIM_Try, /*On fail goto*//*Label 6290*/ GIMT_Encode4(430124), // Rule ID 10880 // |
| 132873 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132874 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132875 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132876 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132877 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132878 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132879 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132880 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132881 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132882 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132883 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 132884 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132885 | // MIs[3] src1 |
| 132886 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132887 | // MIs[3] src0 |
| 132888 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132889 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132890 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132893 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132894 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132895 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 132896 | GIR_RootConstrainSelectedInstOperands, |
| 132897 | // GIR_Coverage, 10880, |
| 132898 | GIR_EraseRootFromParent_Done, |
| 132899 | // Label 6290: @430124 |
| 132900 | GIM_Try, /*On fail goto*//*Label 6291*/ GIMT_Encode4(430207), // Rule ID 10877 // |
| 132901 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132903 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132904 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132905 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132906 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132907 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132908 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132909 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132910 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132911 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132912 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132913 | // MIs[3] src0 |
| 132914 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132915 | // MIs[3] src1 |
| 132916 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132917 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132918 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132921 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132922 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132923 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132924 | GIR_RootConstrainSelectedInstOperands, |
| 132925 | // GIR_Coverage, 10877, |
| 132926 | GIR_EraseRootFromParent_Done, |
| 132927 | // Label 6291: @430207 |
| 132928 | GIM_Try, /*On fail goto*//*Label 6292*/ GIMT_Encode4(430290), // Rule ID 10878 // |
| 132929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132931 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132932 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132933 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132934 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132935 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132936 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132937 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132938 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132939 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132940 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132941 | // MIs[3] src1 |
| 132942 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132943 | // MIs[3] src0 |
| 132944 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132945 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132946 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132947 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132948 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132949 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 132950 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 132951 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132952 | GIR_RootConstrainSelectedInstOperands, |
| 132953 | // GIR_Coverage, 10878, |
| 132954 | GIR_EraseRootFromParent_Done, |
| 132955 | // Label 6292: @430290 |
| 132956 | GIM_Try, /*On fail goto*//*Label 6293*/ GIMT_Encode4(430373), // Rule ID 10881 // |
| 132957 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132958 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132959 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132960 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132961 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132962 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132963 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132964 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132965 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132966 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132967 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132968 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132969 | // MIs[3] src0 |
| 132970 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 132971 | // MIs[3] src1 |
| 132972 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132973 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 132974 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 132975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 132976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 132977 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 132978 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 132979 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 132980 | GIR_RootConstrainSelectedInstOperands, |
| 132981 | // GIR_Coverage, 10881, |
| 132982 | GIR_EraseRootFromParent_Done, |
| 132983 | // Label 6293: @430373 |
| 132984 | GIM_Try, /*On fail goto*//*Label 6294*/ GIMT_Encode4(430456), // Rule ID 10882 // |
| 132985 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 132986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 132987 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 132988 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132989 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 132990 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 132991 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 132992 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 132993 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 132994 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 132995 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 132996 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_SMAX), |
| 132997 | // MIs[3] src1 |
| 132998 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 132999 | // MIs[3] src0 |
| 133000 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133001 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133002 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (smin:{ *:[i32] } i32:{ *:[i32] }:$src2, (smax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 133004 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133005 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133006 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133007 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 133008 | GIR_RootConstrainSelectedInstOperands, |
| 133009 | // GIR_Coverage, 10882, |
| 133010 | GIR_EraseRootFromParent_Done, |
| 133011 | // Label 6294: @430456 |
| 133012 | GIM_Try, /*On fail goto*//*Label 6295*/ GIMT_Encode4(430510), // Rule ID 8114 // |
| 133013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 133014 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133015 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), |
| 133016 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133017 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133018 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0, |
| 133019 | // MIs[0] x |
| 133020 | GIM_CheckIsSameOperand, /*MI*/0, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133021 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18503), |
| 133022 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 133023 | // (smax:{ *:[i32] } (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$x), i32:{ *:[i32] }:$x)<<P:Predicate_anonymous_18503>> => (S_ABS_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$x) |
| 133024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32), |
| 133025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 133026 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // x |
| 133027 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 133028 | GIR_RootConstrainSelectedInstOperands, |
| 133029 | // GIR_Coverage, 8114, |
| 133030 | GIR_EraseRootFromParent_Done, |
| 133031 | // Label 6295: @430510 |
| 133032 | GIM_Try, /*On fail goto*//*Label 6296*/ GIMT_Encode4(430561), // Rule ID 1643 // |
| 133033 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 133035 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 133036 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SUB), |
| 133037 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133038 | GIM_CheckConstantInt8, /*MI*/1, /*Op*/1, 0, |
| 133039 | // MIs[1] x |
| 133040 | GIM_CheckIsSameOperand, /*MI*/1, /*OpIdx*/2, /*OtherMI*/0, /*OtherOpIdx*/1, |
| 133041 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18503), |
| 133042 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 133043 | // (smax:{ *:[i32] } i32:{ *:[i32] }:$x, (sub:{ *:[i32] } 0:{ *:[i32] }, i32:{ *:[i32] }:$x))<<P:Predicate_anonymous_18503>> => (S_ABS_I32:{ *:[i32] }:{ *:[i1] } SReg_32:{ *:[i32] }:$x) |
| 133044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32), |
| 133045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 133046 | GIR_RootToRootCopy, /*OpIdx*/1, // x |
| 133047 | GIR_SetImplicitDefDead, /*InsnID*/0, /*OpIdx for AMDGPU::SCC*/0, |
| 133048 | GIR_RootConstrainSelectedInstOperands, |
| 133049 | // GIR_Coverage, 1643, |
| 133050 | GIR_EraseRootFromParent_Done, |
| 133051 | // Label 6296: @430561 |
| 133052 | GIM_Try, /*On fail goto*//*Label 6297*/ GIMT_Encode4(430617), // Rule ID 7381 // |
| 133053 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 133054 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133055 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133056 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133057 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 133058 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133059 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133060 | GIM_CheckHasOneUse, /*MI*/1, |
| 133061 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36295), |
| 133062 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 133063 | // (smax:{ *:[i32] } (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smin_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_36295>> => (V_MINMAX_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_I32_e64), |
| 133065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133066 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133067 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133068 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 133069 | GIR_RootConstrainSelectedInstOperands, |
| 133070 | // GIR_Coverage, 7381, |
| 133071 | GIR_EraseRootFromParent_Done, |
| 133072 | // Label 6297: @430617 |
| 133073 | GIM_Try, /*On fail goto*//*Label 6298*/ GIMT_Encode4(430673), // Rule ID 11912 // |
| 133074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 133075 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133077 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 133078 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_SMIN), |
| 133079 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133080 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133081 | GIM_CheckHasOneUse, /*MI*/1, |
| 133082 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36295), |
| 133083 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 133084 | // (smax:{ *:[i32] } i32:{ *:[i32] }:$src2, (smin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_smin_oneuse>>)<<P:Predicate_anonymous_36295>> => (V_MINMAX_I32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_I32_e64), |
| 133086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133087 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133088 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133089 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 133090 | GIR_RootConstrainSelectedInstOperands, |
| 133091 | // GIR_Coverage, 11912, |
| 133092 | GIR_EraseRootFromParent_Done, |
| 133093 | // Label 6298: @430673 |
| 133094 | GIM_Try, /*On fail goto*//*Label 6299*/ GIMT_Encode4(430702), // Rule ID 51 // |
| 133095 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133096 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 133097 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18503), |
| 133098 | // (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18503>> => (S_MAX_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 133099 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_I32), |
| 133100 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 133101 | GIR_RootConstrainSelectedInstOperands, |
| 133102 | // GIR_Coverage, 51, |
| 133103 | GIR_Done, |
| 133104 | // Label 6299: @430702 |
| 133105 | GIM_Try, /*On fail goto*//*Label 6300*/ GIMT_Encode4(430725), // Rule ID 742 // |
| 133106 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133108 | // (smax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MAX_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 133109 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64), |
| 133110 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 133111 | GIR_RootConstrainSelectedInstOperands, |
| 133112 | // GIR_Coverage, 742, |
| 133113 | GIR_Done, |
| 133114 | // Label 6300: @430725 |
| 133115 | GIM_Reject, |
| 133116 | // Label 6278: @430726 |
| 133117 | GIM_Reject, |
| 133118 | // Label 6257: @430727 |
| 133119 | GIM_Try, /*On fail goto*//*Label 6301*/ GIMT_Encode4(430798), // Rule ID 969 // |
| 133120 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 133121 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 133122 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 133124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 133125 | // (smax:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MAX_I16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 133126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_I16), |
| 133127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 133129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 133130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 133131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 133132 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133133 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133134 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133135 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133136 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133137 | GIR_RootConstrainSelectedInstOperands, |
| 133138 | // GIR_Coverage, 969, |
| 133139 | GIR_EraseRootFromParent_Done, |
| 133140 | // Label 6301: @430798 |
| 133141 | GIM_Reject, |
| 133142 | // Label 6258: @430799 |
| 133143 | GIM_Reject, |
| 133144 | // Label 90: @430800 |
| 133145 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6305*/ GIMT_Encode4(433903), |
| 133146 | /*GILLT_s16*//*Label 6302*/ GIMT_Encode4(430827), |
| 133147 | /*GILLT_s32*//*Label 6303*/ GIMT_Encode4(432386), GIMT_Encode4(0), |
| 133148 | /*GILLT_v2s16*//*Label 6304*/ GIMT_Encode4(433831), |
| 133149 | // Label 6302: @430827 |
| 133150 | GIM_Try, /*On fail goto*//*Label 6306*/ GIMT_Encode4(432385), |
| 133151 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 133152 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 133153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133154 | GIM_Try, /*On fail goto*//*Label 6307*/ GIMT_Encode4(430936), // Rule ID 11969 // |
| 133155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133156 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133157 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133158 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133159 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133160 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133161 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133162 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133163 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133164 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133165 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133166 | // MIs[3] src0 |
| 133167 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133168 | // MIs[3] src1 |
| 133169 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133170 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133171 | // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133174 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133175 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133176 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133177 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133178 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133179 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133180 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133181 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133182 | GIR_RootConstrainSelectedInstOperands, |
| 133183 | // GIR_Coverage, 11969, |
| 133184 | GIR_EraseRootFromParent_Done, |
| 133185 | // Label 6307: @430936 |
| 133186 | GIM_Try, /*On fail goto*//*Label 6308*/ GIMT_Encode4(431030), // Rule ID 11970 // |
| 133187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133188 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133189 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133190 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133191 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133192 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133193 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133194 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133195 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133196 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133197 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133198 | // MIs[3] src1 |
| 133199 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133200 | // MIs[3] src0 |
| 133201 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133202 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133203 | // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133206 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133207 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133208 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133209 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133210 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133211 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133212 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133213 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133214 | GIR_RootConstrainSelectedInstOperands, |
| 133215 | // GIR_Coverage, 11970, |
| 133216 | GIR_EraseRootFromParent_Done, |
| 133217 | // Label 6308: @431030 |
| 133218 | GIM_Try, /*On fail goto*//*Label 6309*/ GIMT_Encode4(431124), // Rule ID 11971 // |
| 133219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133220 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133221 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133222 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133223 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133224 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133225 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133226 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133227 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133228 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133229 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133230 | // MIs[3] src0 |
| 133231 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133232 | // MIs[3] src1 |
| 133233 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133234 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133235 | // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133239 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133240 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133241 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133242 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133243 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133244 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133246 | GIR_RootConstrainSelectedInstOperands, |
| 133247 | // GIR_Coverage, 11971, |
| 133248 | GIR_EraseRootFromParent_Done, |
| 133249 | // Label 6309: @431124 |
| 133250 | GIM_Try, /*On fail goto*//*Label 6310*/ GIMT_Encode4(431218), // Rule ID 11972 // |
| 133251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133252 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133253 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133254 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133255 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133256 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133257 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133258 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133259 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133260 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133261 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133262 | // MIs[3] src1 |
| 133263 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133264 | // MIs[3] src0 |
| 133265 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133266 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133267 | // (umin:{ *:[i16] } (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133268 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133269 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133271 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133272 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133273 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133274 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133275 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133276 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133278 | GIR_RootConstrainSelectedInstOperands, |
| 133279 | // GIR_Coverage, 11972, |
| 133280 | GIR_EraseRootFromParent_Done, |
| 133281 | // Label 6310: @431218 |
| 133282 | GIM_Try, /*On fail goto*//*Label 6311*/ GIMT_Encode4(431312), // Rule ID 11973 // |
| 133283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133284 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133285 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133286 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133287 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133288 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133289 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133290 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133291 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133292 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133293 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133294 | // MIs[3] src0 |
| 133295 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133296 | // MIs[3] src1 |
| 133297 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133298 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133299 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133300 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133301 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133303 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133304 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133305 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133306 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133307 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133308 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133310 | GIR_RootConstrainSelectedInstOperands, |
| 133311 | // GIR_Coverage, 11973, |
| 133312 | GIR_EraseRootFromParent_Done, |
| 133313 | // Label 6311: @431312 |
| 133314 | GIM_Try, /*On fail goto*//*Label 6312*/ GIMT_Encode4(431406), // Rule ID 11974 // |
| 133315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133316 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133317 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133318 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133319 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133320 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133321 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133322 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133323 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133324 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133325 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133326 | // MIs[3] src1 |
| 133327 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133328 | // MIs[3] src0 |
| 133329 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133330 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133331 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133333 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133335 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133337 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133338 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133339 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133340 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133342 | GIR_RootConstrainSelectedInstOperands, |
| 133343 | // GIR_Coverage, 11974, |
| 133344 | GIR_EraseRootFromParent_Done, |
| 133345 | // Label 6312: @431406 |
| 133346 | GIM_Try, /*On fail goto*//*Label 6313*/ GIMT_Encode4(431500), // Rule ID 11975 // |
| 133347 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133348 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133349 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133350 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133351 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133352 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133353 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133354 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133355 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133356 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133357 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133358 | // MIs[3] src0 |
| 133359 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133360 | // MIs[3] src1 |
| 133361 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133362 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133363 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133366 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133367 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133368 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133369 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133370 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133371 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133372 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133374 | GIR_RootConstrainSelectedInstOperands, |
| 133375 | // GIR_Coverage, 11975, |
| 133376 | GIR_EraseRootFromParent_Done, |
| 133377 | // Label 6313: @431500 |
| 133378 | GIM_Try, /*On fail goto*//*Label 6314*/ GIMT_Encode4(431594), // Rule ID 11976 // |
| 133379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133380 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133381 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133382 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133383 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133384 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133385 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133386 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133387 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133388 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133389 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133390 | // MIs[3] src1 |
| 133391 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133392 | // MIs[3] src0 |
| 133393 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133394 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133395 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133396 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133397 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133398 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133399 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133400 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133401 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133402 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133403 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133404 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133406 | GIR_RootConstrainSelectedInstOperands, |
| 133407 | // GIR_Coverage, 11976, |
| 133408 | GIR_EraseRootFromParent_Done, |
| 133409 | // Label 6314: @431594 |
| 133410 | GIM_Try, /*On fail goto*//*Label 6315*/ GIMT_Encode4(431688), // Rule ID 7417 // |
| 133411 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133412 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133413 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133414 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133415 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133416 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133417 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133418 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133419 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133420 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133421 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133422 | // MIs[3] src0 |
| 133423 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133424 | // MIs[3] src1 |
| 133425 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133426 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133427 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133430 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133431 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133432 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133433 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133434 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133435 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133436 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133438 | GIR_RootConstrainSelectedInstOperands, |
| 133439 | // GIR_Coverage, 7417, |
| 133440 | GIR_EraseRootFromParent_Done, |
| 133441 | // Label 6315: @431688 |
| 133442 | GIM_Try, /*On fail goto*//*Label 6316*/ GIMT_Encode4(431782), // Rule ID 11962 // |
| 133443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133444 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133445 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133446 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133447 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133448 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133449 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133450 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133451 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133452 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133453 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133454 | // MIs[3] src1 |
| 133455 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133456 | // MIs[3] src0 |
| 133457 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133458 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133459 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133461 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133462 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133463 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133464 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133465 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133466 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133467 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133468 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133470 | GIR_RootConstrainSelectedInstOperands, |
| 133471 | // GIR_Coverage, 11962, |
| 133472 | GIR_EraseRootFromParent_Done, |
| 133473 | // Label 6316: @431782 |
| 133474 | GIM_Try, /*On fail goto*//*Label 6317*/ GIMT_Encode4(431876), // Rule ID 11965 // |
| 133475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133476 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133477 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133478 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133479 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133480 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133481 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133482 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133483 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133484 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133485 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133486 | // MIs[3] src0 |
| 133487 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133488 | // MIs[3] src1 |
| 133489 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133490 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133491 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133493 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133494 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133495 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133496 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133497 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133499 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133500 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133502 | GIR_RootConstrainSelectedInstOperands, |
| 133503 | // GIR_Coverage, 11965, |
| 133504 | GIR_EraseRootFromParent_Done, |
| 133505 | // Label 6317: @431876 |
| 133506 | GIM_Try, /*On fail goto*//*Label 6318*/ GIMT_Encode4(431970), // Rule ID 11966 // |
| 133507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133508 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133509 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133510 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133511 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133512 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133513 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133514 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133515 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133516 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133517 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133518 | // MIs[3] src1 |
| 133519 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133520 | // MIs[3] src0 |
| 133521 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133522 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133523 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133526 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133527 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133528 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133529 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133530 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133531 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133532 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133534 | GIR_RootConstrainSelectedInstOperands, |
| 133535 | // GIR_Coverage, 11966, |
| 133536 | GIR_EraseRootFromParent_Done, |
| 133537 | // Label 6318: @431970 |
| 133538 | GIM_Try, /*On fail goto*//*Label 6319*/ GIMT_Encode4(432064), // Rule ID 11963 // |
| 133539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133540 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133541 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133542 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133543 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133544 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133545 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133546 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133547 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133548 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 133549 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133550 | // MIs[3] src0 |
| 133551 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133552 | // MIs[3] src1 |
| 133553 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133554 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133555 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133557 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133558 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133559 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133561 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133563 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 133564 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133566 | GIR_RootConstrainSelectedInstOperands, |
| 133567 | // GIR_Coverage, 11963, |
| 133568 | GIR_EraseRootFromParent_Done, |
| 133569 | // Label 6319: @432064 |
| 133570 | GIM_Try, /*On fail goto*//*Label 6320*/ GIMT_Encode4(432158), // Rule ID 11964 // |
| 133571 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133572 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133573 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133574 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133575 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133576 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133577 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133578 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133579 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133580 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 133581 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133582 | // MIs[3] src1 |
| 133583 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133584 | // MIs[3] src0 |
| 133585 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133586 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133587 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133590 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133591 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133592 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133593 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133594 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133595 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 133596 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133598 | GIR_RootConstrainSelectedInstOperands, |
| 133599 | // GIR_Coverage, 11964, |
| 133600 | GIR_EraseRootFromParent_Done, |
| 133601 | // Label 6320: @432158 |
| 133602 | GIM_Try, /*On fail goto*//*Label 6321*/ GIMT_Encode4(432252), // Rule ID 11967 // |
| 133603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133604 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133605 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133606 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133607 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133608 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133609 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133610 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133611 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133612 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 133613 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133614 | // MIs[3] src0 |
| 133615 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133616 | // MIs[3] src1 |
| 133617 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133618 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133619 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133622 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133623 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133624 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133625 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133626 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133627 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 133628 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133630 | GIR_RootConstrainSelectedInstOperands, |
| 133631 | // GIR_Coverage, 11967, |
| 133632 | GIR_EraseRootFromParent_Done, |
| 133633 | // Label 6321: @432252 |
| 133634 | GIM_Try, /*On fail goto*//*Label 6322*/ GIMT_Encode4(432346), // Rule ID 11968 // |
| 133635 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 133636 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133637 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133638 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 133639 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 133640 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133641 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133642 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 133643 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 133644 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 133645 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133646 | // MIs[3] src1 |
| 133647 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133648 | // MIs[3] src0 |
| 133649 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133650 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133651 | // (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umax:{ *:[i16] } i16:{ *:[i16] }:$src2, (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 133652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 133653 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133654 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133655 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133656 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133657 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133658 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133659 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 133660 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 133662 | GIR_RootConstrainSelectedInstOperands, |
| 133663 | // GIR_Coverage, 11968, |
| 133664 | GIR_EraseRootFromParent_Done, |
| 133665 | // Label 6322: @432346 |
| 133666 | GIM_Try, /*On fail goto*//*Label 6323*/ GIMT_Encode4(432365), // Rule ID 825 // |
| 133667 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 133668 | // (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MIN_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 133669 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_e64), |
| 133670 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 133671 | GIR_RootConstrainSelectedInstOperands, |
| 133672 | // GIR_Coverage, 825, |
| 133673 | GIR_Done, |
| 133674 | // Label 6323: @432365 |
| 133675 | GIM_Try, /*On fail goto*//*Label 6324*/ GIMT_Encode4(432384), // Rule ID 826 // |
| 133676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 133677 | // (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MIN_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 133678 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U16_t16_e64), |
| 133679 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 133680 | GIR_RootConstrainSelectedInstOperands, |
| 133681 | // GIR_Coverage, 826, |
| 133682 | GIR_Done, |
| 133683 | // Label 6324: @432384 |
| 133684 | GIM_Reject, |
| 133685 | // Label 6306: @432385 |
| 133686 | GIM_Reject, |
| 133687 | // Label 6303: @432386 |
| 133688 | GIM_Try, /*On fail goto*//*Label 6325*/ GIMT_Encode4(433830), |
| 133689 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 133690 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 133691 | GIM_Try, /*On fail goto*//*Label 6326*/ GIMT_Encode4(432477), // Rule ID 10898 // |
| 133692 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133693 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133694 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133695 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133696 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133697 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133698 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133699 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133700 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133701 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133702 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133703 | // MIs[3] src0 |
| 133704 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133705 | // MIs[3] src1 |
| 133706 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133707 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133708 | // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133711 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133712 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133713 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133714 | GIR_RootConstrainSelectedInstOperands, |
| 133715 | // GIR_Coverage, 10898, |
| 133716 | GIR_EraseRootFromParent_Done, |
| 133717 | // Label 6326: @432477 |
| 133718 | GIM_Try, /*On fail goto*//*Label 6327*/ GIMT_Encode4(432557), // Rule ID 10899 // |
| 133719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133720 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133721 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133722 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133723 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133724 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133725 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133726 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133727 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133728 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133729 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133730 | // MIs[3] src1 |
| 133731 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133732 | // MIs[3] src0 |
| 133733 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133734 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133735 | // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133737 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133738 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133739 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133740 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133741 | GIR_RootConstrainSelectedInstOperands, |
| 133742 | // GIR_Coverage, 10899, |
| 133743 | GIR_EraseRootFromParent_Done, |
| 133744 | // Label 6327: @432557 |
| 133745 | GIM_Try, /*On fail goto*//*Label 6328*/ GIMT_Encode4(432637), // Rule ID 10900 // |
| 133746 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133747 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133748 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133749 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133750 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133751 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133752 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133753 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133754 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133755 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133756 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133757 | // MIs[3] src0 |
| 133758 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133759 | // MIs[3] src1 |
| 133760 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133761 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133762 | // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133765 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133766 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133767 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133768 | GIR_RootConstrainSelectedInstOperands, |
| 133769 | // GIR_Coverage, 10900, |
| 133770 | GIR_EraseRootFromParent_Done, |
| 133771 | // Label 6328: @432637 |
| 133772 | GIM_Try, /*On fail goto*//*Label 6329*/ GIMT_Encode4(432717), // Rule ID 10901 // |
| 133773 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133774 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133775 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133776 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133777 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133778 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 133779 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133780 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133781 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133782 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133783 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133784 | // MIs[3] src1 |
| 133785 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133786 | // MIs[3] src0 |
| 133787 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133788 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133789 | // (umin:{ *:[i32] } (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133792 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133793 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133794 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 133795 | GIR_RootConstrainSelectedInstOperands, |
| 133796 | // GIR_Coverage, 10901, |
| 133797 | GIR_EraseRootFromParent_Done, |
| 133798 | // Label 6329: @432717 |
| 133799 | GIM_Try, /*On fail goto*//*Label 6330*/ GIMT_Encode4(432797), // Rule ID 10902 // |
| 133800 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133801 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133802 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133803 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133804 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133805 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133806 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133807 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133808 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133809 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133810 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133811 | // MIs[3] src0 |
| 133812 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133813 | // MIs[3] src1 |
| 133814 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133815 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133816 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133819 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133820 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133821 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133822 | GIR_RootConstrainSelectedInstOperands, |
| 133823 | // GIR_Coverage, 10902, |
| 133824 | GIR_EraseRootFromParent_Done, |
| 133825 | // Label 6330: @432797 |
| 133826 | GIM_Try, /*On fail goto*//*Label 6331*/ GIMT_Encode4(432877), // Rule ID 10903 // |
| 133827 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133828 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133829 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133830 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133831 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133832 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133833 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133834 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133835 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133836 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133837 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133838 | // MIs[3] src1 |
| 133839 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133840 | // MIs[3] src0 |
| 133841 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133842 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133843 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133846 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 133847 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 133848 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133849 | GIR_RootConstrainSelectedInstOperands, |
| 133850 | // GIR_Coverage, 10903, |
| 133851 | GIR_EraseRootFromParent_Done, |
| 133852 | // Label 6331: @432877 |
| 133853 | GIM_Try, /*On fail goto*//*Label 6332*/ GIMT_Encode4(432957), // Rule ID 10904 // |
| 133854 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133855 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133856 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133857 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133858 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133859 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133860 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133861 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133862 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133863 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133864 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133865 | // MIs[3] src0 |
| 133866 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133867 | // MIs[3] src1 |
| 133868 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133869 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133870 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133873 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133874 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133875 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133876 | GIR_RootConstrainSelectedInstOperands, |
| 133877 | // GIR_Coverage, 10904, |
| 133878 | GIR_EraseRootFromParent_Done, |
| 133879 | // Label 6332: @432957 |
| 133880 | GIM_Try, /*On fail goto*//*Label 6333*/ GIMT_Encode4(433037), // Rule ID 10905 // |
| 133881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133882 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133883 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133884 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133885 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133886 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 133887 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133888 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133889 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133890 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 133891 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133892 | // MIs[3] src1 |
| 133893 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 133894 | // MIs[3] src0 |
| 133895 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 133896 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133897 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133900 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 133901 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 133902 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 133903 | GIR_RootConstrainSelectedInstOperands, |
| 133904 | // GIR_Coverage, 10905, |
| 133905 | GIR_EraseRootFromParent_Done, |
| 133906 | // Label 6333: @433037 |
| 133907 | GIM_Try, /*On fail goto*//*Label 6334*/ GIMT_Encode4(433117), // Rule ID 7312 // |
| 133908 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133909 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133910 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133911 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133912 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133913 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133914 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133915 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133916 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133917 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133918 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133919 | // MIs[3] src0 |
| 133920 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133921 | // MIs[3] src1 |
| 133922 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133923 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133924 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133926 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133927 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133928 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133929 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133930 | GIR_RootConstrainSelectedInstOperands, |
| 133931 | // GIR_Coverage, 7312, |
| 133932 | GIR_EraseRootFromParent_Done, |
| 133933 | // Label 6334: @433117 |
| 133934 | GIM_Try, /*On fail goto*//*Label 6335*/ GIMT_Encode4(433197), // Rule ID 10891 // |
| 133935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133936 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133937 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133938 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133939 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133940 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133941 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133942 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133943 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133944 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133945 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133946 | // MIs[3] src1 |
| 133947 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133948 | // MIs[3] src0 |
| 133949 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133950 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133951 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133952 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133953 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133954 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 133955 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 133956 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133957 | GIR_RootConstrainSelectedInstOperands, |
| 133958 | // GIR_Coverage, 10891, |
| 133959 | GIR_EraseRootFromParent_Done, |
| 133960 | // Label 6335: @433197 |
| 133961 | GIM_Try, /*On fail goto*//*Label 6336*/ GIMT_Encode4(433277), // Rule ID 10894 // |
| 133962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133963 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133964 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133965 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133966 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133967 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133968 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133969 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133970 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133971 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133972 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 133973 | // MIs[3] src0 |
| 133974 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 133975 | // MIs[3] src1 |
| 133976 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 133977 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 133978 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 133979 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 133980 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 133981 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 133982 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 133983 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 133984 | GIR_RootConstrainSelectedInstOperands, |
| 133985 | // GIR_Coverage, 10894, |
| 133986 | GIR_EraseRootFromParent_Done, |
| 133987 | // Label 6336: @433277 |
| 133988 | GIM_Try, /*On fail goto*//*Label 6337*/ GIMT_Encode4(433357), // Rule ID 10895 // |
| 133989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 133990 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 133991 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133992 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 133993 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 133994 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 133995 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 133996 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 133997 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 133998 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 133999 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134000 | // MIs[3] src1 |
| 134001 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134002 | // MIs[3] src0 |
| 134003 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134004 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134005 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134008 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134009 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134010 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134011 | GIR_RootConstrainSelectedInstOperands, |
| 134012 | // GIR_Coverage, 10895, |
| 134013 | GIR_EraseRootFromParent_Done, |
| 134014 | // Label 6337: @433357 |
| 134015 | GIM_Try, /*On fail goto*//*Label 6338*/ GIMT_Encode4(433437), // Rule ID 10892 // |
| 134016 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134017 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134018 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134019 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134020 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134021 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134022 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134023 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134024 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134025 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134026 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134027 | // MIs[3] src0 |
| 134028 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134029 | // MIs[3] src1 |
| 134030 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134031 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134032 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134035 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134036 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134037 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134038 | GIR_RootConstrainSelectedInstOperands, |
| 134039 | // GIR_Coverage, 10892, |
| 134040 | GIR_EraseRootFromParent_Done, |
| 134041 | // Label 6338: @433437 |
| 134042 | GIM_Try, /*On fail goto*//*Label 6339*/ GIMT_Encode4(433517), // Rule ID 10893 // |
| 134043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134044 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134045 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134046 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134047 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134048 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134049 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134050 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134051 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134052 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134053 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134054 | // MIs[3] src1 |
| 134055 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134056 | // MIs[3] src0 |
| 134057 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134058 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134059 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134062 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134063 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134064 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134065 | GIR_RootConstrainSelectedInstOperands, |
| 134066 | // GIR_Coverage, 10893, |
| 134067 | GIR_EraseRootFromParent_Done, |
| 134068 | // Label 6339: @433517 |
| 134069 | GIM_Try, /*On fail goto*//*Label 6340*/ GIMT_Encode4(433597), // Rule ID 10896 // |
| 134070 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134071 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134072 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134073 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134074 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134075 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134076 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134077 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134078 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134079 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134080 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134081 | // MIs[3] src0 |
| 134082 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134083 | // MIs[3] src1 |
| 134084 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134085 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134086 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134089 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134090 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134091 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134092 | GIR_RootConstrainSelectedInstOperands, |
| 134093 | // GIR_Coverage, 10896, |
| 134094 | GIR_EraseRootFromParent_Done, |
| 134095 | // Label 6340: @433597 |
| 134096 | GIM_Try, /*On fail goto*//*Label 6341*/ GIMT_Encode4(433677), // Rule ID 10897 // |
| 134097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134098 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134099 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134100 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134101 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134102 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134103 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134104 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134105 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134106 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134107 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134108 | // MIs[3] src1 |
| 134109 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134110 | // MIs[3] src0 |
| 134111 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134112 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134113 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134115 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134116 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134117 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134118 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134119 | GIR_RootConstrainSelectedInstOperands, |
| 134120 | // GIR_Coverage, 10897, |
| 134121 | GIR_EraseRootFromParent_Done, |
| 134122 | // Label 6341: @433677 |
| 134123 | GIM_Try, /*On fail goto*//*Label 6342*/ GIMT_Encode4(433730), // Rule ID 7382 // |
| 134124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 134125 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134126 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134127 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134128 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134129 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134130 | GIM_CheckHasOneUse, /*MI*/1, |
| 134131 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36297), |
| 134132 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 134133 | // (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umax_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_36297>> => (V_MAXMIN_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_U32_e64), |
| 134135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134136 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134137 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134138 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 134139 | GIR_RootConstrainSelectedInstOperands, |
| 134140 | // GIR_Coverage, 7382, |
| 134141 | GIR_EraseRootFromParent_Done, |
| 134142 | // Label 6342: @433730 |
| 134143 | GIM_Try, /*On fail goto*//*Label 6343*/ GIMT_Encode4(433783), // Rule ID 11913 // |
| 134144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 134145 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134146 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 134147 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134148 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134149 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134150 | GIM_CheckHasOneUse, /*MI*/1, |
| 134151 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36297), |
| 134152 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 134153 | // (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umax_oneuse>>)<<P:Predicate_anonymous_36297>> => (V_MAXMIN_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAXMIN_U32_e64), |
| 134155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134158 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 134159 | GIR_RootConstrainSelectedInstOperands, |
| 134160 | // GIR_Coverage, 11913, |
| 134161 | GIR_EraseRootFromParent_Done, |
| 134162 | // Label 6343: @433783 |
| 134163 | GIM_Try, /*On fail goto*//*Label 6344*/ GIMT_Encode4(433809), // Rule ID 50 // |
| 134164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 134165 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18502), |
| 134166 | // (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18502>> => (S_MIN_U32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 134167 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MIN_U32), |
| 134168 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 134169 | GIR_RootConstrainSelectedInstOperands, |
| 134170 | // GIR_Coverage, 50, |
| 134171 | GIR_Done, |
| 134172 | // Label 6344: @433809 |
| 134173 | GIM_Try, /*On fail goto*//*Label 6345*/ GIMT_Encode4(433829), // Rule ID 743 // |
| 134174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134175 | // (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MIN_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 134176 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_U32_e64), |
| 134177 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 134178 | GIR_RootConstrainSelectedInstOperands, |
| 134179 | // GIR_Coverage, 743, |
| 134180 | GIR_Done, |
| 134181 | // Label 6345: @433829 |
| 134182 | GIM_Reject, |
| 134183 | // Label 6325: @433830 |
| 134184 | GIM_Reject, |
| 134185 | // Label 6304: @433831 |
| 134186 | GIM_Try, /*On fail goto*//*Label 6346*/ GIMT_Encode4(433902), // Rule ID 968 // |
| 134187 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 134188 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 134189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134190 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 134191 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 134192 | // (umin:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MIN_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 134193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MIN_U16), |
| 134194 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134195 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 134196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 134197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 134198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 134199 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134200 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134201 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134202 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134203 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134204 | GIR_RootConstrainSelectedInstOperands, |
| 134205 | // GIR_Coverage, 968, |
| 134206 | GIR_EraseRootFromParent_Done, |
| 134207 | // Label 6346: @433902 |
| 134208 | GIM_Reject, |
| 134209 | // Label 6305: @433903 |
| 134210 | GIM_Reject, |
| 134211 | // Label 91: @433904 |
| 134212 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6350*/ GIMT_Encode4(437007), |
| 134213 | /*GILLT_s16*//*Label 6347*/ GIMT_Encode4(433931), |
| 134214 | /*GILLT_s32*//*Label 6348*/ GIMT_Encode4(435490), GIMT_Encode4(0), |
| 134215 | /*GILLT_v2s16*//*Label 6349*/ GIMT_Encode4(436935), |
| 134216 | // Label 6347: @433931 |
| 134217 | GIM_Try, /*On fail goto*//*Label 6351*/ GIMT_Encode4(435489), |
| 134218 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 134219 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 134220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134221 | GIM_Try, /*On fail goto*//*Label 6352*/ GIMT_Encode4(434040), // Rule ID 11954 // |
| 134222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134223 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134224 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134225 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134226 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134227 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134228 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134229 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134230 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134231 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134232 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134233 | // MIs[3] src0 |
| 134234 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134235 | // MIs[3] src1 |
| 134236 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134237 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134238 | // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134241 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134242 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134243 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134244 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134246 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134249 | GIR_RootConstrainSelectedInstOperands, |
| 134250 | // GIR_Coverage, 11954, |
| 134251 | GIR_EraseRootFromParent_Done, |
| 134252 | // Label 6352: @434040 |
| 134253 | GIM_Try, /*On fail goto*//*Label 6353*/ GIMT_Encode4(434134), // Rule ID 11955 // |
| 134254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134255 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134256 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134257 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134258 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134259 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134260 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134261 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134262 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134263 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134264 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134265 | // MIs[3] src1 |
| 134266 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134267 | // MIs[3] src0 |
| 134268 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134269 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134270 | // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134273 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134274 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134275 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134276 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134277 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134278 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134279 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134280 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134281 | GIR_RootConstrainSelectedInstOperands, |
| 134282 | // GIR_Coverage, 11955, |
| 134283 | GIR_EraseRootFromParent_Done, |
| 134284 | // Label 6353: @434134 |
| 134285 | GIM_Try, /*On fail goto*//*Label 6354*/ GIMT_Encode4(434228), // Rule ID 11956 // |
| 134286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134287 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134288 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134289 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134290 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134291 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134292 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134293 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134294 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134295 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134296 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134297 | // MIs[3] src0 |
| 134298 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134299 | // MIs[3] src1 |
| 134300 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134301 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134302 | // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134303 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134304 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134305 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134306 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134307 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134308 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134309 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134310 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134311 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134312 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134313 | GIR_RootConstrainSelectedInstOperands, |
| 134314 | // GIR_Coverage, 11956, |
| 134315 | GIR_EraseRootFromParent_Done, |
| 134316 | // Label 6354: @434228 |
| 134317 | GIM_Try, /*On fail goto*//*Label 6355*/ GIMT_Encode4(434322), // Rule ID 11957 // |
| 134318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134319 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134320 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134321 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134322 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134323 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134324 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134325 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134326 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134327 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134328 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134329 | // MIs[3] src1 |
| 134330 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134331 | // MIs[3] src0 |
| 134332 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134333 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134334 | // (umax:{ *:[i16] } (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134336 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134337 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134338 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134339 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134340 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134341 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134342 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134343 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134344 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134345 | GIR_RootConstrainSelectedInstOperands, |
| 134346 | // GIR_Coverage, 11957, |
| 134347 | GIR_EraseRootFromParent_Done, |
| 134348 | // Label 6355: @434322 |
| 134349 | GIM_Try, /*On fail goto*//*Label 6356*/ GIMT_Encode4(434416), // Rule ID 11958 // |
| 134350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134351 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134352 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134353 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134354 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134355 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134356 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134357 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134358 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134359 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134360 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134361 | // MIs[3] src0 |
| 134362 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134363 | // MIs[3] src1 |
| 134364 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134365 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134366 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134367 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134368 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134369 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134370 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134371 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134372 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134373 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134374 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134375 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134376 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134377 | GIR_RootConstrainSelectedInstOperands, |
| 134378 | // GIR_Coverage, 11958, |
| 134379 | GIR_EraseRootFromParent_Done, |
| 134380 | // Label 6356: @434416 |
| 134381 | GIM_Try, /*On fail goto*//*Label 6357*/ GIMT_Encode4(434510), // Rule ID 11959 // |
| 134382 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134383 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134384 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134385 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134386 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134387 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134388 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134389 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134390 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134391 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134392 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134393 | // MIs[3] src1 |
| 134394 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134395 | // MIs[3] src0 |
| 134396 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134397 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134398 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134399 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134400 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134401 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134402 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134403 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134404 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134405 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134406 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134407 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134408 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134409 | GIR_RootConstrainSelectedInstOperands, |
| 134410 | // GIR_Coverage, 11959, |
| 134411 | GIR_EraseRootFromParent_Done, |
| 134412 | // Label 6357: @434510 |
| 134413 | GIM_Try, /*On fail goto*//*Label 6358*/ GIMT_Encode4(434604), // Rule ID 11960 // |
| 134414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134415 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134416 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134417 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134418 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134419 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134420 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134421 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134422 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134423 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134424 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134425 | // MIs[3] src0 |
| 134426 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134427 | // MIs[3] src1 |
| 134428 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134429 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134430 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134431 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134432 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134433 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134434 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134435 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134436 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134437 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134438 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134439 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134440 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134441 | GIR_RootConstrainSelectedInstOperands, |
| 134442 | // GIR_Coverage, 11960, |
| 134443 | GIR_EraseRootFromParent_Done, |
| 134444 | // Label 6358: @434604 |
| 134445 | GIM_Try, /*On fail goto*//*Label 6359*/ GIMT_Encode4(434698), // Rule ID 11961 // |
| 134446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134447 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134448 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134449 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134450 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134451 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134452 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134453 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134454 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134455 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134456 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134457 | // MIs[3] src1 |
| 134458 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134459 | // MIs[3] src0 |
| 134460 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134461 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134462 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)), (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134465 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134466 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134467 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134468 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134469 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134470 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134471 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134472 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134473 | GIR_RootConstrainSelectedInstOperands, |
| 134474 | // GIR_Coverage, 11961, |
| 134475 | GIR_EraseRootFromParent_Done, |
| 134476 | // Label 6359: @434698 |
| 134477 | GIM_Try, /*On fail goto*//*Label 6360*/ GIMT_Encode4(434792), // Rule ID 7416 // |
| 134478 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134479 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134480 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134481 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134482 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134483 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134484 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134485 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134486 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134487 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 134488 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134489 | // MIs[3] src0 |
| 134490 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134491 | // MIs[3] src1 |
| 134492 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134493 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134494 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134497 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134498 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134499 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134500 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134501 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134502 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134503 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134504 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134505 | GIR_RootConstrainSelectedInstOperands, |
| 134506 | // GIR_Coverage, 7416, |
| 134507 | GIR_EraseRootFromParent_Done, |
| 134508 | // Label 6360: @434792 |
| 134509 | GIM_Try, /*On fail goto*//*Label 6361*/ GIMT_Encode4(434886), // Rule ID 11947 // |
| 134510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134511 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134512 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134513 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134514 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134515 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134516 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134517 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134518 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134519 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 134520 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134521 | // MIs[3] src1 |
| 134522 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134523 | // MIs[3] src0 |
| 134524 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134525 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134526 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134529 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134530 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134531 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134532 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134533 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134534 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134537 | GIR_RootConstrainSelectedInstOperands, |
| 134538 | // GIR_Coverage, 11947, |
| 134539 | GIR_EraseRootFromParent_Done, |
| 134540 | // Label 6361: @434886 |
| 134541 | GIM_Try, /*On fail goto*//*Label 6362*/ GIMT_Encode4(434980), // Rule ID 11950 // |
| 134542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134543 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134544 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134545 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134546 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134547 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134548 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134549 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134550 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134551 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 134552 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134553 | // MIs[3] src0 |
| 134554 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134555 | // MIs[3] src1 |
| 134556 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134557 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134558 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134562 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134564 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134565 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134566 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134567 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134568 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134569 | GIR_RootConstrainSelectedInstOperands, |
| 134570 | // GIR_Coverage, 11950, |
| 134571 | GIR_EraseRootFromParent_Done, |
| 134572 | // Label 6362: @434980 |
| 134573 | GIM_Try, /*On fail goto*//*Label 6363*/ GIMT_Encode4(435074), // Rule ID 11951 // |
| 134574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134575 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134576 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134577 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134578 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134579 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134580 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134581 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134582 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134583 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 134584 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134585 | // MIs[3] src1 |
| 134586 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134587 | // MIs[3] src0 |
| 134588 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134589 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134590 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), i16:{ *:[i16] }:$src2)) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134593 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134594 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134595 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134596 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134597 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134598 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134599 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134600 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134601 | GIR_RootConstrainSelectedInstOperands, |
| 134602 | // GIR_Coverage, 11951, |
| 134603 | GIR_EraseRootFromParent_Done, |
| 134604 | // Label 6363: @435074 |
| 134605 | GIM_Try, /*On fail goto*//*Label 6364*/ GIMT_Encode4(435168), // Rule ID 11948 // |
| 134606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134607 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134608 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134609 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134610 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134611 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134612 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134613 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134614 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134615 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134616 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134617 | // MIs[3] src0 |
| 134618 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134619 | // MIs[3] src1 |
| 134620 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134621 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134622 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134625 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134626 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134627 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134628 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134629 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134630 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134631 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134632 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134633 | GIR_RootConstrainSelectedInstOperands, |
| 134634 | // GIR_Coverage, 11948, |
| 134635 | GIR_EraseRootFromParent_Done, |
| 134636 | // Label 6364: @435168 |
| 134637 | GIM_Try, /*On fail goto*//*Label 6365*/ GIMT_Encode4(435262), // Rule ID 11949 // |
| 134638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134639 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134640 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134641 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134642 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134643 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134644 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134645 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134646 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134647 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134648 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134649 | // MIs[3] src1 |
| 134650 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134651 | // MIs[3] src0 |
| 134652 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134653 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134654 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134657 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134658 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134659 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134660 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134661 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134662 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134663 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134664 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134665 | GIR_RootConstrainSelectedInstOperands, |
| 134666 | // GIR_Coverage, 11949, |
| 134667 | GIR_EraseRootFromParent_Done, |
| 134668 | // Label 6365: @435262 |
| 134669 | GIM_Try, /*On fail goto*//*Label 6366*/ GIMT_Encode4(435356), // Rule ID 11952 // |
| 134670 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134671 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134672 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134673 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134674 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134675 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134676 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134677 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134678 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134679 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134680 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134681 | // MIs[3] src0 |
| 134682 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134683 | // MIs[3] src1 |
| 134684 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134685 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134686 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134689 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134690 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134691 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134692 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134693 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134694 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134695 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134696 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134697 | GIR_RootConstrainSelectedInstOperands, |
| 134698 | // GIR_Coverage, 11952, |
| 134699 | GIR_EraseRootFromParent_Done, |
| 134700 | // Label 6366: @435356 |
| 134701 | GIM_Try, /*On fail goto*//*Label 6367*/ GIMT_Encode4(435450), // Rule ID 11953 // |
| 134702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 134703 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134704 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134705 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 134706 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 134707 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134708 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134709 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s16, |
| 134710 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s16, |
| 134711 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 134712 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134713 | // MIs[3] src1 |
| 134714 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134715 | // MIs[3] src0 |
| 134716 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134717 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134718 | // (umax:{ *:[i16] } (umin:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0), (umin:{ *:[i16] } i16:{ *:[i16] }:$src2, (umax:{ *:[i16] } i16:{ *:[i16] }:$src1, i16:{ *:[i16] }:$src0))) => (V_MED3_U16_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src0, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src1, 0:{ *:[i32] }, VSrc_b16:{ *:[i16] }:$src2, 0:{ *:[i1] }) |
| 134719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 134720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134721 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134722 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 134723 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134724 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 134725 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134726 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 134727 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134728 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 134729 | GIR_RootConstrainSelectedInstOperands, |
| 134730 | // GIR_Coverage, 11953, |
| 134731 | GIR_EraseRootFromParent_Done, |
| 134732 | // Label 6367: @435450 |
| 134733 | GIM_Try, /*On fail goto*//*Label 6368*/ GIMT_Encode4(435469), // Rule ID 821 // |
| 134734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 134735 | // (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MAX_U16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 134736 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_e64), |
| 134737 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 134738 | GIR_RootConstrainSelectedInstOperands, |
| 134739 | // GIR_Coverage, 821, |
| 134740 | GIR_Done, |
| 134741 | // Label 6368: @435469 |
| 134742 | GIM_Try, /*On fail goto*//*Label 6369*/ GIMT_Encode4(435488), // Rule ID 822 // |
| 134743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 134744 | // (umax:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) => (V_MAX_U16_t16_e64:{ *:[i16] } i16:{ *:[i16] }:$src0, i16:{ *:[i16] }:$src1) |
| 134745 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U16_t16_e64), |
| 134746 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 134747 | GIR_RootConstrainSelectedInstOperands, |
| 134748 | // GIR_Coverage, 822, |
| 134749 | GIR_Done, |
| 134750 | // Label 6369: @435488 |
| 134751 | GIM_Reject, |
| 134752 | // Label 6351: @435489 |
| 134753 | GIM_Reject, |
| 134754 | // Label 6348: @435490 |
| 134755 | GIM_Try, /*On fail goto*//*Label 6370*/ GIMT_Encode4(436934), |
| 134756 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 134757 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 134758 | GIM_Try, /*On fail goto*//*Label 6371*/ GIMT_Encode4(435581), // Rule ID 10913 // |
| 134759 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134760 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134761 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134762 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134763 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134764 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134765 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134766 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134767 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134768 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134769 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134770 | // MIs[3] src0 |
| 134771 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134772 | // MIs[3] src1 |
| 134773 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134774 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134775 | // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134778 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134779 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134780 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134781 | GIR_RootConstrainSelectedInstOperands, |
| 134782 | // GIR_Coverage, 10913, |
| 134783 | GIR_EraseRootFromParent_Done, |
| 134784 | // Label 6371: @435581 |
| 134785 | GIM_Try, /*On fail goto*//*Label 6372*/ GIMT_Encode4(435661), // Rule ID 10914 // |
| 134786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134787 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134788 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134789 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134790 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134791 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134792 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134793 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134794 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134795 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134796 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134797 | // MIs[3] src1 |
| 134798 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134799 | // MIs[3] src0 |
| 134800 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134801 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134802 | // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134803 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134804 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134805 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134806 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134807 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134808 | GIR_RootConstrainSelectedInstOperands, |
| 134809 | // GIR_Coverage, 10914, |
| 134810 | GIR_EraseRootFromParent_Done, |
| 134811 | // Label 6372: @435661 |
| 134812 | GIM_Try, /*On fail goto*//*Label 6373*/ GIMT_Encode4(435741), // Rule ID 10915 // |
| 134813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134814 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134815 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134816 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134817 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134818 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134819 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134820 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134821 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134822 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134823 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134824 | // MIs[3] src0 |
| 134825 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134826 | // MIs[3] src1 |
| 134827 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134828 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134829 | // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134831 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134832 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134833 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134834 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134835 | GIR_RootConstrainSelectedInstOperands, |
| 134836 | // GIR_Coverage, 10915, |
| 134837 | GIR_EraseRootFromParent_Done, |
| 134838 | // Label 6373: @435741 |
| 134839 | GIM_Try, /*On fail goto*//*Label 6374*/ GIMT_Encode4(435821), // Rule ID 10916 // |
| 134840 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134841 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134842 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134843 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134844 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134845 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 134846 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134847 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134848 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134849 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134850 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134851 | // MIs[3] src1 |
| 134852 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134853 | // MIs[3] src0 |
| 134854 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134855 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134856 | // (umax:{ *:[i32] } (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134859 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134860 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134861 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src2 |
| 134862 | GIR_RootConstrainSelectedInstOperands, |
| 134863 | // GIR_Coverage, 10916, |
| 134864 | GIR_EraseRootFromParent_Done, |
| 134865 | // Label 6374: @435821 |
| 134866 | GIM_Try, /*On fail goto*//*Label 6375*/ GIMT_Encode4(435901), // Rule ID 10917 // |
| 134867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134868 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134869 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134870 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134871 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134872 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134873 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134874 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134875 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134876 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134877 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134878 | // MIs[3] src0 |
| 134879 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134880 | // MIs[3] src1 |
| 134881 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134882 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134883 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134885 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134886 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134887 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134888 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134889 | GIR_RootConstrainSelectedInstOperands, |
| 134890 | // GIR_Coverage, 10917, |
| 134891 | GIR_EraseRootFromParent_Done, |
| 134892 | // Label 6375: @435901 |
| 134893 | GIM_Try, /*On fail goto*//*Label 6376*/ GIMT_Encode4(435981), // Rule ID 10918 // |
| 134894 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134895 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134896 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134897 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134898 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134899 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134900 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134901 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134902 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134903 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134904 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134905 | // MIs[3] src1 |
| 134906 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134907 | // MIs[3] src0 |
| 134908 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134909 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134910 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134911 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134912 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134913 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 134914 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src1 |
| 134915 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134916 | GIR_RootConstrainSelectedInstOperands, |
| 134917 | // GIR_Coverage, 10918, |
| 134918 | GIR_EraseRootFromParent_Done, |
| 134919 | // Label 6376: @435981 |
| 134920 | GIM_Try, /*On fail goto*//*Label 6377*/ GIMT_Encode4(436061), // Rule ID 10919 // |
| 134921 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134922 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134923 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134924 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134925 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134926 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134927 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134928 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134929 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134930 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134931 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134932 | // MIs[3] src0 |
| 134933 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134934 | // MIs[3] src1 |
| 134935 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134936 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134937 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134940 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134941 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134942 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134943 | GIR_RootConstrainSelectedInstOperands, |
| 134944 | // GIR_Coverage, 10919, |
| 134945 | GIR_EraseRootFromParent_Done, |
| 134946 | // Label 6377: @436061 |
| 134947 | GIM_Try, /*On fail goto*//*Label 6378*/ GIMT_Encode4(436141), // Rule ID 10920 // |
| 134948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134949 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134950 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134951 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134952 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134953 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/2, // MIs[2] |
| 134954 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134955 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134956 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134957 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/0, /*OpIdx*/2, // MIs[3] |
| 134958 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134959 | // MIs[3] src1 |
| 134960 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/2, /*OtherOpIdx*/1, |
| 134961 | // MIs[3] src0 |
| 134962 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/2, /*OtherOpIdx*/2, |
| 134963 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134964 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)), (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134967 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src0 |
| 134968 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src1 |
| 134969 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src2 |
| 134970 | GIR_RootConstrainSelectedInstOperands, |
| 134971 | // GIR_Coverage, 10920, |
| 134972 | GIR_EraseRootFromParent_Done, |
| 134973 | // Label 6378: @436141 |
| 134974 | GIM_Try, /*On fail goto*//*Label 6379*/ GIMT_Encode4(436221), // Rule ID 7313 // |
| 134975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 134976 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 134977 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134978 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 134979 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 134980 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 134981 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 134982 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 134983 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 134984 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 134985 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 134986 | // MIs[3] src0 |
| 134987 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 134988 | // MIs[3] src1 |
| 134989 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 134990 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 134991 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 134992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 134993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 134994 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 134995 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 134996 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 134997 | GIR_RootConstrainSelectedInstOperands, |
| 134998 | // GIR_Coverage, 7313, |
| 134999 | GIR_EraseRootFromParent_Done, |
| 135000 | // Label 6379: @436221 |
| 135001 | GIM_Try, /*On fail goto*//*Label 6380*/ GIMT_Encode4(436301), // Rule ID 10906 // |
| 135002 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135003 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135004 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135005 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135006 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135007 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135008 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135009 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135010 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135011 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 135012 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135013 | // MIs[3] src1 |
| 135014 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135015 | // MIs[3] src0 |
| 135016 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135017 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135018 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135019 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135020 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135021 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 135022 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 135023 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 135024 | GIR_RootConstrainSelectedInstOperands, |
| 135025 | // GIR_Coverage, 10906, |
| 135026 | GIR_EraseRootFromParent_Done, |
| 135027 | // Label 6380: @436301 |
| 135028 | GIM_Try, /*On fail goto*//*Label 6381*/ GIMT_Encode4(436381), // Rule ID 10909 // |
| 135029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135030 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135031 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135032 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135033 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135034 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135035 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135036 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135037 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135038 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 135039 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135040 | // MIs[3] src0 |
| 135041 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135042 | // MIs[3] src1 |
| 135043 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135044 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135045 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135048 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 135049 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 135050 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 135051 | GIR_RootConstrainSelectedInstOperands, |
| 135052 | // GIR_Coverage, 10909, |
| 135053 | GIR_EraseRootFromParent_Done, |
| 135054 | // Label 6381: @436381 |
| 135055 | GIM_Try, /*On fail goto*//*Label 6382*/ GIMT_Encode4(436461), // Rule ID 10910 // |
| 135056 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135057 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135058 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135059 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135060 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135061 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135062 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135063 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135064 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135065 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 135066 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135067 | // MIs[3] src1 |
| 135068 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135069 | // MIs[3] src0 |
| 135070 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135071 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135072 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src2)) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135074 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135075 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 135076 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 135077 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/2, // src2 |
| 135078 | GIR_RootConstrainSelectedInstOperands, |
| 135079 | // GIR_Coverage, 10910, |
| 135080 | GIR_EraseRootFromParent_Done, |
| 135081 | // Label 6382: @436461 |
| 135082 | GIM_Try, /*On fail goto*//*Label 6383*/ GIMT_Encode4(436541), // Rule ID 10907 // |
| 135083 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135084 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135085 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135086 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135087 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135088 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135089 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135090 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135091 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135092 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 135093 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135094 | // MIs[3] src0 |
| 135095 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135096 | // MIs[3] src1 |
| 135097 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135098 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135099 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135100 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135101 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135102 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 135103 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 135104 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 135105 | GIR_RootConstrainSelectedInstOperands, |
| 135106 | // GIR_Coverage, 10907, |
| 135107 | GIR_EraseRootFromParent_Done, |
| 135108 | // Label 6383: @436541 |
| 135109 | GIM_Try, /*On fail goto*//*Label 6384*/ GIMT_Encode4(436621), // Rule ID 10908 // |
| 135110 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135111 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135112 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135113 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135114 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135115 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135116 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135117 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135118 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135119 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 135120 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135121 | // MIs[3] src1 |
| 135122 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135123 | // MIs[3] src0 |
| 135124 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135125 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135126 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135129 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 135130 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 135131 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 135132 | GIR_RootConstrainSelectedInstOperands, |
| 135133 | // GIR_Coverage, 10908, |
| 135134 | GIR_EraseRootFromParent_Done, |
| 135135 | // Label 6384: @436621 |
| 135136 | GIM_Try, /*On fail goto*//*Label 6385*/ GIMT_Encode4(436701), // Rule ID 10911 // |
| 135137 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135138 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135139 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135140 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135141 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135142 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135143 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135144 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135145 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135146 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 135147 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135148 | // MIs[3] src0 |
| 135149 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135150 | // MIs[3] src1 |
| 135151 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135152 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135153 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135155 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135156 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 135157 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 135158 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 135159 | GIR_RootConstrainSelectedInstOperands, |
| 135160 | // GIR_Coverage, 10911, |
| 135161 | GIR_EraseRootFromParent_Done, |
| 135162 | // Label 6385: @436701 |
| 135163 | GIM_Try, /*On fail goto*//*Label 6386*/ GIMT_Encode4(436781), // Rule ID 10912 // |
| 135164 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135165 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135166 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135167 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135168 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135169 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 135170 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135171 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 135172 | GIM_CheckType, /*MI*/2, /*Op*/2, /*Type*/GILLT_s32, |
| 135173 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/2, // MIs[3] |
| 135174 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_UMAX), |
| 135175 | // MIs[3] src1 |
| 135176 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/1, /*OtherMI*/1, /*OtherOpIdx*/1, |
| 135177 | // MIs[3] src0 |
| 135178 | GIM_CheckIsSameOperand, /*MI*/3, /*OpIdx*/2, /*OtherMI*/1, /*OtherOpIdx*/2, |
| 135179 | GIM_CheckIsSafeToFold, /*NumInsns*/3, |
| 135180 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0), (umin:{ *:[i32] } i32:{ *:[i32] }:$src2, (umax:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src0))) => (V_MED3_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135181 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 135182 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135183 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src0 |
| 135184 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src1 |
| 135185 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src2 |
| 135186 | GIR_RootConstrainSelectedInstOperands, |
| 135187 | // GIR_Coverage, 10912, |
| 135188 | GIR_EraseRootFromParent_Done, |
| 135189 | // Label 6386: @436781 |
| 135190 | GIM_Try, /*On fail goto*//*Label 6387*/ GIMT_Encode4(436834), // Rule ID 7383 // |
| 135191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 135192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135193 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 135194 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135195 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135196 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135197 | GIM_CheckHasOneUse, /*MI*/1, |
| 135198 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36299), |
| 135199 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 135200 | // (umax:{ *:[i32] } (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umin_oneuse>>, i32:{ *:[i32] }:$src2)<<P:Predicate_anonymous_36299>> => (V_MINMAX_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_U32_e64), |
| 135202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135203 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 135204 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 135205 | GIR_RootToRootCopy, /*OpIdx*/2, // src2 |
| 135206 | GIR_RootConstrainSelectedInstOperands, |
| 135207 | // GIR_Coverage, 7383, |
| 135208 | GIR_EraseRootFromParent_Done, |
| 135209 | // Label 6387: @436834 |
| 135210 | GIM_Try, /*On fail goto*//*Label 6388*/ GIMT_Encode4(436887), // Rule ID 11914 // |
| 135211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX11Plus), |
| 135212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135213 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 135214 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_UMIN), |
| 135215 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s32, |
| 135216 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s32, |
| 135217 | GIM_CheckHasOneUse, /*MI*/1, |
| 135218 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36299), |
| 135219 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 135220 | // (umax:{ *:[i32] } i32:{ *:[i32] }:$src2, (umin:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_umin_oneuse>>)<<P:Predicate_anonymous_36299>> => (V_MINMAX_U32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$src0, VSrc_b32:{ *:[i32] }:$src1, VSrc_b32:{ *:[i32] }:$src2) |
| 135221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MINMAX_U32_e64), |
| 135222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135223 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 135224 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/2, // src1 |
| 135225 | GIR_RootToRootCopy, /*OpIdx*/1, // src2 |
| 135226 | GIR_RootConstrainSelectedInstOperands, |
| 135227 | // GIR_Coverage, 11914, |
| 135228 | GIR_EraseRootFromParent_Done, |
| 135229 | // Label 6388: @436887 |
| 135230 | GIM_Try, /*On fail goto*//*Label 6389*/ GIMT_Encode4(436913), // Rule ID 52 // |
| 135231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135232 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18504), |
| 135233 | // (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1)<<P:Predicate_anonymous_18504>> => (S_MAX_U32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 135234 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MAX_U32), |
| 135235 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 135236 | GIR_RootConstrainSelectedInstOperands, |
| 135237 | // GIR_Coverage, 52, |
| 135238 | GIR_Done, |
| 135239 | // Label 6389: @436913 |
| 135240 | GIM_Try, /*On fail goto*//*Label 6390*/ GIMT_Encode4(436933), // Rule ID 744 // |
| 135241 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135242 | // (umax:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_MAX_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 135243 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_U32_e64), |
| 135244 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 135245 | GIR_RootConstrainSelectedInstOperands, |
| 135246 | // GIR_Coverage, 744, |
| 135247 | GIR_Done, |
| 135248 | // Label 6390: @436933 |
| 135249 | GIM_Reject, |
| 135250 | // Label 6370: @436934 |
| 135251 | GIM_Reject, |
| 135252 | // Label 6349: @436935 |
| 135253 | GIM_Try, /*On fail goto*//*Label 6391*/ GIMT_Encode4(437006), // Rule ID 970 // |
| 135254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 135255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 135256 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 135258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 135259 | // (umax:{ *:[v2i16] } (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MAX_U16:{ *:[v2i16] } i32:{ *:[i32] }:$src0_modifiers, v2i16:{ *:[v2i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2i16:{ *:[v2i16] }:$src1) |
| 135260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_U16), |
| 135261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 135265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 135266 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135267 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135268 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135269 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135270 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135271 | GIR_RootConstrainSelectedInstOperands, |
| 135272 | // GIR_Coverage, 970, |
| 135273 | GIR_EraseRootFromParent_Done, |
| 135274 | // Label 6391: @437006 |
| 135275 | GIM_Reject, |
| 135276 | // Label 6350: @437007 |
| 135277 | GIM_Reject, |
| 135278 | // Label 92: @437008 |
| 135279 | GIM_Try, /*On fail goto*//*Label 6392*/ GIMT_Encode4(437144), |
| 135280 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 135281 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135282 | GIM_Try, /*On fail goto*//*Label 6393*/ GIMT_Encode4(437068), // Rule ID 7188 // |
| 135283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAddNoCarryInsts), |
| 135284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135285 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36140), |
| 135286 | // (abs:{ *:[i32] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_36140>> => (V_MAX_I32_e64:{ *:[i32] } (V_SUB_U32_e32:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src), ?:{ *:[i32] }:$src) |
| 135287 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135288 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_U32_e32), |
| 135289 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135290 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 135291 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 135292 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64), |
| 135294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135295 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135296 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 135297 | GIR_RootConstrainSelectedInstOperands, |
| 135298 | // GIR_Coverage, 7188, |
| 135299 | GIR_EraseRootFromParent_Done, |
| 135300 | // Label 6393: @437068 |
| 135301 | GIM_Try, /*On fail goto*//*Label 6394*/ GIMT_Encode4(437094), // Rule ID 23 // |
| 135302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135303 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18486), |
| 135304 | // (abs:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18486>> => (S_ABS_I32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0) |
| 135305 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ABS_I32), |
| 135306 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 135307 | GIR_RootConstrainSelectedInstOperands, |
| 135308 | // GIR_Coverage, 23, |
| 135309 | GIR_Done, |
| 135310 | // Label 6394: @437094 |
| 135311 | GIM_Try, /*On fail goto*//*Label 6395*/ GIMT_Encode4(437143), // Rule ID 7187 // |
| 135312 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135313 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_36140), |
| 135314 | // (abs:{ *:[i32] } i32:{ *:[i32] }:$src)<<P:Predicate_anonymous_36140>> => (V_MAX_I32_e64:{ *:[i32] } (V_SUB_CO_U32_e32:{ *:[i16] } 0:{ *:[i32] }, ?:{ *:[i32] }:$src), ?:{ *:[i32] }:$src) |
| 135315 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135316 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_CO_U32_e32), |
| 135317 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135318 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 135319 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 135320 | GIR_SetImplicitDefDead, /*InsnID*/1, /*OpIdx for AMDGPU::VCC*/0, |
| 135321 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_I32_e64), |
| 135323 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135324 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135325 | GIR_RootToRootCopy, /*OpIdx*/1, // src |
| 135326 | GIR_RootConstrainSelectedInstOperands, |
| 135327 | // GIR_Coverage, 7187, |
| 135328 | GIR_EraseRootFromParent_Done, |
| 135329 | // Label 6395: @437143 |
| 135330 | GIM_Reject, |
| 135331 | // Label 6392: @437144 |
| 135332 | GIM_Reject, |
| 135333 | // Label 93: @437145 |
| 135334 | GIM_Try, /*On fail goto*//*Label 6396*/ GIMT_Encode4(437178), |
| 135335 | GIM_CheckIsMBB, /*MI*/0, /*Op*/0, |
| 135336 | GIM_Try, /*On fail goto*//*Label 6397*/ GIMT_Encode4(437165), // Rule ID 181 // |
| 135337 | // (br (bb:{ *:[Other] }):$simm16) => (S_BRANCH (bb:{ *:[Other] }):$simm16) |
| 135338 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BRANCH), |
| 135339 | GIR_RootConstrainSelectedInstOperands, |
| 135340 | // GIR_Coverage, 181, |
| 135341 | GIR_Done, |
| 135342 | // Label 6397: @437165 |
| 135343 | GIM_Try, /*On fail goto*//*Label 6398*/ GIMT_Encode4(437177), // Rule ID 182 // |
| 135344 | // (br (bb:{ *:[Other] }):$simm16) => (S_BRANCH_pad_s_nop (bb:{ *:[Other] }):$simm16) |
| 135345 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BRANCH_pad_s_nop), |
| 135346 | GIR_RootConstrainSelectedInstOperands, |
| 135347 | // GIR_Coverage, 182, |
| 135348 | GIR_Done, |
| 135349 | // Label 6398: @437177 |
| 135350 | GIM_Reject, |
| 135351 | // Label 6396: @437178 |
| 135352 | GIM_Reject, |
| 135353 | // Label 94: @437179 |
| 135354 | GIM_Try, /*On fail goto*//*Label 6399*/ GIMT_Encode4(437277), |
| 135355 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 135356 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6402*/ GIMT_Encode4(437276), |
| 135357 | /*GILLT_s32*//*Label 6400*/ GIMT_Encode4(437206), |
| 135358 | /*GILLT_s64*//*Label 6401*/ GIMT_Encode4(437255), |
| 135359 | // Label 6400: @437206 |
| 135360 | GIM_Try, /*On fail goto*//*Label 6403*/ GIMT_Encode4(437226), // Rule ID 10 // |
| 135361 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135362 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18481), |
| 135363 | // (cttz_zero_undef:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18481>> => (S_FF1_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135364 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B32), |
| 135365 | GIR_RootConstrainSelectedInstOperands, |
| 135366 | // GIR_Coverage, 10, |
| 135367 | GIR_Done, |
| 135368 | // Label 6403: @437226 |
| 135369 | GIM_Try, /*On fail goto*//*Label 6404*/ GIMT_Encode4(437254), // Rule ID 626 // |
| 135370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135372 | // (cttz_zero_undef:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_FFBL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135373 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBL_B32_e64), |
| 135374 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135376 | GIR_RootConstrainSelectedInstOperands, |
| 135377 | // GIR_Coverage, 626, |
| 135378 | GIR_EraseRootFromParent_Done, |
| 135379 | // Label 6404: @437254 |
| 135380 | GIM_Reject, |
| 135381 | // Label 6401: @437255 |
| 135382 | GIM_Try, /*On fail goto*//*Label 6405*/ GIMT_Encode4(437275), // Rule ID 8 // |
| 135383 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135384 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18481), |
| 135385 | // (cttz_zero_undef:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18481>> => (S_FF1_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0) |
| 135386 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B64), |
| 135387 | GIR_RootConstrainSelectedInstOperands, |
| 135388 | // GIR_Coverage, 8, |
| 135389 | GIR_Done, |
| 135390 | // Label 6405: @437275 |
| 135391 | GIM_Reject, |
| 135392 | // Label 6402: @437276 |
| 135393 | GIM_Reject, |
| 135394 | // Label 6399: @437277 |
| 135395 | GIM_Reject, |
| 135396 | // Label 95: @437278 |
| 135397 | GIM_Try, /*On fail goto*//*Label 6406*/ GIMT_Encode4(437379), |
| 135398 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 135399 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6409*/ GIMT_Encode4(437347), |
| 135400 | /*GILLT_s32*//*Label 6407*/ GIMT_Encode4(437305), |
| 135401 | /*GILLT_s64*//*Label 6408*/ GIMT_Encode4(437326), |
| 135402 | // Label 6407: @437305 |
| 135403 | GIM_Try, /*On fail goto*//*Label 6410*/ GIMT_Encode4(437325), // Rule ID 12 // |
| 135404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135405 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18482), |
| 135406 | // (ctlz_zero_undef:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18482>> => (S_FLBIT_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135407 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B32), |
| 135408 | GIR_RootConstrainSelectedInstOperands, |
| 135409 | // GIR_Coverage, 12, |
| 135410 | GIR_Done, |
| 135411 | // Label 6410: @437325 |
| 135412 | GIM_Reject, |
| 135413 | // Label 6408: @437326 |
| 135414 | GIM_Try, /*On fail goto*//*Label 6411*/ GIMT_Encode4(437346), // Rule ID 14 // |
| 135415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135416 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18482), |
| 135417 | // (ctlz_zero_undef:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18482>> => (S_FLBIT_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0) |
| 135418 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B64), |
| 135419 | GIR_RootConstrainSelectedInstOperands, |
| 135420 | // GIR_Coverage, 14, |
| 135421 | GIR_Done, |
| 135422 | // Label 6411: @437346 |
| 135423 | GIM_Reject, |
| 135424 | // Label 6409: @437347 |
| 135425 | GIM_Try, /*On fail goto*//*Label 6412*/ GIMT_Encode4(437378), // Rule ID 624 // |
| 135426 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135427 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135429 | // (ctlz_zero_undef:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_FFBH_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_U32_e64), |
| 135431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135433 | GIR_RootConstrainSelectedInstOperands, |
| 135434 | // GIR_Coverage, 624, |
| 135435 | GIR_EraseRootFromParent_Done, |
| 135436 | // Label 6412: @437378 |
| 135437 | GIM_Reject, |
| 135438 | // Label 6406: @437379 |
| 135439 | GIM_Reject, |
| 135440 | // Label 96: @437380 |
| 135441 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6415*/ GIMT_Encode4(437591), |
| 135442 | /*GILLT_s32*//*Label 6413*/ GIMT_Encode4(437399), |
| 135443 | /*GILLT_s64*//*Label 6414*/ GIMT_Encode4(437486), |
| 135444 | // Label 6413: @437399 |
| 135445 | GIM_Try, /*On fail goto*//*Label 6416*/ GIMT_Encode4(437428), // Rule ID 6 // |
| 135446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135448 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18480), |
| 135449 | // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18480>> => (S_BCNT1_I32_B32:{ *:[i32] }:{ *:[i1] } i32:{ *:[i32] }:$src0) |
| 135450 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BCNT1_I32_B32), |
| 135451 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 135452 | GIR_RootConstrainSelectedInstOperands, |
| 135453 | // GIR_Coverage, 6, |
| 135454 | GIR_Done, |
| 135455 | // Label 6416: @437428 |
| 135456 | GIM_Try, /*On fail goto*//*Label 6417*/ GIMT_Encode4(437457), // Rule ID 7 // |
| 135457 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 135458 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135459 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18480), |
| 135460 | // (ctpop:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18480>> => (S_BCNT1_I32_B64:{ *:[i32] }:{ *:[i1] } i64:{ *:[i64] }:$src0) |
| 135461 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BCNT1_I32_B64), |
| 135462 | GIR_AddImplicitDef, /*InsnID*/0, GIMT_Encode2(AMDGPU::SCC), GIMT_Encode2(RegState::Dead), |
| 135463 | GIR_RootConstrainSelectedInstOperands, |
| 135464 | // GIR_Coverage, 7, |
| 135465 | GIR_Done, |
| 135466 | // Label 6417: @437457 |
| 135467 | GIM_Try, /*On fail goto*//*Label 6418*/ GIMT_Encode4(437485), // Rule ID 6705 // |
| 135468 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135470 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_35622), |
| 135471 | // (ctpop:{ *:[i32] } i32:{ *:[i32] }:$popcnt)<<P:Predicate_anonymous_35622>> => (V_BCNT_U32_B32_e64:{ *:[i32] } VSrc_b32:{ *:[i32] }:$popcnt, 0:{ *:[i32] }) |
| 135472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BCNT_U32_B32_e64), |
| 135473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135474 | GIR_RootToRootCopy, /*OpIdx*/1, // popcnt |
| 135475 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135476 | GIR_RootConstrainSelectedInstOperands, |
| 135477 | // GIR_Coverage, 6705, |
| 135478 | GIR_EraseRootFromParent_Done, |
| 135479 | // Label 6418: @437485 |
| 135480 | GIM_Reject, |
| 135481 | // Label 6414: @437486 |
| 135482 | GIM_Try, /*On fail goto*//*Label 6419*/ GIMT_Encode4(437590), // Rule ID 1642 // |
| 135483 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 135484 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 135485 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18480), |
| 135486 | // (ctpop:{ *:[i64] } i64:{ *:[i64] }:$src)<<P:Predicate_anonymous_18480>> => (REG_SEQUENCE:{ *:[i64] } SReg_64:{ *:[i32] }, (COPY_TO_REGCLASS:{ *:[i32] } (S_BCNT1_I32_B64:{ *:[i1] }:{ *:[i1] } ?:{ *:[i64] }:$src), SReg_32:{ *:[i32] }), sub0:{ *:[i32] }, (S_MOV_B32:{ *:[i1] } 0:{ *:[i32] }), sub1:{ *:[i32] }) |
| 135487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 135488 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s1, |
| 135489 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s1, |
| 135490 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135491 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135492 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 135493 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 135494 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_BCNT1_I32_B64), |
| 135495 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135496 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // src |
| 135497 | GIR_SetImplicitDefDead, /*InsnID*/2, /*OpIdx for AMDGPU::SCC*/0, |
| 135498 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 135499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135501 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 135502 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 135504 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 135505 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135506 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 135507 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 135508 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 135509 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 135510 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::SReg_32_XEXEC_HI_and_SReg_32_XM0RegClassID), |
| 135511 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::SReg_32_XM0RegClassID), |
| 135512 | // GIR_Coverage, 1642, |
| 135513 | GIR_EraseRootFromParent_Done, |
| 135514 | // Label 6419: @437590 |
| 135515 | GIM_Reject, |
| 135516 | // Label 6415: @437591 |
| 135517 | GIM_Reject, |
| 135518 | // Label 97: @437592 |
| 135519 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 6424*/ GIMT_Encode4(438538), |
| 135520 | /*GILLT_s16*//*Label 6420*/ GIMT_Encode4(437619), |
| 135521 | /*GILLT_s32*//*Label 6421*/ GIMT_Encode4(437674), |
| 135522 | /*GILLT_s64*//*Label 6422*/ GIMT_Encode4(437830), |
| 135523 | /*GILLT_v2s16*//*Label 6423*/ GIMT_Encode4(438483), |
| 135524 | // Label 6420: @437619 |
| 135525 | GIM_Try, /*On fail goto*//*Label 6425*/ GIMT_Encode4(437673), // Rule ID 7205 // |
| 135526 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 135527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 135528 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135529 | // (bswap:{ *:[i16] } i16:{ *:[i16] }:$a) => (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[i16] }:$a, (S_MOV_B32:{ *:[i16] } 202113025:{ *:[i32] })) |
| 135530 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135531 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135532 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135533 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(202113025), |
| 135534 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 135536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135538 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 135539 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135540 | GIR_RootConstrainSelectedInstOperands, |
| 135541 | // GIR_Coverage, 7205, |
| 135542 | GIR_EraseRootFromParent_Done, |
| 135543 | // Label 6425: @437673 |
| 135544 | GIM_Reject, |
| 135545 | // Label 6421: @437674 |
| 135546 | GIM_Try, /*On fail goto*//*Label 6426*/ GIMT_Encode4(437829), |
| 135547 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135548 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135549 | GIM_Try, /*On fail goto*//*Label 6427*/ GIMT_Encode4(437733), // Rule ID 7203 // |
| 135550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 135551 | // (bswap:{ *:[i32] } i32:{ *:[i32] }:$a) => (V_PERM_B32_e64:{ *:[i32] } 0:{ *:[i32] }, VSrc_b32:{ *:[i32] }:$a, (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] })) |
| 135552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135555 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(66051), |
| 135556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 135558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135560 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 135561 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135562 | GIR_RootConstrainSelectedInstOperands, |
| 135563 | // GIR_Coverage, 7203, |
| 135564 | GIR_EraseRootFromParent_Done, |
| 135565 | // Label 6427: @437733 |
| 135566 | GIM_Try, /*On fail goto*//*Label 6428*/ GIMT_Encode4(437828), // Rule ID 7201 // |
| 135567 | // (bswap:{ *:[i32] } i32:{ *:[i32] }:$a) => (V_BFI_B32_e64:{ *:[i32] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i32] }:$a, VSrc_b32:{ *:[i32] }:$a, 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } VSrc_b32:{ *:[i32] }:$a, VSrc_b32:{ *:[i32] }:$a, 8:{ *:[i32] })) |
| 135568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135569 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 135570 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 135571 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135572 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135573 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 135574 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 135575 | GIR_AddImm8, /*InsnID*/3, /*Imm*/8, |
| 135576 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 135577 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135578 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135579 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 135580 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // a |
| 135581 | GIR_AddImm8, /*InsnID*/2, /*Imm*/24, |
| 135582 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 135583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135584 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135585 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(16711935), |
| 135586 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 135588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135589 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135590 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 135591 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 135592 | GIR_RootConstrainSelectedInstOperands, |
| 135593 | // GIR_Coverage, 7201, |
| 135594 | GIR_EraseRootFromParent_Done, |
| 135595 | // Label 6428: @437828 |
| 135596 | GIM_Reject, |
| 135597 | // Label 6426: @437829 |
| 135598 | GIM_Reject, |
| 135599 | // Label 6422: @437830 |
| 135600 | GIM_Try, /*On fail goto*//*Label 6429*/ GIMT_Encode4(438482), |
| 135601 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 135602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135603 | GIM_Try, /*On fail goto*//*Label 6430*/ GIMT_Encode4(438033), // Rule ID 7204 // |
| 135604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 135605 | // (bswap:{ *:[i64] } i64:{ *:[i64] }:$a) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] })), sub0:{ *:[i32] }, (V_PERM_B32_e64:{ *:[i16] } 0:{ *:[i32] }, (EXTRACT_SUBREG:{ *:[i16] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (S_MOV_B32:{ *:[i16] } 66051:{ *:[i32] })), sub1:{ *:[i32] }) |
| 135606 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135607 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 135608 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 135609 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s16, |
| 135610 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s16, |
| 135611 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16, |
| 135612 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135613 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135614 | GIR_AddImm, /*InsnID*/6, /*Imm*/GIMT_Encode8(66051), |
| 135615 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 135616 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135617 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135618 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135619 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135620 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135621 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 135622 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135623 | GIR_AddImm8, /*InsnID*/4, /*Imm*/0, |
| 135624 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/4, |
| 135625 | GIR_AddSimpleTempRegister, /*InsnID*/4, /*TempRegID*/5, |
| 135626 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 135627 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135628 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135629 | GIR_AddImm, /*InsnID*/3, /*Imm*/GIMT_Encode8(66051), |
| 135630 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 135631 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135632 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135633 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135634 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135635 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135636 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 135637 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135638 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 135639 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 135640 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 135641 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 135643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 135644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135645 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 135646 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/3, |
| 135647 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 135648 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135649 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135650 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135651 | // GIR_Coverage, 7204, |
| 135652 | GIR_EraseRootFromParent_Done, |
| 135653 | // Label 6430: @438033 |
| 135654 | GIM_Try, /*On fail goto*//*Label 6431*/ GIMT_Encode4(438481), // Rule ID 7202 // |
| 135655 | // (bswap:{ *:[i64] } i64:{ *:[i64] }:$a) => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] }), 8:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFI_B32_e64:{ *:[i16] } (S_MOV_B32:{ *:[i16] } 16711935:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), 24:{ *:[i32] }), (V_ALIGNBIT_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] }), 8:{ *:[i32] })), sub1:{ *:[i32] }) |
| 135656 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135657 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s16, |
| 135658 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 135659 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 135660 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s32, |
| 135661 | GIR_MakeTempReg, /*TempRegID*/5, /*TypeID*/GILLT_s16, |
| 135662 | GIR_MakeTempReg, /*TempRegID*/6, /*TypeID*/GILLT_s32, |
| 135663 | GIR_MakeTempReg, /*TempRegID*/7, /*TypeID*/GILLT_s32, |
| 135664 | GIR_MakeTempReg, /*TempRegID*/8, /*TypeID*/GILLT_s16, |
| 135665 | GIR_MakeTempReg, /*TempRegID*/9, /*TypeID*/GILLT_s16, |
| 135666 | GIR_MakeTempReg, /*TempRegID*/10, /*TypeID*/GILLT_s16, |
| 135667 | GIR_MakeTempReg, /*TempRegID*/11, /*TypeID*/GILLT_s32, |
| 135668 | GIR_MakeTempReg, /*TempRegID*/12, /*TypeID*/GILLT_s32, |
| 135669 | GIR_MakeTempReg, /*TempRegID*/13, /*TypeID*/GILLT_s16, |
| 135670 | GIR_MakeTempReg, /*TempRegID*/14, /*TypeID*/GILLT_s32, |
| 135671 | GIR_MakeTempReg, /*TempRegID*/15, /*TypeID*/GILLT_s32, |
| 135672 | GIR_BuildMI, /*InsnID*/16, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135673 | GIR_AddTempRegister, /*InsnID*/16, /*TempRegID*/15, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135674 | GIR_CopySubReg, /*NewInsnID*/16, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135675 | GIR_ConstrainOperandRC, /*InsnID*/16, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135676 | GIR_ConstrainOperandRC, /*InsnID*/16, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135677 | GIR_BuildMI, /*InsnID*/15, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135678 | GIR_AddTempRegister, /*InsnID*/15, /*TempRegID*/14, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135679 | GIR_CopySubReg, /*NewInsnID*/15, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135680 | GIR_ConstrainOperandRC, /*InsnID*/15, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135681 | GIR_ConstrainOperandRC, /*InsnID*/15, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135682 | GIR_BuildMI, /*InsnID*/14, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135683 | GIR_AddTempRegister, /*InsnID*/14, /*TempRegID*/13, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135684 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/14, |
| 135685 | GIR_AddSimpleTempRegister, /*InsnID*/14, /*TempRegID*/15, |
| 135686 | GIR_AddImm8, /*InsnID*/14, /*Imm*/8, |
| 135687 | GIR_ConstrainSelectedInstOperands, /*InsnID*/14, |
| 135688 | GIR_BuildMI, /*InsnID*/13, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135689 | GIR_AddTempRegister, /*InsnID*/13, /*TempRegID*/12, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135690 | GIR_CopySubReg, /*NewInsnID*/13, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135691 | GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135692 | GIR_ConstrainOperandRC, /*InsnID*/13, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135693 | GIR_BuildMI, /*InsnID*/12, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135694 | GIR_AddTempRegister, /*InsnID*/12, /*TempRegID*/11, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135695 | GIR_CopySubReg, /*NewInsnID*/12, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135696 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135697 | GIR_ConstrainOperandRC, /*InsnID*/12, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135698 | GIR_BuildMI, /*InsnID*/11, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135699 | GIR_AddTempRegister, /*InsnID*/11, /*TempRegID*/10, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135700 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/11, |
| 135701 | GIR_AddSimpleTempRegister, /*InsnID*/11, /*TempRegID*/12, |
| 135702 | GIR_AddImm8, /*InsnID*/11, /*Imm*/24, |
| 135703 | GIR_ConstrainSelectedInstOperands, /*InsnID*/11, |
| 135704 | GIR_BuildMI, /*InsnID*/10, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135705 | GIR_AddTempRegister, /*InsnID*/10, /*TempRegID*/9, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135706 | GIR_AddImm, /*InsnID*/10, /*Imm*/GIMT_Encode8(16711935), |
| 135707 | GIR_ConstrainSelectedInstOperands, /*InsnID*/10, |
| 135708 | GIR_BuildMI, /*InsnID*/9, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 135709 | GIR_AddTempRegister, /*InsnID*/9, /*TempRegID*/8, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135710 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/9, |
| 135711 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/10, |
| 135712 | GIR_AddSimpleTempRegister, /*InsnID*/9, /*TempRegID*/13, |
| 135713 | GIR_ConstrainSelectedInstOperands, /*InsnID*/9, |
| 135714 | GIR_BuildMI, /*InsnID*/8, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135715 | GIR_AddTempRegister, /*InsnID*/8, /*TempRegID*/7, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135716 | GIR_CopySubReg, /*NewInsnID*/8, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135717 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135718 | GIR_ConstrainOperandRC, /*InsnID*/8, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135719 | GIR_BuildMI, /*InsnID*/7, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135720 | GIR_AddTempRegister, /*InsnID*/7, /*TempRegID*/6, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135721 | GIR_CopySubReg, /*NewInsnID*/7, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135722 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135723 | GIR_ConstrainOperandRC, /*InsnID*/7, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135724 | GIR_BuildMI, /*InsnID*/6, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135725 | GIR_AddTempRegister, /*InsnID*/6, /*TempRegID*/5, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135726 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/6, |
| 135727 | GIR_AddSimpleTempRegister, /*InsnID*/6, /*TempRegID*/7, |
| 135728 | GIR_AddImm8, /*InsnID*/6, /*Imm*/8, |
| 135729 | GIR_ConstrainSelectedInstOperands, /*InsnID*/6, |
| 135730 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135731 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135732 | GIR_CopySubReg, /*NewInsnID*/5, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135733 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135734 | GIR_ConstrainOperandRC, /*InsnID*/5, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135735 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135736 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135737 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135738 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135739 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135740 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_ALIGNBIT_B32_e64), |
| 135741 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135742 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 135743 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/4, |
| 135744 | GIR_AddImm8, /*InsnID*/3, /*Imm*/24, |
| 135745 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 135746 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135747 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135748 | GIR_AddImm, /*InsnID*/2, /*Imm*/GIMT_Encode8(16711935), |
| 135749 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 135750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFI_B32_e64), |
| 135751 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135752 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 135753 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 135754 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/5, |
| 135755 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 135757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 135758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135759 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 135760 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/8, |
| 135761 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 135762 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135763 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135764 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135765 | // GIR_Coverage, 7202, |
| 135766 | GIR_EraseRootFromParent_Done, |
| 135767 | // Label 6431: @438481 |
| 135768 | GIM_Reject, |
| 135769 | // Label 6429: @438482 |
| 135770 | GIM_Reject, |
| 135771 | // Label 6423: @438483 |
| 135772 | GIM_Try, /*On fail goto*//*Label 6432*/ GIMT_Encode4(438537), // Rule ID 7207 // |
| 135773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX8Plus), |
| 135774 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 135775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135776 | // (bswap:{ *:[v2i16] } v2i16:{ *:[v2i16] }:$a) => (V_PERM_B32_e64:{ *:[v2i16] } 0:{ *:[i32] }, VSrc_b32:{ *:[v2i16] }:$a, (S_MOV_B32:{ *:[i16] } 33751041:{ *:[i32] })) |
| 135777 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135778 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 135779 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135780 | GIR_AddImm, /*InsnID*/1, /*Imm*/GIMT_Encode8(33751041), |
| 135781 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PERM_B32_e64), |
| 135783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135784 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135785 | GIR_RootToRootCopy, /*OpIdx*/1, // a |
| 135786 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135787 | GIR_RootConstrainSelectedInstOperands, |
| 135788 | // GIR_Coverage, 7207, |
| 135789 | GIR_EraseRootFromParent_Done, |
| 135790 | // Label 6432: @438537 |
| 135791 | GIM_Reject, |
| 135792 | // Label 6424: @438538 |
| 135793 | GIM_Reject, |
| 135794 | // Label 98: @438539 |
| 135795 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6435*/ GIMT_Encode4(438786), |
| 135796 | /*GILLT_s32*//*Label 6433*/ GIMT_Encode4(438558), |
| 135797 | /*GILLT_s64*//*Label 6434*/ GIMT_Encode4(438620), |
| 135798 | // Label 6433: @438558 |
| 135799 | GIM_Try, /*On fail goto*//*Label 6436*/ GIMT_Encode4(438619), |
| 135800 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135801 | GIM_Try, /*On fail goto*//*Label 6437*/ GIMT_Encode4(438586), // Rule ID 4 // |
| 135802 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135803 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18479), |
| 135804 | // (bitreverse:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18479>> => (S_BREV_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135805 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BREV_B32), |
| 135806 | GIR_RootConstrainSelectedInstOperands, |
| 135807 | // GIR_Coverage, 4, |
| 135808 | GIR_Done, |
| 135809 | // Label 6437: @438586 |
| 135810 | GIM_Try, /*On fail goto*//*Label 6438*/ GIMT_Encode4(438618), // Rule ID 623 // |
| 135811 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135812 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22135), |
| 135813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135814 | // (bitreverse:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0))<<P:Predicate_anonymous_22135>> => (V_BFREV_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 135815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64), |
| 135816 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135818 | GIR_RootConstrainSelectedInstOperands, |
| 135819 | // GIR_Coverage, 623, |
| 135820 | GIR_EraseRootFromParent_Done, |
| 135821 | // Label 6438: @438618 |
| 135822 | GIM_Reject, |
| 135823 | // Label 6436: @438619 |
| 135824 | GIM_Reject, |
| 135825 | // Label 6434: @438620 |
| 135826 | GIM_Try, /*On fail goto*//*Label 6439*/ GIMT_Encode4(438785), |
| 135827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 135828 | GIM_Try, /*On fail goto*//*Label 6440*/ GIMT_Encode4(438648), // Rule ID 5 // |
| 135829 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64RegClassID), |
| 135830 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18479), |
| 135831 | // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18479>> => (S_BREV_B64:{ *:[i64] } i64:{ *:[i64] }:$src0) |
| 135832 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_BREV_B64), |
| 135833 | GIR_RootConstrainSelectedInstOperands, |
| 135834 | // GIR_Coverage, 5, |
| 135835 | GIR_Done, |
| 135836 | // Label 6440: @438648 |
| 135837 | GIM_Try, /*On fail goto*//*Label 6441*/ GIMT_Encode4(438784), // Rule ID 7208 // |
| 135838 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135839 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_22135), |
| 135840 | // (bitreverse:{ *:[i64] } i64:{ *:[i64] }:$a)<<P:Predicate_anonymous_22135>> => (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, (V_BFREV_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub1:{ *:[i32] })), sub0:{ *:[i32] }, (V_BFREV_B32_e64:{ *:[i16] } (EXTRACT_SUBREG:{ *:[i32] } VReg_64:{ *:[i64] }:$a, sub0:{ *:[i32] })), sub1:{ *:[i32] }) |
| 135841 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 135842 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 135843 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s16, |
| 135844 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s32, |
| 135845 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135846 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135847 | GIR_CopySubReg, /*NewInsnID*/4, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(3), // a |
| 135848 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135849 | GIR_ConstrainOperandRC, /*InsnID*/4, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135850 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64), |
| 135851 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135852 | GIR_AddSimpleTempRegister, /*InsnID*/3, /*TempRegID*/3, |
| 135853 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 135854 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 135855 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135856 | GIR_CopySubReg, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, /*SubRegIdx*/GIMT_Encode2(11), // a |
| 135857 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135858 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135859 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_BFREV_B32_e64), |
| 135860 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 135861 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 135862 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 135863 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 135864 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 135865 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 135866 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/3, |
| 135867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/2, |
| 135868 | GIR_AddImm8, /*InsnID*/0, /*SubRegIndex*/11, |
| 135869 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135870 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135871 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135872 | // GIR_Coverage, 7208, |
| 135873 | GIR_EraseRootFromParent_Done, |
| 135874 | // Label 6441: @438784 |
| 135875 | GIM_Reject, |
| 135876 | // Label 6439: @438785 |
| 135877 | GIM_Reject, |
| 135878 | // Label 6435: @438786 |
| 135879 | GIM_Reject, |
| 135880 | // Label 99: @438787 |
| 135881 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 6445*/ GIMT_Encode4(439114), |
| 135882 | /*GILLT_s16*//*Label 6442*/ GIMT_Encode4(438810), |
| 135883 | /*GILLT_s32*//*Label 6443*/ GIMT_Encode4(438984), |
| 135884 | /*GILLT_s64*//*Label 6444*/ GIMT_Encode4(439064), |
| 135885 | // Label 6442: @438810 |
| 135886 | GIM_Try, /*On fail goto*//*Label 6446*/ GIMT_Encode4(438983), |
| 135887 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 135888 | GIM_Try, /*On fail goto*//*Label 6447*/ GIMT_Encode4(438845), // Rule ID 37 // |
| 135889 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 135890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135891 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18492), |
| 135892 | // (fceil:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_18492>> => (S_CEIL_F16:{ *:[f16] } f16:{ *:[f16] }:$src0) |
| 135893 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CEIL_F16), |
| 135894 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 135895 | GIR_RootConstrainSelectedInstOperands, |
| 135896 | // GIR_Coverage, 37, |
| 135897 | GIR_Done, |
| 135898 | // Label 6447: @438845 |
| 135899 | GIM_Try, /*On fail goto*//*Label 6448*/ GIMT_Encode4(438891), // Rule ID 706 // |
| 135900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 135901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135902 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135903 | // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CEIL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 135904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_e64), |
| 135905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 135909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 135910 | GIR_RootConstrainSelectedInstOperands, |
| 135911 | // GIR_Coverage, 706, |
| 135912 | GIR_EraseRootFromParent_Done, |
| 135913 | // Label 6448: @438891 |
| 135914 | GIM_Try, /*On fail goto*//*Label 6449*/ GIMT_Encode4(438937), // Rule ID 708 // |
| 135915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 135916 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135918 | // (fceil:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CEIL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 135919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_fake16_e64), |
| 135920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 135924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 135925 | GIR_RootConstrainSelectedInstOperands, |
| 135926 | // GIR_Coverage, 708, |
| 135927 | GIR_EraseRootFromParent_Done, |
| 135928 | // Label 6449: @438937 |
| 135929 | GIM_Try, /*On fail goto*//*Label 6450*/ GIMT_Encode4(438982), // Rule ID 707 // |
| 135930 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 135931 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 135932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 135933 | // (fceil:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_CEIL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 135934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F16_t16_e64), |
| 135935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135939 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 135941 | GIR_RootConstrainSelectedInstOperands, |
| 135942 | // GIR_Coverage, 707, |
| 135943 | GIR_EraseRootFromParent_Done, |
| 135944 | // Label 6450: @438982 |
| 135945 | GIM_Reject, |
| 135946 | // Label 6446: @438983 |
| 135947 | GIM_Reject, |
| 135948 | // Label 6443: @438984 |
| 135949 | GIM_Try, /*On fail goto*//*Label 6451*/ GIMT_Encode4(439063), |
| 135950 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 135951 | GIM_Try, /*On fail goto*//*Label 6452*/ GIMT_Encode4(439019), // Rule ID 32 // |
| 135952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 135953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 135954 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18492), |
| 135955 | // (fceil:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18492>> => (S_CEIL_F32:{ *:[f32] } f32:{ *:[f32] }:$src0) |
| 135956 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_CEIL_F32), |
| 135957 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 135958 | GIR_RootConstrainSelectedInstOperands, |
| 135959 | // GIR_Coverage, 32, |
| 135960 | GIR_Done, |
| 135961 | // Label 6452: @439019 |
| 135962 | GIM_Try, /*On fail goto*//*Label 6453*/ GIMT_Encode4(439062), // Rule ID 601 // |
| 135963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 135964 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135965 | // (fceil:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CEIL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 135966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F32_e64), |
| 135967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 135971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 135972 | GIR_RootConstrainSelectedInstOperands, |
| 135973 | // GIR_Coverage, 601, |
| 135974 | GIR_EraseRootFromParent_Done, |
| 135975 | // Label 6453: @439062 |
| 135976 | GIM_Reject, |
| 135977 | // Label 6451: @439063 |
| 135978 | GIM_Reject, |
| 135979 | // Label 6444: @439064 |
| 135980 | GIM_Try, /*On fail goto*//*Label 6454*/ GIMT_Encode4(439113), // Rule ID 645 // |
| 135981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus), |
| 135982 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 135983 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 135984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 135985 | // (fceil:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CEIL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 135986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CEIL_F64_e64), |
| 135987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 135988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 135989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 135990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 135991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 135992 | GIR_RootConstrainSelectedInstOperands, |
| 135993 | // GIR_Coverage, 645, |
| 135994 | GIR_EraseRootFromParent_Done, |
| 135995 | // Label 6454: @439113 |
| 135996 | GIM_Reject, |
| 135997 | // Label 6445: @439114 |
| 135998 | GIM_Reject, |
| 135999 | // Label 100: @439115 |
| 136000 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 6457*/ GIMT_Encode4(439406), |
| 136001 | /*GILLT_s16*//*Label 6455*/ GIMT_Encode4(439134), |
| 136002 | /*GILLT_s32*//*Label 6456*/ GIMT_Encode4(439352), |
| 136003 | // Label 6455: @439134 |
| 136004 | GIM_Try, /*On fail goto*//*Label 6458*/ GIMT_Encode4(439351), |
| 136005 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 136006 | GIM_Try, /*On fail goto*//*Label 6459*/ GIMT_Encode4(439213), // Rule ID 2288 // |
| 136007 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 136008 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 136009 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24202), |
| 136010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136011 | // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24202>> => (COPY_TO_REGCLASS:{ *:[f16] } (V_S_SQRT_F16_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), SReg_32_XEXEC:{ *:[i32] }) |
| 136012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 136013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F16_e64), |
| 136014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136015 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136016 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136017 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136018 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136019 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 136021 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 136022 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136023 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 136024 | // GIR_Coverage, 2288, |
| 136025 | GIR_EraseRootFromParent_Done, |
| 136026 | // Label 6459: @439213 |
| 136027 | GIM_Try, /*On fail goto*//*Label 6460*/ GIMT_Encode4(439259), // Rule ID 662 // |
| 136028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136031 | // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_e64), |
| 136033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136038 | GIR_RootConstrainSelectedInstOperands, |
| 136039 | // GIR_Coverage, 662, |
| 136040 | GIR_EraseRootFromParent_Done, |
| 136041 | // Label 6460: @439259 |
| 136042 | GIM_Try, /*On fail goto*//*Label 6461*/ GIMT_Encode4(439305), // Rule ID 666 // |
| 136043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136044 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136046 | // (fsqrt:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_SQRT_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_fake16_e64), |
| 136048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136053 | GIR_RootConstrainSelectedInstOperands, |
| 136054 | // GIR_Coverage, 666, |
| 136055 | GIR_EraseRootFromParent_Done, |
| 136056 | // Label 6461: @439305 |
| 136057 | GIM_Try, /*On fail goto*//*Label 6462*/ GIMT_Encode4(439350), // Rule ID 664 // |
| 136058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 136059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 136060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136061 | // (fsqrt:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_SQRT_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 136062 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SQRT_F16_t16_e64), |
| 136063 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136066 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136067 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136068 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136069 | GIR_RootConstrainSelectedInstOperands, |
| 136070 | // GIR_Coverage, 664, |
| 136071 | GIR_EraseRootFromParent_Done, |
| 136072 | // Label 6462: @439350 |
| 136073 | GIM_Reject, |
| 136074 | // Label 6458: @439351 |
| 136075 | GIM_Reject, |
| 136076 | // Label 6456: @439352 |
| 136077 | GIM_Try, /*On fail goto*//*Label 6463*/ GIMT_Encode4(439405), // Rule ID 952 // |
| 136078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPseudoScalarTrans), |
| 136079 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 136080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XEXECRegClassID), |
| 136081 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_24202), |
| 136082 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136083 | // (fsqrt:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod))<<P:Predicate_anonymous_24202>> => (V_S_SQRT_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_S_SQRT_F32_e64), |
| 136085 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136090 | GIR_RootConstrainSelectedInstOperands, |
| 136091 | // GIR_Coverage, 952, |
| 136092 | GIR_EraseRootFromParent_Done, |
| 136093 | // Label 6463: @439405 |
| 136094 | GIM_Reject, |
| 136095 | // Label 6457: @439406 |
| 136096 | GIM_Reject, |
| 136097 | // Label 101: @439407 |
| 136098 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 6467*/ GIMT_Encode4(439920), |
| 136099 | /*GILLT_s16*//*Label 6464*/ GIMT_Encode4(439430), |
| 136100 | /*GILLT_s32*//*Label 6465*/ GIMT_Encode4(439604), |
| 136101 | /*GILLT_s64*//*Label 6466*/ GIMT_Encode4(439684), |
| 136102 | // Label 6464: @439430 |
| 136103 | GIM_Try, /*On fail goto*//*Label 6468*/ GIMT_Encode4(439603), |
| 136104 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 136105 | GIM_Try, /*On fail goto*//*Label 6469*/ GIMT_Encode4(439465), // Rule ID 38 // |
| 136106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136107 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136108 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18493), |
| 136109 | // (ffloor:{ *:[f16] } f16:{ *:[f16] }:$src0)<<P:Predicate_anonymous_18493>> => (S_FLOOR_F16:{ *:[f16] } f16:{ *:[f16] }:$src0) |
| 136110 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLOOR_F16), |
| 136111 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136112 | GIR_RootConstrainSelectedInstOperands, |
| 136113 | // GIR_Coverage, 38, |
| 136114 | GIR_Done, |
| 136115 | // Label 6469: @439465 |
| 136116 | GIM_Try, /*On fail goto*//*Label 6470*/ GIMT_Encode4(439511), // Rule ID 703 // |
| 136117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136118 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136120 | // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FLOOR_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136121 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_e64), |
| 136122 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136127 | GIR_RootConstrainSelectedInstOperands, |
| 136128 | // GIR_Coverage, 703, |
| 136129 | GIR_EraseRootFromParent_Done, |
| 136130 | // Label 6470: @439511 |
| 136131 | GIM_Try, /*On fail goto*//*Label 6471*/ GIMT_Encode4(439557), // Rule ID 705 // |
| 136132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136133 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136134 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136135 | // (ffloor:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FLOOR_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136136 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_fake16_e64), |
| 136137 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136142 | GIR_RootConstrainSelectedInstOperands, |
| 136143 | // GIR_Coverage, 705, |
| 136144 | GIR_EraseRootFromParent_Done, |
| 136145 | // Label 6471: @439557 |
| 136146 | GIM_Try, /*On fail goto*//*Label 6472*/ GIMT_Encode4(439602), // Rule ID 704 // |
| 136147 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 136148 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 136149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136150 | // (ffloor:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_FLOOR_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0) |
| 136151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F16_t16_e64), |
| 136152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136155 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136156 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136157 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136158 | GIR_RootConstrainSelectedInstOperands, |
| 136159 | // GIR_Coverage, 704, |
| 136160 | GIR_EraseRootFromParent_Done, |
| 136161 | // Label 6472: @439602 |
| 136162 | GIM_Reject, |
| 136163 | // Label 6468: @439603 |
| 136164 | GIM_Reject, |
| 136165 | // Label 6465: @439604 |
| 136166 | GIM_Try, /*On fail goto*//*Label 6473*/ GIMT_Encode4(439683), |
| 136167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 136168 | GIM_Try, /*On fail goto*//*Label 6474*/ GIMT_Encode4(439639), // Rule ID 33 // |
| 136169 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136170 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136171 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18493), |
| 136172 | // (ffloor:{ *:[f32] } f32:{ *:[f32] }:$src0)<<P:Predicate_anonymous_18493>> => (S_FLOOR_F32:{ *:[f32] } f32:{ *:[f32] }:$src0) |
| 136173 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLOOR_F32), |
| 136174 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136175 | GIR_RootConstrainSelectedInstOperands, |
| 136176 | // GIR_Coverage, 33, |
| 136177 | GIR_Done, |
| 136178 | // Label 6474: @439639 |
| 136179 | GIM_Try, /*On fail goto*//*Label 6475*/ GIMT_Encode4(439682), // Rule ID 603 // |
| 136180 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136181 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136182 | // (ffloor:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FLOOR_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F32_e64), |
| 136184 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136189 | GIR_RootConstrainSelectedInstOperands, |
| 136190 | // GIR_Coverage, 603, |
| 136191 | GIR_EraseRootFromParent_Done, |
| 136192 | // Label 6475: @439682 |
| 136193 | GIM_Reject, |
| 136194 | // Label 6473: @439683 |
| 136195 | GIM_Reject, |
| 136196 | // Label 6466: @439684 |
| 136197 | GIM_Try, /*On fail goto*//*Label 6476*/ GIMT_Encode4(439919), |
| 136198 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 136199 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 136200 | GIM_Try, /*On fail goto*//*Label 6477*/ GIMT_Encode4(439876), // Rule ID 7293 // |
| 136201 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6), |
| 136202 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136203 | // (ffloor:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$x, i32:{ *:[i32] }:$mods)) => (V_ADD_F64_e64:{ *:[f64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x, 1:{ *:[i32] }, (V_CNDMASK_B64_PSEUDO:{ *:[i64] } (V_MIN_F64_e64:{ *:[i64] } 0:{ *:[i32] }, (V_FRACT_F64_e64:{ *:[i64] } ?:{ *:[i32] }:$mods, ?:{ *:[f64] }:$x), 0:{ *:[i32] }, (V_MOV_B64_PSEUDO:{ *:[i64] } 4607182418800017407:{ *:[i64] })), ?:{ *:[f64] }:$x, (V_CMP_CLASS_F64_e64:{ *:[i1] } 0:{ *:[i32] }, ?:{ *:[f64] }:$x, 3:{ *:[i32] }))) |
| 136204 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 136205 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 136206 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 136207 | GIR_MakeTempReg, /*TempRegID*/3, /*TypeID*/GILLT_s64, |
| 136208 | GIR_MakeTempReg, /*TempRegID*/4, /*TypeID*/GILLT_s1, |
| 136209 | GIR_BuildMI, /*InsnID*/5, /*Opcode*/GIMT_Encode2(AMDGPU::V_CMP_CLASS_F64_e64), |
| 136210 | GIR_AddTempRegister, /*InsnID*/5, /*TempRegID*/4, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136211 | GIR_AddImm8, /*InsnID*/5, /*Imm*/0, |
| 136212 | GIR_ComplexSubOperandRenderer, /*InsnID*/5, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x |
| 136213 | GIR_AddImm8, /*InsnID*/5, /*Imm*/3, |
| 136214 | GIR_ConstrainSelectedInstOperands, /*InsnID*/5, |
| 136215 | GIR_BuildMI, /*InsnID*/4, /*Opcode*/GIMT_Encode2(AMDGPU::V_MOV_B64_PSEUDO), |
| 136216 | GIR_AddTempRegister, /*InsnID*/4, /*TempRegID*/3, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136217 | GIR_AddImm, /*InsnID*/4, /*Imm*/GIMT_Encode8(4607182418800017407), |
| 136218 | GIR_ConstrainSelectedInstOperands, /*InsnID*/4, |
| 136219 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(AMDGPU::V_FRACT_F64_e64), |
| 136220 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136221 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods |
| 136222 | GIR_ComplexSubOperandRenderer, /*InsnID*/3, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x |
| 136223 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 136224 | GIR_AddImm8, /*InsnID*/3, /*Imm*/0, |
| 136225 | GIR_ConstrainSelectedInstOperands, /*InsnID*/3, |
| 136226 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_F64_e64), |
| 136227 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136228 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 136229 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/2, |
| 136230 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 136231 | GIR_AddSimpleTempRegister, /*InsnID*/2, /*TempRegID*/3, |
| 136232 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 136233 | GIR_AddImm8, /*InsnID*/2, /*Imm*/0, |
| 136234 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 136235 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_CNDMASK_B64_PSEUDO), |
| 136236 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136237 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 136238 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x |
| 136239 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/4, |
| 136240 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64), |
| 136242 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // mods |
| 136244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // x |
| 136245 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 136246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136247 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136248 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136249 | GIR_RootConstrainSelectedInstOperands, |
| 136250 | // GIR_Coverage, 7293, |
| 136251 | GIR_EraseRootFromParent_Done, |
| 136252 | // Label 6477: @439876 |
| 136253 | GIM_Try, /*On fail goto*//*Label 6478*/ GIMT_Encode4(439918), // Rule ID 647 // |
| 136254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Plus), |
| 136255 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136256 | // (ffloor:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_FLOOR_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FLOOR_F64_e64), |
| 136258 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136260 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136263 | GIR_RootConstrainSelectedInstOperands, |
| 136264 | // GIR_Coverage, 647, |
| 136265 | GIR_EraseRootFromParent_Done, |
| 136266 | // Label 6478: @439918 |
| 136267 | GIM_Reject, |
| 136268 | // Label 6476: @439919 |
| 136269 | GIM_Reject, |
| 136270 | // Label 6467: @439920 |
| 136271 | GIM_Reject, |
| 136272 | // Label 102: @439921 |
| 136273 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 6484*/ GIMT_Encode4(440882), |
| 136274 | /*GILLT_s16*//*Label 6479*/ GIMT_Encode4(439952), |
| 136275 | /*GILLT_s32*//*Label 6480*/ GIMT_Encode4(440314), |
| 136276 | /*GILLT_s64*//*Label 6481*/ GIMT_Encode4(440482), |
| 136277 | /*GILLT_v2s16*//*Label 6482*/ GIMT_Encode4(440735), |
| 136278 | /*GILLT_v2s32*//*Label 6483*/ GIMT_Encode4(440807), |
| 136279 | // Label 6479: @439952 |
| 136280 | GIM_Try, /*On fail goto*//*Label 6485*/ GIMT_Encode4(440313), |
| 136281 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 136282 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 136283 | GIM_Try, /*On fail goto*//*Label 6486*/ GIMT_Encode4(439998), // Rule ID 98 // |
| 136284 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136285 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136286 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136287 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136288 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18518), |
| 136289 | // (strict_fadd:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18518>> => (S_ADD_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 136290 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F16), |
| 136291 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136292 | GIR_RootConstrainSelectedInstOperands, |
| 136293 | // GIR_Coverage, 98, |
| 136294 | GIR_Done, |
| 136295 | // Label 6486: @439998 |
| 136296 | GIM_Try, /*On fail goto*//*Label 6487*/ GIMT_Encode4(440061), // Rule ID 789 // |
| 136297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136301 | // (strict_fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64), |
| 136303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136310 | GIR_RootConstrainSelectedInstOperands, |
| 136311 | // GIR_Coverage, 789, |
| 136312 | GIR_EraseRootFromParent_Done, |
| 136313 | // Label 6487: @440061 |
| 136314 | GIM_Try, /*On fail goto*//*Label 6488*/ GIMT_Encode4(440124), // Rule ID 793 // |
| 136315 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136316 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136318 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136319 | // (strict_fadd:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136320 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64), |
| 136321 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136322 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136328 | GIR_RootConstrainSelectedInstOperands, |
| 136329 | // GIR_Coverage, 793, |
| 136330 | GIR_EraseRootFromParent_Done, |
| 136331 | // Label 6488: @440124 |
| 136332 | GIM_Try, /*On fail goto*//*Label 6489*/ GIMT_Encode4(440187), // Rule ID 8062 // |
| 136333 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136334 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136336 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136337 | // (strict_fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_e64), |
| 136339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136346 | GIR_RootConstrainSelectedInstOperands, |
| 136347 | // GIR_Coverage, 8062, |
| 136348 | GIR_EraseRootFromParent_Done, |
| 136349 | // Label 6489: @440187 |
| 136350 | GIM_Try, /*On fail goto*//*Label 6490*/ GIMT_Encode4(440250), // Rule ID 8064 // |
| 136351 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136352 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136355 | // (strict_fadd:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_fake16_e64), |
| 136357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136361 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136362 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136364 | GIR_RootConstrainSelectedInstOperands, |
| 136365 | // GIR_Coverage, 8064, |
| 136366 | GIR_EraseRootFromParent_Done, |
| 136367 | // Label 6490: @440250 |
| 136368 | GIM_Try, /*On fail goto*//*Label 6491*/ GIMT_Encode4(440312), // Rule ID 791 // |
| 136369 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 136370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 136371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136372 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136373 | // (strict_fadd:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 136374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F16_t16_e64), |
| 136375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136379 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136380 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136381 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136382 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136383 | GIR_RootConstrainSelectedInstOperands, |
| 136384 | // GIR_Coverage, 791, |
| 136385 | GIR_EraseRootFromParent_Done, |
| 136386 | // Label 6491: @440312 |
| 136387 | GIM_Reject, |
| 136388 | // Label 6485: @440313 |
| 136389 | GIM_Reject, |
| 136390 | // Label 6480: @440314 |
| 136391 | GIM_Try, /*On fail goto*//*Label 6492*/ GIMT_Encode4(440481), |
| 136392 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 136393 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 136394 | GIM_Try, /*On fail goto*//*Label 6493*/ GIMT_Encode4(440360), // Rule ID 90 // |
| 136395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136396 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136397 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136398 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136399 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18518), |
| 136400 | // (strict_fadd:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18518>> => (S_ADD_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 136401 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_ADD_F32), |
| 136402 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136403 | GIR_RootConstrainSelectedInstOperands, |
| 136404 | // GIR_Coverage, 90, |
| 136405 | GIR_Done, |
| 136406 | // Label 6493: @440360 |
| 136407 | GIM_Try, /*On fail goto*//*Label 6494*/ GIMT_Encode4(440420), // Rule ID 721 // |
| 136408 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136410 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136411 | // (strict_fadd:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64), |
| 136413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136420 | GIR_RootConstrainSelectedInstOperands, |
| 136421 | // GIR_Coverage, 721, |
| 136422 | GIR_EraseRootFromParent_Done, |
| 136423 | // Label 6494: @440420 |
| 136424 | GIM_Try, /*On fail goto*//*Label 6495*/ GIMT_Encode4(440480), // Rule ID 8051 // |
| 136425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136427 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136428 | // (strict_fadd:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F32_e64), |
| 136430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136437 | GIR_RootConstrainSelectedInstOperands, |
| 136438 | // GIR_Coverage, 8051, |
| 136439 | GIR_EraseRootFromParent_Done, |
| 136440 | // Label 6495: @440480 |
| 136441 | GIM_Reject, |
| 136442 | // Label 6492: @440481 |
| 136443 | GIM_Reject, |
| 136444 | // Label 6481: @440482 |
| 136445 | GIM_Try, /*On fail goto*//*Label 6496*/ GIMT_Encode4(440734), |
| 136446 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 136447 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 136448 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 136449 | GIM_Try, /*On fail goto*//*Label 6497*/ GIMT_Encode4(440556), // Rule ID 835 // |
| 136450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 136451 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136453 | // (strict_fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64), |
| 136455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136458 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136459 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136462 | GIR_RootConstrainSelectedInstOperands, |
| 136463 | // GIR_Coverage, 835, |
| 136464 | GIR_EraseRootFromParent_Done, |
| 136465 | // Label 6497: @440556 |
| 136466 | GIM_Try, /*On fail goto*//*Label 6498*/ GIMT_Encode4(440615), // Rule ID 853 // |
| 136467 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 136468 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136469 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136470 | // (strict_fadd:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136471 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64), |
| 136472 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136475 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136478 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136479 | GIR_RootConstrainSelectedInstOperands, |
| 136480 | // GIR_Coverage, 853, |
| 136481 | GIR_EraseRootFromParent_Done, |
| 136482 | // Label 6498: @440615 |
| 136483 | GIM_Try, /*On fail goto*//*Label 6499*/ GIMT_Encode4(440674), // Rule ID 8080 // |
| 136484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 136485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136486 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136487 | // (strict_fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F64_pseudo_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_pseudo_e64), |
| 136489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136494 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136496 | GIR_RootConstrainSelectedInstOperands, |
| 136497 | // GIR_Coverage, 8080, |
| 136498 | GIR_EraseRootFromParent_Done, |
| 136499 | // Label 6499: @440674 |
| 136500 | GIM_Try, /*On fail goto*//*Label 6500*/ GIMT_Encode4(440733), // Rule ID 8093 // |
| 136501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 136502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136504 | // (strict_fadd:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_ADD_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_ADD_F64_e64), |
| 136506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136510 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136513 | GIR_RootConstrainSelectedInstOperands, |
| 136514 | // GIR_Coverage, 8093, |
| 136515 | GIR_EraseRootFromParent_Done, |
| 136516 | // Label 6500: @440733 |
| 136517 | GIM_Reject, |
| 136518 | // Label 6496: @440734 |
| 136519 | GIM_Reject, |
| 136520 | // Label 6482: @440735 |
| 136521 | GIM_Try, /*On fail goto*//*Label 6501*/ GIMT_Encode4(440806), // Rule ID 957 // |
| 136522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 136523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 136524 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 136526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 136527 | // (strict_fadd:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 136528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F16), |
| 136529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136534 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136535 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136536 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136537 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136538 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136539 | GIR_RootConstrainSelectedInstOperands, |
| 136540 | // GIR_Coverage, 957, |
| 136541 | GIR_EraseRootFromParent_Done, |
| 136542 | // Label 6501: @440806 |
| 136543 | GIM_Reject, |
| 136544 | // Label 6483: @440807 |
| 136545 | GIM_Try, /*On fail goto*//*Label 6502*/ GIMT_Encode4(440881), // Rule ID 1085 // |
| 136546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 136547 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 136548 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 136549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 136550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 136551 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 136552 | // (strict_fadd:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_ADD_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1) |
| 136553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_ADD_F32), |
| 136554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136558 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136559 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136560 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136561 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136562 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136563 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136564 | GIR_RootConstrainSelectedInstOperands, |
| 136565 | // GIR_Coverage, 1085, |
| 136566 | GIR_EraseRootFromParent_Done, |
| 136567 | // Label 6502: @440881 |
| 136568 | GIM_Reject, |
| 136569 | // Label 6484: @440882 |
| 136570 | GIM_Reject, |
| 136571 | // Label 103: @440883 |
| 136572 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 6505*/ GIMT_Encode4(441246), |
| 136573 | /*GILLT_s16*//*Label 6503*/ GIMT_Encode4(440902), |
| 136574 | /*GILLT_s32*//*Label 6504*/ GIMT_Encode4(441138), |
| 136575 | // Label 6503: @440902 |
| 136576 | GIM_Try, /*On fail goto*//*Label 6506*/ GIMT_Encode4(441137), |
| 136577 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 136578 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 136579 | GIM_Try, /*On fail goto*//*Label 6507*/ GIMT_Encode4(440948), // Rule ID 106 // |
| 136580 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136581 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136582 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136583 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136584 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18522), |
| 136585 | // (strict_fsub:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18522>> => (S_SUB_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 136586 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F16), |
| 136587 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136588 | GIR_RootConstrainSelectedInstOperands, |
| 136589 | // GIR_Coverage, 106, |
| 136590 | GIR_Done, |
| 136591 | // Label 6507: @440948 |
| 136592 | GIM_Try, /*On fail goto*//*Label 6508*/ GIMT_Encode4(441011), // Rule ID 795 // |
| 136593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136594 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136597 | // (strict_fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_e64), |
| 136599 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136606 | GIR_RootConstrainSelectedInstOperands, |
| 136607 | // GIR_Coverage, 795, |
| 136608 | GIR_EraseRootFromParent_Done, |
| 136609 | // Label 6508: @441011 |
| 136610 | GIM_Try, /*On fail goto*//*Label 6509*/ GIMT_Encode4(441074), // Rule ID 799 // |
| 136611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136612 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136615 | // (strict_fsub:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_fake16_e64), |
| 136617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136624 | GIR_RootConstrainSelectedInstOperands, |
| 136625 | // GIR_Coverage, 799, |
| 136626 | GIR_EraseRootFromParent_Done, |
| 136627 | // Label 6509: @441074 |
| 136628 | GIM_Try, /*On fail goto*//*Label 6510*/ GIMT_Encode4(441136), // Rule ID 797 // |
| 136629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 136630 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 136631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136633 | // (strict_fsub:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 136634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F16_t16_e64), |
| 136635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136640 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136641 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136642 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136643 | GIR_RootConstrainSelectedInstOperands, |
| 136644 | // GIR_Coverage, 797, |
| 136645 | GIR_EraseRootFromParent_Done, |
| 136646 | // Label 6510: @441136 |
| 136647 | GIM_Reject, |
| 136648 | // Label 6506: @441137 |
| 136649 | GIM_Reject, |
| 136650 | // Label 6504: @441138 |
| 136651 | GIM_Try, /*On fail goto*//*Label 6511*/ GIMT_Encode4(441245), |
| 136652 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 136653 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 136654 | GIM_Try, /*On fail goto*//*Label 6512*/ GIMT_Encode4(441184), // Rule ID 108 // |
| 136655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136657 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136658 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136659 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18522), |
| 136660 | // (strict_fsub:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18522>> => (S_SUB_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 136661 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_SUB_F32), |
| 136662 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136663 | GIR_RootConstrainSelectedInstOperands, |
| 136664 | // GIR_Coverage, 108, |
| 136665 | GIR_Done, |
| 136666 | // Label 6512: @441184 |
| 136667 | GIM_Try, /*On fail goto*//*Label 6513*/ GIMT_Encode4(441244), // Rule ID 723 // |
| 136668 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136669 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136670 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136671 | // (strict_fsub:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_SUB_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_SUB_F32_e64), |
| 136673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136680 | GIR_RootConstrainSelectedInstOperands, |
| 136681 | // GIR_Coverage, 723, |
| 136682 | GIR_EraseRootFromParent_Done, |
| 136683 | // Label 6513: @441244 |
| 136684 | GIM_Reject, |
| 136685 | // Label 6511: @441245 |
| 136686 | GIM_Reject, |
| 136687 | // Label 6505: @441246 |
| 136688 | GIM_Reject, |
| 136689 | // Label 104: @441247 |
| 136690 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 6519*/ GIMT_Encode4(442514), |
| 136691 | /*GILLT_s16*//*Label 6514*/ GIMT_Encode4(441278), |
| 136692 | /*GILLT_s32*//*Label 6515*/ GIMT_Encode4(441640), |
| 136693 | /*GILLT_s64*//*Label 6516*/ GIMT_Encode4(441808), |
| 136694 | /*GILLT_v2s16*//*Label 6517*/ GIMT_Encode4(442367), |
| 136695 | /*GILLT_v2s32*//*Label 6518*/ GIMT_Encode4(442439), |
| 136696 | // Label 6514: @441278 |
| 136697 | GIM_Try, /*On fail goto*//*Label 6520*/ GIMT_Encode4(441639), |
| 136698 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 136699 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 136700 | GIM_Try, /*On fail goto*//*Label 6521*/ GIMT_Encode4(441324), // Rule ID 100 // |
| 136701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136702 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136703 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136704 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136705 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18521), |
| 136706 | // (strict_fmul:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1)<<P:Predicate_anonymous_18521>> => (S_MUL_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1) |
| 136707 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F16), |
| 136708 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136709 | GIR_RootConstrainSelectedInstOperands, |
| 136710 | // GIR_Coverage, 100, |
| 136711 | GIR_Done, |
| 136712 | // Label 6521: @441324 |
| 136713 | GIM_Try, /*On fail goto*//*Label 6522*/ GIMT_Encode4(441387), // Rule ID 801 // |
| 136714 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136715 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136716 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136718 | // (strict_fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 136720 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136727 | GIR_RootConstrainSelectedInstOperands, |
| 136728 | // GIR_Coverage, 801, |
| 136729 | GIR_EraseRootFromParent_Done, |
| 136730 | // Label 6522: @441387 |
| 136731 | GIM_Try, /*On fail goto*//*Label 6523*/ GIMT_Encode4(441450), // Rule ID 805 // |
| 136732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136733 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136734 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136736 | // (strict_fmul:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 136738 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136741 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136744 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136745 | GIR_RootConstrainSelectedInstOperands, |
| 136746 | // GIR_Coverage, 805, |
| 136747 | GIR_EraseRootFromParent_Done, |
| 136748 | // Label 6523: @441450 |
| 136749 | GIM_Try, /*On fail goto*//*Label 6524*/ GIMT_Encode4(441513), // Rule ID 8066 // |
| 136750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_NotHasTrue16BitInsts), |
| 136751 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136752 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136753 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136754 | // (strict_fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136755 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_e64), |
| 136756 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136761 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136763 | GIR_RootConstrainSelectedInstOperands, |
| 136764 | // GIR_Coverage, 8066, |
| 136765 | GIR_EraseRootFromParent_Done, |
| 136766 | // Label 6524: @441513 |
| 136767 | GIM_Try, /*On fail goto*//*Label 6525*/ GIMT_Encode4(441576), // Rule ID 8068 // |
| 136768 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 136769 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136770 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136772 | // (strict_fmul:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_fake16_e64), |
| 136774 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136776 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136781 | GIR_RootConstrainSelectedInstOperands, |
| 136782 | // GIR_Coverage, 8068, |
| 136783 | GIR_EraseRootFromParent_Done, |
| 136784 | // Label 6525: @441576 |
| 136785 | GIM_Try, /*On fail goto*//*Label 6526*/ GIMT_Encode4(441638), // Rule ID 803 // |
| 136786 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 136787 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 136788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 136790 | // (strict_fmul:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1) |
| 136791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F16_t16_e64), |
| 136792 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136797 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136798 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136800 | GIR_RootConstrainSelectedInstOperands, |
| 136801 | // GIR_Coverage, 803, |
| 136802 | GIR_EraseRootFromParent_Done, |
| 136803 | // Label 6526: @441638 |
| 136804 | GIM_Reject, |
| 136805 | // Label 6520: @441639 |
| 136806 | GIM_Reject, |
| 136807 | // Label 6515: @441640 |
| 136808 | GIM_Try, /*On fail goto*//*Label 6527*/ GIMT_Encode4(441807), |
| 136809 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 136810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 136811 | GIM_Try, /*On fail goto*//*Label 6528*/ GIMT_Encode4(441686), // Rule ID 96 // |
| 136812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 136813 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136814 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136815 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 136816 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18521), |
| 136817 | // (strict_fmul:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1)<<P:Predicate_anonymous_18521>> => (S_MUL_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1) |
| 136818 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_MUL_F32), |
| 136819 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 136820 | GIR_RootConstrainSelectedInstOperands, |
| 136821 | // GIR_Coverage, 96, |
| 136822 | GIR_Done, |
| 136823 | // Label 6528: @441686 |
| 136824 | GIM_Try, /*On fail goto*//*Label 6529*/ GIMT_Encode4(441746), // Rule ID 727 // |
| 136825 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136826 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 136828 | // (strict_fmul:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 136830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136831 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 136832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 136834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 136835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 136836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 136837 | GIR_RootConstrainSelectedInstOperands, |
| 136838 | // GIR_Coverage, 727, |
| 136839 | GIR_EraseRootFromParent_Done, |
| 136840 | // Label 6529: @441746 |
| 136841 | GIM_Try, /*On fail goto*//*Label 6530*/ GIMT_Encode4(441806), // Rule ID 8055 // |
| 136842 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 136843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 136845 | // (strict_fmul:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 136846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F32_e64), |
| 136847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 136849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 136850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 136851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 136852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 136853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 136854 | GIR_RootConstrainSelectedInstOperands, |
| 136855 | // GIR_Coverage, 8055, |
| 136856 | GIR_EraseRootFromParent_Done, |
| 136857 | // Label 6530: @441806 |
| 136858 | GIM_Reject, |
| 136859 | // Label 6527: @441807 |
| 136860 | GIM_Reject, |
| 136861 | // Label 6516: @441808 |
| 136862 | GIM_Try, /*On fail goto*//*Label 6531*/ GIMT_Encode4(442366), |
| 136863 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 136864 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 136865 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 136866 | GIM_Try, /*On fail goto*//*Label 6532*/ GIMT_Encode4(441897), // Rule ID 7426 // |
| 136867 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 136868 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 136869 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64), |
| 136870 | // MIs[1] Operand 1 |
| 136871 | // No operand predicates |
| 136872 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 136873 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136874 | // (strict_fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 136875 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 136876 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 136877 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136878 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 136879 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 136881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 136883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136884 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136886 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136887 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136888 | GIR_RootConstrainSelectedInstOperands, |
| 136889 | // GIR_Coverage, 7426, |
| 136890 | GIR_EraseRootFromParent_Done, |
| 136891 | // Label 6532: @441897 |
| 136892 | GIM_Try, /*On fail goto*//*Label 6533*/ GIMT_Encode4(441971), // Rule ID 11985 // |
| 136893 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 136894 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 136895 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_pos_pow2_prefer_ldexp_f64), |
| 136896 | // MIs[1] Operand 1 |
| 136897 | // No operand predicates |
| 136898 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 136899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 136900 | // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_pos_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_mods)) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_mods, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 136901 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 136902 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 136903 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136904 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 136905 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 136907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_mods |
| 136909 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 136910 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136911 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136912 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136913 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136914 | GIR_RootConstrainSelectedInstOperands, |
| 136915 | // GIR_Coverage, 11985, |
| 136916 | GIR_EraseRootFromParent_Done, |
| 136917 | // Label 6533: @441971 |
| 136918 | GIM_Try, /*On fail goto*//*Label 6534*/ GIMT_Encode4(442047), // Rule ID 7430 // |
| 136919 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 136920 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FABS), |
| 136921 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s64, |
| 136922 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 136923 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 136924 | GIM_CheckAPFloatImmPredicate, /*MI*/2, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 136925 | // MIs[2] Operand 1 |
| 136926 | // No operand predicates |
| 136927 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 136928 | // (strict_fmul:{ *:[f64] } (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0), (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 136929 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 136930 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 136931 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136932 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/2, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 136933 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 136935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136936 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 136937 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/1, /*OpIdx*/1, // src0 |
| 136938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136939 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136940 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136941 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136942 | GIR_RootConstrainSelectedInstOperands, |
| 136943 | // GIR_Coverage, 7430, |
| 136944 | GIR_EraseRootFromParent_Done, |
| 136945 | // Label 6534: @442047 |
| 136946 | GIM_Try, /*On fail goto*//*Label 6535*/ GIMT_Encode4(442123), // Rule ID 11989 // |
| 136947 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 136948 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 136949 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 136950 | // MIs[1] Operand 1 |
| 136951 | // No operand predicates |
| 136952 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/0, /*OpIdx*/2, // MIs[2] |
| 136953 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FABS), |
| 136954 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s64, |
| 136955 | GIM_CheckIsSafeToFold, /*NumInsns*/2, |
| 136956 | // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, (fabs:{ *:[f64] } f64:{ *:[f64] }:$src0)) => (V_LDEXP_F64_e64:{ *:[f64] } 3:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 136957 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 136958 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 136959 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136960 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 136961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 136963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136964 | GIR_AddImm8, /*InsnID*/0, /*Imm*/3, |
| 136965 | GIR_Copy, /*NewInsnID*/0, /*OldInsnID*/2, /*OpIdx*/1, // src0 |
| 136966 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136967 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136968 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136969 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136970 | GIR_RootConstrainSelectedInstOperands, |
| 136971 | // GIR_Coverage, 11989, |
| 136972 | GIR_EraseRootFromParent_Done, |
| 136973 | // Label 6535: @442123 |
| 136974 | GIM_Try, /*On fail goto*//*Label 6536*/ GIMT_Encode4(442185), // Rule ID 11987 // |
| 136975 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 136976 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 136977 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 136978 | // MIs[1] Operand 1 |
| 136979 | // No operand predicates |
| 136980 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 136981 | // (strict_fmul:{ *:[f64] } (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1, f64:{ *:[f64] }:$src0) => (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 136982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 136983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 136984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 136985 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 136986 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 136987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 136988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 136989 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 136990 | GIR_RootToRootCopy, /*OpIdx*/2, // src0 |
| 136991 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 136993 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136994 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 136995 | GIR_RootConstrainSelectedInstOperands, |
| 136996 | // GIR_Coverage, 11987, |
| 136997 | GIR_EraseRootFromParent_Done, |
| 136998 | // Label 6536: @442185 |
| 136999 | GIM_Try, /*On fail goto*//*Label 6537*/ GIMT_Encode4(442247), // Rule ID 7428 // |
| 137000 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/2, // MIs[1] |
| 137001 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_FCONSTANT), |
| 137002 | GIM_CheckAPFloatImmPredicate, /*MI*/1, /*Predicate*/GIMT_Encode2(GICXXPred_APFloat_Predicate_fpimm_neg_pow2_prefer_ldexp_f64), |
| 137003 | // MIs[1] Operand 1 |
| 137004 | // No operand predicates |
| 137005 | GIM_CheckIsSafeToFold, /*NumInsns*/1, |
| 137006 | // (strict_fmul:{ *:[f64] } f64:{ *:[f64] }:$src0, (fpimm:{ *:[f64] })<<P:Predicate_fpimm_neg_pow2_prefer_ldexp_f64>><<X:FPPow2ToExponentXForm>>:$src1) => (V_LDEXP_F64_e64:{ *:[f64] } 1:{ *:[i32] }, VSrc_b64:{ *:[f64] }:$src0, 0:{ *:[i32] }, (S_MOV_B32:{ *:[i16] } (FPPow2ToExponentXForm:{ *:[i32] } ?:{ *:[f64] }:$src1))) |
| 137007 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 137008 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::S_MOV_B32), |
| 137009 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137010 | GIR_CustomRenderer, /*InsnID*/1, /*OldInsnID*/1, /*Renderer*/GIMT_Encode2(GICR_renderFPPow2ToExponent), // src1 |
| 137011 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 137013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137014 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 137015 | GIR_RootToRootCopy, /*OpIdx*/1, // src0 |
| 137016 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137017 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 137018 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137019 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137020 | GIR_RootConstrainSelectedInstOperands, |
| 137021 | // GIR_Coverage, 7428, |
| 137022 | GIR_EraseRootFromParent_Done, |
| 137023 | // Label 6537: @442247 |
| 137024 | GIM_Try, /*On fail goto*//*Label 6538*/ GIMT_Encode4(442306), // Rule ID 855 // |
| 137025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 137026 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137028 | // (strict_fmul:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137029 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64), |
| 137030 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137037 | GIR_RootConstrainSelectedInstOperands, |
| 137038 | // GIR_Coverage, 855, |
| 137039 | GIR_EraseRootFromParent_Done, |
| 137040 | // Label 6538: @442306 |
| 137041 | GIM_Try, /*On fail goto*//*Label 6539*/ GIMT_Encode4(442365), // Rule ID 8095 // |
| 137042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 137043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 137044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137045 | // (strict_fmul:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_MUL_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137046 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MUL_F64_e64), |
| 137047 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 137049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 137050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 137051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 137052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 137053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 137054 | GIR_RootConstrainSelectedInstOperands, |
| 137055 | // GIR_Coverage, 8095, |
| 137056 | GIR_EraseRootFromParent_Done, |
| 137057 | // Label 6539: @442365 |
| 137058 | GIM_Reject, |
| 137059 | // Label 6531: @442366 |
| 137060 | GIM_Reject, |
| 137061 | // Label 6517: @442367 |
| 137062 | GIM_Try, /*On fail goto*//*Label 6540*/ GIMT_Encode4(442438), // Rule ID 959 // |
| 137063 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 137064 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 137065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137066 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137068 | // (strict_fmul:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MUL_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1) |
| 137069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F16), |
| 137070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137075 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137076 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137077 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137078 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137079 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137080 | GIR_RootConstrainSelectedInstOperands, |
| 137081 | // GIR_Coverage, 959, |
| 137082 | GIR_EraseRootFromParent_Done, |
| 137083 | // Label 6540: @442438 |
| 137084 | GIM_Reject, |
| 137085 | // Label 6518: @442439 |
| 137086 | GIM_Try, /*On fail goto*//*Label 6541*/ GIMT_Encode4(442513), // Rule ID 1083 // |
| 137087 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 137088 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 137089 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 137090 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137093 | // (strict_fmul:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_PK_MUL_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1) |
| 137094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MUL_F32), |
| 137095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137100 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137101 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137102 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137104 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137105 | GIR_RootConstrainSelectedInstOperands, |
| 137106 | // GIR_Coverage, 1083, |
| 137107 | GIR_EraseRootFromParent_Done, |
| 137108 | // Label 6541: @442513 |
| 137109 | GIM_Reject, |
| 137110 | // Label 6519: @442514 |
| 137111 | GIM_Reject, |
| 137112 | // Label 105: @442515 |
| 137113 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(13), /*)*//*default:*//*Label 6547*/ GIMT_Encode4(443402), |
| 137114 | /*GILLT_s16*//*Label 6542*/ GIMT_Encode4(442546), |
| 137115 | /*GILLT_s32*//*Label 6543*/ GIMT_Encode4(442840), |
| 137116 | /*GILLT_s64*//*Label 6544*/ GIMT_Encode4(443049), |
| 137117 | /*GILLT_v2s16*//*Label 6545*/ GIMT_Encode4(443215), |
| 137118 | /*GILLT_v2s32*//*Label 6546*/ GIMT_Encode4(443307), |
| 137119 | // Label 6542: @442546 |
| 137120 | GIM_Try, /*On fail goto*//*Label 6548*/ GIMT_Encode4(442839), |
| 137121 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 137122 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 137123 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 137124 | GIM_Try, /*On fail goto*//*Label 6549*/ GIMT_Encode4(442599), // Rule ID 114 // |
| 137125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 137126 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137127 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137128 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137129 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137130 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18524), |
| 137131 | // (strict_fma:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2)<<P:Predicate_anonymous_18524>> => (S_FMAC_F16:{ *:[f16] } SSrc_f16:{ *:[f16] }:$src0, SSrc_f16:{ *:[f16] }:$src1, SReg_32:{ *:[f16] }:$src2) |
| 137132 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F16), |
| 137133 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 137134 | GIR_RootConstrainSelectedInstOperands, |
| 137135 | // GIR_Coverage, 114, |
| 137136 | GIR_Done, |
| 137137 | // Label 6549: @442599 |
| 137138 | GIM_Try, /*On fail goto*//*Label 6550*/ GIMT_Encode4(442679), // Rule ID 917 // |
| 137139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only), |
| 137140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137143 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137144 | // (strict_fma:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137145 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64), |
| 137146 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137150 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137155 | GIR_RootConstrainSelectedInstOperands, |
| 137156 | // GIR_Coverage, 917, |
| 137157 | GIR_EraseRootFromParent_Done, |
| 137158 | // Label 6550: @442679 |
| 137159 | GIM_Try, /*On fail goto*//*Label 6551*/ GIMT_Encode4(442759), // Rule ID 8110 // |
| 137160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_Has16BitInsts_isGFX8Only), |
| 137161 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 137163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137165 | // (strict_fma:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_e64), |
| 137167 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 137169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 137170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 137171 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 137172 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137174 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 137175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 137176 | GIR_RootConstrainSelectedInstOperands, |
| 137177 | // GIR_Coverage, 8110, |
| 137178 | GIR_EraseRootFromParent_Done, |
| 137179 | // Label 6551: @442759 |
| 137180 | GIM_Try, /*On fail goto*//*Label 6552*/ GIMT_Encode4(442838), // Rule ID 921 // |
| 137181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 137182 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 137184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 137185 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 137186 | // (strict_fma:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F16_gfx9_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 137187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F16_gfx9_e64), |
| 137188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137191 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137194 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137195 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137196 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137197 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137198 | GIR_RootConstrainSelectedInstOperands, |
| 137199 | // GIR_Coverage, 921, |
| 137200 | GIR_EraseRootFromParent_Done, |
| 137201 | // Label 6552: @442838 |
| 137202 | GIM_Reject, |
| 137203 | // Label 6548: @442839 |
| 137204 | GIM_Reject, |
| 137205 | // Label 6543: @442840 |
| 137206 | GIM_Try, /*On fail goto*//*Label 6553*/ GIMT_Encode4(443048), |
| 137207 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 137208 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 137209 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 137210 | GIM_Try, /*On fail goto*//*Label 6554*/ GIMT_Encode4(442893), // Rule ID 112 // |
| 137211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasSALUFloatInsts), |
| 137212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137213 | GIM_RootCheckRegBankForClass, /*Op*/1, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137214 | GIM_RootCheckRegBankForClass, /*Op*/2, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137215 | GIM_RootCheckRegBankForClass, /*Op*/3, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 137216 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18524), |
| 137217 | // (strict_fma:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2)<<P:Predicate_anonymous_18524>> => (S_FMAC_F32:{ *:[f32] } SSrc_f32:{ *:[f32] }:$src0, SSrc_f32:{ *:[f32] }:$src1, SReg_32:{ *:[f32] }:$src2) |
| 137218 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FMAC_F32), |
| 137219 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 137220 | GIR_RootConstrainSelectedInstOperands, |
| 137221 | // GIR_Coverage, 112, |
| 137222 | GIR_Done, |
| 137223 | // Label 6554: @442893 |
| 137224 | GIM_Try, /*On fail goto*//*Label 6555*/ GIMT_Encode4(442970), // Rule ID 848 // |
| 137225 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137229 | // (strict_fma:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64), |
| 137231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137237 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137240 | GIR_RootConstrainSelectedInstOperands, |
| 137241 | // GIR_Coverage, 848, |
| 137242 | GIR_EraseRootFromParent_Done, |
| 137243 | // Label 6555: @442970 |
| 137244 | GIM_Try, /*On fail goto*//*Label 6556*/ GIMT_Encode4(443047), // Rule ID 8089 // |
| 137245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 137247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137249 | // (strict_fma:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F32_e64), |
| 137251 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 137253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 137254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 137255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 137256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137257 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 137259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 137260 | GIR_RootConstrainSelectedInstOperands, |
| 137261 | // GIR_Coverage, 8089, |
| 137262 | GIR_EraseRootFromParent_Done, |
| 137263 | // Label 6556: @443047 |
| 137264 | GIM_Reject, |
| 137265 | // Label 6553: @443048 |
| 137266 | GIM_Reject, |
| 137267 | // Label 6544: @443049 |
| 137268 | GIM_Try, /*On fail goto*//*Label 6557*/ GIMT_Encode4(443214), |
| 137269 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 137270 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 137271 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s64, |
| 137272 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137273 | GIM_Try, /*On fail goto*//*Label 6558*/ GIMT_Encode4(443140), // Rule ID 851 // |
| 137274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137275 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137277 | // (strict_fma:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64), |
| 137279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137284 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137288 | GIR_RootConstrainSelectedInstOperands, |
| 137289 | // GIR_Coverage, 851, |
| 137290 | GIR_EraseRootFromParent_Done, |
| 137291 | // Label 6558: @443140 |
| 137292 | GIM_Try, /*On fail goto*//*Label 6559*/ GIMT_Encode4(443213), // Rule ID 8091 // |
| 137293 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 137294 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 137296 | // (strict_fma:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_FMA_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f64:{ *:[f64] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f64:{ *:[f64] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137297 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_F64_e64), |
| 137298 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src0_modifiers |
| 137300 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src0 |
| 137301 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src1_modifiers |
| 137302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src1 |
| 137303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137305 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/2, // clamp |
| 137306 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/3, // omod |
| 137307 | GIR_RootConstrainSelectedInstOperands, |
| 137308 | // GIR_Coverage, 8091, |
| 137309 | GIR_EraseRootFromParent_Done, |
| 137310 | // Label 6559: @443213 |
| 137311 | GIM_Reject, |
| 137312 | // Label 6557: @443214 |
| 137313 | GIM_Reject, |
| 137314 | // Label 6545: @443215 |
| 137315 | GIM_Try, /*On fail goto*//*Label 6560*/ GIMT_Encode4(443306), // Rule ID 955 // |
| 137316 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 137317 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s16, |
| 137318 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s16, |
| 137319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137322 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137323 | // (strict_fma:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_PK_FMA_F16:{ *:[v2f16] } i32:{ *:[i32] }:$src0_modifiers, v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f16:{ *:[v2f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f16:{ *:[v2f16] }:$src2) |
| 137324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F16), |
| 137325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137329 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137332 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137333 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137334 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137335 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137336 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137337 | GIR_RootConstrainSelectedInstOperands, |
| 137338 | // GIR_Coverage, 955, |
| 137339 | GIR_EraseRootFromParent_Done, |
| 137340 | // Label 6560: @443306 |
| 137341 | GIM_Reject, |
| 137342 | // Label 6546: @443307 |
| 137343 | GIM_Try, /*On fail goto*//*Label 6561*/ GIMT_Encode4(443401), // Rule ID 1081 // |
| 137344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedFP32Ops), |
| 137345 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s32, |
| 137346 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 137347 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v2s32, |
| 137348 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3pmods), |
| 137352 | // (strict_fma:{ *:[v2f32] } (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3PMods:{ *:[v2f32] } v2f32:{ *:[v2f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_PK_FMA_F32:{ *:[v2f32] } i32:{ *:[i32] }:$src0_modifiers, v2f32:{ *:[v2f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, v2f32:{ *:[v2f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, v2f32:{ *:[v2f32] }:$src2) |
| 137353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_FMA_F32), |
| 137354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 137360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 137361 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137362 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137363 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137364 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137365 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137366 | GIR_RootConstrainSelectedInstOperands, |
| 137367 | // GIR_Coverage, 1081, |
| 137368 | GIR_EraseRootFromParent_Done, |
| 137369 | // Label 6561: @443401 |
| 137370 | GIM_Reject, |
| 137371 | // Label 6547: @443402 |
| 137372 | GIM_Reject, |
| 137373 | // Label 106: @443403 |
| 137374 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(11), /*)*//*default:*//*Label 6565*/ GIMT_Encode4(443695), |
| 137375 | /*GILLT_s16*//*Label 6562*/ GIMT_Encode4(443426), |
| 137376 | /*GILLT_s32*//*Label 6563*/ GIMT_Encode4(443561), |
| 137377 | /*GILLT_s64*//*Label 6564*/ GIMT_Encode4(443628), |
| 137378 | // Label 6562: @443426 |
| 137379 | GIM_Try, /*On fail goto*//*Label 6566*/ GIMT_Encode4(443560), |
| 137380 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 137381 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 137382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137383 | GIM_Try, /*On fail goto*//*Label 6567*/ GIMT_Encode4(443500), // Rule ID 2145 // |
| 137384 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 137385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137387 | // (strict_fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod) |
| 137388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_e64), |
| 137389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137396 | GIR_RootConstrainSelectedInstOperands, |
| 137397 | // GIR_Coverage, 2145, |
| 137398 | GIR_EraseRootFromParent_Done, |
| 137399 | // Label 6567: @443500 |
| 137400 | GIM_Try, /*On fail goto*//*Label 6568*/ GIMT_Encode4(443559), // Rule ID 2147 // |
| 137401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasTrue16BitInsts), |
| 137402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137403 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137404 | // (strict_fldexp:{ *:[f16] } (VOP3Mods0:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods0:{ *:[i16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F16_t16_e64:{ *:[f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[f16] }:$src0, ?:{ *:[i32] }:$src1_modifiers, ?:{ *:[f16] }:$src1, ?:{ *:[i1] }:$clamp, ?:{ *:[i32] }:$omod) |
| 137405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F16_t16_e64), |
| 137406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137410 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137413 | GIR_RootConstrainSelectedInstOperands, |
| 137414 | // GIR_Coverage, 2147, |
| 137415 | GIR_EraseRootFromParent_Done, |
| 137416 | // Label 6568: @443559 |
| 137417 | GIM_Reject, |
| 137418 | // Label 6566: @443560 |
| 137419 | GIM_Reject, |
| 137420 | // Label 6563: @443561 |
| 137421 | GIM_Try, /*On fail goto*//*Label 6569*/ GIMT_Encode4(443627), // Rule ID 757 // |
| 137422 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 137423 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 137424 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137427 | // (strict_fldexp:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F32_e64), |
| 137429 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137435 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137436 | GIR_RootConstrainSelectedInstOperands, |
| 137437 | // GIR_Coverage, 757, |
| 137438 | GIR_EraseRootFromParent_Done, |
| 137439 | // Label 6569: @443627 |
| 137440 | GIM_Reject, |
| 137441 | // Label 6564: @443628 |
| 137442 | GIM_Try, /*On fail goto*//*Label 6570*/ GIMT_Encode4(443694), // Rule ID 898 // |
| 137443 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 137444 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 137445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137446 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 137447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 137448 | // (strict_fldexp:{ *:[f64] } (VOP3Mods0:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[i32] } i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_LDEXP_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i32:{ *:[i32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 137449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_LDEXP_F64_e64), |
| 137450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137451 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 137452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 137453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 137454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 137455 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 137456 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 137457 | GIR_RootConstrainSelectedInstOperands, |
| 137458 | // GIR_Coverage, 898, |
| 137459 | GIR_EraseRootFromParent_Done, |
| 137460 | // Label 6570: @443694 |
| 137461 | GIM_Reject, |
| 137462 | // Label 6565: @443695 |
| 137463 | GIM_Reject, |
| 137464 | // Label 107: @443696 |
| 137465 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6573*/ GIMT_Encode4(445975), |
| 137466 | /*GILLT_s32*//*Label 6571*/ GIMT_Encode4(443715), |
| 137467 | /*GILLT_s64*//*Label 6572*/ GIMT_Encode4(444845), |
| 137468 | // Label 6571: @443715 |
| 137469 | GIM_Try, /*On fail goto*//*Label 6574*/ GIMT_Encode4(444844), |
| 137470 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s32, |
| 137471 | GIM_Try, /*On fail goto*//*Label 6575*/ GIMT_Encode4(443785), // Rule ID 5474 // |
| 137472 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137473 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137474 | GIM_CheckHasNoUse, /*MI*/0, |
| 137475 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137477 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (BUFFER_ATOMIC_CMPSWAP_ADDR64 VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64), |
| 137479 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137482 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137484 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137486 | GIR_RootConstrainSelectedInstOperands, |
| 137487 | // GIR_Coverage, 5474, |
| 137488 | GIR_EraseRootFromParent_Done, |
| 137489 | // Label 6575: @443785 |
| 137490 | GIM_Try, /*On fail goto*//*Label 6576*/ GIMT_Encode4(443844), // Rule ID 5478 // |
| 137491 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137492 | GIM_CheckHasNoUse, /*MI*/0, |
| 137493 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137495 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64 VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64), |
| 137497 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137502 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137503 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137504 | GIR_RootConstrainSelectedInstOperands, |
| 137505 | // GIR_Coverage, 5478, |
| 137506 | GIR_EraseRootFromParent_Done, |
| 137507 | // Label 6576: @443844 |
| 137508 | GIM_Try, /*On fail goto*//*Label 6577*/ GIMT_Encode4(443959), // Rule ID 5250 // |
| 137509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137510 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137511 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137512 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137513 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137514 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 137515 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 137516 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 137517 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_ADDR64_RTN), |
| 137518 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137519 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137520 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137521 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137522 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137523 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137524 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137525 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137526 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137527 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137528 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137529 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137530 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137533 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 137534 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137535 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137536 | // GIR_Coverage, 5250, |
| 137537 | GIR_EraseRootFromParent_Done, |
| 137538 | // Label 6577: @443959 |
| 137539 | GIM_Try, /*On fail goto*//*Label 6578*/ GIMT_Encode4(444071), // Rule ID 5476 // |
| 137540 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137541 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137542 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137543 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137544 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 137545 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 137546 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 137547 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_ADDR64_RTN), |
| 137548 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137549 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137550 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137551 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137552 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137553 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137554 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137555 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137556 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137557 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137558 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137559 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137560 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137563 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 137564 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137565 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137566 | // GIR_Coverage, 5476, |
| 137567 | GIR_EraseRootFromParent_Done, |
| 137568 | // Label 6578: @444071 |
| 137569 | GIM_Try, /*On fail goto*//*Label 6579*/ GIMT_Encode4(444128), // Rule ID 5473 // |
| 137570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137571 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137572 | GIM_CheckHasNoUse, /*MI*/0, |
| 137573 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137575 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (BUFFER_ATOMIC_CMPSWAP_OFFSET VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET), |
| 137577 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137581 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137582 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137583 | GIR_RootConstrainSelectedInstOperands, |
| 137584 | // GIR_Coverage, 5473, |
| 137585 | GIR_EraseRootFromParent_Done, |
| 137586 | // Label 6579: @444128 |
| 137587 | GIM_Try, /*On fail goto*//*Label 6580*/ GIMT_Encode4(444182), // Rule ID 5477 // |
| 137588 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137589 | GIM_CheckHasNoUse, /*MI*/0, |
| 137590 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137591 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137592 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET), |
| 137594 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137598 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137599 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137600 | GIR_RootConstrainSelectedInstOperands, |
| 137601 | // GIR_Coverage, 5477, |
| 137602 | GIR_EraseRootFromParent_Done, |
| 137603 | // Label 6580: @444182 |
| 137604 | GIM_Try, /*On fail goto*//*Label 6581*/ GIMT_Encode4(444292), // Rule ID 5249 // |
| 137605 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137606 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137607 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137608 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137609 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137610 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 137611 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 137612 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 137613 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN), |
| 137614 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137615 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137616 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137617 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137618 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137619 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137620 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137621 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137622 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137623 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137624 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137625 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137628 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 137629 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137630 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137631 | // GIR_Coverage, 5249, |
| 137632 | GIR_EraseRootFromParent_Done, |
| 137633 | // Label 6581: @444292 |
| 137634 | GIM_Try, /*On fail goto*//*Label 6582*/ GIMT_Encode4(444399), // Rule ID 5475 // |
| 137635 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137636 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137637 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137639 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (EXTRACT_SUBREG:{ *:[i32] } (COPY_TO_REGCLASS:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN:{ *:[i64] } VReg_64:{ *:[v2i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_64:{ *:[i32] }), sub0:{ *:[i32] }) |
| 137640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s32, |
| 137641 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 137642 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN), |
| 137643 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137644 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137645 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137646 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137647 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137648 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137649 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137650 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137651 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137652 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137653 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137654 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137655 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137656 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137657 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 137658 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 137659 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137660 | // GIR_Coverage, 5475, |
| 137661 | GIR_EraseRootFromParent_Done, |
| 137662 | // Label 6582: @444399 |
| 137663 | GIM_Try, /*On fail goto*//*Label 6583*/ GIMT_Encode4(444456), // Rule ID 3647 // |
| 137664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 137665 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137666 | GIM_CheckHasNoUse, /*MI*/0, |
| 137667 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 137669 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (GLOBAL_ATOMIC_CMPSWAP_SADDR ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 137670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR), |
| 137671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 137672 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 137674 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137675 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137676 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137677 | GIR_RootConstrainSelectedInstOperands, |
| 137678 | // GIR_Coverage, 3647, |
| 137679 | GIR_EraseRootFromParent_Done, |
| 137680 | // Label 6583: @444456 |
| 137681 | GIM_Try, /*On fail goto*//*Label 6584*/ GIMT_Encode4(444517), // Rule ID 3649 // |
| 137682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 137683 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137684 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 137685 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137686 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 137687 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN:{ *:[i32] } ?:{ *:[i32] }:$voffset, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 137688 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_SADDR_RTN), |
| 137689 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 137691 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 137693 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137694 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 137695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137696 | GIR_RootConstrainSelectedInstOperands, |
| 137697 | // GIR_Coverage, 3649, |
| 137698 | GIR_EraseRootFromParent_Done, |
| 137699 | // Label 6584: @444517 |
| 137700 | GIM_Try, /*On fail goto*//*Label 6585*/ GIMT_Encode4(444569), // Rule ID 3646 // |
| 137701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 137702 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137703 | GIM_CheckHasNoUse, /*MI*/0, |
| 137704 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 137706 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (GLOBAL_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP), |
| 137708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137709 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137711 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137713 | GIR_RootConstrainSelectedInstOperands, |
| 137714 | // GIR_Coverage, 3646, |
| 137715 | GIR_EraseRootFromParent_Done, |
| 137716 | // Label 6585: @444569 |
| 137717 | GIM_Try, /*On fail goto*//*Label 6586*/ GIMT_Encode4(444625), // Rule ID 3648 // |
| 137718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 137719 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137720 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 137721 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 137723 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (GLOBAL_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_RTN), |
| 137725 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137727 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137729 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 137730 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137731 | GIR_RootConstrainSelectedInstOperands, |
| 137732 | // GIR_Coverage, 3648, |
| 137733 | GIR_EraseRootFromParent_Done, |
| 137734 | // Label 6586: @444625 |
| 137735 | GIM_Try, /*On fail goto*//*Label 6587*/ GIMT_Encode4(444678), // Rule ID 3309 // |
| 137736 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 137737 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137738 | GIM_CheckHasNoUse, /*MI*/0, |
| 137739 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 137741 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_noret_i32>> => (FLAT_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP), |
| 137743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137744 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137746 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137747 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137748 | GIR_RootConstrainSelectedInstOperands, |
| 137749 | // GIR_Coverage, 3309, |
| 137750 | GIR_EraseRootFromParent_Done, |
| 137751 | // Label 6587: @444678 |
| 137752 | GIM_Try, /*On fail goto*//*Label 6588*/ GIMT_Encode4(444730), // Rule ID 3369 // |
| 137753 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 137754 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137755 | GIM_CheckHasNoUse, /*MI*/0, |
| 137756 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137757 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 137758 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i32>> => (FLAT_ATOMIC_CMPSWAP VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP), |
| 137760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137761 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137763 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137765 | GIR_RootConstrainSelectedInstOperands, |
| 137766 | // GIR_Coverage, 3369, |
| 137767 | GIR_EraseRootFromParent_Done, |
| 137768 | // Label 6588: @444730 |
| 137769 | GIM_Try, /*On fail goto*//*Label 6589*/ GIMT_Encode4(444787), // Rule ID 3308 // |
| 137770 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 137771 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 137773 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 137775 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_i32>> => (FLAT_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN), |
| 137777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137779 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137781 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 137782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137783 | GIR_RootConstrainSelectedInstOperands, |
| 137784 | // GIR_Coverage, 3308, |
| 137785 | GIR_EraseRootFromParent_Done, |
| 137786 | // Label 6589: @444787 |
| 137787 | GIM_Try, /*On fail goto*//*Label 6590*/ GIMT_Encode4(444843), // Rule ID 3368 // |
| 137788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 137789 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 137791 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137792 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 137793 | // (AMDGPUatomic_cmp_swap:{ *:[i32] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i32:{ *:[v2i32] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i32>> => (FLAT_ATOMIC_CMPSWAP_RTN:{ *:[i32] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15875:{ *:[v2i32] }:$data, ?:{ *:[i32] }:$offset) |
| 137794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_RTN), |
| 137795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 137796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 137797 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 137798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 137799 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 137800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137801 | GIR_RootConstrainSelectedInstOperands, |
| 137802 | // GIR_Coverage, 3368, |
| 137803 | GIR_EraseRootFromParent_Done, |
| 137804 | // Label 6590: @444843 |
| 137805 | GIM_Reject, |
| 137806 | // Label 6574: @444844 |
| 137807 | GIM_Reject, |
| 137808 | // Label 6572: @444845 |
| 137809 | GIM_Try, /*On fail goto*//*Label 6591*/ GIMT_Encode4(445974), |
| 137810 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v2s64, |
| 137811 | GIM_Try, /*On fail goto*//*Label 6592*/ GIMT_Encode4(444915), // Rule ID 5482 // |
| 137812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137813 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137814 | GIM_CheckHasNoUse, /*MI*/0, |
| 137815 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137817 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (BUFFER_ATOMIC_CMPSWAP_X2_ADDR64 VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64), |
| 137819 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137823 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137824 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137825 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137826 | GIR_RootConstrainSelectedInstOperands, |
| 137827 | // GIR_Coverage, 5482, |
| 137828 | GIR_EraseRootFromParent_Done, |
| 137829 | // Label 6592: @444915 |
| 137830 | GIM_Try, /*On fail goto*//*Label 6593*/ GIMT_Encode4(444974), // Rule ID 5486 // |
| 137831 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137832 | GIM_CheckHasNoUse, /*MI*/0, |
| 137833 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137834 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137835 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64 VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137836 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64), |
| 137837 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137842 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137843 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137844 | GIR_RootConstrainSelectedInstOperands, |
| 137845 | // GIR_Coverage, 5486, |
| 137846 | GIR_EraseRootFromParent_Done, |
| 137847 | // Label 6593: @444974 |
| 137848 | GIM_Try, /*On fail goto*//*Label 6594*/ GIMT_Encode4(445089), // Rule ID 5480 // |
| 137849 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137850 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137851 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137852 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137854 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] }) |
| 137855 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 137856 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 137857 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_ADDR64_RTN), |
| 137858 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137859 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137860 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137861 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137862 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137863 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137864 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137865 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137866 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137867 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137868 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137869 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137870 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137873 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 137874 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137875 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137876 | // GIR_Coverage, 5480, |
| 137877 | GIR_EraseRootFromParent_Done, |
| 137878 | // Label 6594: @445089 |
| 137879 | GIM_Try, /*On fail goto*//*Label 6595*/ GIMT_Encode4(445201), // Rule ID 5484 // |
| 137880 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137882 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_addr64), |
| 137884 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFAddr64:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, VReg_64:{ *:[i64] }:$vaddr, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] }) |
| 137885 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 137886 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 137887 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_ADDR64_RTN), |
| 137888 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137889 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137890 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // vaddr |
| 137891 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137892 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // soffset |
| 137893 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // offset |
| 137894 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137895 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137896 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137897 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137898 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137899 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137900 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137903 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 137904 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137905 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137906 | // GIR_Coverage, 5484, |
| 137907 | GIR_EraseRootFromParent_Done, |
| 137908 | // Label 6595: @445201 |
| 137909 | GIM_Try, /*On fail goto*//*Label 6596*/ GIMT_Encode4(445258), // Rule ID 5481 // |
| 137910 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137911 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137912 | GIM_CheckHasNoUse, /*MI*/0, |
| 137913 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137915 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET), |
| 137917 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137921 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137923 | GIR_RootConstrainSelectedInstOperands, |
| 137924 | // GIR_Coverage, 5481, |
| 137925 | GIR_EraseRootFromParent_Done, |
| 137926 | // Label 6596: @445258 |
| 137927 | GIM_Try, /*On fail goto*//*Label 6597*/ GIMT_Encode4(445312), // Rule ID 5485 // |
| 137928 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137929 | GIM_CheckHasNoUse, /*MI*/0, |
| 137930 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137932 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset) |
| 137933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET), |
| 137934 | GIR_RootToRootCopy, /*OpIdx*/2, // vdata_in |
| 137935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 137939 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137940 | GIR_RootConstrainSelectedInstOperands, |
| 137941 | // GIR_Coverage, 5485, |
| 137942 | GIR_EraseRootFromParent_Done, |
| 137943 | // Label 6597: @445312 |
| 137944 | GIM_Try, /*On fail goto*//*Label 6598*/ GIMT_Encode4(445422), // Rule ID 5479 // |
| 137945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 137946 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137947 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137948 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137949 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137950 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] }) |
| 137951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 137952 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 137953 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN), |
| 137954 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137955 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137956 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137957 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137958 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137959 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137960 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137961 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137962 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137963 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137964 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137965 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137966 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137967 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137968 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 137969 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137970 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137971 | // GIR_Coverage, 5479, |
| 137972 | GIR_EraseRootFromParent_Done, |
| 137973 | // Label 6598: @445422 |
| 137974 | GIM_Try, /*On fail goto*//*Label 6599*/ GIMT_Encode4(445529), // Rule ID 5483 // |
| 137975 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 137976 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 137977 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 137978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_mubuf_offset), |
| 137979 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (MUBUFOffset:{ *:[iPTR] } v4i32:{ *:[v4i32] }:$srsrc, i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$vdata_in)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (EXTRACT_SUBREG:{ *:[i64] } (COPY_TO_REGCLASS:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN:{ *:[v8i16] } VReg_128:{ *:[v2i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$srsrc, SCSrc_b32:{ *:[i32] }:$soffset, Offset:{ *:[i32] }:$offset), VReg_128:{ *:[i32] }), sub0_sub1:{ *:[i32] }) |
| 137980 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 137981 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 137982 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN), |
| 137983 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137984 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // vdata_in |
| 137985 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // srsrc |
| 137986 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // soffset |
| 137987 | GIR_ComplexSubOperandRenderer, /*InsnID*/2, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 137988 | GIR_AddImm8, /*InsnID*/2, /*Imm*/1, |
| 137989 | GIR_MergeMemOperands, /*InsnID*/2, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 137990 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 137991 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137992 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 137993 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 137994 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 137995 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 137996 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 137997 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 137998 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 137999 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 138000 | // GIR_Coverage, 5483, |
| 138001 | GIR_EraseRootFromParent_Done, |
| 138002 | // Label 6599: @445529 |
| 138003 | GIM_Try, /*On fail goto*//*Label 6600*/ GIMT_Encode4(445586), // Rule ID 3703 // |
| 138004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 138005 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138006 | GIM_CheckHasNoUse, /*MI*/0, |
| 138007 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 138009 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (GLOBAL_ATOMIC_CMPSWAP_X2_SADDR ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 138010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR), |
| 138011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 138012 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 138014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 138015 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 138016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138017 | GIR_RootConstrainSelectedInstOperands, |
| 138018 | // GIR_Coverage, 3703, |
| 138019 | GIR_EraseRootFromParent_Done, |
| 138020 | // Label 6600: @445586 |
| 138021 | GIM_Try, /*On fail goto*//*Label 6601*/ GIMT_Encode4(445647), // Rule ID 3705 // |
| 138022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 138023 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138024 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138025 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138026 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_saddr), |
| 138027 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalSAddr:{ *:[iPTR] } SReg_64:{ *:[i64] }:$saddr, VGPR_32:{ *:[i32] }:$voffset, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN:{ *:[i64] } ?:{ *:[i32] }:$voffset, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i64] }:$saddr, ?:{ *:[i32] }:$offset) |
| 138028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_SADDR_RTN), |
| 138029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 138030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // voffset |
| 138031 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138032 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // saddr |
| 138033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // offset |
| 138034 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 138035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138036 | GIR_RootConstrainSelectedInstOperands, |
| 138037 | // GIR_Coverage, 3705, |
| 138038 | GIR_EraseRootFromParent_Done, |
| 138039 | // Label 6601: @445647 |
| 138040 | GIM_Try, /*On fail goto*//*Label 6602*/ GIMT_Encode4(445699), // Rule ID 3702 // |
| 138041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 138042 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138043 | GIM_CheckHasNoUse, /*MI*/0, |
| 138044 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 138046 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (GLOBAL_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2), |
| 138048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138049 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138050 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138051 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 138052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138053 | GIR_RootConstrainSelectedInstOperands, |
| 138054 | // GIR_Coverage, 3702, |
| 138055 | GIR_EraseRootFromParent_Done, |
| 138056 | // Label 6602: @445699 |
| 138057 | GIM_Try, /*On fail goto*//*Label 6603*/ GIMT_Encode4(445755), // Rule ID 3704 // |
| 138058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatGlobalInsts), |
| 138059 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138060 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138061 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138062 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_global_offset), |
| 138063 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (GlobalOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (GLOBAL_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::GLOBAL_ATOMIC_CMPSWAP_X2_RTN), |
| 138065 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 138066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138067 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138069 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 138070 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138071 | GIR_RootConstrainSelectedInstOperands, |
| 138072 | // GIR_Coverage, 3704, |
| 138073 | GIR_EraseRootFromParent_Done, |
| 138074 | // Label 6603: @445755 |
| 138075 | GIM_Try, /*On fail goto*//*Label 6604*/ GIMT_Encode4(445808), // Rule ID 3335 // |
| 138076 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 138077 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138078 | GIM_CheckHasNoUse, /*MI*/0, |
| 138079 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 138081 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_noret_i64>> => (FLAT_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2), |
| 138083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138084 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138086 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 138087 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138088 | GIR_RootConstrainSelectedInstOperands, |
| 138089 | // GIR_Coverage, 3335, |
| 138090 | GIR_EraseRootFromParent_Done, |
| 138091 | // Label 6604: @445808 |
| 138092 | GIM_Try, /*On fail goto*//*Label 6605*/ GIMT_Encode4(445860), // Rule ID 3395 // |
| 138093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 138094 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138095 | GIM_CheckHasNoUse, /*MI*/0, |
| 138096 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138097 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 138098 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_noret_i64>> => (FLAT_ATOMIC_CMPSWAP_X2 VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138099 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2), |
| 138100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138101 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138103 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 138104 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138105 | GIR_RootConstrainSelectedInstOperands, |
| 138106 | // GIR_Coverage, 3395, |
| 138107 | GIR_EraseRootFromParent_Done, |
| 138108 | // Label 6605: @445860 |
| 138109 | GIM_Try, /*On fail goto*//*Label 6606*/ GIMT_Encode4(445917), // Rule ID 3334 // |
| 138110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 138111 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/4, /*AddrSpace*/0, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138113 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 138115 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_flat_i64>> => (FLAT_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN), |
| 138117 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 138118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138119 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138121 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 138122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138123 | GIR_RootConstrainSelectedInstOperands, |
| 138124 | // GIR_Coverage, 3334, |
| 138125 | GIR_EraseRootFromParent_Done, |
| 138126 | // Label 6606: @445917 |
| 138127 | GIM_Try, /*On fail goto*//*Label 6607*/ GIMT_Encode4(445973), // Rule ID 3394 // |
| 138128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatAddressSpace), |
| 138129 | GIM_CheckMemoryAddressSpace, /*MI*/0, /*MMO*/0, /*NumAddrSpace*/3, /*AddrSpace*/1, /*AddrSpace*/4, /*AddrSpace*/6, |
| 138130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138131 | GIM_CheckPointerToAny, /*MI*/0, /*Op*/1, /*SizeInBits*/0, |
| 138132 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_flat_offset), |
| 138133 | // (AMDGPUatomic_cmp_swap:{ *:[i64] } (FlatOffset:{ *:[iPTR] } i64:{ *:[i64] }:$vaddr, i32:{ *:[i32] }:$offset), v2i64:{ *:[v2i64] }:$data)<<P:Predicate_AMDGPUatomic_cmp_swap_global_i64>> => (FLAT_ATOMIC_CMPSWAP_X2_RTN:{ *:[i64] } VReg_64:{ *:[i64] }:$vaddr, anonymous_15873:{ *:[v2i64] }:$data, ?:{ *:[i32] }:$offset) |
| 138134 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::FLAT_ATOMIC_CMPSWAP_X2_RTN), |
| 138135 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 138136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // vaddr |
| 138137 | GIR_RootToRootCopy, /*OpIdx*/2, // data |
| 138138 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 138139 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 138140 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138141 | GIR_RootConstrainSelectedInstOperands, |
| 138142 | // GIR_Coverage, 3394, |
| 138143 | GIR_EraseRootFromParent_Done, |
| 138144 | // Label 6607: @445973 |
| 138145 | GIM_Reject, |
| 138146 | // Label 6591: @445974 |
| 138147 | GIM_Reject, |
| 138148 | // Label 6573: @445975 |
| 138149 | GIM_Reject, |
| 138150 | // Label 108: @445976 |
| 138151 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6610*/ GIMT_Encode4(448359), |
| 138152 | /*GILLT_s32*//*Label 6608*/ GIMT_Encode4(445995), |
| 138153 | /*GILLT_s64*//*Label 6609*/ GIMT_Encode4(447177), |
| 138154 | // Label 6608: @445995 |
| 138155 | GIM_Try, /*On fail goto*//*Label 6611*/ GIMT_Encode4(447176), |
| 138156 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 138157 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 138158 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 138159 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 138160 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 138161 | GIM_Try, /*On fail goto*//*Label 6612*/ GIMT_Encode4(446083), // Rule ID 5523 // |
| 138162 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138163 | GIM_CheckHasNoUse, /*MI*/0, |
| 138164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138165 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138166 | // MIs[0] offset |
| 138167 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138168 | // MIs[0] auxiliary |
| 138169 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138170 | // MIs[0] Operand 8 |
| 138171 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138173 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET), |
| 138175 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138176 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138178 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138181 | GIR_RootConstrainSelectedInstOperands, |
| 138182 | // GIR_Coverage, 5523, |
| 138183 | GIR_EraseRootFromParent_Done, |
| 138184 | // Label 6612: @446083 |
| 138185 | GIM_Try, /*On fail goto*//*Label 6613*/ GIMT_Encode4(446148), // Rule ID 5531 // |
| 138186 | GIM_CheckHasNoUse, /*MI*/0, |
| 138187 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138188 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138189 | // MIs[0] offset |
| 138190 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138191 | // MIs[0] auxiliary |
| 138192 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138193 | // MIs[0] Operand 8 |
| 138194 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138195 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138196 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET), |
| 138198 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138199 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138201 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138202 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138203 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138204 | GIR_RootConstrainSelectedInstOperands, |
| 138205 | // GIR_Coverage, 5531, |
| 138206 | GIR_EraseRootFromParent_Done, |
| 138207 | // Label 6613: @446148 |
| 138208 | GIM_Try, /*On fail goto*//*Label 6614*/ GIMT_Encode4(446220), // Rule ID 5519 // |
| 138209 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138211 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138212 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138213 | // MIs[0] offset |
| 138214 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138215 | // MIs[0] auxiliary |
| 138216 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138217 | // MIs[0] Operand 8 |
| 138218 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138219 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138220 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFSET_RTN), |
| 138222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138223 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138224 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138226 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138229 | GIR_RootConstrainSelectedInstOperands, |
| 138230 | // GIR_Coverage, 5519, |
| 138231 | GIR_EraseRootFromParent_Done, |
| 138232 | // Label 6614: @446220 |
| 138233 | GIM_Try, /*On fail goto*//*Label 6615*/ GIMT_Encode4(446289), // Rule ID 5527 // |
| 138234 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138235 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138236 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138237 | // MIs[0] offset |
| 138238 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138239 | // MIs[0] auxiliary |
| 138240 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138241 | // MIs[0] Operand 8 |
| 138242 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138244 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFSET_RTN), |
| 138246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138247 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138248 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138250 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138253 | GIR_RootConstrainSelectedInstOperands, |
| 138254 | // GIR_Coverage, 5527, |
| 138255 | GIR_EraseRootFromParent_Done, |
| 138256 | // Label 6615: @446289 |
| 138257 | GIM_Try, /*On fail goto*//*Label 6616*/ GIMT_Encode4(446355), // Rule ID 5525 // |
| 138258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138259 | GIM_CheckHasNoUse, /*MI*/0, |
| 138260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138261 | // MIs[0] offset |
| 138262 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138263 | // MIs[0] auxiliary |
| 138264 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138265 | // MIs[0] Operand 8 |
| 138266 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138268 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFEN), |
| 138270 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138271 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138272 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138274 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138276 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138277 | GIR_RootConstrainSelectedInstOperands, |
| 138278 | // GIR_Coverage, 5525, |
| 138279 | GIR_EraseRootFromParent_Done, |
| 138280 | // Label 6616: @446355 |
| 138281 | GIM_Try, /*On fail goto*//*Label 6617*/ GIMT_Encode4(446418), // Rule ID 5533 // |
| 138282 | GIM_CheckHasNoUse, /*MI*/0, |
| 138283 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138284 | // MIs[0] offset |
| 138285 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138286 | // MIs[0] auxiliary |
| 138287 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138288 | // MIs[0] Operand 8 |
| 138289 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138290 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138291 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN), |
| 138293 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138294 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138295 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138297 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138300 | GIR_RootConstrainSelectedInstOperands, |
| 138301 | // GIR_Coverage, 5533, |
| 138302 | GIR_EraseRootFromParent_Done, |
| 138303 | // Label 6617: @446418 |
| 138304 | GIM_Try, /*On fail goto*//*Label 6618*/ GIMT_Encode4(446488), // Rule ID 5521 // |
| 138305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138306 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138307 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138308 | // MIs[0] offset |
| 138309 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138310 | // MIs[0] auxiliary |
| 138311 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138312 | // MIs[0] Operand 8 |
| 138313 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138315 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_OFFEN_RTN), |
| 138317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138318 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138319 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138320 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138322 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138324 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138325 | GIR_RootConstrainSelectedInstOperands, |
| 138326 | // GIR_Coverage, 5521, |
| 138327 | GIR_EraseRootFromParent_Done, |
| 138328 | // Label 6618: @446488 |
| 138329 | GIM_Try, /*On fail goto*//*Label 6619*/ GIMT_Encode4(446555), // Rule ID 5529 // |
| 138330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138332 | // MIs[0] offset |
| 138333 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138334 | // MIs[0] auxiliary |
| 138335 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138336 | // MIs[0] Operand 8 |
| 138337 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138339 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_OFFEN_RTN), |
| 138341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138342 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138343 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138344 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138346 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138349 | GIR_RootConstrainSelectedInstOperands, |
| 138350 | // GIR_Coverage, 5529, |
| 138351 | GIR_EraseRootFromParent_Done, |
| 138352 | // Label 6619: @446555 |
| 138353 | GIM_Try, /*On fail goto*//*Label 6620*/ GIMT_Encode4(446613), // Rule ID 5524 // |
| 138354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138355 | GIM_CheckHasNoUse, /*MI*/0, |
| 138356 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138357 | // MIs[0] offset |
| 138358 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138359 | // MIs[0] auxiliary |
| 138360 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138361 | // MIs[0] Operand 8 |
| 138362 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138364 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_IDXEN), |
| 138366 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138367 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138368 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138370 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138371 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138373 | GIR_RootConstrainSelectedInstOperands, |
| 138374 | // GIR_Coverage, 5524, |
| 138375 | GIR_EraseRootFromParent_Done, |
| 138376 | // Label 6620: @446613 |
| 138377 | GIM_Try, /*On fail goto*//*Label 6621*/ GIMT_Encode4(446668), // Rule ID 5532 // |
| 138378 | GIM_CheckHasNoUse, /*MI*/0, |
| 138379 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138380 | // MIs[0] offset |
| 138381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138382 | // MIs[0] auxiliary |
| 138383 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138384 | // MIs[0] Operand 8 |
| 138385 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138387 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN), |
| 138389 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138390 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138391 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138393 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138395 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138396 | GIR_RootConstrainSelectedInstOperands, |
| 138397 | // GIR_Coverage, 5532, |
| 138398 | GIR_EraseRootFromParent_Done, |
| 138399 | // Label 6621: @446668 |
| 138400 | GIM_Try, /*On fail goto*//*Label 6622*/ GIMT_Encode4(446730), // Rule ID 5520 // |
| 138401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138403 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138404 | // MIs[0] offset |
| 138405 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138406 | // MIs[0] auxiliary |
| 138407 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138408 | // MIs[0] Operand 8 |
| 138409 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138410 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138411 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_IDXEN_RTN), |
| 138413 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138414 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138415 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138416 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138418 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138419 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138420 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138421 | GIR_RootConstrainSelectedInstOperands, |
| 138422 | // GIR_Coverage, 5520, |
| 138423 | GIR_EraseRootFromParent_Done, |
| 138424 | // Label 6622: @446730 |
| 138425 | GIM_Try, /*On fail goto*//*Label 6623*/ GIMT_Encode4(446789), // Rule ID 5528 // |
| 138426 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138427 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138428 | // MIs[0] offset |
| 138429 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138430 | // MIs[0] auxiliary |
| 138431 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138432 | // MIs[0] Operand 8 |
| 138433 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138435 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_IDXEN_RTN), |
| 138437 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138438 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138439 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138440 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138442 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138445 | GIR_RootConstrainSelectedInstOperands, |
| 138446 | // GIR_Coverage, 5528, |
| 138447 | GIR_EraseRootFromParent_Done, |
| 138448 | // Label 6623: @446789 |
| 138449 | GIM_Try, /*On fail goto*//*Label 6624*/ GIMT_Encode4(446885), // Rule ID 5526 // |
| 138450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138451 | GIM_CheckHasNoUse, /*MI*/0, |
| 138452 | // MIs[0] offset |
| 138453 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138454 | // MIs[0] auxiliary |
| 138455 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138456 | // MIs[0] Operand 8 |
| 138457 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138459 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138460 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138461 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138462 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138463 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138464 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138465 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138466 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138467 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138468 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138469 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN), |
| 138471 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138472 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138473 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138475 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138476 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138477 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138478 | GIR_RootConstrainSelectedInstOperands, |
| 138479 | // GIR_Coverage, 5526, |
| 138480 | GIR_EraseRootFromParent_Done, |
| 138481 | // Label 6624: @446885 |
| 138482 | GIM_Try, /*On fail goto*//*Label 6625*/ GIMT_Encode4(446978), // Rule ID 5534 // |
| 138483 | GIM_CheckHasNoUse, /*MI*/0, |
| 138484 | // MIs[0] offset |
| 138485 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138486 | // MIs[0] auxiliary |
| 138487 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138488 | // MIs[0] Operand 8 |
| 138489 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138490 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138491 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138492 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138493 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138494 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138495 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138496 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138497 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138498 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138499 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138500 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138501 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138502 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN), |
| 138503 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138504 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138505 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138506 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138507 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138508 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138509 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138510 | GIR_RootConstrainSelectedInstOperands, |
| 138511 | // GIR_Coverage, 5534, |
| 138512 | GIR_EraseRootFromParent_Done, |
| 138513 | // Label 6625: @446978 |
| 138514 | GIM_Try, /*On fail goto*//*Label 6626*/ GIMT_Encode4(447078), // Rule ID 5522 // |
| 138515 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138516 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138517 | // MIs[0] offset |
| 138518 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138519 | // MIs[0] auxiliary |
| 138520 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138521 | // MIs[0] Operand 8 |
| 138522 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138523 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138524 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138525 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138526 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138527 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138528 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138529 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138530 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138531 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138532 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138533 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138534 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_BOTHEN_RTN), |
| 138536 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138537 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138538 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138539 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138541 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138542 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138543 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138544 | GIR_RootConstrainSelectedInstOperands, |
| 138545 | // GIR_Coverage, 5522, |
| 138546 | GIR_EraseRootFromParent_Done, |
| 138547 | // Label 6626: @447078 |
| 138548 | GIM_Try, /*On fail goto*//*Label 6627*/ GIMT_Encode4(447175), // Rule ID 5530 // |
| 138549 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 138550 | // MIs[0] offset |
| 138551 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138552 | // MIs[0] auxiliary |
| 138553 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138554 | // MIs[0] Operand 8 |
| 138555 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138556 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138557 | // (SIbuffer_atomic_add:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138558 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138559 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138560 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138561 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138562 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138563 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138564 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138565 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138566 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138567 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138568 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_VBUFFER_BOTHEN_RTN), |
| 138569 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138570 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138571 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138572 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138574 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138575 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138576 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138577 | GIR_RootConstrainSelectedInstOperands, |
| 138578 | // GIR_Coverage, 5530, |
| 138579 | GIR_EraseRootFromParent_Done, |
| 138580 | // Label 6627: @447175 |
| 138581 | GIM_Reject, |
| 138582 | // Label 6611: @447176 |
| 138583 | GIM_Reject, |
| 138584 | // Label 6609: @447177 |
| 138585 | GIM_Try, /*On fail goto*//*Label 6628*/ GIMT_Encode4(448358), |
| 138586 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 138587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 138588 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 138589 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 138590 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 138591 | GIM_Try, /*On fail goto*//*Label 6629*/ GIMT_Encode4(447265), // Rule ID 5723 // |
| 138592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138593 | GIM_CheckHasNoUse, /*MI*/0, |
| 138594 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138595 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138596 | // MIs[0] offset |
| 138597 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138598 | // MIs[0] auxiliary |
| 138599 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138600 | // MIs[0] Operand 8 |
| 138601 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138603 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET), |
| 138605 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138606 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138608 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138609 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138610 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138611 | GIR_RootConstrainSelectedInstOperands, |
| 138612 | // GIR_Coverage, 5723, |
| 138613 | GIR_EraseRootFromParent_Done, |
| 138614 | // Label 6629: @447265 |
| 138615 | GIM_Try, /*On fail goto*//*Label 6630*/ GIMT_Encode4(447330), // Rule ID 5731 // |
| 138616 | GIM_CheckHasNoUse, /*MI*/0, |
| 138617 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138618 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138619 | // MIs[0] offset |
| 138620 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138621 | // MIs[0] auxiliary |
| 138622 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138623 | // MIs[0] Operand 8 |
| 138624 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138626 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET), |
| 138628 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138629 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138631 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138633 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138634 | GIR_RootConstrainSelectedInstOperands, |
| 138635 | // GIR_Coverage, 5731, |
| 138636 | GIR_EraseRootFromParent_Done, |
| 138637 | // Label 6630: @447330 |
| 138638 | GIM_Try, /*On fail goto*//*Label 6631*/ GIMT_Encode4(447402), // Rule ID 5719 // |
| 138639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138640 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138641 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138643 | // MIs[0] offset |
| 138644 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138645 | // MIs[0] auxiliary |
| 138646 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138647 | // MIs[0] Operand 8 |
| 138648 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138650 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFSET_RTN), |
| 138652 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138653 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138654 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138656 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138659 | GIR_RootConstrainSelectedInstOperands, |
| 138660 | // GIR_Coverage, 5719, |
| 138661 | GIR_EraseRootFromParent_Done, |
| 138662 | // Label 6631: @447402 |
| 138663 | GIM_Try, /*On fail goto*//*Label 6632*/ GIMT_Encode4(447471), // Rule ID 5727 // |
| 138664 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138665 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138666 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138667 | // MIs[0] offset |
| 138668 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138669 | // MIs[0] auxiliary |
| 138670 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138671 | // MIs[0] Operand 8 |
| 138672 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138674 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFSET_RTN), |
| 138676 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138677 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138678 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138680 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138681 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138683 | GIR_RootConstrainSelectedInstOperands, |
| 138684 | // GIR_Coverage, 5727, |
| 138685 | GIR_EraseRootFromParent_Done, |
| 138686 | // Label 6632: @447471 |
| 138687 | GIM_Try, /*On fail goto*//*Label 6633*/ GIMT_Encode4(447537), // Rule ID 5725 // |
| 138688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138689 | GIM_CheckHasNoUse, /*MI*/0, |
| 138690 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138691 | // MIs[0] offset |
| 138692 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138693 | // MIs[0] auxiliary |
| 138694 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138695 | // MIs[0] Operand 8 |
| 138696 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138698 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN), |
| 138700 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138701 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138702 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138704 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138705 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138707 | GIR_RootConstrainSelectedInstOperands, |
| 138708 | // GIR_Coverage, 5725, |
| 138709 | GIR_EraseRootFromParent_Done, |
| 138710 | // Label 6633: @447537 |
| 138711 | GIM_Try, /*On fail goto*//*Label 6634*/ GIMT_Encode4(447600), // Rule ID 5733 // |
| 138712 | GIM_CheckHasNoUse, /*MI*/0, |
| 138713 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138714 | // MIs[0] offset |
| 138715 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138716 | // MIs[0] auxiliary |
| 138717 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138718 | // MIs[0] Operand 8 |
| 138719 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138721 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN), |
| 138723 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138724 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138725 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138727 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138728 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138729 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138730 | GIR_RootConstrainSelectedInstOperands, |
| 138731 | // GIR_Coverage, 5733, |
| 138732 | GIR_EraseRootFromParent_Done, |
| 138733 | // Label 6634: @447600 |
| 138734 | GIM_Try, /*On fail goto*//*Label 6635*/ GIMT_Encode4(447670), // Rule ID 5721 // |
| 138735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138736 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138737 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138738 | // MIs[0] offset |
| 138739 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138740 | // MIs[0] auxiliary |
| 138741 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138742 | // MIs[0] Operand 8 |
| 138743 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138745 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_OFFEN_RTN), |
| 138747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138748 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138749 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138750 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138752 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138753 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138754 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138755 | GIR_RootConstrainSelectedInstOperands, |
| 138756 | // GIR_Coverage, 5721, |
| 138757 | GIR_EraseRootFromParent_Done, |
| 138758 | // Label 6635: @447670 |
| 138759 | GIM_Try, /*On fail goto*//*Label 6636*/ GIMT_Encode4(447737), // Rule ID 5729 // |
| 138760 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138761 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 138762 | // MIs[0] offset |
| 138763 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138764 | // MIs[0] auxiliary |
| 138765 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138766 | // MIs[0] Operand 8 |
| 138767 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 138768 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138769 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138770 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_OFFEN_RTN), |
| 138771 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138772 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138773 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 138774 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138775 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138776 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138777 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138778 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138779 | GIR_RootConstrainSelectedInstOperands, |
| 138780 | // GIR_Coverage, 5729, |
| 138781 | GIR_EraseRootFromParent_Done, |
| 138782 | // Label 6636: @447737 |
| 138783 | GIM_Try, /*On fail goto*//*Label 6637*/ GIMT_Encode4(447795), // Rule ID 5724 // |
| 138784 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138785 | GIM_CheckHasNoUse, /*MI*/0, |
| 138786 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138787 | // MIs[0] offset |
| 138788 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138789 | // MIs[0] auxiliary |
| 138790 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138791 | // MIs[0] Operand 8 |
| 138792 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138794 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN), |
| 138796 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138797 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138798 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138800 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138803 | GIR_RootConstrainSelectedInstOperands, |
| 138804 | // GIR_Coverage, 5724, |
| 138805 | GIR_EraseRootFromParent_Done, |
| 138806 | // Label 6637: @447795 |
| 138807 | GIM_Try, /*On fail goto*//*Label 6638*/ GIMT_Encode4(447850), // Rule ID 5732 // |
| 138808 | GIM_CheckHasNoUse, /*MI*/0, |
| 138809 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138810 | // MIs[0] offset |
| 138811 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138812 | // MIs[0] auxiliary |
| 138813 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138814 | // MIs[0] Operand 8 |
| 138815 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138816 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138817 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138818 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN), |
| 138819 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138820 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138821 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138822 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138823 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138824 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138825 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138826 | GIR_RootConstrainSelectedInstOperands, |
| 138827 | // GIR_Coverage, 5732, |
| 138828 | GIR_EraseRootFromParent_Done, |
| 138829 | // Label 6638: @447850 |
| 138830 | GIM_Try, /*On fail goto*//*Label 6639*/ GIMT_Encode4(447912), // Rule ID 5720 // |
| 138831 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138833 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138834 | // MIs[0] offset |
| 138835 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138836 | // MIs[0] auxiliary |
| 138837 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138838 | // MIs[0] Operand 8 |
| 138839 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138841 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138842 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_IDXEN_RTN), |
| 138843 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138844 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138845 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138846 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138847 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138848 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138849 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138850 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138851 | GIR_RootConstrainSelectedInstOperands, |
| 138852 | // GIR_Coverage, 5720, |
| 138853 | GIR_EraseRootFromParent_Done, |
| 138854 | // Label 6639: @447912 |
| 138855 | GIM_Try, /*On fail goto*//*Label 6640*/ GIMT_Encode4(447971), // Rule ID 5728 // |
| 138856 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138857 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 138858 | // MIs[0] offset |
| 138859 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138860 | // MIs[0] auxiliary |
| 138861 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138862 | // MIs[0] Operand 8 |
| 138863 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138865 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_IDXEN_RTN), |
| 138867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138868 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138869 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 138870 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138872 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138873 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138874 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138875 | GIR_RootConstrainSelectedInstOperands, |
| 138876 | // GIR_Coverage, 5728, |
| 138877 | GIR_EraseRootFromParent_Done, |
| 138878 | // Label 6640: @447971 |
| 138879 | GIM_Try, /*On fail goto*//*Label 6641*/ GIMT_Encode4(448067), // Rule ID 5726 // |
| 138880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138881 | GIM_CheckHasNoUse, /*MI*/0, |
| 138882 | // MIs[0] offset |
| 138883 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138884 | // MIs[0] auxiliary |
| 138885 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138886 | // MIs[0] Operand 8 |
| 138887 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138888 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138889 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138890 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138891 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138892 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138893 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138894 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138895 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138896 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138897 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138898 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138899 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN), |
| 138901 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138902 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138903 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138905 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138906 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138907 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138908 | GIR_RootConstrainSelectedInstOperands, |
| 138909 | // GIR_Coverage, 5726, |
| 138910 | GIR_EraseRootFromParent_Done, |
| 138911 | // Label 6641: @448067 |
| 138912 | GIM_Try, /*On fail goto*//*Label 6642*/ GIMT_Encode4(448160), // Rule ID 5734 // |
| 138913 | GIM_CheckHasNoUse, /*MI*/0, |
| 138914 | // MIs[0] offset |
| 138915 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138916 | // MIs[0] auxiliary |
| 138917 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138918 | // MIs[0] Operand 8 |
| 138919 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138920 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138921 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_add_noret>> => (BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138922 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138923 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138924 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138925 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138926 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138927 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138928 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138929 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138930 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138931 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138932 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN), |
| 138933 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138934 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138935 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138936 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138937 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138938 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 138939 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138940 | GIR_RootConstrainSelectedInstOperands, |
| 138941 | // GIR_Coverage, 5734, |
| 138942 | GIR_EraseRootFromParent_Done, |
| 138943 | // Label 6642: @448160 |
| 138944 | GIM_Try, /*On fail goto*//*Label 6643*/ GIMT_Encode4(448260), // Rule ID 5722 // |
| 138945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 138946 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138947 | // MIs[0] offset |
| 138948 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138949 | // MIs[0] auxiliary |
| 138950 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138951 | // MIs[0] Operand 8 |
| 138952 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138954 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138955 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138956 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138957 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138958 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138959 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138960 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138961 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138962 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138963 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138964 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_BOTHEN_RTN), |
| 138966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 138967 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 138968 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 138969 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 138970 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 138971 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 138972 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 138973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 138974 | GIR_RootConstrainSelectedInstOperands, |
| 138975 | // GIR_Coverage, 5722, |
| 138976 | GIR_EraseRootFromParent_Done, |
| 138977 | // Label 6643: @448260 |
| 138978 | GIM_Try, /*On fail goto*//*Label 6644*/ GIMT_Encode4(448357), // Rule ID 5730 // |
| 138979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 138980 | // MIs[0] offset |
| 138981 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 138982 | // MIs[0] auxiliary |
| 138983 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 138984 | // MIs[0] Operand 8 |
| 138985 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 138986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 138987 | // (SIbuffer_atomic_add:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 138988 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 138989 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 138990 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 138991 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 138992 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 138993 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 138994 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 138995 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 138996 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138997 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 138998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_X2_VBUFFER_BOTHEN_RTN), |
| 138999 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139000 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139001 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139002 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139004 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139005 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139006 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139007 | GIR_RootConstrainSelectedInstOperands, |
| 139008 | // GIR_Coverage, 5730, |
| 139009 | GIR_EraseRootFromParent_Done, |
| 139010 | // Label 6644: @448357 |
| 139011 | GIM_Reject, |
| 139012 | // Label 6628: @448358 |
| 139013 | GIM_Reject, |
| 139014 | // Label 6610: @448359 |
| 139015 | GIM_Reject, |
| 139016 | // Label 109: @448360 |
| 139017 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6647*/ GIMT_Encode4(450743), |
| 139018 | /*GILLT_s32*//*Label 6645*/ GIMT_Encode4(448379), |
| 139019 | /*GILLT_s64*//*Label 6646*/ GIMT_Encode4(449561), |
| 139020 | // Label 6645: @448379 |
| 139021 | GIM_Try, /*On fail goto*//*Label 6648*/ GIMT_Encode4(449560), |
| 139022 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 139023 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 139024 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 139025 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 139026 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 139027 | GIM_Try, /*On fail goto*//*Label 6649*/ GIMT_Encode4(448467), // Rule ID 5619 // |
| 139028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139029 | GIM_CheckHasNoUse, /*MI*/0, |
| 139030 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139031 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139032 | // MIs[0] offset |
| 139033 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139034 | // MIs[0] auxiliary |
| 139035 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139036 | // MIs[0] Operand 8 |
| 139037 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139039 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET), |
| 139041 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139042 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139044 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139045 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139046 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139047 | GIR_RootConstrainSelectedInstOperands, |
| 139048 | // GIR_Coverage, 5619, |
| 139049 | GIR_EraseRootFromParent_Done, |
| 139050 | // Label 6649: @448467 |
| 139051 | GIM_Try, /*On fail goto*//*Label 6650*/ GIMT_Encode4(448532), // Rule ID 5627 // |
| 139052 | GIM_CheckHasNoUse, /*MI*/0, |
| 139053 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139054 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139055 | // MIs[0] offset |
| 139056 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139057 | // MIs[0] auxiliary |
| 139058 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139059 | // MIs[0] Operand 8 |
| 139060 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139061 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139062 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139063 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET), |
| 139064 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139065 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139066 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139067 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139068 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139070 | GIR_RootConstrainSelectedInstOperands, |
| 139071 | // GIR_Coverage, 5627, |
| 139072 | GIR_EraseRootFromParent_Done, |
| 139073 | // Label 6650: @448532 |
| 139074 | GIM_Try, /*On fail goto*//*Label 6651*/ GIMT_Encode4(448604), // Rule ID 5615 // |
| 139075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139076 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139077 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139078 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139079 | // MIs[0] offset |
| 139080 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139081 | // MIs[0] auxiliary |
| 139082 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139083 | // MIs[0] Operand 8 |
| 139084 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139086 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFSET_RTN), |
| 139088 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139089 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139090 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139092 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139093 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139094 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139095 | GIR_RootConstrainSelectedInstOperands, |
| 139096 | // GIR_Coverage, 5615, |
| 139097 | GIR_EraseRootFromParent_Done, |
| 139098 | // Label 6651: @448604 |
| 139099 | GIM_Try, /*On fail goto*//*Label 6652*/ GIMT_Encode4(448673), // Rule ID 5623 // |
| 139100 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139101 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139102 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139103 | // MIs[0] offset |
| 139104 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139105 | // MIs[0] auxiliary |
| 139106 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139107 | // MIs[0] Operand 8 |
| 139108 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139110 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFSET_RTN), |
| 139112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139113 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139114 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139116 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139117 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139118 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139119 | GIR_RootConstrainSelectedInstOperands, |
| 139120 | // GIR_Coverage, 5623, |
| 139121 | GIR_EraseRootFromParent_Done, |
| 139122 | // Label 6652: @448673 |
| 139123 | GIM_Try, /*On fail goto*//*Label 6653*/ GIMT_Encode4(448739), // Rule ID 5621 // |
| 139124 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139125 | GIM_CheckHasNoUse, /*MI*/0, |
| 139126 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139127 | // MIs[0] offset |
| 139128 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139129 | // MIs[0] auxiliary |
| 139130 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139131 | // MIs[0] Operand 8 |
| 139132 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139133 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139134 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFEN), |
| 139136 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139137 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139138 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139140 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139141 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139142 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139143 | GIR_RootConstrainSelectedInstOperands, |
| 139144 | // GIR_Coverage, 5621, |
| 139145 | GIR_EraseRootFromParent_Done, |
| 139146 | // Label 6653: @448739 |
| 139147 | GIM_Try, /*On fail goto*//*Label 6654*/ GIMT_Encode4(448802), // Rule ID 5629 // |
| 139148 | GIM_CheckHasNoUse, /*MI*/0, |
| 139149 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139150 | // MIs[0] offset |
| 139151 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139152 | // MIs[0] auxiliary |
| 139153 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139154 | // MIs[0] Operand 8 |
| 139155 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139156 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139157 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN), |
| 139159 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139160 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139161 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139163 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139164 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139166 | GIR_RootConstrainSelectedInstOperands, |
| 139167 | // GIR_Coverage, 5629, |
| 139168 | GIR_EraseRootFromParent_Done, |
| 139169 | // Label 6654: @448802 |
| 139170 | GIM_Try, /*On fail goto*//*Label 6655*/ GIMT_Encode4(448872), // Rule ID 5617 // |
| 139171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139173 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139174 | // MIs[0] offset |
| 139175 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139176 | // MIs[0] auxiliary |
| 139177 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139178 | // MIs[0] Operand 8 |
| 139179 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139181 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_OFFEN_RTN), |
| 139183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139184 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139185 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139186 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139187 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139188 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139189 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139190 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139191 | GIR_RootConstrainSelectedInstOperands, |
| 139192 | // GIR_Coverage, 5617, |
| 139193 | GIR_EraseRootFromParent_Done, |
| 139194 | // Label 6655: @448872 |
| 139195 | GIM_Try, /*On fail goto*//*Label 6656*/ GIMT_Encode4(448939), // Rule ID 5625 // |
| 139196 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139197 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139198 | // MIs[0] offset |
| 139199 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139200 | // MIs[0] auxiliary |
| 139201 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139202 | // MIs[0] Operand 8 |
| 139203 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139204 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139205 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_OFFEN_RTN), |
| 139207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139208 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139209 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139210 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139212 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139215 | GIR_RootConstrainSelectedInstOperands, |
| 139216 | // GIR_Coverage, 5625, |
| 139217 | GIR_EraseRootFromParent_Done, |
| 139218 | // Label 6656: @448939 |
| 139219 | GIM_Try, /*On fail goto*//*Label 6657*/ GIMT_Encode4(448997), // Rule ID 5620 // |
| 139220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139221 | GIM_CheckHasNoUse, /*MI*/0, |
| 139222 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139223 | // MIs[0] offset |
| 139224 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139225 | // MIs[0] auxiliary |
| 139226 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139227 | // MIs[0] Operand 8 |
| 139228 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139229 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139230 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_IDXEN), |
| 139232 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139233 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139234 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139236 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139237 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139239 | GIR_RootConstrainSelectedInstOperands, |
| 139240 | // GIR_Coverage, 5620, |
| 139241 | GIR_EraseRootFromParent_Done, |
| 139242 | // Label 6657: @448997 |
| 139243 | GIM_Try, /*On fail goto*//*Label 6658*/ GIMT_Encode4(449052), // Rule ID 5628 // |
| 139244 | GIM_CheckHasNoUse, /*MI*/0, |
| 139245 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139246 | // MIs[0] offset |
| 139247 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139248 | // MIs[0] auxiliary |
| 139249 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139250 | // MIs[0] Operand 8 |
| 139251 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139253 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN), |
| 139255 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139256 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139257 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139259 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139260 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139261 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139262 | GIR_RootConstrainSelectedInstOperands, |
| 139263 | // GIR_Coverage, 5628, |
| 139264 | GIR_EraseRootFromParent_Done, |
| 139265 | // Label 6658: @449052 |
| 139266 | GIM_Try, /*On fail goto*//*Label 6659*/ GIMT_Encode4(449114), // Rule ID 5616 // |
| 139267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139269 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139270 | // MIs[0] offset |
| 139271 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139272 | // MIs[0] auxiliary |
| 139273 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139274 | // MIs[0] Operand 8 |
| 139275 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139277 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139278 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_IDXEN_RTN), |
| 139279 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139280 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139281 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139282 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139284 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139285 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139286 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139287 | GIR_RootConstrainSelectedInstOperands, |
| 139288 | // GIR_Coverage, 5616, |
| 139289 | GIR_EraseRootFromParent_Done, |
| 139290 | // Label 6659: @449114 |
| 139291 | GIM_Try, /*On fail goto*//*Label 6660*/ GIMT_Encode4(449173), // Rule ID 5624 // |
| 139292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139293 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139294 | // MIs[0] offset |
| 139295 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139296 | // MIs[0] auxiliary |
| 139297 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139298 | // MIs[0] Operand 8 |
| 139299 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139300 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139301 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139302 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_IDXEN_RTN), |
| 139303 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139304 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139305 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139306 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139307 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139308 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139309 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139310 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139311 | GIR_RootConstrainSelectedInstOperands, |
| 139312 | // GIR_Coverage, 5624, |
| 139313 | GIR_EraseRootFromParent_Done, |
| 139314 | // Label 6660: @449173 |
| 139315 | GIM_Try, /*On fail goto*//*Label 6661*/ GIMT_Encode4(449269), // Rule ID 5622 // |
| 139316 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139317 | GIM_CheckHasNoUse, /*MI*/0, |
| 139318 | // MIs[0] offset |
| 139319 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139320 | // MIs[0] auxiliary |
| 139321 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139322 | // MIs[0] Operand 8 |
| 139323 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139325 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139329 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139330 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139331 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139332 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139333 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139334 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139335 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_BOTHEN), |
| 139337 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139339 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139341 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139342 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139343 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139344 | GIR_RootConstrainSelectedInstOperands, |
| 139345 | // GIR_Coverage, 5622, |
| 139346 | GIR_EraseRootFromParent_Done, |
| 139347 | // Label 6661: @449269 |
| 139348 | GIM_Try, /*On fail goto*//*Label 6662*/ GIMT_Encode4(449362), // Rule ID 5630 // |
| 139349 | GIM_CheckHasNoUse, /*MI*/0, |
| 139350 | // MIs[0] offset |
| 139351 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139352 | // MIs[0] auxiliary |
| 139353 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139354 | // MIs[0] Operand 8 |
| 139355 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139356 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139357 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139358 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139359 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139360 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139361 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139362 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139363 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139364 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139365 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139366 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139367 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN), |
| 139369 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139371 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139373 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139374 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139376 | GIR_RootConstrainSelectedInstOperands, |
| 139377 | // GIR_Coverage, 5630, |
| 139378 | GIR_EraseRootFromParent_Done, |
| 139379 | // Label 6662: @449362 |
| 139380 | GIM_Try, /*On fail goto*//*Label 6663*/ GIMT_Encode4(449462), // Rule ID 5618 // |
| 139381 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139382 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139383 | // MIs[0] offset |
| 139384 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139385 | // MIs[0] auxiliary |
| 139386 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139387 | // MIs[0] Operand 8 |
| 139388 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139390 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139391 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139392 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139393 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139394 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139395 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139396 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139397 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139398 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139399 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139400 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_BOTHEN_RTN), |
| 139402 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139403 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139404 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139405 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139406 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139407 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139408 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139410 | GIR_RootConstrainSelectedInstOperands, |
| 139411 | // GIR_Coverage, 5618, |
| 139412 | GIR_EraseRootFromParent_Done, |
| 139413 | // Label 6663: @449462 |
| 139414 | GIM_Try, /*On fail goto*//*Label 6664*/ GIMT_Encode4(449559), // Rule ID 5626 // |
| 139415 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139416 | // MIs[0] offset |
| 139417 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139418 | // MIs[0] auxiliary |
| 139419 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139420 | // MIs[0] Operand 8 |
| 139421 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139423 | // (SIbuffer_atomic_and:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139424 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139425 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139426 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139427 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139428 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139429 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139430 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139431 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139432 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139433 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_VBUFFER_BOTHEN_RTN), |
| 139435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139436 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139437 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139438 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139440 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139441 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139443 | GIR_RootConstrainSelectedInstOperands, |
| 139444 | // GIR_Coverage, 5626, |
| 139445 | GIR_EraseRootFromParent_Done, |
| 139446 | // Label 6664: @449559 |
| 139447 | GIM_Reject, |
| 139448 | // Label 6648: @449560 |
| 139449 | GIM_Reject, |
| 139450 | // Label 6646: @449561 |
| 139451 | GIM_Try, /*On fail goto*//*Label 6665*/ GIMT_Encode4(450742), |
| 139452 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 139453 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 139454 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 139455 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 139456 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 139457 | GIM_Try, /*On fail goto*//*Label 6666*/ GIMT_Encode4(449649), // Rule ID 5819 // |
| 139458 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139459 | GIM_CheckHasNoUse, /*MI*/0, |
| 139460 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139461 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139462 | // MIs[0] offset |
| 139463 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139464 | // MIs[0] auxiliary |
| 139465 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139466 | // MIs[0] Operand 8 |
| 139467 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139468 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139469 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET), |
| 139471 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139472 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139474 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139475 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139476 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139477 | GIR_RootConstrainSelectedInstOperands, |
| 139478 | // GIR_Coverage, 5819, |
| 139479 | GIR_EraseRootFromParent_Done, |
| 139480 | // Label 6666: @449649 |
| 139481 | GIM_Try, /*On fail goto*//*Label 6667*/ GIMT_Encode4(449714), // Rule ID 5827 // |
| 139482 | GIM_CheckHasNoUse, /*MI*/0, |
| 139483 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139484 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139485 | // MIs[0] offset |
| 139486 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139487 | // MIs[0] auxiliary |
| 139488 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139489 | // MIs[0] Operand 8 |
| 139490 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139492 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET), |
| 139494 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139495 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139496 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139497 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139498 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139499 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139500 | GIR_RootConstrainSelectedInstOperands, |
| 139501 | // GIR_Coverage, 5827, |
| 139502 | GIR_EraseRootFromParent_Done, |
| 139503 | // Label 6667: @449714 |
| 139504 | GIM_Try, /*On fail goto*//*Label 6668*/ GIMT_Encode4(449786), // Rule ID 5815 // |
| 139505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139506 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139507 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139508 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139509 | // MIs[0] offset |
| 139510 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139511 | // MIs[0] auxiliary |
| 139512 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139513 | // MIs[0] Operand 8 |
| 139514 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139516 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFSET_RTN), |
| 139518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139519 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139520 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139522 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139523 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139524 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139525 | GIR_RootConstrainSelectedInstOperands, |
| 139526 | // GIR_Coverage, 5815, |
| 139527 | GIR_EraseRootFromParent_Done, |
| 139528 | // Label 6668: @449786 |
| 139529 | GIM_Try, /*On fail goto*//*Label 6669*/ GIMT_Encode4(449855), // Rule ID 5823 // |
| 139530 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139531 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139532 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139533 | // MIs[0] offset |
| 139534 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139535 | // MIs[0] auxiliary |
| 139536 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139537 | // MIs[0] Operand 8 |
| 139538 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139540 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFSET_RTN), |
| 139542 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139543 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139544 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139546 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139547 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139549 | GIR_RootConstrainSelectedInstOperands, |
| 139550 | // GIR_Coverage, 5823, |
| 139551 | GIR_EraseRootFromParent_Done, |
| 139552 | // Label 6669: @449855 |
| 139553 | GIM_Try, /*On fail goto*//*Label 6670*/ GIMT_Encode4(449921), // Rule ID 5821 // |
| 139554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139555 | GIM_CheckHasNoUse, /*MI*/0, |
| 139556 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139557 | // MIs[0] offset |
| 139558 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139559 | // MIs[0] auxiliary |
| 139560 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139561 | // MIs[0] Operand 8 |
| 139562 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139564 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN), |
| 139566 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139567 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139568 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139570 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139573 | GIR_RootConstrainSelectedInstOperands, |
| 139574 | // GIR_Coverage, 5821, |
| 139575 | GIR_EraseRootFromParent_Done, |
| 139576 | // Label 6670: @449921 |
| 139577 | GIM_Try, /*On fail goto*//*Label 6671*/ GIMT_Encode4(449984), // Rule ID 5829 // |
| 139578 | GIM_CheckHasNoUse, /*MI*/0, |
| 139579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139580 | // MIs[0] offset |
| 139581 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139582 | // MIs[0] auxiliary |
| 139583 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139584 | // MIs[0] Operand 8 |
| 139585 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139587 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN), |
| 139589 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139590 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139591 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139593 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139596 | GIR_RootConstrainSelectedInstOperands, |
| 139597 | // GIR_Coverage, 5829, |
| 139598 | GIR_EraseRootFromParent_Done, |
| 139599 | // Label 6671: @449984 |
| 139600 | GIM_Try, /*On fail goto*//*Label 6672*/ GIMT_Encode4(450054), // Rule ID 5817 // |
| 139601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139603 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139604 | // MIs[0] offset |
| 139605 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139606 | // MIs[0] auxiliary |
| 139607 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139608 | // MIs[0] Operand 8 |
| 139609 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139611 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_OFFEN_RTN), |
| 139613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139614 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139615 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139616 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139618 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139619 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139620 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139621 | GIR_RootConstrainSelectedInstOperands, |
| 139622 | // GIR_Coverage, 5817, |
| 139623 | GIR_EraseRootFromParent_Done, |
| 139624 | // Label 6672: @450054 |
| 139625 | GIM_Try, /*On fail goto*//*Label 6673*/ GIMT_Encode4(450121), // Rule ID 5825 // |
| 139626 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139627 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 139628 | // MIs[0] offset |
| 139629 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139630 | // MIs[0] auxiliary |
| 139631 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139632 | // MIs[0] Operand 8 |
| 139633 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 139634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139635 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_OFFEN_RTN), |
| 139637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139638 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139639 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 139640 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139642 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139643 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139645 | GIR_RootConstrainSelectedInstOperands, |
| 139646 | // GIR_Coverage, 5825, |
| 139647 | GIR_EraseRootFromParent_Done, |
| 139648 | // Label 6673: @450121 |
| 139649 | GIM_Try, /*On fail goto*//*Label 6674*/ GIMT_Encode4(450179), // Rule ID 5820 // |
| 139650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139651 | GIM_CheckHasNoUse, /*MI*/0, |
| 139652 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139653 | // MIs[0] offset |
| 139654 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139655 | // MIs[0] auxiliary |
| 139656 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139657 | // MIs[0] Operand 8 |
| 139658 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139660 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN), |
| 139662 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139663 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139664 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139666 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139669 | GIR_RootConstrainSelectedInstOperands, |
| 139670 | // GIR_Coverage, 5820, |
| 139671 | GIR_EraseRootFromParent_Done, |
| 139672 | // Label 6674: @450179 |
| 139673 | GIM_Try, /*On fail goto*//*Label 6675*/ GIMT_Encode4(450234), // Rule ID 5828 // |
| 139674 | GIM_CheckHasNoUse, /*MI*/0, |
| 139675 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139676 | // MIs[0] offset |
| 139677 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139678 | // MIs[0] auxiliary |
| 139679 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139680 | // MIs[0] Operand 8 |
| 139681 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139682 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139683 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN), |
| 139685 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139686 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139687 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139689 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139690 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139692 | GIR_RootConstrainSelectedInstOperands, |
| 139693 | // GIR_Coverage, 5828, |
| 139694 | GIR_EraseRootFromParent_Done, |
| 139695 | // Label 6675: @450234 |
| 139696 | GIM_Try, /*On fail goto*//*Label 6676*/ GIMT_Encode4(450296), // Rule ID 5816 // |
| 139697 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139698 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139699 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139700 | // MIs[0] offset |
| 139701 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139702 | // MIs[0] auxiliary |
| 139703 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139704 | // MIs[0] Operand 8 |
| 139705 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139706 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139707 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_IDXEN_RTN), |
| 139709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139710 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139711 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139712 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139714 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139715 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139717 | GIR_RootConstrainSelectedInstOperands, |
| 139718 | // GIR_Coverage, 5816, |
| 139719 | GIR_EraseRootFromParent_Done, |
| 139720 | // Label 6676: @450296 |
| 139721 | GIM_Try, /*On fail goto*//*Label 6677*/ GIMT_Encode4(450355), // Rule ID 5824 // |
| 139722 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139723 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139724 | // MIs[0] offset |
| 139725 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139726 | // MIs[0] auxiliary |
| 139727 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139728 | // MIs[0] Operand 8 |
| 139729 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139730 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139731 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_IDXEN_RTN), |
| 139733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139734 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139735 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 139736 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139738 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139741 | GIR_RootConstrainSelectedInstOperands, |
| 139742 | // GIR_Coverage, 5824, |
| 139743 | GIR_EraseRootFromParent_Done, |
| 139744 | // Label 6677: @450355 |
| 139745 | GIM_Try, /*On fail goto*//*Label 6678*/ GIMT_Encode4(450451), // Rule ID 5822 // |
| 139746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139747 | GIM_CheckHasNoUse, /*MI*/0, |
| 139748 | // MIs[0] offset |
| 139749 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139750 | // MIs[0] auxiliary |
| 139751 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139752 | // MIs[0] Operand 8 |
| 139753 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139755 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139757 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139758 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139759 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139760 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139761 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139762 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139763 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139764 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139765 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN), |
| 139767 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139768 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139769 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139771 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139772 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139774 | GIR_RootConstrainSelectedInstOperands, |
| 139775 | // GIR_Coverage, 5822, |
| 139776 | GIR_EraseRootFromParent_Done, |
| 139777 | // Label 6678: @450451 |
| 139778 | GIM_Try, /*On fail goto*//*Label 6679*/ GIMT_Encode4(450544), // Rule ID 5830 // |
| 139779 | GIM_CheckHasNoUse, /*MI*/0, |
| 139780 | // MIs[0] offset |
| 139781 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139782 | // MIs[0] auxiliary |
| 139783 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139784 | // MIs[0] Operand 8 |
| 139785 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139786 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139787 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_and_noret>> => (BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139788 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139789 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139790 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139791 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139792 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139793 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139794 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139795 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139796 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139797 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN), |
| 139799 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139800 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139801 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139803 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139804 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139805 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139806 | GIR_RootConstrainSelectedInstOperands, |
| 139807 | // GIR_Coverage, 5830, |
| 139808 | GIR_EraseRootFromParent_Done, |
| 139809 | // Label 6679: @450544 |
| 139810 | GIM_Try, /*On fail goto*//*Label 6680*/ GIMT_Encode4(450644), // Rule ID 5818 // |
| 139811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139812 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139813 | // MIs[0] offset |
| 139814 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139815 | // MIs[0] auxiliary |
| 139816 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139817 | // MIs[0] Operand 8 |
| 139818 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139819 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139820 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139824 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139825 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139826 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139827 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139830 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_BOTHEN_RTN), |
| 139832 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139833 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139835 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139837 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139840 | GIR_RootConstrainSelectedInstOperands, |
| 139841 | // GIR_Coverage, 5818, |
| 139842 | GIR_EraseRootFromParent_Done, |
| 139843 | // Label 6680: @450644 |
| 139844 | GIM_Try, /*On fail goto*//*Label 6681*/ GIMT_Encode4(450741), // Rule ID 5826 // |
| 139845 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139846 | // MIs[0] offset |
| 139847 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 139848 | // MIs[0] auxiliary |
| 139849 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139850 | // MIs[0] Operand 8 |
| 139851 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139852 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139853 | // (SIbuffer_atomic_and:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139857 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 139858 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139859 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 139860 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139861 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139862 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139863 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_AND_X2_VBUFFER_BOTHEN_RTN), |
| 139865 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 139866 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 139867 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139868 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 139869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139870 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 139871 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139873 | GIR_RootConstrainSelectedInstOperands, |
| 139874 | // GIR_Coverage, 5826, |
| 139875 | GIR_EraseRootFromParent_Done, |
| 139876 | // Label 6681: @450741 |
| 139877 | GIM_Reject, |
| 139878 | // Label 6665: @450742 |
| 139879 | GIM_Reject, |
| 139880 | // Label 6647: @450743 |
| 139881 | GIM_Reject, |
| 139882 | // Label 110: @450744 |
| 139883 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6684*/ GIMT_Encode4(455037), |
| 139884 | /*GILLT_s32*//*Label 6682*/ GIMT_Encode4(450763), |
| 139885 | /*GILLT_s64*//*Label 6683*/ GIMT_Encode4(452900), |
| 139886 | // Label 6682: @450763 |
| 139887 | GIM_Try, /*On fail goto*//*Label 6685*/ GIMT_Encode4(452899), |
| 139888 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 139889 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 139890 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 139891 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 139892 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 139893 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 139894 | GIM_Try, /*On fail goto*//*Label 6686*/ GIMT_Encode4(450896), // Rule ID 6075 // |
| 139895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139896 | GIM_CheckHasNoUse, /*MI*/0, |
| 139897 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139898 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 139899 | // MIs[0] offset |
| 139900 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139901 | // MIs[0] auxiliary |
| 139902 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139903 | // MIs[0] Operand 9 |
| 139904 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 139905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139906 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_OFFSET (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139907 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139908 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139909 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139910 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 139911 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139912 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 139913 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139914 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139915 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139916 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET), |
| 139918 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139919 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 139920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139921 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 139922 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139924 | GIR_RootConstrainSelectedInstOperands, |
| 139925 | // GIR_Coverage, 6075, |
| 139926 | GIR_EraseRootFromParent_Done, |
| 139927 | // Label 6686: @450896 |
| 139928 | GIM_Try, /*On fail goto*//*Label 6687*/ GIMT_Encode4(451003), // Rule ID 6083 // |
| 139929 | GIM_CheckHasNoUse, /*MI*/0, |
| 139930 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139931 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 139932 | // MIs[0] offset |
| 139933 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139934 | // MIs[0] auxiliary |
| 139935 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139936 | // MIs[0] Operand 9 |
| 139937 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 139938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139939 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 139940 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139941 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139942 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139943 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 139944 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 139945 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 139946 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 139947 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139948 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139949 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET), |
| 139951 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 139952 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 139953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139954 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 139955 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 139956 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139957 | GIR_RootConstrainSelectedInstOperands, |
| 139958 | // GIR_Coverage, 6083, |
| 139959 | GIR_EraseRootFromParent_Done, |
| 139960 | // Label 6687: @451003 |
| 139961 | GIM_Try, /*On fail goto*//*Label 6688*/ GIMT_Encode4(451151), // Rule ID 6071 // |
| 139962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 139963 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139964 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 139965 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 139966 | // MIs[0] offset |
| 139967 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 139968 | // MIs[0] auxiliary |
| 139969 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 139970 | // MIs[0] Operand 9 |
| 139971 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 139972 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 139973 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 139974 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 139975 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 139976 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 139977 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139978 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 139979 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 139980 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 139981 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 139982 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 139983 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139984 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 139985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFSET_RTN), |
| 139986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 139987 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 139988 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 139989 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 139990 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 139991 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 139992 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 139993 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 139994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 139995 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 139996 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 139997 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 139998 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 139999 | // GIR_Coverage, 6071, |
| 140000 | GIR_EraseRootFromParent_Done, |
| 140001 | // Label 6688: @451151 |
| 140002 | GIM_Try, /*On fail goto*//*Label 6689*/ GIMT_Encode4(451296), // Rule ID 6079 // |
| 140003 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140004 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140005 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140006 | // MIs[0] offset |
| 140007 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140008 | // MIs[0] auxiliary |
| 140009 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140010 | // MIs[0] Operand 9 |
| 140011 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140013 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140015 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140016 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140017 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140018 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140019 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140020 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140021 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140022 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140023 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140024 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140025 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFSET_RTN), |
| 140026 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140027 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140028 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140029 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140030 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140031 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140032 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140033 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140035 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140036 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140037 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140038 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140039 | // GIR_Coverage, 6079, |
| 140040 | GIR_EraseRootFromParent_Done, |
| 140041 | // Label 6689: @451296 |
| 140042 | GIM_Try, /*On fail goto*//*Label 6690*/ GIMT_Encode4(451404), // Rule ID 6077 // |
| 140043 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140044 | GIM_CheckHasNoUse, /*MI*/0, |
| 140045 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140046 | // MIs[0] offset |
| 140047 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140048 | // MIs[0] auxiliary |
| 140049 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140050 | // MIs[0] Operand 9 |
| 140051 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140053 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_OFFEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140057 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140058 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140059 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140060 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140061 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140062 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140063 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN), |
| 140065 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140066 | GIR_RootToRootCopy, /*OpIdx*/5, // voffset |
| 140067 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140069 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140070 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140072 | GIR_RootConstrainSelectedInstOperands, |
| 140073 | // GIR_Coverage, 6077, |
| 140074 | GIR_EraseRootFromParent_Done, |
| 140075 | // Label 6690: @451404 |
| 140076 | GIM_Try, /*On fail goto*//*Label 6691*/ GIMT_Encode4(451509), // Rule ID 6085 // |
| 140077 | GIM_CheckHasNoUse, /*MI*/0, |
| 140078 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140079 | // MIs[0] offset |
| 140080 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140081 | // MIs[0] auxiliary |
| 140082 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140083 | // MIs[0] Operand 9 |
| 140084 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140086 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140087 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140088 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140090 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140091 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140092 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140093 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140094 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140095 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140096 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN), |
| 140098 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140099 | GIR_RootToRootCopy, /*OpIdx*/5, // voffset |
| 140100 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140102 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140103 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140104 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140105 | GIR_RootConstrainSelectedInstOperands, |
| 140106 | // GIR_Coverage, 6085, |
| 140107 | GIR_EraseRootFromParent_Done, |
| 140108 | // Label 6691: @451509 |
| 140109 | GIM_Try, /*On fail goto*//*Label 6692*/ GIMT_Encode4(451657), // Rule ID 6073 // |
| 140110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140111 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140112 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140113 | // MIs[0] offset |
| 140114 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140115 | // MIs[0] auxiliary |
| 140116 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140117 | // MIs[0] Operand 9 |
| 140118 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140119 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140120 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140121 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140122 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140123 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140124 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140125 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140126 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140127 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140128 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140129 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140130 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140131 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_OFFEN_RTN), |
| 140133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140134 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140135 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140136 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140137 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140138 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140139 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140140 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140141 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140144 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140145 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140146 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140147 | // GIR_Coverage, 6073, |
| 140148 | GIR_EraseRootFromParent_Done, |
| 140149 | // Label 6692: @451657 |
| 140150 | GIM_Try, /*On fail goto*//*Label 6693*/ GIMT_Encode4(451802), // Rule ID 6081 // |
| 140151 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140152 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140153 | // MIs[0] offset |
| 140154 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140155 | // MIs[0] auxiliary |
| 140156 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140157 | // MIs[0] Operand 9 |
| 140158 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140160 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140162 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140163 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140164 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140165 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140166 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140167 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140168 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140169 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140170 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140171 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140172 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_OFFEN_RTN), |
| 140173 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140174 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140175 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140176 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140177 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140178 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140179 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140180 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140181 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140183 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140184 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140185 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140186 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140187 | // GIR_Coverage, 6081, |
| 140188 | GIR_EraseRootFromParent_Done, |
| 140189 | // Label 6693: @451802 |
| 140190 | GIM_Try, /*On fail goto*//*Label 6694*/ GIMT_Encode4(451902), // Rule ID 6076 // |
| 140191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140192 | GIM_CheckHasNoUse, /*MI*/0, |
| 140193 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140194 | // MIs[0] offset |
| 140195 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140196 | // MIs[0] auxiliary |
| 140197 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140198 | // MIs[0] Operand 9 |
| 140199 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140201 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_IDXEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140202 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140203 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140204 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140205 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140206 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140207 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140208 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140209 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140210 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140211 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN), |
| 140213 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140214 | GIR_RootToRootCopy, /*OpIdx*/4, // vindex |
| 140215 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140217 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140220 | GIR_RootConstrainSelectedInstOperands, |
| 140221 | // GIR_Coverage, 6076, |
| 140222 | GIR_EraseRootFromParent_Done, |
| 140223 | // Label 6694: @451902 |
| 140224 | GIM_Try, /*On fail goto*//*Label 6695*/ GIMT_Encode4(451999), // Rule ID 6084 // |
| 140225 | GIM_CheckHasNoUse, /*MI*/0, |
| 140226 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140227 | // MIs[0] offset |
| 140228 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140229 | // MIs[0] auxiliary |
| 140230 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140231 | // MIs[0] Operand 9 |
| 140232 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140234 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140238 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140239 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140240 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140241 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140242 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140243 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140244 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN), |
| 140246 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140247 | GIR_RootToRootCopy, /*OpIdx*/4, // vindex |
| 140248 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140250 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140253 | GIR_RootConstrainSelectedInstOperands, |
| 140254 | // GIR_Coverage, 6084, |
| 140255 | GIR_EraseRootFromParent_Done, |
| 140256 | // Label 6695: @451999 |
| 140257 | GIM_Try, /*On fail goto*//*Label 6696*/ GIMT_Encode4(452139), // Rule ID 6072 // |
| 140258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140259 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140261 | // MIs[0] offset |
| 140262 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140263 | // MIs[0] auxiliary |
| 140264 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140265 | // MIs[0] Operand 9 |
| 140266 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140268 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140270 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140271 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140272 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140273 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140274 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140275 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140276 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140277 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140278 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140279 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140280 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_IDXEN_RTN), |
| 140281 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140282 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140283 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140284 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140285 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140286 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140287 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140288 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140289 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140292 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140293 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140294 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140295 | // GIR_Coverage, 6072, |
| 140296 | GIR_EraseRootFromParent_Done, |
| 140297 | // Label 6696: @452139 |
| 140298 | GIM_Try, /*On fail goto*//*Label 6697*/ GIMT_Encode4(452276), // Rule ID 6080 // |
| 140299 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140300 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140301 | // MIs[0] offset |
| 140302 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140303 | // MIs[0] auxiliary |
| 140304 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140305 | // MIs[0] Operand 9 |
| 140306 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140308 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140309 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140310 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140311 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140312 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140313 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140314 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140315 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140316 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140317 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140318 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140319 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140320 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_IDXEN_RTN), |
| 140321 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140322 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140323 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140324 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140325 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140326 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140327 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140328 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140329 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140332 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140333 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140334 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140335 | // GIR_Coverage, 6080, |
| 140336 | GIR_EraseRootFromParent_Done, |
| 140337 | // Label 6697: @452276 |
| 140338 | GIM_Try, /*On fail goto*//*Label 6698*/ GIMT_Encode4(452414), // Rule ID 6078 // |
| 140339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140340 | GIM_CheckHasNoUse, /*MI*/0, |
| 140341 | // MIs[0] offset |
| 140342 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140343 | // MIs[0] auxiliary |
| 140344 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140345 | // MIs[0] Operand 9 |
| 140346 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140347 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140348 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_BOTHEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140349 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140350 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140351 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140352 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140353 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140354 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140355 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140356 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140357 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140358 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140359 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140360 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140361 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140362 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140363 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140364 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140365 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140366 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140367 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140368 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN), |
| 140370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140371 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 140372 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140374 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140375 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140376 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140377 | GIR_RootConstrainSelectedInstOperands, |
| 140378 | // GIR_Coverage, 6078, |
| 140379 | GIR_EraseRootFromParent_Done, |
| 140380 | // Label 6698: @452414 |
| 140381 | GIM_Try, /*On fail goto*//*Label 6699*/ GIMT_Encode4(452549), // Rule ID 6086 // |
| 140382 | GIM_CheckHasNoUse, /*MI*/0, |
| 140383 | // MIs[0] offset |
| 140384 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140385 | // MIs[0] auxiliary |
| 140386 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140387 | // MIs[0] Operand 9 |
| 140388 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140390 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140391 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140392 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140393 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140394 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140395 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140396 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140397 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140398 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140399 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140400 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140401 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140402 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140403 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140404 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140405 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 140406 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140407 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 140408 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140409 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN), |
| 140412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140413 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 140414 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140416 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140418 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140419 | GIR_RootConstrainSelectedInstOperands, |
| 140420 | // GIR_Coverage, 6086, |
| 140421 | GIR_EraseRootFromParent_Done, |
| 140422 | // Label 6699: @452549 |
| 140423 | GIM_Try, /*On fail goto*//*Label 6700*/ GIMT_Encode4(452725), // Rule ID 6074 // |
| 140424 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140425 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140426 | // MIs[0] offset |
| 140427 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140428 | // MIs[0] auxiliary |
| 140429 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140430 | // MIs[0] Operand 9 |
| 140431 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140433 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140434 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140435 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140436 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 140437 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140438 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140439 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140440 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3, |
| 140441 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140442 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11, |
| 140443 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140444 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140445 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140446 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140447 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140448 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140449 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140450 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140451 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140452 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140453 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140454 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140455 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_BOTHEN_RTN), |
| 140456 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140457 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140458 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 140459 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140460 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140461 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140462 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140463 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140464 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140466 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140467 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140468 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140469 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140470 | // GIR_Coverage, 6074, |
| 140471 | GIR_EraseRootFromParent_Done, |
| 140472 | // Label 6700: @452725 |
| 140473 | GIM_Try, /*On fail goto*//*Label 6701*/ GIMT_Encode4(452898), // Rule ID 6082 // |
| 140474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140475 | // MIs[0] offset |
| 140476 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140477 | // MIs[0] auxiliary |
| 140478 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140479 | // MIs[0] Operand 9 |
| 140480 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140482 | // (SIbuffer_atomic_cmpswap:{ *:[i32] } i32:{ *:[i32] }:$data, i32:{ *:[i32] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i32] } (BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$data, sub0:{ *:[i32] }, anonymous_15876:{ *:[i32] }:$cmp, sub1:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0:{ *:[i32] }) |
| 140483 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 140484 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140485 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 140486 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140487 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140488 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140489 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3, |
| 140490 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140491 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11, |
| 140492 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140493 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140494 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140495 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140496 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140497 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140498 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140499 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140500 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140501 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140502 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140503 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140504 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_VBUFFER_BOTHEN_RTN), |
| 140505 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140506 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140507 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 140508 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140509 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140510 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140511 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140512 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140513 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140514 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140515 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140516 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0), |
| 140517 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 140518 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140519 | // GIR_Coverage, 6082, |
| 140520 | GIR_EraseRootFromParent_Done, |
| 140521 | // Label 6701: @452898 |
| 140522 | GIM_Reject, |
| 140523 | // Label 6685: @452899 |
| 140524 | GIM_Reject, |
| 140525 | // Label 6683: @452900 |
| 140526 | GIM_Try, /*On fail goto*//*Label 6702*/ GIMT_Encode4(455036), |
| 140527 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 140528 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s64, |
| 140529 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_v4s32, |
| 140530 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 140531 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 140532 | GIM_RootCheckType, /*Op*/6, /*Type*/GILLT_s32, |
| 140533 | GIM_Try, /*On fail goto*//*Label 6703*/ GIMT_Encode4(453033), // Rule ID 6091 // |
| 140534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140535 | GIM_CheckHasNoUse, /*MI*/0, |
| 140536 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140537 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140538 | // MIs[0] offset |
| 140539 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140540 | // MIs[0] auxiliary |
| 140541 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140542 | // MIs[0] Operand 9 |
| 140543 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140545 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140549 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140550 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140551 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140552 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140553 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140554 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140555 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET), |
| 140557 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140558 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140560 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140561 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140562 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140563 | GIR_RootConstrainSelectedInstOperands, |
| 140564 | // GIR_Coverage, 6091, |
| 140565 | GIR_EraseRootFromParent_Done, |
| 140566 | // Label 6703: @453033 |
| 140567 | GIM_Try, /*On fail goto*//*Label 6704*/ GIMT_Encode4(453140), // Rule ID 6099 // |
| 140568 | GIM_CheckHasNoUse, /*MI*/0, |
| 140569 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140570 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140571 | // MIs[0] offset |
| 140572 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140573 | // MIs[0] auxiliary |
| 140574 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140575 | // MIs[0] Operand 9 |
| 140576 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140577 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140578 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140579 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140580 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140581 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140582 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140583 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140584 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140585 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140586 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140587 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140588 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET), |
| 140590 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140591 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140593 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140596 | GIR_RootConstrainSelectedInstOperands, |
| 140597 | // GIR_Coverage, 6099, |
| 140598 | GIR_EraseRootFromParent_Done, |
| 140599 | // Label 6704: @453140 |
| 140600 | GIM_Try, /*On fail goto*//*Label 6705*/ GIMT_Encode4(453288), // Rule ID 6087 // |
| 140601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140602 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140603 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140604 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140605 | // MIs[0] offset |
| 140606 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140607 | // MIs[0] auxiliary |
| 140608 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140609 | // MIs[0] Operand 9 |
| 140610 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140611 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140612 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140613 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140614 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140615 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140616 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140617 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140618 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140619 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140620 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140621 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140622 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140623 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140624 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFSET_RTN), |
| 140625 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140626 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140627 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140628 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140629 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140630 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140631 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140632 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140635 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140636 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140637 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140638 | // GIR_Coverage, 6087, |
| 140639 | GIR_EraseRootFromParent_Done, |
| 140640 | // Label 6705: @453288 |
| 140641 | GIM_Try, /*On fail goto*//*Label 6706*/ GIMT_Encode4(453433), // Rule ID 6095 // |
| 140642 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140643 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140644 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140645 | // MIs[0] offset |
| 140646 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140647 | // MIs[0] auxiliary |
| 140648 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140649 | // MIs[0] Operand 9 |
| 140650 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140652 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140653 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140654 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140655 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140656 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140657 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140658 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140659 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140660 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140661 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140662 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140663 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140664 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFSET_RTN), |
| 140665 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140666 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140667 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140668 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140669 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140670 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140671 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140672 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140675 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140676 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140677 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140678 | // GIR_Coverage, 6095, |
| 140679 | GIR_EraseRootFromParent_Done, |
| 140680 | // Label 6706: @453433 |
| 140681 | GIM_Try, /*On fail goto*//*Label 6707*/ GIMT_Encode4(453541), // Rule ID 6093 // |
| 140682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140683 | GIM_CheckHasNoUse, /*MI*/0, |
| 140684 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140685 | // MIs[0] offset |
| 140686 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140687 | // MIs[0] auxiliary |
| 140688 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140689 | // MIs[0] Operand 9 |
| 140690 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140692 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_OFFEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140693 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140694 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140695 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140696 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140697 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140698 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140699 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140700 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140701 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140702 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140703 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN), |
| 140704 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140705 | GIR_RootToRootCopy, /*OpIdx*/5, // voffset |
| 140706 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140708 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140709 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140710 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140711 | GIR_RootConstrainSelectedInstOperands, |
| 140712 | // GIR_Coverage, 6093, |
| 140713 | GIR_EraseRootFromParent_Done, |
| 140714 | // Label 6707: @453541 |
| 140715 | GIM_Try, /*On fail goto*//*Label 6708*/ GIMT_Encode4(453646), // Rule ID 6101 // |
| 140716 | GIM_CheckHasNoUse, /*MI*/0, |
| 140717 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140718 | // MIs[0] offset |
| 140719 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140720 | // MIs[0] auxiliary |
| 140721 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140722 | // MIs[0] Operand 9 |
| 140723 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140724 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140725 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140726 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140727 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140728 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140729 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140730 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140731 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140732 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140733 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140734 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140735 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140736 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN), |
| 140737 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140738 | GIR_RootToRootCopy, /*OpIdx*/5, // voffset |
| 140739 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140741 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140742 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140743 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140744 | GIR_RootConstrainSelectedInstOperands, |
| 140745 | // GIR_Coverage, 6101, |
| 140746 | GIR_EraseRootFromParent_Done, |
| 140747 | // Label 6708: @453646 |
| 140748 | GIM_Try, /*On fail goto*//*Label 6709*/ GIMT_Encode4(453794), // Rule ID 6089 // |
| 140749 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140750 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140751 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140752 | // MIs[0] offset |
| 140753 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140754 | // MIs[0] auxiliary |
| 140755 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140756 | // MIs[0] Operand 9 |
| 140757 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140759 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140760 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140761 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140762 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140763 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140764 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140765 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140766 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140767 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140768 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140769 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140770 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140771 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_OFFEN_RTN), |
| 140772 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140773 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140774 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140775 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140776 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140777 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140778 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140779 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140780 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140781 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140782 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140783 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140784 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140785 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140786 | // GIR_Coverage, 6089, |
| 140787 | GIR_EraseRootFromParent_Done, |
| 140788 | // Label 6709: @453794 |
| 140789 | GIM_Try, /*On fail goto*//*Label 6710*/ GIMT_Encode4(453939), // Rule ID 6097 // |
| 140790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 140792 | // MIs[0] offset |
| 140793 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140794 | // MIs[0] auxiliary |
| 140795 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140796 | // MIs[0] Operand 9 |
| 140797 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/9, GIMT_Encode8(0), |
| 140798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140799 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140800 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140801 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140802 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140803 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140804 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140805 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140806 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140807 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140808 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140809 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140810 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_OFFEN_RTN), |
| 140812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140813 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140814 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140815 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140816 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140817 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140818 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140819 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140820 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140823 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140824 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140825 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140826 | // GIR_Coverage, 6097, |
| 140827 | GIR_EraseRootFromParent_Done, |
| 140828 | // Label 6710: @453939 |
| 140829 | GIM_Try, /*On fail goto*//*Label 6711*/ GIMT_Encode4(454039), // Rule ID 6092 // |
| 140830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140831 | GIM_CheckHasNoUse, /*MI*/0, |
| 140832 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140833 | // MIs[0] offset |
| 140834 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140835 | // MIs[0] auxiliary |
| 140836 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140837 | // MIs[0] Operand 9 |
| 140838 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140840 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_IDXEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140841 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140842 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140843 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140844 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140845 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140846 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140847 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140848 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140849 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140851 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN), |
| 140852 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140853 | GIR_RootToRootCopy, /*OpIdx*/4, // vindex |
| 140854 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140855 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140856 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140857 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140859 | GIR_RootConstrainSelectedInstOperands, |
| 140860 | // GIR_Coverage, 6092, |
| 140861 | GIR_EraseRootFromParent_Done, |
| 140862 | // Label 6711: @454039 |
| 140863 | GIM_Try, /*On fail goto*//*Label 6712*/ GIMT_Encode4(454136), // Rule ID 6100 // |
| 140864 | GIM_CheckHasNoUse, /*MI*/0, |
| 140865 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140866 | // MIs[0] offset |
| 140867 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140868 | // MIs[0] auxiliary |
| 140869 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140870 | // MIs[0] Operand 9 |
| 140871 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140873 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140874 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140875 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140876 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140877 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140878 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 140879 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140880 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 140881 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140882 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140883 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140884 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN), |
| 140885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 140886 | GIR_RootToRootCopy, /*OpIdx*/4, // vindex |
| 140887 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 140888 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140889 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 140890 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 140891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140892 | GIR_RootConstrainSelectedInstOperands, |
| 140893 | // GIR_Coverage, 6100, |
| 140894 | GIR_EraseRootFromParent_Done, |
| 140895 | // Label 6712: @454136 |
| 140896 | GIM_Try, /*On fail goto*//*Label 6713*/ GIMT_Encode4(454276), // Rule ID 6088 // |
| 140897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140898 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140899 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140900 | // MIs[0] offset |
| 140901 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140902 | // MIs[0] auxiliary |
| 140903 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140904 | // MIs[0] Operand 9 |
| 140905 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140907 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140909 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140910 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140911 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140912 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140913 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140914 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140915 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140916 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140917 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140918 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140919 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_IDXEN_RTN), |
| 140920 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140921 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140922 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140923 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140924 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140925 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140926 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140927 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140928 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140930 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140931 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140932 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140933 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140934 | // GIR_Coverage, 6088, |
| 140935 | GIR_EraseRootFromParent_Done, |
| 140936 | // Label 6713: @454276 |
| 140937 | GIM_Try, /*On fail goto*//*Label 6714*/ GIMT_Encode4(454413), // Rule ID 6096 // |
| 140938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140939 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/5, 0, |
| 140940 | // MIs[0] offset |
| 140941 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140942 | // MIs[0] auxiliary |
| 140943 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140944 | // MIs[0] Operand 9 |
| 140945 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140947 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 140948 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140949 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 140950 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140951 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140952 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 140953 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 140954 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 140955 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 140956 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 140957 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140958 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140959 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_IDXEN_RTN), |
| 140960 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140961 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 140962 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140963 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 140964 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 140965 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 140966 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 140967 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 140968 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 140969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 140970 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 140971 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 140972 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 140973 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 140974 | // GIR_Coverage, 6096, |
| 140975 | GIR_EraseRootFromParent_Done, |
| 140976 | // Label 6714: @454413 |
| 140977 | GIM_Try, /*On fail goto*//*Label 6715*/ GIMT_Encode4(454551), // Rule ID 6094 // |
| 140978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 140979 | GIM_CheckHasNoUse, /*MI*/0, |
| 140980 | // MIs[0] offset |
| 140981 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 140982 | // MIs[0] auxiliary |
| 140983 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 140984 | // MIs[0] Operand 9 |
| 140985 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 140986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 140987 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 140988 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 140989 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 140990 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 140991 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 140992 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 140993 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 140994 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 140995 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 140996 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 140997 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140998 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 140999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 141002 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 141003 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 141004 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 141005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 141006 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141007 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN), |
| 141009 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 141011 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 141012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141013 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 141014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141016 | GIR_RootConstrainSelectedInstOperands, |
| 141017 | // GIR_Coverage, 6094, |
| 141018 | GIR_EraseRootFromParent_Done, |
| 141019 | // Label 6715: @454551 |
| 141020 | GIM_Try, /*On fail goto*//*Label 6716*/ GIMT_Encode4(454686), // Rule ID 6102 // |
| 141021 | GIM_CheckHasNoUse, /*MI*/0, |
| 141022 | // MIs[0] offset |
| 141023 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141024 | // MIs[0] auxiliary |
| 141025 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141026 | // MIs[0] Operand 9 |
| 141027 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 141028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141029 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cmpswap_noret>> => (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141030 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 141031 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s64, |
| 141032 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141033 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141034 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 141035 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/3, |
| 141036 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 141037 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/11, |
| 141038 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141039 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141040 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141041 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141042 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141043 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 141044 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/4, |
| 141045 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 141046 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/24, |
| 141047 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 141048 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141049 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN), |
| 141051 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141052 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/1, |
| 141053 | GIR_RootToRootCopy, /*OpIdx*/3, // rsrc |
| 141054 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141055 | GIR_RootToRootCopy, /*OpIdx*/7, // offset |
| 141056 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141057 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141058 | GIR_RootConstrainSelectedInstOperands, |
| 141059 | // GIR_Coverage, 6102, |
| 141060 | GIR_EraseRootFromParent_Done, |
| 141061 | // Label 6716: @454686 |
| 141062 | GIM_Try, /*On fail goto*//*Label 6717*/ GIMT_Encode4(454862), // Rule ID 6090 // |
| 141063 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 141065 | // MIs[0] offset |
| 141066 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141067 | // MIs[0] auxiliary |
| 141068 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141069 | // MIs[0] Operand 9 |
| 141070 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 141071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141072 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 141073 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 141074 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 141075 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 141076 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141077 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141078 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 141079 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3, |
| 141080 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 141081 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11, |
| 141082 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141083 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141084 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141085 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141086 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141087 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 141088 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 141089 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 141090 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 141091 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 141092 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141093 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141094 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_BOTHEN_RTN), |
| 141095 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141096 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 141097 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 141098 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 141099 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141100 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 141101 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141102 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141103 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 141104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 141105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 141106 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 141107 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 141108 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 141109 | // GIR_Coverage, 6090, |
| 141110 | GIR_EraseRootFromParent_Done, |
| 141111 | // Label 6717: @454862 |
| 141112 | GIM_Try, /*On fail goto*//*Label 6718*/ GIMT_Encode4(455035), // Rule ID 6098 // |
| 141113 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 141114 | // MIs[0] offset |
| 141115 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141116 | // MIs[0] auxiliary |
| 141117 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141118 | // MIs[0] Operand 9 |
| 141119 | GIM_CheckIsImm, /*MI*/0, /*Op*/9, |
| 141120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/6, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141121 | // (SIbuffer_atomic_cmpswap:{ *:[i64] } i64:{ *:[i64] }:$data, i64:{ *:[i64] }:$cmp, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (EXTRACT_SUBREG:{ *:[i64] } (BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[v8i16] } VReg_128:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$data, sub0_sub1:{ *:[i32] }, anonymous_15875:{ *:[i64] }:$cmp, sub2_sub3:{ *:[i32] }), (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)), sub0_sub1:{ *:[i32] }) |
| 141122 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_v8s16, |
| 141123 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_v8s16, |
| 141124 | GIR_MakeTempReg, /*TempRegID*/2, /*TypeID*/GILLT_s64, |
| 141125 | GIR_BuildMI, /*InsnID*/3, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141126 | GIR_AddTempRegister, /*InsnID*/3, /*TempRegID*/2, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141127 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/4, // vindex |
| 141128 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/3, |
| 141129 | GIR_Copy, /*NewInsnID*/3, /*OldInsnID*/0, /*OpIdx*/5, // voffset |
| 141130 | GIR_AddImm8, /*InsnID*/3, /*SubRegIndex*/11, |
| 141131 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141132 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141133 | GIR_ConstrainOperandRC, /*InsnID*/3, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141134 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141135 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141136 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/1, // data |
| 141137 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/4, |
| 141138 | GIR_Copy, /*NewInsnID*/2, /*OldInsnID*/0, /*OpIdx*/2, // cmp |
| 141139 | GIR_AddImm8, /*InsnID*/2, /*SubRegIndex*/24, |
| 141140 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_128RegClassID), |
| 141141 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/1, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141142 | GIR_ConstrainOperandRC, /*InsnID*/2, /*Op*/3, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141143 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_CMPSWAP_X2_VBUFFER_BOTHEN_RTN), |
| 141144 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141145 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 141146 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/2, |
| 141147 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // rsrc |
| 141148 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141149 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/7, // offset |
| 141150 | GIR_CustomOperandRenderer, /*InsnID*/1, /*OldInsnID*/0, /*OpIdx*/8, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141151 | GIR_MergeMemOperands, /*InsnID*/1, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141152 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 141153 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(TargetOpcode::COPY), |
| 141154 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[dst] |
| 141155 | GIR_AddTempSubRegister, /*InsnID*/0, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(0), GIMT_Encode2(AMDGPU::sub0_sub1), |
| 141156 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/0, GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 141157 | GIR_ConstrainOperandRC, /*InsnID*/0, /*Op*/1, GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 141158 | // GIR_Coverage, 6098, |
| 141159 | GIR_EraseRootFromParent_Done, |
| 141160 | // Label 6718: @455035 |
| 141161 | GIM_Reject, |
| 141162 | // Label 6702: @455036 |
| 141163 | GIM_Reject, |
| 141164 | // Label 6684: @455037 |
| 141165 | GIM_Reject, |
| 141166 | // Label 111: @455038 |
| 141167 | GIM_Try, /*On fail goto*//*Label 6719*/ GIMT_Encode4(455654), |
| 141168 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 141169 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 141170 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 141171 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 141172 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 141173 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 141174 | GIM_Try, /*On fail goto*//*Label 6720*/ GIMT_Encode4(455129), // Rule ID 5923 // |
| 141175 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 141176 | GIM_CheckHasNoUse, /*MI*/0, |
| 141177 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141178 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141179 | // MIs[0] offset |
| 141180 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141181 | // MIs[0] auxiliary |
| 141182 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141183 | // MIs[0] Operand 8 |
| 141184 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141185 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141186 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>> => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET), |
| 141188 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141189 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141191 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141192 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141193 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141194 | GIR_RootConstrainSelectedInstOperands, |
| 141195 | // GIR_Coverage, 5923, |
| 141196 | GIR_EraseRootFromParent_Done, |
| 141197 | // Label 6720: @455129 |
| 141198 | GIM_Try, /*On fail goto*//*Label 6721*/ GIMT_Encode4(455201), // Rule ID 5919 // |
| 141199 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 141200 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141201 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141202 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141203 | // MIs[0] offset |
| 141204 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141205 | // MIs[0] auxiliary |
| 141206 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141207 | // MIs[0] Operand 8 |
| 141208 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141210 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141211 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFSET_RTN), |
| 141212 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141213 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141214 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141216 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141217 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141218 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141219 | GIR_RootConstrainSelectedInstOperands, |
| 141220 | // GIR_Coverage, 5919, |
| 141221 | GIR_EraseRootFromParent_Done, |
| 141222 | // Label 6721: @455201 |
| 141223 | GIM_Try, /*On fail goto*//*Label 6722*/ GIMT_Encode4(455267), // Rule ID 5925 // |
| 141224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 141225 | GIM_CheckHasNoUse, /*MI*/0, |
| 141226 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141227 | // MIs[0] offset |
| 141228 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141229 | // MIs[0] auxiliary |
| 141230 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141231 | // MIs[0] Operand 8 |
| 141232 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141234 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>> => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN), |
| 141236 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141237 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141238 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141240 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141241 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141242 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141243 | GIR_RootConstrainSelectedInstOperands, |
| 141244 | // GIR_Coverage, 5925, |
| 141245 | GIR_EraseRootFromParent_Done, |
| 141246 | // Label 6722: @455267 |
| 141247 | GIM_Try, /*On fail goto*//*Label 6723*/ GIMT_Encode4(455337), // Rule ID 5921 // |
| 141248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 141249 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141250 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141251 | // MIs[0] offset |
| 141252 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141253 | // MIs[0] auxiliary |
| 141254 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141255 | // MIs[0] Operand 8 |
| 141256 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141258 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_OFFEN_RTN), |
| 141260 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141261 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141262 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141263 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141265 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141266 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141267 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141268 | GIR_RootConstrainSelectedInstOperands, |
| 141269 | // GIR_Coverage, 5921, |
| 141270 | GIR_EraseRootFromParent_Done, |
| 141271 | // Label 6723: @455337 |
| 141272 | GIM_Try, /*On fail goto*//*Label 6724*/ GIMT_Encode4(455395), // Rule ID 5924 // |
| 141273 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 141274 | GIM_CheckHasNoUse, /*MI*/0, |
| 141275 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141276 | // MIs[0] offset |
| 141277 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141278 | // MIs[0] auxiliary |
| 141279 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141280 | // MIs[0] Operand 8 |
| 141281 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141283 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>> => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141284 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN), |
| 141285 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141286 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141287 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141288 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141289 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141290 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141291 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141292 | GIR_RootConstrainSelectedInstOperands, |
| 141293 | // GIR_Coverage, 5924, |
| 141294 | GIR_EraseRootFromParent_Done, |
| 141295 | // Label 6724: @455395 |
| 141296 | GIM_Try, /*On fail goto*//*Label 6725*/ GIMT_Encode4(455457), // Rule ID 5920 // |
| 141297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 141298 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141299 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141300 | // MIs[0] offset |
| 141301 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141302 | // MIs[0] auxiliary |
| 141303 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141304 | // MIs[0] Operand 8 |
| 141305 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141306 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141307 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141308 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_IDXEN_RTN), |
| 141309 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141310 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141311 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141312 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141314 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141315 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141316 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141317 | GIR_RootConstrainSelectedInstOperands, |
| 141318 | // GIR_Coverage, 5920, |
| 141319 | GIR_EraseRootFromParent_Done, |
| 141320 | // Label 6725: @455457 |
| 141321 | GIM_Try, /*On fail goto*//*Label 6726*/ GIMT_Encode4(455553), // Rule ID 5926 // |
| 141322 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicCSubNoRtnInsts), |
| 141323 | GIM_CheckHasNoUse, /*MI*/0, |
| 141324 | // MIs[0] offset |
| 141325 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141326 | // MIs[0] auxiliary |
| 141327 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141328 | // MIs[0] Operand 8 |
| 141329 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141330 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141331 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_cond_sub_u32_noret>> => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141336 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141338 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141339 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141340 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141341 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN), |
| 141343 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141344 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141345 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141347 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141348 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141350 | GIR_RootConstrainSelectedInstOperands, |
| 141351 | // GIR_Coverage, 5926, |
| 141352 | GIR_EraseRootFromParent_Done, |
| 141353 | // Label 6726: @455553 |
| 141354 | GIM_Try, /*On fail goto*//*Label 6727*/ GIMT_Encode4(455653), // Rule ID 5922 // |
| 141355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 141356 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141357 | // MIs[0] offset |
| 141358 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141359 | // MIs[0] auxiliary |
| 141360 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141361 | // MIs[0] Operand 8 |
| 141362 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141364 | // (SIbuffer_atomic_cond_sub_u32:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141365 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141366 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141367 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141368 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141369 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141370 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141371 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141372 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141373 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141374 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141375 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_COND_SUB_U32_VBUFFER_BOTHEN_RTN), |
| 141376 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141377 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141379 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141381 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141384 | GIR_RootConstrainSelectedInstOperands, |
| 141385 | // GIR_Coverage, 5922, |
| 141386 | GIR_EraseRootFromParent_Done, |
| 141387 | // Label 6727: @455653 |
| 141388 | GIM_Reject, |
| 141389 | // Label 6719: @455654 |
| 141390 | GIM_Reject, |
| 141391 | // Label 112: @455655 |
| 141392 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6730*/ GIMT_Encode4(458038), |
| 141393 | /*GILLT_s32*//*Label 6728*/ GIMT_Encode4(455674), |
| 141394 | /*GILLT_s64*//*Label 6729*/ GIMT_Encode4(456856), |
| 141395 | // Label 6728: @455674 |
| 141396 | GIM_Try, /*On fail goto*//*Label 6731*/ GIMT_Encode4(456855), |
| 141397 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 141398 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 141399 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 141400 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 141401 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 141402 | GIM_Try, /*On fail goto*//*Label 6732*/ GIMT_Encode4(455762), // Rule ID 5683 // |
| 141403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141404 | GIM_CheckHasNoUse, /*MI*/0, |
| 141405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141406 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141407 | // MIs[0] offset |
| 141408 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141409 | // MIs[0] auxiliary |
| 141410 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141411 | // MIs[0] Operand 8 |
| 141412 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141413 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141414 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141415 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET), |
| 141416 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141417 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141419 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141420 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141422 | GIR_RootConstrainSelectedInstOperands, |
| 141423 | // GIR_Coverage, 5683, |
| 141424 | GIR_EraseRootFromParent_Done, |
| 141425 | // Label 6732: @455762 |
| 141426 | GIM_Try, /*On fail goto*//*Label 6733*/ GIMT_Encode4(455827), // Rule ID 5691 // |
| 141427 | GIM_CheckHasNoUse, /*MI*/0, |
| 141428 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141429 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141430 | // MIs[0] offset |
| 141431 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141432 | // MIs[0] auxiliary |
| 141433 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141434 | // MIs[0] Operand 8 |
| 141435 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141436 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141437 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET), |
| 141439 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141440 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141442 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141445 | GIR_RootConstrainSelectedInstOperands, |
| 141446 | // GIR_Coverage, 5691, |
| 141447 | GIR_EraseRootFromParent_Done, |
| 141448 | // Label 6733: @455827 |
| 141449 | GIM_Try, /*On fail goto*//*Label 6734*/ GIMT_Encode4(455899), // Rule ID 5679 // |
| 141450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141451 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141453 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141454 | // MIs[0] offset |
| 141455 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141456 | // MIs[0] auxiliary |
| 141457 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141458 | // MIs[0] Operand 8 |
| 141459 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141460 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141461 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFSET_RTN), |
| 141463 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141464 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141465 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141467 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141470 | GIR_RootConstrainSelectedInstOperands, |
| 141471 | // GIR_Coverage, 5679, |
| 141472 | GIR_EraseRootFromParent_Done, |
| 141473 | // Label 6734: @455899 |
| 141474 | GIM_Try, /*On fail goto*//*Label 6735*/ GIMT_Encode4(455968), // Rule ID 5687 // |
| 141475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141476 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141477 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141478 | // MIs[0] offset |
| 141479 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141480 | // MIs[0] auxiliary |
| 141481 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141482 | // MIs[0] Operand 8 |
| 141483 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141485 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFSET_RTN), |
| 141487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141488 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141489 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141491 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141492 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141493 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141494 | GIR_RootConstrainSelectedInstOperands, |
| 141495 | // GIR_Coverage, 5687, |
| 141496 | GIR_EraseRootFromParent_Done, |
| 141497 | // Label 6735: @455968 |
| 141498 | GIM_Try, /*On fail goto*//*Label 6736*/ GIMT_Encode4(456034), // Rule ID 5685 // |
| 141499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141500 | GIM_CheckHasNoUse, /*MI*/0, |
| 141501 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141502 | // MIs[0] offset |
| 141503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141504 | // MIs[0] auxiliary |
| 141505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141506 | // MIs[0] Operand 8 |
| 141507 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141509 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFEN), |
| 141511 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141512 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141513 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141515 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141516 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141517 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141518 | GIR_RootConstrainSelectedInstOperands, |
| 141519 | // GIR_Coverage, 5685, |
| 141520 | GIR_EraseRootFromParent_Done, |
| 141521 | // Label 6736: @456034 |
| 141522 | GIM_Try, /*On fail goto*//*Label 6737*/ GIMT_Encode4(456097), // Rule ID 5693 // |
| 141523 | GIM_CheckHasNoUse, /*MI*/0, |
| 141524 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141525 | // MIs[0] offset |
| 141526 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141527 | // MIs[0] auxiliary |
| 141528 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141529 | // MIs[0] Operand 8 |
| 141530 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141531 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141532 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141533 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN), |
| 141534 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141535 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141536 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141537 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141538 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141539 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141541 | GIR_RootConstrainSelectedInstOperands, |
| 141542 | // GIR_Coverage, 5693, |
| 141543 | GIR_EraseRootFromParent_Done, |
| 141544 | // Label 6737: @456097 |
| 141545 | GIM_Try, /*On fail goto*//*Label 6738*/ GIMT_Encode4(456167), // Rule ID 5681 // |
| 141546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141547 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141548 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141549 | // MIs[0] offset |
| 141550 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141551 | // MIs[0] auxiliary |
| 141552 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141553 | // MIs[0] Operand 8 |
| 141554 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141555 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141556 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141557 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_OFFEN_RTN), |
| 141558 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141559 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141560 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141561 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141562 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141563 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141564 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141565 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141566 | GIR_RootConstrainSelectedInstOperands, |
| 141567 | // GIR_Coverage, 5681, |
| 141568 | GIR_EraseRootFromParent_Done, |
| 141569 | // Label 6738: @456167 |
| 141570 | GIM_Try, /*On fail goto*//*Label 6739*/ GIMT_Encode4(456234), // Rule ID 5689 // |
| 141571 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141572 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141573 | // MIs[0] offset |
| 141574 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141575 | // MIs[0] auxiliary |
| 141576 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141577 | // MIs[0] Operand 8 |
| 141578 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141579 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141580 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141581 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_OFFEN_RTN), |
| 141582 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141583 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141584 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141585 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141586 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141587 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141588 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141589 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141590 | GIR_RootConstrainSelectedInstOperands, |
| 141591 | // GIR_Coverage, 5689, |
| 141592 | GIR_EraseRootFromParent_Done, |
| 141593 | // Label 6739: @456234 |
| 141594 | GIM_Try, /*On fail goto*//*Label 6740*/ GIMT_Encode4(456292), // Rule ID 5684 // |
| 141595 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141596 | GIM_CheckHasNoUse, /*MI*/0, |
| 141597 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141598 | // MIs[0] offset |
| 141599 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141600 | // MIs[0] auxiliary |
| 141601 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141602 | // MIs[0] Operand 8 |
| 141603 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141604 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141605 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141606 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_IDXEN), |
| 141607 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141608 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141609 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141610 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141611 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141612 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141613 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141614 | GIR_RootConstrainSelectedInstOperands, |
| 141615 | // GIR_Coverage, 5684, |
| 141616 | GIR_EraseRootFromParent_Done, |
| 141617 | // Label 6740: @456292 |
| 141618 | GIM_Try, /*On fail goto*//*Label 6741*/ GIMT_Encode4(456347), // Rule ID 5692 // |
| 141619 | GIM_CheckHasNoUse, /*MI*/0, |
| 141620 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141621 | // MIs[0] offset |
| 141622 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141623 | // MIs[0] auxiliary |
| 141624 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141625 | // MIs[0] Operand 8 |
| 141626 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141627 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141628 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN), |
| 141630 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141631 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141632 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141634 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141635 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141636 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141637 | GIR_RootConstrainSelectedInstOperands, |
| 141638 | // GIR_Coverage, 5692, |
| 141639 | GIR_EraseRootFromParent_Done, |
| 141640 | // Label 6741: @456347 |
| 141641 | GIM_Try, /*On fail goto*//*Label 6742*/ GIMT_Encode4(456409), // Rule ID 5680 // |
| 141642 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141643 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141644 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141645 | // MIs[0] offset |
| 141646 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141647 | // MIs[0] auxiliary |
| 141648 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141649 | // MIs[0] Operand 8 |
| 141650 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141652 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_IDXEN_RTN), |
| 141654 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141655 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141656 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141657 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141659 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141660 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141662 | GIR_RootConstrainSelectedInstOperands, |
| 141663 | // GIR_Coverage, 5680, |
| 141664 | GIR_EraseRootFromParent_Done, |
| 141665 | // Label 6742: @456409 |
| 141666 | GIM_Try, /*On fail goto*//*Label 6743*/ GIMT_Encode4(456468), // Rule ID 5688 // |
| 141667 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141668 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141669 | // MIs[0] offset |
| 141670 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141671 | // MIs[0] auxiliary |
| 141672 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141673 | // MIs[0] Operand 8 |
| 141674 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141676 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_IDXEN_RTN), |
| 141678 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141679 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141680 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 141681 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141683 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141684 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141685 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141686 | GIR_RootConstrainSelectedInstOperands, |
| 141687 | // GIR_Coverage, 5688, |
| 141688 | GIR_EraseRootFromParent_Done, |
| 141689 | // Label 6743: @456468 |
| 141690 | GIM_Try, /*On fail goto*//*Label 6744*/ GIMT_Encode4(456564), // Rule ID 5686 // |
| 141691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141692 | GIM_CheckHasNoUse, /*MI*/0, |
| 141693 | // MIs[0] offset |
| 141694 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141695 | // MIs[0] auxiliary |
| 141696 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141697 | // MIs[0] Operand 8 |
| 141698 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141700 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141701 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141702 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141703 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141704 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141705 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141706 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141707 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141708 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141709 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141710 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN), |
| 141712 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141713 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141714 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141716 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141717 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141718 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141719 | GIR_RootConstrainSelectedInstOperands, |
| 141720 | // GIR_Coverage, 5686, |
| 141721 | GIR_EraseRootFromParent_Done, |
| 141722 | // Label 6744: @456564 |
| 141723 | GIM_Try, /*On fail goto*//*Label 6745*/ GIMT_Encode4(456657), // Rule ID 5694 // |
| 141724 | GIM_CheckHasNoUse, /*MI*/0, |
| 141725 | // MIs[0] offset |
| 141726 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141727 | // MIs[0] auxiliary |
| 141728 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141729 | // MIs[0] Operand 8 |
| 141730 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141732 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141736 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141737 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141738 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141739 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141740 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141741 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141742 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN), |
| 141744 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141746 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141748 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141751 | GIR_RootConstrainSelectedInstOperands, |
| 141752 | // GIR_Coverage, 5694, |
| 141753 | GIR_EraseRootFromParent_Done, |
| 141754 | // Label 6745: @456657 |
| 141755 | GIM_Try, /*On fail goto*//*Label 6746*/ GIMT_Encode4(456757), // Rule ID 5682 // |
| 141756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141758 | // MIs[0] offset |
| 141759 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141760 | // MIs[0] auxiliary |
| 141761 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141762 | // MIs[0] Operand 8 |
| 141763 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141765 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141766 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141769 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141770 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141771 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141772 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141773 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141774 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141775 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_BOTHEN_RTN), |
| 141777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141778 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141780 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141782 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141785 | GIR_RootConstrainSelectedInstOperands, |
| 141786 | // GIR_Coverage, 5682, |
| 141787 | GIR_EraseRootFromParent_Done, |
| 141788 | // Label 6746: @456757 |
| 141789 | GIM_Try, /*On fail goto*//*Label 6747*/ GIMT_Encode4(456854), // Rule ID 5690 // |
| 141790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 141791 | // MIs[0] offset |
| 141792 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141793 | // MIs[0] auxiliary |
| 141794 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141795 | // MIs[0] Operand 8 |
| 141796 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 141797 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141798 | // (SIbuffer_atomic_dec:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141799 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 141800 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 141801 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 141802 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 141803 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 141804 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 141805 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 141806 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 141807 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141808 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 141809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_VBUFFER_BOTHEN_RTN), |
| 141810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141811 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141812 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 141813 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141815 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141816 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141818 | GIR_RootConstrainSelectedInstOperands, |
| 141819 | // GIR_Coverage, 5690, |
| 141820 | GIR_EraseRootFromParent_Done, |
| 141821 | // Label 6747: @456854 |
| 141822 | GIM_Reject, |
| 141823 | // Label 6731: @456855 |
| 141824 | GIM_Reject, |
| 141825 | // Label 6729: @456856 |
| 141826 | GIM_Try, /*On fail goto*//*Label 6748*/ GIMT_Encode4(458037), |
| 141827 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 141828 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 141829 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 141830 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 141831 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 141832 | GIM_Try, /*On fail goto*//*Label 6749*/ GIMT_Encode4(456944), // Rule ID 5883 // |
| 141833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141834 | GIM_CheckHasNoUse, /*MI*/0, |
| 141835 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141836 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141837 | // MIs[0] offset |
| 141838 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141839 | // MIs[0] auxiliary |
| 141840 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141841 | // MIs[0] Operand 8 |
| 141842 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141844 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET), |
| 141846 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141847 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141849 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141850 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141852 | GIR_RootConstrainSelectedInstOperands, |
| 141853 | // GIR_Coverage, 5883, |
| 141854 | GIR_EraseRootFromParent_Done, |
| 141855 | // Label 6749: @456944 |
| 141856 | GIM_Try, /*On fail goto*//*Label 6750*/ GIMT_Encode4(457009), // Rule ID 5891 // |
| 141857 | GIM_CheckHasNoUse, /*MI*/0, |
| 141858 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141859 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141860 | // MIs[0] offset |
| 141861 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141862 | // MIs[0] auxiliary |
| 141863 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141864 | // MIs[0] Operand 8 |
| 141865 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141866 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141867 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141868 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET), |
| 141869 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141870 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141871 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141872 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141873 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141874 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141875 | GIR_RootConstrainSelectedInstOperands, |
| 141876 | // GIR_Coverage, 5891, |
| 141877 | GIR_EraseRootFromParent_Done, |
| 141878 | // Label 6750: @457009 |
| 141879 | GIM_Try, /*On fail goto*//*Label 6751*/ GIMT_Encode4(457081), // Rule ID 5879 // |
| 141880 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141881 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 141882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141884 | // MIs[0] offset |
| 141885 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141886 | // MIs[0] auxiliary |
| 141887 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141888 | // MIs[0] Operand 8 |
| 141889 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141891 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFSET_RTN), |
| 141893 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141894 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141895 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141897 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141898 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141899 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141900 | GIR_RootConstrainSelectedInstOperands, |
| 141901 | // GIR_Coverage, 5879, |
| 141902 | GIR_EraseRootFromParent_Done, |
| 141903 | // Label 6751: @457081 |
| 141904 | GIM_Try, /*On fail goto*//*Label 6752*/ GIMT_Encode4(457150), // Rule ID 5887 // |
| 141905 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 141906 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141907 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 141908 | // MIs[0] offset |
| 141909 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141910 | // MIs[0] auxiliary |
| 141911 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141912 | // MIs[0] Operand 8 |
| 141913 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141915 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFSET_RTN), |
| 141917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141918 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141919 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141921 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141922 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141924 | GIR_RootConstrainSelectedInstOperands, |
| 141925 | // GIR_Coverage, 5887, |
| 141926 | GIR_EraseRootFromParent_Done, |
| 141927 | // Label 6752: @457150 |
| 141928 | GIM_Try, /*On fail goto*//*Label 6753*/ GIMT_Encode4(457216), // Rule ID 5885 // |
| 141929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141930 | GIM_CheckHasNoUse, /*MI*/0, |
| 141931 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141932 | // MIs[0] offset |
| 141933 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141934 | // MIs[0] auxiliary |
| 141935 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141936 | // MIs[0] Operand 8 |
| 141937 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141939 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN), |
| 141941 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141942 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141943 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141944 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141945 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141946 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141948 | GIR_RootConstrainSelectedInstOperands, |
| 141949 | // GIR_Coverage, 5885, |
| 141950 | GIR_EraseRootFromParent_Done, |
| 141951 | // Label 6753: @457216 |
| 141952 | GIM_Try, /*On fail goto*//*Label 6754*/ GIMT_Encode4(457279), // Rule ID 5893 // |
| 141953 | GIM_CheckHasNoUse, /*MI*/0, |
| 141954 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141955 | // MIs[0] offset |
| 141956 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141957 | // MIs[0] auxiliary |
| 141958 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141959 | // MIs[0] Operand 8 |
| 141960 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141962 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN), |
| 141964 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141965 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141966 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141967 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141968 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141969 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 141970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141971 | GIR_RootConstrainSelectedInstOperands, |
| 141972 | // GIR_Coverage, 5893, |
| 141973 | GIR_EraseRootFromParent_Done, |
| 141974 | // Label 6754: @457279 |
| 141975 | GIM_Try, /*On fail goto*//*Label 6755*/ GIMT_Encode4(457349), // Rule ID 5881 // |
| 141976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 141977 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 141978 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 141979 | // MIs[0] offset |
| 141980 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 141981 | // MIs[0] auxiliary |
| 141982 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 141983 | // MIs[0] Operand 8 |
| 141984 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 141985 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 141986 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 141987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_OFFEN_RTN), |
| 141988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 141989 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 141990 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 141991 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 141992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 141993 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 141994 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 141995 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 141996 | GIR_RootConstrainSelectedInstOperands, |
| 141997 | // GIR_Coverage, 5881, |
| 141998 | GIR_EraseRootFromParent_Done, |
| 141999 | // Label 6755: @457349 |
| 142000 | GIM_Try, /*On fail goto*//*Label 6756*/ GIMT_Encode4(457416), // Rule ID 5889 // |
| 142001 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142002 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142003 | // MIs[0] offset |
| 142004 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142005 | // MIs[0] auxiliary |
| 142006 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142007 | // MIs[0] Operand 8 |
| 142008 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142010 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_OFFEN_RTN), |
| 142012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142013 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142014 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142015 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142017 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142020 | GIR_RootConstrainSelectedInstOperands, |
| 142021 | // GIR_Coverage, 5889, |
| 142022 | GIR_EraseRootFromParent_Done, |
| 142023 | // Label 6756: @457416 |
| 142024 | GIM_Try, /*On fail goto*//*Label 6757*/ GIMT_Encode4(457474), // Rule ID 5884 // |
| 142025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 142026 | GIM_CheckHasNoUse, /*MI*/0, |
| 142027 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142028 | // MIs[0] offset |
| 142029 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142030 | // MIs[0] auxiliary |
| 142031 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142032 | // MIs[0] Operand 8 |
| 142033 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142034 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142035 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN), |
| 142037 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142038 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142039 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142041 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142044 | GIR_RootConstrainSelectedInstOperands, |
| 142045 | // GIR_Coverage, 5884, |
| 142046 | GIR_EraseRootFromParent_Done, |
| 142047 | // Label 6757: @457474 |
| 142048 | GIM_Try, /*On fail goto*//*Label 6758*/ GIMT_Encode4(457529), // Rule ID 5892 // |
| 142049 | GIM_CheckHasNoUse, /*MI*/0, |
| 142050 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142051 | // MIs[0] offset |
| 142052 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142053 | // MIs[0] auxiliary |
| 142054 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142055 | // MIs[0] Operand 8 |
| 142056 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142058 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN), |
| 142060 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142061 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142062 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142064 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142066 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142067 | GIR_RootConstrainSelectedInstOperands, |
| 142068 | // GIR_Coverage, 5892, |
| 142069 | GIR_EraseRootFromParent_Done, |
| 142070 | // Label 6758: @457529 |
| 142071 | GIM_Try, /*On fail goto*//*Label 6759*/ GIMT_Encode4(457591), // Rule ID 5880 // |
| 142072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 142073 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142074 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142075 | // MIs[0] offset |
| 142076 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142077 | // MIs[0] auxiliary |
| 142078 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142079 | // MIs[0] Operand 8 |
| 142080 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142082 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_IDXEN_RTN), |
| 142084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142085 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142086 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142087 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142089 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142090 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142091 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142092 | GIR_RootConstrainSelectedInstOperands, |
| 142093 | // GIR_Coverage, 5880, |
| 142094 | GIR_EraseRootFromParent_Done, |
| 142095 | // Label 6759: @457591 |
| 142096 | GIM_Try, /*On fail goto*//*Label 6760*/ GIMT_Encode4(457650), // Rule ID 5888 // |
| 142097 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142098 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142099 | // MIs[0] offset |
| 142100 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142101 | // MIs[0] auxiliary |
| 142102 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142103 | // MIs[0] Operand 8 |
| 142104 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142106 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142107 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_IDXEN_RTN), |
| 142108 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142109 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142110 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142111 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142113 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142114 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142115 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142116 | GIR_RootConstrainSelectedInstOperands, |
| 142117 | // GIR_Coverage, 5888, |
| 142118 | GIR_EraseRootFromParent_Done, |
| 142119 | // Label 6760: @457650 |
| 142120 | GIM_Try, /*On fail goto*//*Label 6761*/ GIMT_Encode4(457746), // Rule ID 5886 // |
| 142121 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 142122 | GIM_CheckHasNoUse, /*MI*/0, |
| 142123 | // MIs[0] offset |
| 142124 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142125 | // MIs[0] auxiliary |
| 142126 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142127 | // MIs[0] Operand 8 |
| 142128 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142130 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142131 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142132 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142133 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142135 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142136 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142137 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142138 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142139 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142140 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN), |
| 142142 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142143 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142144 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142146 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142148 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142149 | GIR_RootConstrainSelectedInstOperands, |
| 142150 | // GIR_Coverage, 5886, |
| 142151 | GIR_EraseRootFromParent_Done, |
| 142152 | // Label 6761: @457746 |
| 142153 | GIM_Try, /*On fail goto*//*Label 6762*/ GIMT_Encode4(457839), // Rule ID 5894 // |
| 142154 | GIM_CheckHasNoUse, /*MI*/0, |
| 142155 | // MIs[0] offset |
| 142156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142157 | // MIs[0] auxiliary |
| 142158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142159 | // MIs[0] Operand 8 |
| 142160 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142162 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_dec_noret>> => (BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142163 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142164 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142165 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142167 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142168 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142169 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142171 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN), |
| 142174 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142175 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142176 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142178 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142181 | GIR_RootConstrainSelectedInstOperands, |
| 142182 | // GIR_Coverage, 5894, |
| 142183 | GIR_EraseRootFromParent_Done, |
| 142184 | // Label 6762: @457839 |
| 142185 | GIM_Try, /*On fail goto*//*Label 6763*/ GIMT_Encode4(457939), // Rule ID 5882 // |
| 142186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 142187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142188 | // MIs[0] offset |
| 142189 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142190 | // MIs[0] auxiliary |
| 142191 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142192 | // MIs[0] Operand 8 |
| 142193 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142195 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142196 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142197 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142198 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142199 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142200 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142203 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142204 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_BOTHEN_RTN), |
| 142207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142208 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142209 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142210 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142212 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142215 | GIR_RootConstrainSelectedInstOperands, |
| 142216 | // GIR_Coverage, 5882, |
| 142217 | GIR_EraseRootFromParent_Done, |
| 142218 | // Label 6763: @457939 |
| 142219 | GIM_Try, /*On fail goto*//*Label 6764*/ GIMT_Encode4(458036), // Rule ID 5890 // |
| 142220 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142221 | // MIs[0] offset |
| 142222 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142223 | // MIs[0] auxiliary |
| 142224 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142225 | // MIs[0] Operand 8 |
| 142226 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142228 | // (SIbuffer_atomic_dec:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142229 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142230 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142231 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142232 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142233 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142235 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142236 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142237 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_DEC_X2_VBUFFER_BOTHEN_RTN), |
| 142240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142241 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142242 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142243 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142245 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142248 | GIR_RootConstrainSelectedInstOperands, |
| 142249 | // GIR_Coverage, 5890, |
| 142250 | GIR_EraseRootFromParent_Done, |
| 142251 | // Label 6764: @458036 |
| 142252 | GIM_Reject, |
| 142253 | // Label 6748: @458037 |
| 142254 | GIM_Reject, |
| 142255 | // Label 6730: @458038 |
| 142256 | GIM_Reject, |
| 142257 | // Label 113: @458039 |
| 142258 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(12), /*)*//*default:*//*Label 6768*/ GIMT_Encode4(462864), |
| 142259 | /*GILLT_s32*//*Label 6765*/ GIMT_Encode4(458062), |
| 142260 | /*GILLT_s64*//*Label 6766*/ GIMT_Encode4(459268), |
| 142261 | /*GILLT_v2s16*//*Label 6767*/ GIMT_Encode4(460474), |
| 142262 | // Label 6765: @458062 |
| 142263 | GIM_Try, /*On fail goto*//*Label 6769*/ GIMT_Encode4(459267), |
| 142264 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 142265 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 142266 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 142267 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 142268 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 142269 | GIM_Try, /*On fail goto*//*Label 6770*/ GIMT_Encode4(458150), // Rule ID 5991 // |
| 142270 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset), |
| 142271 | GIM_CheckHasNoUse, /*MI*/0, |
| 142272 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142273 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142274 | // MIs[0] offset |
| 142275 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142276 | // MIs[0] auxiliary |
| 142277 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142278 | // MIs[0] Operand 8 |
| 142279 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142281 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET), |
| 142283 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142284 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142286 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142287 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142289 | GIR_RootConstrainSelectedInstOperands, |
| 142290 | // GIR_Coverage, 5991, |
| 142291 | GIR_EraseRootFromParent_Done, |
| 142292 | // Label 6770: @458150 |
| 142293 | GIM_Try, /*On fail goto*//*Label 6771*/ GIMT_Encode4(458218), // Rule ID 5995 // |
| 142294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 142295 | GIM_CheckHasNoUse, /*MI*/0, |
| 142296 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142297 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142298 | // MIs[0] offset |
| 142299 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142300 | // MIs[0] auxiliary |
| 142301 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142302 | // MIs[0] Operand 8 |
| 142303 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142305 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET), |
| 142307 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142308 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142310 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142311 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142313 | GIR_RootConstrainSelectedInstOperands, |
| 142314 | // GIR_Coverage, 5995, |
| 142315 | GIR_EraseRootFromParent_Done, |
| 142316 | // Label 6771: @458218 |
| 142317 | GIM_Try, /*On fail goto*//*Label 6772*/ GIMT_Encode4(458290), // Rule ID 6007 // |
| 142318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset), |
| 142319 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142322 | // MIs[0] offset |
| 142323 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142324 | // MIs[0] auxiliary |
| 142325 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142326 | // MIs[0] Operand 8 |
| 142327 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142329 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F32_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFSET_RTN), |
| 142331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142332 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142333 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142335 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142336 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142338 | GIR_RootConstrainSelectedInstOperands, |
| 142339 | // GIR_Coverage, 6007, |
| 142340 | GIR_EraseRootFromParent_Done, |
| 142341 | // Label 6772: @458290 |
| 142342 | GIM_Try, /*On fail goto*//*Label 6773*/ GIMT_Encode4(458362), // Rule ID 6011 // |
| 142343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 142344 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142345 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142346 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142347 | // MIs[0] offset |
| 142348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142349 | // MIs[0] auxiliary |
| 142350 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142351 | // MIs[0] Operand 8 |
| 142352 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142354 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142355 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFSET_RTN), |
| 142356 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142357 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142358 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142360 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142361 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142362 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142363 | GIR_RootConstrainSelectedInstOperands, |
| 142364 | // GIR_Coverage, 6011, |
| 142365 | GIR_EraseRootFromParent_Done, |
| 142366 | // Label 6773: @458362 |
| 142367 | GIM_Try, /*On fail goto*//*Label 6774*/ GIMT_Encode4(458428), // Rule ID 5993 // |
| 142368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset), |
| 142369 | GIM_CheckHasNoUse, /*MI*/0, |
| 142370 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142371 | // MIs[0] offset |
| 142372 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142373 | // MIs[0] auxiliary |
| 142374 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142375 | // MIs[0] Operand 8 |
| 142376 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142378 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN), |
| 142380 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142381 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142382 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142383 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142384 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142385 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142387 | GIR_RootConstrainSelectedInstOperands, |
| 142388 | // GIR_Coverage, 5993, |
| 142389 | GIR_EraseRootFromParent_Done, |
| 142390 | // Label 6774: @458428 |
| 142391 | GIM_Try, /*On fail goto*//*Label 6775*/ GIMT_Encode4(458494), // Rule ID 5997 // |
| 142392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 142393 | GIM_CheckHasNoUse, /*MI*/0, |
| 142394 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142395 | // MIs[0] offset |
| 142396 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142397 | // MIs[0] auxiliary |
| 142398 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142399 | // MIs[0] Operand 8 |
| 142400 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142401 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142402 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142403 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN), |
| 142404 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142405 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142406 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142407 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142408 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142409 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142410 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142411 | GIR_RootConstrainSelectedInstOperands, |
| 142412 | // GIR_Coverage, 5997, |
| 142413 | GIR_EraseRootFromParent_Done, |
| 142414 | // Label 6775: @458494 |
| 142415 | GIM_Try, /*On fail goto*//*Label 6776*/ GIMT_Encode4(458564), // Rule ID 6009 // |
| 142416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset), |
| 142417 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142418 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142419 | // MIs[0] offset |
| 142420 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142421 | // MIs[0] auxiliary |
| 142422 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142423 | // MIs[0] Operand 8 |
| 142424 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142426 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F32_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_OFFEN_RTN), |
| 142428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142429 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142430 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142431 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142433 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142434 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142435 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142436 | GIR_RootConstrainSelectedInstOperands, |
| 142437 | // GIR_Coverage, 6009, |
| 142438 | GIR_EraseRootFromParent_Done, |
| 142439 | // Label 6776: @458564 |
| 142440 | GIM_Try, /*On fail goto*//*Label 6777*/ GIMT_Encode4(458634), // Rule ID 6013 // |
| 142441 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 142442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142443 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142444 | // MIs[0] offset |
| 142445 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142446 | // MIs[0] auxiliary |
| 142447 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142448 | // MIs[0] Operand 8 |
| 142449 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142450 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142451 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142452 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_OFFEN_RTN), |
| 142453 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142454 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142455 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142456 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142458 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142459 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142460 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142461 | GIR_RootConstrainSelectedInstOperands, |
| 142462 | // GIR_Coverage, 6013, |
| 142463 | GIR_EraseRootFromParent_Done, |
| 142464 | // Label 6777: @458634 |
| 142465 | GIM_Try, /*On fail goto*//*Label 6778*/ GIMT_Encode4(458692), // Rule ID 5992 // |
| 142466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset), |
| 142467 | GIM_CheckHasNoUse, /*MI*/0, |
| 142468 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142469 | // MIs[0] offset |
| 142470 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142471 | // MIs[0] auxiliary |
| 142472 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142473 | // MIs[0] Operand 8 |
| 142474 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142476 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN), |
| 142478 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142479 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142480 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142482 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142483 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142485 | GIR_RootConstrainSelectedInstOperands, |
| 142486 | // GIR_Coverage, 5992, |
| 142487 | GIR_EraseRootFromParent_Done, |
| 142488 | // Label 6778: @458692 |
| 142489 | GIM_Try, /*On fail goto*//*Label 6779*/ GIMT_Encode4(458750), // Rule ID 5996 // |
| 142490 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 142491 | GIM_CheckHasNoUse, /*MI*/0, |
| 142492 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142493 | // MIs[0] offset |
| 142494 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142495 | // MIs[0] auxiliary |
| 142496 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142497 | // MIs[0] Operand 8 |
| 142498 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142499 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142500 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142501 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN), |
| 142502 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142503 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142504 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142505 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142506 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142507 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142508 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142509 | GIR_RootConstrainSelectedInstOperands, |
| 142510 | // GIR_Coverage, 5996, |
| 142511 | GIR_EraseRootFromParent_Done, |
| 142512 | // Label 6779: @458750 |
| 142513 | GIM_Try, /*On fail goto*//*Label 6780*/ GIMT_Encode4(458812), // Rule ID 6008 // |
| 142514 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset), |
| 142515 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142516 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142517 | // MIs[0] offset |
| 142518 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142519 | // MIs[0] auxiliary |
| 142520 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142521 | // MIs[0] Operand 8 |
| 142522 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142523 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142524 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F32_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142525 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_IDXEN_RTN), |
| 142526 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142527 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142528 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142529 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142531 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142532 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142533 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142534 | GIR_RootConstrainSelectedInstOperands, |
| 142535 | // GIR_Coverage, 6008, |
| 142536 | GIR_EraseRootFromParent_Done, |
| 142537 | // Label 6780: @458812 |
| 142538 | GIM_Try, /*On fail goto*//*Label 6781*/ GIMT_Encode4(458874), // Rule ID 6012 // |
| 142539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 142540 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142541 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142542 | // MIs[0] offset |
| 142543 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142544 | // MIs[0] auxiliary |
| 142545 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142546 | // MIs[0] Operand 8 |
| 142547 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142549 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_IDXEN_RTN), |
| 142551 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142552 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142553 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142554 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142556 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142557 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142558 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142559 | GIR_RootConstrainSelectedInstOperands, |
| 142560 | // GIR_Coverage, 6012, |
| 142561 | GIR_EraseRootFromParent_Done, |
| 142562 | // Label 6781: @458874 |
| 142563 | GIM_Try, /*On fail goto*//*Label 6782*/ GIMT_Encode4(458970), // Rule ID 5994 // |
| 142564 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts_HasUnrestrictedSOffset), |
| 142565 | GIM_CheckHasNoUse, /*MI*/0, |
| 142566 | // MIs[0] offset |
| 142567 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142568 | // MIs[0] auxiliary |
| 142569 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142570 | // MIs[0] Operand 8 |
| 142571 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142572 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142573 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142574 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142577 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142578 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142579 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142580 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142582 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142583 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN), |
| 142585 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142587 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142589 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142592 | GIR_RootConstrainSelectedInstOperands, |
| 142593 | // GIR_Coverage, 5994, |
| 142594 | GIR_EraseRootFromParent_Done, |
| 142595 | // Label 6782: @458970 |
| 142596 | GIM_Try, /*On fail goto*//*Label 6783*/ GIMT_Encode4(459066), // Rule ID 5998 // |
| 142597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddNoRtnInsts), |
| 142598 | GIM_CheckHasNoUse, /*MI*/0, |
| 142599 | // MIs[0] offset |
| 142600 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142601 | // MIs[0] auxiliary |
| 142602 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142603 | // MIs[0] Operand 8 |
| 142604 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142606 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142607 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142610 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142611 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142612 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142613 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142614 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142616 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN), |
| 142618 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142620 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142622 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142623 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142625 | GIR_RootConstrainSelectedInstOperands, |
| 142626 | // GIR_Coverage, 5998, |
| 142627 | GIR_EraseRootFromParent_Done, |
| 142628 | // Label 6783: @459066 |
| 142629 | GIM_Try, /*On fail goto*//*Label 6784*/ GIMT_Encode4(459166), // Rule ID 6010 // |
| 142630 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts_HasUnrestrictedSOffset), |
| 142631 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142632 | // MIs[0] offset |
| 142633 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142634 | // MIs[0] auxiliary |
| 142635 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142636 | // MIs[0] Operand 8 |
| 142637 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142639 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142643 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142644 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142645 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142646 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142647 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142648 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142649 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_BOTHEN_RTN), |
| 142651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142652 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142654 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142656 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142659 | GIR_RootConstrainSelectedInstOperands, |
| 142660 | // GIR_Coverage, 6010, |
| 142661 | GIR_EraseRootFromParent_Done, |
| 142662 | // Label 6784: @459166 |
| 142663 | GIM_Try, /*On fail goto*//*Label 6785*/ GIMT_Encode4(459266), // Rule ID 6014 // |
| 142664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFaddRtnInsts), |
| 142665 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 142666 | // MIs[0] offset |
| 142667 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142668 | // MIs[0] auxiliary |
| 142669 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142670 | // MIs[0] Operand 8 |
| 142671 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142673 | // (SIbuffer_atomic_fadd:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 142675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 142676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 142677 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 142678 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 142679 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 142680 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 142681 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 142682 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142683 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 142684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F32_VBUFFER_BOTHEN_RTN), |
| 142685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142686 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 142688 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142690 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142691 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142692 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142693 | GIR_RootConstrainSelectedInstOperands, |
| 142694 | // GIR_Coverage, 6014, |
| 142695 | GIR_EraseRootFromParent_Done, |
| 142696 | // Label 6785: @459266 |
| 142697 | GIM_Reject, |
| 142698 | // Label 6769: @459267 |
| 142699 | GIM_Reject, |
| 142700 | // Label 6766: @459268 |
| 142701 | GIM_Try, /*On fail goto*//*Label 6786*/ GIMT_Encode4(460473), |
| 142702 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 142703 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 142704 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 142705 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 142706 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 142707 | GIM_Try, /*On fail goto*//*Label 6787*/ GIMT_Encode4(459356), // Rule ID 6027 // |
| 142708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142709 | GIM_CheckHasNoUse, /*MI*/0, |
| 142710 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142712 | // MIs[0] offset |
| 142713 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142714 | // MIs[0] auxiliary |
| 142715 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142716 | // MIs[0] Operand 8 |
| 142717 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142719 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET), |
| 142721 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142722 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142724 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142725 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142726 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142727 | GIR_RootConstrainSelectedInstOperands, |
| 142728 | // GIR_Coverage, 6027, |
| 142729 | GIR_EraseRootFromParent_Done, |
| 142730 | // Label 6787: @459356 |
| 142731 | GIM_Try, /*On fail goto*//*Label 6788*/ GIMT_Encode4(459424), // Rule ID 6035 // |
| 142732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142733 | GIM_CheckHasNoUse, /*MI*/0, |
| 142734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142735 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142736 | // MIs[0] offset |
| 142737 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142738 | // MIs[0] auxiliary |
| 142739 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142740 | // MIs[0] Operand 8 |
| 142741 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142742 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142743 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET), |
| 142745 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142746 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142748 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142751 | GIR_RootConstrainSelectedInstOperands, |
| 142752 | // GIR_Coverage, 6035, |
| 142753 | GIR_EraseRootFromParent_Done, |
| 142754 | // Label 6788: @459424 |
| 142755 | GIM_Try, /*On fail goto*//*Label 6789*/ GIMT_Encode4(459496), // Rule ID 6023 // |
| 142756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142758 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142759 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142760 | // MIs[0] offset |
| 142761 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142762 | // MIs[0] auxiliary |
| 142763 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142764 | // MIs[0] Operand 8 |
| 142765 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142767 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFSET_RTN), |
| 142769 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142770 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142771 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142773 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142776 | GIR_RootConstrainSelectedInstOperands, |
| 142777 | // GIR_Coverage, 6023, |
| 142778 | GIR_EraseRootFromParent_Done, |
| 142779 | // Label 6789: @459496 |
| 142780 | GIM_Try, /*On fail goto*//*Label 6790*/ GIMT_Encode4(459568), // Rule ID 6031 // |
| 142781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142784 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142785 | // MIs[0] offset |
| 142786 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142787 | // MIs[0] auxiliary |
| 142788 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142789 | // MIs[0] Operand 8 |
| 142790 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142792 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFSET_RTN), |
| 142794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142795 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142796 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142798 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142799 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142801 | GIR_RootConstrainSelectedInstOperands, |
| 142802 | // GIR_Coverage, 6031, |
| 142803 | GIR_EraseRootFromParent_Done, |
| 142804 | // Label 6790: @459568 |
| 142805 | GIM_Try, /*On fail goto*//*Label 6791*/ GIMT_Encode4(459634), // Rule ID 6029 // |
| 142806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142807 | GIM_CheckHasNoUse, /*MI*/0, |
| 142808 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142809 | // MIs[0] offset |
| 142810 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142811 | // MIs[0] auxiliary |
| 142812 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142813 | // MIs[0] Operand 8 |
| 142814 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142815 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142816 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN), |
| 142818 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142819 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142820 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142822 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142823 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142825 | GIR_RootConstrainSelectedInstOperands, |
| 142826 | // GIR_Coverage, 6029, |
| 142827 | GIR_EraseRootFromParent_Done, |
| 142828 | // Label 6791: @459634 |
| 142829 | GIM_Try, /*On fail goto*//*Label 6792*/ GIMT_Encode4(459700), // Rule ID 6037 // |
| 142830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142831 | GIM_CheckHasNoUse, /*MI*/0, |
| 142832 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142833 | // MIs[0] offset |
| 142834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142835 | // MIs[0] auxiliary |
| 142836 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142837 | // MIs[0] Operand 8 |
| 142838 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142840 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN), |
| 142842 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142843 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142844 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142846 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142847 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142849 | GIR_RootConstrainSelectedInstOperands, |
| 142850 | // GIR_Coverage, 6037, |
| 142851 | GIR_EraseRootFromParent_Done, |
| 142852 | // Label 6792: @459700 |
| 142853 | GIM_Try, /*On fail goto*//*Label 6793*/ GIMT_Encode4(459770), // Rule ID 6025 // |
| 142854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142855 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142856 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142857 | // MIs[0] offset |
| 142858 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142859 | // MIs[0] auxiliary |
| 142860 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142861 | // MIs[0] Operand 8 |
| 142862 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142863 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142864 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F64_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142865 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_OFFEN_RTN), |
| 142866 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142867 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142868 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142869 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142871 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142872 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142873 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142874 | GIR_RootConstrainSelectedInstOperands, |
| 142875 | // GIR_Coverage, 6025, |
| 142876 | GIR_EraseRootFromParent_Done, |
| 142877 | // Label 6793: @459770 |
| 142878 | GIM_Try, /*On fail goto*//*Label 6794*/ GIMT_Encode4(459840), // Rule ID 6033 // |
| 142879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142880 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142881 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 142882 | // MIs[0] offset |
| 142883 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142884 | // MIs[0] auxiliary |
| 142885 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142886 | // MIs[0] Operand 8 |
| 142887 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 142888 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142889 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_OFFEN_RTN), |
| 142891 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142892 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142893 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 142894 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142895 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142896 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142897 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142898 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142899 | GIR_RootConstrainSelectedInstOperands, |
| 142900 | // GIR_Coverage, 6033, |
| 142901 | GIR_EraseRootFromParent_Done, |
| 142902 | // Label 6794: @459840 |
| 142903 | GIM_Try, /*On fail goto*//*Label 6795*/ GIMT_Encode4(459898), // Rule ID 6028 // |
| 142904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142905 | GIM_CheckHasNoUse, /*MI*/0, |
| 142906 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142907 | // MIs[0] offset |
| 142908 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142909 | // MIs[0] auxiliary |
| 142910 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142911 | // MIs[0] Operand 8 |
| 142912 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142914 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN), |
| 142916 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142917 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142918 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142920 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142921 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142923 | GIR_RootConstrainSelectedInstOperands, |
| 142924 | // GIR_Coverage, 6028, |
| 142925 | GIR_EraseRootFromParent_Done, |
| 142926 | // Label 6795: @459898 |
| 142927 | GIM_Try, /*On fail goto*//*Label 6796*/ GIMT_Encode4(459956), // Rule ID 6036 // |
| 142928 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142929 | GIM_CheckHasNoUse, /*MI*/0, |
| 142930 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142931 | // MIs[0] offset |
| 142932 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142933 | // MIs[0] auxiliary |
| 142934 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142935 | // MIs[0] Operand 8 |
| 142936 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142937 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142938 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN), |
| 142940 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142941 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142942 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142944 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142945 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 142946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142947 | GIR_RootConstrainSelectedInstOperands, |
| 142948 | // GIR_Coverage, 6036, |
| 142949 | GIR_EraseRootFromParent_Done, |
| 142950 | // Label 6796: @459956 |
| 142951 | GIM_Try, /*On fail goto*//*Label 6797*/ GIMT_Encode4(460018), // Rule ID 6024 // |
| 142952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 142953 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142954 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142955 | // MIs[0] offset |
| 142956 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142957 | // MIs[0] auxiliary |
| 142958 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142959 | // MIs[0] Operand 8 |
| 142960 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142962 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F64_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_IDXEN_RTN), |
| 142964 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142965 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142966 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142967 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142969 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142970 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142971 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142972 | GIR_RootConstrainSelectedInstOperands, |
| 142973 | // GIR_Coverage, 6024, |
| 142974 | GIR_EraseRootFromParent_Done, |
| 142975 | // Label 6797: @460018 |
| 142976 | GIM_Try, /*On fail goto*//*Label 6798*/ GIMT_Encode4(460080), // Rule ID 6032 // |
| 142977 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 142978 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 142979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 142980 | // MIs[0] offset |
| 142981 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 142982 | // MIs[0] auxiliary |
| 142983 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 142984 | // MIs[0] Operand 8 |
| 142985 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 142986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 142987 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 142988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_IDXEN_RTN), |
| 142989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 142990 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 142991 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 142992 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 142993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 142994 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 142995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 142996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 142997 | GIR_RootConstrainSelectedInstOperands, |
| 142998 | // GIR_Coverage, 6032, |
| 142999 | GIR_EraseRootFromParent_Done, |
| 143000 | // Label 6798: @460080 |
| 143001 | GIM_Try, /*On fail goto*//*Label 6799*/ GIMT_Encode4(460176), // Rule ID 6030 // |
| 143002 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 143003 | GIM_CheckHasNoUse, /*MI*/0, |
| 143004 | // MIs[0] offset |
| 143005 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143006 | // MIs[0] auxiliary |
| 143007 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143008 | // MIs[0] Operand 8 |
| 143009 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143011 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143012 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143013 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143014 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143015 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143016 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143017 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143018 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143019 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143020 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143021 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143022 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN), |
| 143023 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143024 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143025 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143026 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143027 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143028 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143030 | GIR_RootConstrainSelectedInstOperands, |
| 143031 | // GIR_Coverage, 6030, |
| 143032 | GIR_EraseRootFromParent_Done, |
| 143033 | // Label 6799: @460176 |
| 143034 | GIM_Try, /*On fail goto*//*Label 6800*/ GIMT_Encode4(460272), // Rule ID 6038 // |
| 143035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 143036 | GIM_CheckHasNoUse, /*MI*/0, |
| 143037 | // MIs[0] offset |
| 143038 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143039 | // MIs[0] auxiliary |
| 143040 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143041 | // MIs[0] Operand 8 |
| 143042 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143044 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143045 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143046 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143047 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143048 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143049 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143050 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143051 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143052 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143053 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN), |
| 143056 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143057 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143058 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143060 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143061 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143062 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143063 | GIR_RootConstrainSelectedInstOperands, |
| 143064 | // GIR_Coverage, 6038, |
| 143065 | GIR_EraseRootFromParent_Done, |
| 143066 | // Label 6800: @460272 |
| 143067 | GIM_Try, /*On fail goto*//*Label 6801*/ GIMT_Encode4(460372), // Rule ID 6026 // |
| 143068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst_HasUnrestrictedSOffset), |
| 143069 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 143070 | // MIs[0] offset |
| 143071 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143072 | // MIs[0] auxiliary |
| 143073 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143074 | // MIs[0] Operand 8 |
| 143075 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143077 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143078 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143079 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143080 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143081 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143082 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143083 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143084 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143085 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143086 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143087 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_BOTHEN_RTN), |
| 143089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143090 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143091 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143092 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143094 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143095 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143097 | GIR_RootConstrainSelectedInstOperands, |
| 143098 | // GIR_Coverage, 6026, |
| 143099 | GIR_EraseRootFromParent_Done, |
| 143100 | // Label 6801: @460372 |
| 143101 | GIM_Try, /*On fail goto*//*Label 6802*/ GIMT_Encode4(460472), // Rule ID 6034 // |
| 143102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFlatBufferGlobalAtomicFaddF64Inst), |
| 143103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 143104 | // MIs[0] offset |
| 143105 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143106 | // MIs[0] auxiliary |
| 143107 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143108 | // MIs[0] Operand 8 |
| 143109 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143111 | // (SIbuffer_atomic_fadd:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143112 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143113 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143114 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143115 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143116 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143117 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143118 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143119 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143120 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143121 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_ADD_F64_VBUFFER_BOTHEN_RTN), |
| 143123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143124 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143126 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143128 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143129 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143131 | GIR_RootConstrainSelectedInstOperands, |
| 143132 | // GIR_Coverage, 6034, |
| 143133 | GIR_EraseRootFromParent_Done, |
| 143134 | // Label 6802: @460472 |
| 143135 | GIM_Reject, |
| 143136 | // Label 6786: @460473 |
| 143137 | GIM_Reject, |
| 143138 | // Label 6767: @460474 |
| 143139 | GIM_Try, /*On fail goto*//*Label 6803*/ GIMT_Encode4(462863), |
| 143140 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 143141 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 143142 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 143143 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 143144 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 143145 | GIM_Try, /*On fail goto*//*Label 6804*/ GIMT_Encode4(460562), // Rule ID 5907 // |
| 143146 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143147 | GIM_CheckHasNoUse, /*MI*/0, |
| 143148 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143149 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143150 | // MIs[0] offset |
| 143151 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143152 | // MIs[0] auxiliary |
| 143153 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143154 | // MIs[0] Operand 8 |
| 143155 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143156 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143157 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_OFFSET anonymous_15876:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET), |
| 143159 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143160 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143162 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143163 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143165 | GIR_RootConstrainSelectedInstOperands, |
| 143166 | // GIR_Coverage, 5907, |
| 143167 | GIR_EraseRootFromParent_Done, |
| 143168 | // Label 6804: @460562 |
| 143169 | GIM_Try, /*On fail goto*//*Label 6805*/ GIMT_Encode4(460630), // Rule ID 5915 // |
| 143170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143171 | GIM_CheckHasNoUse, /*MI*/0, |
| 143172 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143173 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143174 | // MIs[0] offset |
| 143175 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143176 | // MIs[0] auxiliary |
| 143177 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143178 | // MIs[0] Operand 8 |
| 143179 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143181 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET anonymous_15876:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET), |
| 143183 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143184 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143185 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143186 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143187 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143188 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143189 | GIR_RootConstrainSelectedInstOperands, |
| 143190 | // GIR_Coverage, 5915, |
| 143191 | GIR_EraseRootFromParent_Done, |
| 143192 | // Label 6805: @460630 |
| 143193 | GIM_Try, /*On fail goto*//*Label 6806*/ GIMT_Encode4(460698), // Rule ID 5999 // |
| 143194 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset), |
| 143195 | GIM_CheckHasNoUse, /*MI*/0, |
| 143196 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143197 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143198 | // MIs[0] offset |
| 143199 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143200 | // MIs[0] auxiliary |
| 143201 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143202 | // MIs[0] Operand 8 |
| 143203 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143204 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143205 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_OFFSET anonymous_15876:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET), |
| 143207 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143208 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143210 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143211 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143212 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143213 | GIR_RootConstrainSelectedInstOperands, |
| 143214 | // GIR_Coverage, 5999, |
| 143215 | GIR_EraseRootFromParent_Done, |
| 143216 | // Label 6806: @460698 |
| 143217 | GIM_Try, /*On fail goto*//*Label 6807*/ GIMT_Encode4(460766), // Rule ID 6003 // |
| 143218 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 143219 | GIM_CheckHasNoUse, /*MI*/0, |
| 143220 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143221 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143222 | // MIs[0] offset |
| 143223 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143224 | // MIs[0] auxiliary |
| 143225 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143226 | // MIs[0] Operand 8 |
| 143227 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143229 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET anonymous_15876:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET), |
| 143231 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143232 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143234 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143235 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143236 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143237 | GIR_RootConstrainSelectedInstOperands, |
| 143238 | // GIR_Coverage, 6003, |
| 143239 | GIR_EraseRootFromParent_Done, |
| 143240 | // Label 6807: @460766 |
| 143241 | GIM_Try, /*On fail goto*//*Label 6808*/ GIMT_Encode4(460838), // Rule ID 5903 // |
| 143242 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143243 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143244 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143245 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143246 | // MIs[0] offset |
| 143247 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143248 | // MIs[0] auxiliary |
| 143249 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143250 | // MIs[0] Operand 8 |
| 143251 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143253 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFSET_RTN), |
| 143255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143256 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143257 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143259 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143260 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143261 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143262 | GIR_RootConstrainSelectedInstOperands, |
| 143263 | // GIR_Coverage, 5903, |
| 143264 | GIR_EraseRootFromParent_Done, |
| 143265 | // Label 6808: @460838 |
| 143266 | GIM_Try, /*On fail goto*//*Label 6809*/ GIMT_Encode4(460910), // Rule ID 5911 // |
| 143267 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143268 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143269 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143270 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143271 | // MIs[0] offset |
| 143272 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143273 | // MIs[0] auxiliary |
| 143274 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143275 | // MIs[0] Operand 8 |
| 143276 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143278 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFSET_RTN), |
| 143280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143281 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143282 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143284 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143285 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143286 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143287 | GIR_RootConstrainSelectedInstOperands, |
| 143288 | // GIR_Coverage, 5911, |
| 143289 | GIR_EraseRootFromParent_Done, |
| 143290 | // Label 6809: @460910 |
| 143291 | GIM_Try, /*On fail goto*//*Label 6810*/ GIMT_Encode4(460982), // Rule ID 6015 // |
| 143292 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset), |
| 143293 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143294 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143295 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143296 | // MIs[0] offset |
| 143297 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143298 | // MIs[0] auxiliary |
| 143299 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143300 | // MIs[0] Operand 8 |
| 143301 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143302 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143303 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFSET_RTN), |
| 143305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143306 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143307 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143309 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143310 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143311 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143312 | GIR_RootConstrainSelectedInstOperands, |
| 143313 | // GIR_Coverage, 6015, |
| 143314 | GIR_EraseRootFromParent_Done, |
| 143315 | // Label 6810: @460982 |
| 143316 | GIM_Try, /*On fail goto*//*Label 6811*/ GIMT_Encode4(461054), // Rule ID 6019 // |
| 143317 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 143318 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143319 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143321 | // MIs[0] offset |
| 143322 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143323 | // MIs[0] auxiliary |
| 143324 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143325 | // MIs[0] Operand 8 |
| 143326 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143328 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFSET_RTN), |
| 143330 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143331 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143332 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143334 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143335 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143336 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143337 | GIR_RootConstrainSelectedInstOperands, |
| 143338 | // GIR_Coverage, 6019, |
| 143339 | GIR_EraseRootFromParent_Done, |
| 143340 | // Label 6811: @461054 |
| 143341 | GIM_Try, /*On fail goto*//*Label 6812*/ GIMT_Encode4(461120), // Rule ID 5909 // |
| 143342 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143343 | GIM_CheckHasNoUse, /*MI*/0, |
| 143344 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143345 | // MIs[0] offset |
| 143346 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143347 | // MIs[0] auxiliary |
| 143348 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143349 | // MIs[0] Operand 8 |
| 143350 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143352 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_OFFEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN), |
| 143354 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143355 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143356 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143358 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143360 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143361 | GIR_RootConstrainSelectedInstOperands, |
| 143362 | // GIR_Coverage, 5909, |
| 143363 | GIR_EraseRootFromParent_Done, |
| 143364 | // Label 6812: @461120 |
| 143365 | GIM_Try, /*On fail goto*//*Label 6813*/ GIMT_Encode4(461186), // Rule ID 5917 // |
| 143366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143367 | GIM_CheckHasNoUse, /*MI*/0, |
| 143368 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143369 | // MIs[0] offset |
| 143370 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143371 | // MIs[0] auxiliary |
| 143372 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143373 | // MIs[0] Operand 8 |
| 143374 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143375 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143376 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN), |
| 143378 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143379 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143380 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143382 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143385 | GIR_RootConstrainSelectedInstOperands, |
| 143386 | // GIR_Coverage, 5917, |
| 143387 | GIR_EraseRootFromParent_Done, |
| 143388 | // Label 6813: @461186 |
| 143389 | GIM_Try, /*On fail goto*//*Label 6814*/ GIMT_Encode4(461252), // Rule ID 6001 // |
| 143390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset), |
| 143391 | GIM_CheckHasNoUse, /*MI*/0, |
| 143392 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143393 | // MIs[0] offset |
| 143394 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143395 | // MIs[0] auxiliary |
| 143396 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143397 | // MIs[0] Operand 8 |
| 143398 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143399 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143400 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_OFFEN anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143401 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN), |
| 143402 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143403 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143404 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143406 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143407 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143409 | GIR_RootConstrainSelectedInstOperands, |
| 143410 | // GIR_Coverage, 6001, |
| 143411 | GIR_EraseRootFromParent_Done, |
| 143412 | // Label 6814: @461252 |
| 143413 | GIM_Try, /*On fail goto*//*Label 6815*/ GIMT_Encode4(461318), // Rule ID 6005 // |
| 143414 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 143415 | GIM_CheckHasNoUse, /*MI*/0, |
| 143416 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143417 | // MIs[0] offset |
| 143418 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143419 | // MIs[0] auxiliary |
| 143420 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143421 | // MIs[0] Operand 8 |
| 143422 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143424 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN), |
| 143426 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143427 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143428 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143430 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143433 | GIR_RootConstrainSelectedInstOperands, |
| 143434 | // GIR_Coverage, 6005, |
| 143435 | GIR_EraseRootFromParent_Done, |
| 143436 | // Label 6815: @461318 |
| 143437 | GIM_Try, /*On fail goto*//*Label 6816*/ GIMT_Encode4(461388), // Rule ID 5905 // |
| 143438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143439 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143441 | // MIs[0] offset |
| 143442 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143443 | // MIs[0] auxiliary |
| 143444 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143445 | // MIs[0] Operand 8 |
| 143446 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143448 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_OFFEN_RTN), |
| 143450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143451 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143452 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143453 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143455 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143456 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143458 | GIR_RootConstrainSelectedInstOperands, |
| 143459 | // GIR_Coverage, 5905, |
| 143460 | GIR_EraseRootFromParent_Done, |
| 143461 | // Label 6816: @461388 |
| 143462 | GIM_Try, /*On fail goto*//*Label 6817*/ GIMT_Encode4(461458), // Rule ID 5913 // |
| 143463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143466 | // MIs[0] offset |
| 143467 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143468 | // MIs[0] auxiliary |
| 143469 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143470 | // MIs[0] Operand 8 |
| 143471 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143473 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_OFFEN_RTN), |
| 143475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143476 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143477 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143478 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143480 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143481 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143483 | GIR_RootConstrainSelectedInstOperands, |
| 143484 | // GIR_Coverage, 5913, |
| 143485 | GIR_EraseRootFromParent_Done, |
| 143486 | // Label 6817: @461458 |
| 143487 | GIM_Try, /*On fail goto*//*Label 6818*/ GIMT_Encode4(461528), // Rule ID 6017 // |
| 143488 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset), |
| 143489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143490 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143491 | // MIs[0] offset |
| 143492 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143493 | // MIs[0] auxiliary |
| 143494 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143495 | // MIs[0] Operand 8 |
| 143496 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143498 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_OFFEN_RTN), |
| 143500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143501 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143502 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143503 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143505 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143506 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143508 | GIR_RootConstrainSelectedInstOperands, |
| 143509 | // GIR_Coverage, 6017, |
| 143510 | GIR_EraseRootFromParent_Done, |
| 143511 | // Label 6818: @461528 |
| 143512 | GIM_Try, /*On fail goto*//*Label 6819*/ GIMT_Encode4(461598), // Rule ID 6021 // |
| 143513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 143514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143515 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 143516 | // MIs[0] offset |
| 143517 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143518 | // MIs[0] auxiliary |
| 143519 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143520 | // MIs[0] Operand 8 |
| 143521 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 143522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143523 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_OFFEN_RTN), |
| 143525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143526 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143527 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 143528 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143530 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143531 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143532 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143533 | GIR_RootConstrainSelectedInstOperands, |
| 143534 | // GIR_Coverage, 6021, |
| 143535 | GIR_EraseRootFromParent_Done, |
| 143536 | // Label 6819: @461598 |
| 143537 | GIM_Try, /*On fail goto*//*Label 6820*/ GIMT_Encode4(461656), // Rule ID 5908 // |
| 143538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143539 | GIM_CheckHasNoUse, /*MI*/0, |
| 143540 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143541 | // MIs[0] offset |
| 143542 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143543 | // MIs[0] auxiliary |
| 143544 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143545 | // MIs[0] Operand 8 |
| 143546 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143547 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143548 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_IDXEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN), |
| 143550 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143551 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143552 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143554 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143555 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143557 | GIR_RootConstrainSelectedInstOperands, |
| 143558 | // GIR_Coverage, 5908, |
| 143559 | GIR_EraseRootFromParent_Done, |
| 143560 | // Label 6820: @461656 |
| 143561 | GIM_Try, /*On fail goto*//*Label 6821*/ GIMT_Encode4(461714), // Rule ID 5916 // |
| 143562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143563 | GIM_CheckHasNoUse, /*MI*/0, |
| 143564 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143565 | // MIs[0] offset |
| 143566 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143567 | // MIs[0] auxiliary |
| 143568 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143569 | // MIs[0] Operand 8 |
| 143570 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143572 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN), |
| 143574 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143575 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143576 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143578 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143579 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143580 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143581 | GIR_RootConstrainSelectedInstOperands, |
| 143582 | // GIR_Coverage, 5916, |
| 143583 | GIR_EraseRootFromParent_Done, |
| 143584 | // Label 6821: @461714 |
| 143585 | GIM_Try, /*On fail goto*//*Label 6822*/ GIMT_Encode4(461772), // Rule ID 6000 // |
| 143586 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset), |
| 143587 | GIM_CheckHasNoUse, /*MI*/0, |
| 143588 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143589 | // MIs[0] offset |
| 143590 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143591 | // MIs[0] auxiliary |
| 143592 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143593 | // MIs[0] Operand 8 |
| 143594 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143596 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_IDXEN anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN), |
| 143598 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143599 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143600 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143602 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143603 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143605 | GIR_RootConstrainSelectedInstOperands, |
| 143606 | // GIR_Coverage, 6000, |
| 143607 | GIR_EraseRootFromParent_Done, |
| 143608 | // Label 6822: @461772 |
| 143609 | GIM_Try, /*On fail goto*//*Label 6823*/ GIMT_Encode4(461830), // Rule ID 6004 // |
| 143610 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 143611 | GIM_CheckHasNoUse, /*MI*/0, |
| 143612 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143613 | // MIs[0] offset |
| 143614 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143615 | // MIs[0] auxiliary |
| 143616 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143617 | // MIs[0] Operand 8 |
| 143618 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143619 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143620 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143621 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN), |
| 143622 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143623 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143624 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143626 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143627 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143629 | GIR_RootConstrainSelectedInstOperands, |
| 143630 | // GIR_Coverage, 6004, |
| 143631 | GIR_EraseRootFromParent_Done, |
| 143632 | // Label 6823: @461830 |
| 143633 | GIM_Try, /*On fail goto*//*Label 6824*/ GIMT_Encode4(461892), // Rule ID 5904 // |
| 143634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143635 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143636 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143637 | // MIs[0] offset |
| 143638 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143639 | // MIs[0] auxiliary |
| 143640 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143641 | // MIs[0] Operand 8 |
| 143642 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143643 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143644 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_IDXEN_RTN), |
| 143646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143647 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143648 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143649 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143650 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143651 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143652 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143653 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143654 | GIR_RootConstrainSelectedInstOperands, |
| 143655 | // GIR_Coverage, 5904, |
| 143656 | GIR_EraseRootFromParent_Done, |
| 143657 | // Label 6824: @461892 |
| 143658 | GIM_Try, /*On fail goto*//*Label 6825*/ GIMT_Encode4(461954), // Rule ID 5912 // |
| 143659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143660 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143661 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143662 | // MIs[0] offset |
| 143663 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143664 | // MIs[0] auxiliary |
| 143665 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143666 | // MIs[0] Operand 8 |
| 143667 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143669 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143670 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_IDXEN_RTN), |
| 143671 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143672 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143673 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143674 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143676 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143677 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143678 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143679 | GIR_RootConstrainSelectedInstOperands, |
| 143680 | // GIR_Coverage, 5912, |
| 143681 | GIR_EraseRootFromParent_Done, |
| 143682 | // Label 6825: @461954 |
| 143683 | GIM_Try, /*On fail goto*//*Label 6826*/ GIMT_Encode4(462016), // Rule ID 6016 // |
| 143684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset), |
| 143685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143686 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143687 | // MIs[0] offset |
| 143688 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143689 | // MIs[0] auxiliary |
| 143690 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143691 | // MIs[0] Operand 8 |
| 143692 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143693 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143694 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143695 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_IDXEN_RTN), |
| 143696 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143697 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143698 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143699 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143701 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143702 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143703 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143704 | GIR_RootConstrainSelectedInstOperands, |
| 143705 | // GIR_Coverage, 6016, |
| 143706 | GIR_EraseRootFromParent_Done, |
| 143707 | // Label 6826: @462016 |
| 143708 | GIM_Try, /*On fail goto*//*Label 6827*/ GIMT_Encode4(462078), // Rule ID 6020 // |
| 143709 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 143710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 143712 | // MIs[0] offset |
| 143713 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143714 | // MIs[0] auxiliary |
| 143715 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143716 | // MIs[0] Operand 8 |
| 143717 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143719 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_IDXEN_RTN), |
| 143721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143722 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143723 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 143724 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143726 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143729 | GIR_RootConstrainSelectedInstOperands, |
| 143730 | // GIR_Coverage, 6020, |
| 143731 | GIR_EraseRootFromParent_Done, |
| 143732 | // Label 6827: @462078 |
| 143733 | GIM_Try, /*On fail goto*//*Label 6828*/ GIMT_Encode4(462174), // Rule ID 5910 // |
| 143734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143735 | GIM_CheckHasNoUse, /*MI*/0, |
| 143736 | // MIs[0] offset |
| 143737 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143738 | // MIs[0] auxiliary |
| 143739 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143740 | // MIs[0] Operand 8 |
| 143741 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143742 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143743 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143744 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143745 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143746 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143747 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143748 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143749 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143750 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143751 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143752 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143753 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN), |
| 143755 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143756 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143757 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143758 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143759 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143760 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143761 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143762 | GIR_RootConstrainSelectedInstOperands, |
| 143763 | // GIR_Coverage, 5910, |
| 143764 | GIR_EraseRootFromParent_Done, |
| 143765 | // Label 6828: @462174 |
| 143766 | GIM_Try, /*On fail goto*//*Label 6829*/ GIMT_Encode4(462270), // Rule ID 5918 // |
| 143767 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143768 | GIM_CheckHasNoUse, /*MI*/0, |
| 143769 | // MIs[0] offset |
| 143770 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143771 | // MIs[0] auxiliary |
| 143772 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143773 | // MIs[0] Operand 8 |
| 143774 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143776 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN anonymous_15876:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143777 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143778 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143779 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143780 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143781 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143782 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143783 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143784 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143785 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143786 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN), |
| 143788 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143789 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143790 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143791 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143792 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143793 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143795 | GIR_RootConstrainSelectedInstOperands, |
| 143796 | // GIR_Coverage, 5918, |
| 143797 | GIR_EraseRootFromParent_Done, |
| 143798 | // Label 6829: @462270 |
| 143799 | GIM_Try, /*On fail goto*//*Label 6830*/ GIMT_Encode4(462366), // Rule ID 6002 // |
| 143800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts_HasUnrestrictedSOffset), |
| 143801 | GIM_CheckHasNoUse, /*MI*/0, |
| 143802 | // MIs[0] offset |
| 143803 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143804 | // MIs[0] auxiliary |
| 143805 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143806 | // MIs[0] Operand 8 |
| 143807 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143809 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_BOTHEN anonymous_15876:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143810 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143811 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143812 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143813 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143814 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143815 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143816 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143817 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143818 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143819 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN), |
| 143821 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143822 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143823 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143824 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143825 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143826 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143827 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143828 | GIR_RootConstrainSelectedInstOperands, |
| 143829 | // GIR_Coverage, 6002, |
| 143830 | GIR_EraseRootFromParent_Done, |
| 143831 | // Label 6830: @462366 |
| 143832 | GIM_Try, /*On fail goto*//*Label 6831*/ GIMT_Encode4(462462), // Rule ID 6006 // |
| 143833 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16NoRtnInsts), |
| 143834 | GIM_CheckHasNoUse, /*MI*/0, |
| 143835 | // MIs[0] offset |
| 143836 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143837 | // MIs[0] auxiliary |
| 143838 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143839 | // MIs[0] Operand 8 |
| 143840 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143842 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fadd_noret>> => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN anonymous_15876:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143843 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143844 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143845 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143846 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143847 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143848 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143849 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143851 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143852 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN), |
| 143854 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143855 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143856 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143858 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143859 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 143860 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143861 | GIR_RootConstrainSelectedInstOperands, |
| 143862 | // GIR_Coverage, 6006, |
| 143863 | GIR_EraseRootFromParent_Done, |
| 143864 | // Label 6831: @462462 |
| 143865 | GIM_Try, /*On fail goto*//*Label 6832*/ GIMT_Encode4(462562), // Rule ID 5906 // |
| 143866 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst_HasUnrestrictedSOffset), |
| 143867 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143868 | // MIs[0] offset |
| 143869 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143870 | // MIs[0] auxiliary |
| 143871 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143872 | // MIs[0] Operand 8 |
| 143873 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143875 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143876 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143877 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143878 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143879 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143880 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143881 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143882 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143883 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143884 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143885 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_BOTHEN_RTN), |
| 143887 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143888 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143889 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143890 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143892 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143893 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143895 | GIR_RootConstrainSelectedInstOperands, |
| 143896 | // GIR_Coverage, 5906, |
| 143897 | GIR_EraseRootFromParent_Done, |
| 143898 | // Label 6832: @462562 |
| 143899 | GIM_Try, /*On fail goto*//*Label 6833*/ GIMT_Encode4(462662), // Rule ID 5914 // |
| 143900 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferPkAddBF16Inst), |
| 143901 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143902 | // MIs[0] offset |
| 143903 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143904 | // MIs[0] auxiliary |
| 143905 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143906 | // MIs[0] Operand 8 |
| 143907 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143909 | // (SIbuffer_atomic_fadd:{ *:[v2bf16] } v2bf16:{ *:[v2bf16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN:{ *:[v2bf16] } anonymous_15876:{ *:[v2bf16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143910 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143911 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143912 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143913 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143914 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143915 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143916 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143917 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143918 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143919 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_BF16_VBUFFER_BOTHEN_RTN), |
| 143921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143922 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143923 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143924 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143926 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143927 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143929 | GIR_RootConstrainSelectedInstOperands, |
| 143930 | // GIR_Coverage, 5914, |
| 143931 | GIR_EraseRootFromParent_Done, |
| 143932 | // Label 6833: @462662 |
| 143933 | GIM_Try, /*On fail goto*//*Label 6834*/ GIMT_Encode4(462762), // Rule ID 6018 // |
| 143934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts_HasUnrestrictedSOffset), |
| 143935 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143936 | // MIs[0] offset |
| 143937 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143938 | // MIs[0] auxiliary |
| 143939 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143940 | // MIs[0] Operand 8 |
| 143941 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143943 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143947 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143948 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143950 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143951 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143952 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143953 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_BOTHEN_RTN), |
| 143955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143956 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143957 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143958 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143960 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143963 | GIR_RootConstrainSelectedInstOperands, |
| 143964 | // GIR_Coverage, 6018, |
| 143965 | GIR_EraseRootFromParent_Done, |
| 143966 | // Label 6834: @462762 |
| 143967 | GIM_Try, /*On fail goto*//*Label 6835*/ GIMT_Encode4(462862), // Rule ID 6022 // |
| 143968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicBufferGlobalPkAddF16Insts), |
| 143969 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 143970 | // MIs[0] offset |
| 143971 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 143972 | // MIs[0] auxiliary |
| 143973 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 143974 | // MIs[0] Operand 8 |
| 143975 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 143976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 143977 | // (SIbuffer_atomic_fadd:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN:{ *:[v2f16] } anonymous_15876:{ *:[v2f16] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 143978 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 143979 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 143980 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 143981 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 143982 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 143983 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 143984 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 143985 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 143986 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143987 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 143988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_PK_ADD_F16_VBUFFER_BOTHEN_RTN), |
| 143989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 143990 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 143991 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 143992 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 143993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 143994 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 143995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 143996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 143997 | GIR_RootConstrainSelectedInstOperands, |
| 143998 | // GIR_Coverage, 6022, |
| 143999 | GIR_EraseRootFromParent_Done, |
| 144000 | // Label 6835: @462862 |
| 144001 | GIM_Reject, |
| 144002 | // Label 6803: @462863 |
| 144003 | GIM_Reject, |
| 144004 | // Label 6768: @462864 |
| 144005 | GIM_Reject, |
| 144006 | // Label 114: @462865 |
| 144007 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6838*/ GIMT_Encode4(466480), |
| 144008 | /*GILLT_s32*//*Label 6836*/ GIMT_Encode4(462884), |
| 144009 | /*GILLT_s64*//*Label 6837*/ GIMT_Encode4(464090), |
| 144010 | // Label 6836: @462884 |
| 144011 | GIM_Try, /*On fail goto*//*Label 6839*/ GIMT_Encode4(464089), |
| 144012 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 144013 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 144014 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 144015 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 144016 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 144017 | GIM_Try, /*On fail goto*//*Label 6840*/ GIMT_Encode4(462972), // Rule ID 5947 // |
| 144018 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144019 | GIM_CheckHasNoUse, /*MI*/0, |
| 144020 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144021 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144022 | // MIs[0] offset |
| 144023 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144024 | // MIs[0] auxiliary |
| 144025 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144026 | // MIs[0] Operand 8 |
| 144027 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144029 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET), |
| 144031 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144032 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144033 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144034 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144035 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144037 | GIR_RootConstrainSelectedInstOperands, |
| 144038 | // GIR_Coverage, 5947, |
| 144039 | GIR_EraseRootFromParent_Done, |
| 144040 | // Label 6840: @462972 |
| 144041 | GIM_Try, /*On fail goto*//*Label 6841*/ GIMT_Encode4(463040), // Rule ID 5955 // |
| 144042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144043 | GIM_CheckHasNoUse, /*MI*/0, |
| 144044 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144045 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144046 | // MIs[0] offset |
| 144047 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144048 | // MIs[0] auxiliary |
| 144049 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144050 | // MIs[0] Operand 8 |
| 144051 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144053 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144054 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET), |
| 144055 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144056 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144057 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144058 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144059 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144060 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144061 | GIR_RootConstrainSelectedInstOperands, |
| 144062 | // GIR_Coverage, 5955, |
| 144063 | GIR_EraseRootFromParent_Done, |
| 144064 | // Label 6841: @463040 |
| 144065 | GIM_Try, /*On fail goto*//*Label 6842*/ GIMT_Encode4(463112), // Rule ID 5943 // |
| 144066 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144067 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144068 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144069 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144070 | // MIs[0] offset |
| 144071 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144072 | // MIs[0] auxiliary |
| 144073 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144074 | // MIs[0] Operand 8 |
| 144075 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144077 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMAX_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFSET_RTN), |
| 144079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144080 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144081 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144083 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144084 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144085 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144086 | GIR_RootConstrainSelectedInstOperands, |
| 144087 | // GIR_Coverage, 5943, |
| 144088 | GIR_EraseRootFromParent_Done, |
| 144089 | // Label 6842: @463112 |
| 144090 | GIM_Try, /*On fail goto*//*Label 6843*/ GIMT_Encode4(463184), // Rule ID 5951 // |
| 144091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144092 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144093 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144094 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144095 | // MIs[0] offset |
| 144096 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144097 | // MIs[0] auxiliary |
| 144098 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144099 | // MIs[0] Operand 8 |
| 144100 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144102 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFSET_RTN), |
| 144104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144105 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144106 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144108 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144110 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144111 | GIR_RootConstrainSelectedInstOperands, |
| 144112 | // GIR_Coverage, 5951, |
| 144113 | GIR_EraseRootFromParent_Done, |
| 144114 | // Label 6843: @463184 |
| 144115 | GIM_Try, /*On fail goto*//*Label 6844*/ GIMT_Encode4(463250), // Rule ID 5949 // |
| 144116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144117 | GIM_CheckHasNoUse, /*MI*/0, |
| 144118 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144119 | // MIs[0] offset |
| 144120 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144121 | // MIs[0] auxiliary |
| 144122 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144123 | // MIs[0] Operand 8 |
| 144124 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144126 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN), |
| 144128 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144129 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144130 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144132 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144133 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144134 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144135 | GIR_RootConstrainSelectedInstOperands, |
| 144136 | // GIR_Coverage, 5949, |
| 144137 | GIR_EraseRootFromParent_Done, |
| 144138 | // Label 6844: @463250 |
| 144139 | GIM_Try, /*On fail goto*//*Label 6845*/ GIMT_Encode4(463316), // Rule ID 5957 // |
| 144140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144141 | GIM_CheckHasNoUse, /*MI*/0, |
| 144142 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144143 | // MIs[0] offset |
| 144144 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144145 | // MIs[0] auxiliary |
| 144146 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144147 | // MIs[0] Operand 8 |
| 144148 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144150 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN), |
| 144152 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144153 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144154 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144156 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144157 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144159 | GIR_RootConstrainSelectedInstOperands, |
| 144160 | // GIR_Coverage, 5957, |
| 144161 | GIR_EraseRootFromParent_Done, |
| 144162 | // Label 6845: @463316 |
| 144163 | GIM_Try, /*On fail goto*//*Label 6846*/ GIMT_Encode4(463386), // Rule ID 5945 // |
| 144164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144165 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144167 | // MIs[0] offset |
| 144168 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144169 | // MIs[0] auxiliary |
| 144170 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144171 | // MIs[0] Operand 8 |
| 144172 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144174 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMAX_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_OFFEN_RTN), |
| 144176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144177 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144178 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144179 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144180 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144181 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144182 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144184 | GIR_RootConstrainSelectedInstOperands, |
| 144185 | // GIR_Coverage, 5945, |
| 144186 | GIR_EraseRootFromParent_Done, |
| 144187 | // Label 6846: @463386 |
| 144188 | GIM_Try, /*On fail goto*//*Label 6847*/ GIMT_Encode4(463456), // Rule ID 5953 // |
| 144189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144190 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144191 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144192 | // MIs[0] offset |
| 144193 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144194 | // MIs[0] auxiliary |
| 144195 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144196 | // MIs[0] Operand 8 |
| 144197 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144199 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_OFFEN_RTN), |
| 144201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144202 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144203 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144204 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144206 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144207 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144208 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144209 | GIR_RootConstrainSelectedInstOperands, |
| 144210 | // GIR_Coverage, 5953, |
| 144211 | GIR_EraseRootFromParent_Done, |
| 144212 | // Label 6847: @463456 |
| 144213 | GIM_Try, /*On fail goto*//*Label 6848*/ GIMT_Encode4(463514), // Rule ID 5948 // |
| 144214 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144215 | GIM_CheckHasNoUse, /*MI*/0, |
| 144216 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144217 | // MIs[0] offset |
| 144218 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144219 | // MIs[0] auxiliary |
| 144220 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144221 | // MIs[0] Operand 8 |
| 144222 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144223 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144224 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN), |
| 144226 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144227 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144228 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144230 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144231 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144232 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144233 | GIR_RootConstrainSelectedInstOperands, |
| 144234 | // GIR_Coverage, 5948, |
| 144235 | GIR_EraseRootFromParent_Done, |
| 144236 | // Label 6848: @463514 |
| 144237 | GIM_Try, /*On fail goto*//*Label 6849*/ GIMT_Encode4(463572), // Rule ID 5956 // |
| 144238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144239 | GIM_CheckHasNoUse, /*MI*/0, |
| 144240 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144241 | // MIs[0] offset |
| 144242 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144243 | // MIs[0] auxiliary |
| 144244 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144245 | // MIs[0] Operand 8 |
| 144246 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144247 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144248 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144249 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN), |
| 144250 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144251 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144252 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144253 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144254 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144255 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144257 | GIR_RootConstrainSelectedInstOperands, |
| 144258 | // GIR_Coverage, 5956, |
| 144259 | GIR_EraseRootFromParent_Done, |
| 144260 | // Label 6849: @463572 |
| 144261 | GIM_Try, /*On fail goto*//*Label 6850*/ GIMT_Encode4(463634), // Rule ID 5944 // |
| 144262 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144263 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144264 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144265 | // MIs[0] offset |
| 144266 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144267 | // MIs[0] auxiliary |
| 144268 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144269 | // MIs[0] Operand 8 |
| 144270 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144271 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144272 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMAX_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144273 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_IDXEN_RTN), |
| 144274 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144275 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144276 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144277 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144279 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144280 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144281 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144282 | GIR_RootConstrainSelectedInstOperands, |
| 144283 | // GIR_Coverage, 5944, |
| 144284 | GIR_EraseRootFromParent_Done, |
| 144285 | // Label 6850: @463634 |
| 144286 | GIM_Try, /*On fail goto*//*Label 6851*/ GIMT_Encode4(463696), // Rule ID 5952 // |
| 144287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144290 | // MIs[0] offset |
| 144291 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144292 | // MIs[0] auxiliary |
| 144293 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144294 | // MIs[0] Operand 8 |
| 144295 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144297 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_IDXEN_RTN), |
| 144299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144300 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144301 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144302 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144304 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144306 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144307 | GIR_RootConstrainSelectedInstOperands, |
| 144308 | // GIR_Coverage, 5952, |
| 144309 | GIR_EraseRootFromParent_Done, |
| 144310 | // Label 6851: @463696 |
| 144311 | GIM_Try, /*On fail goto*//*Label 6852*/ GIMT_Encode4(463792), // Rule ID 5950 // |
| 144312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144313 | GIM_CheckHasNoUse, /*MI*/0, |
| 144314 | // MIs[0] offset |
| 144315 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144316 | // MIs[0] auxiliary |
| 144317 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144318 | // MIs[0] Operand 8 |
| 144319 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144321 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144322 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 144323 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 144324 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 144325 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 144326 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 144327 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 144328 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 144329 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 144330 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144331 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144332 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN), |
| 144333 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144334 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 144335 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144336 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144337 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144338 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144339 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144340 | GIR_RootConstrainSelectedInstOperands, |
| 144341 | // GIR_Coverage, 5950, |
| 144342 | GIR_EraseRootFromParent_Done, |
| 144343 | // Label 6852: @463792 |
| 144344 | GIM_Try, /*On fail goto*//*Label 6853*/ GIMT_Encode4(463888), // Rule ID 5958 // |
| 144345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144346 | GIM_CheckHasNoUse, /*MI*/0, |
| 144347 | // MIs[0] offset |
| 144348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144349 | // MIs[0] auxiliary |
| 144350 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144351 | // MIs[0] Operand 8 |
| 144352 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144353 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144354 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144355 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 144356 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 144357 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 144358 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 144359 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 144360 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 144361 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 144362 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 144363 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144364 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN), |
| 144366 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144367 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 144368 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144370 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144371 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144373 | GIR_RootConstrainSelectedInstOperands, |
| 144374 | // GIR_Coverage, 5958, |
| 144375 | GIR_EraseRootFromParent_Done, |
| 144376 | // Label 6853: @463888 |
| 144377 | GIM_Try, /*On fail goto*//*Label 6854*/ GIMT_Encode4(463988), // Rule ID 5946 // |
| 144378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 144379 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144380 | // MIs[0] offset |
| 144381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144382 | // MIs[0] auxiliary |
| 144383 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144384 | // MIs[0] Operand 8 |
| 144385 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144387 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMAX_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144388 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 144389 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 144390 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 144391 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 144392 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 144393 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 144394 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 144395 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 144396 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144397 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_BOTHEN_RTN), |
| 144399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144400 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144401 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 144402 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144404 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144405 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144406 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144407 | GIR_RootConstrainSelectedInstOperands, |
| 144408 | // GIR_Coverage, 5946, |
| 144409 | GIR_EraseRootFromParent_Done, |
| 144410 | // Label 6854: @463988 |
| 144411 | GIM_Try, /*On fail goto*//*Label 6855*/ GIMT_Encode4(464088), // Rule ID 5954 // |
| 144412 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 144413 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 144414 | // MIs[0] offset |
| 144415 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144416 | // MIs[0] auxiliary |
| 144417 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144418 | // MIs[0] Operand 8 |
| 144419 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144420 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144421 | // (SIbuffer_atomic_fmax:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144422 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 144423 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 144424 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 144425 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 144426 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 144427 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 144428 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 144429 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 144430 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144431 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 144432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMAX_VBUFFER_BOTHEN_RTN), |
| 144433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144434 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144435 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 144436 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144438 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144440 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144441 | GIR_RootConstrainSelectedInstOperands, |
| 144442 | // GIR_Coverage, 5954, |
| 144443 | GIR_EraseRootFromParent_Done, |
| 144444 | // Label 6855: @464088 |
| 144445 | GIM_Reject, |
| 144446 | // Label 6839: @464089 |
| 144447 | GIM_Reject, |
| 144448 | // Label 6837: @464090 |
| 144449 | GIM_Try, /*On fail goto*//*Label 6856*/ GIMT_Encode4(466479), |
| 144450 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 144451 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 144452 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 144453 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 144454 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 144455 | GIM_Try, /*On fail goto*//*Label 6857*/ GIMT_Encode4(464178), // Rule ID 5979 // |
| 144456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144457 | GIM_CheckHasNoUse, /*MI*/0, |
| 144458 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144459 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144460 | // MIs[0] offset |
| 144461 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144462 | // MIs[0] auxiliary |
| 144463 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144464 | // MIs[0] Operand 8 |
| 144465 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144467 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET), |
| 144469 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144470 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144472 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144473 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144474 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144475 | GIR_RootConstrainSelectedInstOperands, |
| 144476 | // GIR_Coverage, 5979, |
| 144477 | GIR_EraseRootFromParent_Done, |
| 144478 | // Label 6857: @464178 |
| 144479 | GIM_Try, /*On fail goto*//*Label 6858*/ GIMT_Encode4(464246), // Rule ID 5987 // |
| 144480 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144481 | GIM_CheckHasNoUse, /*MI*/0, |
| 144482 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144483 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144484 | // MIs[0] offset |
| 144485 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144486 | // MIs[0] auxiliary |
| 144487 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144488 | // MIs[0] Operand 8 |
| 144489 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144490 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144491 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144492 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET), |
| 144493 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144494 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144496 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144497 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144499 | GIR_RootConstrainSelectedInstOperands, |
| 144500 | // GIR_Coverage, 5987, |
| 144501 | GIR_EraseRootFromParent_Done, |
| 144502 | // Label 6858: @464246 |
| 144503 | GIM_Try, /*On fail goto*//*Label 6859*/ GIMT_Encode4(464314), // Rule ID 6059 // |
| 144504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144505 | GIM_CheckHasNoUse, /*MI*/0, |
| 144506 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144507 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144508 | // MIs[0] offset |
| 144509 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144510 | // MIs[0] auxiliary |
| 144511 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144512 | // MIs[0] Operand 8 |
| 144513 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144515 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET), |
| 144517 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144518 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144520 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144521 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144523 | GIR_RootConstrainSelectedInstOperands, |
| 144524 | // GIR_Coverage, 6059, |
| 144525 | GIR_EraseRootFromParent_Done, |
| 144526 | // Label 6859: @464314 |
| 144527 | GIM_Try, /*On fail goto*//*Label 6860*/ GIMT_Encode4(464382), // Rule ID 6067 // |
| 144528 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144529 | GIM_CheckHasNoUse, /*MI*/0, |
| 144530 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144531 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144532 | // MIs[0] offset |
| 144533 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144534 | // MIs[0] auxiliary |
| 144535 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144536 | // MIs[0] Operand 8 |
| 144537 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144539 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET), |
| 144541 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144542 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144544 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144545 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144547 | GIR_RootConstrainSelectedInstOperands, |
| 144548 | // GIR_Coverage, 6067, |
| 144549 | GIR_EraseRootFromParent_Done, |
| 144550 | // Label 6860: @464382 |
| 144551 | GIM_Try, /*On fail goto*//*Label 6861*/ GIMT_Encode4(464454), // Rule ID 5975 // |
| 144552 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144553 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144555 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144556 | // MIs[0] offset |
| 144557 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144558 | // MIs[0] auxiliary |
| 144559 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144560 | // MIs[0] Operand 8 |
| 144561 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144563 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN), |
| 144565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144566 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144567 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144569 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144570 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144572 | GIR_RootConstrainSelectedInstOperands, |
| 144573 | // GIR_Coverage, 5975, |
| 144574 | GIR_EraseRootFromParent_Done, |
| 144575 | // Label 6861: @464454 |
| 144576 | GIM_Try, /*On fail goto*//*Label 6862*/ GIMT_Encode4(464526), // Rule ID 5983 // |
| 144577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144578 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144581 | // MIs[0] offset |
| 144582 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144583 | // MIs[0] auxiliary |
| 144584 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144585 | // MIs[0] Operand 8 |
| 144586 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144588 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN), |
| 144590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144591 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144592 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144594 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144595 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144597 | GIR_RootConstrainSelectedInstOperands, |
| 144598 | // GIR_Coverage, 5983, |
| 144599 | GIR_EraseRootFromParent_Done, |
| 144600 | // Label 6862: @464526 |
| 144601 | GIM_Try, /*On fail goto*//*Label 6863*/ GIMT_Encode4(464598), // Rule ID 6055 // |
| 144602 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144603 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144604 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144605 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144606 | // MIs[0] offset |
| 144607 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144608 | // MIs[0] auxiliary |
| 144609 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144610 | // MIs[0] Operand 8 |
| 144611 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144612 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144613 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFSET_RTN), |
| 144615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144616 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144617 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144619 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144620 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144621 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144622 | GIR_RootConstrainSelectedInstOperands, |
| 144623 | // GIR_Coverage, 6055, |
| 144624 | GIR_EraseRootFromParent_Done, |
| 144625 | // Label 6863: @464598 |
| 144626 | GIM_Try, /*On fail goto*//*Label 6864*/ GIMT_Encode4(464670), // Rule ID 6063 // |
| 144627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144628 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144629 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144630 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144631 | // MIs[0] offset |
| 144632 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144633 | // MIs[0] auxiliary |
| 144634 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144635 | // MIs[0] Operand 8 |
| 144636 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144638 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFSET_RTN), |
| 144640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144641 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144642 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144644 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144645 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144646 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144647 | GIR_RootConstrainSelectedInstOperands, |
| 144648 | // GIR_Coverage, 6063, |
| 144649 | GIR_EraseRootFromParent_Done, |
| 144650 | // Label 6864: @464670 |
| 144651 | GIM_Try, /*On fail goto*//*Label 6865*/ GIMT_Encode4(464736), // Rule ID 5981 // |
| 144652 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144653 | GIM_CheckHasNoUse, /*MI*/0, |
| 144654 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144655 | // MIs[0] offset |
| 144656 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144657 | // MIs[0] auxiliary |
| 144658 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144659 | // MIs[0] Operand 8 |
| 144660 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144661 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144662 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144663 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN), |
| 144664 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144665 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144666 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144667 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144668 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144669 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144670 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144671 | GIR_RootConstrainSelectedInstOperands, |
| 144672 | // GIR_Coverage, 5981, |
| 144673 | GIR_EraseRootFromParent_Done, |
| 144674 | // Label 6865: @464736 |
| 144675 | GIM_Try, /*On fail goto*//*Label 6866*/ GIMT_Encode4(464802), // Rule ID 5989 // |
| 144676 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144677 | GIM_CheckHasNoUse, /*MI*/0, |
| 144678 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144679 | // MIs[0] offset |
| 144680 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144681 | // MIs[0] auxiliary |
| 144682 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144683 | // MIs[0] Operand 8 |
| 144684 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144686 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN), |
| 144688 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144689 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144690 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144692 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144693 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144695 | GIR_RootConstrainSelectedInstOperands, |
| 144696 | // GIR_Coverage, 5989, |
| 144697 | GIR_EraseRootFromParent_Done, |
| 144698 | // Label 6866: @464802 |
| 144699 | GIM_Try, /*On fail goto*//*Label 6867*/ GIMT_Encode4(464868), // Rule ID 6061 // |
| 144700 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144701 | GIM_CheckHasNoUse, /*MI*/0, |
| 144702 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144703 | // MIs[0] offset |
| 144704 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144705 | // MIs[0] auxiliary |
| 144706 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144707 | // MIs[0] Operand 8 |
| 144708 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144709 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144710 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144711 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN), |
| 144712 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144713 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144714 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144716 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144717 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144718 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144719 | GIR_RootConstrainSelectedInstOperands, |
| 144720 | // GIR_Coverage, 6061, |
| 144721 | GIR_EraseRootFromParent_Done, |
| 144722 | // Label 6867: @464868 |
| 144723 | GIM_Try, /*On fail goto*//*Label 6868*/ GIMT_Encode4(464934), // Rule ID 6069 // |
| 144724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144725 | GIM_CheckHasNoUse, /*MI*/0, |
| 144726 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144727 | // MIs[0] offset |
| 144728 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144729 | // MIs[0] auxiliary |
| 144730 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144731 | // MIs[0] Operand 8 |
| 144732 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144734 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN), |
| 144736 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144737 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144738 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144740 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144741 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144743 | GIR_RootConstrainSelectedInstOperands, |
| 144744 | // GIR_Coverage, 6069, |
| 144745 | GIR_EraseRootFromParent_Done, |
| 144746 | // Label 6868: @464934 |
| 144747 | GIM_Try, /*On fail goto*//*Label 6869*/ GIMT_Encode4(465004), // Rule ID 5977 // |
| 144748 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144749 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144750 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144751 | // MIs[0] offset |
| 144752 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144753 | // MIs[0] auxiliary |
| 144754 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144755 | // MIs[0] Operand 8 |
| 144756 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144757 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144758 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN), |
| 144760 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144761 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144762 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144763 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144765 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144767 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144768 | GIR_RootConstrainSelectedInstOperands, |
| 144769 | // GIR_Coverage, 5977, |
| 144770 | GIR_EraseRootFromParent_Done, |
| 144771 | // Label 6869: @465004 |
| 144772 | GIM_Try, /*On fail goto*//*Label 6870*/ GIMT_Encode4(465074), // Rule ID 5985 // |
| 144773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144774 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144775 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144776 | // MIs[0] offset |
| 144777 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144778 | // MIs[0] auxiliary |
| 144779 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144780 | // MIs[0] Operand 8 |
| 144781 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144783 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN), |
| 144785 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144786 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144787 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144788 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144790 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144791 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144792 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144793 | GIR_RootConstrainSelectedInstOperands, |
| 144794 | // GIR_Coverage, 5985, |
| 144795 | GIR_EraseRootFromParent_Done, |
| 144796 | // Label 6870: @465074 |
| 144797 | GIM_Try, /*On fail goto*//*Label 6871*/ GIMT_Encode4(465144), // Rule ID 6057 // |
| 144798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144799 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144800 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144801 | // MIs[0] offset |
| 144802 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144803 | // MIs[0] auxiliary |
| 144804 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144805 | // MIs[0] Operand 8 |
| 144806 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144807 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144808 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144809 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_OFFEN_RTN), |
| 144810 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144811 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144812 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144813 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144814 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144815 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144816 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144818 | GIR_RootConstrainSelectedInstOperands, |
| 144819 | // GIR_Coverage, 6057, |
| 144820 | GIR_EraseRootFromParent_Done, |
| 144821 | // Label 6871: @465144 |
| 144822 | GIM_Try, /*On fail goto*//*Label 6872*/ GIMT_Encode4(465214), // Rule ID 6065 // |
| 144823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144824 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144825 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 144826 | // MIs[0] offset |
| 144827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144828 | // MIs[0] auxiliary |
| 144829 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144830 | // MIs[0] Operand 8 |
| 144831 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 144832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144833 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144834 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_OFFEN_RTN), |
| 144835 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144836 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144837 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 144838 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144839 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144840 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144841 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144842 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144843 | GIR_RootConstrainSelectedInstOperands, |
| 144844 | // GIR_Coverage, 6065, |
| 144845 | GIR_EraseRootFromParent_Done, |
| 144846 | // Label 6872: @465214 |
| 144847 | GIM_Try, /*On fail goto*//*Label 6873*/ GIMT_Encode4(465272), // Rule ID 5980 // |
| 144848 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144849 | GIM_CheckHasNoUse, /*MI*/0, |
| 144850 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144851 | // MIs[0] offset |
| 144852 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144853 | // MIs[0] auxiliary |
| 144854 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144855 | // MIs[0] Operand 8 |
| 144856 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144857 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144858 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN), |
| 144860 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144861 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144862 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144864 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144865 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144866 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144867 | GIR_RootConstrainSelectedInstOperands, |
| 144868 | // GIR_Coverage, 5980, |
| 144869 | GIR_EraseRootFromParent_Done, |
| 144870 | // Label 6873: @465272 |
| 144871 | GIM_Try, /*On fail goto*//*Label 6874*/ GIMT_Encode4(465330), // Rule ID 5988 // |
| 144872 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144873 | GIM_CheckHasNoUse, /*MI*/0, |
| 144874 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144875 | // MIs[0] offset |
| 144876 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144877 | // MIs[0] auxiliary |
| 144878 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144879 | // MIs[0] Operand 8 |
| 144880 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144882 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN), |
| 144884 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144885 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144886 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144888 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144891 | GIR_RootConstrainSelectedInstOperands, |
| 144892 | // GIR_Coverage, 5988, |
| 144893 | GIR_EraseRootFromParent_Done, |
| 144894 | // Label 6874: @465330 |
| 144895 | GIM_Try, /*On fail goto*//*Label 6875*/ GIMT_Encode4(465388), // Rule ID 6060 // |
| 144896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144897 | GIM_CheckHasNoUse, /*MI*/0, |
| 144898 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144899 | // MIs[0] offset |
| 144900 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144901 | // MIs[0] auxiliary |
| 144902 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144903 | // MIs[0] Operand 8 |
| 144904 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144906 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN), |
| 144908 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144909 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144910 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144912 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144913 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144915 | GIR_RootConstrainSelectedInstOperands, |
| 144916 | // GIR_Coverage, 6060, |
| 144917 | GIR_EraseRootFromParent_Done, |
| 144918 | // Label 6875: @465388 |
| 144919 | GIM_Try, /*On fail goto*//*Label 6876*/ GIMT_Encode4(465446), // Rule ID 6068 // |
| 144920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144921 | GIM_CheckHasNoUse, /*MI*/0, |
| 144922 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144923 | // MIs[0] offset |
| 144924 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144925 | // MIs[0] auxiliary |
| 144926 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144927 | // MIs[0] Operand 8 |
| 144928 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144929 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144930 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144931 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN), |
| 144932 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144933 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144934 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144935 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144936 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144937 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 144938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144939 | GIR_RootConstrainSelectedInstOperands, |
| 144940 | // GIR_Coverage, 6068, |
| 144941 | GIR_EraseRootFromParent_Done, |
| 144942 | // Label 6876: @465446 |
| 144943 | GIM_Try, /*On fail goto*//*Label 6877*/ GIMT_Encode4(465508), // Rule ID 5976 // |
| 144944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144945 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144946 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144947 | // MIs[0] offset |
| 144948 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144949 | // MIs[0] auxiliary |
| 144950 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144951 | // MIs[0] Operand 8 |
| 144952 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144954 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN), |
| 144956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144957 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144958 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144959 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144961 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144962 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144964 | GIR_RootConstrainSelectedInstOperands, |
| 144965 | // GIR_Coverage, 5976, |
| 144966 | GIR_EraseRootFromParent_Done, |
| 144967 | // Label 6877: @465508 |
| 144968 | GIM_Try, /*On fail goto*//*Label 6878*/ GIMT_Encode4(465570), // Rule ID 5984 // |
| 144969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 144970 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144971 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144972 | // MIs[0] offset |
| 144973 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144974 | // MIs[0] auxiliary |
| 144975 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 144976 | // MIs[0] Operand 8 |
| 144977 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 144978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 144979 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 144980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN), |
| 144981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 144982 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 144983 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 144984 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 144985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 144986 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 144987 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 144988 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 144989 | GIR_RootConstrainSelectedInstOperands, |
| 144990 | // GIR_Coverage, 5984, |
| 144991 | GIR_EraseRootFromParent_Done, |
| 144992 | // Label 6878: @465570 |
| 144993 | GIM_Try, /*On fail goto*//*Label 6879*/ GIMT_Encode4(465632), // Rule ID 6056 // |
| 144994 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 144995 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 144996 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 144997 | // MIs[0] offset |
| 144998 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 144999 | // MIs[0] auxiliary |
| 145000 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145001 | // MIs[0] Operand 8 |
| 145002 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145003 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145004 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145005 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_IDXEN_RTN), |
| 145006 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145007 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145008 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145009 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145011 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145012 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145013 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145014 | GIR_RootConstrainSelectedInstOperands, |
| 145015 | // GIR_Coverage, 6056, |
| 145016 | GIR_EraseRootFromParent_Done, |
| 145017 | // Label 6879: @465632 |
| 145018 | GIM_Try, /*On fail goto*//*Label 6880*/ GIMT_Encode4(465694), // Rule ID 6064 // |
| 145019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145021 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145022 | // MIs[0] offset |
| 145023 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145024 | // MIs[0] auxiliary |
| 145025 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145026 | // MIs[0] Operand 8 |
| 145027 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145029 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_IDXEN_RTN), |
| 145031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145032 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145033 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145034 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145036 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145037 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145038 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145039 | GIR_RootConstrainSelectedInstOperands, |
| 145040 | // GIR_Coverage, 6064, |
| 145041 | GIR_EraseRootFromParent_Done, |
| 145042 | // Label 6880: @465694 |
| 145043 | GIM_Try, /*On fail goto*//*Label 6881*/ GIMT_Encode4(465790), // Rule ID 5982 // |
| 145044 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145045 | GIM_CheckHasNoUse, /*MI*/0, |
| 145046 | // MIs[0] offset |
| 145047 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145048 | // MIs[0] auxiliary |
| 145049 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145050 | // MIs[0] Operand 8 |
| 145051 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145052 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145053 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145054 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145055 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145056 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145057 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145058 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145059 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145060 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145061 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145062 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145063 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN), |
| 145065 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145066 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145067 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145069 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145070 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145072 | GIR_RootConstrainSelectedInstOperands, |
| 145073 | // GIR_Coverage, 5982, |
| 145074 | GIR_EraseRootFromParent_Done, |
| 145075 | // Label 6881: @465790 |
| 145076 | GIM_Try, /*On fail goto*//*Label 6882*/ GIMT_Encode4(465886), // Rule ID 5990 // |
| 145077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145078 | GIM_CheckHasNoUse, /*MI*/0, |
| 145079 | // MIs[0] offset |
| 145080 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145081 | // MIs[0] auxiliary |
| 145082 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145083 | // MIs[0] Operand 8 |
| 145084 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145086 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145087 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145088 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145089 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145090 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145091 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145092 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145093 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145094 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145095 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145096 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145097 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN), |
| 145098 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145099 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145100 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145101 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145102 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145103 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145104 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145105 | GIR_RootConstrainSelectedInstOperands, |
| 145106 | // GIR_Coverage, 5990, |
| 145107 | GIR_EraseRootFromParent_Done, |
| 145108 | // Label 6882: @465886 |
| 145109 | GIM_Try, /*On fail goto*//*Label 6883*/ GIMT_Encode4(465982), // Rule ID 6062 // |
| 145110 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145111 | GIM_CheckHasNoUse, /*MI*/0, |
| 145112 | // MIs[0] offset |
| 145113 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145114 | // MIs[0] auxiliary |
| 145115 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145116 | // MIs[0] Operand 8 |
| 145117 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145118 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145119 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145120 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145121 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145122 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145123 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145124 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145125 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145126 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145127 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145128 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145129 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145130 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN), |
| 145131 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145132 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145133 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145135 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145136 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145138 | GIR_RootConstrainSelectedInstOperands, |
| 145139 | // GIR_Coverage, 6062, |
| 145140 | GIR_EraseRootFromParent_Done, |
| 145141 | // Label 6883: @465982 |
| 145142 | GIM_Try, /*On fail goto*//*Label 6884*/ GIMT_Encode4(466078), // Rule ID 6070 // |
| 145143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145144 | GIM_CheckHasNoUse, /*MI*/0, |
| 145145 | // MIs[0] offset |
| 145146 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145147 | // MIs[0] auxiliary |
| 145148 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145149 | // MIs[0] Operand 8 |
| 145150 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145151 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145152 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmax_noret>> => (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145153 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145154 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145155 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145156 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145157 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145158 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145159 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145160 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145161 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145162 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN), |
| 145164 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145165 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145166 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145168 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145169 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145170 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145171 | GIR_RootConstrainSelectedInstOperands, |
| 145172 | // GIR_Coverage, 6070, |
| 145173 | GIR_EraseRootFromParent_Done, |
| 145174 | // Label 6884: @466078 |
| 145175 | GIM_Try, /*On fail goto*//*Label 6885*/ GIMT_Encode4(466178), // Rule ID 5978 // |
| 145176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145178 | // MIs[0] offset |
| 145179 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145180 | // MIs[0] auxiliary |
| 145181 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145182 | // MIs[0] Operand 8 |
| 145183 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145185 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145186 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145187 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145188 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145189 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145190 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145191 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145192 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145193 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145194 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145195 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN), |
| 145197 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145198 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145199 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145200 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145202 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145203 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145204 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145205 | GIR_RootConstrainSelectedInstOperands, |
| 145206 | // GIR_Coverage, 5978, |
| 145207 | GIR_EraseRootFromParent_Done, |
| 145208 | // Label 6885: @466178 |
| 145209 | GIM_Try, /*On fail goto*//*Label 6886*/ GIMT_Encode4(466278), // Rule ID 5986 // |
| 145210 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145211 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145212 | // MIs[0] offset |
| 145213 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145214 | // MIs[0] auxiliary |
| 145215 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145216 | // MIs[0] Operand 8 |
| 145217 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145219 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145220 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145221 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145222 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145223 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145224 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145225 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145226 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145227 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145228 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145229 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN), |
| 145231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145232 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145233 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145234 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145236 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145237 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145239 | GIR_RootConstrainSelectedInstOperands, |
| 145240 | // GIR_Coverage, 5986, |
| 145241 | GIR_EraseRootFromParent_Done, |
| 145242 | // Label 6886: @466278 |
| 145243 | GIM_Try, /*On fail goto*//*Label 6887*/ GIMT_Encode4(466378), // Rule ID 6058 // |
| 145244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145246 | // MIs[0] offset |
| 145247 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145248 | // MIs[0] auxiliary |
| 145249 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145250 | // MIs[0] Operand 8 |
| 145251 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145252 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145253 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145254 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145255 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145256 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145257 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145258 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145259 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145260 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145261 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145262 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145263 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_BOTHEN_RTN), |
| 145265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145266 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145267 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145268 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145270 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145273 | GIR_RootConstrainSelectedInstOperands, |
| 145274 | // GIR_Coverage, 6058, |
| 145275 | GIR_EraseRootFromParent_Done, |
| 145276 | // Label 6887: @466378 |
| 145277 | GIM_Try, /*On fail goto*//*Label 6888*/ GIMT_Encode4(466478), // Rule ID 6066 // |
| 145278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145280 | // MIs[0] offset |
| 145281 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145282 | // MIs[0] auxiliary |
| 145283 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145284 | // MIs[0] Operand 8 |
| 145285 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145286 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145287 | // (SIbuffer_atomic_fmax:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145288 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145289 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145290 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145291 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145292 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145293 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145294 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145295 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145296 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145297 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MAX_F64_VBUFFER_BOTHEN_RTN), |
| 145299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145300 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145302 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145304 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145306 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145307 | GIR_RootConstrainSelectedInstOperands, |
| 145308 | // GIR_Coverage, 6066, |
| 145309 | GIR_EraseRootFromParent_Done, |
| 145310 | // Label 6888: @466478 |
| 145311 | GIM_Reject, |
| 145312 | // Label 6856: @466479 |
| 145313 | GIM_Reject, |
| 145314 | // Label 6838: @466480 |
| 145315 | GIM_Reject, |
| 145316 | // Label 115: @466481 |
| 145317 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6891*/ GIMT_Encode4(470096), |
| 145318 | /*GILLT_s32*//*Label 6889*/ GIMT_Encode4(466500), |
| 145319 | /*GILLT_s64*//*Label 6890*/ GIMT_Encode4(467706), |
| 145320 | // Label 6889: @466500 |
| 145321 | GIM_Try, /*On fail goto*//*Label 6892*/ GIMT_Encode4(467705), |
| 145322 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 145323 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 145324 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 145325 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 145326 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 145327 | GIM_Try, /*On fail goto*//*Label 6893*/ GIMT_Encode4(466588), // Rule ID 5931 // |
| 145328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145329 | GIM_CheckHasNoUse, /*MI*/0, |
| 145330 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145332 | // MIs[0] offset |
| 145333 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145334 | // MIs[0] auxiliary |
| 145335 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145336 | // MIs[0] Operand 8 |
| 145337 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145339 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET), |
| 145341 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145342 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145344 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145347 | GIR_RootConstrainSelectedInstOperands, |
| 145348 | // GIR_Coverage, 5931, |
| 145349 | GIR_EraseRootFromParent_Done, |
| 145350 | // Label 6893: @466588 |
| 145351 | GIM_Try, /*On fail goto*//*Label 6894*/ GIMT_Encode4(466656), // Rule ID 5939 // |
| 145352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145353 | GIM_CheckHasNoUse, /*MI*/0, |
| 145354 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145355 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145356 | // MIs[0] offset |
| 145357 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145358 | // MIs[0] auxiliary |
| 145359 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145360 | // MIs[0] Operand 8 |
| 145361 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145363 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET), |
| 145365 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145366 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145368 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145371 | GIR_RootConstrainSelectedInstOperands, |
| 145372 | // GIR_Coverage, 5939, |
| 145373 | GIR_EraseRootFromParent_Done, |
| 145374 | // Label 6894: @466656 |
| 145375 | GIM_Try, /*On fail goto*//*Label 6895*/ GIMT_Encode4(466728), // Rule ID 5927 // |
| 145376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145377 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145379 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145380 | // MIs[0] offset |
| 145381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145382 | // MIs[0] auxiliary |
| 145383 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145384 | // MIs[0] Operand 8 |
| 145385 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145387 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMIN_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFSET_RTN), |
| 145389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145390 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145391 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145393 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145395 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145396 | GIR_RootConstrainSelectedInstOperands, |
| 145397 | // GIR_Coverage, 5927, |
| 145398 | GIR_EraseRootFromParent_Done, |
| 145399 | // Label 6895: @466728 |
| 145400 | GIM_Try, /*On fail goto*//*Label 6896*/ GIMT_Encode4(466800), // Rule ID 5935 // |
| 145401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145402 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145403 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145404 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145405 | // MIs[0] offset |
| 145406 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145407 | // MIs[0] auxiliary |
| 145408 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145409 | // MIs[0] Operand 8 |
| 145410 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145412 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFSET_RTN), |
| 145414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145415 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145416 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145418 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145419 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145420 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145421 | GIR_RootConstrainSelectedInstOperands, |
| 145422 | // GIR_Coverage, 5935, |
| 145423 | GIR_EraseRootFromParent_Done, |
| 145424 | // Label 6896: @466800 |
| 145425 | GIM_Try, /*On fail goto*//*Label 6897*/ GIMT_Encode4(466866), // Rule ID 5933 // |
| 145426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145427 | GIM_CheckHasNoUse, /*MI*/0, |
| 145428 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145429 | // MIs[0] offset |
| 145430 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145431 | // MIs[0] auxiliary |
| 145432 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145433 | // MIs[0] Operand 8 |
| 145434 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145436 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN), |
| 145438 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145439 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 145440 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145442 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145445 | GIR_RootConstrainSelectedInstOperands, |
| 145446 | // GIR_Coverage, 5933, |
| 145447 | GIR_EraseRootFromParent_Done, |
| 145448 | // Label 6897: @466866 |
| 145449 | GIM_Try, /*On fail goto*//*Label 6898*/ GIMT_Encode4(466932), // Rule ID 5941 // |
| 145450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145451 | GIM_CheckHasNoUse, /*MI*/0, |
| 145452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145453 | // MIs[0] offset |
| 145454 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145455 | // MIs[0] auxiliary |
| 145456 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145457 | // MIs[0] Operand 8 |
| 145458 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145460 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN), |
| 145462 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145463 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 145464 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145466 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145469 | GIR_RootConstrainSelectedInstOperands, |
| 145470 | // GIR_Coverage, 5941, |
| 145471 | GIR_EraseRootFromParent_Done, |
| 145472 | // Label 6898: @466932 |
| 145473 | GIM_Try, /*On fail goto*//*Label 6899*/ GIMT_Encode4(467002), // Rule ID 5929 // |
| 145474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145476 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145477 | // MIs[0] offset |
| 145478 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145479 | // MIs[0] auxiliary |
| 145480 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145481 | // MIs[0] Operand 8 |
| 145482 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145484 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMIN_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_OFFEN_RTN), |
| 145486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145487 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145488 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 145489 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145490 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145491 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145492 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145493 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145494 | GIR_RootConstrainSelectedInstOperands, |
| 145495 | // GIR_Coverage, 5929, |
| 145496 | GIR_EraseRootFromParent_Done, |
| 145497 | // Label 6899: @467002 |
| 145498 | GIM_Try, /*On fail goto*//*Label 6900*/ GIMT_Encode4(467072), // Rule ID 5937 // |
| 145499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145501 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145502 | // MIs[0] offset |
| 145503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145504 | // MIs[0] auxiliary |
| 145505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145506 | // MIs[0] Operand 8 |
| 145507 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145509 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_OFFEN_RTN), |
| 145511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145512 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145513 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 145514 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145516 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145517 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145518 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145519 | GIR_RootConstrainSelectedInstOperands, |
| 145520 | // GIR_Coverage, 5937, |
| 145521 | GIR_EraseRootFromParent_Done, |
| 145522 | // Label 6900: @467072 |
| 145523 | GIM_Try, /*On fail goto*//*Label 6901*/ GIMT_Encode4(467130), // Rule ID 5932 // |
| 145524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145525 | GIM_CheckHasNoUse, /*MI*/0, |
| 145526 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145527 | // MIs[0] offset |
| 145528 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145529 | // MIs[0] auxiliary |
| 145530 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145531 | // MIs[0] Operand 8 |
| 145532 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145534 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145535 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN), |
| 145536 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145537 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145538 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145539 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145540 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145541 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145542 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145543 | GIR_RootConstrainSelectedInstOperands, |
| 145544 | // GIR_Coverage, 5932, |
| 145545 | GIR_EraseRootFromParent_Done, |
| 145546 | // Label 6901: @467130 |
| 145547 | GIM_Try, /*On fail goto*//*Label 6902*/ GIMT_Encode4(467188), // Rule ID 5940 // |
| 145548 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145549 | GIM_CheckHasNoUse, /*MI*/0, |
| 145550 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145551 | // MIs[0] offset |
| 145552 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145553 | // MIs[0] auxiliary |
| 145554 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145555 | // MIs[0] Operand 8 |
| 145556 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145557 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145558 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN), |
| 145560 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145561 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145562 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145564 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145565 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145566 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145567 | GIR_RootConstrainSelectedInstOperands, |
| 145568 | // GIR_Coverage, 5940, |
| 145569 | GIR_EraseRootFromParent_Done, |
| 145570 | // Label 6902: @467188 |
| 145571 | GIM_Try, /*On fail goto*//*Label 6903*/ GIMT_Encode4(467250), // Rule ID 5928 // |
| 145572 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145573 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145574 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145575 | // MIs[0] offset |
| 145576 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145577 | // MIs[0] auxiliary |
| 145578 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145579 | // MIs[0] Operand 8 |
| 145580 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145582 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMIN_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_IDXEN_RTN), |
| 145584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145585 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145586 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145587 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145589 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145592 | GIR_RootConstrainSelectedInstOperands, |
| 145593 | // GIR_Coverage, 5928, |
| 145594 | GIR_EraseRootFromParent_Done, |
| 145595 | // Label 6903: @467250 |
| 145596 | GIM_Try, /*On fail goto*//*Label 6904*/ GIMT_Encode4(467312), // Rule ID 5936 // |
| 145597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145599 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145600 | // MIs[0] offset |
| 145601 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145602 | // MIs[0] auxiliary |
| 145603 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145604 | // MIs[0] Operand 8 |
| 145605 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145607 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_IDXEN_RTN), |
| 145609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145610 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145611 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 145612 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145614 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145615 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145617 | GIR_RootConstrainSelectedInstOperands, |
| 145618 | // GIR_Coverage, 5936, |
| 145619 | GIR_EraseRootFromParent_Done, |
| 145620 | // Label 6904: @467312 |
| 145621 | GIM_Try, /*On fail goto*//*Label 6905*/ GIMT_Encode4(467408), // Rule ID 5934 // |
| 145622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145623 | GIM_CheckHasNoUse, /*MI*/0, |
| 145624 | // MIs[0] offset |
| 145625 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145626 | // MIs[0] auxiliary |
| 145627 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145628 | // MIs[0] Operand 8 |
| 145629 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145631 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145633 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145634 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145635 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145636 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145637 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145638 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145639 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145640 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145641 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN), |
| 145643 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145644 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145645 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145647 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145648 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145650 | GIR_RootConstrainSelectedInstOperands, |
| 145651 | // GIR_Coverage, 5934, |
| 145652 | GIR_EraseRootFromParent_Done, |
| 145653 | // Label 6905: @467408 |
| 145654 | GIM_Try, /*On fail goto*//*Label 6906*/ GIMT_Encode4(467504), // Rule ID 5942 // |
| 145655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145656 | GIM_CheckHasNoUse, /*MI*/0, |
| 145657 | // MIs[0] offset |
| 145658 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145659 | // MIs[0] auxiliary |
| 145660 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145661 | // MIs[0] Operand 8 |
| 145662 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145663 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145664 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145665 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145666 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145667 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145668 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145669 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145670 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145671 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145672 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145673 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145674 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN), |
| 145676 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145677 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145678 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145679 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145680 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145681 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145683 | GIR_RootConstrainSelectedInstOperands, |
| 145684 | // GIR_Coverage, 5942, |
| 145685 | GIR_EraseRootFromParent_Done, |
| 145686 | // Label 6906: @467504 |
| 145687 | GIM_Try, /*On fail goto*//*Label 6907*/ GIMT_Encode4(467604), // Rule ID 5930 // |
| 145688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts_HasUnrestrictedSOffset), |
| 145689 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145690 | // MIs[0] offset |
| 145691 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145692 | // MIs[0] auxiliary |
| 145693 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145694 | // MIs[0] Operand 8 |
| 145695 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145696 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145697 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMIN_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145698 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145699 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145700 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145701 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145702 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145703 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145704 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145705 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145706 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145707 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_BOTHEN_RTN), |
| 145709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145710 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145711 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145712 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145713 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145714 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145715 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145717 | GIR_RootConstrainSelectedInstOperands, |
| 145718 | // GIR_Coverage, 5930, |
| 145719 | GIR_EraseRootFromParent_Done, |
| 145720 | // Label 6907: @467604 |
| 145721 | GIM_Try, /*On fail goto*//*Label 6908*/ GIMT_Encode4(467704), // Rule ID 5938 // |
| 145722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF32GlobalInsts), |
| 145723 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 145724 | // MIs[0] offset |
| 145725 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145726 | // MIs[0] auxiliary |
| 145727 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145728 | // MIs[0] Operand 8 |
| 145729 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 145730 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145731 | // (SIbuffer_atomic_fmin:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145732 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 145733 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 145734 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 145735 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 145736 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 145737 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 145738 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 145739 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 145740 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145741 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 145742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_FMIN_VBUFFER_BOTHEN_RTN), |
| 145743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145744 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145745 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 145746 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145748 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145751 | GIR_RootConstrainSelectedInstOperands, |
| 145752 | // GIR_Coverage, 5938, |
| 145753 | GIR_EraseRootFromParent_Done, |
| 145754 | // Label 6908: @467704 |
| 145755 | GIM_Reject, |
| 145756 | // Label 6892: @467705 |
| 145757 | GIM_Reject, |
| 145758 | // Label 6890: @467706 |
| 145759 | GIM_Try, /*On fail goto*//*Label 6909*/ GIMT_Encode4(470095), |
| 145760 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 145761 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 145762 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 145763 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 145764 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 145765 | GIM_Try, /*On fail goto*//*Label 6910*/ GIMT_Encode4(467794), // Rule ID 5963 // |
| 145766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145767 | GIM_CheckHasNoUse, /*MI*/0, |
| 145768 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145770 | // MIs[0] offset |
| 145771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145772 | // MIs[0] auxiliary |
| 145773 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145774 | // MIs[0] Operand 8 |
| 145775 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145777 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET), |
| 145779 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145780 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145782 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145785 | GIR_RootConstrainSelectedInstOperands, |
| 145786 | // GIR_Coverage, 5963, |
| 145787 | GIR_EraseRootFromParent_Done, |
| 145788 | // Label 6910: @467794 |
| 145789 | GIM_Try, /*On fail goto*//*Label 6911*/ GIMT_Encode4(467862), // Rule ID 5971 // |
| 145790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145791 | GIM_CheckHasNoUse, /*MI*/0, |
| 145792 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145793 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145794 | // MIs[0] offset |
| 145795 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145796 | // MIs[0] auxiliary |
| 145797 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145798 | // MIs[0] Operand 8 |
| 145799 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145801 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET), |
| 145803 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145804 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145806 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145809 | GIR_RootConstrainSelectedInstOperands, |
| 145810 | // GIR_Coverage, 5971, |
| 145811 | GIR_EraseRootFromParent_Done, |
| 145812 | // Label 6911: @467862 |
| 145813 | GIM_Try, /*On fail goto*//*Label 6912*/ GIMT_Encode4(467930), // Rule ID 6043 // |
| 145814 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145815 | GIM_CheckHasNoUse, /*MI*/0, |
| 145816 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145817 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145818 | // MIs[0] offset |
| 145819 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145820 | // MIs[0] auxiliary |
| 145821 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145822 | // MIs[0] Operand 8 |
| 145823 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145824 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145825 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET), |
| 145827 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145828 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145830 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145831 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145832 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145833 | GIR_RootConstrainSelectedInstOperands, |
| 145834 | // GIR_Coverage, 6043, |
| 145835 | GIR_EraseRootFromParent_Done, |
| 145836 | // Label 6912: @467930 |
| 145837 | GIM_Try, /*On fail goto*//*Label 6913*/ GIMT_Encode4(467998), // Rule ID 6051 // |
| 145838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145839 | GIM_CheckHasNoUse, /*MI*/0, |
| 145840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145841 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145842 | // MIs[0] offset |
| 145843 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145844 | // MIs[0] auxiliary |
| 145845 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145846 | // MIs[0] Operand 8 |
| 145847 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145848 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145849 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145850 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET), |
| 145851 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145852 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145854 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145857 | GIR_RootConstrainSelectedInstOperands, |
| 145858 | // GIR_Coverage, 6051, |
| 145859 | GIR_EraseRootFromParent_Done, |
| 145860 | // Label 6913: @467998 |
| 145861 | GIM_Try, /*On fail goto*//*Label 6914*/ GIMT_Encode4(468070), // Rule ID 5959 // |
| 145862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145863 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145864 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145865 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145866 | // MIs[0] offset |
| 145867 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145868 | // MIs[0] auxiliary |
| 145869 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145870 | // MIs[0] Operand 8 |
| 145871 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145873 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN), |
| 145875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145876 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145877 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145879 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145880 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145881 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145882 | GIR_RootConstrainSelectedInstOperands, |
| 145883 | // GIR_Coverage, 5959, |
| 145884 | GIR_EraseRootFromParent_Done, |
| 145885 | // Label 6914: @468070 |
| 145886 | GIM_Try, /*On fail goto*//*Label 6915*/ GIMT_Encode4(468142), // Rule ID 5967 // |
| 145887 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145888 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145889 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145890 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145891 | // MIs[0] offset |
| 145892 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145893 | // MIs[0] auxiliary |
| 145894 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145895 | // MIs[0] Operand 8 |
| 145896 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145897 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145898 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145899 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN), |
| 145900 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145901 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145902 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145903 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145904 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145905 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145906 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145907 | GIR_RootConstrainSelectedInstOperands, |
| 145908 | // GIR_Coverage, 5967, |
| 145909 | GIR_EraseRootFromParent_Done, |
| 145910 | // Label 6915: @468142 |
| 145911 | GIM_Try, /*On fail goto*//*Label 6916*/ GIMT_Encode4(468214), // Rule ID 6039 // |
| 145912 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145913 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145914 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145915 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145916 | // MIs[0] offset |
| 145917 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145918 | // MIs[0] auxiliary |
| 145919 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145920 | // MIs[0] Operand 8 |
| 145921 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145923 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145924 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFSET_RTN), |
| 145925 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145926 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145927 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145929 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145930 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145931 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145932 | GIR_RootConstrainSelectedInstOperands, |
| 145933 | // GIR_Coverage, 6039, |
| 145934 | GIR_EraseRootFromParent_Done, |
| 145935 | // Label 6916: @468214 |
| 145936 | GIM_Try, /*On fail goto*//*Label 6917*/ GIMT_Encode4(468286), // Rule ID 6047 // |
| 145937 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145938 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 145939 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145940 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 145941 | // MIs[0] offset |
| 145942 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145943 | // MIs[0] auxiliary |
| 145944 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145945 | // MIs[0] Operand 8 |
| 145946 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145948 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145949 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFSET_RTN), |
| 145950 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 145951 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145952 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145953 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145954 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145955 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 145956 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145957 | GIR_RootConstrainSelectedInstOperands, |
| 145958 | // GIR_Coverage, 6047, |
| 145959 | GIR_EraseRootFromParent_Done, |
| 145960 | // Label 6917: @468286 |
| 145961 | GIM_Try, /*On fail goto*//*Label 6918*/ GIMT_Encode4(468352), // Rule ID 5965 // |
| 145962 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 145963 | GIM_CheckHasNoUse, /*MI*/0, |
| 145964 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145965 | // MIs[0] offset |
| 145966 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145967 | // MIs[0] auxiliary |
| 145968 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145969 | // MIs[0] Operand 8 |
| 145970 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145971 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145972 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN), |
| 145974 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145975 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 145976 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 145977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 145978 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 145979 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 145980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 145981 | GIR_RootConstrainSelectedInstOperands, |
| 145982 | // GIR_Coverage, 5965, |
| 145983 | GIR_EraseRootFromParent_Done, |
| 145984 | // Label 6918: @468352 |
| 145985 | GIM_Try, /*On fail goto*//*Label 6919*/ GIMT_Encode4(468418), // Rule ID 5973 // |
| 145986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 145987 | GIM_CheckHasNoUse, /*MI*/0, |
| 145988 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 145989 | // MIs[0] offset |
| 145990 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 145991 | // MIs[0] auxiliary |
| 145992 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 145993 | // MIs[0] Operand 8 |
| 145994 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 145995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 145996 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 145997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN), |
| 145998 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 145999 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146000 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146002 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146003 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146004 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146005 | GIR_RootConstrainSelectedInstOperands, |
| 146006 | // GIR_Coverage, 5973, |
| 146007 | GIR_EraseRootFromParent_Done, |
| 146008 | // Label 6919: @468418 |
| 146009 | GIM_Try, /*On fail goto*//*Label 6920*/ GIMT_Encode4(468484), // Rule ID 6045 // |
| 146010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146011 | GIM_CheckHasNoUse, /*MI*/0, |
| 146012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146013 | // MIs[0] offset |
| 146014 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146015 | // MIs[0] auxiliary |
| 146016 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146017 | // MIs[0] Operand 8 |
| 146018 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146020 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN), |
| 146022 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146023 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146024 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146026 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146029 | GIR_RootConstrainSelectedInstOperands, |
| 146030 | // GIR_Coverage, 6045, |
| 146031 | GIR_EraseRootFromParent_Done, |
| 146032 | // Label 6920: @468484 |
| 146033 | GIM_Try, /*On fail goto*//*Label 6921*/ GIMT_Encode4(468550), // Rule ID 6053 // |
| 146034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146035 | GIM_CheckHasNoUse, /*MI*/0, |
| 146036 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146037 | // MIs[0] offset |
| 146038 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146039 | // MIs[0] auxiliary |
| 146040 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146041 | // MIs[0] Operand 8 |
| 146042 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146044 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN), |
| 146046 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146047 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146048 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146050 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146051 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146053 | GIR_RootConstrainSelectedInstOperands, |
| 146054 | // GIR_Coverage, 6053, |
| 146055 | GIR_EraseRootFromParent_Done, |
| 146056 | // Label 6921: @468550 |
| 146057 | GIM_Try, /*On fail goto*//*Label 6922*/ GIMT_Encode4(468620), // Rule ID 5961 // |
| 146058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146059 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146060 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146061 | // MIs[0] offset |
| 146062 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146063 | // MIs[0] auxiliary |
| 146064 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146065 | // MIs[0] Operand 8 |
| 146066 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146068 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN), |
| 146070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146071 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146072 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146073 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146074 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146075 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146076 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146077 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146078 | GIR_RootConstrainSelectedInstOperands, |
| 146079 | // GIR_Coverage, 5961, |
| 146080 | GIR_EraseRootFromParent_Done, |
| 146081 | // Label 6922: @468620 |
| 146082 | GIM_Try, /*On fail goto*//*Label 6923*/ GIMT_Encode4(468690), // Rule ID 5969 // |
| 146083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146084 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146086 | // MIs[0] offset |
| 146087 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146088 | // MIs[0] auxiliary |
| 146089 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146090 | // MIs[0] Operand 8 |
| 146091 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146093 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN), |
| 146095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146096 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146097 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146098 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146100 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146101 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146102 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146103 | GIR_RootConstrainSelectedInstOperands, |
| 146104 | // GIR_Coverage, 5969, |
| 146105 | GIR_EraseRootFromParent_Done, |
| 146106 | // Label 6923: @468690 |
| 146107 | GIM_Try, /*On fail goto*//*Label 6924*/ GIMT_Encode4(468760), // Rule ID 6041 // |
| 146108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146109 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146110 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146111 | // MIs[0] offset |
| 146112 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146113 | // MIs[0] auxiliary |
| 146114 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146115 | // MIs[0] Operand 8 |
| 146116 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146117 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146118 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_OFFEN_RTN), |
| 146120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146121 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146122 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146123 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146125 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146126 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146127 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146128 | GIR_RootConstrainSelectedInstOperands, |
| 146129 | // GIR_Coverage, 6041, |
| 146130 | GIR_EraseRootFromParent_Done, |
| 146131 | // Label 6924: @468760 |
| 146132 | GIM_Try, /*On fail goto*//*Label 6925*/ GIMT_Encode4(468830), // Rule ID 6049 // |
| 146133 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146134 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146135 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146136 | // MIs[0] offset |
| 146137 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146138 | // MIs[0] auxiliary |
| 146139 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146140 | // MIs[0] Operand 8 |
| 146141 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146143 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_OFFEN_RTN), |
| 146145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146146 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146147 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146148 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146150 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146151 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146152 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146153 | GIR_RootConstrainSelectedInstOperands, |
| 146154 | // GIR_Coverage, 6049, |
| 146155 | GIR_EraseRootFromParent_Done, |
| 146156 | // Label 6925: @468830 |
| 146157 | GIM_Try, /*On fail goto*//*Label 6926*/ GIMT_Encode4(468888), // Rule ID 5964 // |
| 146158 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146159 | GIM_CheckHasNoUse, /*MI*/0, |
| 146160 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146161 | // MIs[0] offset |
| 146162 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146163 | // MIs[0] auxiliary |
| 146164 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146165 | // MIs[0] Operand 8 |
| 146166 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146167 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146168 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146169 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN), |
| 146170 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146171 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146172 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146173 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146174 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146175 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146176 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146177 | GIR_RootConstrainSelectedInstOperands, |
| 146178 | // GIR_Coverage, 5964, |
| 146179 | GIR_EraseRootFromParent_Done, |
| 146180 | // Label 6926: @468888 |
| 146181 | GIM_Try, /*On fail goto*//*Label 6927*/ GIMT_Encode4(468946), // Rule ID 5972 // |
| 146182 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146183 | GIM_CheckHasNoUse, /*MI*/0, |
| 146184 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146185 | // MIs[0] offset |
| 146186 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146187 | // MIs[0] auxiliary |
| 146188 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146189 | // MIs[0] Operand 8 |
| 146190 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146191 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146192 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN), |
| 146194 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146195 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146196 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146198 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146199 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146200 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146201 | GIR_RootConstrainSelectedInstOperands, |
| 146202 | // GIR_Coverage, 5972, |
| 146203 | GIR_EraseRootFromParent_Done, |
| 146204 | // Label 6927: @468946 |
| 146205 | GIM_Try, /*On fail goto*//*Label 6928*/ GIMT_Encode4(469004), // Rule ID 6044 // |
| 146206 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146207 | GIM_CheckHasNoUse, /*MI*/0, |
| 146208 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146209 | // MIs[0] offset |
| 146210 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146211 | // MIs[0] auxiliary |
| 146212 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146213 | // MIs[0] Operand 8 |
| 146214 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146215 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146216 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146217 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN), |
| 146218 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146219 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146220 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146221 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146222 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146223 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146224 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146225 | GIR_RootConstrainSelectedInstOperands, |
| 146226 | // GIR_Coverage, 6044, |
| 146227 | GIR_EraseRootFromParent_Done, |
| 146228 | // Label 6928: @469004 |
| 146229 | GIM_Try, /*On fail goto*//*Label 6929*/ GIMT_Encode4(469062), // Rule ID 6052 // |
| 146230 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146231 | GIM_CheckHasNoUse, /*MI*/0, |
| 146232 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146233 | // MIs[0] offset |
| 146234 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146235 | // MIs[0] auxiliary |
| 146236 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146237 | // MIs[0] Operand 8 |
| 146238 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146239 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146240 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN), |
| 146242 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146243 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146244 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146246 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146249 | GIR_RootConstrainSelectedInstOperands, |
| 146250 | // GIR_Coverage, 6052, |
| 146251 | GIR_EraseRootFromParent_Done, |
| 146252 | // Label 6929: @469062 |
| 146253 | GIM_Try, /*On fail goto*//*Label 6930*/ GIMT_Encode4(469124), // Rule ID 5960 // |
| 146254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146256 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146257 | // MIs[0] offset |
| 146258 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146259 | // MIs[0] auxiliary |
| 146260 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146261 | // MIs[0] Operand 8 |
| 146262 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146263 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146264 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN), |
| 146266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146267 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146268 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146269 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146271 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146272 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146274 | GIR_RootConstrainSelectedInstOperands, |
| 146275 | // GIR_Coverage, 5960, |
| 146276 | GIR_EraseRootFromParent_Done, |
| 146277 | // Label 6930: @469124 |
| 146278 | GIM_Try, /*On fail goto*//*Label 6931*/ GIMT_Encode4(469186), // Rule ID 5968 // |
| 146279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146280 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146281 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146282 | // MIs[0] offset |
| 146283 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146284 | // MIs[0] auxiliary |
| 146285 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146286 | // MIs[0] Operand 8 |
| 146287 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146289 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN), |
| 146291 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146292 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146293 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146294 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146296 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146298 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146299 | GIR_RootConstrainSelectedInstOperands, |
| 146300 | // GIR_Coverage, 5968, |
| 146301 | GIR_EraseRootFromParent_Done, |
| 146302 | // Label 6931: @469186 |
| 146303 | GIM_Try, /*On fail goto*//*Label 6932*/ GIMT_Encode4(469248), // Rule ID 6040 // |
| 146304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146306 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146307 | // MIs[0] offset |
| 146308 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146309 | // MIs[0] auxiliary |
| 146310 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146311 | // MIs[0] Operand 8 |
| 146312 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146313 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146314 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_IDXEN_RTN), |
| 146316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146317 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146318 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146319 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146321 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146322 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146323 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146324 | GIR_RootConstrainSelectedInstOperands, |
| 146325 | // GIR_Coverage, 6040, |
| 146326 | GIR_EraseRootFromParent_Done, |
| 146327 | // Label 6932: @469248 |
| 146328 | GIM_Try, /*On fail goto*//*Label 6933*/ GIMT_Encode4(469310), // Rule ID 6048 // |
| 146329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146330 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146332 | // MIs[0] offset |
| 146333 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146334 | // MIs[0] auxiliary |
| 146335 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146336 | // MIs[0] Operand 8 |
| 146337 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146339 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_IDXEN_RTN), |
| 146341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146342 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146343 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146344 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146346 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146349 | GIR_RootConstrainSelectedInstOperands, |
| 146350 | // GIR_Coverage, 6048, |
| 146351 | GIR_EraseRootFromParent_Done, |
| 146352 | // Label 6933: @469310 |
| 146353 | GIM_Try, /*On fail goto*//*Label 6934*/ GIMT_Encode4(469406), // Rule ID 5966 // |
| 146354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146355 | GIM_CheckHasNoUse, /*MI*/0, |
| 146356 | // MIs[0] offset |
| 146357 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146358 | // MIs[0] auxiliary |
| 146359 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146360 | // MIs[0] Operand 8 |
| 146361 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146363 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146364 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146365 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146366 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146367 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146368 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146369 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146370 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146371 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146372 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146373 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN), |
| 146375 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146376 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146377 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146378 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146379 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146380 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146381 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146382 | GIR_RootConstrainSelectedInstOperands, |
| 146383 | // GIR_Coverage, 5966, |
| 146384 | GIR_EraseRootFromParent_Done, |
| 146385 | // Label 6934: @469406 |
| 146386 | GIM_Try, /*On fail goto*//*Label 6935*/ GIMT_Encode4(469502), // Rule ID 5974 // |
| 146387 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146388 | GIM_CheckHasNoUse, /*MI*/0, |
| 146389 | // MIs[0] offset |
| 146390 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146391 | // MIs[0] auxiliary |
| 146392 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146393 | // MIs[0] Operand 8 |
| 146394 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146395 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146396 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146397 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146398 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146399 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146400 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146401 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146402 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146403 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146404 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146405 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146406 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146407 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN), |
| 146408 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146409 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146410 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146411 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146412 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146413 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146414 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146415 | GIR_RootConstrainSelectedInstOperands, |
| 146416 | // GIR_Coverage, 5974, |
| 146417 | GIR_EraseRootFromParent_Done, |
| 146418 | // Label 6935: @469502 |
| 146419 | GIM_Try, /*On fail goto*//*Label 6936*/ GIMT_Encode4(469598), // Rule ID 6046 // |
| 146420 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146421 | GIM_CheckHasNoUse, /*MI*/0, |
| 146422 | // MIs[0] offset |
| 146423 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146424 | // MIs[0] auxiliary |
| 146425 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146426 | // MIs[0] Operand 8 |
| 146427 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146429 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146430 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146431 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146432 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146433 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146434 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146435 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146436 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146437 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146438 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146439 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN), |
| 146441 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146442 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146443 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146445 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146446 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146448 | GIR_RootConstrainSelectedInstOperands, |
| 146449 | // GIR_Coverage, 6046, |
| 146450 | GIR_EraseRootFromParent_Done, |
| 146451 | // Label 6936: @469598 |
| 146452 | GIM_Try, /*On fail goto*//*Label 6937*/ GIMT_Encode4(469694), // Rule ID 6054 // |
| 146453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146454 | GIM_CheckHasNoUse, /*MI*/0, |
| 146455 | // MIs[0] offset |
| 146456 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146457 | // MIs[0] auxiliary |
| 146458 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146459 | // MIs[0] Operand 8 |
| 146460 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146462 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_fmin_noret>> => (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146466 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146467 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146468 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146469 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146470 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146471 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146472 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN), |
| 146474 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146475 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146476 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146478 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146480 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146481 | GIR_RootConstrainSelectedInstOperands, |
| 146482 | // GIR_Coverage, 6054, |
| 146483 | GIR_EraseRootFromParent_Done, |
| 146484 | // Label 6937: @469694 |
| 146485 | GIM_Try, /*On fail goto*//*Label 6938*/ GIMT_Encode4(469794), // Rule ID 5962 // |
| 146486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146487 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146488 | // MIs[0] offset |
| 146489 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146490 | // MIs[0] auxiliary |
| 146491 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146492 | // MIs[0] Operand 8 |
| 146493 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146495 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146496 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146497 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146498 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146499 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146500 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146501 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146502 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146503 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146504 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146505 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN), |
| 146507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146508 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146509 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146510 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146512 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146513 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146514 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146515 | GIR_RootConstrainSelectedInstOperands, |
| 146516 | // GIR_Coverage, 5962, |
| 146517 | GIR_EraseRootFromParent_Done, |
| 146518 | // Label 6938: @469794 |
| 146519 | GIM_Try, /*On fail goto*//*Label 6939*/ GIMT_Encode4(469894), // Rule ID 5970 // |
| 146520 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146521 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146522 | // MIs[0] offset |
| 146523 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146524 | // MIs[0] auxiliary |
| 146525 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146526 | // MIs[0] Operand 8 |
| 146527 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146529 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146530 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146531 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146532 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146533 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146534 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146535 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146536 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146537 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146538 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146539 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN), |
| 146541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146542 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146543 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146544 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146546 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146547 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146549 | GIR_RootConstrainSelectedInstOperands, |
| 146550 | // GIR_Coverage, 5970, |
| 146551 | GIR_EraseRootFromParent_Done, |
| 146552 | // Label 6939: @469894 |
| 146553 | GIM_Try, /*On fail goto*//*Label 6940*/ GIMT_Encode4(469994), // Rule ID 6042 // |
| 146554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts_HasUnrestrictedSOffset), |
| 146555 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146556 | // MIs[0] offset |
| 146557 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146558 | // MIs[0] auxiliary |
| 146559 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146560 | // MIs[0] Operand 8 |
| 146561 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146563 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146564 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146565 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146566 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146567 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146568 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146569 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146570 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146571 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146572 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146573 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146574 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_BOTHEN_RTN), |
| 146575 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146576 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146577 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146578 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146579 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146580 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146581 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146582 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146583 | GIR_RootConstrainSelectedInstOperands, |
| 146584 | // GIR_Coverage, 6042, |
| 146585 | GIR_EraseRootFromParent_Done, |
| 146586 | // Label 6940: @469994 |
| 146587 | GIM_Try, /*On fail goto*//*Label 6941*/ GIMT_Encode4(470094), // Rule ID 6050 // |
| 146588 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasAtomicFMinFMaxF64GlobalInsts), |
| 146589 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 146590 | // MIs[0] offset |
| 146591 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146592 | // MIs[0] auxiliary |
| 146593 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146594 | // MIs[0] Operand 8 |
| 146595 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146596 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146597 | // (SIbuffer_atomic_fmin:{ *:[f64] } f64:{ *:[f64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN:{ *:[f64] } anonymous_15875:{ *:[f64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146598 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146599 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146600 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146601 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146602 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146603 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146604 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146605 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146606 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146607 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146608 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_MIN_F64_VBUFFER_BOTHEN_RTN), |
| 146609 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146610 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146611 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146612 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146614 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146615 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146617 | GIR_RootConstrainSelectedInstOperands, |
| 146618 | // GIR_Coverage, 6050, |
| 146619 | GIR_EraseRootFromParent_Done, |
| 146620 | // Label 6941: @470094 |
| 146621 | GIM_Reject, |
| 146622 | // Label 6909: @470095 |
| 146623 | GIM_Reject, |
| 146624 | // Label 6891: @470096 |
| 146625 | GIM_Reject, |
| 146626 | // Label 116: @470097 |
| 146627 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6944*/ GIMT_Encode4(472480), |
| 146628 | /*GILLT_s32*//*Label 6942*/ GIMT_Encode4(470116), |
| 146629 | /*GILLT_s64*//*Label 6943*/ GIMT_Encode4(471298), |
| 146630 | // Label 6942: @470116 |
| 146631 | GIM_Try, /*On fail goto*//*Label 6945*/ GIMT_Encode4(471297), |
| 146632 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 146633 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 146634 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 146635 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 146636 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 146637 | GIM_Try, /*On fail goto*//*Label 6946*/ GIMT_Encode4(470204), // Rule ID 5667 // |
| 146638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146639 | GIM_CheckHasNoUse, /*MI*/0, |
| 146640 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146641 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146642 | // MIs[0] offset |
| 146643 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146644 | // MIs[0] auxiliary |
| 146645 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146646 | // MIs[0] Operand 8 |
| 146647 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146649 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET), |
| 146651 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146652 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146654 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146655 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146656 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146657 | GIR_RootConstrainSelectedInstOperands, |
| 146658 | // GIR_Coverage, 5667, |
| 146659 | GIR_EraseRootFromParent_Done, |
| 146660 | // Label 6946: @470204 |
| 146661 | GIM_Try, /*On fail goto*//*Label 6947*/ GIMT_Encode4(470269), // Rule ID 5675 // |
| 146662 | GIM_CheckHasNoUse, /*MI*/0, |
| 146663 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146664 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146665 | // MIs[0] offset |
| 146666 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146667 | // MIs[0] auxiliary |
| 146668 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146669 | // MIs[0] Operand 8 |
| 146670 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146671 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146672 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET), |
| 146674 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146675 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146677 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146678 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146679 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146680 | GIR_RootConstrainSelectedInstOperands, |
| 146681 | // GIR_Coverage, 5675, |
| 146682 | GIR_EraseRootFromParent_Done, |
| 146683 | // Label 6947: @470269 |
| 146684 | GIM_Try, /*On fail goto*//*Label 6948*/ GIMT_Encode4(470341), // Rule ID 5663 // |
| 146685 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146686 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146687 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146688 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146689 | // MIs[0] offset |
| 146690 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146691 | // MIs[0] auxiliary |
| 146692 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146693 | // MIs[0] Operand 8 |
| 146694 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146696 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFSET_RTN), |
| 146698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146699 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146700 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146702 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146704 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146705 | GIR_RootConstrainSelectedInstOperands, |
| 146706 | // GIR_Coverage, 5663, |
| 146707 | GIR_EraseRootFromParent_Done, |
| 146708 | // Label 6948: @470341 |
| 146709 | GIM_Try, /*On fail goto*//*Label 6949*/ GIMT_Encode4(470410), // Rule ID 5671 // |
| 146710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146712 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146713 | // MIs[0] offset |
| 146714 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146715 | // MIs[0] auxiliary |
| 146716 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146717 | // MIs[0] Operand 8 |
| 146718 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146719 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146720 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFSET_RTN), |
| 146722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146723 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146724 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146726 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146729 | GIR_RootConstrainSelectedInstOperands, |
| 146730 | // GIR_Coverage, 5671, |
| 146731 | GIR_EraseRootFromParent_Done, |
| 146732 | // Label 6949: @470410 |
| 146733 | GIM_Try, /*On fail goto*//*Label 6950*/ GIMT_Encode4(470476), // Rule ID 5669 // |
| 146734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146735 | GIM_CheckHasNoUse, /*MI*/0, |
| 146736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146737 | // MIs[0] offset |
| 146738 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146739 | // MIs[0] auxiliary |
| 146740 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146741 | // MIs[0] Operand 8 |
| 146742 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146744 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFEN), |
| 146746 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146747 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146748 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146750 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146751 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146753 | GIR_RootConstrainSelectedInstOperands, |
| 146754 | // GIR_Coverage, 5669, |
| 146755 | GIR_EraseRootFromParent_Done, |
| 146756 | // Label 6950: @470476 |
| 146757 | GIM_Try, /*On fail goto*//*Label 6951*/ GIMT_Encode4(470539), // Rule ID 5677 // |
| 146758 | GIM_CheckHasNoUse, /*MI*/0, |
| 146759 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146760 | // MIs[0] offset |
| 146761 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146762 | // MIs[0] auxiliary |
| 146763 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146764 | // MIs[0] Operand 8 |
| 146765 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146767 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN), |
| 146769 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146770 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146771 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146773 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146776 | GIR_RootConstrainSelectedInstOperands, |
| 146777 | // GIR_Coverage, 5677, |
| 146778 | GIR_EraseRootFromParent_Done, |
| 146779 | // Label 6951: @470539 |
| 146780 | GIM_Try, /*On fail goto*//*Label 6952*/ GIMT_Encode4(470609), // Rule ID 5665 // |
| 146781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146782 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146784 | // MIs[0] offset |
| 146785 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146786 | // MIs[0] auxiliary |
| 146787 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146788 | // MIs[0] Operand 8 |
| 146789 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146791 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_OFFEN_RTN), |
| 146793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146794 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146795 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146796 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146798 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146799 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146801 | GIR_RootConstrainSelectedInstOperands, |
| 146802 | // GIR_Coverage, 5665, |
| 146803 | GIR_EraseRootFromParent_Done, |
| 146804 | // Label 6952: @470609 |
| 146805 | GIM_Try, /*On fail goto*//*Label 6953*/ GIMT_Encode4(470676), // Rule ID 5673 // |
| 146806 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146807 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 146808 | // MIs[0] offset |
| 146809 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146810 | // MIs[0] auxiliary |
| 146811 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146812 | // MIs[0] Operand 8 |
| 146813 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 146814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146815 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_OFFEN_RTN), |
| 146817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146818 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146819 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 146820 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146821 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146822 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146823 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146825 | GIR_RootConstrainSelectedInstOperands, |
| 146826 | // GIR_Coverage, 5673, |
| 146827 | GIR_EraseRootFromParent_Done, |
| 146828 | // Label 6953: @470676 |
| 146829 | GIM_Try, /*On fail goto*//*Label 6954*/ GIMT_Encode4(470734), // Rule ID 5668 // |
| 146830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146831 | GIM_CheckHasNoUse, /*MI*/0, |
| 146832 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146833 | // MIs[0] offset |
| 146834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146835 | // MIs[0] auxiliary |
| 146836 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146837 | // MIs[0] Operand 8 |
| 146838 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146839 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146840 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146841 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_IDXEN), |
| 146842 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146843 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146844 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146845 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146846 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146847 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146848 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146849 | GIR_RootConstrainSelectedInstOperands, |
| 146850 | // GIR_Coverage, 5668, |
| 146851 | GIR_EraseRootFromParent_Done, |
| 146852 | // Label 6954: @470734 |
| 146853 | GIM_Try, /*On fail goto*//*Label 6955*/ GIMT_Encode4(470789), // Rule ID 5676 // |
| 146854 | GIM_CheckHasNoUse, /*MI*/0, |
| 146855 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146856 | // MIs[0] offset |
| 146857 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146858 | // MIs[0] auxiliary |
| 146859 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146860 | // MIs[0] Operand 8 |
| 146861 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146862 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146863 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN), |
| 146865 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146866 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146867 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146869 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146870 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146871 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146872 | GIR_RootConstrainSelectedInstOperands, |
| 146873 | // GIR_Coverage, 5676, |
| 146874 | GIR_EraseRootFromParent_Done, |
| 146875 | // Label 6955: @470789 |
| 146876 | GIM_Try, /*On fail goto*//*Label 6956*/ GIMT_Encode4(470851), // Rule ID 5664 // |
| 146877 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146878 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146879 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146880 | // MIs[0] offset |
| 146881 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146882 | // MIs[0] auxiliary |
| 146883 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146884 | // MIs[0] Operand 8 |
| 146885 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146887 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_IDXEN_RTN), |
| 146889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146890 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146891 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146892 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146894 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146895 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146897 | GIR_RootConstrainSelectedInstOperands, |
| 146898 | // GIR_Coverage, 5664, |
| 146899 | GIR_EraseRootFromParent_Done, |
| 146900 | // Label 6956: @470851 |
| 146901 | GIM_Try, /*On fail goto*//*Label 6957*/ GIMT_Encode4(470910), // Rule ID 5672 // |
| 146902 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146903 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 146904 | // MIs[0] offset |
| 146905 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146906 | // MIs[0] auxiliary |
| 146907 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146908 | // MIs[0] Operand 8 |
| 146909 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146910 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146911 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_IDXEN_RTN), |
| 146913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 146914 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146915 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 146916 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146918 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146919 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 146920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146921 | GIR_RootConstrainSelectedInstOperands, |
| 146922 | // GIR_Coverage, 5672, |
| 146923 | GIR_EraseRootFromParent_Done, |
| 146924 | // Label 6957: @470910 |
| 146925 | GIM_Try, /*On fail goto*//*Label 6958*/ GIMT_Encode4(471006), // Rule ID 5670 // |
| 146926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146927 | GIM_CheckHasNoUse, /*MI*/0, |
| 146928 | // MIs[0] offset |
| 146929 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146930 | // MIs[0] auxiliary |
| 146931 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146932 | // MIs[0] Operand 8 |
| 146933 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146935 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146936 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146937 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146938 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146939 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146940 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146941 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146942 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146943 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146944 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146945 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_BOTHEN), |
| 146947 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146948 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146949 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146950 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146951 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146952 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146954 | GIR_RootConstrainSelectedInstOperands, |
| 146955 | // GIR_Coverage, 5670, |
| 146956 | GIR_EraseRootFromParent_Done, |
| 146957 | // Label 6958: @471006 |
| 146958 | GIM_Try, /*On fail goto*//*Label 6959*/ GIMT_Encode4(471099), // Rule ID 5678 // |
| 146959 | GIM_CheckHasNoUse, /*MI*/0, |
| 146960 | // MIs[0] offset |
| 146961 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146962 | // MIs[0] auxiliary |
| 146963 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146964 | // MIs[0] Operand 8 |
| 146965 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 146967 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 146968 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 146969 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 146970 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 146971 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 146972 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 146973 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 146974 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 146975 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 146976 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146977 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 146978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN), |
| 146979 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 146980 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 146981 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 146982 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 146983 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 146984 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 146985 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 146986 | GIR_RootConstrainSelectedInstOperands, |
| 146987 | // GIR_Coverage, 5678, |
| 146988 | GIR_EraseRootFromParent_Done, |
| 146989 | // Label 6959: @471099 |
| 146990 | GIM_Try, /*On fail goto*//*Label 6960*/ GIMT_Encode4(471199), // Rule ID 5666 // |
| 146991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 146992 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 146993 | // MIs[0] offset |
| 146994 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 146995 | // MIs[0] auxiliary |
| 146996 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 146997 | // MIs[0] Operand 8 |
| 146998 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 146999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147000 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147001 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147002 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147003 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147004 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147005 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147006 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147007 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147008 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147009 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147010 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_BOTHEN_RTN), |
| 147012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147013 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147014 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147015 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147017 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147020 | GIR_RootConstrainSelectedInstOperands, |
| 147021 | // GIR_Coverage, 5666, |
| 147022 | GIR_EraseRootFromParent_Done, |
| 147023 | // Label 6960: @471199 |
| 147024 | GIM_Try, /*On fail goto*//*Label 6961*/ GIMT_Encode4(471296), // Rule ID 5674 // |
| 147025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147026 | // MIs[0] offset |
| 147027 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147028 | // MIs[0] auxiliary |
| 147029 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147030 | // MIs[0] Operand 8 |
| 147031 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147032 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147033 | // (SIbuffer_atomic_inc:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147034 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147035 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147036 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147037 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147038 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147039 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147040 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147041 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147042 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147043 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_VBUFFER_BOTHEN_RTN), |
| 147045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147046 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147047 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147048 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147050 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147051 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147053 | GIR_RootConstrainSelectedInstOperands, |
| 147054 | // GIR_Coverage, 5674, |
| 147055 | GIR_EraseRootFromParent_Done, |
| 147056 | // Label 6961: @471296 |
| 147057 | GIM_Reject, |
| 147058 | // Label 6945: @471297 |
| 147059 | GIM_Reject, |
| 147060 | // Label 6943: @471298 |
| 147061 | GIM_Try, /*On fail goto*//*Label 6962*/ GIMT_Encode4(472479), |
| 147062 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 147063 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 147064 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 147065 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 147066 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 147067 | GIM_Try, /*On fail goto*//*Label 6963*/ GIMT_Encode4(471386), // Rule ID 5867 // |
| 147068 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147069 | GIM_CheckHasNoUse, /*MI*/0, |
| 147070 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147071 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147072 | // MIs[0] offset |
| 147073 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147074 | // MIs[0] auxiliary |
| 147075 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147076 | // MIs[0] Operand 8 |
| 147077 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147079 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET), |
| 147081 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147082 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147084 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147085 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147086 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147087 | GIR_RootConstrainSelectedInstOperands, |
| 147088 | // GIR_Coverage, 5867, |
| 147089 | GIR_EraseRootFromParent_Done, |
| 147090 | // Label 6963: @471386 |
| 147091 | GIM_Try, /*On fail goto*//*Label 6964*/ GIMT_Encode4(471451), // Rule ID 5875 // |
| 147092 | GIM_CheckHasNoUse, /*MI*/0, |
| 147093 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147094 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147095 | // MIs[0] offset |
| 147096 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147097 | // MIs[0] auxiliary |
| 147098 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147099 | // MIs[0] Operand 8 |
| 147100 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147102 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET), |
| 147104 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147105 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147107 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147108 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147109 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147110 | GIR_RootConstrainSelectedInstOperands, |
| 147111 | // GIR_Coverage, 5875, |
| 147112 | GIR_EraseRootFromParent_Done, |
| 147113 | // Label 6964: @471451 |
| 147114 | GIM_Try, /*On fail goto*//*Label 6965*/ GIMT_Encode4(471523), // Rule ID 5863 // |
| 147115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147116 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147118 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147119 | // MIs[0] offset |
| 147120 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147121 | // MIs[0] auxiliary |
| 147122 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147123 | // MIs[0] Operand 8 |
| 147124 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147126 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFSET_RTN), |
| 147128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147129 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147130 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147132 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147133 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147134 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147135 | GIR_RootConstrainSelectedInstOperands, |
| 147136 | // GIR_Coverage, 5863, |
| 147137 | GIR_EraseRootFromParent_Done, |
| 147138 | // Label 6965: @471523 |
| 147139 | GIM_Try, /*On fail goto*//*Label 6966*/ GIMT_Encode4(471592), // Rule ID 5871 // |
| 147140 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147142 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147143 | // MIs[0] offset |
| 147144 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147145 | // MIs[0] auxiliary |
| 147146 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147147 | // MIs[0] Operand 8 |
| 147148 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147149 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147150 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147151 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFSET_RTN), |
| 147152 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147153 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147154 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147155 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147156 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147157 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147159 | GIR_RootConstrainSelectedInstOperands, |
| 147160 | // GIR_Coverage, 5871, |
| 147161 | GIR_EraseRootFromParent_Done, |
| 147162 | // Label 6966: @471592 |
| 147163 | GIM_Try, /*On fail goto*//*Label 6967*/ GIMT_Encode4(471658), // Rule ID 5869 // |
| 147164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147165 | GIM_CheckHasNoUse, /*MI*/0, |
| 147166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147167 | // MIs[0] offset |
| 147168 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147169 | // MIs[0] auxiliary |
| 147170 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147171 | // MIs[0] Operand 8 |
| 147172 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147174 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN), |
| 147176 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147177 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147178 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147180 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147183 | GIR_RootConstrainSelectedInstOperands, |
| 147184 | // GIR_Coverage, 5869, |
| 147185 | GIR_EraseRootFromParent_Done, |
| 147186 | // Label 6967: @471658 |
| 147187 | GIM_Try, /*On fail goto*//*Label 6968*/ GIMT_Encode4(471721), // Rule ID 5877 // |
| 147188 | GIM_CheckHasNoUse, /*MI*/0, |
| 147189 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147190 | // MIs[0] offset |
| 147191 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147192 | // MIs[0] auxiliary |
| 147193 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147194 | // MIs[0] Operand 8 |
| 147195 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147197 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN), |
| 147199 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147200 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147201 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147202 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147203 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147204 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147206 | GIR_RootConstrainSelectedInstOperands, |
| 147207 | // GIR_Coverage, 5877, |
| 147208 | GIR_EraseRootFromParent_Done, |
| 147209 | // Label 6968: @471721 |
| 147210 | GIM_Try, /*On fail goto*//*Label 6969*/ GIMT_Encode4(471791), // Rule ID 5865 // |
| 147211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147212 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147213 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147214 | // MIs[0] offset |
| 147215 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147216 | // MIs[0] auxiliary |
| 147217 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147218 | // MIs[0] Operand 8 |
| 147219 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147221 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_OFFEN_RTN), |
| 147223 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147224 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147225 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147226 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147227 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147228 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147229 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147230 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147231 | GIR_RootConstrainSelectedInstOperands, |
| 147232 | // GIR_Coverage, 5865, |
| 147233 | GIR_EraseRootFromParent_Done, |
| 147234 | // Label 6969: @471791 |
| 147235 | GIM_Try, /*On fail goto*//*Label 6970*/ GIMT_Encode4(471858), // Rule ID 5873 // |
| 147236 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147237 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147238 | // MIs[0] offset |
| 147239 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147240 | // MIs[0] auxiliary |
| 147241 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147242 | // MIs[0] Operand 8 |
| 147243 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147245 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_OFFEN_RTN), |
| 147247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147248 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147249 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147250 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147252 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147253 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147255 | GIR_RootConstrainSelectedInstOperands, |
| 147256 | // GIR_Coverage, 5873, |
| 147257 | GIR_EraseRootFromParent_Done, |
| 147258 | // Label 6970: @471858 |
| 147259 | GIM_Try, /*On fail goto*//*Label 6971*/ GIMT_Encode4(471916), // Rule ID 5868 // |
| 147260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147261 | GIM_CheckHasNoUse, /*MI*/0, |
| 147262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147263 | // MIs[0] offset |
| 147264 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147265 | // MIs[0] auxiliary |
| 147266 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147267 | // MIs[0] Operand 8 |
| 147268 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147270 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN), |
| 147272 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147273 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147274 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147276 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147277 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147279 | GIR_RootConstrainSelectedInstOperands, |
| 147280 | // GIR_Coverage, 5868, |
| 147281 | GIR_EraseRootFromParent_Done, |
| 147282 | // Label 6971: @471916 |
| 147283 | GIM_Try, /*On fail goto*//*Label 6972*/ GIMT_Encode4(471971), // Rule ID 5876 // |
| 147284 | GIM_CheckHasNoUse, /*MI*/0, |
| 147285 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147286 | // MIs[0] offset |
| 147287 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147288 | // MIs[0] auxiliary |
| 147289 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147290 | // MIs[0] Operand 8 |
| 147291 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147293 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN), |
| 147295 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147296 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147297 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147299 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147302 | GIR_RootConstrainSelectedInstOperands, |
| 147303 | // GIR_Coverage, 5876, |
| 147304 | GIR_EraseRootFromParent_Done, |
| 147305 | // Label 6972: @471971 |
| 147306 | GIM_Try, /*On fail goto*//*Label 6973*/ GIMT_Encode4(472033), // Rule ID 5864 // |
| 147307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147309 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147310 | // MIs[0] offset |
| 147311 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147312 | // MIs[0] auxiliary |
| 147313 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147314 | // MIs[0] Operand 8 |
| 147315 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147316 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147317 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_IDXEN_RTN), |
| 147319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147320 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147321 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147322 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147324 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147325 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147327 | GIR_RootConstrainSelectedInstOperands, |
| 147328 | // GIR_Coverage, 5864, |
| 147329 | GIR_EraseRootFromParent_Done, |
| 147330 | // Label 6973: @472033 |
| 147331 | GIM_Try, /*On fail goto*//*Label 6974*/ GIMT_Encode4(472092), // Rule ID 5872 // |
| 147332 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147333 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147334 | // MIs[0] offset |
| 147335 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147336 | // MIs[0] auxiliary |
| 147337 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147338 | // MIs[0] Operand 8 |
| 147339 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147341 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_IDXEN_RTN), |
| 147343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147344 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147345 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147346 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147348 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147349 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147351 | GIR_RootConstrainSelectedInstOperands, |
| 147352 | // GIR_Coverage, 5872, |
| 147353 | GIR_EraseRootFromParent_Done, |
| 147354 | // Label 6974: @472092 |
| 147355 | GIM_Try, /*On fail goto*//*Label 6975*/ GIMT_Encode4(472188), // Rule ID 5870 // |
| 147356 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147357 | GIM_CheckHasNoUse, /*MI*/0, |
| 147358 | // MIs[0] offset |
| 147359 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147360 | // MIs[0] auxiliary |
| 147361 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147362 | // MIs[0] Operand 8 |
| 147363 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147365 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147366 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147367 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147368 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147369 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147370 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147371 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147372 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147373 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147374 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147375 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN), |
| 147377 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147378 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147379 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147381 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147383 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147384 | GIR_RootConstrainSelectedInstOperands, |
| 147385 | // GIR_Coverage, 5870, |
| 147386 | GIR_EraseRootFromParent_Done, |
| 147387 | // Label 6975: @472188 |
| 147388 | GIM_Try, /*On fail goto*//*Label 6976*/ GIMT_Encode4(472281), // Rule ID 5878 // |
| 147389 | GIM_CheckHasNoUse, /*MI*/0, |
| 147390 | // MIs[0] offset |
| 147391 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147392 | // MIs[0] auxiliary |
| 147393 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147394 | // MIs[0] Operand 8 |
| 147395 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147397 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_inc_noret>> => (BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147398 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147399 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147400 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147401 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147402 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147403 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147404 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147405 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147406 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147407 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN), |
| 147409 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147410 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147411 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147413 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147414 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147415 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147416 | GIR_RootConstrainSelectedInstOperands, |
| 147417 | // GIR_Coverage, 5878, |
| 147418 | GIR_EraseRootFromParent_Done, |
| 147419 | // Label 6976: @472281 |
| 147420 | GIM_Try, /*On fail goto*//*Label 6977*/ GIMT_Encode4(472381), // Rule ID 5866 // |
| 147421 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147423 | // MIs[0] offset |
| 147424 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147425 | // MIs[0] auxiliary |
| 147426 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147427 | // MIs[0] Operand 8 |
| 147428 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147429 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147430 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147431 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147432 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147433 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147434 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147435 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147436 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147437 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147438 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147439 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147440 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_BOTHEN_RTN), |
| 147442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147443 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147445 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147447 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147448 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147449 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147450 | GIR_RootConstrainSelectedInstOperands, |
| 147451 | // GIR_Coverage, 5866, |
| 147452 | GIR_EraseRootFromParent_Done, |
| 147453 | // Label 6977: @472381 |
| 147454 | GIM_Try, /*On fail goto*//*Label 6978*/ GIMT_Encode4(472478), // Rule ID 5874 // |
| 147455 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147456 | // MIs[0] offset |
| 147457 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147458 | // MIs[0] auxiliary |
| 147459 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147460 | // MIs[0] Operand 8 |
| 147461 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147463 | // (SIbuffer_atomic_inc:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147464 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147465 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147466 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147467 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147468 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147469 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147470 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147471 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147472 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147473 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_INC_X2_VBUFFER_BOTHEN_RTN), |
| 147475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147476 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147477 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147478 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147480 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147481 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147483 | GIR_RootConstrainSelectedInstOperands, |
| 147484 | // GIR_Coverage, 5874, |
| 147485 | GIR_EraseRootFromParent_Done, |
| 147486 | // Label 6978: @472478 |
| 147487 | GIM_Reject, |
| 147488 | // Label 6962: @472479 |
| 147489 | GIM_Reject, |
| 147490 | // Label 6944: @472480 |
| 147491 | GIM_Reject, |
| 147492 | // Label 117: @472481 |
| 147493 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 6981*/ GIMT_Encode4(474864), |
| 147494 | /*GILLT_s32*//*Label 6979*/ GIMT_Encode4(472500), |
| 147495 | /*GILLT_s64*//*Label 6980*/ GIMT_Encode4(473682), |
| 147496 | // Label 6979: @472500 |
| 147497 | GIM_Try, /*On fail goto*//*Label 6982*/ GIMT_Encode4(473681), |
| 147498 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 147499 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 147500 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 147501 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 147502 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 147503 | GIM_Try, /*On fail goto*//*Label 6983*/ GIMT_Encode4(472588), // Rule ID 5635 // |
| 147504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147505 | GIM_CheckHasNoUse, /*MI*/0, |
| 147506 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147507 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147508 | // MIs[0] offset |
| 147509 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147510 | // MIs[0] auxiliary |
| 147511 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147512 | // MIs[0] Operand 8 |
| 147513 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147515 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET), |
| 147517 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147518 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147519 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147520 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147521 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147522 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147523 | GIR_RootConstrainSelectedInstOperands, |
| 147524 | // GIR_Coverage, 5635, |
| 147525 | GIR_EraseRootFromParent_Done, |
| 147526 | // Label 6983: @472588 |
| 147527 | GIM_Try, /*On fail goto*//*Label 6984*/ GIMT_Encode4(472653), // Rule ID 5643 // |
| 147528 | GIM_CheckHasNoUse, /*MI*/0, |
| 147529 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147530 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147531 | // MIs[0] offset |
| 147532 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147533 | // MIs[0] auxiliary |
| 147534 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147535 | // MIs[0] Operand 8 |
| 147536 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147537 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147538 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET), |
| 147540 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147541 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147543 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147546 | GIR_RootConstrainSelectedInstOperands, |
| 147547 | // GIR_Coverage, 5643, |
| 147548 | GIR_EraseRootFromParent_Done, |
| 147549 | // Label 6984: @472653 |
| 147550 | GIM_Try, /*On fail goto*//*Label 6985*/ GIMT_Encode4(472725), // Rule ID 5631 // |
| 147551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147552 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147553 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147555 | // MIs[0] offset |
| 147556 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147557 | // MIs[0] auxiliary |
| 147558 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147559 | // MIs[0] Operand 8 |
| 147560 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147562 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFSET_RTN), |
| 147564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147565 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147566 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147568 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147569 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147570 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147571 | GIR_RootConstrainSelectedInstOperands, |
| 147572 | // GIR_Coverage, 5631, |
| 147573 | GIR_EraseRootFromParent_Done, |
| 147574 | // Label 6985: @472725 |
| 147575 | GIM_Try, /*On fail goto*//*Label 6986*/ GIMT_Encode4(472794), // Rule ID 5639 // |
| 147576 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147577 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147578 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147579 | // MIs[0] offset |
| 147580 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147581 | // MIs[0] auxiliary |
| 147582 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147583 | // MIs[0] Operand 8 |
| 147584 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147586 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFSET_RTN), |
| 147588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147589 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147590 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147592 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147594 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147595 | GIR_RootConstrainSelectedInstOperands, |
| 147596 | // GIR_Coverage, 5639, |
| 147597 | GIR_EraseRootFromParent_Done, |
| 147598 | // Label 6986: @472794 |
| 147599 | GIM_Try, /*On fail goto*//*Label 6987*/ GIMT_Encode4(472860), // Rule ID 5637 // |
| 147600 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147601 | GIM_CheckHasNoUse, /*MI*/0, |
| 147602 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147603 | // MIs[0] offset |
| 147604 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147605 | // MIs[0] auxiliary |
| 147606 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147607 | // MIs[0] Operand 8 |
| 147608 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147609 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147610 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFEN), |
| 147612 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147613 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147614 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147616 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147618 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147619 | GIR_RootConstrainSelectedInstOperands, |
| 147620 | // GIR_Coverage, 5637, |
| 147621 | GIR_EraseRootFromParent_Done, |
| 147622 | // Label 6987: @472860 |
| 147623 | GIM_Try, /*On fail goto*//*Label 6988*/ GIMT_Encode4(472923), // Rule ID 5645 // |
| 147624 | GIM_CheckHasNoUse, /*MI*/0, |
| 147625 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147626 | // MIs[0] offset |
| 147627 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147628 | // MIs[0] auxiliary |
| 147629 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147630 | // MIs[0] Operand 8 |
| 147631 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147633 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN), |
| 147635 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147636 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147637 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147639 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147640 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147641 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147642 | GIR_RootConstrainSelectedInstOperands, |
| 147643 | // GIR_Coverage, 5645, |
| 147644 | GIR_EraseRootFromParent_Done, |
| 147645 | // Label 6988: @472923 |
| 147646 | GIM_Try, /*On fail goto*//*Label 6989*/ GIMT_Encode4(472993), // Rule ID 5633 // |
| 147647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147649 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147650 | // MIs[0] offset |
| 147651 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147652 | // MIs[0] auxiliary |
| 147653 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147654 | // MIs[0] Operand 8 |
| 147655 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147657 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_OFFEN_RTN), |
| 147659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147660 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147661 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147662 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147664 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147665 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147667 | GIR_RootConstrainSelectedInstOperands, |
| 147668 | // GIR_Coverage, 5633, |
| 147669 | GIR_EraseRootFromParent_Done, |
| 147670 | // Label 6989: @472993 |
| 147671 | GIM_Try, /*On fail goto*//*Label 6990*/ GIMT_Encode4(473060), // Rule ID 5641 // |
| 147672 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147673 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147674 | // MIs[0] offset |
| 147675 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147676 | // MIs[0] auxiliary |
| 147677 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147678 | // MIs[0] Operand 8 |
| 147679 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147680 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147681 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_OFFEN_RTN), |
| 147683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147684 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147685 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 147686 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147688 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147689 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147690 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147691 | GIR_RootConstrainSelectedInstOperands, |
| 147692 | // GIR_Coverage, 5641, |
| 147693 | GIR_EraseRootFromParent_Done, |
| 147694 | // Label 6990: @473060 |
| 147695 | GIM_Try, /*On fail goto*//*Label 6991*/ GIMT_Encode4(473118), // Rule ID 5636 // |
| 147696 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147697 | GIM_CheckHasNoUse, /*MI*/0, |
| 147698 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147699 | // MIs[0] offset |
| 147700 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147701 | // MIs[0] auxiliary |
| 147702 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147703 | // MIs[0] Operand 8 |
| 147704 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147706 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_IDXEN), |
| 147708 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147709 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147710 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147712 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147713 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147714 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147715 | GIR_RootConstrainSelectedInstOperands, |
| 147716 | // GIR_Coverage, 5636, |
| 147717 | GIR_EraseRootFromParent_Done, |
| 147718 | // Label 6991: @473118 |
| 147719 | GIM_Try, /*On fail goto*//*Label 6992*/ GIMT_Encode4(473173), // Rule ID 5644 // |
| 147720 | GIM_CheckHasNoUse, /*MI*/0, |
| 147721 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147722 | // MIs[0] offset |
| 147723 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147724 | // MIs[0] auxiliary |
| 147725 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147726 | // MIs[0] Operand 8 |
| 147727 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147728 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147729 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN), |
| 147731 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147732 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147733 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147735 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147736 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147737 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147738 | GIR_RootConstrainSelectedInstOperands, |
| 147739 | // GIR_Coverage, 5644, |
| 147740 | GIR_EraseRootFromParent_Done, |
| 147741 | // Label 6992: @473173 |
| 147742 | GIM_Try, /*On fail goto*//*Label 6993*/ GIMT_Encode4(473235), // Rule ID 5632 // |
| 147743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147744 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147745 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147746 | // MIs[0] offset |
| 147747 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147748 | // MIs[0] auxiliary |
| 147749 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147750 | // MIs[0] Operand 8 |
| 147751 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147752 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147753 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147754 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_IDXEN_RTN), |
| 147755 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147756 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147757 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147758 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147760 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147761 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147762 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147763 | GIR_RootConstrainSelectedInstOperands, |
| 147764 | // GIR_Coverage, 5632, |
| 147765 | GIR_EraseRootFromParent_Done, |
| 147766 | // Label 6993: @473235 |
| 147767 | GIM_Try, /*On fail goto*//*Label 6994*/ GIMT_Encode4(473294), // Rule ID 5640 // |
| 147768 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147770 | // MIs[0] offset |
| 147771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147772 | // MIs[0] auxiliary |
| 147773 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147774 | // MIs[0] Operand 8 |
| 147775 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147776 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147777 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147778 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_IDXEN_RTN), |
| 147779 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147780 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147781 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 147782 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147783 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147784 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147785 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147786 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147787 | GIR_RootConstrainSelectedInstOperands, |
| 147788 | // GIR_Coverage, 5640, |
| 147789 | GIR_EraseRootFromParent_Done, |
| 147790 | // Label 6994: @473294 |
| 147791 | GIM_Try, /*On fail goto*//*Label 6995*/ GIMT_Encode4(473390), // Rule ID 5638 // |
| 147792 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147793 | GIM_CheckHasNoUse, /*MI*/0, |
| 147794 | // MIs[0] offset |
| 147795 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147796 | // MIs[0] auxiliary |
| 147797 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147798 | // MIs[0] Operand 8 |
| 147799 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147801 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147802 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147803 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147804 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147805 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147806 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147807 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147808 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147809 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147810 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147811 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_BOTHEN), |
| 147813 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147814 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147815 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147817 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147818 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147819 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147820 | GIR_RootConstrainSelectedInstOperands, |
| 147821 | // GIR_Coverage, 5638, |
| 147822 | GIR_EraseRootFromParent_Done, |
| 147823 | // Label 6995: @473390 |
| 147824 | GIM_Try, /*On fail goto*//*Label 6996*/ GIMT_Encode4(473483), // Rule ID 5646 // |
| 147825 | GIM_CheckHasNoUse, /*MI*/0, |
| 147826 | // MIs[0] offset |
| 147827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147828 | // MIs[0] auxiliary |
| 147829 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147830 | // MIs[0] Operand 8 |
| 147831 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147832 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147833 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147834 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147835 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147836 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147837 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147838 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147839 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147840 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147841 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147842 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147843 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN), |
| 147845 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147846 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147847 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147848 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147849 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147850 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147851 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147852 | GIR_RootConstrainSelectedInstOperands, |
| 147853 | // GIR_Coverage, 5646, |
| 147854 | GIR_EraseRootFromParent_Done, |
| 147855 | // Label 6996: @473483 |
| 147856 | GIM_Try, /*On fail goto*//*Label 6997*/ GIMT_Encode4(473583), // Rule ID 5634 // |
| 147857 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147858 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147859 | // MIs[0] offset |
| 147860 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147861 | // MIs[0] auxiliary |
| 147862 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147863 | // MIs[0] Operand 8 |
| 147864 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147865 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147866 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147867 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147868 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147869 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147870 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147871 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147872 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147873 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147874 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147875 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147876 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_BOTHEN_RTN), |
| 147878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147879 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147880 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147881 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147882 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147883 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147884 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147885 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147886 | GIR_RootConstrainSelectedInstOperands, |
| 147887 | // GIR_Coverage, 5634, |
| 147888 | GIR_EraseRootFromParent_Done, |
| 147889 | // Label 6997: @473583 |
| 147890 | GIM_Try, /*On fail goto*//*Label 6998*/ GIMT_Encode4(473680), // Rule ID 5642 // |
| 147891 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 147892 | // MIs[0] offset |
| 147893 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147894 | // MIs[0] auxiliary |
| 147895 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147896 | // MIs[0] Operand 8 |
| 147897 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 147898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147899 | // (SIbuffer_atomic_or:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147900 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 147901 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 147902 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 147903 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 147904 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 147905 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 147906 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 147907 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 147908 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147909 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 147910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_VBUFFER_BOTHEN_RTN), |
| 147911 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147912 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147913 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 147914 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147915 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147916 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147917 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 147918 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147919 | GIR_RootConstrainSelectedInstOperands, |
| 147920 | // GIR_Coverage, 5642, |
| 147921 | GIR_EraseRootFromParent_Done, |
| 147922 | // Label 6998: @473680 |
| 147923 | GIM_Reject, |
| 147924 | // Label 6982: @473681 |
| 147925 | GIM_Reject, |
| 147926 | // Label 6980: @473682 |
| 147927 | GIM_Try, /*On fail goto*//*Label 6999*/ GIMT_Encode4(474863), |
| 147928 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 147929 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 147930 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 147931 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 147932 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 147933 | GIM_Try, /*On fail goto*//*Label 7000*/ GIMT_Encode4(473770), // Rule ID 5835 // |
| 147934 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147935 | GIM_CheckHasNoUse, /*MI*/0, |
| 147936 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147937 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147938 | // MIs[0] offset |
| 147939 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147940 | // MIs[0] auxiliary |
| 147941 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147942 | // MIs[0] Operand 8 |
| 147943 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147945 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147946 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET), |
| 147947 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147948 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147949 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147950 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147951 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147952 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147953 | GIR_RootConstrainSelectedInstOperands, |
| 147954 | // GIR_Coverage, 5835, |
| 147955 | GIR_EraseRootFromParent_Done, |
| 147956 | // Label 7000: @473770 |
| 147957 | GIM_Try, /*On fail goto*//*Label 7001*/ GIMT_Encode4(473835), // Rule ID 5843 // |
| 147958 | GIM_CheckHasNoUse, /*MI*/0, |
| 147959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147960 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147961 | // MIs[0] offset |
| 147962 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147963 | // MIs[0] auxiliary |
| 147964 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147965 | // MIs[0] Operand 8 |
| 147966 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147967 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147968 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147969 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET), |
| 147970 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147971 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147973 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147974 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 147975 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 147976 | GIR_RootConstrainSelectedInstOperands, |
| 147977 | // GIR_Coverage, 5843, |
| 147978 | GIR_EraseRootFromParent_Done, |
| 147979 | // Label 7001: @473835 |
| 147980 | GIM_Try, /*On fail goto*//*Label 7002*/ GIMT_Encode4(473907), // Rule ID 5831 // |
| 147981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 147982 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 147983 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 147984 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 147985 | // MIs[0] offset |
| 147986 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 147987 | // MIs[0] auxiliary |
| 147988 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 147989 | // MIs[0] Operand 8 |
| 147990 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 147991 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 147992 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 147993 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFSET_RTN), |
| 147994 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 147995 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 147996 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 147997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 147998 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 147999 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148000 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148001 | GIR_RootConstrainSelectedInstOperands, |
| 148002 | // GIR_Coverage, 5831, |
| 148003 | GIR_EraseRootFromParent_Done, |
| 148004 | // Label 7002: @473907 |
| 148005 | GIM_Try, /*On fail goto*//*Label 7003*/ GIMT_Encode4(473976), // Rule ID 5839 // |
| 148006 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148007 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148008 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148009 | // MIs[0] offset |
| 148010 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148011 | // MIs[0] auxiliary |
| 148012 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148013 | // MIs[0] Operand 8 |
| 148014 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148016 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFSET_RTN), |
| 148018 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148019 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148020 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148021 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148022 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148023 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148024 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148025 | GIR_RootConstrainSelectedInstOperands, |
| 148026 | // GIR_Coverage, 5839, |
| 148027 | GIR_EraseRootFromParent_Done, |
| 148028 | // Label 7003: @473976 |
| 148029 | GIM_Try, /*On fail goto*//*Label 7004*/ GIMT_Encode4(474042), // Rule ID 5837 // |
| 148030 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148031 | GIM_CheckHasNoUse, /*MI*/0, |
| 148032 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148033 | // MIs[0] offset |
| 148034 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148035 | // MIs[0] auxiliary |
| 148036 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148037 | // MIs[0] Operand 8 |
| 148038 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148039 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148040 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148041 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN), |
| 148042 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148043 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148044 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148045 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148046 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148047 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148048 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148049 | GIR_RootConstrainSelectedInstOperands, |
| 148050 | // GIR_Coverage, 5837, |
| 148051 | GIR_EraseRootFromParent_Done, |
| 148052 | // Label 7004: @474042 |
| 148053 | GIM_Try, /*On fail goto*//*Label 7005*/ GIMT_Encode4(474105), // Rule ID 5845 // |
| 148054 | GIM_CheckHasNoUse, /*MI*/0, |
| 148055 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148056 | // MIs[0] offset |
| 148057 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148058 | // MIs[0] auxiliary |
| 148059 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148060 | // MIs[0] Operand 8 |
| 148061 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148062 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148063 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148064 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN), |
| 148065 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148066 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148067 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148069 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148070 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148071 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148072 | GIR_RootConstrainSelectedInstOperands, |
| 148073 | // GIR_Coverage, 5845, |
| 148074 | GIR_EraseRootFromParent_Done, |
| 148075 | // Label 7005: @474105 |
| 148076 | GIM_Try, /*On fail goto*//*Label 7006*/ GIMT_Encode4(474175), // Rule ID 5833 // |
| 148077 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148079 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148080 | // MIs[0] offset |
| 148081 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148082 | // MIs[0] auxiliary |
| 148083 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148084 | // MIs[0] Operand 8 |
| 148085 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148086 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148087 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_OFFEN_RTN), |
| 148089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148090 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148091 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148092 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148094 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148095 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148097 | GIR_RootConstrainSelectedInstOperands, |
| 148098 | // GIR_Coverage, 5833, |
| 148099 | GIR_EraseRootFromParent_Done, |
| 148100 | // Label 7006: @474175 |
| 148101 | GIM_Try, /*On fail goto*//*Label 7007*/ GIMT_Encode4(474242), // Rule ID 5841 // |
| 148102 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148103 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148104 | // MIs[0] offset |
| 148105 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148106 | // MIs[0] auxiliary |
| 148107 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148108 | // MIs[0] Operand 8 |
| 148109 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148110 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148111 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148112 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_OFFEN_RTN), |
| 148113 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148114 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148115 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148116 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148118 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148119 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148121 | GIR_RootConstrainSelectedInstOperands, |
| 148122 | // GIR_Coverage, 5841, |
| 148123 | GIR_EraseRootFromParent_Done, |
| 148124 | // Label 7007: @474242 |
| 148125 | GIM_Try, /*On fail goto*//*Label 7008*/ GIMT_Encode4(474300), // Rule ID 5836 // |
| 148126 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148127 | GIM_CheckHasNoUse, /*MI*/0, |
| 148128 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148129 | // MIs[0] offset |
| 148130 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148131 | // MIs[0] auxiliary |
| 148132 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148133 | // MIs[0] Operand 8 |
| 148134 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148136 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN), |
| 148138 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148139 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148140 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148142 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148143 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148145 | GIR_RootConstrainSelectedInstOperands, |
| 148146 | // GIR_Coverage, 5836, |
| 148147 | GIR_EraseRootFromParent_Done, |
| 148148 | // Label 7008: @474300 |
| 148149 | GIM_Try, /*On fail goto*//*Label 7009*/ GIMT_Encode4(474355), // Rule ID 5844 // |
| 148150 | GIM_CheckHasNoUse, /*MI*/0, |
| 148151 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148152 | // MIs[0] offset |
| 148153 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148154 | // MIs[0] auxiliary |
| 148155 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148156 | // MIs[0] Operand 8 |
| 148157 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148159 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN), |
| 148161 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148162 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148163 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148165 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148166 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148167 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148168 | GIR_RootConstrainSelectedInstOperands, |
| 148169 | // GIR_Coverage, 5844, |
| 148170 | GIR_EraseRootFromParent_Done, |
| 148171 | // Label 7009: @474355 |
| 148172 | GIM_Try, /*On fail goto*//*Label 7010*/ GIMT_Encode4(474417), // Rule ID 5832 // |
| 148173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148176 | // MIs[0] offset |
| 148177 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148178 | // MIs[0] auxiliary |
| 148179 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148180 | // MIs[0] Operand 8 |
| 148181 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148183 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_IDXEN_RTN), |
| 148185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148186 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148187 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148188 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148190 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148191 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148192 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148193 | GIR_RootConstrainSelectedInstOperands, |
| 148194 | // GIR_Coverage, 5832, |
| 148195 | GIR_EraseRootFromParent_Done, |
| 148196 | // Label 7010: @474417 |
| 148197 | GIM_Try, /*On fail goto*//*Label 7011*/ GIMT_Encode4(474476), // Rule ID 5840 // |
| 148198 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148199 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148200 | // MIs[0] offset |
| 148201 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148202 | // MIs[0] auxiliary |
| 148203 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148204 | // MIs[0] Operand 8 |
| 148205 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148207 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_IDXEN_RTN), |
| 148209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148210 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148211 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148212 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148214 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148217 | GIR_RootConstrainSelectedInstOperands, |
| 148218 | // GIR_Coverage, 5840, |
| 148219 | GIR_EraseRootFromParent_Done, |
| 148220 | // Label 7011: @474476 |
| 148221 | GIM_Try, /*On fail goto*//*Label 7012*/ GIMT_Encode4(474572), // Rule ID 5838 // |
| 148222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148223 | GIM_CheckHasNoUse, /*MI*/0, |
| 148224 | // MIs[0] offset |
| 148225 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148226 | // MIs[0] auxiliary |
| 148227 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148228 | // MIs[0] Operand 8 |
| 148229 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148230 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148231 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148232 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148233 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148234 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148235 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148236 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148237 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148238 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148239 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148240 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148241 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148242 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN), |
| 148243 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148244 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148245 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148246 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148247 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148248 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148250 | GIR_RootConstrainSelectedInstOperands, |
| 148251 | // GIR_Coverage, 5838, |
| 148252 | GIR_EraseRootFromParent_Done, |
| 148253 | // Label 7012: @474572 |
| 148254 | GIM_Try, /*On fail goto*//*Label 7013*/ GIMT_Encode4(474665), // Rule ID 5846 // |
| 148255 | GIM_CheckHasNoUse, /*MI*/0, |
| 148256 | // MIs[0] offset |
| 148257 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148258 | // MIs[0] auxiliary |
| 148259 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148260 | // MIs[0] Operand 8 |
| 148261 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148262 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148263 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_or_noret>> => (BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148267 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148268 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148269 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148270 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148271 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148272 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148273 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN), |
| 148275 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148276 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148277 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148279 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148280 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148281 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148282 | GIR_RootConstrainSelectedInstOperands, |
| 148283 | // GIR_Coverage, 5846, |
| 148284 | GIR_EraseRootFromParent_Done, |
| 148285 | // Label 7013: @474665 |
| 148286 | GIM_Try, /*On fail goto*//*Label 7014*/ GIMT_Encode4(474765), // Rule ID 5834 // |
| 148287 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148289 | // MIs[0] offset |
| 148290 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148291 | // MIs[0] auxiliary |
| 148292 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148293 | // MIs[0] Operand 8 |
| 148294 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148296 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148297 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148299 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148300 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148301 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148302 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148303 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148304 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148305 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148306 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_BOTHEN_RTN), |
| 148308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148309 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148310 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148311 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148312 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148313 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148314 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148316 | GIR_RootConstrainSelectedInstOperands, |
| 148317 | // GIR_Coverage, 5834, |
| 148318 | GIR_EraseRootFromParent_Done, |
| 148319 | // Label 7014: @474765 |
| 148320 | GIM_Try, /*On fail goto*//*Label 7015*/ GIMT_Encode4(474862), // Rule ID 5842 // |
| 148321 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148322 | // MIs[0] offset |
| 148323 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148324 | // MIs[0] auxiliary |
| 148325 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148326 | // MIs[0] Operand 8 |
| 148327 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148329 | // (SIbuffer_atomic_or:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148330 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148331 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148332 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148333 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148334 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148336 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148337 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148338 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148339 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_OR_X2_VBUFFER_BOTHEN_RTN), |
| 148341 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148342 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148343 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148344 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148346 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148349 | GIR_RootConstrainSelectedInstOperands, |
| 148350 | // GIR_Coverage, 5842, |
| 148351 | GIR_EraseRootFromParent_Done, |
| 148352 | // Label 7015: @474862 |
| 148353 | GIM_Reject, |
| 148354 | // Label 6999: @474863 |
| 148355 | GIM_Reject, |
| 148356 | // Label 6981: @474864 |
| 148357 | GIM_Reject, |
| 148358 | // Label 118: @474865 |
| 148359 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7018*/ GIMT_Encode4(477248), |
| 148360 | /*GILLT_s32*//*Label 7016*/ GIMT_Encode4(474884), |
| 148361 | /*GILLT_s64*//*Label 7017*/ GIMT_Encode4(476066), |
| 148362 | // Label 7016: @474884 |
| 148363 | GIM_Try, /*On fail goto*//*Label 7019*/ GIMT_Encode4(476065), |
| 148364 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 148365 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 148366 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 148367 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 148368 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 148369 | GIM_Try, /*On fail goto*//*Label 7020*/ GIMT_Encode4(474972), // Rule ID 5587 // |
| 148370 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148371 | GIM_CheckHasNoUse, /*MI*/0, |
| 148372 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148373 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148374 | // MIs[0] offset |
| 148375 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148376 | // MIs[0] auxiliary |
| 148377 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148378 | // MIs[0] Operand 8 |
| 148379 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148381 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148382 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET), |
| 148383 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148384 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148385 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148386 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148387 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148388 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148389 | GIR_RootConstrainSelectedInstOperands, |
| 148390 | // GIR_Coverage, 5587, |
| 148391 | GIR_EraseRootFromParent_Done, |
| 148392 | // Label 7020: @474972 |
| 148393 | GIM_Try, /*On fail goto*//*Label 7021*/ GIMT_Encode4(475037), // Rule ID 5595 // |
| 148394 | GIM_CheckHasNoUse, /*MI*/0, |
| 148395 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148396 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148397 | // MIs[0] offset |
| 148398 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148399 | // MIs[0] auxiliary |
| 148400 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148401 | // MIs[0] Operand 8 |
| 148402 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148403 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148404 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET), |
| 148406 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148407 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148409 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148410 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148411 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148412 | GIR_RootConstrainSelectedInstOperands, |
| 148413 | // GIR_Coverage, 5595, |
| 148414 | GIR_EraseRootFromParent_Done, |
| 148415 | // Label 7021: @475037 |
| 148416 | GIM_Try, /*On fail goto*//*Label 7022*/ GIMT_Encode4(475109), // Rule ID 5583 // |
| 148417 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148418 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148419 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148420 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148421 | // MIs[0] offset |
| 148422 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148423 | // MIs[0] auxiliary |
| 148424 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148425 | // MIs[0] Operand 8 |
| 148426 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148427 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148428 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFSET_RTN), |
| 148430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148431 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148432 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148434 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148435 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148436 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148437 | GIR_RootConstrainSelectedInstOperands, |
| 148438 | // GIR_Coverage, 5583, |
| 148439 | GIR_EraseRootFromParent_Done, |
| 148440 | // Label 7022: @475109 |
| 148441 | GIM_Try, /*On fail goto*//*Label 7023*/ GIMT_Encode4(475178), // Rule ID 5591 // |
| 148442 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148443 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148444 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148445 | // MIs[0] offset |
| 148446 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148447 | // MIs[0] auxiliary |
| 148448 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148449 | // MIs[0] Operand 8 |
| 148450 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148451 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148452 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148453 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFSET_RTN), |
| 148454 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148455 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148456 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148458 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148459 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148460 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148461 | GIR_RootConstrainSelectedInstOperands, |
| 148462 | // GIR_Coverage, 5591, |
| 148463 | GIR_EraseRootFromParent_Done, |
| 148464 | // Label 7023: @475178 |
| 148465 | GIM_Try, /*On fail goto*//*Label 7024*/ GIMT_Encode4(475244), // Rule ID 5589 // |
| 148466 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148467 | GIM_CheckHasNoUse, /*MI*/0, |
| 148468 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148469 | // MIs[0] offset |
| 148470 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148471 | // MIs[0] auxiliary |
| 148472 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148473 | // MIs[0] Operand 8 |
| 148474 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148475 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148476 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN), |
| 148478 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148479 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148480 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148482 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148483 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148485 | GIR_RootConstrainSelectedInstOperands, |
| 148486 | // GIR_Coverage, 5589, |
| 148487 | GIR_EraseRootFromParent_Done, |
| 148488 | // Label 7024: @475244 |
| 148489 | GIM_Try, /*On fail goto*//*Label 7025*/ GIMT_Encode4(475307), // Rule ID 5597 // |
| 148490 | GIM_CheckHasNoUse, /*MI*/0, |
| 148491 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148492 | // MIs[0] offset |
| 148493 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148494 | // MIs[0] auxiliary |
| 148495 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148496 | // MIs[0] Operand 8 |
| 148497 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148498 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148499 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148500 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN), |
| 148501 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148502 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148503 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148504 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148505 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148506 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148507 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148508 | GIR_RootConstrainSelectedInstOperands, |
| 148509 | // GIR_Coverage, 5597, |
| 148510 | GIR_EraseRootFromParent_Done, |
| 148511 | // Label 7025: @475307 |
| 148512 | GIM_Try, /*On fail goto*//*Label 7026*/ GIMT_Encode4(475377), // Rule ID 5585 // |
| 148513 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148514 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148515 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148516 | // MIs[0] offset |
| 148517 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148518 | // MIs[0] auxiliary |
| 148519 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148520 | // MIs[0] Operand 8 |
| 148521 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148523 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_OFFEN_RTN), |
| 148525 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148526 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148527 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148528 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148529 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148530 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148531 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148532 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148533 | GIR_RootConstrainSelectedInstOperands, |
| 148534 | // GIR_Coverage, 5585, |
| 148535 | GIR_EraseRootFromParent_Done, |
| 148536 | // Label 7026: @475377 |
| 148537 | GIM_Try, /*On fail goto*//*Label 7027*/ GIMT_Encode4(475444), // Rule ID 5593 // |
| 148538 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148539 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148540 | // MIs[0] offset |
| 148541 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148542 | // MIs[0] auxiliary |
| 148543 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148544 | // MIs[0] Operand 8 |
| 148545 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148547 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_OFFEN_RTN), |
| 148549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148550 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148551 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148552 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148554 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148555 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148557 | GIR_RootConstrainSelectedInstOperands, |
| 148558 | // GIR_Coverage, 5593, |
| 148559 | GIR_EraseRootFromParent_Done, |
| 148560 | // Label 7027: @475444 |
| 148561 | GIM_Try, /*On fail goto*//*Label 7028*/ GIMT_Encode4(475502), // Rule ID 5588 // |
| 148562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148563 | GIM_CheckHasNoUse, /*MI*/0, |
| 148564 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148565 | // MIs[0] offset |
| 148566 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148567 | // MIs[0] auxiliary |
| 148568 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148569 | // MIs[0] Operand 8 |
| 148570 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148572 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN), |
| 148574 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148575 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148576 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148578 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148579 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148580 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148581 | GIR_RootConstrainSelectedInstOperands, |
| 148582 | // GIR_Coverage, 5588, |
| 148583 | GIR_EraseRootFromParent_Done, |
| 148584 | // Label 7028: @475502 |
| 148585 | GIM_Try, /*On fail goto*//*Label 7029*/ GIMT_Encode4(475557), // Rule ID 5596 // |
| 148586 | GIM_CheckHasNoUse, /*MI*/0, |
| 148587 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148588 | // MIs[0] offset |
| 148589 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148590 | // MIs[0] auxiliary |
| 148591 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148592 | // MIs[0] Operand 8 |
| 148593 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148594 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148595 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN), |
| 148597 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148598 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148599 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148601 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148602 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148604 | GIR_RootConstrainSelectedInstOperands, |
| 148605 | // GIR_Coverage, 5596, |
| 148606 | GIR_EraseRootFromParent_Done, |
| 148607 | // Label 7029: @475557 |
| 148608 | GIM_Try, /*On fail goto*//*Label 7030*/ GIMT_Encode4(475619), // Rule ID 5584 // |
| 148609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148610 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148611 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148612 | // MIs[0] offset |
| 148613 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148614 | // MIs[0] auxiliary |
| 148615 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148616 | // MIs[0] Operand 8 |
| 148617 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148619 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_IDXEN_RTN), |
| 148621 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148622 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148623 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148624 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148625 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148626 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148627 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148629 | GIR_RootConstrainSelectedInstOperands, |
| 148630 | // GIR_Coverage, 5584, |
| 148631 | GIR_EraseRootFromParent_Done, |
| 148632 | // Label 7030: @475619 |
| 148633 | GIM_Try, /*On fail goto*//*Label 7031*/ GIMT_Encode4(475678), // Rule ID 5592 // |
| 148634 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148635 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148636 | // MIs[0] offset |
| 148637 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148638 | // MIs[0] auxiliary |
| 148639 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148640 | // MIs[0] Operand 8 |
| 148641 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148643 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_IDXEN_RTN), |
| 148645 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148646 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148647 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 148648 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148649 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148650 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148651 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148652 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148653 | GIR_RootConstrainSelectedInstOperands, |
| 148654 | // GIR_Coverage, 5592, |
| 148655 | GIR_EraseRootFromParent_Done, |
| 148656 | // Label 7031: @475678 |
| 148657 | GIM_Try, /*On fail goto*//*Label 7032*/ GIMT_Encode4(475774), // Rule ID 5590 // |
| 148658 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148659 | GIM_CheckHasNoUse, /*MI*/0, |
| 148660 | // MIs[0] offset |
| 148661 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148662 | // MIs[0] auxiliary |
| 148663 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148664 | // MIs[0] Operand 8 |
| 148665 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148667 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148671 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148672 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148673 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148674 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148675 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148676 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148677 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN), |
| 148679 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148680 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148681 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148683 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148684 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148685 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148686 | GIR_RootConstrainSelectedInstOperands, |
| 148687 | // GIR_Coverage, 5590, |
| 148688 | GIR_EraseRootFromParent_Done, |
| 148689 | // Label 7032: @475774 |
| 148690 | GIM_Try, /*On fail goto*//*Label 7033*/ GIMT_Encode4(475867), // Rule ID 5598 // |
| 148691 | GIM_CheckHasNoUse, /*MI*/0, |
| 148692 | // MIs[0] offset |
| 148693 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148694 | // MIs[0] auxiliary |
| 148695 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148696 | // MIs[0] Operand 8 |
| 148697 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148698 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148699 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148700 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148701 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148702 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148703 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148704 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148705 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148706 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148707 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148708 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148709 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN), |
| 148711 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148712 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148713 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148714 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148715 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148716 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148717 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148718 | GIR_RootConstrainSelectedInstOperands, |
| 148719 | // GIR_Coverage, 5598, |
| 148720 | GIR_EraseRootFromParent_Done, |
| 148721 | // Label 7033: @475867 |
| 148722 | GIM_Try, /*On fail goto*//*Label 7034*/ GIMT_Encode4(475967), // Rule ID 5586 // |
| 148723 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148724 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148725 | // MIs[0] offset |
| 148726 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148727 | // MIs[0] auxiliary |
| 148728 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148729 | // MIs[0] Operand 8 |
| 148730 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148732 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148733 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148734 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148735 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148736 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148737 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148738 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148739 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148740 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148741 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148742 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_BOTHEN_RTN), |
| 148744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148745 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148746 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148747 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148749 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148750 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148751 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148752 | GIR_RootConstrainSelectedInstOperands, |
| 148753 | // GIR_Coverage, 5586, |
| 148754 | GIR_EraseRootFromParent_Done, |
| 148755 | // Label 7034: @475967 |
| 148756 | GIM_Try, /*On fail goto*//*Label 7035*/ GIMT_Encode4(476064), // Rule ID 5594 // |
| 148757 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 148758 | // MIs[0] offset |
| 148759 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148760 | // MIs[0] auxiliary |
| 148761 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148762 | // MIs[0] Operand 8 |
| 148763 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 148764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148765 | // (SIbuffer_atomic_smax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148766 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 148767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 148768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 148769 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 148770 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 148771 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 148772 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 148773 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 148774 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148775 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 148776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_VBUFFER_BOTHEN_RTN), |
| 148777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148778 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148779 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 148780 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148782 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148785 | GIR_RootConstrainSelectedInstOperands, |
| 148786 | // GIR_Coverage, 5594, |
| 148787 | GIR_EraseRootFromParent_Done, |
| 148788 | // Label 7035: @476064 |
| 148789 | GIM_Reject, |
| 148790 | // Label 7019: @476065 |
| 148791 | GIM_Reject, |
| 148792 | // Label 7017: @476066 |
| 148793 | GIM_Try, /*On fail goto*//*Label 7036*/ GIMT_Encode4(477247), |
| 148794 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 148795 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 148796 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 148797 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 148798 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 148799 | GIM_Try, /*On fail goto*//*Label 7037*/ GIMT_Encode4(476154), // Rule ID 5787 // |
| 148800 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148801 | GIM_CheckHasNoUse, /*MI*/0, |
| 148802 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148803 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148804 | // MIs[0] offset |
| 148805 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148806 | // MIs[0] auxiliary |
| 148807 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148808 | // MIs[0] Operand 8 |
| 148809 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148811 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET), |
| 148813 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148814 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148815 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148816 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148817 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148818 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148819 | GIR_RootConstrainSelectedInstOperands, |
| 148820 | // GIR_Coverage, 5787, |
| 148821 | GIR_EraseRootFromParent_Done, |
| 148822 | // Label 7037: @476154 |
| 148823 | GIM_Try, /*On fail goto*//*Label 7038*/ GIMT_Encode4(476219), // Rule ID 5795 // |
| 148824 | GIM_CheckHasNoUse, /*MI*/0, |
| 148825 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148826 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148827 | // MIs[0] offset |
| 148828 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148829 | // MIs[0] auxiliary |
| 148830 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148831 | // MIs[0] Operand 8 |
| 148832 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148833 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148834 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148835 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET), |
| 148836 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148837 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148838 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148839 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148840 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148842 | GIR_RootConstrainSelectedInstOperands, |
| 148843 | // GIR_Coverage, 5795, |
| 148844 | GIR_EraseRootFromParent_Done, |
| 148845 | // Label 7038: @476219 |
| 148846 | GIM_Try, /*On fail goto*//*Label 7039*/ GIMT_Encode4(476291), // Rule ID 5783 // |
| 148847 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148848 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148849 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148850 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148851 | // MIs[0] offset |
| 148852 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148853 | // MIs[0] auxiliary |
| 148854 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148855 | // MIs[0] Operand 8 |
| 148856 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148857 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148858 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148859 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFSET_RTN), |
| 148860 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148861 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148862 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148864 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148865 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148866 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148867 | GIR_RootConstrainSelectedInstOperands, |
| 148868 | // GIR_Coverage, 5783, |
| 148869 | GIR_EraseRootFromParent_Done, |
| 148870 | // Label 7039: @476291 |
| 148871 | GIM_Try, /*On fail goto*//*Label 7040*/ GIMT_Encode4(476360), // Rule ID 5791 // |
| 148872 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148873 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148874 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148875 | // MIs[0] offset |
| 148876 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148877 | // MIs[0] auxiliary |
| 148878 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148879 | // MIs[0] Operand 8 |
| 148880 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148882 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFSET_RTN), |
| 148884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148885 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148886 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148888 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148891 | GIR_RootConstrainSelectedInstOperands, |
| 148892 | // GIR_Coverage, 5791, |
| 148893 | GIR_EraseRootFromParent_Done, |
| 148894 | // Label 7040: @476360 |
| 148895 | GIM_Try, /*On fail goto*//*Label 7041*/ GIMT_Encode4(476426), // Rule ID 5789 // |
| 148896 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148897 | GIM_CheckHasNoUse, /*MI*/0, |
| 148898 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148899 | // MIs[0] offset |
| 148900 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148901 | // MIs[0] auxiliary |
| 148902 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148903 | // MIs[0] Operand 8 |
| 148904 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148906 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN), |
| 148908 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148909 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148910 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148912 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148913 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148915 | GIR_RootConstrainSelectedInstOperands, |
| 148916 | // GIR_Coverage, 5789, |
| 148917 | GIR_EraseRootFromParent_Done, |
| 148918 | // Label 7041: @476426 |
| 148919 | GIM_Try, /*On fail goto*//*Label 7042*/ GIMT_Encode4(476489), // Rule ID 5797 // |
| 148920 | GIM_CheckHasNoUse, /*MI*/0, |
| 148921 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148922 | // MIs[0] offset |
| 148923 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148924 | // MIs[0] auxiliary |
| 148925 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148926 | // MIs[0] Operand 8 |
| 148927 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148928 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148929 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN), |
| 148931 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148932 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148933 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148935 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148936 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 148937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148938 | GIR_RootConstrainSelectedInstOperands, |
| 148939 | // GIR_Coverage, 5797, |
| 148940 | GIR_EraseRootFromParent_Done, |
| 148941 | // Label 7042: @476489 |
| 148942 | GIM_Try, /*On fail goto*//*Label 7043*/ GIMT_Encode4(476559), // Rule ID 5785 // |
| 148943 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148944 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148945 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148946 | // MIs[0] offset |
| 148947 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148948 | // MIs[0] auxiliary |
| 148949 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148950 | // MIs[0] Operand 8 |
| 148951 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148952 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148953 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_OFFEN_RTN), |
| 148955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148956 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148957 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148958 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148959 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148960 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148963 | GIR_RootConstrainSelectedInstOperands, |
| 148964 | // GIR_Coverage, 5785, |
| 148965 | GIR_EraseRootFromParent_Done, |
| 148966 | // Label 7043: @476559 |
| 148967 | GIM_Try, /*On fail goto*//*Label 7044*/ GIMT_Encode4(476626), // Rule ID 5793 // |
| 148968 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 148969 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 148970 | // MIs[0] offset |
| 148971 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148972 | // MIs[0] auxiliary |
| 148973 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148974 | // MIs[0] Operand 8 |
| 148975 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 148976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 148977 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 148978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_OFFEN_RTN), |
| 148979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 148980 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 148981 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 148982 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 148983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 148984 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 148985 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 148986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 148987 | GIR_RootConstrainSelectedInstOperands, |
| 148988 | // GIR_Coverage, 5793, |
| 148989 | GIR_EraseRootFromParent_Done, |
| 148990 | // Label 7044: @476626 |
| 148991 | GIM_Try, /*On fail goto*//*Label 7045*/ GIMT_Encode4(476684), // Rule ID 5788 // |
| 148992 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 148993 | GIM_CheckHasNoUse, /*MI*/0, |
| 148994 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 148995 | // MIs[0] offset |
| 148996 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 148997 | // MIs[0] auxiliary |
| 148998 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 148999 | // MIs[0] Operand 8 |
| 149000 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149001 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149002 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN), |
| 149004 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149005 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149006 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149007 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149008 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149009 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149011 | GIR_RootConstrainSelectedInstOperands, |
| 149012 | // GIR_Coverage, 5788, |
| 149013 | GIR_EraseRootFromParent_Done, |
| 149014 | // Label 7045: @476684 |
| 149015 | GIM_Try, /*On fail goto*//*Label 7046*/ GIMT_Encode4(476739), // Rule ID 5796 // |
| 149016 | GIM_CheckHasNoUse, /*MI*/0, |
| 149017 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149018 | // MIs[0] offset |
| 149019 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149020 | // MIs[0] auxiliary |
| 149021 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149022 | // MIs[0] Operand 8 |
| 149023 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149024 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149025 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149026 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN), |
| 149027 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149028 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149029 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149031 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149032 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149033 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149034 | GIR_RootConstrainSelectedInstOperands, |
| 149035 | // GIR_Coverage, 5796, |
| 149036 | GIR_EraseRootFromParent_Done, |
| 149037 | // Label 7046: @476739 |
| 149038 | GIM_Try, /*On fail goto*//*Label 7047*/ GIMT_Encode4(476801), // Rule ID 5784 // |
| 149039 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149040 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149041 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149042 | // MIs[0] offset |
| 149043 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149044 | // MIs[0] auxiliary |
| 149045 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149046 | // MIs[0] Operand 8 |
| 149047 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149049 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_IDXEN_RTN), |
| 149051 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149052 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149053 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149054 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149055 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149056 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149057 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149058 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149059 | GIR_RootConstrainSelectedInstOperands, |
| 149060 | // GIR_Coverage, 5784, |
| 149061 | GIR_EraseRootFromParent_Done, |
| 149062 | // Label 7047: @476801 |
| 149063 | GIM_Try, /*On fail goto*//*Label 7048*/ GIMT_Encode4(476860), // Rule ID 5792 // |
| 149064 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149065 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149066 | // MIs[0] offset |
| 149067 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149068 | // MIs[0] auxiliary |
| 149069 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149070 | // MIs[0] Operand 8 |
| 149071 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149073 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_IDXEN_RTN), |
| 149075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149076 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149077 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149078 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149079 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149080 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149081 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149082 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149083 | GIR_RootConstrainSelectedInstOperands, |
| 149084 | // GIR_Coverage, 5792, |
| 149085 | GIR_EraseRootFromParent_Done, |
| 149086 | // Label 7048: @476860 |
| 149087 | GIM_Try, /*On fail goto*//*Label 7049*/ GIMT_Encode4(476956), // Rule ID 5790 // |
| 149088 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149089 | GIM_CheckHasNoUse, /*MI*/0, |
| 149090 | // MIs[0] offset |
| 149091 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149092 | // MIs[0] auxiliary |
| 149093 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149094 | // MIs[0] Operand 8 |
| 149095 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149096 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149097 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149098 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149099 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149100 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149101 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149102 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149103 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149104 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149105 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149106 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149107 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN), |
| 149109 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149110 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149111 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149113 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149114 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149115 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149116 | GIR_RootConstrainSelectedInstOperands, |
| 149117 | // GIR_Coverage, 5790, |
| 149118 | GIR_EraseRootFromParent_Done, |
| 149119 | // Label 7049: @476956 |
| 149120 | GIM_Try, /*On fail goto*//*Label 7050*/ GIMT_Encode4(477049), // Rule ID 5798 // |
| 149121 | GIM_CheckHasNoUse, /*MI*/0, |
| 149122 | // MIs[0] offset |
| 149123 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149124 | // MIs[0] auxiliary |
| 149125 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149126 | // MIs[0] Operand 8 |
| 149127 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149128 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149129 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smax_noret>> => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149130 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149131 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149132 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149133 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149134 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149135 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149136 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149137 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149138 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149139 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN), |
| 149141 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149142 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149143 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149145 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149146 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149148 | GIR_RootConstrainSelectedInstOperands, |
| 149149 | // GIR_Coverage, 5798, |
| 149150 | GIR_EraseRootFromParent_Done, |
| 149151 | // Label 7050: @477049 |
| 149152 | GIM_Try, /*On fail goto*//*Label 7051*/ GIMT_Encode4(477149), // Rule ID 5786 // |
| 149153 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149154 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149155 | // MIs[0] offset |
| 149156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149157 | // MIs[0] auxiliary |
| 149158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149159 | // MIs[0] Operand 8 |
| 149160 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149162 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149163 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149164 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149165 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149167 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149168 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149169 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149171 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_BOTHEN_RTN), |
| 149174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149175 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149177 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149179 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149181 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149182 | GIR_RootConstrainSelectedInstOperands, |
| 149183 | // GIR_Coverage, 5786, |
| 149184 | GIR_EraseRootFromParent_Done, |
| 149185 | // Label 7051: @477149 |
| 149186 | GIM_Try, /*On fail goto*//*Label 7052*/ GIMT_Encode4(477246), // Rule ID 5794 // |
| 149187 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149188 | // MIs[0] offset |
| 149189 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149190 | // MIs[0] auxiliary |
| 149191 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149192 | // MIs[0] Operand 8 |
| 149193 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149195 | // (SIbuffer_atomic_smax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149196 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149197 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149198 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149199 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149200 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149203 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149204 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMAX_X2_VBUFFER_BOTHEN_RTN), |
| 149207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149208 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149209 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149210 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149212 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149215 | GIR_RootConstrainSelectedInstOperands, |
| 149216 | // GIR_Coverage, 5794, |
| 149217 | GIR_EraseRootFromParent_Done, |
| 149218 | // Label 7052: @477246 |
| 149219 | GIM_Reject, |
| 149220 | // Label 7036: @477247 |
| 149221 | GIM_Reject, |
| 149222 | // Label 7018: @477248 |
| 149223 | GIM_Reject, |
| 149224 | // Label 119: @477249 |
| 149225 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7055*/ GIMT_Encode4(479632), |
| 149226 | /*GILLT_s32*//*Label 7053*/ GIMT_Encode4(477268), |
| 149227 | /*GILLT_s64*//*Label 7054*/ GIMT_Encode4(478450), |
| 149228 | // Label 7053: @477268 |
| 149229 | GIM_Try, /*On fail goto*//*Label 7056*/ GIMT_Encode4(478449), |
| 149230 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 149231 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 149232 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 149233 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 149234 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 149235 | GIM_Try, /*On fail goto*//*Label 7057*/ GIMT_Encode4(477356), // Rule ID 5555 // |
| 149236 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149237 | GIM_CheckHasNoUse, /*MI*/0, |
| 149238 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149239 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149240 | // MIs[0] offset |
| 149241 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149242 | // MIs[0] auxiliary |
| 149243 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149244 | // MIs[0] Operand 8 |
| 149245 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149247 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET), |
| 149249 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149250 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149252 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149253 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149255 | GIR_RootConstrainSelectedInstOperands, |
| 149256 | // GIR_Coverage, 5555, |
| 149257 | GIR_EraseRootFromParent_Done, |
| 149258 | // Label 7057: @477356 |
| 149259 | GIM_Try, /*On fail goto*//*Label 7058*/ GIMT_Encode4(477421), // Rule ID 5563 // |
| 149260 | GIM_CheckHasNoUse, /*MI*/0, |
| 149261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149263 | // MIs[0] offset |
| 149264 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149265 | // MIs[0] auxiliary |
| 149266 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149267 | // MIs[0] Operand 8 |
| 149268 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149270 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET), |
| 149272 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149273 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149275 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149278 | GIR_RootConstrainSelectedInstOperands, |
| 149279 | // GIR_Coverage, 5563, |
| 149280 | GIR_EraseRootFromParent_Done, |
| 149281 | // Label 7058: @477421 |
| 149282 | GIM_Try, /*On fail goto*//*Label 7059*/ GIMT_Encode4(477493), // Rule ID 5551 // |
| 149283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149284 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149285 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149286 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149287 | // MIs[0] offset |
| 149288 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149289 | // MIs[0] auxiliary |
| 149290 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149291 | // MIs[0] Operand 8 |
| 149292 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149293 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149294 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFSET_RTN), |
| 149296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149297 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149298 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149300 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149301 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149302 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149303 | GIR_RootConstrainSelectedInstOperands, |
| 149304 | // GIR_Coverage, 5551, |
| 149305 | GIR_EraseRootFromParent_Done, |
| 149306 | // Label 7059: @477493 |
| 149307 | GIM_Try, /*On fail goto*//*Label 7060*/ GIMT_Encode4(477562), // Rule ID 5559 // |
| 149308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149309 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149310 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149311 | // MIs[0] offset |
| 149312 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149313 | // MIs[0] auxiliary |
| 149314 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149315 | // MIs[0] Operand 8 |
| 149316 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149317 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149318 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149319 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFSET_RTN), |
| 149320 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149321 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149322 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149323 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149324 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149325 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149327 | GIR_RootConstrainSelectedInstOperands, |
| 149328 | // GIR_Coverage, 5559, |
| 149329 | GIR_EraseRootFromParent_Done, |
| 149330 | // Label 7060: @477562 |
| 149331 | GIM_Try, /*On fail goto*//*Label 7061*/ GIMT_Encode4(477628), // Rule ID 5557 // |
| 149332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149333 | GIM_CheckHasNoUse, /*MI*/0, |
| 149334 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149335 | // MIs[0] offset |
| 149336 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149337 | // MIs[0] auxiliary |
| 149338 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149339 | // MIs[0] Operand 8 |
| 149340 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149341 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149342 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149343 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN), |
| 149344 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149345 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149346 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149348 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149349 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149351 | GIR_RootConstrainSelectedInstOperands, |
| 149352 | // GIR_Coverage, 5557, |
| 149353 | GIR_EraseRootFromParent_Done, |
| 149354 | // Label 7061: @477628 |
| 149355 | GIM_Try, /*On fail goto*//*Label 7062*/ GIMT_Encode4(477691), // Rule ID 5565 // |
| 149356 | GIM_CheckHasNoUse, /*MI*/0, |
| 149357 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149358 | // MIs[0] offset |
| 149359 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149360 | // MIs[0] auxiliary |
| 149361 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149362 | // MIs[0] Operand 8 |
| 149363 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149364 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149365 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149366 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN), |
| 149367 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149368 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149369 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149370 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149371 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149372 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149374 | GIR_RootConstrainSelectedInstOperands, |
| 149375 | // GIR_Coverage, 5565, |
| 149376 | GIR_EraseRootFromParent_Done, |
| 149377 | // Label 7062: @477691 |
| 149378 | GIM_Try, /*On fail goto*//*Label 7063*/ GIMT_Encode4(477761), // Rule ID 5553 // |
| 149379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149380 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149381 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149382 | // MIs[0] offset |
| 149383 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149384 | // MIs[0] auxiliary |
| 149385 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149386 | // MIs[0] Operand 8 |
| 149387 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149388 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149389 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_OFFEN_RTN), |
| 149391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149392 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149393 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149394 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149395 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149396 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149397 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149399 | GIR_RootConstrainSelectedInstOperands, |
| 149400 | // GIR_Coverage, 5553, |
| 149401 | GIR_EraseRootFromParent_Done, |
| 149402 | // Label 7063: @477761 |
| 149403 | GIM_Try, /*On fail goto*//*Label 7064*/ GIMT_Encode4(477828), // Rule ID 5561 // |
| 149404 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149406 | // MIs[0] offset |
| 149407 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149408 | // MIs[0] auxiliary |
| 149409 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149410 | // MIs[0] Operand 8 |
| 149411 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149412 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149413 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_OFFEN_RTN), |
| 149415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149416 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149417 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149418 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149420 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149421 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149422 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149423 | GIR_RootConstrainSelectedInstOperands, |
| 149424 | // GIR_Coverage, 5561, |
| 149425 | GIR_EraseRootFromParent_Done, |
| 149426 | // Label 7064: @477828 |
| 149427 | GIM_Try, /*On fail goto*//*Label 7065*/ GIMT_Encode4(477886), // Rule ID 5556 // |
| 149428 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149429 | GIM_CheckHasNoUse, /*MI*/0, |
| 149430 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149431 | // MIs[0] offset |
| 149432 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149433 | // MIs[0] auxiliary |
| 149434 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149435 | // MIs[0] Operand 8 |
| 149436 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149438 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN), |
| 149440 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149441 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149442 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149444 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149445 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149447 | GIR_RootConstrainSelectedInstOperands, |
| 149448 | // GIR_Coverage, 5556, |
| 149449 | GIR_EraseRootFromParent_Done, |
| 149450 | // Label 7065: @477886 |
| 149451 | GIM_Try, /*On fail goto*//*Label 7066*/ GIMT_Encode4(477941), // Rule ID 5564 // |
| 149452 | GIM_CheckHasNoUse, /*MI*/0, |
| 149453 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149454 | // MIs[0] offset |
| 149455 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149456 | // MIs[0] auxiliary |
| 149457 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149458 | // MIs[0] Operand 8 |
| 149459 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149460 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149461 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149462 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN), |
| 149463 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149464 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149465 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149467 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149470 | GIR_RootConstrainSelectedInstOperands, |
| 149471 | // GIR_Coverage, 5564, |
| 149472 | GIR_EraseRootFromParent_Done, |
| 149473 | // Label 7066: @477941 |
| 149474 | GIM_Try, /*On fail goto*//*Label 7067*/ GIMT_Encode4(478003), // Rule ID 5552 // |
| 149475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149476 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149477 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149478 | // MIs[0] offset |
| 149479 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149480 | // MIs[0] auxiliary |
| 149481 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149482 | // MIs[0] Operand 8 |
| 149483 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149485 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_IDXEN_RTN), |
| 149487 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149488 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149489 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149490 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149492 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149493 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149494 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149495 | GIR_RootConstrainSelectedInstOperands, |
| 149496 | // GIR_Coverage, 5552, |
| 149497 | GIR_EraseRootFromParent_Done, |
| 149498 | // Label 7067: @478003 |
| 149499 | GIM_Try, /*On fail goto*//*Label 7068*/ GIMT_Encode4(478062), // Rule ID 5560 // |
| 149500 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149501 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149502 | // MIs[0] offset |
| 149503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149504 | // MIs[0] auxiliary |
| 149505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149506 | // MIs[0] Operand 8 |
| 149507 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149509 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_IDXEN_RTN), |
| 149511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149512 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149513 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149514 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149516 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149517 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149518 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149519 | GIR_RootConstrainSelectedInstOperands, |
| 149520 | // GIR_Coverage, 5560, |
| 149521 | GIR_EraseRootFromParent_Done, |
| 149522 | // Label 7068: @478062 |
| 149523 | GIM_Try, /*On fail goto*//*Label 7069*/ GIMT_Encode4(478158), // Rule ID 5558 // |
| 149524 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149525 | GIM_CheckHasNoUse, /*MI*/0, |
| 149526 | // MIs[0] offset |
| 149527 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149528 | // MIs[0] auxiliary |
| 149529 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149530 | // MIs[0] Operand 8 |
| 149531 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149532 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149533 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149534 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149535 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149536 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149537 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149538 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149539 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149540 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149541 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149542 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149543 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN), |
| 149545 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149546 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149547 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149548 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149549 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149550 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149551 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149552 | GIR_RootConstrainSelectedInstOperands, |
| 149553 | // GIR_Coverage, 5558, |
| 149554 | GIR_EraseRootFromParent_Done, |
| 149555 | // Label 7069: @478158 |
| 149556 | GIM_Try, /*On fail goto*//*Label 7070*/ GIMT_Encode4(478251), // Rule ID 5566 // |
| 149557 | GIM_CheckHasNoUse, /*MI*/0, |
| 149558 | // MIs[0] offset |
| 149559 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149560 | // MIs[0] auxiliary |
| 149561 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149562 | // MIs[0] Operand 8 |
| 149563 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149564 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149565 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149566 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149567 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149568 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149569 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149570 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149571 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149572 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149573 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149574 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149575 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN), |
| 149577 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149578 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149579 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149580 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149581 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149582 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149583 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149584 | GIR_RootConstrainSelectedInstOperands, |
| 149585 | // GIR_Coverage, 5566, |
| 149586 | GIR_EraseRootFromParent_Done, |
| 149587 | // Label 7070: @478251 |
| 149588 | GIM_Try, /*On fail goto*//*Label 7071*/ GIMT_Encode4(478351), // Rule ID 5554 // |
| 149589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149590 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149591 | // MIs[0] offset |
| 149592 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149593 | // MIs[0] auxiliary |
| 149594 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149595 | // MIs[0] Operand 8 |
| 149596 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149597 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149598 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149599 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149600 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149601 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149602 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149603 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149604 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149605 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149606 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149607 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149608 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_BOTHEN_RTN), |
| 149610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149611 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149613 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149615 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149616 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149617 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149618 | GIR_RootConstrainSelectedInstOperands, |
| 149619 | // GIR_Coverage, 5554, |
| 149620 | GIR_EraseRootFromParent_Done, |
| 149621 | // Label 7071: @478351 |
| 149622 | GIM_Try, /*On fail goto*//*Label 7072*/ GIMT_Encode4(478448), // Rule ID 5562 // |
| 149623 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 149624 | // MIs[0] offset |
| 149625 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149626 | // MIs[0] auxiliary |
| 149627 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149628 | // MIs[0] Operand 8 |
| 149629 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149630 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149631 | // (SIbuffer_atomic_smin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149632 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149633 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149634 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149635 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149636 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149637 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149638 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149639 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149640 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149641 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_VBUFFER_BOTHEN_RTN), |
| 149643 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149644 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149646 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149648 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149649 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149650 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149651 | GIR_RootConstrainSelectedInstOperands, |
| 149652 | // GIR_Coverage, 5562, |
| 149653 | GIR_EraseRootFromParent_Done, |
| 149654 | // Label 7072: @478448 |
| 149655 | GIM_Reject, |
| 149656 | // Label 7056: @478449 |
| 149657 | GIM_Reject, |
| 149658 | // Label 7054: @478450 |
| 149659 | GIM_Try, /*On fail goto*//*Label 7073*/ GIMT_Encode4(479631), |
| 149660 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 149661 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 149662 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 149663 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 149664 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 149665 | GIM_Try, /*On fail goto*//*Label 7074*/ GIMT_Encode4(478538), // Rule ID 5755 // |
| 149666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149667 | GIM_CheckHasNoUse, /*MI*/0, |
| 149668 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149669 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149670 | // MIs[0] offset |
| 149671 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149672 | // MIs[0] auxiliary |
| 149673 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149674 | // MIs[0] Operand 8 |
| 149675 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149676 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149677 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET), |
| 149679 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149680 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149682 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149683 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149684 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149685 | GIR_RootConstrainSelectedInstOperands, |
| 149686 | // GIR_Coverage, 5755, |
| 149687 | GIR_EraseRootFromParent_Done, |
| 149688 | // Label 7074: @478538 |
| 149689 | GIM_Try, /*On fail goto*//*Label 7075*/ GIMT_Encode4(478603), // Rule ID 5763 // |
| 149690 | GIM_CheckHasNoUse, /*MI*/0, |
| 149691 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149692 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149693 | // MIs[0] offset |
| 149694 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149695 | // MIs[0] auxiliary |
| 149696 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149697 | // MIs[0] Operand 8 |
| 149698 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149699 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149700 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET), |
| 149702 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149703 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149705 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149706 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149707 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149708 | GIR_RootConstrainSelectedInstOperands, |
| 149709 | // GIR_Coverage, 5763, |
| 149710 | GIR_EraseRootFromParent_Done, |
| 149711 | // Label 7075: @478603 |
| 149712 | GIM_Try, /*On fail goto*//*Label 7076*/ GIMT_Encode4(478675), // Rule ID 5751 // |
| 149713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149714 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149715 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149716 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149717 | // MIs[0] offset |
| 149718 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149719 | // MIs[0] auxiliary |
| 149720 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149721 | // MIs[0] Operand 8 |
| 149722 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149723 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149724 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149725 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFSET_RTN), |
| 149726 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149727 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149728 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149730 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149731 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149732 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149733 | GIR_RootConstrainSelectedInstOperands, |
| 149734 | // GIR_Coverage, 5751, |
| 149735 | GIR_EraseRootFromParent_Done, |
| 149736 | // Label 7076: @478675 |
| 149737 | GIM_Try, /*On fail goto*//*Label 7077*/ GIMT_Encode4(478744), // Rule ID 5759 // |
| 149738 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149739 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149740 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149741 | // MIs[0] offset |
| 149742 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149743 | // MIs[0] auxiliary |
| 149744 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149745 | // MIs[0] Operand 8 |
| 149746 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149748 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFSET_RTN), |
| 149750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149751 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149752 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149754 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149755 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149756 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149757 | GIR_RootConstrainSelectedInstOperands, |
| 149758 | // GIR_Coverage, 5759, |
| 149759 | GIR_EraseRootFromParent_Done, |
| 149760 | // Label 7077: @478744 |
| 149761 | GIM_Try, /*On fail goto*//*Label 7078*/ GIMT_Encode4(478810), // Rule ID 5757 // |
| 149762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149763 | GIM_CheckHasNoUse, /*MI*/0, |
| 149764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149765 | // MIs[0] offset |
| 149766 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149767 | // MIs[0] auxiliary |
| 149768 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149769 | // MIs[0] Operand 8 |
| 149770 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149772 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149773 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN), |
| 149774 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149775 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149776 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149778 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149779 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149780 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149781 | GIR_RootConstrainSelectedInstOperands, |
| 149782 | // GIR_Coverage, 5757, |
| 149783 | GIR_EraseRootFromParent_Done, |
| 149784 | // Label 7078: @478810 |
| 149785 | GIM_Try, /*On fail goto*//*Label 7079*/ GIMT_Encode4(478873), // Rule ID 5765 // |
| 149786 | GIM_CheckHasNoUse, /*MI*/0, |
| 149787 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149788 | // MIs[0] offset |
| 149789 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149790 | // MIs[0] auxiliary |
| 149791 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149792 | // MIs[0] Operand 8 |
| 149793 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149795 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN), |
| 149797 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149798 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149799 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149800 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149801 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149802 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149803 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149804 | GIR_RootConstrainSelectedInstOperands, |
| 149805 | // GIR_Coverage, 5765, |
| 149806 | GIR_EraseRootFromParent_Done, |
| 149807 | // Label 7079: @478873 |
| 149808 | GIM_Try, /*On fail goto*//*Label 7080*/ GIMT_Encode4(478943), // Rule ID 5753 // |
| 149809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149810 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149811 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149812 | // MIs[0] offset |
| 149813 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149814 | // MIs[0] auxiliary |
| 149815 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149816 | // MIs[0] Operand 8 |
| 149817 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149818 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149819 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149820 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_OFFEN_RTN), |
| 149821 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149822 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149823 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149824 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149826 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149827 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149828 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149829 | GIR_RootConstrainSelectedInstOperands, |
| 149830 | // GIR_Coverage, 5753, |
| 149831 | GIR_EraseRootFromParent_Done, |
| 149832 | // Label 7080: @478943 |
| 149833 | GIM_Try, /*On fail goto*//*Label 7081*/ GIMT_Encode4(479010), // Rule ID 5761 // |
| 149834 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149835 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 149836 | // MIs[0] offset |
| 149837 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149838 | // MIs[0] auxiliary |
| 149839 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149840 | // MIs[0] Operand 8 |
| 149841 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 149842 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149843 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149844 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_OFFEN_RTN), |
| 149845 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149846 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149847 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 149848 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149850 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149851 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149852 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149853 | GIR_RootConstrainSelectedInstOperands, |
| 149854 | // GIR_Coverage, 5761, |
| 149855 | GIR_EraseRootFromParent_Done, |
| 149856 | // Label 7081: @479010 |
| 149857 | GIM_Try, /*On fail goto*//*Label 7082*/ GIMT_Encode4(479068), // Rule ID 5756 // |
| 149858 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149859 | GIM_CheckHasNoUse, /*MI*/0, |
| 149860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149861 | // MIs[0] offset |
| 149862 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149863 | // MIs[0] auxiliary |
| 149864 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149865 | // MIs[0] Operand 8 |
| 149866 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149868 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN), |
| 149870 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149871 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149872 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149874 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149875 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149877 | GIR_RootConstrainSelectedInstOperands, |
| 149878 | // GIR_Coverage, 5756, |
| 149879 | GIR_EraseRootFromParent_Done, |
| 149880 | // Label 7082: @479068 |
| 149881 | GIM_Try, /*On fail goto*//*Label 7083*/ GIMT_Encode4(479123), // Rule ID 5764 // |
| 149882 | GIM_CheckHasNoUse, /*MI*/0, |
| 149883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149884 | // MIs[0] offset |
| 149885 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149886 | // MIs[0] auxiliary |
| 149887 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149888 | // MIs[0] Operand 8 |
| 149889 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149891 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN), |
| 149893 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149894 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149895 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149897 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149898 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149899 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149900 | GIR_RootConstrainSelectedInstOperands, |
| 149901 | // GIR_Coverage, 5764, |
| 149902 | GIR_EraseRootFromParent_Done, |
| 149903 | // Label 7083: @479123 |
| 149904 | GIM_Try, /*On fail goto*//*Label 7084*/ GIMT_Encode4(479185), // Rule ID 5752 // |
| 149905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149906 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149907 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149908 | // MIs[0] offset |
| 149909 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149910 | // MIs[0] auxiliary |
| 149911 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149912 | // MIs[0] Operand 8 |
| 149913 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149915 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_IDXEN_RTN), |
| 149917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149918 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149919 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149920 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149922 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149923 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149924 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149925 | GIR_RootConstrainSelectedInstOperands, |
| 149926 | // GIR_Coverage, 5752, |
| 149927 | GIR_EraseRootFromParent_Done, |
| 149928 | // Label 7084: @479185 |
| 149929 | GIM_Try, /*On fail goto*//*Label 7085*/ GIMT_Encode4(479244), // Rule ID 5760 // |
| 149930 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 149931 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 149932 | // MIs[0] offset |
| 149933 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149934 | // MIs[0] auxiliary |
| 149935 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149936 | // MIs[0] Operand 8 |
| 149937 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149938 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149939 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149940 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_IDXEN_RTN), |
| 149941 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 149942 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149943 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 149944 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149946 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149947 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 149948 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149949 | GIR_RootConstrainSelectedInstOperands, |
| 149950 | // GIR_Coverage, 5760, |
| 149951 | GIR_EraseRootFromParent_Done, |
| 149952 | // Label 7085: @479244 |
| 149953 | GIM_Try, /*On fail goto*//*Label 7086*/ GIMT_Encode4(479340), // Rule ID 5758 // |
| 149954 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 149955 | GIM_CheckHasNoUse, /*MI*/0, |
| 149956 | // MIs[0] offset |
| 149957 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149958 | // MIs[0] auxiliary |
| 149959 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149960 | // MIs[0] Operand 8 |
| 149961 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149963 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149964 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149965 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149966 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149967 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 149968 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 149969 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 149970 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 149971 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 149972 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149973 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 149974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN), |
| 149975 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 149976 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 149977 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 149978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 149979 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 149980 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 149981 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 149982 | GIR_RootConstrainSelectedInstOperands, |
| 149983 | // GIR_Coverage, 5758, |
| 149984 | GIR_EraseRootFromParent_Done, |
| 149985 | // Label 7086: @479340 |
| 149986 | GIM_Try, /*On fail goto*//*Label 7087*/ GIMT_Encode4(479433), // Rule ID 5766 // |
| 149987 | GIM_CheckHasNoUse, /*MI*/0, |
| 149988 | // MIs[0] offset |
| 149989 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 149990 | // MIs[0] auxiliary |
| 149991 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 149992 | // MIs[0] Operand 8 |
| 149993 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 149994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 149995 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_smin_noret>> => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 149996 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 149997 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 149998 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 149999 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150000 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150002 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150003 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150004 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN), |
| 150007 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150008 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150009 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150011 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150012 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150013 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150014 | GIR_RootConstrainSelectedInstOperands, |
| 150015 | // GIR_Coverage, 5766, |
| 150016 | GIR_EraseRootFromParent_Done, |
| 150017 | // Label 7087: @479433 |
| 150018 | GIM_Try, /*On fail goto*//*Label 7088*/ GIMT_Encode4(479533), // Rule ID 5754 // |
| 150019 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150020 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150021 | // MIs[0] offset |
| 150022 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150023 | // MIs[0] auxiliary |
| 150024 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150025 | // MIs[0] Operand 8 |
| 150026 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150028 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150029 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150030 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150031 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150032 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150033 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150035 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150036 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150037 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150038 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_BOTHEN_RTN), |
| 150040 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150041 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150042 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150043 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150045 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150046 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150048 | GIR_RootConstrainSelectedInstOperands, |
| 150049 | // GIR_Coverage, 5754, |
| 150050 | GIR_EraseRootFromParent_Done, |
| 150051 | // Label 7088: @479533 |
| 150052 | GIM_Try, /*On fail goto*//*Label 7089*/ GIMT_Encode4(479630), // Rule ID 5762 // |
| 150053 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150054 | // MIs[0] offset |
| 150055 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150056 | // MIs[0] auxiliary |
| 150057 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150058 | // MIs[0] Operand 8 |
| 150059 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150060 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150061 | // (SIbuffer_atomic_smin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150062 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150063 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150064 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150065 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150066 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150067 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150068 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150069 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150070 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150071 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SMIN_X2_VBUFFER_BOTHEN_RTN), |
| 150073 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150074 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150075 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150076 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150077 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150078 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150079 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150081 | GIR_RootConstrainSelectedInstOperands, |
| 150082 | // GIR_Coverage, 5762, |
| 150083 | GIR_EraseRootFromParent_Done, |
| 150084 | // Label 7089: @479630 |
| 150085 | GIM_Reject, |
| 150086 | // Label 7073: @479631 |
| 150087 | GIM_Reject, |
| 150088 | // Label 7055: @479632 |
| 150089 | GIM_Reject, |
| 150090 | // Label 120: @479633 |
| 150091 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7092*/ GIMT_Encode4(482016), |
| 150092 | /*GILLT_s32*//*Label 7090*/ GIMT_Encode4(479652), |
| 150093 | /*GILLT_s64*//*Label 7091*/ GIMT_Encode4(480834), |
| 150094 | // Label 7090: @479652 |
| 150095 | GIM_Try, /*On fail goto*//*Label 7093*/ GIMT_Encode4(480833), |
| 150096 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 150097 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 150098 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 150099 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 150100 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 150101 | GIM_Try, /*On fail goto*//*Label 7094*/ GIMT_Encode4(479740), // Rule ID 5539 // |
| 150102 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150103 | GIM_CheckHasNoUse, /*MI*/0, |
| 150104 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150105 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150106 | // MIs[0] offset |
| 150107 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150108 | // MIs[0] auxiliary |
| 150109 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150110 | // MIs[0] Operand 8 |
| 150111 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150112 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150113 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET), |
| 150115 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150116 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150118 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150119 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150120 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150121 | GIR_RootConstrainSelectedInstOperands, |
| 150122 | // GIR_Coverage, 5539, |
| 150123 | GIR_EraseRootFromParent_Done, |
| 150124 | // Label 7094: @479740 |
| 150125 | GIM_Try, /*On fail goto*//*Label 7095*/ GIMT_Encode4(479805), // Rule ID 5547 // |
| 150126 | GIM_CheckHasNoUse, /*MI*/0, |
| 150127 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150128 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150129 | // MIs[0] offset |
| 150130 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150131 | // MIs[0] auxiliary |
| 150132 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150133 | // MIs[0] Operand 8 |
| 150134 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150136 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET), |
| 150138 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150139 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150140 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150141 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150142 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150143 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150144 | GIR_RootConstrainSelectedInstOperands, |
| 150145 | // GIR_Coverage, 5547, |
| 150146 | GIR_EraseRootFromParent_Done, |
| 150147 | // Label 7095: @479805 |
| 150148 | GIM_Try, /*On fail goto*//*Label 7096*/ GIMT_Encode4(479877), // Rule ID 5535 // |
| 150149 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150150 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150151 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150152 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150153 | // MIs[0] offset |
| 150154 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150155 | // MIs[0] auxiliary |
| 150156 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150157 | // MIs[0] Operand 8 |
| 150158 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150160 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150161 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFSET_RTN), |
| 150162 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150163 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150164 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150165 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150166 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150167 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150169 | GIR_RootConstrainSelectedInstOperands, |
| 150170 | // GIR_Coverage, 5535, |
| 150171 | GIR_EraseRootFromParent_Done, |
| 150172 | // Label 7096: @479877 |
| 150173 | GIM_Try, /*On fail goto*//*Label 7097*/ GIMT_Encode4(479946), // Rule ID 5543 // |
| 150174 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150176 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150177 | // MIs[0] offset |
| 150178 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150179 | // MIs[0] auxiliary |
| 150180 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150181 | // MIs[0] Operand 8 |
| 150182 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150183 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150184 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150185 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFSET_RTN), |
| 150186 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150187 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150188 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150190 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150191 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150192 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150193 | GIR_RootConstrainSelectedInstOperands, |
| 150194 | // GIR_Coverage, 5543, |
| 150195 | GIR_EraseRootFromParent_Done, |
| 150196 | // Label 7097: @479946 |
| 150197 | GIM_Try, /*On fail goto*//*Label 7098*/ GIMT_Encode4(480012), // Rule ID 5541 // |
| 150198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150199 | GIM_CheckHasNoUse, /*MI*/0, |
| 150200 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150201 | // MIs[0] offset |
| 150202 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150203 | // MIs[0] auxiliary |
| 150204 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150205 | // MIs[0] Operand 8 |
| 150206 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150208 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFEN), |
| 150210 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150211 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150212 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150214 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150217 | GIR_RootConstrainSelectedInstOperands, |
| 150218 | // GIR_Coverage, 5541, |
| 150219 | GIR_EraseRootFromParent_Done, |
| 150220 | // Label 7098: @480012 |
| 150221 | GIM_Try, /*On fail goto*//*Label 7099*/ GIMT_Encode4(480075), // Rule ID 5549 // |
| 150222 | GIM_CheckHasNoUse, /*MI*/0, |
| 150223 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150224 | // MIs[0] offset |
| 150225 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150226 | // MIs[0] auxiliary |
| 150227 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150228 | // MIs[0] Operand 8 |
| 150229 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150230 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150231 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150232 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN), |
| 150233 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150234 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150235 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150236 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150237 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150238 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150239 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150240 | GIR_RootConstrainSelectedInstOperands, |
| 150241 | // GIR_Coverage, 5549, |
| 150242 | GIR_EraseRootFromParent_Done, |
| 150243 | // Label 7099: @480075 |
| 150244 | GIM_Try, /*On fail goto*//*Label 7100*/ GIMT_Encode4(480145), // Rule ID 5537 // |
| 150245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150246 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150247 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150248 | // MIs[0] offset |
| 150249 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150250 | // MIs[0] auxiliary |
| 150251 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150252 | // MIs[0] Operand 8 |
| 150253 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150254 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150255 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150256 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_OFFEN_RTN), |
| 150257 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150258 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150259 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150260 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150262 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150263 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150264 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150265 | GIR_RootConstrainSelectedInstOperands, |
| 150266 | // GIR_Coverage, 5537, |
| 150267 | GIR_EraseRootFromParent_Done, |
| 150268 | // Label 7100: @480145 |
| 150269 | GIM_Try, /*On fail goto*//*Label 7101*/ GIMT_Encode4(480212), // Rule ID 5545 // |
| 150270 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150271 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150272 | // MIs[0] offset |
| 150273 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150274 | // MIs[0] auxiliary |
| 150275 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150276 | // MIs[0] Operand 8 |
| 150277 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150279 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_OFFEN_RTN), |
| 150281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150282 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150283 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150284 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150286 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150287 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150289 | GIR_RootConstrainSelectedInstOperands, |
| 150290 | // GIR_Coverage, 5545, |
| 150291 | GIR_EraseRootFromParent_Done, |
| 150292 | // Label 7101: @480212 |
| 150293 | GIM_Try, /*On fail goto*//*Label 7102*/ GIMT_Encode4(480270), // Rule ID 5540 // |
| 150294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150295 | GIM_CheckHasNoUse, /*MI*/0, |
| 150296 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150297 | // MIs[0] offset |
| 150298 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150299 | // MIs[0] auxiliary |
| 150300 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150301 | // MIs[0] Operand 8 |
| 150302 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150303 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150304 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150305 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_IDXEN), |
| 150306 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150307 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150308 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150309 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150310 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150311 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150313 | GIR_RootConstrainSelectedInstOperands, |
| 150314 | // GIR_Coverage, 5540, |
| 150315 | GIR_EraseRootFromParent_Done, |
| 150316 | // Label 7102: @480270 |
| 150317 | GIM_Try, /*On fail goto*//*Label 7103*/ GIMT_Encode4(480325), // Rule ID 5548 // |
| 150318 | GIM_CheckHasNoUse, /*MI*/0, |
| 150319 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150320 | // MIs[0] offset |
| 150321 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150322 | // MIs[0] auxiliary |
| 150323 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150324 | // MIs[0] Operand 8 |
| 150325 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150326 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150327 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150328 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN), |
| 150329 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150330 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150331 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150332 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150333 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150334 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150335 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150336 | GIR_RootConstrainSelectedInstOperands, |
| 150337 | // GIR_Coverage, 5548, |
| 150338 | GIR_EraseRootFromParent_Done, |
| 150339 | // Label 7103: @480325 |
| 150340 | GIM_Try, /*On fail goto*//*Label 7104*/ GIMT_Encode4(480387), // Rule ID 5536 // |
| 150341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150342 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150343 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150344 | // MIs[0] offset |
| 150345 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150346 | // MIs[0] auxiliary |
| 150347 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150348 | // MIs[0] Operand 8 |
| 150349 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150350 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150351 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_IDXEN_RTN), |
| 150353 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150354 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150355 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150356 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150358 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150360 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150361 | GIR_RootConstrainSelectedInstOperands, |
| 150362 | // GIR_Coverage, 5536, |
| 150363 | GIR_EraseRootFromParent_Done, |
| 150364 | // Label 7104: @480387 |
| 150365 | GIM_Try, /*On fail goto*//*Label 7105*/ GIMT_Encode4(480446), // Rule ID 5544 // |
| 150366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150367 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150368 | // MIs[0] offset |
| 150369 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150370 | // MIs[0] auxiliary |
| 150371 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150372 | // MIs[0] Operand 8 |
| 150373 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150374 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150375 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_IDXEN_RTN), |
| 150377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150378 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150379 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150380 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150382 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150385 | GIR_RootConstrainSelectedInstOperands, |
| 150386 | // GIR_Coverage, 5544, |
| 150387 | GIR_EraseRootFromParent_Done, |
| 150388 | // Label 7105: @480446 |
| 150389 | GIM_Try, /*On fail goto*//*Label 7106*/ GIMT_Encode4(480542), // Rule ID 5542 // |
| 150390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150391 | GIM_CheckHasNoUse, /*MI*/0, |
| 150392 | // MIs[0] offset |
| 150393 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150394 | // MIs[0] auxiliary |
| 150395 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150396 | // MIs[0] Operand 8 |
| 150397 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150399 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150400 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150401 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150402 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150403 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150404 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150405 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150406 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150407 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150408 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150409 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN), |
| 150411 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150412 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150413 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150415 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150418 | GIR_RootConstrainSelectedInstOperands, |
| 150419 | // GIR_Coverage, 5542, |
| 150420 | GIR_EraseRootFromParent_Done, |
| 150421 | // Label 7106: @480542 |
| 150422 | GIM_Try, /*On fail goto*//*Label 7107*/ GIMT_Encode4(480635), // Rule ID 5550 // |
| 150423 | GIM_CheckHasNoUse, /*MI*/0, |
| 150424 | // MIs[0] offset |
| 150425 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150426 | // MIs[0] auxiliary |
| 150427 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150428 | // MIs[0] Operand 8 |
| 150429 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150430 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150431 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150432 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150433 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150434 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150435 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150436 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150437 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150438 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150439 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150440 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150441 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN), |
| 150443 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150444 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150445 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150447 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150448 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150449 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150450 | GIR_RootConstrainSelectedInstOperands, |
| 150451 | // GIR_Coverage, 5550, |
| 150452 | GIR_EraseRootFromParent_Done, |
| 150453 | // Label 7107: @480635 |
| 150454 | GIM_Try, /*On fail goto*//*Label 7108*/ GIMT_Encode4(480735), // Rule ID 5538 // |
| 150455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150456 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150457 | // MIs[0] offset |
| 150458 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150459 | // MIs[0] auxiliary |
| 150460 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150461 | // MIs[0] Operand 8 |
| 150462 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150464 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150465 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150466 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150467 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150468 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150469 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150470 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150471 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150472 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150473 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150474 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_BOTHEN_RTN), |
| 150476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150477 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150479 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150481 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150482 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150483 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150484 | GIR_RootConstrainSelectedInstOperands, |
| 150485 | // GIR_Coverage, 5538, |
| 150486 | GIR_EraseRootFromParent_Done, |
| 150487 | // Label 7108: @480735 |
| 150488 | GIM_Try, /*On fail goto*//*Label 7109*/ GIMT_Encode4(480832), // Rule ID 5546 // |
| 150489 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 150490 | // MIs[0] offset |
| 150491 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150492 | // MIs[0] auxiliary |
| 150493 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150494 | // MIs[0] Operand 8 |
| 150495 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150497 | // (SIbuffer_atomic_sub:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150501 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150502 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150503 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150504 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150505 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150506 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150507 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_VBUFFER_BOTHEN_RTN), |
| 150509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150510 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150511 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150512 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150514 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150515 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150517 | GIR_RootConstrainSelectedInstOperands, |
| 150518 | // GIR_Coverage, 5546, |
| 150519 | GIR_EraseRootFromParent_Done, |
| 150520 | // Label 7109: @480832 |
| 150521 | GIM_Reject, |
| 150522 | // Label 7093: @480833 |
| 150523 | GIM_Reject, |
| 150524 | // Label 7091: @480834 |
| 150525 | GIM_Try, /*On fail goto*//*Label 7110*/ GIMT_Encode4(482015), |
| 150526 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 150527 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 150528 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 150529 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 150530 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 150531 | GIM_Try, /*On fail goto*//*Label 7111*/ GIMT_Encode4(480922), // Rule ID 5739 // |
| 150532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150533 | GIM_CheckHasNoUse, /*MI*/0, |
| 150534 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150535 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150536 | // MIs[0] offset |
| 150537 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150538 | // MIs[0] auxiliary |
| 150539 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150540 | // MIs[0] Operand 8 |
| 150541 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150542 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150543 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150544 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET), |
| 150545 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150546 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150548 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150549 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150550 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150551 | GIR_RootConstrainSelectedInstOperands, |
| 150552 | // GIR_Coverage, 5739, |
| 150553 | GIR_EraseRootFromParent_Done, |
| 150554 | // Label 7111: @480922 |
| 150555 | GIM_Try, /*On fail goto*//*Label 7112*/ GIMT_Encode4(480987), // Rule ID 5747 // |
| 150556 | GIM_CheckHasNoUse, /*MI*/0, |
| 150557 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150558 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150559 | // MIs[0] offset |
| 150560 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150561 | // MIs[0] auxiliary |
| 150562 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150563 | // MIs[0] Operand 8 |
| 150564 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150565 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150566 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET), |
| 150568 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150569 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150571 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150574 | GIR_RootConstrainSelectedInstOperands, |
| 150575 | // GIR_Coverage, 5747, |
| 150576 | GIR_EraseRootFromParent_Done, |
| 150577 | // Label 7112: @480987 |
| 150578 | GIM_Try, /*On fail goto*//*Label 7113*/ GIMT_Encode4(481059), // Rule ID 5735 // |
| 150579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150580 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150581 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150583 | // MIs[0] offset |
| 150584 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150585 | // MIs[0] auxiliary |
| 150586 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150587 | // MIs[0] Operand 8 |
| 150588 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150590 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFSET_RTN), |
| 150592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150593 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150594 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150596 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150597 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150598 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150599 | GIR_RootConstrainSelectedInstOperands, |
| 150600 | // GIR_Coverage, 5735, |
| 150601 | GIR_EraseRootFromParent_Done, |
| 150602 | // Label 7113: @481059 |
| 150603 | GIM_Try, /*On fail goto*//*Label 7114*/ GIMT_Encode4(481128), // Rule ID 5743 // |
| 150604 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150605 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150606 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150607 | // MIs[0] offset |
| 150608 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150609 | // MIs[0] auxiliary |
| 150610 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150611 | // MIs[0] Operand 8 |
| 150612 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150614 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150615 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFSET_RTN), |
| 150616 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150617 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150618 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150620 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150621 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150623 | GIR_RootConstrainSelectedInstOperands, |
| 150624 | // GIR_Coverage, 5743, |
| 150625 | GIR_EraseRootFromParent_Done, |
| 150626 | // Label 7114: @481128 |
| 150627 | GIM_Try, /*On fail goto*//*Label 7115*/ GIMT_Encode4(481194), // Rule ID 5741 // |
| 150628 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150629 | GIM_CheckHasNoUse, /*MI*/0, |
| 150630 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150631 | // MIs[0] offset |
| 150632 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150633 | // MIs[0] auxiliary |
| 150634 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150635 | // MIs[0] Operand 8 |
| 150636 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150638 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN), |
| 150640 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150641 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150642 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150644 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150645 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150646 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150647 | GIR_RootConstrainSelectedInstOperands, |
| 150648 | // GIR_Coverage, 5741, |
| 150649 | GIR_EraseRootFromParent_Done, |
| 150650 | // Label 7115: @481194 |
| 150651 | GIM_Try, /*On fail goto*//*Label 7116*/ GIMT_Encode4(481257), // Rule ID 5749 // |
| 150652 | GIM_CheckHasNoUse, /*MI*/0, |
| 150653 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150654 | // MIs[0] offset |
| 150655 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150656 | // MIs[0] auxiliary |
| 150657 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150658 | // MIs[0] Operand 8 |
| 150659 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150661 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150662 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN), |
| 150663 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150664 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150665 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150666 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150667 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150668 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150670 | GIR_RootConstrainSelectedInstOperands, |
| 150671 | // GIR_Coverage, 5749, |
| 150672 | GIR_EraseRootFromParent_Done, |
| 150673 | // Label 7116: @481257 |
| 150674 | GIM_Try, /*On fail goto*//*Label 7117*/ GIMT_Encode4(481327), // Rule ID 5737 // |
| 150675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150676 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150677 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150678 | // MIs[0] offset |
| 150679 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150680 | // MIs[0] auxiliary |
| 150681 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150682 | // MIs[0] Operand 8 |
| 150683 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150685 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_OFFEN_RTN), |
| 150687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150688 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150689 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150690 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150692 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150693 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150695 | GIR_RootConstrainSelectedInstOperands, |
| 150696 | // GIR_Coverage, 5737, |
| 150697 | GIR_EraseRootFromParent_Done, |
| 150698 | // Label 7117: @481327 |
| 150699 | GIM_Try, /*On fail goto*//*Label 7118*/ GIMT_Encode4(481394), // Rule ID 5745 // |
| 150700 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150701 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150702 | // MIs[0] offset |
| 150703 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150704 | // MIs[0] auxiliary |
| 150705 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150706 | // MIs[0] Operand 8 |
| 150707 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150708 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150709 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150710 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_OFFEN_RTN), |
| 150711 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150712 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150713 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 150714 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150715 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150716 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150717 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150718 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150719 | GIR_RootConstrainSelectedInstOperands, |
| 150720 | // GIR_Coverage, 5745, |
| 150721 | GIR_EraseRootFromParent_Done, |
| 150722 | // Label 7118: @481394 |
| 150723 | GIM_Try, /*On fail goto*//*Label 7119*/ GIMT_Encode4(481452), // Rule ID 5740 // |
| 150724 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150725 | GIM_CheckHasNoUse, /*MI*/0, |
| 150726 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150727 | // MIs[0] offset |
| 150728 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150729 | // MIs[0] auxiliary |
| 150730 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150731 | // MIs[0] Operand 8 |
| 150732 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150733 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150734 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN), |
| 150736 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150737 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150738 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150739 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150740 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150741 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150743 | GIR_RootConstrainSelectedInstOperands, |
| 150744 | // GIR_Coverage, 5740, |
| 150745 | GIR_EraseRootFromParent_Done, |
| 150746 | // Label 7119: @481452 |
| 150747 | GIM_Try, /*On fail goto*//*Label 7120*/ GIMT_Encode4(481507), // Rule ID 5748 // |
| 150748 | GIM_CheckHasNoUse, /*MI*/0, |
| 150749 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150750 | // MIs[0] offset |
| 150751 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150752 | // MIs[0] auxiliary |
| 150753 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150754 | // MIs[0] Operand 8 |
| 150755 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150756 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150757 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN), |
| 150759 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150760 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150761 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150763 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150764 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150765 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150766 | GIR_RootConstrainSelectedInstOperands, |
| 150767 | // GIR_Coverage, 5748, |
| 150768 | GIR_EraseRootFromParent_Done, |
| 150769 | // Label 7120: @481507 |
| 150770 | GIM_Try, /*On fail goto*//*Label 7121*/ GIMT_Encode4(481569), // Rule ID 5736 // |
| 150771 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150772 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150773 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150774 | // MIs[0] offset |
| 150775 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150776 | // MIs[0] auxiliary |
| 150777 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150778 | // MIs[0] Operand 8 |
| 150779 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150780 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150781 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_IDXEN_RTN), |
| 150783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150784 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150785 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150786 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150788 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150789 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150790 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150791 | GIR_RootConstrainSelectedInstOperands, |
| 150792 | // GIR_Coverage, 5736, |
| 150793 | GIR_EraseRootFromParent_Done, |
| 150794 | // Label 7121: @481569 |
| 150795 | GIM_Try, /*On fail goto*//*Label 7122*/ GIMT_Encode4(481628), // Rule ID 5744 // |
| 150796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150797 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150798 | // MIs[0] offset |
| 150799 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150800 | // MIs[0] auxiliary |
| 150801 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150802 | // MIs[0] Operand 8 |
| 150803 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150804 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150805 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150806 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_IDXEN_RTN), |
| 150807 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150808 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150809 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 150810 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150811 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150812 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150813 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150815 | GIR_RootConstrainSelectedInstOperands, |
| 150816 | // GIR_Coverage, 5744, |
| 150817 | GIR_EraseRootFromParent_Done, |
| 150818 | // Label 7122: @481628 |
| 150819 | GIM_Try, /*On fail goto*//*Label 7123*/ GIMT_Encode4(481724), // Rule ID 5742 // |
| 150820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150821 | GIM_CheckHasNoUse, /*MI*/0, |
| 150822 | // MIs[0] offset |
| 150823 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150824 | // MIs[0] auxiliary |
| 150825 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150826 | // MIs[0] Operand 8 |
| 150827 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150829 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150830 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150831 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150832 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150833 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150834 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150835 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150836 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150837 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150838 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150839 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150840 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN), |
| 150841 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150842 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150843 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150844 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150845 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150846 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150847 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150848 | GIR_RootConstrainSelectedInstOperands, |
| 150849 | // GIR_Coverage, 5742, |
| 150850 | GIR_EraseRootFromParent_Done, |
| 150851 | // Label 7123: @481724 |
| 150852 | GIM_Try, /*On fail goto*//*Label 7124*/ GIMT_Encode4(481817), // Rule ID 5750 // |
| 150853 | GIM_CheckHasNoUse, /*MI*/0, |
| 150854 | // MIs[0] offset |
| 150855 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150856 | // MIs[0] auxiliary |
| 150857 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150858 | // MIs[0] Operand 8 |
| 150859 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150861 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_sub_noret>> => (BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150865 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150866 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150867 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150868 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150869 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150870 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150871 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN), |
| 150873 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150874 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150875 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150877 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150878 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150880 | GIR_RootConstrainSelectedInstOperands, |
| 150881 | // GIR_Coverage, 5750, |
| 150882 | GIR_EraseRootFromParent_Done, |
| 150883 | // Label 7124: @481817 |
| 150884 | GIM_Try, /*On fail goto*//*Label 7125*/ GIMT_Encode4(481917), // Rule ID 5738 // |
| 150885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150886 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150887 | // MIs[0] offset |
| 150888 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150889 | // MIs[0] auxiliary |
| 150890 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150891 | // MIs[0] Operand 8 |
| 150892 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150893 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150894 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150895 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150896 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150897 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150898 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150899 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150900 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150901 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150902 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150903 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150904 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150905 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_BOTHEN_RTN), |
| 150906 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150907 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150908 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150909 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150911 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150912 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150913 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150914 | GIR_RootConstrainSelectedInstOperands, |
| 150915 | // GIR_Coverage, 5738, |
| 150916 | GIR_EraseRootFromParent_Done, |
| 150917 | // Label 7125: @481917 |
| 150918 | GIM_Try, /*On fail goto*//*Label 7126*/ GIMT_Encode4(482014), // Rule ID 5746 // |
| 150919 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 150920 | // MIs[0] offset |
| 150921 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150922 | // MIs[0] auxiliary |
| 150923 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150924 | // MIs[0] Operand 8 |
| 150925 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 150926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150927 | // (SIbuffer_atomic_sub:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150928 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 150929 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 150930 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 150931 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 150932 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 150933 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 150934 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 150935 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 150936 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150937 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 150938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SUB_X2_VBUFFER_BOTHEN_RTN), |
| 150939 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 150940 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150941 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 150942 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150944 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150945 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 150946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150947 | GIR_RootConstrainSelectedInstOperands, |
| 150948 | // GIR_Coverage, 5746, |
| 150949 | GIR_EraseRootFromParent_Done, |
| 150950 | // Label 7126: @482014 |
| 150951 | GIM_Reject, |
| 150952 | // Label 7110: @482015 |
| 150953 | GIM_Reject, |
| 150954 | // Label 7092: @482016 |
| 150955 | GIM_Reject, |
| 150956 | // Label 121: @482017 |
| 150957 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7129*/ GIMT_Encode4(485560), |
| 150958 | /*GILLT_s32*//*Label 7127*/ GIMT_Encode4(482036), |
| 150959 | /*GILLT_s64*//*Label 7128*/ GIMT_Encode4(484378), |
| 150960 | // Label 7127: @482036 |
| 150961 | GIM_Try, /*On fail goto*//*Label 7130*/ GIMT_Encode4(484377), |
| 150962 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 150963 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 150964 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 150965 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 150966 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 150967 | GIM_Try, /*On fail goto*//*Label 7131*/ GIMT_Encode4(482124), // Rule ID 5491 // |
| 150968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 150969 | GIM_CheckHasNoUse, /*MI*/0, |
| 150970 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150971 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150972 | // MIs[0] offset |
| 150973 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150974 | // MIs[0] auxiliary |
| 150975 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150976 | // MIs[0] Operand 8 |
| 150977 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 150978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 150979 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 150980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET), |
| 150981 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 150982 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 150983 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 150984 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 150985 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 150986 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 150987 | GIR_RootConstrainSelectedInstOperands, |
| 150988 | // GIR_Coverage, 5491, |
| 150989 | GIR_EraseRootFromParent_Done, |
| 150990 | // Label 7131: @482124 |
| 150991 | GIM_Try, /*On fail goto*//*Label 7132*/ GIMT_Encode4(482189), // Rule ID 5499 // |
| 150992 | GIM_CheckHasNoUse, /*MI*/0, |
| 150993 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 150994 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 150995 | // MIs[0] offset |
| 150996 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 150997 | // MIs[0] auxiliary |
| 150998 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 150999 | // MIs[0] Operand 8 |
| 151000 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151001 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151002 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151003 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET), |
| 151004 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151005 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151006 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151007 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151008 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151009 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151010 | GIR_RootConstrainSelectedInstOperands, |
| 151011 | // GIR_Coverage, 5499, |
| 151012 | GIR_EraseRootFromParent_Done, |
| 151013 | // Label 7132: @482189 |
| 151014 | GIM_Try, /*On fail goto*//*Label 7133*/ GIMT_Encode4(482257), // Rule ID 5507 // |
| 151015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151016 | GIM_CheckHasNoUse, /*MI*/0, |
| 151017 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151018 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151019 | // MIs[0] offset |
| 151020 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151021 | // MIs[0] auxiliary |
| 151022 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151023 | // MIs[0] Operand 8 |
| 151024 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151026 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET), |
| 151028 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151029 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151031 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151032 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151033 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151034 | GIR_RootConstrainSelectedInstOperands, |
| 151035 | // GIR_Coverage, 5507, |
| 151036 | GIR_EraseRootFromParent_Done, |
| 151037 | // Label 7133: @482257 |
| 151038 | GIM_Try, /*On fail goto*//*Label 7134*/ GIMT_Encode4(482322), // Rule ID 5515 // |
| 151039 | GIM_CheckHasNoUse, /*MI*/0, |
| 151040 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151041 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151042 | // MIs[0] offset |
| 151043 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151044 | // MIs[0] auxiliary |
| 151045 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151046 | // MIs[0] Operand 8 |
| 151047 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151049 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151050 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET), |
| 151051 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151052 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151053 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151054 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151055 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151056 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151057 | GIR_RootConstrainSelectedInstOperands, |
| 151058 | // GIR_Coverage, 5515, |
| 151059 | GIR_EraseRootFromParent_Done, |
| 151060 | // Label 7134: @482322 |
| 151061 | GIM_Try, /*On fail goto*//*Label 7135*/ GIMT_Encode4(482394), // Rule ID 5487 // |
| 151062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151064 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151065 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151066 | // MIs[0] offset |
| 151067 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151068 | // MIs[0] auxiliary |
| 151069 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151070 | // MIs[0] Operand 8 |
| 151071 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151072 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151073 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151074 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN), |
| 151075 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151076 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151077 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151078 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151079 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151080 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151081 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151082 | GIR_RootConstrainSelectedInstOperands, |
| 151083 | // GIR_Coverage, 5487, |
| 151084 | GIR_EraseRootFromParent_Done, |
| 151085 | // Label 7135: @482394 |
| 151086 | GIM_Try, /*On fail goto*//*Label 7136*/ GIMT_Encode4(482463), // Rule ID 5495 // |
| 151087 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151088 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151089 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151090 | // MIs[0] offset |
| 151091 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151092 | // MIs[0] auxiliary |
| 151093 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151094 | // MIs[0] Operand 8 |
| 151095 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151096 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151097 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151098 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN), |
| 151099 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151100 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151101 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151102 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151103 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151104 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151105 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151106 | GIR_RootConstrainSelectedInstOperands, |
| 151107 | // GIR_Coverage, 5495, |
| 151108 | GIR_EraseRootFromParent_Done, |
| 151109 | // Label 7136: @482463 |
| 151110 | GIM_Try, /*On fail goto*//*Label 7137*/ GIMT_Encode4(482535), // Rule ID 5503 // |
| 151111 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151112 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151113 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151114 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151115 | // MIs[0] offset |
| 151116 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151117 | // MIs[0] auxiliary |
| 151118 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151119 | // MIs[0] Operand 8 |
| 151120 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151121 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151122 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFSET_RTN), |
| 151124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151125 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151126 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151128 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151129 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151130 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151131 | GIR_RootConstrainSelectedInstOperands, |
| 151132 | // GIR_Coverage, 5503, |
| 151133 | GIR_EraseRootFromParent_Done, |
| 151134 | // Label 7137: @482535 |
| 151135 | GIM_Try, /*On fail goto*//*Label 7138*/ GIMT_Encode4(482604), // Rule ID 5511 // |
| 151136 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151137 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151138 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151139 | // MIs[0] offset |
| 151140 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151141 | // MIs[0] auxiliary |
| 151142 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151143 | // MIs[0] Operand 8 |
| 151144 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151145 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151146 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151147 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFSET_RTN), |
| 151148 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151149 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151150 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151151 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151152 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151153 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151154 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151155 | GIR_RootConstrainSelectedInstOperands, |
| 151156 | // GIR_Coverage, 5511, |
| 151157 | GIR_EraseRootFromParent_Done, |
| 151158 | // Label 7138: @482604 |
| 151159 | GIM_Try, /*On fail goto*//*Label 7139*/ GIMT_Encode4(482670), // Rule ID 5493 // |
| 151160 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151161 | GIM_CheckHasNoUse, /*MI*/0, |
| 151162 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151163 | // MIs[0] offset |
| 151164 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151165 | // MIs[0] auxiliary |
| 151166 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151167 | // MIs[0] Operand 8 |
| 151168 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151169 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151170 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN), |
| 151172 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151173 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151174 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151176 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151177 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151178 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151179 | GIR_RootConstrainSelectedInstOperands, |
| 151180 | // GIR_Coverage, 5493, |
| 151181 | GIR_EraseRootFromParent_Done, |
| 151182 | // Label 7139: @482670 |
| 151183 | GIM_Try, /*On fail goto*//*Label 7140*/ GIMT_Encode4(482733), // Rule ID 5501 // |
| 151184 | GIM_CheckHasNoUse, /*MI*/0, |
| 151185 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151186 | // MIs[0] offset |
| 151187 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151188 | // MIs[0] auxiliary |
| 151189 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151190 | // MIs[0] Operand 8 |
| 151191 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151193 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151194 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN), |
| 151195 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151196 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151197 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151198 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151199 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151200 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151201 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151202 | GIR_RootConstrainSelectedInstOperands, |
| 151203 | // GIR_Coverage, 5501, |
| 151204 | GIR_EraseRootFromParent_Done, |
| 151205 | // Label 7140: @482733 |
| 151206 | GIM_Try, /*On fail goto*//*Label 7141*/ GIMT_Encode4(482799), // Rule ID 5509 // |
| 151207 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151208 | GIM_CheckHasNoUse, /*MI*/0, |
| 151209 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151210 | // MIs[0] offset |
| 151211 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151212 | // MIs[0] auxiliary |
| 151213 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151214 | // MIs[0] Operand 8 |
| 151215 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151216 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151217 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151218 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN), |
| 151219 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151220 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151221 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151222 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151223 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151224 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151225 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151226 | GIR_RootConstrainSelectedInstOperands, |
| 151227 | // GIR_Coverage, 5509, |
| 151228 | GIR_EraseRootFromParent_Done, |
| 151229 | // Label 7141: @482799 |
| 151230 | GIM_Try, /*On fail goto*//*Label 7142*/ GIMT_Encode4(482862), // Rule ID 5517 // |
| 151231 | GIM_CheckHasNoUse, /*MI*/0, |
| 151232 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151233 | // MIs[0] offset |
| 151234 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151235 | // MIs[0] auxiliary |
| 151236 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151237 | // MIs[0] Operand 8 |
| 151238 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151239 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151240 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN), |
| 151242 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151243 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151244 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151246 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151249 | GIR_RootConstrainSelectedInstOperands, |
| 151250 | // GIR_Coverage, 5517, |
| 151251 | GIR_EraseRootFromParent_Done, |
| 151252 | // Label 7142: @482862 |
| 151253 | GIM_Try, /*On fail goto*//*Label 7143*/ GIMT_Encode4(482932), // Rule ID 5489 // |
| 151254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151256 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151257 | // MIs[0] offset |
| 151258 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151259 | // MIs[0] auxiliary |
| 151260 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151261 | // MIs[0] Operand 8 |
| 151262 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151263 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151264 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN), |
| 151266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151267 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151268 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151269 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151271 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151272 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151274 | GIR_RootConstrainSelectedInstOperands, |
| 151275 | // GIR_Coverage, 5489, |
| 151276 | GIR_EraseRootFromParent_Done, |
| 151277 | // Label 7143: @482932 |
| 151278 | GIM_Try, /*On fail goto*//*Label 7144*/ GIMT_Encode4(482999), // Rule ID 5497 // |
| 151279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151280 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151281 | // MIs[0] offset |
| 151282 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151283 | // MIs[0] auxiliary |
| 151284 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151285 | // MIs[0] Operand 8 |
| 151286 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151288 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN), |
| 151290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151291 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151292 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151293 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151295 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151296 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151298 | GIR_RootConstrainSelectedInstOperands, |
| 151299 | // GIR_Coverage, 5497, |
| 151300 | GIR_EraseRootFromParent_Done, |
| 151301 | // Label 7144: @482999 |
| 151302 | GIM_Try, /*On fail goto*//*Label 7145*/ GIMT_Encode4(483069), // Rule ID 5505 // |
| 151303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151304 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151305 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151306 | // MIs[0] offset |
| 151307 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151308 | // MIs[0] auxiliary |
| 151309 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151310 | // MIs[0] Operand 8 |
| 151311 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151312 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151313 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_OFFEN_RTN), |
| 151315 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151316 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151317 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151318 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151320 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151321 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151323 | GIR_RootConstrainSelectedInstOperands, |
| 151324 | // GIR_Coverage, 5505, |
| 151325 | GIR_EraseRootFromParent_Done, |
| 151326 | // Label 7145: @483069 |
| 151327 | GIM_Try, /*On fail goto*//*Label 7146*/ GIMT_Encode4(483136), // Rule ID 5513 // |
| 151328 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151329 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151330 | // MIs[0] offset |
| 151331 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151332 | // MIs[0] auxiliary |
| 151333 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151334 | // MIs[0] Operand 8 |
| 151335 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151336 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151337 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_OFFEN_RTN), |
| 151339 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151340 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151341 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151342 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151344 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151347 | GIR_RootConstrainSelectedInstOperands, |
| 151348 | // GIR_Coverage, 5513, |
| 151349 | GIR_EraseRootFromParent_Done, |
| 151350 | // Label 7146: @483136 |
| 151351 | GIM_Try, /*On fail goto*//*Label 7147*/ GIMT_Encode4(483194), // Rule ID 5492 // |
| 151352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151353 | GIM_CheckHasNoUse, /*MI*/0, |
| 151354 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151355 | // MIs[0] offset |
| 151356 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151357 | // MIs[0] auxiliary |
| 151358 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151359 | // MIs[0] Operand 8 |
| 151360 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151362 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN), |
| 151364 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151365 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151366 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151368 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151371 | GIR_RootConstrainSelectedInstOperands, |
| 151372 | // GIR_Coverage, 5492, |
| 151373 | GIR_EraseRootFromParent_Done, |
| 151374 | // Label 7147: @483194 |
| 151375 | GIM_Try, /*On fail goto*//*Label 7148*/ GIMT_Encode4(483249), // Rule ID 5500 // |
| 151376 | GIM_CheckHasNoUse, /*MI*/0, |
| 151377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151378 | // MIs[0] offset |
| 151379 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151380 | // MIs[0] auxiliary |
| 151381 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151382 | // MIs[0] Operand 8 |
| 151383 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151385 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN), |
| 151387 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151388 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151389 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151391 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151392 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151394 | GIR_RootConstrainSelectedInstOperands, |
| 151395 | // GIR_Coverage, 5500, |
| 151396 | GIR_EraseRootFromParent_Done, |
| 151397 | // Label 7148: @483249 |
| 151398 | GIM_Try, /*On fail goto*//*Label 7149*/ GIMT_Encode4(483307), // Rule ID 5508 // |
| 151399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151400 | GIM_CheckHasNoUse, /*MI*/0, |
| 151401 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151402 | // MIs[0] offset |
| 151403 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151404 | // MIs[0] auxiliary |
| 151405 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151406 | // MIs[0] Operand 8 |
| 151407 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151409 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN), |
| 151411 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151412 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151413 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151415 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151418 | GIR_RootConstrainSelectedInstOperands, |
| 151419 | // GIR_Coverage, 5508, |
| 151420 | GIR_EraseRootFromParent_Done, |
| 151421 | // Label 7149: @483307 |
| 151422 | GIM_Try, /*On fail goto*//*Label 7150*/ GIMT_Encode4(483362), // Rule ID 5516 // |
| 151423 | GIM_CheckHasNoUse, /*MI*/0, |
| 151424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151425 | // MIs[0] offset |
| 151426 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151427 | // MIs[0] auxiliary |
| 151428 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151429 | // MIs[0] Operand 8 |
| 151430 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151432 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN), |
| 151434 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151435 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151436 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151438 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151440 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151441 | GIR_RootConstrainSelectedInstOperands, |
| 151442 | // GIR_Coverage, 5516, |
| 151443 | GIR_EraseRootFromParent_Done, |
| 151444 | // Label 7150: @483362 |
| 151445 | GIM_Try, /*On fail goto*//*Label 7151*/ GIMT_Encode4(483424), // Rule ID 5488 // |
| 151446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151447 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151449 | // MIs[0] offset |
| 151450 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151451 | // MIs[0] auxiliary |
| 151452 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151453 | // MIs[0] Operand 8 |
| 151454 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151456 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN), |
| 151458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151459 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151460 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151461 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151463 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151466 | GIR_RootConstrainSelectedInstOperands, |
| 151467 | // GIR_Coverage, 5488, |
| 151468 | GIR_EraseRootFromParent_Done, |
| 151469 | // Label 7151: @483424 |
| 151470 | GIM_Try, /*On fail goto*//*Label 7152*/ GIMT_Encode4(483483), // Rule ID 5496 // |
| 151471 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151472 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151473 | // MIs[0] offset |
| 151474 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151475 | // MIs[0] auxiliary |
| 151476 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151477 | // MIs[0] Operand 8 |
| 151478 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151479 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151480 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN), |
| 151482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151483 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151484 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151485 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151487 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151488 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151490 | GIR_RootConstrainSelectedInstOperands, |
| 151491 | // GIR_Coverage, 5496, |
| 151492 | GIR_EraseRootFromParent_Done, |
| 151493 | // Label 7152: @483483 |
| 151494 | GIM_Try, /*On fail goto*//*Label 7153*/ GIMT_Encode4(483545), // Rule ID 5504 // |
| 151495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151496 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151497 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151498 | // MIs[0] offset |
| 151499 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151500 | // MIs[0] auxiliary |
| 151501 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151502 | // MIs[0] Operand 8 |
| 151503 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151504 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151505 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151506 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_IDXEN_RTN), |
| 151507 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151508 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151509 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151510 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151511 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151512 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151513 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151514 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151515 | GIR_RootConstrainSelectedInstOperands, |
| 151516 | // GIR_Coverage, 5504, |
| 151517 | GIR_EraseRootFromParent_Done, |
| 151518 | // Label 7153: @483545 |
| 151519 | GIM_Try, /*On fail goto*//*Label 7154*/ GIMT_Encode4(483604), // Rule ID 5512 // |
| 151520 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151521 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151522 | // MIs[0] offset |
| 151523 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151524 | // MIs[0] auxiliary |
| 151525 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151526 | // MIs[0] Operand 8 |
| 151527 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151528 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151529 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151530 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_IDXEN_RTN), |
| 151531 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151532 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151533 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 151534 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151536 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151537 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151538 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151539 | GIR_RootConstrainSelectedInstOperands, |
| 151540 | // GIR_Coverage, 5512, |
| 151541 | GIR_EraseRootFromParent_Done, |
| 151542 | // Label 7154: @483604 |
| 151543 | GIM_Try, /*On fail goto*//*Label 7155*/ GIMT_Encode4(483700), // Rule ID 5494 // |
| 151544 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151545 | GIM_CheckHasNoUse, /*MI*/0, |
| 151546 | // MIs[0] offset |
| 151547 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151548 | // MIs[0] auxiliary |
| 151549 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151550 | // MIs[0] Operand 8 |
| 151551 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151552 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151553 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151554 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151555 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151556 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151557 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151558 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151559 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151560 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151561 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151562 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151563 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN), |
| 151565 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151566 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151567 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151569 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151570 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151572 | GIR_RootConstrainSelectedInstOperands, |
| 151573 | // GIR_Coverage, 5494, |
| 151574 | GIR_EraseRootFromParent_Done, |
| 151575 | // Label 7155: @483700 |
| 151576 | GIM_Try, /*On fail goto*//*Label 7156*/ GIMT_Encode4(483793), // Rule ID 5502 // |
| 151577 | GIM_CheckHasNoUse, /*MI*/0, |
| 151578 | // MIs[0] offset |
| 151579 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151580 | // MIs[0] auxiliary |
| 151581 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151582 | // MIs[0] Operand 8 |
| 151583 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151584 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151585 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151586 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151587 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151588 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151589 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151590 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151591 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151592 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151593 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151594 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151595 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151596 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN), |
| 151597 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151598 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151599 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151600 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151601 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151602 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151603 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151604 | GIR_RootConstrainSelectedInstOperands, |
| 151605 | // GIR_Coverage, 5502, |
| 151606 | GIR_EraseRootFromParent_Done, |
| 151607 | // Label 7156: @483793 |
| 151608 | GIM_Try, /*On fail goto*//*Label 7157*/ GIMT_Encode4(483889), // Rule ID 5510 // |
| 151609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151610 | GIM_CheckHasNoUse, /*MI*/0, |
| 151611 | // MIs[0] offset |
| 151612 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151613 | // MIs[0] auxiliary |
| 151614 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151615 | // MIs[0] Operand 8 |
| 151616 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151618 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151619 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151620 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151621 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151622 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151623 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151624 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151625 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151626 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151627 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151628 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN), |
| 151630 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151631 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151632 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151633 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151634 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151635 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151636 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151637 | GIR_RootConstrainSelectedInstOperands, |
| 151638 | // GIR_Coverage, 5510, |
| 151639 | GIR_EraseRootFromParent_Done, |
| 151640 | // Label 7157: @483889 |
| 151641 | GIM_Try, /*On fail goto*//*Label 7158*/ GIMT_Encode4(483982), // Rule ID 5518 // |
| 151642 | GIM_CheckHasNoUse, /*MI*/0, |
| 151643 | // MIs[0] offset |
| 151644 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151645 | // MIs[0] auxiliary |
| 151646 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151647 | // MIs[0] Operand 8 |
| 151648 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151650 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151651 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151652 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151653 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151654 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151655 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151656 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151657 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151658 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151659 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151660 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN), |
| 151662 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151664 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151666 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151669 | GIR_RootConstrainSelectedInstOperands, |
| 151670 | // GIR_Coverage, 5518, |
| 151671 | GIR_EraseRootFromParent_Done, |
| 151672 | // Label 7158: @483982 |
| 151673 | GIM_Try, /*On fail goto*//*Label 7159*/ GIMT_Encode4(484082), // Rule ID 5490 // |
| 151674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151675 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151676 | // MIs[0] offset |
| 151677 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151678 | // MIs[0] auxiliary |
| 151679 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151680 | // MIs[0] Operand 8 |
| 151681 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151682 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151683 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151684 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151685 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151686 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151687 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151688 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151689 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151690 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151691 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151692 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151693 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN), |
| 151695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151696 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151697 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151698 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151700 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151701 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151703 | GIR_RootConstrainSelectedInstOperands, |
| 151704 | // GIR_Coverage, 5490, |
| 151705 | GIR_EraseRootFromParent_Done, |
| 151706 | // Label 7159: @484082 |
| 151707 | GIM_Try, /*On fail goto*//*Label 7160*/ GIMT_Encode4(484179), // Rule ID 5498 // |
| 151708 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151709 | // MIs[0] offset |
| 151710 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151711 | // MIs[0] auxiliary |
| 151712 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151713 | // MIs[0] Operand 8 |
| 151714 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151715 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151716 | // (SIbuffer_atomic_swap:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151717 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151718 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151719 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151720 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151721 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151722 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151723 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151724 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151725 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151726 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151727 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN), |
| 151728 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151729 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151730 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151731 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151733 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151734 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151735 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151736 | GIR_RootConstrainSelectedInstOperands, |
| 151737 | // GIR_Coverage, 5498, |
| 151738 | GIR_EraseRootFromParent_Done, |
| 151739 | // Label 7160: @484179 |
| 151740 | GIM_Try, /*On fail goto*//*Label 7161*/ GIMT_Encode4(484279), // Rule ID 5506 // |
| 151741 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151742 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151743 | // MIs[0] offset |
| 151744 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151745 | // MIs[0] auxiliary |
| 151746 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151747 | // MIs[0] Operand 8 |
| 151748 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151750 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151751 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151752 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151753 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151754 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151755 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151756 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151757 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151758 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151759 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151760 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_BOTHEN_RTN), |
| 151762 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151763 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151764 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151765 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151767 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151768 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151769 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151770 | GIR_RootConstrainSelectedInstOperands, |
| 151771 | // GIR_Coverage, 5506, |
| 151772 | GIR_EraseRootFromParent_Done, |
| 151773 | // Label 7161: @484279 |
| 151774 | GIM_Try, /*On fail goto*//*Label 7162*/ GIMT_Encode4(484376), // Rule ID 5514 // |
| 151775 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 151776 | // MIs[0] offset |
| 151777 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151778 | // MIs[0] auxiliary |
| 151779 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151780 | // MIs[0] Operand 8 |
| 151781 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 151782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151783 | // (SIbuffer_atomic_swap:{ *:[f32] } f32:{ *:[f32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN:{ *:[f32] } anonymous_15876:{ *:[f32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 151785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 151786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 151787 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 151788 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 151789 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 151790 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 151791 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 151792 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151793 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 151794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_VBUFFER_BOTHEN_RTN), |
| 151795 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151796 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151797 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 151798 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151800 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151803 | GIR_RootConstrainSelectedInstOperands, |
| 151804 | // GIR_Coverage, 5514, |
| 151805 | GIR_EraseRootFromParent_Done, |
| 151806 | // Label 7162: @484376 |
| 151807 | GIM_Reject, |
| 151808 | // Label 7130: @484377 |
| 151809 | GIM_Reject, |
| 151810 | // Label 7128: @484378 |
| 151811 | GIM_Try, /*On fail goto*//*Label 7163*/ GIMT_Encode4(485559), |
| 151812 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 151813 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 151814 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 151815 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 151816 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 151817 | GIM_Try, /*On fail goto*//*Label 7164*/ GIMT_Encode4(484466), // Rule ID 5707 // |
| 151818 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151819 | GIM_CheckHasNoUse, /*MI*/0, |
| 151820 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151821 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151822 | // MIs[0] offset |
| 151823 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151824 | // MIs[0] auxiliary |
| 151825 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151826 | // MIs[0] Operand 8 |
| 151827 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151828 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151829 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET), |
| 151831 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151832 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151833 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151834 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151835 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151836 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151837 | GIR_RootConstrainSelectedInstOperands, |
| 151838 | // GIR_Coverage, 5707, |
| 151839 | GIR_EraseRootFromParent_Done, |
| 151840 | // Label 7164: @484466 |
| 151841 | GIM_Try, /*On fail goto*//*Label 7165*/ GIMT_Encode4(484531), // Rule ID 5715 // |
| 151842 | GIM_CheckHasNoUse, /*MI*/0, |
| 151843 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151844 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151845 | // MIs[0] offset |
| 151846 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151847 | // MIs[0] auxiliary |
| 151848 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151849 | // MIs[0] Operand 8 |
| 151850 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151852 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET), |
| 151854 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151855 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151857 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151858 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151859 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151860 | GIR_RootConstrainSelectedInstOperands, |
| 151861 | // GIR_Coverage, 5715, |
| 151862 | GIR_EraseRootFromParent_Done, |
| 151863 | // Label 7165: @484531 |
| 151864 | GIM_Try, /*On fail goto*//*Label 7166*/ GIMT_Encode4(484603), // Rule ID 5703 // |
| 151865 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151866 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 151867 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151868 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151869 | // MIs[0] offset |
| 151870 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151871 | // MIs[0] auxiliary |
| 151872 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151873 | // MIs[0] Operand 8 |
| 151874 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151875 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151876 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151877 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFSET_RTN), |
| 151878 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151879 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151880 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151881 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151882 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151883 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151884 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151885 | GIR_RootConstrainSelectedInstOperands, |
| 151886 | // GIR_Coverage, 5703, |
| 151887 | GIR_EraseRootFromParent_Done, |
| 151888 | // Label 7166: @484603 |
| 151889 | GIM_Try, /*On fail goto*//*Label 7167*/ GIMT_Encode4(484672), // Rule ID 5711 // |
| 151890 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 151891 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151892 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 151893 | // MIs[0] offset |
| 151894 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151895 | // MIs[0] auxiliary |
| 151896 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151897 | // MIs[0] Operand 8 |
| 151898 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151900 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFSET_RTN), |
| 151902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151903 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151904 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151906 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151907 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151908 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151909 | GIR_RootConstrainSelectedInstOperands, |
| 151910 | // GIR_Coverage, 5711, |
| 151911 | GIR_EraseRootFromParent_Done, |
| 151912 | // Label 7167: @484672 |
| 151913 | GIM_Try, /*On fail goto*//*Label 7168*/ GIMT_Encode4(484738), // Rule ID 5709 // |
| 151914 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151915 | GIM_CheckHasNoUse, /*MI*/0, |
| 151916 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151917 | // MIs[0] offset |
| 151918 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151919 | // MIs[0] auxiliary |
| 151920 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151921 | // MIs[0] Operand 8 |
| 151922 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151923 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151924 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151925 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN), |
| 151926 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151927 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151928 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151929 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151930 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151931 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151932 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151933 | GIR_RootConstrainSelectedInstOperands, |
| 151934 | // GIR_Coverage, 5709, |
| 151935 | GIR_EraseRootFromParent_Done, |
| 151936 | // Label 7168: @484738 |
| 151937 | GIM_Try, /*On fail goto*//*Label 7169*/ GIMT_Encode4(484801), // Rule ID 5717 // |
| 151938 | GIM_CheckHasNoUse, /*MI*/0, |
| 151939 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151940 | // MIs[0] offset |
| 151941 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151942 | // MIs[0] auxiliary |
| 151943 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151944 | // MIs[0] Operand 8 |
| 151945 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151946 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151947 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN), |
| 151949 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151950 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151951 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151952 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151953 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151954 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 151955 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151956 | GIR_RootConstrainSelectedInstOperands, |
| 151957 | // GIR_Coverage, 5717, |
| 151958 | GIR_EraseRootFromParent_Done, |
| 151959 | // Label 7169: @484801 |
| 151960 | GIM_Try, /*On fail goto*//*Label 7170*/ GIMT_Encode4(484871), // Rule ID 5705 // |
| 151961 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 151962 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 151963 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151964 | // MIs[0] offset |
| 151965 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151966 | // MIs[0] auxiliary |
| 151967 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151968 | // MIs[0] Operand 8 |
| 151969 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151970 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151971 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151972 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_OFFEN_RTN), |
| 151973 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151974 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151975 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 151976 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 151977 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 151978 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 151979 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 151980 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 151981 | GIR_RootConstrainSelectedInstOperands, |
| 151982 | // GIR_Coverage, 5705, |
| 151983 | GIR_EraseRootFromParent_Done, |
| 151984 | // Label 7170: @484871 |
| 151985 | GIM_Try, /*On fail goto*//*Label 7171*/ GIMT_Encode4(484938), // Rule ID 5713 // |
| 151986 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 151987 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 151988 | // MIs[0] offset |
| 151989 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 151990 | // MIs[0] auxiliary |
| 151991 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 151992 | // MIs[0] Operand 8 |
| 151993 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 151994 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 151995 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 151996 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_OFFEN_RTN), |
| 151997 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 151998 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 151999 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152000 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152002 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152003 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152004 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152005 | GIR_RootConstrainSelectedInstOperands, |
| 152006 | // GIR_Coverage, 5713, |
| 152007 | GIR_EraseRootFromParent_Done, |
| 152008 | // Label 7171: @484938 |
| 152009 | GIM_Try, /*On fail goto*//*Label 7172*/ GIMT_Encode4(484996), // Rule ID 5708 // |
| 152010 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152011 | GIM_CheckHasNoUse, /*MI*/0, |
| 152012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152013 | // MIs[0] offset |
| 152014 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152015 | // MIs[0] auxiliary |
| 152016 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152017 | // MIs[0] Operand 8 |
| 152018 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152020 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN), |
| 152022 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152023 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152024 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152026 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152029 | GIR_RootConstrainSelectedInstOperands, |
| 152030 | // GIR_Coverage, 5708, |
| 152031 | GIR_EraseRootFromParent_Done, |
| 152032 | // Label 7172: @484996 |
| 152033 | GIM_Try, /*On fail goto*//*Label 7173*/ GIMT_Encode4(485051), // Rule ID 5716 // |
| 152034 | GIM_CheckHasNoUse, /*MI*/0, |
| 152035 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152036 | // MIs[0] offset |
| 152037 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152038 | // MIs[0] auxiliary |
| 152039 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152040 | // MIs[0] Operand 8 |
| 152041 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152043 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN), |
| 152045 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152046 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152047 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152049 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152050 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152052 | GIR_RootConstrainSelectedInstOperands, |
| 152053 | // GIR_Coverage, 5716, |
| 152054 | GIR_EraseRootFromParent_Done, |
| 152055 | // Label 7173: @485051 |
| 152056 | GIM_Try, /*On fail goto*//*Label 7174*/ GIMT_Encode4(485113), // Rule ID 5704 // |
| 152057 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152060 | // MIs[0] offset |
| 152061 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152062 | // MIs[0] auxiliary |
| 152063 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152064 | // MIs[0] Operand 8 |
| 152065 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152066 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152067 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_IDXEN_RTN), |
| 152069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152070 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152071 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152072 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152074 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152075 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152077 | GIR_RootConstrainSelectedInstOperands, |
| 152078 | // GIR_Coverage, 5704, |
| 152079 | GIR_EraseRootFromParent_Done, |
| 152080 | // Label 7174: @485113 |
| 152081 | GIM_Try, /*On fail goto*//*Label 7175*/ GIMT_Encode4(485172), // Rule ID 5712 // |
| 152082 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152083 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152084 | // MIs[0] offset |
| 152085 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152086 | // MIs[0] auxiliary |
| 152087 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152088 | // MIs[0] Operand 8 |
| 152089 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152091 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_IDXEN_RTN), |
| 152093 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152094 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152095 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152096 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152098 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152099 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152100 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152101 | GIR_RootConstrainSelectedInstOperands, |
| 152102 | // GIR_Coverage, 5712, |
| 152103 | GIR_EraseRootFromParent_Done, |
| 152104 | // Label 7175: @485172 |
| 152105 | GIM_Try, /*On fail goto*//*Label 7176*/ GIMT_Encode4(485268), // Rule ID 5710 // |
| 152106 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152107 | GIM_CheckHasNoUse, /*MI*/0, |
| 152108 | // MIs[0] offset |
| 152109 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152110 | // MIs[0] auxiliary |
| 152111 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152112 | // MIs[0] Operand 8 |
| 152113 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152115 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152116 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152117 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152118 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152119 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152120 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152121 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152122 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152123 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152124 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152125 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN), |
| 152127 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152128 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152129 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152131 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152132 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152134 | GIR_RootConstrainSelectedInstOperands, |
| 152135 | // GIR_Coverage, 5710, |
| 152136 | GIR_EraseRootFromParent_Done, |
| 152137 | // Label 7176: @485268 |
| 152138 | GIM_Try, /*On fail goto*//*Label 7177*/ GIMT_Encode4(485361), // Rule ID 5718 // |
| 152139 | GIM_CheckHasNoUse, /*MI*/0, |
| 152140 | // MIs[0] offset |
| 152141 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152142 | // MIs[0] auxiliary |
| 152143 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152144 | // MIs[0] Operand 8 |
| 152145 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152146 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152147 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_swap_noret>> => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152148 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152149 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152150 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152151 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152152 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152153 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152154 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152155 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152156 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152157 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152158 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN), |
| 152159 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152160 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152161 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152163 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152164 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152166 | GIR_RootConstrainSelectedInstOperands, |
| 152167 | // GIR_Coverage, 5718, |
| 152168 | GIR_EraseRootFromParent_Done, |
| 152169 | // Label 7177: @485361 |
| 152170 | GIM_Try, /*On fail goto*//*Label 7178*/ GIMT_Encode4(485461), // Rule ID 5706 // |
| 152171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152172 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152173 | // MIs[0] offset |
| 152174 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152175 | // MIs[0] auxiliary |
| 152176 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152177 | // MIs[0] Operand 8 |
| 152178 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152179 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152180 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152181 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152182 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152183 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152184 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152185 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152186 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152187 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152188 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152189 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152190 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152191 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_BOTHEN_RTN), |
| 152192 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152193 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152194 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152195 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152196 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152197 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152198 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152199 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152200 | GIR_RootConstrainSelectedInstOperands, |
| 152201 | // GIR_Coverage, 5706, |
| 152202 | GIR_EraseRootFromParent_Done, |
| 152203 | // Label 7178: @485461 |
| 152204 | GIM_Try, /*On fail goto*//*Label 7179*/ GIMT_Encode4(485558), // Rule ID 5714 // |
| 152205 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152206 | // MIs[0] offset |
| 152207 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152208 | // MIs[0] auxiliary |
| 152209 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152210 | // MIs[0] Operand 8 |
| 152211 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152212 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152213 | // (SIbuffer_atomic_swap:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152214 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152215 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152216 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152217 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152218 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152219 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152220 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152221 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152222 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152223 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_SWAP_X2_VBUFFER_BOTHEN_RTN), |
| 152225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152226 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152227 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152228 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152230 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152231 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152232 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152233 | GIR_RootConstrainSelectedInstOperands, |
| 152234 | // GIR_Coverage, 5714, |
| 152235 | GIR_EraseRootFromParent_Done, |
| 152236 | // Label 7179: @485558 |
| 152237 | GIM_Reject, |
| 152238 | // Label 7163: @485559 |
| 152239 | GIM_Reject, |
| 152240 | // Label 7129: @485560 |
| 152241 | GIM_Reject, |
| 152242 | // Label 122: @485561 |
| 152243 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7182*/ GIMT_Encode4(487944), |
| 152244 | /*GILLT_s32*//*Label 7180*/ GIMT_Encode4(485580), |
| 152245 | /*GILLT_s64*//*Label 7181*/ GIMT_Encode4(486762), |
| 152246 | // Label 7180: @485580 |
| 152247 | GIM_Try, /*On fail goto*//*Label 7183*/ GIMT_Encode4(486761), |
| 152248 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 152249 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 152250 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 152251 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 152252 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 152253 | GIM_Try, /*On fail goto*//*Label 7184*/ GIMT_Encode4(485668), // Rule ID 5603 // |
| 152254 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152255 | GIM_CheckHasNoUse, /*MI*/0, |
| 152256 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152257 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152258 | // MIs[0] offset |
| 152259 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152260 | // MIs[0] auxiliary |
| 152261 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152262 | // MIs[0] Operand 8 |
| 152263 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152265 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET), |
| 152267 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152268 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152270 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152273 | GIR_RootConstrainSelectedInstOperands, |
| 152274 | // GIR_Coverage, 5603, |
| 152275 | GIR_EraseRootFromParent_Done, |
| 152276 | // Label 7184: @485668 |
| 152277 | GIM_Try, /*On fail goto*//*Label 7185*/ GIMT_Encode4(485733), // Rule ID 5611 // |
| 152278 | GIM_CheckHasNoUse, /*MI*/0, |
| 152279 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152280 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152281 | // MIs[0] offset |
| 152282 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152283 | // MIs[0] auxiliary |
| 152284 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152285 | // MIs[0] Operand 8 |
| 152286 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152288 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET), |
| 152290 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152291 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152293 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152294 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152295 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152296 | GIR_RootConstrainSelectedInstOperands, |
| 152297 | // GIR_Coverage, 5611, |
| 152298 | GIR_EraseRootFromParent_Done, |
| 152299 | // Label 7185: @485733 |
| 152300 | GIM_Try, /*On fail goto*//*Label 7186*/ GIMT_Encode4(485805), // Rule ID 5599 // |
| 152301 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152302 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152303 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152304 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152305 | // MIs[0] offset |
| 152306 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152307 | // MIs[0] auxiliary |
| 152308 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152309 | // MIs[0] Operand 8 |
| 152310 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152311 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152312 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFSET_RTN), |
| 152314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152315 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152316 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152318 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152319 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152320 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152321 | GIR_RootConstrainSelectedInstOperands, |
| 152322 | // GIR_Coverage, 5599, |
| 152323 | GIR_EraseRootFromParent_Done, |
| 152324 | // Label 7186: @485805 |
| 152325 | GIM_Try, /*On fail goto*//*Label 7187*/ GIMT_Encode4(485874), // Rule ID 5607 // |
| 152326 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152327 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152328 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152329 | // MIs[0] offset |
| 152330 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152331 | // MIs[0] auxiliary |
| 152332 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152333 | // MIs[0] Operand 8 |
| 152334 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152335 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152336 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152337 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFSET_RTN), |
| 152338 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152339 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152340 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152342 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152343 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152345 | GIR_RootConstrainSelectedInstOperands, |
| 152346 | // GIR_Coverage, 5607, |
| 152347 | GIR_EraseRootFromParent_Done, |
| 152348 | // Label 7187: @485874 |
| 152349 | GIM_Try, /*On fail goto*//*Label 7188*/ GIMT_Encode4(485940), // Rule ID 5605 // |
| 152350 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152351 | GIM_CheckHasNoUse, /*MI*/0, |
| 152352 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152353 | // MIs[0] offset |
| 152354 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152355 | // MIs[0] auxiliary |
| 152356 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152357 | // MIs[0] Operand 8 |
| 152358 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152360 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN), |
| 152362 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152363 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152364 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152366 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152367 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152369 | GIR_RootConstrainSelectedInstOperands, |
| 152370 | // GIR_Coverage, 5605, |
| 152371 | GIR_EraseRootFromParent_Done, |
| 152372 | // Label 7188: @485940 |
| 152373 | GIM_Try, /*On fail goto*//*Label 7189*/ GIMT_Encode4(486003), // Rule ID 5613 // |
| 152374 | GIM_CheckHasNoUse, /*MI*/0, |
| 152375 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152376 | // MIs[0] offset |
| 152377 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152378 | // MIs[0] auxiliary |
| 152379 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152380 | // MIs[0] Operand 8 |
| 152381 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152383 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152384 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN), |
| 152385 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152386 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152387 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152388 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152389 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152390 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152391 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152392 | GIR_RootConstrainSelectedInstOperands, |
| 152393 | // GIR_Coverage, 5613, |
| 152394 | GIR_EraseRootFromParent_Done, |
| 152395 | // Label 7189: @486003 |
| 152396 | GIM_Try, /*On fail goto*//*Label 7190*/ GIMT_Encode4(486073), // Rule ID 5601 // |
| 152397 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152399 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152400 | // MIs[0] offset |
| 152401 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152402 | // MIs[0] auxiliary |
| 152403 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152404 | // MIs[0] Operand 8 |
| 152405 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152407 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152408 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_OFFEN_RTN), |
| 152409 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152410 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152411 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152412 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152414 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152415 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152416 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152417 | GIR_RootConstrainSelectedInstOperands, |
| 152418 | // GIR_Coverage, 5601, |
| 152419 | GIR_EraseRootFromParent_Done, |
| 152420 | // Label 7190: @486073 |
| 152421 | GIM_Try, /*On fail goto*//*Label 7191*/ GIMT_Encode4(486140), // Rule ID 5609 // |
| 152422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152423 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152424 | // MIs[0] offset |
| 152425 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152426 | // MIs[0] auxiliary |
| 152427 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152428 | // MIs[0] Operand 8 |
| 152429 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152430 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152431 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_OFFEN_RTN), |
| 152433 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152434 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152435 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152436 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152438 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152440 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152441 | GIR_RootConstrainSelectedInstOperands, |
| 152442 | // GIR_Coverage, 5609, |
| 152443 | GIR_EraseRootFromParent_Done, |
| 152444 | // Label 7191: @486140 |
| 152445 | GIM_Try, /*On fail goto*//*Label 7192*/ GIMT_Encode4(486198), // Rule ID 5604 // |
| 152446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152447 | GIM_CheckHasNoUse, /*MI*/0, |
| 152448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152449 | // MIs[0] offset |
| 152450 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152451 | // MIs[0] auxiliary |
| 152452 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152453 | // MIs[0] Operand 8 |
| 152454 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152456 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN), |
| 152458 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152459 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152460 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152462 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152465 | GIR_RootConstrainSelectedInstOperands, |
| 152466 | // GIR_Coverage, 5604, |
| 152467 | GIR_EraseRootFromParent_Done, |
| 152468 | // Label 7192: @486198 |
| 152469 | GIM_Try, /*On fail goto*//*Label 7193*/ GIMT_Encode4(486253), // Rule ID 5612 // |
| 152470 | GIM_CheckHasNoUse, /*MI*/0, |
| 152471 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152472 | // MIs[0] offset |
| 152473 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152474 | // MIs[0] auxiliary |
| 152475 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152476 | // MIs[0] Operand 8 |
| 152477 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152479 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN), |
| 152481 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152482 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152483 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152485 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152486 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152488 | GIR_RootConstrainSelectedInstOperands, |
| 152489 | // GIR_Coverage, 5612, |
| 152490 | GIR_EraseRootFromParent_Done, |
| 152491 | // Label 7193: @486253 |
| 152492 | GIM_Try, /*On fail goto*//*Label 7194*/ GIMT_Encode4(486315), // Rule ID 5600 // |
| 152493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152494 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152495 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152496 | // MIs[0] offset |
| 152497 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152498 | // MIs[0] auxiliary |
| 152499 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152500 | // MIs[0] Operand 8 |
| 152501 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152503 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_IDXEN_RTN), |
| 152505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152506 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152507 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152508 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152510 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152513 | GIR_RootConstrainSelectedInstOperands, |
| 152514 | // GIR_Coverage, 5600, |
| 152515 | GIR_EraseRootFromParent_Done, |
| 152516 | // Label 7194: @486315 |
| 152517 | GIM_Try, /*On fail goto*//*Label 7195*/ GIMT_Encode4(486374), // Rule ID 5608 // |
| 152518 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152519 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152520 | // MIs[0] offset |
| 152521 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152522 | // MIs[0] auxiliary |
| 152523 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152524 | // MIs[0] Operand 8 |
| 152525 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152527 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_IDXEN_RTN), |
| 152529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152530 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152531 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152532 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152533 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152534 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152535 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152536 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152537 | GIR_RootConstrainSelectedInstOperands, |
| 152538 | // GIR_Coverage, 5608, |
| 152539 | GIR_EraseRootFromParent_Done, |
| 152540 | // Label 7195: @486374 |
| 152541 | GIM_Try, /*On fail goto*//*Label 7196*/ GIMT_Encode4(486470), // Rule ID 5606 // |
| 152542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152543 | GIM_CheckHasNoUse, /*MI*/0, |
| 152544 | // MIs[0] offset |
| 152545 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152546 | // MIs[0] auxiliary |
| 152547 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152548 | // MIs[0] Operand 8 |
| 152549 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152550 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152551 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152552 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152553 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152554 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152555 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152556 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152557 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152558 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152559 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152560 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152561 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN), |
| 152563 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152564 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152565 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152567 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152568 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152570 | GIR_RootConstrainSelectedInstOperands, |
| 152571 | // GIR_Coverage, 5606, |
| 152572 | GIR_EraseRootFromParent_Done, |
| 152573 | // Label 7196: @486470 |
| 152574 | GIM_Try, /*On fail goto*//*Label 7197*/ GIMT_Encode4(486563), // Rule ID 5614 // |
| 152575 | GIM_CheckHasNoUse, /*MI*/0, |
| 152576 | // MIs[0] offset |
| 152577 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152578 | // MIs[0] auxiliary |
| 152579 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152580 | // MIs[0] Operand 8 |
| 152581 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152583 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152584 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152585 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152586 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152587 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152588 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152589 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152590 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152591 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152592 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152593 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN), |
| 152595 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152596 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152597 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152599 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152600 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152601 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152602 | GIR_RootConstrainSelectedInstOperands, |
| 152603 | // GIR_Coverage, 5614, |
| 152604 | GIR_EraseRootFromParent_Done, |
| 152605 | // Label 7197: @486563 |
| 152606 | GIM_Try, /*On fail goto*//*Label 7198*/ GIMT_Encode4(486663), // Rule ID 5602 // |
| 152607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152608 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152609 | // MIs[0] offset |
| 152610 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152611 | // MIs[0] auxiliary |
| 152612 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152613 | // MIs[0] Operand 8 |
| 152614 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152615 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152616 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152617 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152618 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152619 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152620 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152621 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152622 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152623 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152624 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152625 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152626 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_BOTHEN_RTN), |
| 152628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152629 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152630 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152631 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152632 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152633 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152634 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152635 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152636 | GIR_RootConstrainSelectedInstOperands, |
| 152637 | // GIR_Coverage, 5602, |
| 152638 | GIR_EraseRootFromParent_Done, |
| 152639 | // Label 7198: @486663 |
| 152640 | GIM_Try, /*On fail goto*//*Label 7199*/ GIMT_Encode4(486760), // Rule ID 5610 // |
| 152641 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 152642 | // MIs[0] offset |
| 152643 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152644 | // MIs[0] auxiliary |
| 152645 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152646 | // MIs[0] Operand 8 |
| 152647 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152649 | // (SIbuffer_atomic_umax:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152651 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152652 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152653 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152654 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152655 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152656 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152657 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152658 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152659 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_VBUFFER_BOTHEN_RTN), |
| 152661 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152662 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152663 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152664 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152666 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152669 | GIR_RootConstrainSelectedInstOperands, |
| 152670 | // GIR_Coverage, 5610, |
| 152671 | GIR_EraseRootFromParent_Done, |
| 152672 | // Label 7199: @486760 |
| 152673 | GIM_Reject, |
| 152674 | // Label 7183: @486761 |
| 152675 | GIM_Reject, |
| 152676 | // Label 7181: @486762 |
| 152677 | GIM_Try, /*On fail goto*//*Label 7200*/ GIMT_Encode4(487943), |
| 152678 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 152679 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 152680 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 152681 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 152682 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 152683 | GIM_Try, /*On fail goto*//*Label 7201*/ GIMT_Encode4(486850), // Rule ID 5803 // |
| 152684 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152685 | GIM_CheckHasNoUse, /*MI*/0, |
| 152686 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152687 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152688 | // MIs[0] offset |
| 152689 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152690 | // MIs[0] auxiliary |
| 152691 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152692 | // MIs[0] Operand 8 |
| 152693 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152695 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET), |
| 152697 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152698 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152699 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152700 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152701 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152703 | GIR_RootConstrainSelectedInstOperands, |
| 152704 | // GIR_Coverage, 5803, |
| 152705 | GIR_EraseRootFromParent_Done, |
| 152706 | // Label 7201: @486850 |
| 152707 | GIM_Try, /*On fail goto*//*Label 7202*/ GIMT_Encode4(486915), // Rule ID 5811 // |
| 152708 | GIM_CheckHasNoUse, /*MI*/0, |
| 152709 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152710 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152711 | // MIs[0] offset |
| 152712 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152713 | // MIs[0] auxiliary |
| 152714 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152715 | // MIs[0] Operand 8 |
| 152716 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152717 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152718 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET), |
| 152720 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152721 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152723 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152726 | GIR_RootConstrainSelectedInstOperands, |
| 152727 | // GIR_Coverage, 5811, |
| 152728 | GIR_EraseRootFromParent_Done, |
| 152729 | // Label 7202: @486915 |
| 152730 | GIM_Try, /*On fail goto*//*Label 7203*/ GIMT_Encode4(486987), // Rule ID 5799 // |
| 152731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152732 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152735 | // MIs[0] offset |
| 152736 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152737 | // MIs[0] auxiliary |
| 152738 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152739 | // MIs[0] Operand 8 |
| 152740 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152742 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFSET_RTN), |
| 152744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152745 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152746 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152748 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152751 | GIR_RootConstrainSelectedInstOperands, |
| 152752 | // GIR_Coverage, 5799, |
| 152753 | GIR_EraseRootFromParent_Done, |
| 152754 | // Label 7203: @486987 |
| 152755 | GIM_Try, /*On fail goto*//*Label 7204*/ GIMT_Encode4(487056), // Rule ID 5807 // |
| 152756 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152758 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152759 | // MIs[0] offset |
| 152760 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152761 | // MIs[0] auxiliary |
| 152762 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152763 | // MIs[0] Operand 8 |
| 152764 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152766 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFSET_RTN), |
| 152768 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152769 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152770 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152772 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152773 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152774 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152775 | GIR_RootConstrainSelectedInstOperands, |
| 152776 | // GIR_Coverage, 5807, |
| 152777 | GIR_EraseRootFromParent_Done, |
| 152778 | // Label 7204: @487056 |
| 152779 | GIM_Try, /*On fail goto*//*Label 7205*/ GIMT_Encode4(487122), // Rule ID 5805 // |
| 152780 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152781 | GIM_CheckHasNoUse, /*MI*/0, |
| 152782 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152783 | // MIs[0] offset |
| 152784 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152785 | // MIs[0] auxiliary |
| 152786 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152787 | // MIs[0] Operand 8 |
| 152788 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152790 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN), |
| 152792 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152793 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152794 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152796 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152797 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152798 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152799 | GIR_RootConstrainSelectedInstOperands, |
| 152800 | // GIR_Coverage, 5805, |
| 152801 | GIR_EraseRootFromParent_Done, |
| 152802 | // Label 7205: @487122 |
| 152803 | GIM_Try, /*On fail goto*//*Label 7206*/ GIMT_Encode4(487185), // Rule ID 5813 // |
| 152804 | GIM_CheckHasNoUse, /*MI*/0, |
| 152805 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152806 | // MIs[0] offset |
| 152807 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152808 | // MIs[0] auxiliary |
| 152809 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152810 | // MIs[0] Operand 8 |
| 152811 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152813 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN), |
| 152815 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152816 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152817 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152819 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152821 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152822 | GIR_RootConstrainSelectedInstOperands, |
| 152823 | // GIR_Coverage, 5813, |
| 152824 | GIR_EraseRootFromParent_Done, |
| 152825 | // Label 7206: @487185 |
| 152826 | GIM_Try, /*On fail goto*//*Label 7207*/ GIMT_Encode4(487255), // Rule ID 5801 // |
| 152827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152828 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152829 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152830 | // MIs[0] offset |
| 152831 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152832 | // MIs[0] auxiliary |
| 152833 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152834 | // MIs[0] Operand 8 |
| 152835 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152836 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152837 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_OFFEN_RTN), |
| 152839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152840 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152841 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152842 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152844 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152845 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152846 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152847 | GIR_RootConstrainSelectedInstOperands, |
| 152848 | // GIR_Coverage, 5801, |
| 152849 | GIR_EraseRootFromParent_Done, |
| 152850 | // Label 7207: @487255 |
| 152851 | GIM_Try, /*On fail goto*//*Label 7208*/ GIMT_Encode4(487322), // Rule ID 5809 // |
| 152852 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152853 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 152854 | // MIs[0] offset |
| 152855 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152856 | // MIs[0] auxiliary |
| 152857 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152858 | // MIs[0] Operand 8 |
| 152859 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 152860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152861 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_OFFEN_RTN), |
| 152863 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152864 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152865 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 152866 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152867 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152868 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152869 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152870 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152871 | GIR_RootConstrainSelectedInstOperands, |
| 152872 | // GIR_Coverage, 5809, |
| 152873 | GIR_EraseRootFromParent_Done, |
| 152874 | // Label 7208: @487322 |
| 152875 | GIM_Try, /*On fail goto*//*Label 7209*/ GIMT_Encode4(487380), // Rule ID 5804 // |
| 152876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152877 | GIM_CheckHasNoUse, /*MI*/0, |
| 152878 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152879 | // MIs[0] offset |
| 152880 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152881 | // MIs[0] auxiliary |
| 152882 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152883 | // MIs[0] Operand 8 |
| 152884 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152885 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152886 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152887 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN), |
| 152888 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152889 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152890 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152892 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152893 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152895 | GIR_RootConstrainSelectedInstOperands, |
| 152896 | // GIR_Coverage, 5804, |
| 152897 | GIR_EraseRootFromParent_Done, |
| 152898 | // Label 7209: @487380 |
| 152899 | GIM_Try, /*On fail goto*//*Label 7210*/ GIMT_Encode4(487435), // Rule ID 5812 // |
| 152900 | GIM_CheckHasNoUse, /*MI*/0, |
| 152901 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152902 | // MIs[0] offset |
| 152903 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152904 | // MIs[0] auxiliary |
| 152905 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152906 | // MIs[0] Operand 8 |
| 152907 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152909 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152910 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN), |
| 152911 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152912 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152913 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152914 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152915 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152916 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152918 | GIR_RootConstrainSelectedInstOperands, |
| 152919 | // GIR_Coverage, 5812, |
| 152920 | GIR_EraseRootFromParent_Done, |
| 152921 | // Label 7210: @487435 |
| 152922 | GIM_Try, /*On fail goto*//*Label 7211*/ GIMT_Encode4(487497), // Rule ID 5800 // |
| 152923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152924 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152925 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152926 | // MIs[0] offset |
| 152927 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152928 | // MIs[0] auxiliary |
| 152929 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152930 | // MIs[0] Operand 8 |
| 152931 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152933 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_IDXEN_RTN), |
| 152935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152936 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152937 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152938 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152940 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152943 | GIR_RootConstrainSelectedInstOperands, |
| 152944 | // GIR_Coverage, 5800, |
| 152945 | GIR_EraseRootFromParent_Done, |
| 152946 | // Label 7211: @487497 |
| 152947 | GIM_Try, /*On fail goto*//*Label 7212*/ GIMT_Encode4(487556), // Rule ID 5808 // |
| 152948 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 152949 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 152950 | // MIs[0] offset |
| 152951 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152952 | // MIs[0] auxiliary |
| 152953 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152954 | // MIs[0] Operand 8 |
| 152955 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152956 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152957 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152958 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_IDXEN_RTN), |
| 152959 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 152960 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152961 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 152962 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152964 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 152966 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 152967 | GIR_RootConstrainSelectedInstOperands, |
| 152968 | // GIR_Coverage, 5808, |
| 152969 | GIR_EraseRootFromParent_Done, |
| 152970 | // Label 7212: @487556 |
| 152971 | GIM_Try, /*On fail goto*//*Label 7213*/ GIMT_Encode4(487652), // Rule ID 5806 // |
| 152972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 152973 | GIM_CheckHasNoUse, /*MI*/0, |
| 152974 | // MIs[0] offset |
| 152975 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 152976 | // MIs[0] auxiliary |
| 152977 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 152978 | // MIs[0] Operand 8 |
| 152979 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 152980 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 152981 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 152982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 152983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 152984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 152985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 152986 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 152987 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 152988 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 152989 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 152990 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152991 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 152992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN), |
| 152993 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 152994 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 152995 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 152996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 152997 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 152998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 152999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153000 | GIR_RootConstrainSelectedInstOperands, |
| 153001 | // GIR_Coverage, 5806, |
| 153002 | GIR_EraseRootFromParent_Done, |
| 153003 | // Label 7213: @487652 |
| 153004 | GIM_Try, /*On fail goto*//*Label 7214*/ GIMT_Encode4(487745), // Rule ID 5814 // |
| 153005 | GIM_CheckHasNoUse, /*MI*/0, |
| 153006 | // MIs[0] offset |
| 153007 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153008 | // MIs[0] auxiliary |
| 153009 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153010 | // MIs[0] Operand 8 |
| 153011 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153013 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umax_noret>> => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153017 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153018 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153019 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153020 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153021 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153022 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153023 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN), |
| 153025 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153027 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153029 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153031 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153032 | GIR_RootConstrainSelectedInstOperands, |
| 153033 | // GIR_Coverage, 5814, |
| 153034 | GIR_EraseRootFromParent_Done, |
| 153035 | // Label 7214: @487745 |
| 153036 | GIM_Try, /*On fail goto*//*Label 7215*/ GIMT_Encode4(487845), // Rule ID 5802 // |
| 153037 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153038 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153039 | // MIs[0] offset |
| 153040 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153041 | // MIs[0] auxiliary |
| 153042 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153043 | // MIs[0] Operand 8 |
| 153044 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153046 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153047 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153048 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153049 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153050 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153051 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153052 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153053 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153055 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153056 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_BOTHEN_RTN), |
| 153058 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153059 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153060 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153061 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153063 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153066 | GIR_RootConstrainSelectedInstOperands, |
| 153067 | // GIR_Coverage, 5802, |
| 153068 | GIR_EraseRootFromParent_Done, |
| 153069 | // Label 7215: @487845 |
| 153070 | GIM_Try, /*On fail goto*//*Label 7216*/ GIMT_Encode4(487942), // Rule ID 5810 // |
| 153071 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153072 | // MIs[0] offset |
| 153073 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153074 | // MIs[0] auxiliary |
| 153075 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153076 | // MIs[0] Operand 8 |
| 153077 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153079 | // (SIbuffer_atomic_umax:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153080 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153081 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153082 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153083 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153084 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153085 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153086 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153087 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153088 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153089 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153090 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMAX_X2_VBUFFER_BOTHEN_RTN), |
| 153091 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153092 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153094 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153096 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153099 | GIR_RootConstrainSelectedInstOperands, |
| 153100 | // GIR_Coverage, 5810, |
| 153101 | GIR_EraseRootFromParent_Done, |
| 153102 | // Label 7216: @487942 |
| 153103 | GIM_Reject, |
| 153104 | // Label 7200: @487943 |
| 153105 | GIM_Reject, |
| 153106 | // Label 7182: @487944 |
| 153107 | GIM_Reject, |
| 153108 | // Label 123: @487945 |
| 153109 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7219*/ GIMT_Encode4(490328), |
| 153110 | /*GILLT_s32*//*Label 7217*/ GIMT_Encode4(487964), |
| 153111 | /*GILLT_s64*//*Label 7218*/ GIMT_Encode4(489146), |
| 153112 | // Label 7217: @487964 |
| 153113 | GIM_Try, /*On fail goto*//*Label 7220*/ GIMT_Encode4(489145), |
| 153114 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 153115 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 153116 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 153117 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 153118 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 153119 | GIM_Try, /*On fail goto*//*Label 7221*/ GIMT_Encode4(488052), // Rule ID 5571 // |
| 153120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153121 | GIM_CheckHasNoUse, /*MI*/0, |
| 153122 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153123 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153124 | // MIs[0] offset |
| 153125 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153126 | // MIs[0] auxiliary |
| 153127 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153128 | // MIs[0] Operand 8 |
| 153129 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153131 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153132 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET), |
| 153133 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153134 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153135 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153136 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153137 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153139 | GIR_RootConstrainSelectedInstOperands, |
| 153140 | // GIR_Coverage, 5571, |
| 153141 | GIR_EraseRootFromParent_Done, |
| 153142 | // Label 7221: @488052 |
| 153143 | GIM_Try, /*On fail goto*//*Label 7222*/ GIMT_Encode4(488117), // Rule ID 5579 // |
| 153144 | GIM_CheckHasNoUse, /*MI*/0, |
| 153145 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153146 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153147 | // MIs[0] offset |
| 153148 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153149 | // MIs[0] auxiliary |
| 153150 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153151 | // MIs[0] Operand 8 |
| 153152 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153154 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET), |
| 153156 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153157 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153159 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153160 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153161 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153162 | GIR_RootConstrainSelectedInstOperands, |
| 153163 | // GIR_Coverage, 5579, |
| 153164 | GIR_EraseRootFromParent_Done, |
| 153165 | // Label 7222: @488117 |
| 153166 | GIM_Try, /*On fail goto*//*Label 7223*/ GIMT_Encode4(488189), // Rule ID 5567 // |
| 153167 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153168 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153169 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153170 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153171 | // MIs[0] offset |
| 153172 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153173 | // MIs[0] auxiliary |
| 153174 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153175 | // MIs[0] Operand 8 |
| 153176 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153177 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153178 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153179 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFSET_RTN), |
| 153180 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153181 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153182 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153183 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153184 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153185 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153186 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153187 | GIR_RootConstrainSelectedInstOperands, |
| 153188 | // GIR_Coverage, 5567, |
| 153189 | GIR_EraseRootFromParent_Done, |
| 153190 | // Label 7223: @488189 |
| 153191 | GIM_Try, /*On fail goto*//*Label 7224*/ GIMT_Encode4(488258), // Rule ID 5575 // |
| 153192 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153193 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153194 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153195 | // MIs[0] offset |
| 153196 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153197 | // MIs[0] auxiliary |
| 153198 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153199 | // MIs[0] Operand 8 |
| 153200 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153202 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFSET_RTN), |
| 153204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153205 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153206 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153207 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153208 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153209 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153210 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153211 | GIR_RootConstrainSelectedInstOperands, |
| 153212 | // GIR_Coverage, 5575, |
| 153213 | GIR_EraseRootFromParent_Done, |
| 153214 | // Label 7224: @488258 |
| 153215 | GIM_Try, /*On fail goto*//*Label 7225*/ GIMT_Encode4(488324), // Rule ID 5573 // |
| 153216 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153217 | GIM_CheckHasNoUse, /*MI*/0, |
| 153218 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153219 | // MIs[0] offset |
| 153220 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153221 | // MIs[0] auxiliary |
| 153222 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153223 | // MIs[0] Operand 8 |
| 153224 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153225 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153226 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN), |
| 153228 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153229 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153230 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153232 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153233 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153234 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153235 | GIR_RootConstrainSelectedInstOperands, |
| 153236 | // GIR_Coverage, 5573, |
| 153237 | GIR_EraseRootFromParent_Done, |
| 153238 | // Label 7225: @488324 |
| 153239 | GIM_Try, /*On fail goto*//*Label 7226*/ GIMT_Encode4(488387), // Rule ID 5581 // |
| 153240 | GIM_CheckHasNoUse, /*MI*/0, |
| 153241 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153242 | // MIs[0] offset |
| 153243 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153244 | // MIs[0] auxiliary |
| 153245 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153246 | // MIs[0] Operand 8 |
| 153247 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153248 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153249 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153250 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN), |
| 153251 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153252 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153253 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153255 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153256 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153257 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153258 | GIR_RootConstrainSelectedInstOperands, |
| 153259 | // GIR_Coverage, 5581, |
| 153260 | GIR_EraseRootFromParent_Done, |
| 153261 | // Label 7226: @488387 |
| 153262 | GIM_Try, /*On fail goto*//*Label 7227*/ GIMT_Encode4(488457), // Rule ID 5569 // |
| 153263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153264 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153265 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153266 | // MIs[0] offset |
| 153267 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153268 | // MIs[0] auxiliary |
| 153269 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153270 | // MIs[0] Operand 8 |
| 153271 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153272 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153273 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_OFFEN_RTN), |
| 153275 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153276 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153277 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153278 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153279 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153280 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153281 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153282 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153283 | GIR_RootConstrainSelectedInstOperands, |
| 153284 | // GIR_Coverage, 5569, |
| 153285 | GIR_EraseRootFromParent_Done, |
| 153286 | // Label 7227: @488457 |
| 153287 | GIM_Try, /*On fail goto*//*Label 7228*/ GIMT_Encode4(488524), // Rule ID 5577 // |
| 153288 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153289 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153290 | // MIs[0] offset |
| 153291 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153292 | // MIs[0] auxiliary |
| 153293 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153294 | // MIs[0] Operand 8 |
| 153295 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153296 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153297 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153298 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_OFFEN_RTN), |
| 153299 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153300 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153301 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153302 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153304 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153306 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153307 | GIR_RootConstrainSelectedInstOperands, |
| 153308 | // GIR_Coverage, 5577, |
| 153309 | GIR_EraseRootFromParent_Done, |
| 153310 | // Label 7228: @488524 |
| 153311 | GIM_Try, /*On fail goto*//*Label 7229*/ GIMT_Encode4(488582), // Rule ID 5572 // |
| 153312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153313 | GIM_CheckHasNoUse, /*MI*/0, |
| 153314 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153315 | // MIs[0] offset |
| 153316 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153317 | // MIs[0] auxiliary |
| 153318 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153319 | // MIs[0] Operand 8 |
| 153320 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153322 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN), |
| 153324 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153325 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153326 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153328 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153329 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153330 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153331 | GIR_RootConstrainSelectedInstOperands, |
| 153332 | // GIR_Coverage, 5572, |
| 153333 | GIR_EraseRootFromParent_Done, |
| 153334 | // Label 7229: @488582 |
| 153335 | GIM_Try, /*On fail goto*//*Label 7230*/ GIMT_Encode4(488637), // Rule ID 5580 // |
| 153336 | GIM_CheckHasNoUse, /*MI*/0, |
| 153337 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153338 | // MIs[0] offset |
| 153339 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153340 | // MIs[0] auxiliary |
| 153341 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153342 | // MIs[0] Operand 8 |
| 153343 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153345 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN), |
| 153347 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153348 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153349 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153351 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153354 | GIR_RootConstrainSelectedInstOperands, |
| 153355 | // GIR_Coverage, 5580, |
| 153356 | GIR_EraseRootFromParent_Done, |
| 153357 | // Label 7230: @488637 |
| 153358 | GIM_Try, /*On fail goto*//*Label 7231*/ GIMT_Encode4(488699), // Rule ID 5568 // |
| 153359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153360 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153362 | // MIs[0] offset |
| 153363 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153364 | // MIs[0] auxiliary |
| 153365 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153366 | // MIs[0] Operand 8 |
| 153367 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153369 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_IDXEN_RTN), |
| 153371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153372 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153373 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153374 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153376 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153377 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153378 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153379 | GIR_RootConstrainSelectedInstOperands, |
| 153380 | // GIR_Coverage, 5568, |
| 153381 | GIR_EraseRootFromParent_Done, |
| 153382 | // Label 7231: @488699 |
| 153383 | GIM_Try, /*On fail goto*//*Label 7232*/ GIMT_Encode4(488758), // Rule ID 5576 // |
| 153384 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153385 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153386 | // MIs[0] offset |
| 153387 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153388 | // MIs[0] auxiliary |
| 153389 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153390 | // MIs[0] Operand 8 |
| 153391 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153392 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153393 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_IDXEN_RTN), |
| 153395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153396 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153397 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153398 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153400 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153401 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153402 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153403 | GIR_RootConstrainSelectedInstOperands, |
| 153404 | // GIR_Coverage, 5576, |
| 153405 | GIR_EraseRootFromParent_Done, |
| 153406 | // Label 7232: @488758 |
| 153407 | GIM_Try, /*On fail goto*//*Label 7233*/ GIMT_Encode4(488854), // Rule ID 5574 // |
| 153408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153409 | GIM_CheckHasNoUse, /*MI*/0, |
| 153410 | // MIs[0] offset |
| 153411 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153412 | // MIs[0] auxiliary |
| 153413 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153414 | // MIs[0] Operand 8 |
| 153415 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153417 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153418 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153421 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153422 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153423 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153424 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153425 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153426 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153427 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN), |
| 153429 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153431 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153433 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153434 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153435 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153436 | GIR_RootConstrainSelectedInstOperands, |
| 153437 | // GIR_Coverage, 5574, |
| 153438 | GIR_EraseRootFromParent_Done, |
| 153439 | // Label 7233: @488854 |
| 153440 | GIM_Try, /*On fail goto*//*Label 7234*/ GIMT_Encode4(488947), // Rule ID 5582 // |
| 153441 | GIM_CheckHasNoUse, /*MI*/0, |
| 153442 | // MIs[0] offset |
| 153443 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153444 | // MIs[0] auxiliary |
| 153445 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153446 | // MIs[0] Operand 8 |
| 153447 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153449 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153453 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153454 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153455 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153456 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153457 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153458 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153459 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN), |
| 153461 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153463 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153465 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153466 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153467 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153468 | GIR_RootConstrainSelectedInstOperands, |
| 153469 | // GIR_Coverage, 5582, |
| 153470 | GIR_EraseRootFromParent_Done, |
| 153471 | // Label 7234: @488947 |
| 153472 | GIM_Try, /*On fail goto*//*Label 7235*/ GIMT_Encode4(489047), // Rule ID 5570 // |
| 153473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153474 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153475 | // MIs[0] offset |
| 153476 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153477 | // MIs[0] auxiliary |
| 153478 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153479 | // MIs[0] Operand 8 |
| 153480 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153482 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153483 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153484 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153485 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153486 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153487 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153488 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153489 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153490 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153491 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153492 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_BOTHEN_RTN), |
| 153494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153495 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153496 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153497 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153498 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153499 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153500 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153502 | GIR_RootConstrainSelectedInstOperands, |
| 153503 | // GIR_Coverage, 5570, |
| 153504 | GIR_EraseRootFromParent_Done, |
| 153505 | // Label 7235: @489047 |
| 153506 | GIM_Try, /*On fail goto*//*Label 7236*/ GIMT_Encode4(489144), // Rule ID 5578 // |
| 153507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 153508 | // MIs[0] offset |
| 153509 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153510 | // MIs[0] auxiliary |
| 153511 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153512 | // MIs[0] Operand 8 |
| 153513 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153515 | // (SIbuffer_atomic_umin:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153516 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153517 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153518 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153519 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153520 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153521 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153522 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153523 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153524 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153525 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_VBUFFER_BOTHEN_RTN), |
| 153527 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153528 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153529 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153530 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153532 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153533 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153535 | GIR_RootConstrainSelectedInstOperands, |
| 153536 | // GIR_Coverage, 5578, |
| 153537 | GIR_EraseRootFromParent_Done, |
| 153538 | // Label 7236: @489144 |
| 153539 | GIM_Reject, |
| 153540 | // Label 7220: @489145 |
| 153541 | GIM_Reject, |
| 153542 | // Label 7218: @489146 |
| 153543 | GIM_Try, /*On fail goto*//*Label 7237*/ GIMT_Encode4(490327), |
| 153544 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 153545 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 153546 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 153547 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 153548 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 153549 | GIM_Try, /*On fail goto*//*Label 7238*/ GIMT_Encode4(489234), // Rule ID 5771 // |
| 153550 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153551 | GIM_CheckHasNoUse, /*MI*/0, |
| 153552 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153553 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153554 | // MIs[0] offset |
| 153555 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153556 | // MIs[0] auxiliary |
| 153557 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153558 | // MIs[0] Operand 8 |
| 153559 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153561 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153562 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET), |
| 153563 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153564 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153566 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153569 | GIR_RootConstrainSelectedInstOperands, |
| 153570 | // GIR_Coverage, 5771, |
| 153571 | GIR_EraseRootFromParent_Done, |
| 153572 | // Label 7238: @489234 |
| 153573 | GIM_Try, /*On fail goto*//*Label 7239*/ GIMT_Encode4(489299), // Rule ID 5779 // |
| 153574 | GIM_CheckHasNoUse, /*MI*/0, |
| 153575 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153576 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153577 | // MIs[0] offset |
| 153578 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153579 | // MIs[0] auxiliary |
| 153580 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153581 | // MIs[0] Operand 8 |
| 153582 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153584 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET), |
| 153586 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153587 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153589 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153591 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153592 | GIR_RootConstrainSelectedInstOperands, |
| 153593 | // GIR_Coverage, 5779, |
| 153594 | GIR_EraseRootFromParent_Done, |
| 153595 | // Label 7239: @489299 |
| 153596 | GIM_Try, /*On fail goto*//*Label 7240*/ GIMT_Encode4(489371), // Rule ID 5767 // |
| 153597 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153598 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153599 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153600 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153601 | // MIs[0] offset |
| 153602 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153603 | // MIs[0] auxiliary |
| 153604 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153605 | // MIs[0] Operand 8 |
| 153606 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153607 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153608 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153609 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFSET_RTN), |
| 153610 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153611 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153612 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153613 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153614 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153615 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153617 | GIR_RootConstrainSelectedInstOperands, |
| 153618 | // GIR_Coverage, 5767, |
| 153619 | GIR_EraseRootFromParent_Done, |
| 153620 | // Label 7240: @489371 |
| 153621 | GIM_Try, /*On fail goto*//*Label 7241*/ GIMT_Encode4(489440), // Rule ID 5775 // |
| 153622 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153623 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153624 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153625 | // MIs[0] offset |
| 153626 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153627 | // MIs[0] auxiliary |
| 153628 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153629 | // MIs[0] Operand 8 |
| 153630 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153632 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFSET_RTN), |
| 153634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153635 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153636 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153637 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153638 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153639 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153640 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153641 | GIR_RootConstrainSelectedInstOperands, |
| 153642 | // GIR_Coverage, 5775, |
| 153643 | GIR_EraseRootFromParent_Done, |
| 153644 | // Label 7241: @489440 |
| 153645 | GIM_Try, /*On fail goto*//*Label 7242*/ GIMT_Encode4(489506), // Rule ID 5773 // |
| 153646 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153647 | GIM_CheckHasNoUse, /*MI*/0, |
| 153648 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153649 | // MIs[0] offset |
| 153650 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153651 | // MIs[0] auxiliary |
| 153652 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153653 | // MIs[0] Operand 8 |
| 153654 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153656 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN), |
| 153658 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153659 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153660 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153662 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153663 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153664 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153665 | GIR_RootConstrainSelectedInstOperands, |
| 153666 | // GIR_Coverage, 5773, |
| 153667 | GIR_EraseRootFromParent_Done, |
| 153668 | // Label 7242: @489506 |
| 153669 | GIM_Try, /*On fail goto*//*Label 7243*/ GIMT_Encode4(489569), // Rule ID 5781 // |
| 153670 | GIM_CheckHasNoUse, /*MI*/0, |
| 153671 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153672 | // MIs[0] offset |
| 153673 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153674 | // MIs[0] auxiliary |
| 153675 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153676 | // MIs[0] Operand 8 |
| 153677 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153679 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN), |
| 153681 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153682 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153683 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153685 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153686 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153688 | GIR_RootConstrainSelectedInstOperands, |
| 153689 | // GIR_Coverage, 5781, |
| 153690 | GIR_EraseRootFromParent_Done, |
| 153691 | // Label 7243: @489569 |
| 153692 | GIM_Try, /*On fail goto*//*Label 7244*/ GIMT_Encode4(489639), // Rule ID 5769 // |
| 153693 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153694 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153696 | // MIs[0] offset |
| 153697 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153698 | // MIs[0] auxiliary |
| 153699 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153700 | // MIs[0] Operand 8 |
| 153701 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153703 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_OFFEN_RTN), |
| 153705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153706 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153707 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153708 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153710 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153713 | GIR_RootConstrainSelectedInstOperands, |
| 153714 | // GIR_Coverage, 5769, |
| 153715 | GIR_EraseRootFromParent_Done, |
| 153716 | // Label 7244: @489639 |
| 153717 | GIM_Try, /*On fail goto*//*Label 7245*/ GIMT_Encode4(489706), // Rule ID 5777 // |
| 153718 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153719 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153720 | // MIs[0] offset |
| 153721 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153722 | // MIs[0] auxiliary |
| 153723 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153724 | // MIs[0] Operand 8 |
| 153725 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153726 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153727 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_OFFEN_RTN), |
| 153729 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153730 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153731 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 153732 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153734 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153735 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153737 | GIR_RootConstrainSelectedInstOperands, |
| 153738 | // GIR_Coverage, 5777, |
| 153739 | GIR_EraseRootFromParent_Done, |
| 153740 | // Label 7245: @489706 |
| 153741 | GIM_Try, /*On fail goto*//*Label 7246*/ GIMT_Encode4(489764), // Rule ID 5772 // |
| 153742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153743 | GIM_CheckHasNoUse, /*MI*/0, |
| 153744 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153745 | // MIs[0] offset |
| 153746 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153747 | // MIs[0] auxiliary |
| 153748 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153749 | // MIs[0] Operand 8 |
| 153750 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153752 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN), |
| 153754 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153755 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153756 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153758 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153759 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153760 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153761 | GIR_RootConstrainSelectedInstOperands, |
| 153762 | // GIR_Coverage, 5772, |
| 153763 | GIR_EraseRootFromParent_Done, |
| 153764 | // Label 7246: @489764 |
| 153765 | GIM_Try, /*On fail goto*//*Label 7247*/ GIMT_Encode4(489819), // Rule ID 5780 // |
| 153766 | GIM_CheckHasNoUse, /*MI*/0, |
| 153767 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153768 | // MIs[0] offset |
| 153769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153770 | // MIs[0] auxiliary |
| 153771 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153772 | // MIs[0] Operand 8 |
| 153773 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153775 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN), |
| 153777 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153778 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153779 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153781 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153783 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153784 | GIR_RootConstrainSelectedInstOperands, |
| 153785 | // GIR_Coverage, 5780, |
| 153786 | GIR_EraseRootFromParent_Done, |
| 153787 | // Label 7247: @489819 |
| 153788 | GIM_Try, /*On fail goto*//*Label 7248*/ GIMT_Encode4(489881), // Rule ID 5768 // |
| 153789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153790 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153792 | // MIs[0] offset |
| 153793 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153794 | // MIs[0] auxiliary |
| 153795 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153796 | // MIs[0] Operand 8 |
| 153797 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153798 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153799 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153800 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_IDXEN_RTN), |
| 153801 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153802 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153803 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153804 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153806 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153809 | GIR_RootConstrainSelectedInstOperands, |
| 153810 | // GIR_Coverage, 5768, |
| 153811 | GIR_EraseRootFromParent_Done, |
| 153812 | // Label 7248: @489881 |
| 153813 | GIM_Try, /*On fail goto*//*Label 7249*/ GIMT_Encode4(489940), // Rule ID 5776 // |
| 153814 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153815 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153816 | // MIs[0] offset |
| 153817 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153818 | // MIs[0] auxiliary |
| 153819 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153820 | // MIs[0] Operand 8 |
| 153821 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153822 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153823 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_IDXEN_RTN), |
| 153825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153826 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153827 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 153828 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153829 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153830 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153831 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153832 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153833 | GIR_RootConstrainSelectedInstOperands, |
| 153834 | // GIR_Coverage, 5776, |
| 153835 | GIR_EraseRootFromParent_Done, |
| 153836 | // Label 7249: @489940 |
| 153837 | GIM_Try, /*On fail goto*//*Label 7250*/ GIMT_Encode4(490036), // Rule ID 5774 // |
| 153838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153839 | GIM_CheckHasNoUse, /*MI*/0, |
| 153840 | // MIs[0] offset |
| 153841 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153842 | // MIs[0] auxiliary |
| 153843 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153844 | // MIs[0] Operand 8 |
| 153845 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153847 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153848 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153849 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153850 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153851 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153852 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153853 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153854 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153855 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153856 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153857 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153858 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN), |
| 153859 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153860 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153861 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153862 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153863 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153864 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153865 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153866 | GIR_RootConstrainSelectedInstOperands, |
| 153867 | // GIR_Coverage, 5774, |
| 153868 | GIR_EraseRootFromParent_Done, |
| 153869 | // Label 7250: @490036 |
| 153870 | GIM_Try, /*On fail goto*//*Label 7251*/ GIMT_Encode4(490129), // Rule ID 5782 // |
| 153871 | GIM_CheckHasNoUse, /*MI*/0, |
| 153872 | // MIs[0] offset |
| 153873 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153874 | // MIs[0] auxiliary |
| 153875 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153876 | // MIs[0] Operand 8 |
| 153877 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153879 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_umin_noret>> => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153880 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153881 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153882 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153883 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153884 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153885 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153886 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153887 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153888 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153889 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153890 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN), |
| 153891 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153892 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153893 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153895 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153896 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 153897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153898 | GIR_RootConstrainSelectedInstOperands, |
| 153899 | // GIR_Coverage, 5782, |
| 153900 | GIR_EraseRootFromParent_Done, |
| 153901 | // Label 7251: @490129 |
| 153902 | GIM_Try, /*On fail goto*//*Label 7252*/ GIMT_Encode4(490229), // Rule ID 5770 // |
| 153903 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153905 | // MIs[0] offset |
| 153906 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153907 | // MIs[0] auxiliary |
| 153908 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153909 | // MIs[0] Operand 8 |
| 153910 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153912 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153913 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153914 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153915 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153916 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153917 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153918 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153919 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153920 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153921 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153922 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153923 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_BOTHEN_RTN), |
| 153924 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153925 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153926 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153927 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153928 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153929 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153930 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153931 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153932 | GIR_RootConstrainSelectedInstOperands, |
| 153933 | // GIR_Coverage, 5770, |
| 153934 | GIR_EraseRootFromParent_Done, |
| 153935 | // Label 7252: @490229 |
| 153936 | GIM_Try, /*On fail goto*//*Label 7253*/ GIMT_Encode4(490326), // Rule ID 5778 // |
| 153937 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 153938 | // MIs[0] offset |
| 153939 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153940 | // MIs[0] auxiliary |
| 153941 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153942 | // MIs[0] Operand 8 |
| 153943 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 153944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153945 | // (SIbuffer_atomic_umin:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153946 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 153947 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 153948 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 153949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 153950 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 153951 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 153952 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 153953 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 153954 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153955 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 153956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_UMIN_X2_VBUFFER_BOTHEN_RTN), |
| 153957 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 153958 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 153959 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 153960 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 153961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 153962 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 153963 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 153964 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 153965 | GIR_RootConstrainSelectedInstOperands, |
| 153966 | // GIR_Coverage, 5778, |
| 153967 | GIR_EraseRootFromParent_Done, |
| 153968 | // Label 7253: @490326 |
| 153969 | GIM_Reject, |
| 153970 | // Label 7237: @490327 |
| 153971 | GIM_Reject, |
| 153972 | // Label 7219: @490328 |
| 153973 | GIM_Reject, |
| 153974 | // Label 124: @490329 |
| 153975 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 7256*/ GIMT_Encode4(492712), |
| 153976 | /*GILLT_s32*//*Label 7254*/ GIMT_Encode4(490348), |
| 153977 | /*GILLT_s64*//*Label 7255*/ GIMT_Encode4(491530), |
| 153978 | // Label 7254: @490348 |
| 153979 | GIM_Try, /*On fail goto*//*Label 7257*/ GIMT_Encode4(491529), |
| 153980 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 153981 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 153982 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 153983 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 153984 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 153985 | GIM_Try, /*On fail goto*//*Label 7258*/ GIMT_Encode4(490436), // Rule ID 5651 // |
| 153986 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 153987 | GIM_CheckHasNoUse, /*MI*/0, |
| 153988 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 153989 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 153990 | // MIs[0] offset |
| 153991 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 153992 | // MIs[0] auxiliary |
| 153993 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 153994 | // MIs[0] Operand 8 |
| 153995 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 153996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 153997 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 153998 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET), |
| 153999 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154000 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154002 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154003 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154004 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154005 | GIR_RootConstrainSelectedInstOperands, |
| 154006 | // GIR_Coverage, 5651, |
| 154007 | GIR_EraseRootFromParent_Done, |
| 154008 | // Label 7258: @490436 |
| 154009 | GIM_Try, /*On fail goto*//*Label 7259*/ GIMT_Encode4(490501), // Rule ID 5659 // |
| 154010 | GIM_CheckHasNoUse, /*MI*/0, |
| 154011 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154013 | // MIs[0] offset |
| 154014 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154015 | // MIs[0] auxiliary |
| 154016 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154017 | // MIs[0] Operand 8 |
| 154018 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154020 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET), |
| 154022 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154023 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154025 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154026 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154027 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154028 | GIR_RootConstrainSelectedInstOperands, |
| 154029 | // GIR_Coverage, 5659, |
| 154030 | GIR_EraseRootFromParent_Done, |
| 154031 | // Label 7259: @490501 |
| 154032 | GIM_Try, /*On fail goto*//*Label 7260*/ GIMT_Encode4(490573), // Rule ID 5647 // |
| 154033 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154034 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154035 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154036 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154037 | // MIs[0] offset |
| 154038 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154039 | // MIs[0] auxiliary |
| 154040 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154041 | // MIs[0] Operand 8 |
| 154042 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154043 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154044 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154045 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFSET_RTN), |
| 154046 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154047 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154048 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154049 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154050 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154051 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154053 | GIR_RootConstrainSelectedInstOperands, |
| 154054 | // GIR_Coverage, 5647, |
| 154055 | GIR_EraseRootFromParent_Done, |
| 154056 | // Label 7260: @490573 |
| 154057 | GIM_Try, /*On fail goto*//*Label 7261*/ GIMT_Encode4(490642), // Rule ID 5655 // |
| 154058 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154060 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154061 | // MIs[0] offset |
| 154062 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154063 | // MIs[0] auxiliary |
| 154064 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154065 | // MIs[0] Operand 8 |
| 154066 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154067 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154068 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154069 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFSET_RTN), |
| 154070 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154071 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154072 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154074 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154075 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154077 | GIR_RootConstrainSelectedInstOperands, |
| 154078 | // GIR_Coverage, 5655, |
| 154079 | GIR_EraseRootFromParent_Done, |
| 154080 | // Label 7261: @490642 |
| 154081 | GIM_Try, /*On fail goto*//*Label 7262*/ GIMT_Encode4(490708), // Rule ID 5653 // |
| 154082 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154083 | GIM_CheckHasNoUse, /*MI*/0, |
| 154084 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154085 | // MIs[0] offset |
| 154086 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154087 | // MIs[0] auxiliary |
| 154088 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154089 | // MIs[0] Operand 8 |
| 154090 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154091 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154092 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154093 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFEN), |
| 154094 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154095 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154096 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154098 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154099 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154100 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154101 | GIR_RootConstrainSelectedInstOperands, |
| 154102 | // GIR_Coverage, 5653, |
| 154103 | GIR_EraseRootFromParent_Done, |
| 154104 | // Label 7262: @490708 |
| 154105 | GIM_Try, /*On fail goto*//*Label 7263*/ GIMT_Encode4(490771), // Rule ID 5661 // |
| 154106 | GIM_CheckHasNoUse, /*MI*/0, |
| 154107 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154108 | // MIs[0] offset |
| 154109 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154110 | // MIs[0] auxiliary |
| 154111 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154112 | // MIs[0] Operand 8 |
| 154113 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154114 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154115 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_VBUFFER_OFFEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154116 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN), |
| 154117 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154118 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154119 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154120 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154121 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154122 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154123 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154124 | GIR_RootConstrainSelectedInstOperands, |
| 154125 | // GIR_Coverage, 5661, |
| 154126 | GIR_EraseRootFromParent_Done, |
| 154127 | // Label 7263: @490771 |
| 154128 | GIM_Try, /*On fail goto*//*Label 7264*/ GIMT_Encode4(490841), // Rule ID 5649 // |
| 154129 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154130 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154131 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154132 | // MIs[0] offset |
| 154133 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154134 | // MIs[0] auxiliary |
| 154135 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154136 | // MIs[0] Operand 8 |
| 154137 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154139 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_OFFEN_RTN), |
| 154141 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154142 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154143 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154144 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154146 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154148 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154149 | GIR_RootConstrainSelectedInstOperands, |
| 154150 | // GIR_Coverage, 5649, |
| 154151 | GIR_EraseRootFromParent_Done, |
| 154152 | // Label 7264: @490841 |
| 154153 | GIM_Try, /*On fail goto*//*Label 7265*/ GIMT_Encode4(490908), // Rule ID 5657 // |
| 154154 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154155 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154156 | // MIs[0] offset |
| 154157 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154158 | // MIs[0] auxiliary |
| 154159 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154160 | // MIs[0] Operand 8 |
| 154161 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154163 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_OFFEN_RTN), |
| 154165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154166 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154167 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154168 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154170 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154171 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154173 | GIR_RootConstrainSelectedInstOperands, |
| 154174 | // GIR_Coverage, 5657, |
| 154175 | GIR_EraseRootFromParent_Done, |
| 154176 | // Label 7265: @490908 |
| 154177 | GIM_Try, /*On fail goto*//*Label 7266*/ GIMT_Encode4(490966), // Rule ID 5652 // |
| 154178 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154179 | GIM_CheckHasNoUse, /*MI*/0, |
| 154180 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154181 | // MIs[0] offset |
| 154182 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154183 | // MIs[0] auxiliary |
| 154184 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154185 | // MIs[0] Operand 8 |
| 154186 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154188 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_IDXEN), |
| 154190 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154191 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154192 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154194 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154196 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154197 | GIR_RootConstrainSelectedInstOperands, |
| 154198 | // GIR_Coverage, 5652, |
| 154199 | GIR_EraseRootFromParent_Done, |
| 154200 | // Label 7266: @490966 |
| 154201 | GIM_Try, /*On fail goto*//*Label 7267*/ GIMT_Encode4(491021), // Rule ID 5660 // |
| 154202 | GIM_CheckHasNoUse, /*MI*/0, |
| 154203 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154204 | // MIs[0] offset |
| 154205 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154206 | // MIs[0] auxiliary |
| 154207 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154208 | // MIs[0] Operand 8 |
| 154209 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154211 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_VBUFFER_IDXEN anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN), |
| 154213 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154214 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154215 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154217 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154220 | GIR_RootConstrainSelectedInstOperands, |
| 154221 | // GIR_Coverage, 5660, |
| 154222 | GIR_EraseRootFromParent_Done, |
| 154223 | // Label 7267: @491021 |
| 154224 | GIM_Try, /*On fail goto*//*Label 7268*/ GIMT_Encode4(491083), // Rule ID 5648 // |
| 154225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154226 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154227 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154228 | // MIs[0] offset |
| 154229 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154230 | // MIs[0] auxiliary |
| 154231 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154232 | // MIs[0] Operand 8 |
| 154233 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154235 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_IDXEN_RTN), |
| 154237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154238 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154239 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154240 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154241 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154242 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154243 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154245 | GIR_RootConstrainSelectedInstOperands, |
| 154246 | // GIR_Coverage, 5648, |
| 154247 | GIR_EraseRootFromParent_Done, |
| 154248 | // Label 7268: @491083 |
| 154249 | GIM_Try, /*On fail goto*//*Label 7269*/ GIMT_Encode4(491142), // Rule ID 5656 // |
| 154250 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154251 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154252 | // MIs[0] offset |
| 154253 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154254 | // MIs[0] auxiliary |
| 154255 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154256 | // MIs[0] Operand 8 |
| 154257 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154259 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_IDXEN_RTN), |
| 154261 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154262 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154263 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154264 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154265 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154266 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154267 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154268 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154269 | GIR_RootConstrainSelectedInstOperands, |
| 154270 | // GIR_Coverage, 5656, |
| 154271 | GIR_EraseRootFromParent_Done, |
| 154272 | // Label 7269: @491142 |
| 154273 | GIM_Try, /*On fail goto*//*Label 7270*/ GIMT_Encode4(491238), // Rule ID 5654 // |
| 154274 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154275 | GIM_CheckHasNoUse, /*MI*/0, |
| 154276 | // MIs[0] offset |
| 154277 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154278 | // MIs[0] auxiliary |
| 154279 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154280 | // MIs[0] Operand 8 |
| 154281 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154282 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154283 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154284 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154285 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154286 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154287 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154288 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154289 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154290 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154291 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154292 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154293 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN), |
| 154295 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154296 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154297 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154299 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154302 | GIR_RootConstrainSelectedInstOperands, |
| 154303 | // GIR_Coverage, 5654, |
| 154304 | GIR_EraseRootFromParent_Done, |
| 154305 | // Label 7270: @491238 |
| 154306 | GIM_Try, /*On fail goto*//*Label 7271*/ GIMT_Encode4(491331), // Rule ID 5662 // |
| 154307 | GIM_CheckHasNoUse, /*MI*/0, |
| 154308 | // MIs[0] offset |
| 154309 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154310 | // MIs[0] auxiliary |
| 154311 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154312 | // MIs[0] Operand 8 |
| 154313 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154315 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154316 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154317 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154318 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154319 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154320 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154321 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154322 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154323 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154324 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154325 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN), |
| 154327 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154328 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154329 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154331 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154332 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154334 | GIR_RootConstrainSelectedInstOperands, |
| 154335 | // GIR_Coverage, 5662, |
| 154336 | GIR_EraseRootFromParent_Done, |
| 154337 | // Label 7271: @491331 |
| 154338 | GIM_Try, /*On fail goto*//*Label 7272*/ GIMT_Encode4(491431), // Rule ID 5650 // |
| 154339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154341 | // MIs[0] offset |
| 154342 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154343 | // MIs[0] auxiliary |
| 154344 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154345 | // MIs[0] Operand 8 |
| 154346 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154347 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154348 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154349 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154350 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154351 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154352 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154353 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154354 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154355 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154356 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154357 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154358 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_BOTHEN_RTN), |
| 154360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154361 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154363 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154365 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154366 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154368 | GIR_RootConstrainSelectedInstOperands, |
| 154369 | // GIR_Coverage, 5650, |
| 154370 | GIR_EraseRootFromParent_Done, |
| 154371 | // Label 7272: @491431 |
| 154372 | GIM_Try, /*On fail goto*//*Label 7273*/ GIMT_Encode4(491528), // Rule ID 5658 // |
| 154373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 154374 | // MIs[0] offset |
| 154375 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154376 | // MIs[0] auxiliary |
| 154377 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154378 | // MIs[0] Operand 8 |
| 154379 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154381 | // (SIbuffer_atomic_xor:{ *:[i32] } i32:{ *:[i32] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN:{ *:[i32] } anonymous_15876:{ *:[i32] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154382 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154385 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154386 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154387 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154388 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154389 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154390 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154391 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_VBUFFER_BOTHEN_RTN), |
| 154393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154394 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154395 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154396 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154398 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154401 | GIR_RootConstrainSelectedInstOperands, |
| 154402 | // GIR_Coverage, 5658, |
| 154403 | GIR_EraseRootFromParent_Done, |
| 154404 | // Label 7273: @491528 |
| 154405 | GIM_Reject, |
| 154406 | // Label 7257: @491529 |
| 154407 | GIM_Reject, |
| 154408 | // Label 7255: @491530 |
| 154409 | GIM_Try, /*On fail goto*//*Label 7274*/ GIMT_Encode4(492711), |
| 154410 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 154411 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_v4s32, |
| 154412 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 154413 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 154414 | GIM_RootCheckType, /*Op*/5, /*Type*/GILLT_s32, |
| 154415 | GIM_Try, /*On fail goto*//*Label 7275*/ GIMT_Encode4(491618), // Rule ID 5851 // |
| 154416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154417 | GIM_CheckHasNoUse, /*MI*/0, |
| 154418 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154419 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154420 | // MIs[0] offset |
| 154421 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154422 | // MIs[0] auxiliary |
| 154423 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154424 | // MIs[0] Operand 8 |
| 154425 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154427 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET), |
| 154429 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154430 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154431 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154432 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154433 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154435 | GIR_RootConstrainSelectedInstOperands, |
| 154436 | // GIR_Coverage, 5851, |
| 154437 | GIR_EraseRootFromParent_Done, |
| 154438 | // Label 7275: @491618 |
| 154439 | GIM_Try, /*On fail goto*//*Label 7276*/ GIMT_Encode4(491683), // Rule ID 5859 // |
| 154440 | GIM_CheckHasNoUse, /*MI*/0, |
| 154441 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154442 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154443 | // MIs[0] offset |
| 154444 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154445 | // MIs[0] auxiliary |
| 154446 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154447 | // MIs[0] Operand 8 |
| 154448 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154450 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154451 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET), |
| 154452 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154453 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154455 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154456 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154458 | GIR_RootConstrainSelectedInstOperands, |
| 154459 | // GIR_Coverage, 5859, |
| 154460 | GIR_EraseRootFromParent_Done, |
| 154461 | // Label 7276: @491683 |
| 154462 | GIM_Try, /*On fail goto*//*Label 7277*/ GIMT_Encode4(491755), // Rule ID 5847 // |
| 154463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154464 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154466 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154467 | // MIs[0] offset |
| 154468 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154469 | // MIs[0] auxiliary |
| 154470 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154471 | // MIs[0] Operand 8 |
| 154472 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154473 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154474 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_X2_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154475 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFSET_RTN), |
| 154476 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154477 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154478 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154479 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154480 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154481 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154482 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154483 | GIR_RootConstrainSelectedInstOperands, |
| 154484 | // GIR_Coverage, 5847, |
| 154485 | GIR_EraseRootFromParent_Done, |
| 154486 | // Label 7277: @491755 |
| 154487 | GIM_Try, /*On fail goto*//*Label 7278*/ GIMT_Encode4(491824), // Rule ID 5855 // |
| 154488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154489 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154490 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154491 | // MIs[0] offset |
| 154492 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154493 | // MIs[0] auxiliary |
| 154494 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154495 | // MIs[0] Operand 8 |
| 154496 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154497 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154498 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154499 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFSET_RTN), |
| 154500 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154501 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154502 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154503 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154504 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154505 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154507 | GIR_RootConstrainSelectedInstOperands, |
| 154508 | // GIR_Coverage, 5855, |
| 154509 | GIR_EraseRootFromParent_Done, |
| 154510 | // Label 7278: @491824 |
| 154511 | GIM_Try, /*On fail goto*//*Label 7279*/ GIMT_Encode4(491890), // Rule ID 5853 // |
| 154512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154513 | GIM_CheckHasNoUse, /*MI*/0, |
| 154514 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154515 | // MIs[0] offset |
| 154516 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154517 | // MIs[0] auxiliary |
| 154518 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154519 | // MIs[0] Operand 8 |
| 154520 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154522 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN), |
| 154524 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154525 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154526 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154528 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154529 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154531 | GIR_RootConstrainSelectedInstOperands, |
| 154532 | // GIR_Coverage, 5853, |
| 154533 | GIR_EraseRootFromParent_Done, |
| 154534 | // Label 7279: @491890 |
| 154535 | GIM_Try, /*On fail goto*//*Label 7280*/ GIMT_Encode4(491953), // Rule ID 5861 // |
| 154536 | GIM_CheckHasNoUse, /*MI*/0, |
| 154537 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154538 | // MIs[0] offset |
| 154539 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154540 | // MIs[0] auxiliary |
| 154541 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154542 | // MIs[0] Operand 8 |
| 154543 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154545 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN), |
| 154547 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154548 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154549 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154550 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154551 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154552 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154554 | GIR_RootConstrainSelectedInstOperands, |
| 154555 | // GIR_Coverage, 5861, |
| 154556 | GIR_EraseRootFromParent_Done, |
| 154557 | // Label 7280: @491953 |
| 154558 | GIM_Try, /*On fail goto*//*Label 7281*/ GIMT_Encode4(492023), // Rule ID 5849 // |
| 154559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154561 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154562 | // MIs[0] offset |
| 154563 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154564 | // MIs[0] auxiliary |
| 154565 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154566 | // MIs[0] Operand 8 |
| 154567 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154568 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154569 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_X2_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_OFFEN_RTN), |
| 154571 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154572 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154573 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154574 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154575 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154576 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154577 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154578 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154579 | GIR_RootConstrainSelectedInstOperands, |
| 154580 | // GIR_Coverage, 5849, |
| 154581 | GIR_EraseRootFromParent_Done, |
| 154582 | // Label 7281: @492023 |
| 154583 | GIM_Try, /*On fail goto*//*Label 7282*/ GIMT_Encode4(492090), // Rule ID 5857 // |
| 154584 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154585 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154586 | // MIs[0] offset |
| 154587 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154588 | // MIs[0] auxiliary |
| 154589 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154590 | // MIs[0] Operand 8 |
| 154591 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 154592 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154593 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_OFFEN_RTN), |
| 154595 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154596 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154597 | GIR_RootToRootCopy, /*OpIdx*/4, // voffset |
| 154598 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154600 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154601 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154602 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154603 | GIR_RootConstrainSelectedInstOperands, |
| 154604 | // GIR_Coverage, 5857, |
| 154605 | GIR_EraseRootFromParent_Done, |
| 154606 | // Label 7282: @492090 |
| 154607 | GIM_Try, /*On fail goto*//*Label 7283*/ GIMT_Encode4(492148), // Rule ID 5852 // |
| 154608 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154609 | GIM_CheckHasNoUse, /*MI*/0, |
| 154610 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154611 | // MIs[0] offset |
| 154612 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154613 | // MIs[0] auxiliary |
| 154614 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154615 | // MIs[0] Operand 8 |
| 154616 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154617 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154618 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154619 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN), |
| 154620 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154621 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154622 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154623 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154624 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154625 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154627 | GIR_RootConstrainSelectedInstOperands, |
| 154628 | // GIR_Coverage, 5852, |
| 154629 | GIR_EraseRootFromParent_Done, |
| 154630 | // Label 7283: @492148 |
| 154631 | GIM_Try, /*On fail goto*//*Label 7284*/ GIMT_Encode4(492203), // Rule ID 5860 // |
| 154632 | GIM_CheckHasNoUse, /*MI*/0, |
| 154633 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154634 | // MIs[0] offset |
| 154635 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154636 | // MIs[0] auxiliary |
| 154637 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154638 | // MIs[0] Operand 8 |
| 154639 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154640 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154641 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154642 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN), |
| 154643 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154644 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154645 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154646 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154647 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154648 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154649 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154650 | GIR_RootConstrainSelectedInstOperands, |
| 154651 | // GIR_Coverage, 5860, |
| 154652 | GIR_EraseRootFromParent_Done, |
| 154653 | // Label 7284: @492203 |
| 154654 | GIM_Try, /*On fail goto*//*Label 7285*/ GIMT_Encode4(492265), // Rule ID 5848 // |
| 154655 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154656 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154657 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154658 | // MIs[0] offset |
| 154659 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154660 | // MIs[0] auxiliary |
| 154661 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154662 | // MIs[0] Operand 8 |
| 154663 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154665 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_X2_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154666 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_IDXEN_RTN), |
| 154667 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154668 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154669 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154670 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154672 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154673 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154675 | GIR_RootConstrainSelectedInstOperands, |
| 154676 | // GIR_Coverage, 5848, |
| 154677 | GIR_EraseRootFromParent_Done, |
| 154678 | // Label 7285: @492265 |
| 154679 | GIM_Try, /*On fail goto*//*Label 7286*/ GIMT_Encode4(492324), // Rule ID 5856 // |
| 154680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154681 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/4, 0, |
| 154682 | // MIs[0] offset |
| 154683 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154684 | // MIs[0] auxiliary |
| 154685 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154686 | // MIs[0] Operand 8 |
| 154687 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154688 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154689 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154690 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_IDXEN_RTN), |
| 154691 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154692 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154693 | GIR_RootToRootCopy, /*OpIdx*/3, // vindex |
| 154694 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154696 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154697 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154698 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154699 | GIR_RootConstrainSelectedInstOperands, |
| 154700 | // GIR_Coverage, 5856, |
| 154701 | GIR_EraseRootFromParent_Done, |
| 154702 | // Label 7286: @492324 |
| 154703 | GIM_Try, /*On fail goto*//*Label 7287*/ GIMT_Encode4(492420), // Rule ID 5854 // |
| 154704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154705 | GIM_CheckHasNoUse, /*MI*/0, |
| 154706 | // MIs[0] offset |
| 154707 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154708 | // MIs[0] auxiliary |
| 154709 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154710 | // MIs[0] Operand 8 |
| 154711 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154712 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154713 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154714 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154715 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154716 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154717 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154718 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154719 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154720 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154721 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154722 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154723 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN), |
| 154725 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154726 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154727 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154729 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154730 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154731 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154732 | GIR_RootConstrainSelectedInstOperands, |
| 154733 | // GIR_Coverage, 5854, |
| 154734 | GIR_EraseRootFromParent_Done, |
| 154735 | // Label 7287: @492420 |
| 154736 | GIM_Try, /*On fail goto*//*Label 7288*/ GIMT_Encode4(492513), // Rule ID 5862 // |
| 154737 | GIM_CheckHasNoUse, /*MI*/0, |
| 154738 | // MIs[0] offset |
| 154739 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154740 | // MIs[0] auxiliary |
| 154741 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154742 | // MIs[0] Operand 8 |
| 154743 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154745 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_SIbuffer_atomic_xor_noret>> => (BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154746 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154747 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154748 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154749 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154750 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154751 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154752 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154753 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154754 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154755 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN), |
| 154757 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154759 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154761 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154762 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154764 | GIR_RootConstrainSelectedInstOperands, |
| 154765 | // GIR_Coverage, 5862, |
| 154766 | GIR_EraseRootFromParent_Done, |
| 154767 | // Label 7288: @492513 |
| 154768 | GIM_Try, /*On fail goto*//*Label 7289*/ GIMT_Encode4(492613), // Rule ID 5850 // |
| 154769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154770 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154771 | // MIs[0] offset |
| 154772 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154773 | // MIs[0] auxiliary |
| 154774 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154775 | // MIs[0] Operand 8 |
| 154776 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154777 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154778 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154779 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154780 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154781 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154782 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154783 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154784 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154785 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154786 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154787 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154788 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_BOTHEN_RTN), |
| 154790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154791 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154792 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154793 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154794 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154795 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154796 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154798 | GIR_RootConstrainSelectedInstOperands, |
| 154799 | // GIR_Coverage, 5850, |
| 154800 | GIR_EraseRootFromParent_Done, |
| 154801 | // Label 7289: @492613 |
| 154802 | GIM_Try, /*On fail goto*//*Label 7290*/ GIMT_Encode4(492710), // Rule ID 5858 // |
| 154803 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154804 | // MIs[0] offset |
| 154805 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154806 | // MIs[0] auxiliary |
| 154807 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154808 | // MIs[0] Operand 8 |
| 154809 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 154810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/5, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154811 | // (SIbuffer_atomic_xor:{ *:[i64] } i64:{ *:[i64] }:$vdata_in, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN:{ *:[i64] } anonymous_15875:{ *:[i64] }:$vdata_in, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol_set_glc:{ *:[i32] } ?:{ *:[i32] }:$auxiliary)) |
| 154812 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 154813 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 154814 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 154815 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // vindex |
| 154816 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 154817 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/4, // voffset |
| 154818 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 154819 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 154820 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154821 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 154822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_ATOMIC_XOR_X2_VBUFFER_BOTHEN_RTN), |
| 154823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154824 | GIR_RootToRootCopy, /*OpIdx*/1, // vdata_in |
| 154825 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 154826 | GIR_RootToRootCopy, /*OpIdx*/2, // rsrc |
| 154827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154828 | GIR_RootToRootCopy, /*OpIdx*/6, // offset |
| 154829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCpolSetGLC), // auxiliary |
| 154830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154831 | GIR_RootConstrainSelectedInstOperands, |
| 154832 | // GIR_Coverage, 5858, |
| 154833 | GIR_EraseRootFromParent_Done, |
| 154834 | // Label 7290: @492710 |
| 154835 | GIM_Reject, |
| 154836 | // Label 7274: @492711 |
| 154837 | GIM_Reject, |
| 154838 | // Label 7256: @492712 |
| 154839 | GIM_Reject, |
| 154840 | // Label 125: @492713 |
| 154841 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(23), /*)*//*default:*//*Label 7305*/ GIMT_Encode4(508634), |
| 154842 | /*GILLT_p0s64*//*Label 7291*/ GIMT_Encode4(492816), GIMT_Encode4(0), |
| 154843 | /*GILLT_p2s32*//*Label 7292*/ GIMT_Encode4(493435), |
| 154844 | /*GILLT_p3s32*//*Label 7293*/ GIMT_Encode4(494054), GIMT_Encode4(0), |
| 154845 | /*GILLT_p5s32*//*Label 7294*/ GIMT_Encode4(494673), |
| 154846 | /*GILLT_p6s32*//*Label 7295*/ GIMT_Encode4(495292), GIMT_Encode4(0), GIMT_Encode4(0), |
| 154847 | /*GILLT_s32*//*Label 7296*/ GIMT_Encode4(495911), |
| 154848 | /*GILLT_s64*//*Label 7297*/ GIMT_Encode4(497126), |
| 154849 | /*GILLT_v2s16*//*Label 7298*/ GIMT_Encode4(498341), |
| 154850 | /*GILLT_v2s32*//*Label 7299*/ GIMT_Encode4(500152), |
| 154851 | /*GILLT_v2s64*//*Label 7300*/ GIMT_Encode4(501367), |
| 154852 | /*GILLT_v3s32*//*Label 7301*/ GIMT_Encode4(502582), GIMT_Encode4(0), |
| 154853 | /*GILLT_v4s16*//*Label 7302*/ GIMT_Encode4(503797), |
| 154854 | /*GILLT_v4s32*//*Label 7303*/ GIMT_Encode4(505608), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 154855 | /*GILLT_v8s16*//*Label 7304*/ GIMT_Encode4(506823), |
| 154856 | // Label 7291: @492816 |
| 154857 | GIM_Try, /*On fail goto*//*Label 7306*/ GIMT_Encode4(493434), |
| 154858 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 154859 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 154860 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 154861 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 154862 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 154863 | GIM_Try, /*On fail goto*//*Label 7307*/ GIMT_Encode4(492909), // Rule ID 4655 // |
| 154864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154865 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 154866 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154867 | // MIs[0] offset |
| 154868 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154869 | // MIs[0] auxiliary |
| 154870 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154871 | // MIs[0] Operand 7 |
| 154872 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 154873 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154874 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154875 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 154876 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154877 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154879 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154880 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154881 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154882 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154883 | GIR_RootConstrainSelectedInstOperands, |
| 154884 | // GIR_Coverage, 4655, |
| 154885 | GIR_EraseRootFromParent_Done, |
| 154886 | // Label 7307: @492909 |
| 154887 | GIM_Try, /*On fail goto*//*Label 7308*/ GIMT_Encode4(492978), // Rule ID 4659 // |
| 154888 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 154889 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154890 | // MIs[0] offset |
| 154891 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154892 | // MIs[0] auxiliary |
| 154893 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154894 | // MIs[0] Operand 7 |
| 154895 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 154896 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154897 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154898 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 154899 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154900 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154902 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154903 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154904 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154905 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154906 | GIR_RootConstrainSelectedInstOperands, |
| 154907 | // GIR_Coverage, 4659, |
| 154908 | GIR_EraseRootFromParent_Done, |
| 154909 | // Label 7308: @492978 |
| 154910 | GIM_Try, /*On fail goto*//*Label 7309*/ GIMT_Encode4(493048), // Rule ID 4656 // |
| 154911 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154912 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 154913 | // MIs[0] offset |
| 154914 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154915 | // MIs[0] auxiliary |
| 154916 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154917 | // MIs[0] Operand 7 |
| 154918 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 154919 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154920 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 154922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154923 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 154924 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154925 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154926 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154927 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154928 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154930 | GIR_RootConstrainSelectedInstOperands, |
| 154931 | // GIR_Coverage, 4656, |
| 154932 | GIR_EraseRootFromParent_Done, |
| 154933 | // Label 7309: @493048 |
| 154934 | GIM_Try, /*On fail goto*//*Label 7310*/ GIMT_Encode4(493115), // Rule ID 4660 // |
| 154935 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 154936 | // MIs[0] offset |
| 154937 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154938 | // MIs[0] auxiliary |
| 154939 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154940 | // MIs[0] Operand 7 |
| 154941 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 154942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154943 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154944 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 154945 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154946 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 154947 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154949 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154950 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154951 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154952 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154953 | GIR_RootConstrainSelectedInstOperands, |
| 154954 | // GIR_Coverage, 4660, |
| 154955 | GIR_EraseRootFromParent_Done, |
| 154956 | // Label 7310: @493115 |
| 154957 | GIM_Try, /*On fail goto*//*Label 7311*/ GIMT_Encode4(493177), // Rule ID 4657 // |
| 154958 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 154959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154960 | // MIs[0] offset |
| 154961 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154962 | // MIs[0] auxiliary |
| 154963 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154964 | // MIs[0] Operand 7 |
| 154965 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154967 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 154969 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154970 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 154971 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154972 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154973 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154974 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154975 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154976 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 154977 | GIR_RootConstrainSelectedInstOperands, |
| 154978 | // GIR_Coverage, 4657, |
| 154979 | GIR_EraseRootFromParent_Done, |
| 154980 | // Label 7311: @493177 |
| 154981 | GIM_Try, /*On fail goto*//*Label 7312*/ GIMT_Encode4(493236), // Rule ID 4661 // |
| 154982 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 154983 | // MIs[0] offset |
| 154984 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 154985 | // MIs[0] auxiliary |
| 154986 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 154987 | // MIs[0] Operand 7 |
| 154988 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 154989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 154990 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 154991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 154992 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 154993 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 154994 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 154995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 154996 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 154997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 154998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 154999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155000 | GIR_RootConstrainSelectedInstOperands, |
| 155001 | // GIR_Coverage, 4661, |
| 155002 | GIR_EraseRootFromParent_Done, |
| 155003 | // Label 7312: @493236 |
| 155004 | GIM_Try, /*On fail goto*//*Label 7313*/ GIMT_Encode4(493336), // Rule ID 4658 // |
| 155005 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155006 | // MIs[0] offset |
| 155007 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155008 | // MIs[0] auxiliary |
| 155009 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155010 | // MIs[0] Operand 7 |
| 155011 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155013 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155017 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155018 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155019 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155020 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155021 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155022 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155023 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 155025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155027 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155029 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155033 | GIR_RootConstrainSelectedInstOperands, |
| 155034 | // GIR_Coverage, 4658, |
| 155035 | GIR_EraseRootFromParent_Done, |
| 155036 | // Label 7313: @493336 |
| 155037 | GIM_Try, /*On fail goto*//*Label 7314*/ GIMT_Encode4(493433), // Rule ID 4662 // |
| 155038 | // MIs[0] offset |
| 155039 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155040 | // MIs[0] auxiliary |
| 155041 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155042 | // MIs[0] Operand 7 |
| 155043 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155045 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155049 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155050 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155051 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155052 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155053 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155055 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 155057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155059 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155061 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155063 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155065 | GIR_RootConstrainSelectedInstOperands, |
| 155066 | // GIR_Coverage, 4662, |
| 155067 | GIR_EraseRootFromParent_Done, |
| 155068 | // Label 7314: @493433 |
| 155069 | GIM_Reject, |
| 155070 | // Label 7306: @493434 |
| 155071 | GIM_Reject, |
| 155072 | // Label 7292: @493435 |
| 155073 | GIM_Try, /*On fail goto*//*Label 7315*/ GIMT_Encode4(494053), |
| 155074 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 155075 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 155076 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 155077 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 155078 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 155079 | GIM_Try, /*On fail goto*//*Label 7316*/ GIMT_Encode4(493528), // Rule ID 4591 // |
| 155080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155081 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155082 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155083 | // MIs[0] offset |
| 155084 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155085 | // MIs[0] auxiliary |
| 155086 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155087 | // MIs[0] Operand 7 |
| 155088 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155090 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 155092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155093 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155095 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155096 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155099 | GIR_RootConstrainSelectedInstOperands, |
| 155100 | // GIR_Coverage, 4591, |
| 155101 | GIR_EraseRootFromParent_Done, |
| 155102 | // Label 7316: @493528 |
| 155103 | GIM_Try, /*On fail goto*//*Label 7317*/ GIMT_Encode4(493597), // Rule ID 4595 // |
| 155104 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155105 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155106 | // MIs[0] offset |
| 155107 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155108 | // MIs[0] auxiliary |
| 155109 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155110 | // MIs[0] Operand 7 |
| 155111 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155112 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155113 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155114 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 155115 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155116 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155118 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155119 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155120 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155121 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155122 | GIR_RootConstrainSelectedInstOperands, |
| 155123 | // GIR_Coverage, 4595, |
| 155124 | GIR_EraseRootFromParent_Done, |
| 155125 | // Label 7317: @493597 |
| 155126 | GIM_Try, /*On fail goto*//*Label 7318*/ GIMT_Encode4(493667), // Rule ID 4592 // |
| 155127 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155128 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155129 | // MIs[0] offset |
| 155130 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155131 | // MIs[0] auxiliary |
| 155132 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155133 | // MIs[0] Operand 7 |
| 155134 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155136 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 155138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155139 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155140 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155142 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155143 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155144 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155145 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155146 | GIR_RootConstrainSelectedInstOperands, |
| 155147 | // GIR_Coverage, 4592, |
| 155148 | GIR_EraseRootFromParent_Done, |
| 155149 | // Label 7318: @493667 |
| 155150 | GIM_Try, /*On fail goto*//*Label 7319*/ GIMT_Encode4(493734), // Rule ID 4596 // |
| 155151 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155152 | // MIs[0] offset |
| 155153 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155154 | // MIs[0] auxiliary |
| 155155 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155156 | // MIs[0] Operand 7 |
| 155157 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155159 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 155161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155162 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155163 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155165 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155166 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155167 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155168 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155169 | GIR_RootConstrainSelectedInstOperands, |
| 155170 | // GIR_Coverage, 4596, |
| 155171 | GIR_EraseRootFromParent_Done, |
| 155172 | // Label 7319: @493734 |
| 155173 | GIM_Try, /*On fail goto*//*Label 7320*/ GIMT_Encode4(493796), // Rule ID 4593 // |
| 155174 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155176 | // MIs[0] offset |
| 155177 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155178 | // MIs[0] auxiliary |
| 155179 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155180 | // MIs[0] Operand 7 |
| 155181 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155182 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155183 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155184 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 155185 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155186 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155187 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155188 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155189 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155190 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155191 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155192 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155193 | GIR_RootConstrainSelectedInstOperands, |
| 155194 | // GIR_Coverage, 4593, |
| 155195 | GIR_EraseRootFromParent_Done, |
| 155196 | // Label 7320: @493796 |
| 155197 | GIM_Try, /*On fail goto*//*Label 7321*/ GIMT_Encode4(493855), // Rule ID 4597 // |
| 155198 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155199 | // MIs[0] offset |
| 155200 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155201 | // MIs[0] auxiliary |
| 155202 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155203 | // MIs[0] Operand 7 |
| 155204 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155205 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155206 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155207 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 155208 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155209 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155210 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155212 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155214 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155215 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155216 | GIR_RootConstrainSelectedInstOperands, |
| 155217 | // GIR_Coverage, 4597, |
| 155218 | GIR_EraseRootFromParent_Done, |
| 155219 | // Label 7321: @493855 |
| 155220 | GIM_Try, /*On fail goto*//*Label 7322*/ GIMT_Encode4(493955), // Rule ID 4594 // |
| 155221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155222 | // MIs[0] offset |
| 155223 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155224 | // MIs[0] auxiliary |
| 155225 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155226 | // MIs[0] Operand 7 |
| 155227 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155229 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155230 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155233 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155234 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155235 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155236 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155237 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155239 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 155241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155242 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155243 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155245 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155249 | GIR_RootConstrainSelectedInstOperands, |
| 155250 | // GIR_Coverage, 4594, |
| 155251 | GIR_EraseRootFromParent_Done, |
| 155252 | // Label 7322: @493955 |
| 155253 | GIM_Try, /*On fail goto*//*Label 7323*/ GIMT_Encode4(494052), // Rule ID 4598 // |
| 155254 | // MIs[0] offset |
| 155255 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155256 | // MIs[0] auxiliary |
| 155257 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155258 | // MIs[0] Operand 7 |
| 155259 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155260 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155261 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155262 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155263 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155264 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155265 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155266 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155267 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155268 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155269 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155270 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155271 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 155273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155274 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155275 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155276 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155277 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155278 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155279 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155281 | GIR_RootConstrainSelectedInstOperands, |
| 155282 | // GIR_Coverage, 4598, |
| 155283 | GIR_EraseRootFromParent_Done, |
| 155284 | // Label 7323: @494052 |
| 155285 | GIM_Reject, |
| 155286 | // Label 7315: @494053 |
| 155287 | GIM_Reject, |
| 155288 | // Label 7293: @494054 |
| 155289 | GIM_Try, /*On fail goto*//*Label 7324*/ GIMT_Encode4(494672), |
| 155290 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 155291 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 155292 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 155293 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 155294 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 155295 | GIM_Try, /*On fail goto*//*Label 7325*/ GIMT_Encode4(494147), // Rule ID 4599 // |
| 155296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155297 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155298 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155299 | // MIs[0] offset |
| 155300 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155301 | // MIs[0] auxiliary |
| 155302 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155303 | // MIs[0] Operand 7 |
| 155304 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155306 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 155308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155309 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155311 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155312 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155313 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155315 | GIR_RootConstrainSelectedInstOperands, |
| 155316 | // GIR_Coverage, 4599, |
| 155317 | GIR_EraseRootFromParent_Done, |
| 155318 | // Label 7325: @494147 |
| 155319 | GIM_Try, /*On fail goto*//*Label 7326*/ GIMT_Encode4(494216), // Rule ID 4603 // |
| 155320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155322 | // MIs[0] offset |
| 155323 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155324 | // MIs[0] auxiliary |
| 155325 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155326 | // MIs[0] Operand 7 |
| 155327 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155329 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 155331 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155332 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155334 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155335 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155336 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155338 | GIR_RootConstrainSelectedInstOperands, |
| 155339 | // GIR_Coverage, 4603, |
| 155340 | GIR_EraseRootFromParent_Done, |
| 155341 | // Label 7326: @494216 |
| 155342 | GIM_Try, /*On fail goto*//*Label 7327*/ GIMT_Encode4(494286), // Rule ID 4600 // |
| 155343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155344 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155345 | // MIs[0] offset |
| 155346 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155347 | // MIs[0] auxiliary |
| 155348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155349 | // MIs[0] Operand 7 |
| 155350 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155352 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 155354 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155355 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155356 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155358 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155360 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155362 | GIR_RootConstrainSelectedInstOperands, |
| 155363 | // GIR_Coverage, 4600, |
| 155364 | GIR_EraseRootFromParent_Done, |
| 155365 | // Label 7327: @494286 |
| 155366 | GIM_Try, /*On fail goto*//*Label 7328*/ GIMT_Encode4(494353), // Rule ID 4604 // |
| 155367 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155368 | // MIs[0] offset |
| 155369 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155370 | // MIs[0] auxiliary |
| 155371 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155372 | // MIs[0] Operand 7 |
| 155373 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155374 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155375 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 155377 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155378 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155379 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155381 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155385 | GIR_RootConstrainSelectedInstOperands, |
| 155386 | // GIR_Coverage, 4604, |
| 155387 | GIR_EraseRootFromParent_Done, |
| 155388 | // Label 7328: @494353 |
| 155389 | GIM_Try, /*On fail goto*//*Label 7329*/ GIMT_Encode4(494415), // Rule ID 4601 // |
| 155390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155392 | // MIs[0] offset |
| 155393 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155394 | // MIs[0] auxiliary |
| 155395 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155396 | // MIs[0] Operand 7 |
| 155397 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155399 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 155401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155402 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155403 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155405 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155406 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155407 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155409 | GIR_RootConstrainSelectedInstOperands, |
| 155410 | // GIR_Coverage, 4601, |
| 155411 | GIR_EraseRootFromParent_Done, |
| 155412 | // Label 7329: @494415 |
| 155413 | GIM_Try, /*On fail goto*//*Label 7330*/ GIMT_Encode4(494474), // Rule ID 4605 // |
| 155414 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155415 | // MIs[0] offset |
| 155416 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155417 | // MIs[0] auxiliary |
| 155418 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155419 | // MIs[0] Operand 7 |
| 155420 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155422 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 155424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155425 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155426 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155428 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155429 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155431 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155432 | GIR_RootConstrainSelectedInstOperands, |
| 155433 | // GIR_Coverage, 4605, |
| 155434 | GIR_EraseRootFromParent_Done, |
| 155435 | // Label 7330: @494474 |
| 155436 | GIM_Try, /*On fail goto*//*Label 7331*/ GIMT_Encode4(494574), // Rule ID 4602 // |
| 155437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155438 | // MIs[0] offset |
| 155439 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155440 | // MIs[0] auxiliary |
| 155441 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155442 | // MIs[0] Operand 7 |
| 155443 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155445 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155446 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155447 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155448 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155449 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155450 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155451 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155452 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155453 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155454 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155455 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 155457 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155458 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155459 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155461 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155462 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155465 | GIR_RootConstrainSelectedInstOperands, |
| 155466 | // GIR_Coverage, 4602, |
| 155467 | GIR_EraseRootFromParent_Done, |
| 155468 | // Label 7331: @494574 |
| 155469 | GIM_Try, /*On fail goto*//*Label 7332*/ GIMT_Encode4(494671), // Rule ID 4606 // |
| 155470 | // MIs[0] offset |
| 155471 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155472 | // MIs[0] auxiliary |
| 155473 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155474 | // MIs[0] Operand 7 |
| 155475 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155477 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155481 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155482 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155483 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155484 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155485 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155486 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155487 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 155489 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155491 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155493 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155494 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155495 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155496 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155497 | GIR_RootConstrainSelectedInstOperands, |
| 155498 | // GIR_Coverage, 4606, |
| 155499 | GIR_EraseRootFromParent_Done, |
| 155500 | // Label 7332: @494671 |
| 155501 | GIM_Reject, |
| 155502 | // Label 7324: @494672 |
| 155503 | GIM_Reject, |
| 155504 | // Label 7294: @494673 |
| 155505 | GIM_Try, /*On fail goto*//*Label 7333*/ GIMT_Encode4(495291), |
| 155506 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 155507 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 155508 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 155509 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 155510 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 155511 | GIM_Try, /*On fail goto*//*Label 7334*/ GIMT_Encode4(494766), // Rule ID 4607 // |
| 155512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155513 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155514 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155515 | // MIs[0] offset |
| 155516 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155517 | // MIs[0] auxiliary |
| 155518 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155519 | // MIs[0] Operand 7 |
| 155520 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155522 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 155524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155525 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155526 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155527 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155528 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155529 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155531 | GIR_RootConstrainSelectedInstOperands, |
| 155532 | // GIR_Coverage, 4607, |
| 155533 | GIR_EraseRootFromParent_Done, |
| 155534 | // Label 7334: @494766 |
| 155535 | GIM_Try, /*On fail goto*//*Label 7335*/ GIMT_Encode4(494835), // Rule ID 4611 // |
| 155536 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155537 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155538 | // MIs[0] offset |
| 155539 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155540 | // MIs[0] auxiliary |
| 155541 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155542 | // MIs[0] Operand 7 |
| 155543 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155545 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155546 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 155547 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155548 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155550 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155551 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155552 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155554 | GIR_RootConstrainSelectedInstOperands, |
| 155555 | // GIR_Coverage, 4611, |
| 155556 | GIR_EraseRootFromParent_Done, |
| 155557 | // Label 7335: @494835 |
| 155558 | GIM_Try, /*On fail goto*//*Label 7336*/ GIMT_Encode4(494905), // Rule ID 4608 // |
| 155559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155560 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155561 | // MIs[0] offset |
| 155562 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155563 | // MIs[0] auxiliary |
| 155564 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155565 | // MIs[0] Operand 7 |
| 155566 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155567 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155568 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155569 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 155570 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155571 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155572 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155574 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155575 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155576 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155577 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155578 | GIR_RootConstrainSelectedInstOperands, |
| 155579 | // GIR_Coverage, 4608, |
| 155580 | GIR_EraseRootFromParent_Done, |
| 155581 | // Label 7336: @494905 |
| 155582 | GIM_Try, /*On fail goto*//*Label 7337*/ GIMT_Encode4(494972), // Rule ID 4612 // |
| 155583 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155584 | // MIs[0] offset |
| 155585 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155586 | // MIs[0] auxiliary |
| 155587 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155588 | // MIs[0] Operand 7 |
| 155589 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155590 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155591 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 155593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155594 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155595 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155597 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155598 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155600 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155601 | GIR_RootConstrainSelectedInstOperands, |
| 155602 | // GIR_Coverage, 4612, |
| 155603 | GIR_EraseRootFromParent_Done, |
| 155604 | // Label 7337: @494972 |
| 155605 | GIM_Try, /*On fail goto*//*Label 7338*/ GIMT_Encode4(495034), // Rule ID 4609 // |
| 155606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155608 | // MIs[0] offset |
| 155609 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155610 | // MIs[0] auxiliary |
| 155611 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155612 | // MIs[0] Operand 7 |
| 155613 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155615 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 155617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155618 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155619 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155620 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155621 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155622 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155623 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155624 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155625 | GIR_RootConstrainSelectedInstOperands, |
| 155626 | // GIR_Coverage, 4609, |
| 155627 | GIR_EraseRootFromParent_Done, |
| 155628 | // Label 7338: @495034 |
| 155629 | GIM_Try, /*On fail goto*//*Label 7339*/ GIMT_Encode4(495093), // Rule ID 4613 // |
| 155630 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155631 | // MIs[0] offset |
| 155632 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155633 | // MIs[0] auxiliary |
| 155634 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155635 | // MIs[0] Operand 7 |
| 155636 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155637 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155638 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155639 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 155640 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155641 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155642 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155644 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155645 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155646 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155647 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155648 | GIR_RootConstrainSelectedInstOperands, |
| 155649 | // GIR_Coverage, 4613, |
| 155650 | GIR_EraseRootFromParent_Done, |
| 155651 | // Label 7339: @495093 |
| 155652 | GIM_Try, /*On fail goto*//*Label 7340*/ GIMT_Encode4(495193), // Rule ID 4610 // |
| 155653 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155654 | // MIs[0] offset |
| 155655 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155656 | // MIs[0] auxiliary |
| 155657 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155658 | // MIs[0] Operand 7 |
| 155659 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155660 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155661 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155662 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155663 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155664 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155665 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155666 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155667 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155668 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155669 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155670 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155671 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155672 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 155673 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155674 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155675 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155676 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155677 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155678 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155679 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155680 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155681 | GIR_RootConstrainSelectedInstOperands, |
| 155682 | // GIR_Coverage, 4610, |
| 155683 | GIR_EraseRootFromParent_Done, |
| 155684 | // Label 7340: @495193 |
| 155685 | GIM_Try, /*On fail goto*//*Label 7341*/ GIMT_Encode4(495290), // Rule ID 4614 // |
| 155686 | // MIs[0] offset |
| 155687 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155688 | // MIs[0] auxiliary |
| 155689 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155690 | // MIs[0] Operand 7 |
| 155691 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155693 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155694 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155695 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155696 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155697 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155698 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155699 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155700 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155701 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155702 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155703 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 155705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155706 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155707 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155709 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155710 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155713 | GIR_RootConstrainSelectedInstOperands, |
| 155714 | // GIR_Coverage, 4614, |
| 155715 | GIR_EraseRootFromParent_Done, |
| 155716 | // Label 7341: @495290 |
| 155717 | GIM_Reject, |
| 155718 | // Label 7333: @495291 |
| 155719 | GIM_Reject, |
| 155720 | // Label 7295: @495292 |
| 155721 | GIM_Try, /*On fail goto*//*Label 7342*/ GIMT_Encode4(495910), |
| 155722 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 155723 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 155724 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 155725 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 155726 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 155727 | GIM_Try, /*On fail goto*//*Label 7343*/ GIMT_Encode4(495385), // Rule ID 4615 // |
| 155728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155729 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155730 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155731 | // MIs[0] offset |
| 155732 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155733 | // MIs[0] auxiliary |
| 155734 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155735 | // MIs[0] Operand 7 |
| 155736 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155738 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155739 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 155740 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155741 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155743 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155744 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155745 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155746 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155747 | GIR_RootConstrainSelectedInstOperands, |
| 155748 | // GIR_Coverage, 4615, |
| 155749 | GIR_EraseRootFromParent_Done, |
| 155750 | // Label 7343: @495385 |
| 155751 | GIM_Try, /*On fail goto*//*Label 7344*/ GIMT_Encode4(495454), // Rule ID 4619 // |
| 155752 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155753 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155754 | // MIs[0] offset |
| 155755 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155756 | // MIs[0] auxiliary |
| 155757 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155758 | // MIs[0] Operand 7 |
| 155759 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155760 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155761 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155762 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 155763 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155764 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155766 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155767 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155768 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155769 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155770 | GIR_RootConstrainSelectedInstOperands, |
| 155771 | // GIR_Coverage, 4619, |
| 155772 | GIR_EraseRootFromParent_Done, |
| 155773 | // Label 7344: @495454 |
| 155774 | GIM_Try, /*On fail goto*//*Label 7345*/ GIMT_Encode4(495524), // Rule ID 4616 // |
| 155775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155776 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155777 | // MIs[0] offset |
| 155778 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155779 | // MIs[0] auxiliary |
| 155780 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155781 | // MIs[0] Operand 7 |
| 155782 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155783 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155784 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 155786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155787 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155788 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155790 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155791 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155794 | GIR_RootConstrainSelectedInstOperands, |
| 155795 | // GIR_Coverage, 4616, |
| 155796 | GIR_EraseRootFromParent_Done, |
| 155797 | // Label 7345: @495524 |
| 155798 | GIM_Try, /*On fail goto*//*Label 7346*/ GIMT_Encode4(495591), // Rule ID 4620 // |
| 155799 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155800 | // MIs[0] offset |
| 155801 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155802 | // MIs[0] auxiliary |
| 155803 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155804 | // MIs[0] Operand 7 |
| 155805 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155807 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 155809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155810 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 155811 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155813 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155814 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155815 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155817 | GIR_RootConstrainSelectedInstOperands, |
| 155818 | // GIR_Coverage, 4620, |
| 155819 | GIR_EraseRootFromParent_Done, |
| 155820 | // Label 7346: @495591 |
| 155821 | GIM_Try, /*On fail goto*//*Label 7347*/ GIMT_Encode4(495653), // Rule ID 4617 // |
| 155822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155824 | // MIs[0] offset |
| 155825 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155826 | // MIs[0] auxiliary |
| 155827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155828 | // MIs[0] Operand 7 |
| 155829 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155831 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 155833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155834 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155835 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155837 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155839 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155841 | GIR_RootConstrainSelectedInstOperands, |
| 155842 | // GIR_Coverage, 4617, |
| 155843 | GIR_EraseRootFromParent_Done, |
| 155844 | // Label 7347: @495653 |
| 155845 | GIM_Try, /*On fail goto*//*Label 7348*/ GIMT_Encode4(495712), // Rule ID 4621 // |
| 155846 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155847 | // MIs[0] offset |
| 155848 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155849 | // MIs[0] auxiliary |
| 155850 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155851 | // MIs[0] Operand 7 |
| 155852 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155854 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 155856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155857 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 155858 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155860 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155861 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155864 | GIR_RootConstrainSelectedInstOperands, |
| 155865 | // GIR_Coverage, 4621, |
| 155866 | GIR_EraseRootFromParent_Done, |
| 155867 | // Label 7348: @495712 |
| 155868 | GIM_Try, /*On fail goto*//*Label 7349*/ GIMT_Encode4(495812), // Rule ID 4618 // |
| 155869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155870 | // MIs[0] offset |
| 155871 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155872 | // MIs[0] auxiliary |
| 155873 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155874 | // MIs[0] Operand 7 |
| 155875 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155876 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155877 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155878 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155879 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155880 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155881 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155882 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155883 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155884 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155885 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155886 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155887 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 155889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155890 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155891 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155892 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155893 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155894 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155895 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155897 | GIR_RootConstrainSelectedInstOperands, |
| 155898 | // GIR_Coverage, 4618, |
| 155899 | GIR_EraseRootFromParent_Done, |
| 155900 | // Label 7349: @495812 |
| 155901 | GIM_Try, /*On fail goto*//*Label 7350*/ GIMT_Encode4(495909), // Rule ID 4622 // |
| 155902 | // MIs[0] offset |
| 155903 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155904 | // MIs[0] auxiliary |
| 155905 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155906 | // MIs[0] Operand 7 |
| 155907 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 155908 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155909 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155910 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 155911 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 155912 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 155913 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 155914 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 155915 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 155916 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 155917 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 155918 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155919 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 155920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 155921 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155922 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 155923 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155925 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155926 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155927 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155929 | GIR_RootConstrainSelectedInstOperands, |
| 155930 | // GIR_Coverage, 4622, |
| 155931 | GIR_EraseRootFromParent_Done, |
| 155932 | // Label 7350: @495909 |
| 155933 | GIM_Reject, |
| 155934 | // Label 7342: @495910 |
| 155935 | GIM_Reject, |
| 155936 | // Label 7296: @495911 |
| 155937 | GIM_Try, /*On fail goto*//*Label 7351*/ GIMT_Encode4(497125), |
| 155938 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 155939 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 155940 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 155941 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 155942 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 155943 | GIM_Try, /*On fail goto*//*Label 7352*/ GIMT_Encode4(496004), // Rule ID 4551 // |
| 155944 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155945 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155946 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155947 | // MIs[0] offset |
| 155948 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155949 | // MIs[0] auxiliary |
| 155950 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155951 | // MIs[0] Operand 7 |
| 155952 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155954 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 155956 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155957 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155959 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155963 | GIR_RootConstrainSelectedInstOperands, |
| 155964 | // GIR_Coverage, 4551, |
| 155965 | GIR_EraseRootFromParent_Done, |
| 155966 | // Label 7352: @496004 |
| 155967 | GIM_Try, /*On fail goto*//*Label 7353*/ GIMT_Encode4(496073), // Rule ID 4555 // |
| 155968 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155969 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155970 | // MIs[0] offset |
| 155971 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155972 | // MIs[0] auxiliary |
| 155973 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155974 | // MIs[0] Operand 7 |
| 155975 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 155976 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 155977 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 155978 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 155979 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 155980 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 155981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 155982 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 155983 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 155984 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 155985 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 155986 | GIR_RootConstrainSelectedInstOperands, |
| 155987 | // GIR_Coverage, 4555, |
| 155988 | GIR_EraseRootFromParent_Done, |
| 155989 | // Label 7353: @496073 |
| 155990 | GIM_Try, /*On fail goto*//*Label 7354*/ GIMT_Encode4(496145), // Rule ID 4559 // |
| 155991 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 155992 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 155993 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 155994 | // MIs[0] offset |
| 155995 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 155996 | // MIs[0] auxiliary |
| 155997 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 155998 | // MIs[0] Operand 7 |
| 155999 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156000 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156001 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156002 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 156003 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156004 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156006 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156007 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156008 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156009 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156010 | GIR_RootConstrainSelectedInstOperands, |
| 156011 | // GIR_Coverage, 4559, |
| 156012 | GIR_EraseRootFromParent_Done, |
| 156013 | // Label 7354: @496145 |
| 156014 | GIM_Try, /*On fail goto*//*Label 7355*/ GIMT_Encode4(496214), // Rule ID 4563 // |
| 156015 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156016 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156017 | // MIs[0] offset |
| 156018 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156019 | // MIs[0] auxiliary |
| 156020 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156021 | // MIs[0] Operand 7 |
| 156022 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156023 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156024 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 156026 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156027 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156029 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156033 | GIR_RootConstrainSelectedInstOperands, |
| 156034 | // GIR_Coverage, 4563, |
| 156035 | GIR_EraseRootFromParent_Done, |
| 156036 | // Label 7355: @496214 |
| 156037 | GIM_Try, /*On fail goto*//*Label 7356*/ GIMT_Encode4(496284), // Rule ID 4552 // |
| 156038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156039 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156040 | // MIs[0] offset |
| 156041 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156042 | // MIs[0] auxiliary |
| 156043 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156044 | // MIs[0] Operand 7 |
| 156045 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156046 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156047 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 156049 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156050 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156051 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156052 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156053 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156054 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156055 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156056 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156057 | GIR_RootConstrainSelectedInstOperands, |
| 156058 | // GIR_Coverage, 4552, |
| 156059 | GIR_EraseRootFromParent_Done, |
| 156060 | // Label 7356: @496284 |
| 156061 | GIM_Try, /*On fail goto*//*Label 7357*/ GIMT_Encode4(496351), // Rule ID 4556 // |
| 156062 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156063 | // MIs[0] offset |
| 156064 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156065 | // MIs[0] auxiliary |
| 156066 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156067 | // MIs[0] Operand 7 |
| 156068 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156070 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 156072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156073 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156074 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156076 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156077 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156078 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156080 | GIR_RootConstrainSelectedInstOperands, |
| 156081 | // GIR_Coverage, 4556, |
| 156082 | GIR_EraseRootFromParent_Done, |
| 156083 | // Label 7357: @496351 |
| 156084 | GIM_Try, /*On fail goto*//*Label 7358*/ GIMT_Encode4(496421), // Rule ID 4560 // |
| 156085 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156087 | // MIs[0] offset |
| 156088 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156089 | // MIs[0] auxiliary |
| 156090 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156091 | // MIs[0] Operand 7 |
| 156092 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156093 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156094 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 156096 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156097 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156098 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156100 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156101 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156102 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156103 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156104 | GIR_RootConstrainSelectedInstOperands, |
| 156105 | // GIR_Coverage, 4560, |
| 156106 | GIR_EraseRootFromParent_Done, |
| 156107 | // Label 7358: @496421 |
| 156108 | GIM_Try, /*On fail goto*//*Label 7359*/ GIMT_Encode4(496488), // Rule ID 4564 // |
| 156109 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156110 | // MIs[0] offset |
| 156111 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156112 | // MIs[0] auxiliary |
| 156113 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156114 | // MIs[0] Operand 7 |
| 156115 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156116 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156117 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 156119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156120 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156121 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156123 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156125 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156127 | GIR_RootConstrainSelectedInstOperands, |
| 156128 | // GIR_Coverage, 4564, |
| 156129 | GIR_EraseRootFromParent_Done, |
| 156130 | // Label 7359: @496488 |
| 156131 | GIM_Try, /*On fail goto*//*Label 7360*/ GIMT_Encode4(496550), // Rule ID 4553 // |
| 156132 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156133 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156134 | // MIs[0] offset |
| 156135 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156136 | // MIs[0] auxiliary |
| 156137 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156138 | // MIs[0] Operand 7 |
| 156139 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156140 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156141 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 156143 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156144 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156145 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156147 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156149 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156151 | GIR_RootConstrainSelectedInstOperands, |
| 156152 | // GIR_Coverage, 4553, |
| 156153 | GIR_EraseRootFromParent_Done, |
| 156154 | // Label 7360: @496550 |
| 156155 | GIM_Try, /*On fail goto*//*Label 7361*/ GIMT_Encode4(496609), // Rule ID 4557 // |
| 156156 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156157 | // MIs[0] offset |
| 156158 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156159 | // MIs[0] auxiliary |
| 156160 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156161 | // MIs[0] Operand 7 |
| 156162 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156164 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 156166 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156167 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156168 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156170 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156171 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156172 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156173 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156174 | GIR_RootConstrainSelectedInstOperands, |
| 156175 | // GIR_Coverage, 4557, |
| 156176 | GIR_EraseRootFromParent_Done, |
| 156177 | // Label 7361: @496609 |
| 156178 | GIM_Try, /*On fail goto*//*Label 7362*/ GIMT_Encode4(496671), // Rule ID 4561 // |
| 156179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156180 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156181 | // MIs[0] offset |
| 156182 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156183 | // MIs[0] auxiliary |
| 156184 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156185 | // MIs[0] Operand 7 |
| 156186 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156188 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 156190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156191 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156192 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156194 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156196 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156198 | GIR_RootConstrainSelectedInstOperands, |
| 156199 | // GIR_Coverage, 4561, |
| 156200 | GIR_EraseRootFromParent_Done, |
| 156201 | // Label 7362: @496671 |
| 156202 | GIM_Try, /*On fail goto*//*Label 7363*/ GIMT_Encode4(496730), // Rule ID 4565 // |
| 156203 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156204 | // MIs[0] offset |
| 156205 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156206 | // MIs[0] auxiliary |
| 156207 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156208 | // MIs[0] Operand 7 |
| 156209 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156211 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 156213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156214 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156215 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156217 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156219 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156221 | GIR_RootConstrainSelectedInstOperands, |
| 156222 | // GIR_Coverage, 4565, |
| 156223 | GIR_EraseRootFromParent_Done, |
| 156224 | // Label 7363: @496730 |
| 156225 | GIM_Try, /*On fail goto*//*Label 7364*/ GIMT_Encode4(496830), // Rule ID 4554 // |
| 156226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156227 | // MIs[0] offset |
| 156228 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156229 | // MIs[0] auxiliary |
| 156230 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156231 | // MIs[0] Operand 7 |
| 156232 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156234 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156235 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156236 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156237 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156238 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156239 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156240 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156241 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156242 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156243 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156244 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 156246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156247 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156248 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156250 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156252 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156254 | GIR_RootConstrainSelectedInstOperands, |
| 156255 | // GIR_Coverage, 4554, |
| 156256 | GIR_EraseRootFromParent_Done, |
| 156257 | // Label 7364: @496830 |
| 156258 | GIM_Try, /*On fail goto*//*Label 7365*/ GIMT_Encode4(496927), // Rule ID 4558 // |
| 156259 | // MIs[0] offset |
| 156260 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156261 | // MIs[0] auxiliary |
| 156262 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156263 | // MIs[0] Operand 7 |
| 156264 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156266 | // (SIbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156267 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156268 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156269 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156270 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156271 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156272 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156273 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156274 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156275 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156276 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156277 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 156278 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156279 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156280 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156281 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156282 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156283 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156284 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156285 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156286 | GIR_RootConstrainSelectedInstOperands, |
| 156287 | // GIR_Coverage, 4558, |
| 156288 | GIR_EraseRootFromParent_Done, |
| 156289 | // Label 7365: @496927 |
| 156290 | GIM_Try, /*On fail goto*//*Label 7366*/ GIMT_Encode4(497027), // Rule ID 4562 // |
| 156291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156292 | // MIs[0] offset |
| 156293 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156294 | // MIs[0] auxiliary |
| 156295 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156296 | // MIs[0] Operand 7 |
| 156297 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156298 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156299 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156300 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156301 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156302 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156303 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156304 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156305 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156306 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156307 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156308 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156309 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156310 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 156311 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156312 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156313 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156315 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156316 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156317 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156318 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156319 | GIR_RootConstrainSelectedInstOperands, |
| 156320 | // GIR_Coverage, 4562, |
| 156321 | GIR_EraseRootFromParent_Done, |
| 156322 | // Label 7366: @497027 |
| 156323 | GIM_Try, /*On fail goto*//*Label 7367*/ GIMT_Encode4(497124), // Rule ID 4566 // |
| 156324 | // MIs[0] offset |
| 156325 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156326 | // MIs[0] auxiliary |
| 156327 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156328 | // MIs[0] Operand 7 |
| 156329 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156330 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156331 | // (SIbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156336 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156338 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156339 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156340 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156341 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 156343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156344 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156345 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156347 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156348 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156349 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156351 | GIR_RootConstrainSelectedInstOperands, |
| 156352 | // GIR_Coverage, 4566, |
| 156353 | GIR_EraseRootFromParent_Done, |
| 156354 | // Label 7367: @497124 |
| 156355 | GIM_Reject, |
| 156356 | // Label 7351: @497125 |
| 156357 | GIM_Reject, |
| 156358 | // Label 7297: @497126 |
| 156359 | GIM_Try, /*On fail goto*//*Label 7368*/ GIMT_Encode4(498340), |
| 156360 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 156361 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 156362 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 156363 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 156364 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 156365 | GIM_Try, /*On fail goto*//*Label 7369*/ GIMT_Encode4(497219), // Rule ID 4623 // |
| 156366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156367 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156368 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156369 | // MIs[0] offset |
| 156370 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156371 | // MIs[0] auxiliary |
| 156372 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156373 | // MIs[0] Operand 7 |
| 156374 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156375 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156376 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 156378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156379 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156381 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156385 | GIR_RootConstrainSelectedInstOperands, |
| 156386 | // GIR_Coverage, 4623, |
| 156387 | GIR_EraseRootFromParent_Done, |
| 156388 | // Label 7369: @497219 |
| 156389 | GIM_Try, /*On fail goto*//*Label 7370*/ GIMT_Encode4(497288), // Rule ID 4627 // |
| 156390 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156392 | // MIs[0] offset |
| 156393 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156394 | // MIs[0] auxiliary |
| 156395 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156396 | // MIs[0] Operand 7 |
| 156397 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156399 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 156401 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156402 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156403 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156404 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156405 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156406 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156407 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156408 | GIR_RootConstrainSelectedInstOperands, |
| 156409 | // GIR_Coverage, 4627, |
| 156410 | GIR_EraseRootFromParent_Done, |
| 156411 | // Label 7370: @497288 |
| 156412 | GIM_Try, /*On fail goto*//*Label 7371*/ GIMT_Encode4(497360), // Rule ID 4631 // |
| 156413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156414 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156415 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156416 | // MIs[0] offset |
| 156417 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156418 | // MIs[0] auxiliary |
| 156419 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156420 | // MIs[0] Operand 7 |
| 156421 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156422 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156423 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[f64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156424 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 156425 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156426 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156428 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156429 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156431 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156432 | GIR_RootConstrainSelectedInstOperands, |
| 156433 | // GIR_Coverage, 4631, |
| 156434 | GIR_EraseRootFromParent_Done, |
| 156435 | // Label 7371: @497360 |
| 156436 | GIM_Try, /*On fail goto*//*Label 7372*/ GIMT_Encode4(497429), // Rule ID 4635 // |
| 156437 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156438 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156439 | // MIs[0] offset |
| 156440 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156441 | // MIs[0] auxiliary |
| 156442 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156443 | // MIs[0] Operand 7 |
| 156444 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156445 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156446 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[f64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156447 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 156448 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156449 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156451 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156452 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156453 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156454 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156455 | GIR_RootConstrainSelectedInstOperands, |
| 156456 | // GIR_Coverage, 4635, |
| 156457 | GIR_EraseRootFromParent_Done, |
| 156458 | // Label 7372: @497429 |
| 156459 | GIM_Try, /*On fail goto*//*Label 7373*/ GIMT_Encode4(497499), // Rule ID 4624 // |
| 156460 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156461 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156462 | // MIs[0] offset |
| 156463 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156464 | // MIs[0] auxiliary |
| 156465 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156466 | // MIs[0] Operand 7 |
| 156467 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156468 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156469 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156470 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 156471 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156472 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156473 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156474 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156475 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156476 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156477 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156478 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156479 | GIR_RootConstrainSelectedInstOperands, |
| 156480 | // GIR_Coverage, 4624, |
| 156481 | GIR_EraseRootFromParent_Done, |
| 156482 | // Label 7373: @497499 |
| 156483 | GIM_Try, /*On fail goto*//*Label 7374*/ GIMT_Encode4(497566), // Rule ID 4628 // |
| 156484 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156485 | // MIs[0] offset |
| 156486 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156487 | // MIs[0] auxiliary |
| 156488 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156489 | // MIs[0] Operand 7 |
| 156490 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156491 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156492 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156493 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 156494 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156495 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156496 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156498 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156499 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156500 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156502 | GIR_RootConstrainSelectedInstOperands, |
| 156503 | // GIR_Coverage, 4628, |
| 156504 | GIR_EraseRootFromParent_Done, |
| 156505 | // Label 7374: @497566 |
| 156506 | GIM_Try, /*On fail goto*//*Label 7375*/ GIMT_Encode4(497636), // Rule ID 4632 // |
| 156507 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156508 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156509 | // MIs[0] offset |
| 156510 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156511 | // MIs[0] auxiliary |
| 156512 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156513 | // MIs[0] Operand 7 |
| 156514 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156516 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[f64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 156518 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156519 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156520 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156521 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156522 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156523 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156524 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156525 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156526 | GIR_RootConstrainSelectedInstOperands, |
| 156527 | // GIR_Coverage, 4632, |
| 156528 | GIR_EraseRootFromParent_Done, |
| 156529 | // Label 7375: @497636 |
| 156530 | GIM_Try, /*On fail goto*//*Label 7376*/ GIMT_Encode4(497703), // Rule ID 4636 // |
| 156531 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156532 | // MIs[0] offset |
| 156533 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156534 | // MIs[0] auxiliary |
| 156535 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156536 | // MIs[0] Operand 7 |
| 156537 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156538 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156539 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[f64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156540 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 156541 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156542 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156543 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156545 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156546 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156547 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156549 | GIR_RootConstrainSelectedInstOperands, |
| 156550 | // GIR_Coverage, 4636, |
| 156551 | GIR_EraseRootFromParent_Done, |
| 156552 | // Label 7376: @497703 |
| 156553 | GIM_Try, /*On fail goto*//*Label 7377*/ GIMT_Encode4(497765), // Rule ID 4625 // |
| 156554 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156555 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156556 | // MIs[0] offset |
| 156557 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156558 | // MIs[0] auxiliary |
| 156559 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156560 | // MIs[0] Operand 7 |
| 156561 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156563 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 156565 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156566 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156567 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156569 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156570 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156573 | GIR_RootConstrainSelectedInstOperands, |
| 156574 | // GIR_Coverage, 4625, |
| 156575 | GIR_EraseRootFromParent_Done, |
| 156576 | // Label 7377: @497765 |
| 156577 | GIM_Try, /*On fail goto*//*Label 7378*/ GIMT_Encode4(497824), // Rule ID 4629 // |
| 156578 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156579 | // MIs[0] offset |
| 156580 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156581 | // MIs[0] auxiliary |
| 156582 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156583 | // MIs[0] Operand 7 |
| 156584 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156586 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 156588 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156589 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156590 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156592 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156596 | GIR_RootConstrainSelectedInstOperands, |
| 156597 | // GIR_Coverage, 4629, |
| 156598 | GIR_EraseRootFromParent_Done, |
| 156599 | // Label 7378: @497824 |
| 156600 | GIM_Try, /*On fail goto*//*Label 7379*/ GIMT_Encode4(497886), // Rule ID 4633 // |
| 156601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156602 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156603 | // MIs[0] offset |
| 156604 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156605 | // MIs[0] auxiliary |
| 156606 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156607 | // MIs[0] Operand 7 |
| 156608 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156609 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156610 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[f64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 156612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156613 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156614 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156616 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156618 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156620 | GIR_RootConstrainSelectedInstOperands, |
| 156621 | // GIR_Coverage, 4633, |
| 156622 | GIR_EraseRootFromParent_Done, |
| 156623 | // Label 7379: @497886 |
| 156624 | GIM_Try, /*On fail goto*//*Label 7380*/ GIMT_Encode4(497945), // Rule ID 4637 // |
| 156625 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156626 | // MIs[0] offset |
| 156627 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156628 | // MIs[0] auxiliary |
| 156629 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156630 | // MIs[0] Operand 7 |
| 156631 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156633 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[f64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 156635 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156636 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 156637 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156639 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156640 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156641 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156642 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156643 | GIR_RootConstrainSelectedInstOperands, |
| 156644 | // GIR_Coverage, 4637, |
| 156645 | GIR_EraseRootFromParent_Done, |
| 156646 | // Label 7380: @497945 |
| 156647 | GIM_Try, /*On fail goto*//*Label 7381*/ GIMT_Encode4(498045), // Rule ID 4626 // |
| 156648 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156649 | // MIs[0] offset |
| 156650 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156651 | // MIs[0] auxiliary |
| 156652 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156653 | // MIs[0] Operand 7 |
| 156654 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156656 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156657 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156658 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156659 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156660 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156661 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156662 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156663 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156664 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156665 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 156668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156669 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156670 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156672 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156673 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156674 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156675 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156676 | GIR_RootConstrainSelectedInstOperands, |
| 156677 | // GIR_Coverage, 4626, |
| 156678 | GIR_EraseRootFromParent_Done, |
| 156679 | // Label 7381: @498045 |
| 156680 | GIM_Try, /*On fail goto*//*Label 7382*/ GIMT_Encode4(498142), // Rule ID 4630 // |
| 156681 | // MIs[0] offset |
| 156682 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156683 | // MIs[0] auxiliary |
| 156684 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156685 | // MIs[0] Operand 7 |
| 156686 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156688 | // (SIbuffer_load:{ *:[i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156689 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156690 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156691 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156692 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156693 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156694 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156695 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156696 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156697 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156698 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 156700 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156701 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156702 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156703 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156704 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156705 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156706 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156707 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156708 | GIR_RootConstrainSelectedInstOperands, |
| 156709 | // GIR_Coverage, 4630, |
| 156710 | GIR_EraseRootFromParent_Done, |
| 156711 | // Label 7382: @498142 |
| 156712 | GIM_Try, /*On fail goto*//*Label 7383*/ GIMT_Encode4(498242), // Rule ID 4634 // |
| 156713 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156714 | // MIs[0] offset |
| 156715 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156716 | // MIs[0] auxiliary |
| 156717 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156718 | // MIs[0] Operand 7 |
| 156719 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156721 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[f64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156722 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156723 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156725 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156726 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156727 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156728 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156729 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156730 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156731 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 156733 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156735 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156737 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156738 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156741 | GIR_RootConstrainSelectedInstOperands, |
| 156742 | // GIR_Coverage, 4634, |
| 156743 | GIR_EraseRootFromParent_Done, |
| 156744 | // Label 7383: @498242 |
| 156745 | GIM_Try, /*On fail goto*//*Label 7384*/ GIMT_Encode4(498339), // Rule ID 4638 // |
| 156746 | // MIs[0] offset |
| 156747 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156748 | // MIs[0] auxiliary |
| 156749 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156750 | // MIs[0] Operand 7 |
| 156751 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 156752 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156753 | // (SIbuffer_load:{ *:[f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[f64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156754 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 156755 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 156756 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 156757 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 156758 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 156759 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 156760 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 156761 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 156762 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156763 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 156764 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 156765 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156766 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 156767 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156768 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156769 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156770 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156771 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156772 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156773 | GIR_RootConstrainSelectedInstOperands, |
| 156774 | // GIR_Coverage, 4638, |
| 156775 | GIR_EraseRootFromParent_Done, |
| 156776 | // Label 7384: @498339 |
| 156777 | GIM_Reject, |
| 156778 | // Label 7368: @498340 |
| 156779 | GIM_Reject, |
| 156780 | // Label 7298: @498341 |
| 156781 | GIM_Try, /*On fail goto*//*Label 7385*/ GIMT_Encode4(500151), |
| 156782 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 156783 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 156784 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 156785 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 156786 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 156787 | GIM_Try, /*On fail goto*//*Label 7386*/ GIMT_Encode4(498434), // Rule ID 4567 // |
| 156788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156791 | // MIs[0] offset |
| 156792 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156793 | // MIs[0] auxiliary |
| 156794 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156795 | // MIs[0] Operand 7 |
| 156796 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156797 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156798 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 156800 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156801 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156803 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156804 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156805 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156806 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156807 | GIR_RootConstrainSelectedInstOperands, |
| 156808 | // GIR_Coverage, 4567, |
| 156809 | GIR_EraseRootFromParent_Done, |
| 156810 | // Label 7386: @498434 |
| 156811 | GIM_Try, /*On fail goto*//*Label 7387*/ GIMT_Encode4(498503), // Rule ID 4571 // |
| 156812 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156813 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156814 | // MIs[0] offset |
| 156815 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156816 | // MIs[0] auxiliary |
| 156817 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156818 | // MIs[0] Operand 7 |
| 156819 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156821 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 156823 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156824 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156826 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156827 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156829 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156830 | GIR_RootConstrainSelectedInstOperands, |
| 156831 | // GIR_Coverage, 4571, |
| 156832 | GIR_EraseRootFromParent_Done, |
| 156833 | // Label 7387: @498503 |
| 156834 | GIM_Try, /*On fail goto*//*Label 7388*/ GIMT_Encode4(498575), // Rule ID 4575 // |
| 156835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156836 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156837 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156838 | // MIs[0] offset |
| 156839 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156840 | // MIs[0] auxiliary |
| 156841 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156842 | // MIs[0] Operand 7 |
| 156843 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156845 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 156847 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156848 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156850 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156851 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156852 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156854 | GIR_RootConstrainSelectedInstOperands, |
| 156855 | // GIR_Coverage, 4575, |
| 156856 | GIR_EraseRootFromParent_Done, |
| 156857 | // Label 7388: @498575 |
| 156858 | GIM_Try, /*On fail goto*//*Label 7389*/ GIMT_Encode4(498644), // Rule ID 4579 // |
| 156859 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156861 | // MIs[0] offset |
| 156862 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156863 | // MIs[0] auxiliary |
| 156864 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156865 | // MIs[0] Operand 7 |
| 156866 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156868 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 156870 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156871 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156873 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156874 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156875 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156877 | GIR_RootConstrainSelectedInstOperands, |
| 156878 | // GIR_Coverage, 4579, |
| 156879 | GIR_EraseRootFromParent_Done, |
| 156880 | // Label 7389: @498644 |
| 156881 | GIM_Try, /*On fail goto*//*Label 7390*/ GIMT_Encode4(498716), // Rule ID 4583 // |
| 156882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156883 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156884 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156885 | // MIs[0] offset |
| 156886 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156887 | // MIs[0] auxiliary |
| 156888 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156889 | // MIs[0] Operand 7 |
| 156890 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156892 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFSET:{ *:[v2bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFSET), |
| 156894 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156895 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156897 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156898 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156899 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156900 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156901 | GIR_RootConstrainSelectedInstOperands, |
| 156902 | // GIR_Coverage, 4583, |
| 156903 | GIR_EraseRootFromParent_Done, |
| 156904 | // Label 7390: @498716 |
| 156905 | GIM_Try, /*On fail goto*//*Label 7391*/ GIMT_Encode4(498785), // Rule ID 4587 // |
| 156906 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156907 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 156908 | // MIs[0] offset |
| 156909 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156910 | // MIs[0] auxiliary |
| 156911 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156912 | // MIs[0] Operand 7 |
| 156913 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156915 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFSET:{ *:[v2bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156916 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFSET), |
| 156917 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156918 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156919 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156920 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156921 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156922 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156923 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156924 | GIR_RootConstrainSelectedInstOperands, |
| 156925 | // GIR_Coverage, 4587, |
| 156926 | GIR_EraseRootFromParent_Done, |
| 156927 | // Label 7391: @498785 |
| 156928 | GIM_Try, /*On fail goto*//*Label 7392*/ GIMT_Encode4(498855), // Rule ID 4568 // |
| 156929 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156930 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156931 | // MIs[0] offset |
| 156932 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156933 | // MIs[0] auxiliary |
| 156934 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156935 | // MIs[0] Operand 7 |
| 156936 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156937 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156938 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 156940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156941 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156942 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156943 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156944 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156945 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156946 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156947 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156948 | GIR_RootConstrainSelectedInstOperands, |
| 156949 | // GIR_Coverage, 4568, |
| 156950 | GIR_EraseRootFromParent_Done, |
| 156951 | // Label 7392: @498855 |
| 156952 | GIM_Try, /*On fail goto*//*Label 7393*/ GIMT_Encode4(498922), // Rule ID 4572 // |
| 156953 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156954 | // MIs[0] offset |
| 156955 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156956 | // MIs[0] auxiliary |
| 156957 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156958 | // MIs[0] Operand 7 |
| 156959 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156961 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 156963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156964 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156965 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156967 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156969 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156971 | GIR_RootConstrainSelectedInstOperands, |
| 156972 | // GIR_Coverage, 4572, |
| 156973 | GIR_EraseRootFromParent_Done, |
| 156974 | // Label 7393: @498922 |
| 156975 | GIM_Try, /*On fail goto*//*Label 7394*/ GIMT_Encode4(498992), // Rule ID 4576 // |
| 156976 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 156977 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 156978 | // MIs[0] offset |
| 156979 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 156980 | // MIs[0] auxiliary |
| 156981 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 156982 | // MIs[0] Operand 7 |
| 156983 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 156984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 156985 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 156986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 156987 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 156988 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 156989 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 156990 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 156991 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 156992 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 156993 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 156994 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 156995 | GIR_RootConstrainSelectedInstOperands, |
| 156996 | // GIR_Coverage, 4576, |
| 156997 | GIR_EraseRootFromParent_Done, |
| 156998 | // Label 7394: @498992 |
| 156999 | GIM_Try, /*On fail goto*//*Label 7395*/ GIMT_Encode4(499059), // Rule ID 4580 // |
| 157000 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157001 | // MIs[0] offset |
| 157002 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157003 | // MIs[0] auxiliary |
| 157004 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157005 | // MIs[0] Operand 7 |
| 157006 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157008 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 157010 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157011 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157012 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157014 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157016 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157018 | GIR_RootConstrainSelectedInstOperands, |
| 157019 | // GIR_Coverage, 4580, |
| 157020 | GIR_EraseRootFromParent_Done, |
| 157021 | // Label 7395: @499059 |
| 157022 | GIM_Try, /*On fail goto*//*Label 7396*/ GIMT_Encode4(499129), // Rule ID 4584 // |
| 157023 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157024 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157025 | // MIs[0] offset |
| 157026 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157027 | // MIs[0] auxiliary |
| 157028 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157029 | // MIs[0] Operand 7 |
| 157030 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157031 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157032 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_OFFEN:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_OFFEN), |
| 157034 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157035 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157036 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157037 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157038 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157039 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157040 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157041 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157042 | GIR_RootConstrainSelectedInstOperands, |
| 157043 | // GIR_Coverage, 4584, |
| 157044 | GIR_EraseRootFromParent_Done, |
| 157045 | // Label 7396: @499129 |
| 157046 | GIM_Try, /*On fail goto*//*Label 7397*/ GIMT_Encode4(499196), // Rule ID 4588 // |
| 157047 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157048 | // MIs[0] offset |
| 157049 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157050 | // MIs[0] auxiliary |
| 157051 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157052 | // MIs[0] Operand 7 |
| 157053 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157054 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157055 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_VBUFFER_OFFEN:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_OFFEN), |
| 157057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157058 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157059 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157061 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157063 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157065 | GIR_RootConstrainSelectedInstOperands, |
| 157066 | // GIR_Coverage, 4588, |
| 157067 | GIR_EraseRootFromParent_Done, |
| 157068 | // Label 7397: @499196 |
| 157069 | GIM_Try, /*On fail goto*//*Label 7398*/ GIMT_Encode4(499258), // Rule ID 4569 // |
| 157070 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157071 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157072 | // MIs[0] offset |
| 157073 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157074 | // MIs[0] auxiliary |
| 157075 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157076 | // MIs[0] Operand 7 |
| 157077 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157079 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 157081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157082 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157083 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157084 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157085 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157086 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157087 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157088 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157089 | GIR_RootConstrainSelectedInstOperands, |
| 157090 | // GIR_Coverage, 4569, |
| 157091 | GIR_EraseRootFromParent_Done, |
| 157092 | // Label 7398: @499258 |
| 157093 | GIM_Try, /*On fail goto*//*Label 7399*/ GIMT_Encode4(499317), // Rule ID 4573 // |
| 157094 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157095 | // MIs[0] offset |
| 157096 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157097 | // MIs[0] auxiliary |
| 157098 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157099 | // MIs[0] Operand 7 |
| 157100 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157102 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 157104 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157105 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157106 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157108 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157110 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157111 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157112 | GIR_RootConstrainSelectedInstOperands, |
| 157113 | // GIR_Coverage, 4573, |
| 157114 | GIR_EraseRootFromParent_Done, |
| 157115 | // Label 7399: @499317 |
| 157116 | GIM_Try, /*On fail goto*//*Label 7400*/ GIMT_Encode4(499379), // Rule ID 4577 // |
| 157117 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157118 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157119 | // MIs[0] offset |
| 157120 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157121 | // MIs[0] auxiliary |
| 157122 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157123 | // MIs[0] Operand 7 |
| 157124 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157126 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157127 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 157128 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157129 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157130 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157131 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157132 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157133 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157134 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157135 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157136 | GIR_RootConstrainSelectedInstOperands, |
| 157137 | // GIR_Coverage, 4577, |
| 157138 | GIR_EraseRootFromParent_Done, |
| 157139 | // Label 7400: @499379 |
| 157140 | GIM_Try, /*On fail goto*//*Label 7401*/ GIMT_Encode4(499438), // Rule ID 4581 // |
| 157141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157142 | // MIs[0] offset |
| 157143 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157144 | // MIs[0] auxiliary |
| 157145 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157146 | // MIs[0] Operand 7 |
| 157147 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157149 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 157151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157152 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157153 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157155 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157157 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157159 | GIR_RootConstrainSelectedInstOperands, |
| 157160 | // GIR_Coverage, 4581, |
| 157161 | GIR_EraseRootFromParent_Done, |
| 157162 | // Label 7401: @499438 |
| 157163 | GIM_Try, /*On fail goto*//*Label 7402*/ GIMT_Encode4(499500), // Rule ID 4585 // |
| 157164 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157165 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157166 | // MIs[0] offset |
| 157167 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157168 | // MIs[0] auxiliary |
| 157169 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157170 | // MIs[0] Operand 7 |
| 157171 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157173 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_IDXEN:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_IDXEN), |
| 157175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157176 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157177 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157179 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157183 | GIR_RootConstrainSelectedInstOperands, |
| 157184 | // GIR_Coverage, 4585, |
| 157185 | GIR_EraseRootFromParent_Done, |
| 157186 | // Label 7402: @499500 |
| 157187 | GIM_Try, /*On fail goto*//*Label 7403*/ GIMT_Encode4(499559), // Rule ID 4589 // |
| 157188 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157189 | // MIs[0] offset |
| 157190 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157191 | // MIs[0] auxiliary |
| 157192 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157193 | // MIs[0] Operand 7 |
| 157194 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157195 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157196 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_IDXEN:{ *:[v2bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_IDXEN), |
| 157198 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157199 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157200 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157202 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157203 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157204 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157206 | GIR_RootConstrainSelectedInstOperands, |
| 157207 | // GIR_Coverage, 4589, |
| 157208 | GIR_EraseRootFromParent_Done, |
| 157209 | // Label 7403: @499559 |
| 157210 | GIM_Try, /*On fail goto*//*Label 7404*/ GIMT_Encode4(499659), // Rule ID 4570 // |
| 157211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157212 | // MIs[0] offset |
| 157213 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157214 | // MIs[0] auxiliary |
| 157215 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157216 | // MIs[0] Operand 7 |
| 157217 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157219 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157220 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157221 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157222 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157223 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157224 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157225 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157226 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157227 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157228 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157229 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 157231 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157232 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157233 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157235 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157236 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157237 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157238 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157239 | GIR_RootConstrainSelectedInstOperands, |
| 157240 | // GIR_Coverage, 4570, |
| 157241 | GIR_EraseRootFromParent_Done, |
| 157242 | // Label 7404: @499659 |
| 157243 | GIM_Try, /*On fail goto*//*Label 7405*/ GIMT_Encode4(499756), // Rule ID 4574 // |
| 157244 | // MIs[0] offset |
| 157245 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157246 | // MIs[0] auxiliary |
| 157247 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157248 | // MIs[0] Operand 7 |
| 157249 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157250 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157251 | // (SIbuffer_load:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157252 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157253 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157254 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157255 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157256 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157257 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157258 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157259 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157260 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157261 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157262 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 157263 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157264 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157265 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157266 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157267 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157268 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157269 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157270 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157271 | GIR_RootConstrainSelectedInstOperands, |
| 157272 | // GIR_Coverage, 4574, |
| 157273 | GIR_EraseRootFromParent_Done, |
| 157274 | // Label 7405: @499756 |
| 157275 | GIM_Try, /*On fail goto*//*Label 7406*/ GIMT_Encode4(499856), // Rule ID 4578 // |
| 157276 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157277 | // MIs[0] offset |
| 157278 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157279 | // MIs[0] auxiliary |
| 157280 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157281 | // MIs[0] Operand 7 |
| 157282 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157283 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157284 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157285 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157286 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157287 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157288 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157289 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157290 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157291 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157292 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157293 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157294 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157295 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 157296 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157297 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157298 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157300 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157301 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157302 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157303 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157304 | GIR_RootConstrainSelectedInstOperands, |
| 157305 | // GIR_Coverage, 4578, |
| 157306 | GIR_EraseRootFromParent_Done, |
| 157307 | // Label 7406: @499856 |
| 157308 | GIM_Try, /*On fail goto*//*Label 7407*/ GIMT_Encode4(499953), // Rule ID 4582 // |
| 157309 | // MIs[0] offset |
| 157310 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157311 | // MIs[0] auxiliary |
| 157312 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157313 | // MIs[0] Operand 7 |
| 157314 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157316 | // (SIbuffer_load:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157317 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157318 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157319 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157320 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157321 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157322 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157323 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157324 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157325 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157326 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157327 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 157328 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157329 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157330 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157331 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157332 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157333 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157334 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157335 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157336 | GIR_RootConstrainSelectedInstOperands, |
| 157337 | // GIR_Coverage, 4582, |
| 157338 | GIR_EraseRootFromParent_Done, |
| 157339 | // Label 7407: @499953 |
| 157340 | GIM_Try, /*On fail goto*//*Label 7408*/ GIMT_Encode4(500053), // Rule ID 4586 // |
| 157341 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157342 | // MIs[0] offset |
| 157343 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157344 | // MIs[0] auxiliary |
| 157345 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157346 | // MIs[0] Operand 7 |
| 157347 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157348 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157349 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_BOTHEN:{ *:[v2bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157350 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157351 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157352 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157353 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157354 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157355 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157356 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157357 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157358 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157359 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157360 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_BOTHEN), |
| 157361 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157362 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157363 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157364 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157365 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157366 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157367 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157368 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157369 | GIR_RootConstrainSelectedInstOperands, |
| 157370 | // GIR_Coverage, 4586, |
| 157371 | GIR_EraseRootFromParent_Done, |
| 157372 | // Label 7408: @500053 |
| 157373 | GIM_Try, /*On fail goto*//*Label 7409*/ GIMT_Encode4(500150), // Rule ID 4590 // |
| 157374 | // MIs[0] offset |
| 157375 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157376 | // MIs[0] auxiliary |
| 157377 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157378 | // MIs[0] Operand 7 |
| 157379 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157380 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157381 | // (SIbuffer_load:{ *:[v2bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_VBUFFER_BOTHEN:{ *:[v2bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157382 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157383 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157384 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157385 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157386 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157387 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157388 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157389 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157390 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157391 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_VBUFFER_BOTHEN), |
| 157393 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157394 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157395 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157397 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157398 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157401 | GIR_RootConstrainSelectedInstOperands, |
| 157402 | // GIR_Coverage, 4590, |
| 157403 | GIR_EraseRootFromParent_Done, |
| 157404 | // Label 7409: @500150 |
| 157405 | GIM_Reject, |
| 157406 | // Label 7385: @500151 |
| 157407 | GIM_Reject, |
| 157408 | // Label 7299: @500152 |
| 157409 | GIM_Try, /*On fail goto*//*Label 7410*/ GIMT_Encode4(501366), |
| 157410 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 157411 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 157412 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 157413 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 157414 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 157415 | GIM_Try, /*On fail goto*//*Label 7411*/ GIMT_Encode4(500245), // Rule ID 4639 // |
| 157416 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157417 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157418 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157419 | // MIs[0] offset |
| 157420 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157421 | // MIs[0] auxiliary |
| 157422 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157423 | // MIs[0] Operand 7 |
| 157424 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157426 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 157428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157429 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157431 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157433 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157435 | GIR_RootConstrainSelectedInstOperands, |
| 157436 | // GIR_Coverage, 4639, |
| 157437 | GIR_EraseRootFromParent_Done, |
| 157438 | // Label 7411: @500245 |
| 157439 | GIM_Try, /*On fail goto*//*Label 7412*/ GIMT_Encode4(500314), // Rule ID 4643 // |
| 157440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157441 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157442 | // MIs[0] offset |
| 157443 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157444 | // MIs[0] auxiliary |
| 157445 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157446 | // MIs[0] Operand 7 |
| 157447 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157449 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 157451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157452 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157453 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157454 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157455 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157456 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157457 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157458 | GIR_RootConstrainSelectedInstOperands, |
| 157459 | // GIR_Coverage, 4643, |
| 157460 | GIR_EraseRootFromParent_Done, |
| 157461 | // Label 7412: @500314 |
| 157462 | GIM_Try, /*On fail goto*//*Label 7413*/ GIMT_Encode4(500386), // Rule ID 4647 // |
| 157463 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157464 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157466 | // MIs[0] offset |
| 157467 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157468 | // MIs[0] auxiliary |
| 157469 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157470 | // MIs[0] Operand 7 |
| 157471 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157472 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157473 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157474 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 157475 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157476 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157478 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157480 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157482 | GIR_RootConstrainSelectedInstOperands, |
| 157483 | // GIR_Coverage, 4647, |
| 157484 | GIR_EraseRootFromParent_Done, |
| 157485 | // Label 7413: @500386 |
| 157486 | GIM_Try, /*On fail goto*//*Label 7414*/ GIMT_Encode4(500455), // Rule ID 4651 // |
| 157487 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157488 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157489 | // MIs[0] offset |
| 157490 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157491 | // MIs[0] auxiliary |
| 157492 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157493 | // MIs[0] Operand 7 |
| 157494 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157495 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157496 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 157498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157499 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157501 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157502 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157503 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157505 | GIR_RootConstrainSelectedInstOperands, |
| 157506 | // GIR_Coverage, 4651, |
| 157507 | GIR_EraseRootFromParent_Done, |
| 157508 | // Label 7414: @500455 |
| 157509 | GIM_Try, /*On fail goto*//*Label 7415*/ GIMT_Encode4(500525), // Rule ID 4640 // |
| 157510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157511 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157512 | // MIs[0] offset |
| 157513 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157514 | // MIs[0] auxiliary |
| 157515 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157516 | // MIs[0] Operand 7 |
| 157517 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157519 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 157521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157522 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157523 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157525 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157526 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157527 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157529 | GIR_RootConstrainSelectedInstOperands, |
| 157530 | // GIR_Coverage, 4640, |
| 157531 | GIR_EraseRootFromParent_Done, |
| 157532 | // Label 7415: @500525 |
| 157533 | GIM_Try, /*On fail goto*//*Label 7416*/ GIMT_Encode4(500592), // Rule ID 4644 // |
| 157534 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157535 | // MIs[0] offset |
| 157536 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157537 | // MIs[0] auxiliary |
| 157538 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157539 | // MIs[0] Operand 7 |
| 157540 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157542 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 157544 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157545 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157546 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157548 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157549 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157550 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157551 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157552 | GIR_RootConstrainSelectedInstOperands, |
| 157553 | // GIR_Coverage, 4644, |
| 157554 | GIR_EraseRootFromParent_Done, |
| 157555 | // Label 7416: @500592 |
| 157556 | GIM_Try, /*On fail goto*//*Label 7417*/ GIMT_Encode4(500662), // Rule ID 4648 // |
| 157557 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157558 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157559 | // MIs[0] offset |
| 157560 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157561 | // MIs[0] auxiliary |
| 157562 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157563 | // MIs[0] Operand 7 |
| 157564 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157565 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157566 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157567 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 157568 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157569 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157570 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157572 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157573 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157574 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157575 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157576 | GIR_RootConstrainSelectedInstOperands, |
| 157577 | // GIR_Coverage, 4648, |
| 157578 | GIR_EraseRootFromParent_Done, |
| 157579 | // Label 7417: @500662 |
| 157580 | GIM_Try, /*On fail goto*//*Label 7418*/ GIMT_Encode4(500729), // Rule ID 4652 // |
| 157581 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157582 | // MIs[0] offset |
| 157583 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157584 | // MIs[0] auxiliary |
| 157585 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157586 | // MIs[0] Operand 7 |
| 157587 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157588 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157589 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157590 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 157591 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157592 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157593 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157595 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157596 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157597 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157598 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157599 | GIR_RootConstrainSelectedInstOperands, |
| 157600 | // GIR_Coverage, 4652, |
| 157601 | GIR_EraseRootFromParent_Done, |
| 157602 | // Label 7418: @500729 |
| 157603 | GIM_Try, /*On fail goto*//*Label 7419*/ GIMT_Encode4(500791), // Rule ID 4641 // |
| 157604 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157605 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157606 | // MIs[0] offset |
| 157607 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157608 | // MIs[0] auxiliary |
| 157609 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157610 | // MIs[0] Operand 7 |
| 157611 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157612 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157613 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157614 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 157615 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157616 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157617 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157618 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157619 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157620 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157621 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157622 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157623 | GIR_RootConstrainSelectedInstOperands, |
| 157624 | // GIR_Coverage, 4641, |
| 157625 | GIR_EraseRootFromParent_Done, |
| 157626 | // Label 7419: @500791 |
| 157627 | GIM_Try, /*On fail goto*//*Label 7420*/ GIMT_Encode4(500850), // Rule ID 4645 // |
| 157628 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157629 | // MIs[0] offset |
| 157630 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157631 | // MIs[0] auxiliary |
| 157632 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157633 | // MIs[0] Operand 7 |
| 157634 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157636 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157637 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 157638 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157639 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157640 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157642 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157643 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157644 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157645 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157646 | GIR_RootConstrainSelectedInstOperands, |
| 157647 | // GIR_Coverage, 4645, |
| 157648 | GIR_EraseRootFromParent_Done, |
| 157649 | // Label 7420: @500850 |
| 157650 | GIM_Try, /*On fail goto*//*Label 7421*/ GIMT_Encode4(500912), // Rule ID 4649 // |
| 157651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157652 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157653 | // MIs[0] offset |
| 157654 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157655 | // MIs[0] auxiliary |
| 157656 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157657 | // MIs[0] Operand 7 |
| 157658 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157660 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 157662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157663 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157664 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157665 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157666 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157668 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157670 | GIR_RootConstrainSelectedInstOperands, |
| 157671 | // GIR_Coverage, 4649, |
| 157672 | GIR_EraseRootFromParent_Done, |
| 157673 | // Label 7421: @500912 |
| 157674 | GIM_Try, /*On fail goto*//*Label 7422*/ GIMT_Encode4(500971), // Rule ID 4653 // |
| 157675 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157676 | // MIs[0] offset |
| 157677 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157678 | // MIs[0] auxiliary |
| 157679 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157680 | // MIs[0] Operand 7 |
| 157681 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157682 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157683 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 157685 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157686 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 157687 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157689 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157690 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157691 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157692 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157693 | GIR_RootConstrainSelectedInstOperands, |
| 157694 | // GIR_Coverage, 4653, |
| 157695 | GIR_EraseRootFromParent_Done, |
| 157696 | // Label 7422: @500971 |
| 157697 | GIM_Try, /*On fail goto*//*Label 7423*/ GIMT_Encode4(501071), // Rule ID 4642 // |
| 157698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157699 | // MIs[0] offset |
| 157700 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157701 | // MIs[0] auxiliary |
| 157702 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157703 | // MIs[0] Operand 7 |
| 157704 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157706 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157710 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157711 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157712 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157713 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157714 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157715 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 157718 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157719 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157720 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157722 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157723 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157726 | GIR_RootConstrainSelectedInstOperands, |
| 157727 | // GIR_Coverage, 4642, |
| 157728 | GIR_EraseRootFromParent_Done, |
| 157729 | // Label 7423: @501071 |
| 157730 | GIM_Try, /*On fail goto*//*Label 7424*/ GIMT_Encode4(501168), // Rule ID 4646 // |
| 157731 | // MIs[0] offset |
| 157732 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157733 | // MIs[0] auxiliary |
| 157734 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157735 | // MIs[0] Operand 7 |
| 157736 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157737 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157738 | // (SIbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157739 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157740 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157741 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157742 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157743 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157744 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157745 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157746 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157747 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157748 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157749 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 157750 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157751 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157752 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157754 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157755 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157756 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157758 | GIR_RootConstrainSelectedInstOperands, |
| 157759 | // GIR_Coverage, 4646, |
| 157760 | GIR_EraseRootFromParent_Done, |
| 157761 | // Label 7424: @501168 |
| 157762 | GIM_Try, /*On fail goto*//*Label 7425*/ GIMT_Encode4(501268), // Rule ID 4650 // |
| 157763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157764 | // MIs[0] offset |
| 157765 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157766 | // MIs[0] auxiliary |
| 157767 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157768 | // MIs[0] Operand 7 |
| 157769 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157770 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157771 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157772 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157773 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157774 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157775 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157776 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157777 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157778 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157779 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157780 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157781 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 157783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157784 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157785 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157786 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157787 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157788 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157789 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157790 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157791 | GIR_RootConstrainSelectedInstOperands, |
| 157792 | // GIR_Coverage, 4650, |
| 157793 | GIR_EraseRootFromParent_Done, |
| 157794 | // Label 7425: @501268 |
| 157795 | GIM_Try, /*On fail goto*//*Label 7426*/ GIMT_Encode4(501365), // Rule ID 4654 // |
| 157796 | // MIs[0] offset |
| 157797 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157798 | // MIs[0] auxiliary |
| 157799 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157800 | // MIs[0] Operand 7 |
| 157801 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 157802 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157803 | // (SIbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157804 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 157805 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 157806 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 157807 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 157808 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 157809 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 157810 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 157811 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 157812 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157813 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 157814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 157815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157816 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 157817 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157819 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157821 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157823 | GIR_RootConstrainSelectedInstOperands, |
| 157824 | // GIR_Coverage, 4654, |
| 157825 | GIR_EraseRootFromParent_Done, |
| 157826 | // Label 7426: @501365 |
| 157827 | GIM_Reject, |
| 157828 | // Label 7410: @501366 |
| 157829 | GIM_Reject, |
| 157830 | // Label 7300: @501367 |
| 157831 | GIM_Try, /*On fail goto*//*Label 7427*/ GIMT_Encode4(502581), |
| 157832 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 157833 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 157834 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 157835 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 157836 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 157837 | GIM_Try, /*On fail goto*//*Label 7428*/ GIMT_Encode4(501460), // Rule ID 4719 // |
| 157838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157839 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157841 | // MIs[0] offset |
| 157842 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157843 | // MIs[0] auxiliary |
| 157844 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157845 | // MIs[0] Operand 7 |
| 157846 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157848 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 157850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157851 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157853 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157857 | GIR_RootConstrainSelectedInstOperands, |
| 157858 | // GIR_Coverage, 4719, |
| 157859 | GIR_EraseRootFromParent_Done, |
| 157860 | // Label 7428: @501460 |
| 157861 | GIM_Try, /*On fail goto*//*Label 7429*/ GIMT_Encode4(501529), // Rule ID 4723 // |
| 157862 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157863 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157864 | // MIs[0] offset |
| 157865 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157866 | // MIs[0] auxiliary |
| 157867 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157868 | // MIs[0] Operand 7 |
| 157869 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157871 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2i64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 157873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157874 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157876 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157877 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157878 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157880 | GIR_RootConstrainSelectedInstOperands, |
| 157881 | // GIR_Coverage, 4723, |
| 157882 | GIR_EraseRootFromParent_Done, |
| 157883 | // Label 7429: @501529 |
| 157884 | GIM_Try, /*On fail goto*//*Label 7430*/ GIMT_Encode4(501601), // Rule ID 4727 // |
| 157885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157886 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157887 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157888 | // MIs[0] offset |
| 157889 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157890 | // MIs[0] auxiliary |
| 157891 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157892 | // MIs[0] Operand 7 |
| 157893 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157894 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157895 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v2f64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 157897 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157898 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157900 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157902 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157903 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157904 | GIR_RootConstrainSelectedInstOperands, |
| 157905 | // GIR_Coverage, 4727, |
| 157906 | GIR_EraseRootFromParent_Done, |
| 157907 | // Label 7430: @501601 |
| 157908 | GIM_Try, /*On fail goto*//*Label 7431*/ GIMT_Encode4(501670), // Rule ID 4731 // |
| 157909 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157910 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 157911 | // MIs[0] offset |
| 157912 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157913 | // MIs[0] auxiliary |
| 157914 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157915 | // MIs[0] Operand 7 |
| 157916 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157918 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v2f64] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 157920 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157921 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157923 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157925 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157927 | GIR_RootConstrainSelectedInstOperands, |
| 157928 | // GIR_Coverage, 4731, |
| 157929 | GIR_EraseRootFromParent_Done, |
| 157930 | // Label 7431: @501670 |
| 157931 | GIM_Try, /*On fail goto*//*Label 7432*/ GIMT_Encode4(501740), // Rule ID 4720 // |
| 157932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157933 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157934 | // MIs[0] offset |
| 157935 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157936 | // MIs[0] auxiliary |
| 157937 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157938 | // MIs[0] Operand 7 |
| 157939 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157941 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v2i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 157943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157944 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157945 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157947 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157949 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157951 | GIR_RootConstrainSelectedInstOperands, |
| 157952 | // GIR_Coverage, 4720, |
| 157953 | GIR_EraseRootFromParent_Done, |
| 157954 | // Label 7432: @501740 |
| 157955 | GIM_Try, /*On fail goto*//*Label 7433*/ GIMT_Encode4(501807), // Rule ID 4724 // |
| 157956 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157957 | // MIs[0] offset |
| 157958 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157959 | // MIs[0] auxiliary |
| 157960 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157961 | // MIs[0] Operand 7 |
| 157962 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157964 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v2i64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 157966 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157967 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157968 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157970 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157972 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157974 | GIR_RootConstrainSelectedInstOperands, |
| 157975 | // GIR_Coverage, 4724, |
| 157976 | GIR_EraseRootFromParent_Done, |
| 157977 | // Label 7433: @501807 |
| 157978 | GIM_Try, /*On fail goto*//*Label 7434*/ GIMT_Encode4(501877), // Rule ID 4728 // |
| 157979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 157980 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 157981 | // MIs[0] offset |
| 157982 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 157983 | // MIs[0] auxiliary |
| 157984 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 157985 | // MIs[0] Operand 7 |
| 157986 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 157987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 157988 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v2f64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 157989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 157990 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 157991 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 157992 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 157993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 157994 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 157995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 157996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 157997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 157998 | GIR_RootConstrainSelectedInstOperands, |
| 157999 | // GIR_Coverage, 4728, |
| 158000 | GIR_EraseRootFromParent_Done, |
| 158001 | // Label 7434: @501877 |
| 158002 | GIM_Try, /*On fail goto*//*Label 7435*/ GIMT_Encode4(501944), // Rule ID 4732 // |
| 158003 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158004 | // MIs[0] offset |
| 158005 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158006 | // MIs[0] auxiliary |
| 158007 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158008 | // MIs[0] Operand 7 |
| 158009 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158011 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v2f64] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 158013 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158014 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158015 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158017 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158019 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158020 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158021 | GIR_RootConstrainSelectedInstOperands, |
| 158022 | // GIR_Coverage, 4732, |
| 158023 | GIR_EraseRootFromParent_Done, |
| 158024 | // Label 7435: @501944 |
| 158025 | GIM_Try, /*On fail goto*//*Label 7436*/ GIMT_Encode4(502006), // Rule ID 4721 // |
| 158026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158027 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158028 | // MIs[0] offset |
| 158029 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158030 | // MIs[0] auxiliary |
| 158031 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158032 | // MIs[0] Operand 7 |
| 158033 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158034 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158035 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v2i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 158037 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158038 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158039 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158041 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158043 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158044 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158045 | GIR_RootConstrainSelectedInstOperands, |
| 158046 | // GIR_Coverage, 4721, |
| 158047 | GIR_EraseRootFromParent_Done, |
| 158048 | // Label 7436: @502006 |
| 158049 | GIM_Try, /*On fail goto*//*Label 7437*/ GIMT_Encode4(502065), // Rule ID 4725 // |
| 158050 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158051 | // MIs[0] offset |
| 158052 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158053 | // MIs[0] auxiliary |
| 158054 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158055 | // MIs[0] Operand 7 |
| 158056 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158058 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v2i64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 158060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158061 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158062 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158064 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158067 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158068 | GIR_RootConstrainSelectedInstOperands, |
| 158069 | // GIR_Coverage, 4725, |
| 158070 | GIR_EraseRootFromParent_Done, |
| 158071 | // Label 7437: @502065 |
| 158072 | GIM_Try, /*On fail goto*//*Label 7438*/ GIMT_Encode4(502127), // Rule ID 4729 // |
| 158073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158074 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158075 | // MIs[0] offset |
| 158076 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158077 | // MIs[0] auxiliary |
| 158078 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158079 | // MIs[0] Operand 7 |
| 158080 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158082 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v2f64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 158084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158085 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158086 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158088 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158089 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158090 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158091 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158092 | GIR_RootConstrainSelectedInstOperands, |
| 158093 | // GIR_Coverage, 4729, |
| 158094 | GIR_EraseRootFromParent_Done, |
| 158095 | // Label 7438: @502127 |
| 158096 | GIM_Try, /*On fail goto*//*Label 7439*/ GIMT_Encode4(502186), // Rule ID 4733 // |
| 158097 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158098 | // MIs[0] offset |
| 158099 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158100 | // MIs[0] auxiliary |
| 158101 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158102 | // MIs[0] Operand 7 |
| 158103 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158104 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158105 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v2f64] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 158107 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158108 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158109 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158111 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158112 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158113 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158114 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158115 | GIR_RootConstrainSelectedInstOperands, |
| 158116 | // GIR_Coverage, 4733, |
| 158117 | GIR_EraseRootFromParent_Done, |
| 158118 | // Label 7439: @502186 |
| 158119 | GIM_Try, /*On fail goto*//*Label 7440*/ GIMT_Encode4(502286), // Rule ID 4722 // |
| 158120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158121 | // MIs[0] offset |
| 158122 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158123 | // MIs[0] auxiliary |
| 158124 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158125 | // MIs[0] Operand 7 |
| 158126 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158128 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v2i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158129 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158130 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158131 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158132 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158133 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158135 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158136 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158137 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158138 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 158140 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158141 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158142 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158144 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158145 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158146 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158148 | GIR_RootConstrainSelectedInstOperands, |
| 158149 | // GIR_Coverage, 4722, |
| 158150 | GIR_EraseRootFromParent_Done, |
| 158151 | // Label 7440: @502286 |
| 158152 | GIM_Try, /*On fail goto*//*Label 7441*/ GIMT_Encode4(502383), // Rule ID 4726 // |
| 158153 | // MIs[0] offset |
| 158154 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158155 | // MIs[0] auxiliary |
| 158156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158157 | // MIs[0] Operand 7 |
| 158158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158160 | // (SIbuffer_load:{ *:[v2i64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v2i64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158164 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158165 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158167 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158168 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158169 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 158172 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158174 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158176 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158177 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158178 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158179 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158180 | GIR_RootConstrainSelectedInstOperands, |
| 158181 | // GIR_Coverage, 4726, |
| 158182 | GIR_EraseRootFromParent_Done, |
| 158183 | // Label 7441: @502383 |
| 158184 | GIM_Try, /*On fail goto*//*Label 7442*/ GIMT_Encode4(502483), // Rule ID 4730 // |
| 158185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158186 | // MIs[0] offset |
| 158187 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158188 | // MIs[0] auxiliary |
| 158189 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158190 | // MIs[0] Operand 7 |
| 158191 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158193 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v2f64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158194 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158195 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158196 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158197 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158198 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158199 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158200 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158201 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158202 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158203 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 158205 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158206 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158207 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158209 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158210 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158211 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158212 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158213 | GIR_RootConstrainSelectedInstOperands, |
| 158214 | // GIR_Coverage, 4730, |
| 158215 | GIR_EraseRootFromParent_Done, |
| 158216 | // Label 7442: @502483 |
| 158217 | GIM_Try, /*On fail goto*//*Label 7443*/ GIMT_Encode4(502580), // Rule ID 4734 // |
| 158218 | // MIs[0] offset |
| 158219 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158220 | // MIs[0] auxiliary |
| 158221 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158222 | // MIs[0] Operand 7 |
| 158223 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158225 | // (SIbuffer_load:{ *:[v2f64] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v2f64] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158229 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158230 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158231 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158232 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158233 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158234 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158235 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 158237 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158239 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158241 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158242 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158243 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158245 | GIR_RootConstrainSelectedInstOperands, |
| 158246 | // GIR_Coverage, 4734, |
| 158247 | GIR_EraseRootFromParent_Done, |
| 158248 | // Label 7443: @502580 |
| 158249 | GIM_Reject, |
| 158250 | // Label 7427: @502581 |
| 158251 | GIM_Reject, |
| 158252 | // Label 7301: @502582 |
| 158253 | GIM_Try, /*On fail goto*//*Label 7444*/ GIMT_Encode4(503796), |
| 158254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 158255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 158256 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 158257 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 158258 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 158259 | GIM_Try, /*On fail goto*//*Label 7445*/ GIMT_Encode4(502675), // Rule ID 4687 // |
| 158260 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158263 | // MIs[0] offset |
| 158264 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158265 | // MIs[0] auxiliary |
| 158266 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158267 | // MIs[0] Operand 7 |
| 158268 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158270 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), |
| 158272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158273 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158274 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158275 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158277 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158278 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158279 | GIR_RootConstrainSelectedInstOperands, |
| 158280 | // GIR_Coverage, 4687, |
| 158281 | GIR_EraseRootFromParent_Done, |
| 158282 | // Label 7445: @502675 |
| 158283 | GIM_Try, /*On fail goto*//*Label 7446*/ GIMT_Encode4(502744), // Rule ID 4691 // |
| 158284 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158285 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158286 | // MIs[0] offset |
| 158287 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158288 | // MIs[0] auxiliary |
| 158289 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158290 | // MIs[0] Operand 7 |
| 158291 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158293 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158294 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET), |
| 158295 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158296 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158298 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158302 | GIR_RootConstrainSelectedInstOperands, |
| 158303 | // GIR_Coverage, 4691, |
| 158304 | GIR_EraseRootFromParent_Done, |
| 158305 | // Label 7446: @502744 |
| 158306 | GIM_Try, /*On fail goto*//*Label 7447*/ GIMT_Encode4(502816), // Rule ID 4695 // |
| 158307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158308 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158309 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158310 | // MIs[0] offset |
| 158311 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158312 | // MIs[0] auxiliary |
| 158313 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158314 | // MIs[0] Operand 7 |
| 158315 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158316 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158317 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158318 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFSET), |
| 158319 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158320 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158322 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158324 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158325 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158326 | GIR_RootConstrainSelectedInstOperands, |
| 158327 | // GIR_Coverage, 4695, |
| 158328 | GIR_EraseRootFromParent_Done, |
| 158329 | // Label 7447: @502816 |
| 158330 | GIM_Try, /*On fail goto*//*Label 7448*/ GIMT_Encode4(502885), // Rule ID 4699 // |
| 158331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158332 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158333 | // MIs[0] offset |
| 158334 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158335 | // MIs[0] auxiliary |
| 158336 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158337 | // MIs[0] Operand 7 |
| 158338 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158340 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFSET), |
| 158342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158343 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158345 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158346 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158349 | GIR_RootConstrainSelectedInstOperands, |
| 158350 | // GIR_Coverage, 4699, |
| 158351 | GIR_EraseRootFromParent_Done, |
| 158352 | // Label 7448: @502885 |
| 158353 | GIM_Try, /*On fail goto*//*Label 7449*/ GIMT_Encode4(502955), // Rule ID 4688 // |
| 158354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158355 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158356 | // MIs[0] offset |
| 158357 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158358 | // MIs[0] auxiliary |
| 158359 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158360 | // MIs[0] Operand 7 |
| 158361 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158362 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158363 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158364 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN), |
| 158365 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158366 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158367 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158369 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158370 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158371 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158373 | GIR_RootConstrainSelectedInstOperands, |
| 158374 | // GIR_Coverage, 4688, |
| 158375 | GIR_EraseRootFromParent_Done, |
| 158376 | // Label 7449: @502955 |
| 158377 | GIM_Try, /*On fail goto*//*Label 7450*/ GIMT_Encode4(503022), // Rule ID 4692 // |
| 158378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158379 | // MIs[0] offset |
| 158380 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158381 | // MIs[0] auxiliary |
| 158382 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158383 | // MIs[0] Operand 7 |
| 158384 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158385 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158386 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158387 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN), |
| 158388 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158389 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158390 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158392 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158393 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158395 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158396 | GIR_RootConstrainSelectedInstOperands, |
| 158397 | // GIR_Coverage, 4692, |
| 158398 | GIR_EraseRootFromParent_Done, |
| 158399 | // Label 7450: @503022 |
| 158400 | GIM_Try, /*On fail goto*//*Label 7451*/ GIMT_Encode4(503092), // Rule ID 4696 // |
| 158401 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158402 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158403 | // MIs[0] offset |
| 158404 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158405 | // MIs[0] auxiliary |
| 158406 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158407 | // MIs[0] Operand 7 |
| 158408 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158410 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_OFFEN), |
| 158412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158413 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158414 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158416 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158418 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158420 | GIR_RootConstrainSelectedInstOperands, |
| 158421 | // GIR_Coverage, 4696, |
| 158422 | GIR_EraseRootFromParent_Done, |
| 158423 | // Label 7451: @503092 |
| 158424 | GIM_Try, /*On fail goto*//*Label 7452*/ GIMT_Encode4(503159), // Rule ID 4700 // |
| 158425 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158426 | // MIs[0] offset |
| 158427 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158428 | // MIs[0] auxiliary |
| 158429 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158430 | // MIs[0] Operand 7 |
| 158431 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158433 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_OFFEN), |
| 158435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158436 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158437 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158438 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158439 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158440 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158441 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158442 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158443 | GIR_RootConstrainSelectedInstOperands, |
| 158444 | // GIR_Coverage, 4700, |
| 158445 | GIR_EraseRootFromParent_Done, |
| 158446 | // Label 7452: @503159 |
| 158447 | GIM_Try, /*On fail goto*//*Label 7453*/ GIMT_Encode4(503221), // Rule ID 4689 // |
| 158448 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158449 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158450 | // MIs[0] offset |
| 158451 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158452 | // MIs[0] auxiliary |
| 158453 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158454 | // MIs[0] Operand 7 |
| 158455 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158456 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158457 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158458 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN), |
| 158459 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158460 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158461 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158462 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158463 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158465 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158467 | GIR_RootConstrainSelectedInstOperands, |
| 158468 | // GIR_Coverage, 4689, |
| 158469 | GIR_EraseRootFromParent_Done, |
| 158470 | // Label 7453: @503221 |
| 158471 | GIM_Try, /*On fail goto*//*Label 7454*/ GIMT_Encode4(503280), // Rule ID 4693 // |
| 158472 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158473 | // MIs[0] offset |
| 158474 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158475 | // MIs[0] auxiliary |
| 158476 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158477 | // MIs[0] Operand 7 |
| 158478 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158479 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158480 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN), |
| 158482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158483 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158484 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158485 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158486 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158487 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158488 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158489 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158490 | GIR_RootConstrainSelectedInstOperands, |
| 158491 | // GIR_Coverage, 4693, |
| 158492 | GIR_EraseRootFromParent_Done, |
| 158493 | // Label 7454: @503280 |
| 158494 | GIM_Try, /*On fail goto*//*Label 7455*/ GIMT_Encode4(503342), // Rule ID 4697 // |
| 158495 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158496 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158497 | // MIs[0] offset |
| 158498 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158499 | // MIs[0] auxiliary |
| 158500 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158501 | // MIs[0] Operand 7 |
| 158502 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158504 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_IDXEN), |
| 158506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158507 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158508 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158510 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158512 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158514 | GIR_RootConstrainSelectedInstOperands, |
| 158515 | // GIR_Coverage, 4697, |
| 158516 | GIR_EraseRootFromParent_Done, |
| 158517 | // Label 7455: @503342 |
| 158518 | GIM_Try, /*On fail goto*//*Label 7456*/ GIMT_Encode4(503401), // Rule ID 4701 // |
| 158519 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158520 | // MIs[0] offset |
| 158521 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158522 | // MIs[0] auxiliary |
| 158523 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158524 | // MIs[0] Operand 7 |
| 158525 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158527 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158528 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_IDXEN), |
| 158529 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158530 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158531 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158532 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158533 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158534 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158535 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158536 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158537 | GIR_RootConstrainSelectedInstOperands, |
| 158538 | // GIR_Coverage, 4701, |
| 158539 | GIR_EraseRootFromParent_Done, |
| 158540 | // Label 7456: @503401 |
| 158541 | GIM_Try, /*On fail goto*//*Label 7457*/ GIMT_Encode4(503501), // Rule ID 4690 // |
| 158542 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158543 | // MIs[0] offset |
| 158544 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158545 | // MIs[0] auxiliary |
| 158546 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158547 | // MIs[0] Operand 7 |
| 158548 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158550 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158551 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158552 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158553 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158554 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158555 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158556 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158557 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158558 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158559 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158560 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN), |
| 158562 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158563 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158564 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158566 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158568 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158570 | GIR_RootConstrainSelectedInstOperands, |
| 158571 | // GIR_Coverage, 4690, |
| 158572 | GIR_EraseRootFromParent_Done, |
| 158573 | // Label 7457: @503501 |
| 158574 | GIM_Try, /*On fail goto*//*Label 7458*/ GIMT_Encode4(503598), // Rule ID 4694 // |
| 158575 | // MIs[0] offset |
| 158576 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158577 | // MIs[0] auxiliary |
| 158578 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158579 | // MIs[0] Operand 7 |
| 158580 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158581 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158582 | // (SIbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158583 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158584 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158585 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158586 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158587 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158588 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158589 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158590 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158591 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158592 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158593 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN), |
| 158594 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158595 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158596 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158598 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158600 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158601 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158602 | GIR_RootConstrainSelectedInstOperands, |
| 158603 | // GIR_Coverage, 4694, |
| 158604 | GIR_EraseRootFromParent_Done, |
| 158605 | // Label 7458: @503598 |
| 158606 | GIM_Try, /*On fail goto*//*Label 7459*/ GIMT_Encode4(503698), // Rule ID 4698 // |
| 158607 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158608 | // MIs[0] offset |
| 158609 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158610 | // MIs[0] auxiliary |
| 158611 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158612 | // MIs[0] Operand 7 |
| 158613 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158615 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158616 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158617 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158618 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158619 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158620 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158621 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158622 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158623 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158624 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158625 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158626 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_BOTHEN), |
| 158627 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158628 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158629 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158631 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158633 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158634 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158635 | GIR_RootConstrainSelectedInstOperands, |
| 158636 | // GIR_Coverage, 4698, |
| 158637 | GIR_EraseRootFromParent_Done, |
| 158638 | // Label 7459: @503698 |
| 158639 | GIM_Try, /*On fail goto*//*Label 7460*/ GIMT_Encode4(503795), // Rule ID 4702 // |
| 158640 | // MIs[0] offset |
| 158641 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158642 | // MIs[0] auxiliary |
| 158643 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158644 | // MIs[0] Operand 7 |
| 158645 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158646 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158647 | // (SIbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158648 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 158649 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 158650 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 158651 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 158652 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 158653 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 158654 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 158655 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 158656 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158657 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 158658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_VBUFFER_BOTHEN), |
| 158659 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158660 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 158661 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158663 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158664 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158665 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158667 | GIR_RootConstrainSelectedInstOperands, |
| 158668 | // GIR_Coverage, 4702, |
| 158669 | GIR_EraseRootFromParent_Done, |
| 158670 | // Label 7460: @503795 |
| 158671 | GIM_Reject, |
| 158672 | // Label 7444: @503796 |
| 158673 | GIM_Reject, |
| 158674 | // Label 7302: @503797 |
| 158675 | GIM_Try, /*On fail goto*//*Label 7461*/ GIMT_Encode4(505607), |
| 158676 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 158677 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 158678 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 158679 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 158680 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 158681 | GIM_Try, /*On fail goto*//*Label 7462*/ GIMT_Encode4(503890), // Rule ID 4663 // |
| 158682 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158683 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158684 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158685 | // MIs[0] offset |
| 158686 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158687 | // MIs[0] auxiliary |
| 158688 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158689 | // MIs[0] Operand 7 |
| 158690 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158691 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158692 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158693 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 158694 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158695 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158696 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158697 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158698 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158699 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158700 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158701 | GIR_RootConstrainSelectedInstOperands, |
| 158702 | // GIR_Coverage, 4663, |
| 158703 | GIR_EraseRootFromParent_Done, |
| 158704 | // Label 7462: @503890 |
| 158705 | GIM_Try, /*On fail goto*//*Label 7463*/ GIMT_Encode4(503959), // Rule ID 4667 // |
| 158706 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158707 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158708 | // MIs[0] offset |
| 158709 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158710 | // MIs[0] auxiliary |
| 158711 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158712 | // MIs[0] Operand 7 |
| 158713 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158715 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 158717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158718 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158720 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158721 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158722 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158723 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158724 | GIR_RootConstrainSelectedInstOperands, |
| 158725 | // GIR_Coverage, 4667, |
| 158726 | GIR_EraseRootFromParent_Done, |
| 158727 | // Label 7463: @503959 |
| 158728 | GIM_Try, /*On fail goto*//*Label 7464*/ GIMT_Encode4(504031), // Rule ID 4671 // |
| 158729 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158730 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158731 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158732 | // MIs[0] offset |
| 158733 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158734 | // MIs[0] auxiliary |
| 158735 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158736 | // MIs[0] Operand 7 |
| 158737 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158739 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158740 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 158741 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158742 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158743 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158744 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158745 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158746 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158747 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158748 | GIR_RootConstrainSelectedInstOperands, |
| 158749 | // GIR_Coverage, 4671, |
| 158750 | GIR_EraseRootFromParent_Done, |
| 158751 | // Label 7464: @504031 |
| 158752 | GIM_Try, /*On fail goto*//*Label 7465*/ GIMT_Encode4(504100), // Rule ID 4675 // |
| 158753 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158754 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158755 | // MIs[0] offset |
| 158756 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158757 | // MIs[0] auxiliary |
| 158758 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158759 | // MIs[0] Operand 7 |
| 158760 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158761 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158762 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158763 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 158764 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158765 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158766 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158767 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158768 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158769 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158770 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158771 | GIR_RootConstrainSelectedInstOperands, |
| 158772 | // GIR_Coverage, 4675, |
| 158773 | GIR_EraseRootFromParent_Done, |
| 158774 | // Label 7465: @504100 |
| 158775 | GIM_Try, /*On fail goto*//*Label 7466*/ GIMT_Encode4(504172), // Rule ID 4679 // |
| 158776 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158777 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158778 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158779 | // MIs[0] offset |
| 158780 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158781 | // MIs[0] auxiliary |
| 158782 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158783 | // MIs[0] Operand 7 |
| 158784 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158785 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158786 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFSET:{ *:[v4bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFSET), |
| 158788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158789 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158791 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158793 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158794 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158795 | GIR_RootConstrainSelectedInstOperands, |
| 158796 | // GIR_Coverage, 4679, |
| 158797 | GIR_EraseRootFromParent_Done, |
| 158798 | // Label 7466: @504172 |
| 158799 | GIM_Try, /*On fail goto*//*Label 7467*/ GIMT_Encode4(504241), // Rule ID 4683 // |
| 158800 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158801 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158802 | // MIs[0] offset |
| 158803 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158804 | // MIs[0] auxiliary |
| 158805 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158806 | // MIs[0] Operand 7 |
| 158807 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158808 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158809 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET:{ *:[v4bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158810 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFSET), |
| 158811 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158812 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158813 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158814 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158815 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158816 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158817 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158818 | GIR_RootConstrainSelectedInstOperands, |
| 158819 | // GIR_Coverage, 4683, |
| 158820 | GIR_EraseRootFromParent_Done, |
| 158821 | // Label 7467: @504241 |
| 158822 | GIM_Try, /*On fail goto*//*Label 7468*/ GIMT_Encode4(504311), // Rule ID 4664 // |
| 158823 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158824 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158825 | // MIs[0] offset |
| 158826 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158827 | // MIs[0] auxiliary |
| 158828 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158829 | // MIs[0] Operand 7 |
| 158830 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158831 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158832 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158833 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 158834 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158835 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158836 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158837 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158838 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158839 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158840 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158841 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158842 | GIR_RootConstrainSelectedInstOperands, |
| 158843 | // GIR_Coverage, 4664, |
| 158844 | GIR_EraseRootFromParent_Done, |
| 158845 | // Label 7468: @504311 |
| 158846 | GIM_Try, /*On fail goto*//*Label 7469*/ GIMT_Encode4(504378), // Rule ID 4668 // |
| 158847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158848 | // MIs[0] offset |
| 158849 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158850 | // MIs[0] auxiliary |
| 158851 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158852 | // MIs[0] Operand 7 |
| 158853 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158855 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 158857 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158858 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158859 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158861 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158863 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158864 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158865 | GIR_RootConstrainSelectedInstOperands, |
| 158866 | // GIR_Coverage, 4668, |
| 158867 | GIR_EraseRootFromParent_Done, |
| 158868 | // Label 7469: @504378 |
| 158869 | GIM_Try, /*On fail goto*//*Label 7470*/ GIMT_Encode4(504448), // Rule ID 4672 // |
| 158870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158871 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158872 | // MIs[0] offset |
| 158873 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158874 | // MIs[0] auxiliary |
| 158875 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158876 | // MIs[0] Operand 7 |
| 158877 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158879 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 158881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158882 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158883 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158885 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158886 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158887 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158889 | GIR_RootConstrainSelectedInstOperands, |
| 158890 | // GIR_Coverage, 4672, |
| 158891 | GIR_EraseRootFromParent_Done, |
| 158892 | // Label 7470: @504448 |
| 158893 | GIM_Try, /*On fail goto*//*Label 7471*/ GIMT_Encode4(504515), // Rule ID 4676 // |
| 158894 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158895 | // MIs[0] offset |
| 158896 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158897 | // MIs[0] auxiliary |
| 158898 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158899 | // MIs[0] Operand 7 |
| 158900 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158901 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158902 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 158904 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158905 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158906 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158908 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158909 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158910 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158911 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158912 | GIR_RootConstrainSelectedInstOperands, |
| 158913 | // GIR_Coverage, 4676, |
| 158914 | GIR_EraseRootFromParent_Done, |
| 158915 | // Label 7471: @504515 |
| 158916 | GIM_Try, /*On fail goto*//*Label 7472*/ GIMT_Encode4(504585), // Rule ID 4680 // |
| 158917 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158919 | // MIs[0] offset |
| 158920 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158921 | // MIs[0] auxiliary |
| 158922 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158923 | // MIs[0] Operand 7 |
| 158924 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158926 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_OFFEN:{ *:[v4bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_OFFEN), |
| 158928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158929 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158930 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158932 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158933 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158934 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158935 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158936 | GIR_RootConstrainSelectedInstOperands, |
| 158937 | // GIR_Coverage, 4680, |
| 158938 | GIR_EraseRootFromParent_Done, |
| 158939 | // Label 7472: @504585 |
| 158940 | GIM_Try, /*On fail goto*//*Label 7473*/ GIMT_Encode4(504652), // Rule ID 4684 // |
| 158941 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 158942 | // MIs[0] offset |
| 158943 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158944 | // MIs[0] auxiliary |
| 158945 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158946 | // MIs[0] Operand 7 |
| 158947 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 158948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158949 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN:{ *:[v4bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158950 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_OFFEN), |
| 158951 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158952 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 158953 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158954 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158955 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158956 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158957 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158958 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158959 | GIR_RootConstrainSelectedInstOperands, |
| 158960 | // GIR_Coverage, 4684, |
| 158961 | GIR_EraseRootFromParent_Done, |
| 158962 | // Label 7473: @504652 |
| 158963 | GIM_Try, /*On fail goto*//*Label 7474*/ GIMT_Encode4(504714), // Rule ID 4665 // |
| 158964 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 158965 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158966 | // MIs[0] offset |
| 158967 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158968 | // MIs[0] auxiliary |
| 158969 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158970 | // MIs[0] Operand 7 |
| 158971 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158972 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158973 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 158975 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158976 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 158977 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 158978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 158979 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 158980 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 158981 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 158982 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 158983 | GIR_RootConstrainSelectedInstOperands, |
| 158984 | // GIR_Coverage, 4665, |
| 158985 | GIR_EraseRootFromParent_Done, |
| 158986 | // Label 7474: @504714 |
| 158987 | GIM_Try, /*On fail goto*//*Label 7475*/ GIMT_Encode4(504773), // Rule ID 4669 // |
| 158988 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 158989 | // MIs[0] offset |
| 158990 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 158991 | // MIs[0] auxiliary |
| 158992 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 158993 | // MIs[0] Operand 7 |
| 158994 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 158995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 158996 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 158997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 158998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 158999 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159000 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159002 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159003 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159004 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159005 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159006 | GIR_RootConstrainSelectedInstOperands, |
| 159007 | // GIR_Coverage, 4669, |
| 159008 | GIR_EraseRootFromParent_Done, |
| 159009 | // Label 7475: @504773 |
| 159010 | GIM_Try, /*On fail goto*//*Label 7476*/ GIMT_Encode4(504835), // Rule ID 4673 // |
| 159011 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159013 | // MIs[0] offset |
| 159014 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159015 | // MIs[0] auxiliary |
| 159016 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159017 | // MIs[0] Operand 7 |
| 159018 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159020 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 159022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159023 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159024 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159025 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159026 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159028 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159030 | GIR_RootConstrainSelectedInstOperands, |
| 159031 | // GIR_Coverage, 4673, |
| 159032 | GIR_EraseRootFromParent_Done, |
| 159033 | // Label 7476: @504835 |
| 159034 | GIM_Try, /*On fail goto*//*Label 7477*/ GIMT_Encode4(504894), // Rule ID 4677 // |
| 159035 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159036 | // MIs[0] offset |
| 159037 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159038 | // MIs[0] auxiliary |
| 159039 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159040 | // MIs[0] Operand 7 |
| 159041 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159043 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 159045 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159046 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159047 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159048 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159049 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159050 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159051 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159053 | GIR_RootConstrainSelectedInstOperands, |
| 159054 | // GIR_Coverage, 4677, |
| 159055 | GIR_EraseRootFromParent_Done, |
| 159056 | // Label 7477: @504894 |
| 159057 | GIM_Try, /*On fail goto*//*Label 7478*/ GIMT_Encode4(504956), // Rule ID 4681 // |
| 159058 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159060 | // MIs[0] offset |
| 159061 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159062 | // MIs[0] auxiliary |
| 159063 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159064 | // MIs[0] Operand 7 |
| 159065 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159066 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159067 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_IDXEN:{ *:[v4bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159068 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_IDXEN), |
| 159069 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159070 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159071 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159072 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159073 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159074 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159075 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159076 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159077 | GIR_RootConstrainSelectedInstOperands, |
| 159078 | // GIR_Coverage, 4681, |
| 159079 | GIR_EraseRootFromParent_Done, |
| 159080 | // Label 7478: @504956 |
| 159081 | GIM_Try, /*On fail goto*//*Label 7479*/ GIMT_Encode4(505015), // Rule ID 4685 // |
| 159082 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159083 | // MIs[0] offset |
| 159084 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159085 | // MIs[0] auxiliary |
| 159086 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159087 | // MIs[0] Operand 7 |
| 159088 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159090 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN:{ *:[v4bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_IDXEN), |
| 159092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159093 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159094 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159096 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159098 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159099 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159100 | GIR_RootConstrainSelectedInstOperands, |
| 159101 | // GIR_Coverage, 4685, |
| 159102 | GIR_EraseRootFromParent_Done, |
| 159103 | // Label 7479: @505015 |
| 159104 | GIM_Try, /*On fail goto*//*Label 7480*/ GIMT_Encode4(505115), // Rule ID 4666 // |
| 159105 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159106 | // MIs[0] offset |
| 159107 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159108 | // MIs[0] auxiliary |
| 159109 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159110 | // MIs[0] Operand 7 |
| 159111 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159112 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159113 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159114 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159115 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159116 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159117 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159118 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159119 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159120 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159121 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159122 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159123 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159124 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 159125 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159126 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159127 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159128 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159129 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159130 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159131 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159132 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159133 | GIR_RootConstrainSelectedInstOperands, |
| 159134 | // GIR_Coverage, 4666, |
| 159135 | GIR_EraseRootFromParent_Done, |
| 159136 | // Label 7480: @505115 |
| 159137 | GIM_Try, /*On fail goto*//*Label 7481*/ GIMT_Encode4(505212), // Rule ID 4670 // |
| 159138 | // MIs[0] offset |
| 159139 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159140 | // MIs[0] auxiliary |
| 159141 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159142 | // MIs[0] Operand 7 |
| 159143 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159145 | // (SIbuffer_load:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159146 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159147 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159148 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159149 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159150 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159151 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159152 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159153 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159154 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159155 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 159157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159159 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159161 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159162 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159163 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159165 | GIR_RootConstrainSelectedInstOperands, |
| 159166 | // GIR_Coverage, 4670, |
| 159167 | GIR_EraseRootFromParent_Done, |
| 159168 | // Label 7481: @505212 |
| 159169 | GIM_Try, /*On fail goto*//*Label 7482*/ GIMT_Encode4(505312), // Rule ID 4674 // |
| 159170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159171 | // MIs[0] offset |
| 159172 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159173 | // MIs[0] auxiliary |
| 159174 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159175 | // MIs[0] Operand 7 |
| 159176 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159177 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159178 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159179 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159180 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159181 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159182 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159183 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159184 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159185 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159186 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159187 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159188 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 159190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159191 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159192 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159194 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159196 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159198 | GIR_RootConstrainSelectedInstOperands, |
| 159199 | // GIR_Coverage, 4674, |
| 159200 | GIR_EraseRootFromParent_Done, |
| 159201 | // Label 7482: @505312 |
| 159202 | GIM_Try, /*On fail goto*//*Label 7483*/ GIMT_Encode4(505409), // Rule ID 4678 // |
| 159203 | // MIs[0] offset |
| 159204 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159205 | // MIs[0] auxiliary |
| 159206 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159207 | // MIs[0] Operand 7 |
| 159208 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159209 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159210 | // (SIbuffer_load:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159211 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159212 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159213 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159214 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159215 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159216 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159217 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159218 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159219 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159220 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 159222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159223 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159224 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159226 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159228 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159230 | GIR_RootConstrainSelectedInstOperands, |
| 159231 | // GIR_Coverage, 4678, |
| 159232 | GIR_EraseRootFromParent_Done, |
| 159233 | // Label 7483: @505409 |
| 159234 | GIM_Try, /*On fail goto*//*Label 7484*/ GIMT_Encode4(505509), // Rule ID 4682 // |
| 159235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159236 | // MIs[0] offset |
| 159237 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159238 | // MIs[0] auxiliary |
| 159239 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159240 | // MIs[0] Operand 7 |
| 159241 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159242 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159243 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_BOTHEN:{ *:[v4bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159244 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159245 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159246 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159247 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159248 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159249 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159250 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159251 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159252 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159253 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159254 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_BOTHEN), |
| 159255 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159256 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159257 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159258 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159259 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159260 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159261 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159262 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159263 | GIR_RootConstrainSelectedInstOperands, |
| 159264 | // GIR_Coverage, 4682, |
| 159265 | GIR_EraseRootFromParent_Done, |
| 159266 | // Label 7484: @505509 |
| 159267 | GIM_Try, /*On fail goto*//*Label 7485*/ GIMT_Encode4(505606), // Rule ID 4686 // |
| 159268 | // MIs[0] offset |
| 159269 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159270 | // MIs[0] auxiliary |
| 159271 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159272 | // MIs[0] Operand 7 |
| 159273 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159275 | // (SIbuffer_load:{ *:[v4bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN:{ *:[v4bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159276 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159277 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159278 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159279 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159280 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159281 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159282 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159283 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159284 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159285 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159286 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_VBUFFER_BOTHEN), |
| 159287 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159288 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159289 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159290 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159291 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159292 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159293 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159294 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159295 | GIR_RootConstrainSelectedInstOperands, |
| 159296 | // GIR_Coverage, 4686, |
| 159297 | GIR_EraseRootFromParent_Done, |
| 159298 | // Label 7485: @505606 |
| 159299 | GIM_Reject, |
| 159300 | // Label 7461: @505607 |
| 159301 | GIM_Reject, |
| 159302 | // Label 7303: @505608 |
| 159303 | GIM_Try, /*On fail goto*//*Label 7486*/ GIMT_Encode4(506822), |
| 159304 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 159305 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 159306 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 159307 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 159308 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 159309 | GIM_Try, /*On fail goto*//*Label 7487*/ GIMT_Encode4(505701), // Rule ID 4703 // |
| 159310 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159311 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159312 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159313 | // MIs[0] offset |
| 159314 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159315 | // MIs[0] auxiliary |
| 159316 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159317 | // MIs[0] Operand 7 |
| 159318 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159320 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 159322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159323 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159325 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159326 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159327 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159328 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159329 | GIR_RootConstrainSelectedInstOperands, |
| 159330 | // GIR_Coverage, 4703, |
| 159331 | GIR_EraseRootFromParent_Done, |
| 159332 | // Label 7487: @505701 |
| 159333 | GIM_Try, /*On fail goto*//*Label 7488*/ GIMT_Encode4(505770), // Rule ID 4707 // |
| 159334 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159335 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159336 | // MIs[0] offset |
| 159337 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159338 | // MIs[0] auxiliary |
| 159339 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159340 | // MIs[0] Operand 7 |
| 159341 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159343 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 159345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159346 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159347 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159348 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159349 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159350 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159351 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159352 | GIR_RootConstrainSelectedInstOperands, |
| 159353 | // GIR_Coverage, 4707, |
| 159354 | GIR_EraseRootFromParent_Done, |
| 159355 | // Label 7488: @505770 |
| 159356 | GIM_Try, /*On fail goto*//*Label 7489*/ GIMT_Encode4(505842), // Rule ID 4711 // |
| 159357 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159358 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159359 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159360 | // MIs[0] offset |
| 159361 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159362 | // MIs[0] auxiliary |
| 159363 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159364 | // MIs[0] Operand 7 |
| 159365 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159366 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159367 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 159369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159370 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159371 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159372 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159373 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159374 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159375 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159376 | GIR_RootConstrainSelectedInstOperands, |
| 159377 | // GIR_Coverage, 4711, |
| 159378 | GIR_EraseRootFromParent_Done, |
| 159379 | // Label 7489: @505842 |
| 159380 | GIM_Try, /*On fail goto*//*Label 7490*/ GIMT_Encode4(505911), // Rule ID 4715 // |
| 159381 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159382 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159383 | // MIs[0] offset |
| 159384 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159385 | // MIs[0] auxiliary |
| 159386 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159387 | // MIs[0] Operand 7 |
| 159388 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159389 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159390 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159391 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 159392 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159393 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159395 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159396 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159397 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159398 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159399 | GIR_RootConstrainSelectedInstOperands, |
| 159400 | // GIR_Coverage, 4715, |
| 159401 | GIR_EraseRootFromParent_Done, |
| 159402 | // Label 7490: @505911 |
| 159403 | GIM_Try, /*On fail goto*//*Label 7491*/ GIMT_Encode4(505981), // Rule ID 4704 // |
| 159404 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159406 | // MIs[0] offset |
| 159407 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159408 | // MIs[0] auxiliary |
| 159409 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159410 | // MIs[0] Operand 7 |
| 159411 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159412 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159413 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 159415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159416 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159417 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159419 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159420 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159421 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159422 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159423 | GIR_RootConstrainSelectedInstOperands, |
| 159424 | // GIR_Coverage, 4704, |
| 159425 | GIR_EraseRootFromParent_Done, |
| 159426 | // Label 7491: @505981 |
| 159427 | GIM_Try, /*On fail goto*//*Label 7492*/ GIMT_Encode4(506048), // Rule ID 4708 // |
| 159428 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159429 | // MIs[0] offset |
| 159430 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159431 | // MIs[0] auxiliary |
| 159432 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159433 | // MIs[0] Operand 7 |
| 159434 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159436 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 159438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159439 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159440 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159442 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159444 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159445 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159446 | GIR_RootConstrainSelectedInstOperands, |
| 159447 | // GIR_Coverage, 4708, |
| 159448 | GIR_EraseRootFromParent_Done, |
| 159449 | // Label 7492: @506048 |
| 159450 | GIM_Try, /*On fail goto*//*Label 7493*/ GIMT_Encode4(506118), // Rule ID 4712 // |
| 159451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159453 | // MIs[0] offset |
| 159454 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159455 | // MIs[0] auxiliary |
| 159456 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159457 | // MIs[0] Operand 7 |
| 159458 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159460 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 159462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159463 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159464 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159466 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159470 | GIR_RootConstrainSelectedInstOperands, |
| 159471 | // GIR_Coverage, 4712, |
| 159472 | GIR_EraseRootFromParent_Done, |
| 159473 | // Label 7493: @506118 |
| 159474 | GIM_Try, /*On fail goto*//*Label 7494*/ GIMT_Encode4(506185), // Rule ID 4716 // |
| 159475 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159476 | // MIs[0] offset |
| 159477 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159478 | // MIs[0] auxiliary |
| 159479 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159480 | // MIs[0] Operand 7 |
| 159481 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159483 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 159485 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159486 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159487 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159489 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159490 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159491 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159493 | GIR_RootConstrainSelectedInstOperands, |
| 159494 | // GIR_Coverage, 4716, |
| 159495 | GIR_EraseRootFromParent_Done, |
| 159496 | // Label 7494: @506185 |
| 159497 | GIM_Try, /*On fail goto*//*Label 7495*/ GIMT_Encode4(506247), // Rule ID 4705 // |
| 159498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159500 | // MIs[0] offset |
| 159501 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159502 | // MIs[0] auxiliary |
| 159503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159504 | // MIs[0] Operand 7 |
| 159505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159507 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 159509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159510 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159511 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159513 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159514 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159515 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159517 | GIR_RootConstrainSelectedInstOperands, |
| 159518 | // GIR_Coverage, 4705, |
| 159519 | GIR_EraseRootFromParent_Done, |
| 159520 | // Label 7495: @506247 |
| 159521 | GIM_Try, /*On fail goto*//*Label 7496*/ GIMT_Encode4(506306), // Rule ID 4709 // |
| 159522 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159523 | // MIs[0] offset |
| 159524 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159525 | // MIs[0] auxiliary |
| 159526 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159527 | // MIs[0] Operand 7 |
| 159528 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159529 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159530 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 159532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159533 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159534 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159536 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159537 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159538 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159539 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159540 | GIR_RootConstrainSelectedInstOperands, |
| 159541 | // GIR_Coverage, 4709, |
| 159542 | GIR_EraseRootFromParent_Done, |
| 159543 | // Label 7496: @506306 |
| 159544 | GIM_Try, /*On fail goto*//*Label 7497*/ GIMT_Encode4(506368), // Rule ID 4713 // |
| 159545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159546 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159547 | // MIs[0] offset |
| 159548 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159549 | // MIs[0] auxiliary |
| 159550 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159551 | // MIs[0] Operand 7 |
| 159552 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159554 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159555 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 159556 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159557 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159558 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159559 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159560 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159561 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159562 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159563 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159564 | GIR_RootConstrainSelectedInstOperands, |
| 159565 | // GIR_Coverage, 4713, |
| 159566 | GIR_EraseRootFromParent_Done, |
| 159567 | // Label 7497: @506368 |
| 159568 | GIM_Try, /*On fail goto*//*Label 7498*/ GIMT_Encode4(506427), // Rule ID 4717 // |
| 159569 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159570 | // MIs[0] offset |
| 159571 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159572 | // MIs[0] auxiliary |
| 159573 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159574 | // MIs[0] Operand 7 |
| 159575 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159576 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159577 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 159579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159580 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 159581 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159583 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159584 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159585 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159587 | GIR_RootConstrainSelectedInstOperands, |
| 159588 | // GIR_Coverage, 4717, |
| 159589 | GIR_EraseRootFromParent_Done, |
| 159590 | // Label 7498: @506427 |
| 159591 | GIM_Try, /*On fail goto*//*Label 7499*/ GIMT_Encode4(506527), // Rule ID 4706 // |
| 159592 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159593 | // MIs[0] offset |
| 159594 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159595 | // MIs[0] auxiliary |
| 159596 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159597 | // MIs[0] Operand 7 |
| 159598 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159600 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159601 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159602 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159603 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159604 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159605 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159606 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159607 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159608 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159609 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159610 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 159612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159613 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159614 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159616 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159618 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159620 | GIR_RootConstrainSelectedInstOperands, |
| 159621 | // GIR_Coverage, 4706, |
| 159622 | GIR_EraseRootFromParent_Done, |
| 159623 | // Label 7499: @506527 |
| 159624 | GIM_Try, /*On fail goto*//*Label 7500*/ GIMT_Encode4(506624), // Rule ID 4710 // |
| 159625 | // MIs[0] offset |
| 159626 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159627 | // MIs[0] auxiliary |
| 159628 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159629 | // MIs[0] Operand 7 |
| 159630 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159632 | // (SIbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159633 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159634 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159635 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159636 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159637 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159638 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159639 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159640 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159641 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159642 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 159644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159646 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159648 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159649 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159650 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159651 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159652 | GIR_RootConstrainSelectedInstOperands, |
| 159653 | // GIR_Coverage, 4710, |
| 159654 | GIR_EraseRootFromParent_Done, |
| 159655 | // Label 7500: @506624 |
| 159656 | GIM_Try, /*On fail goto*//*Label 7501*/ GIMT_Encode4(506724), // Rule ID 4714 // |
| 159657 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159658 | // MIs[0] offset |
| 159659 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159660 | // MIs[0] auxiliary |
| 159661 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159662 | // MIs[0] Operand 7 |
| 159663 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159664 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159665 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159666 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159667 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159668 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159669 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159670 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159671 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159672 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159673 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159674 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159675 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159676 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 159677 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159678 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159679 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159680 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159681 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159682 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159683 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159684 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159685 | GIR_RootConstrainSelectedInstOperands, |
| 159686 | // GIR_Coverage, 4714, |
| 159687 | GIR_EraseRootFromParent_Done, |
| 159688 | // Label 7501: @506724 |
| 159689 | GIM_Try, /*On fail goto*//*Label 7502*/ GIMT_Encode4(506821), // Rule ID 4718 // |
| 159690 | // MIs[0] offset |
| 159691 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159692 | // MIs[0] auxiliary |
| 159693 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159694 | // MIs[0] Operand 7 |
| 159695 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 159696 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159697 | // (SIbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159698 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 159699 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 159700 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 159701 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 159702 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 159703 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 159704 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 159705 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 159706 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159707 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 159708 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 159709 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159710 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 159711 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159713 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159714 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159715 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159717 | GIR_RootConstrainSelectedInstOperands, |
| 159718 | // GIR_Coverage, 4718, |
| 159719 | GIR_EraseRootFromParent_Done, |
| 159720 | // Label 7502: @506821 |
| 159721 | GIM_Reject, |
| 159722 | // Label 7486: @506822 |
| 159723 | GIM_Reject, |
| 159724 | // Label 7304: @506823 |
| 159725 | GIM_Try, /*On fail goto*//*Label 7503*/ GIMT_Encode4(508633), |
| 159726 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 159727 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 159728 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 159729 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 159730 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 159731 | GIM_Try, /*On fail goto*//*Label 7504*/ GIMT_Encode4(506916), // Rule ID 4735 // |
| 159732 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159735 | // MIs[0] offset |
| 159736 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159737 | // MIs[0] auxiliary |
| 159738 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159739 | // MIs[0] Operand 7 |
| 159740 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159742 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 159744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159745 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159746 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159747 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159748 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159751 | GIR_RootConstrainSelectedInstOperands, |
| 159752 | // GIR_Coverage, 4735, |
| 159753 | GIR_EraseRootFromParent_Done, |
| 159754 | // Label 7504: @506916 |
| 159755 | GIM_Try, /*On fail goto*//*Label 7505*/ GIMT_Encode4(506985), // Rule ID 4739 // |
| 159756 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159758 | // MIs[0] offset |
| 159759 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159760 | // MIs[0] auxiliary |
| 159761 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159762 | // MIs[0] Operand 7 |
| 159763 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159765 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 159767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159768 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159770 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159771 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159772 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159774 | GIR_RootConstrainSelectedInstOperands, |
| 159775 | // GIR_Coverage, 4739, |
| 159776 | GIR_EraseRootFromParent_Done, |
| 159777 | // Label 7505: @506985 |
| 159778 | GIM_Try, /*On fail goto*//*Label 7506*/ GIMT_Encode4(507057), // Rule ID 4743 // |
| 159779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159780 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159781 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159782 | // MIs[0] offset |
| 159783 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159784 | // MIs[0] auxiliary |
| 159785 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159786 | // MIs[0] Operand 7 |
| 159787 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159788 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159789 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159790 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 159791 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159792 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159794 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159795 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159796 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159798 | GIR_RootConstrainSelectedInstOperands, |
| 159799 | // GIR_Coverage, 4743, |
| 159800 | GIR_EraseRootFromParent_Done, |
| 159801 | // Label 7506: @507057 |
| 159802 | GIM_Try, /*On fail goto*//*Label 7507*/ GIMT_Encode4(507126), // Rule ID 4747 // |
| 159803 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159804 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159805 | // MIs[0] offset |
| 159806 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159807 | // MIs[0] auxiliary |
| 159808 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159809 | // MIs[0] Operand 7 |
| 159810 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159812 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 159814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159815 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159817 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159818 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159819 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159821 | GIR_RootConstrainSelectedInstOperands, |
| 159822 | // GIR_Coverage, 4747, |
| 159823 | GIR_EraseRootFromParent_Done, |
| 159824 | // Label 7507: @507126 |
| 159825 | GIM_Try, /*On fail goto*//*Label 7508*/ GIMT_Encode4(507198), // Rule ID 4751 // |
| 159826 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159827 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159828 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159829 | // MIs[0] offset |
| 159830 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159831 | // MIs[0] auxiliary |
| 159832 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159833 | // MIs[0] Operand 7 |
| 159834 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159835 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159836 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFSET:{ *:[v8bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFSET), |
| 159838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159839 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159840 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159841 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159842 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159843 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159845 | GIR_RootConstrainSelectedInstOperands, |
| 159846 | // GIR_Coverage, 4751, |
| 159847 | GIR_EraseRootFromParent_Done, |
| 159848 | // Label 7508: @507198 |
| 159849 | GIM_Try, /*On fail goto*//*Label 7509*/ GIMT_Encode4(507267), // Rule ID 4755 // |
| 159850 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159851 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 159852 | // MIs[0] offset |
| 159853 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159854 | // MIs[0] auxiliary |
| 159855 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159856 | // MIs[0] Operand 7 |
| 159857 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159858 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159859 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET:{ *:[v8bf16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159860 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFSET), |
| 159861 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159862 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159863 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159864 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159865 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159866 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159867 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159868 | GIR_RootConstrainSelectedInstOperands, |
| 159869 | // GIR_Coverage, 4755, |
| 159870 | GIR_EraseRootFromParent_Done, |
| 159871 | // Label 7509: @507267 |
| 159872 | GIM_Try, /*On fail goto*//*Label 7510*/ GIMT_Encode4(507337), // Rule ID 4736 // |
| 159873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159874 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159875 | // MIs[0] offset |
| 159876 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159877 | // MIs[0] auxiliary |
| 159878 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159879 | // MIs[0] Operand 7 |
| 159880 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159881 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159882 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v8i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 159884 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159885 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159886 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159888 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159890 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159892 | GIR_RootConstrainSelectedInstOperands, |
| 159893 | // GIR_Coverage, 4736, |
| 159894 | GIR_EraseRootFromParent_Done, |
| 159895 | // Label 7510: @507337 |
| 159896 | GIM_Try, /*On fail goto*//*Label 7511*/ GIMT_Encode4(507404), // Rule ID 4740 // |
| 159897 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159898 | // MIs[0] offset |
| 159899 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159900 | // MIs[0] auxiliary |
| 159901 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159902 | // MIs[0] Operand 7 |
| 159903 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159904 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159905 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v8i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159906 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 159907 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159908 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159909 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159910 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159911 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159912 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159913 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159914 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159915 | GIR_RootConstrainSelectedInstOperands, |
| 159916 | // GIR_Coverage, 4740, |
| 159917 | GIR_EraseRootFromParent_Done, |
| 159918 | // Label 7511: @507404 |
| 159919 | GIM_Try, /*On fail goto*//*Label 7512*/ GIMT_Encode4(507474), // Rule ID 4744 // |
| 159920 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159921 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159922 | // MIs[0] offset |
| 159923 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159924 | // MIs[0] auxiliary |
| 159925 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159926 | // MIs[0] Operand 7 |
| 159927 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159928 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159929 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v8f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 159931 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159932 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159933 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159935 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159936 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159937 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159938 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159939 | GIR_RootConstrainSelectedInstOperands, |
| 159940 | // GIR_Coverage, 4744, |
| 159941 | GIR_EraseRootFromParent_Done, |
| 159942 | // Label 7512: @507474 |
| 159943 | GIM_Try, /*On fail goto*//*Label 7513*/ GIMT_Encode4(507541), // Rule ID 4748 // |
| 159944 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159945 | // MIs[0] offset |
| 159946 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159947 | // MIs[0] auxiliary |
| 159948 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159949 | // MIs[0] Operand 7 |
| 159950 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159952 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v8f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 159954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159955 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159956 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159958 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159959 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159961 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159962 | GIR_RootConstrainSelectedInstOperands, |
| 159963 | // GIR_Coverage, 4748, |
| 159964 | GIR_EraseRootFromParent_Done, |
| 159965 | // Label 7513: @507541 |
| 159966 | GIM_Try, /*On fail goto*//*Label 7514*/ GIMT_Encode4(507611), // Rule ID 4752 // |
| 159967 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 159968 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159969 | // MIs[0] offset |
| 159970 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159971 | // MIs[0] auxiliary |
| 159972 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159973 | // MIs[0] Operand 7 |
| 159974 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159975 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159976 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_OFFEN:{ *:[v8bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 159977 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_OFFEN), |
| 159978 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 159979 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 159980 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 159981 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 159982 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 159983 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 159984 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 159985 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 159986 | GIR_RootConstrainSelectedInstOperands, |
| 159987 | // GIR_Coverage, 4752, |
| 159988 | GIR_EraseRootFromParent_Done, |
| 159989 | // Label 7514: @507611 |
| 159990 | GIM_Try, /*On fail goto*//*Label 7515*/ GIMT_Encode4(507678), // Rule ID 4756 // |
| 159991 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 159992 | // MIs[0] offset |
| 159993 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 159994 | // MIs[0] auxiliary |
| 159995 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 159996 | // MIs[0] Operand 7 |
| 159997 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 159998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 159999 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN:{ *:[v8bf16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_OFFEN), |
| 160001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160002 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160003 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160005 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160006 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160007 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160008 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160009 | GIR_RootConstrainSelectedInstOperands, |
| 160010 | // GIR_Coverage, 4756, |
| 160011 | GIR_EraseRootFromParent_Done, |
| 160012 | // Label 7515: @507678 |
| 160013 | GIM_Try, /*On fail goto*//*Label 7516*/ GIMT_Encode4(507740), // Rule ID 4737 // |
| 160014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160015 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160016 | // MIs[0] offset |
| 160017 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160018 | // MIs[0] auxiliary |
| 160019 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160020 | // MIs[0] Operand 7 |
| 160021 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160023 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v8i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 160025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160026 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160027 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160029 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160033 | GIR_RootConstrainSelectedInstOperands, |
| 160034 | // GIR_Coverage, 4737, |
| 160035 | GIR_EraseRootFromParent_Done, |
| 160036 | // Label 7516: @507740 |
| 160037 | GIM_Try, /*On fail goto*//*Label 7517*/ GIMT_Encode4(507799), // Rule ID 4741 // |
| 160038 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160039 | // MIs[0] offset |
| 160040 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160041 | // MIs[0] auxiliary |
| 160042 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160043 | // MIs[0] Operand 7 |
| 160044 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160045 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160046 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v8i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160047 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 160048 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160049 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160050 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160052 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160053 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160054 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160055 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160056 | GIR_RootConstrainSelectedInstOperands, |
| 160057 | // GIR_Coverage, 4741, |
| 160058 | GIR_EraseRootFromParent_Done, |
| 160059 | // Label 7517: @507799 |
| 160060 | GIM_Try, /*On fail goto*//*Label 7518*/ GIMT_Encode4(507861), // Rule ID 4745 // |
| 160061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160062 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160063 | // MIs[0] offset |
| 160064 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160065 | // MIs[0] auxiliary |
| 160066 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160067 | // MIs[0] Operand 7 |
| 160068 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160069 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160070 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v8f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160071 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 160072 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160073 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160074 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160076 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160077 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160078 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160080 | GIR_RootConstrainSelectedInstOperands, |
| 160081 | // GIR_Coverage, 4745, |
| 160082 | GIR_EraseRootFromParent_Done, |
| 160083 | // Label 7518: @507861 |
| 160084 | GIM_Try, /*On fail goto*//*Label 7519*/ GIMT_Encode4(507920), // Rule ID 4749 // |
| 160085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160086 | // MIs[0] offset |
| 160087 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160088 | // MIs[0] auxiliary |
| 160089 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160090 | // MIs[0] Operand 7 |
| 160091 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160093 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v8f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 160095 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160096 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160097 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160099 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160100 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160101 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160102 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160103 | GIR_RootConstrainSelectedInstOperands, |
| 160104 | // GIR_Coverage, 4749, |
| 160105 | GIR_EraseRootFromParent_Done, |
| 160106 | // Label 7519: @507920 |
| 160107 | GIM_Try, /*On fail goto*//*Label 7520*/ GIMT_Encode4(507982), // Rule ID 4753 // |
| 160108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160109 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160110 | // MIs[0] offset |
| 160111 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160112 | // MIs[0] auxiliary |
| 160113 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160114 | // MIs[0] Operand 7 |
| 160115 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160116 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160117 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_IDXEN:{ *:[v8bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160118 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_IDXEN), |
| 160119 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160120 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160121 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160123 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160125 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160127 | GIR_RootConstrainSelectedInstOperands, |
| 160128 | // GIR_Coverage, 4753, |
| 160129 | GIR_EraseRootFromParent_Done, |
| 160130 | // Label 7520: @507982 |
| 160131 | GIM_Try, /*On fail goto*//*Label 7521*/ GIMT_Encode4(508041), // Rule ID 4757 // |
| 160132 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160133 | // MIs[0] offset |
| 160134 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160135 | // MIs[0] auxiliary |
| 160136 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160137 | // MIs[0] Operand 7 |
| 160138 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160139 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160140 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN:{ *:[v8bf16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_IDXEN), |
| 160142 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160143 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160144 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160146 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160149 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160150 | GIR_RootConstrainSelectedInstOperands, |
| 160151 | // GIR_Coverage, 4757, |
| 160152 | GIR_EraseRootFromParent_Done, |
| 160153 | // Label 7521: @508041 |
| 160154 | GIM_Try, /*On fail goto*//*Label 7522*/ GIMT_Encode4(508141), // Rule ID 4738 // |
| 160155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160156 | // MIs[0] offset |
| 160157 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160158 | // MIs[0] auxiliary |
| 160159 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160160 | // MIs[0] Operand 7 |
| 160161 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160163 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160165 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160166 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160167 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160168 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160169 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160170 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160171 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160173 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 160175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160177 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160179 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160183 | GIR_RootConstrainSelectedInstOperands, |
| 160184 | // GIR_Coverage, 4738, |
| 160185 | GIR_EraseRootFromParent_Done, |
| 160186 | // Label 7522: @508141 |
| 160187 | GIM_Try, /*On fail goto*//*Label 7523*/ GIMT_Encode4(508238), // Rule ID 4742 // |
| 160188 | // MIs[0] offset |
| 160189 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160190 | // MIs[0] auxiliary |
| 160191 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160192 | // MIs[0] Operand 7 |
| 160193 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160195 | // (SIbuffer_load:{ *:[v8i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v8i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160196 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160197 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160198 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160199 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160200 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160203 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160204 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 160207 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160208 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160209 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160210 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160211 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160212 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160214 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160215 | GIR_RootConstrainSelectedInstOperands, |
| 160216 | // GIR_Coverage, 4742, |
| 160217 | GIR_EraseRootFromParent_Done, |
| 160218 | // Label 7523: @508238 |
| 160219 | GIM_Try, /*On fail goto*//*Label 7524*/ GIMT_Encode4(508338), // Rule ID 4746 // |
| 160220 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160221 | // MIs[0] offset |
| 160222 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160223 | // MIs[0] auxiliary |
| 160224 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160225 | // MIs[0] Operand 7 |
| 160226 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160227 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160228 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v8f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160229 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160230 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160231 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160232 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160233 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160235 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160236 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160237 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 160240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160241 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160242 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160244 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160245 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160248 | GIR_RootConstrainSelectedInstOperands, |
| 160249 | // GIR_Coverage, 4746, |
| 160250 | GIR_EraseRootFromParent_Done, |
| 160251 | // Label 7524: @508338 |
| 160252 | GIM_Try, /*On fail goto*//*Label 7525*/ GIMT_Encode4(508435), // Rule ID 4750 // |
| 160253 | // MIs[0] offset |
| 160254 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160255 | // MIs[0] auxiliary |
| 160256 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160257 | // MIs[0] Operand 7 |
| 160258 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160259 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160260 | // (SIbuffer_load:{ *:[v8f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v8f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160261 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160262 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160263 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160264 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160265 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160266 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160267 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160268 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160269 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160270 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 160272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160273 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160274 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160276 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160277 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160278 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160279 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160280 | GIR_RootConstrainSelectedInstOperands, |
| 160281 | // GIR_Coverage, 4750, |
| 160282 | GIR_EraseRootFromParent_Done, |
| 160283 | // Label 7525: @508435 |
| 160284 | GIM_Try, /*On fail goto*//*Label 7526*/ GIMT_Encode4(508535), // Rule ID 4754 // |
| 160285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160286 | // MIs[0] offset |
| 160287 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160288 | // MIs[0] auxiliary |
| 160289 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160290 | // MIs[0] Operand 7 |
| 160291 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160293 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_BOTHEN:{ *:[v8bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160295 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160296 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160297 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160298 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160299 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160300 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160301 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160302 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160303 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_BOTHEN), |
| 160305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160307 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160309 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160310 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160311 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160313 | GIR_RootConstrainSelectedInstOperands, |
| 160314 | // GIR_Coverage, 4754, |
| 160315 | GIR_EraseRootFromParent_Done, |
| 160316 | // Label 7526: @508535 |
| 160317 | GIM_Try, /*On fail goto*//*Label 7527*/ GIMT_Encode4(508632), // Rule ID 4758 // |
| 160318 | // MIs[0] offset |
| 160319 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160320 | // MIs[0] auxiliary |
| 160321 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160322 | // MIs[0] Operand 7 |
| 160323 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160325 | // (SIbuffer_load:{ *:[v8bf16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN:{ *:[v8bf16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160329 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160330 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160331 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160332 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160333 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160334 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160335 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_VBUFFER_BOTHEN), |
| 160337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160339 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160341 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160342 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160343 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160345 | GIR_RootConstrainSelectedInstOperands, |
| 160346 | // GIR_Coverage, 4758, |
| 160347 | GIR_EraseRootFromParent_Done, |
| 160348 | // Label 7527: @508632 |
| 160349 | GIM_Reject, |
| 160350 | // Label 7503: @508633 |
| 160351 | GIM_Reject, |
| 160352 | // Label 7305: @508634 |
| 160353 | GIM_Reject, |
| 160354 | // Label 126: @508635 |
| 160355 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 7532*/ GIMT_Encode4(513542), |
| 160356 | /*GILLT_s32*//*Label 7528*/ GIMT_Encode4(508682), GIMT_Encode4(0), GIMT_Encode4(0), |
| 160357 | /*GILLT_v2s32*//*Label 7529*/ GIMT_Encode4(509897), GIMT_Encode4(0), |
| 160358 | /*GILLT_v3s32*//*Label 7530*/ GIMT_Encode4(511112), GIMT_Encode4(0), GIMT_Encode4(0), |
| 160359 | /*GILLT_v4s32*//*Label 7531*/ GIMT_Encode4(512327), |
| 160360 | // Label 7528: @508682 |
| 160361 | GIM_Try, /*On fail goto*//*Label 7533*/ GIMT_Encode4(509896), |
| 160362 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 160363 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 160364 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 160365 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 160366 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 160367 | GIM_Try, /*On fail goto*//*Label 7534*/ GIMT_Encode4(508775), // Rule ID 4359 // |
| 160368 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160369 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160370 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160371 | // MIs[0] offset |
| 160372 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160373 | // MIs[0] auxiliary |
| 160374 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160375 | // MIs[0] Operand 7 |
| 160376 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160377 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160378 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160379 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET), |
| 160380 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160381 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160383 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160384 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160385 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160387 | GIR_RootConstrainSelectedInstOperands, |
| 160388 | // GIR_Coverage, 4359, |
| 160389 | GIR_EraseRootFromParent_Done, |
| 160390 | // Label 7534: @508775 |
| 160391 | GIM_Try, /*On fail goto*//*Label 7535*/ GIMT_Encode4(508844), // Rule ID 4363 // |
| 160392 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160393 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160394 | // MIs[0] offset |
| 160395 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160396 | // MIs[0] auxiliary |
| 160397 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160398 | // MIs[0] Operand 7 |
| 160399 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160400 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160401 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160402 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET), |
| 160403 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160404 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160405 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160406 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160407 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160408 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160409 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160410 | GIR_RootConstrainSelectedInstOperands, |
| 160411 | // GIR_Coverage, 4363, |
| 160412 | GIR_EraseRootFromParent_Done, |
| 160413 | // Label 7535: @508844 |
| 160414 | GIM_Try, /*On fail goto*//*Label 7536*/ GIMT_Encode4(508916), // Rule ID 4367 // |
| 160415 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160416 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160417 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160418 | // MIs[0] offset |
| 160419 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160420 | // MIs[0] auxiliary |
| 160421 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160422 | // MIs[0] Operand 7 |
| 160423 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160424 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160425 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFSET), |
| 160427 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160428 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160430 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160433 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160434 | GIR_RootConstrainSelectedInstOperands, |
| 160435 | // GIR_Coverage, 4367, |
| 160436 | GIR_EraseRootFromParent_Done, |
| 160437 | // Label 7536: @508916 |
| 160438 | GIM_Try, /*On fail goto*//*Label 7537*/ GIMT_Encode4(508985), // Rule ID 4371 // |
| 160439 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160440 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160441 | // MIs[0] offset |
| 160442 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160443 | // MIs[0] auxiliary |
| 160444 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160445 | // MIs[0] Operand 7 |
| 160446 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160448 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160449 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET), |
| 160450 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160451 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160452 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160453 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160454 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160455 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160456 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160457 | GIR_RootConstrainSelectedInstOperands, |
| 160458 | // GIR_Coverage, 4371, |
| 160459 | GIR_EraseRootFromParent_Done, |
| 160460 | // Label 7537: @508985 |
| 160461 | GIM_Try, /*On fail goto*//*Label 7538*/ GIMT_Encode4(509055), // Rule ID 4360 // |
| 160462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160463 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160464 | // MIs[0] offset |
| 160465 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160466 | // MIs[0] auxiliary |
| 160467 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160468 | // MIs[0] Operand 7 |
| 160469 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160470 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160471 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN), |
| 160473 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160474 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160475 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160477 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160478 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160480 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160481 | GIR_RootConstrainSelectedInstOperands, |
| 160482 | // GIR_Coverage, 4360, |
| 160483 | GIR_EraseRootFromParent_Done, |
| 160484 | // Label 7538: @509055 |
| 160485 | GIM_Try, /*On fail goto*//*Label 7539*/ GIMT_Encode4(509122), // Rule ID 4364 // |
| 160486 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160487 | // MIs[0] offset |
| 160488 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160489 | // MIs[0] auxiliary |
| 160490 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160491 | // MIs[0] Operand 7 |
| 160492 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160493 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160494 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160495 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN), |
| 160496 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160497 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160498 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160499 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160500 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160501 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160502 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160503 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160504 | GIR_RootConstrainSelectedInstOperands, |
| 160505 | // GIR_Coverage, 4364, |
| 160506 | GIR_EraseRootFromParent_Done, |
| 160507 | // Label 7539: @509122 |
| 160508 | GIM_Try, /*On fail goto*//*Label 7540*/ GIMT_Encode4(509192), // Rule ID 4368 // |
| 160509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160510 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160511 | // MIs[0] offset |
| 160512 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160513 | // MIs[0] auxiliary |
| 160514 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160515 | // MIs[0] Operand 7 |
| 160516 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160517 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160518 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160519 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_OFFEN), |
| 160520 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160521 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160522 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160523 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160524 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160525 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160526 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160527 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160528 | GIR_RootConstrainSelectedInstOperands, |
| 160529 | // GIR_Coverage, 4368, |
| 160530 | GIR_EraseRootFromParent_Done, |
| 160531 | // Label 7540: @509192 |
| 160532 | GIM_Try, /*On fail goto*//*Label 7541*/ GIMT_Encode4(509259), // Rule ID 4372 // |
| 160533 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160534 | // MIs[0] offset |
| 160535 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160536 | // MIs[0] auxiliary |
| 160537 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160538 | // MIs[0] Operand 7 |
| 160539 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160541 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN), |
| 160543 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160544 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160545 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160547 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160548 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160549 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160550 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160551 | GIR_RootConstrainSelectedInstOperands, |
| 160552 | // GIR_Coverage, 4372, |
| 160553 | GIR_EraseRootFromParent_Done, |
| 160554 | // Label 7541: @509259 |
| 160555 | GIM_Try, /*On fail goto*//*Label 7542*/ GIMT_Encode4(509321), // Rule ID 4361 // |
| 160556 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160557 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160558 | // MIs[0] offset |
| 160559 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160560 | // MIs[0] auxiliary |
| 160561 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160562 | // MIs[0] Operand 7 |
| 160563 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160564 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160565 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160566 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN), |
| 160567 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160568 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160569 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160571 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160573 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160574 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160575 | GIR_RootConstrainSelectedInstOperands, |
| 160576 | // GIR_Coverage, 4361, |
| 160577 | GIR_EraseRootFromParent_Done, |
| 160578 | // Label 7542: @509321 |
| 160579 | GIM_Try, /*On fail goto*//*Label 7543*/ GIMT_Encode4(509380), // Rule ID 4365 // |
| 160580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160581 | // MIs[0] offset |
| 160582 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160583 | // MIs[0] auxiliary |
| 160584 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160585 | // MIs[0] Operand 7 |
| 160586 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160588 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN), |
| 160590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160591 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160592 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160594 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160595 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160596 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160598 | GIR_RootConstrainSelectedInstOperands, |
| 160599 | // GIR_Coverage, 4365, |
| 160600 | GIR_EraseRootFromParent_Done, |
| 160601 | // Label 7543: @509380 |
| 160602 | GIM_Try, /*On fail goto*//*Label 7544*/ GIMT_Encode4(509442), // Rule ID 4369 // |
| 160603 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160604 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160605 | // MIs[0] offset |
| 160606 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160607 | // MIs[0] auxiliary |
| 160608 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160609 | // MIs[0] Operand 7 |
| 160610 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160611 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160612 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_IDXEN), |
| 160614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160615 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160616 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160618 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160619 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160620 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160621 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160622 | GIR_RootConstrainSelectedInstOperands, |
| 160623 | // GIR_Coverage, 4369, |
| 160624 | GIR_EraseRootFromParent_Done, |
| 160625 | // Label 7544: @509442 |
| 160626 | GIM_Try, /*On fail goto*//*Label 7545*/ GIMT_Encode4(509501), // Rule ID 4373 // |
| 160627 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160628 | // MIs[0] offset |
| 160629 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160630 | // MIs[0] auxiliary |
| 160631 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160632 | // MIs[0] Operand 7 |
| 160633 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160635 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160636 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN), |
| 160637 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160638 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160639 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160641 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160642 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160643 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160644 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160645 | GIR_RootConstrainSelectedInstOperands, |
| 160646 | // GIR_Coverage, 4373, |
| 160647 | GIR_EraseRootFromParent_Done, |
| 160648 | // Label 7545: @509501 |
| 160649 | GIM_Try, /*On fail goto*//*Label 7546*/ GIMT_Encode4(509601), // Rule ID 4362 // |
| 160650 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160651 | // MIs[0] offset |
| 160652 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160653 | // MIs[0] auxiliary |
| 160654 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160655 | // MIs[0] Operand 7 |
| 160656 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160657 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160658 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160659 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160660 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160661 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160662 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160663 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160664 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160665 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160667 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160668 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN), |
| 160670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160671 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160672 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160673 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160674 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160675 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160676 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160677 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160678 | GIR_RootConstrainSelectedInstOperands, |
| 160679 | // GIR_Coverage, 4362, |
| 160680 | GIR_EraseRootFromParent_Done, |
| 160681 | // Label 7546: @509601 |
| 160682 | GIM_Try, /*On fail goto*//*Label 7547*/ GIMT_Encode4(509698), // Rule ID 4366 // |
| 160683 | // MIs[0] offset |
| 160684 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160685 | // MIs[0] auxiliary |
| 160686 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160687 | // MIs[0] Operand 7 |
| 160688 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160690 | // (SIbuffer_load_format:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160691 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160692 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160693 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160694 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160695 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160696 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160697 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160698 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160699 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160700 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160701 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN), |
| 160702 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160703 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160704 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160706 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160707 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160708 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160709 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160710 | GIR_RootConstrainSelectedInstOperands, |
| 160711 | // GIR_Coverage, 4366, |
| 160712 | GIR_EraseRootFromParent_Done, |
| 160713 | // Label 7547: @509698 |
| 160714 | GIM_Try, /*On fail goto*//*Label 7548*/ GIMT_Encode4(509798), // Rule ID 4370 // |
| 160715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160716 | // MIs[0] offset |
| 160717 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160718 | // MIs[0] auxiliary |
| 160719 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160720 | // MIs[0] Operand 7 |
| 160721 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160723 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160724 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160725 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160726 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160727 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160728 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160729 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160730 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160731 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160732 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160733 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160734 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_BOTHEN), |
| 160735 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160736 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160737 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160738 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160739 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160741 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160743 | GIR_RootConstrainSelectedInstOperands, |
| 160744 | // GIR_Coverage, 4370, |
| 160745 | GIR_EraseRootFromParent_Done, |
| 160746 | // Label 7548: @509798 |
| 160747 | GIM_Try, /*On fail goto*//*Label 7549*/ GIMT_Encode4(509895), // Rule ID 4374 // |
| 160748 | // MIs[0] offset |
| 160749 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160750 | // MIs[0] auxiliary |
| 160751 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160752 | // MIs[0] Operand 7 |
| 160753 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160755 | // (SIbuffer_load_format:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160756 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 160757 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 160758 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 160759 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 160760 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 160761 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 160762 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 160763 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 160764 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160765 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 160766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN), |
| 160767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160768 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 160769 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160770 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160771 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160772 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160773 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160774 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160775 | GIR_RootConstrainSelectedInstOperands, |
| 160776 | // GIR_Coverage, 4374, |
| 160777 | GIR_EraseRootFromParent_Done, |
| 160778 | // Label 7549: @509895 |
| 160779 | GIM_Reject, |
| 160780 | // Label 7533: @509896 |
| 160781 | GIM_Reject, |
| 160782 | // Label 7529: @509897 |
| 160783 | GIM_Try, /*On fail goto*//*Label 7550*/ GIMT_Encode4(511111), |
| 160784 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 160785 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 160786 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 160787 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 160788 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 160789 | GIM_Try, /*On fail goto*//*Label 7551*/ GIMT_Encode4(509990), // Rule ID 4375 // |
| 160790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160792 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160793 | // MIs[0] offset |
| 160794 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160795 | // MIs[0] auxiliary |
| 160796 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160797 | // MIs[0] Operand 7 |
| 160798 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160800 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET), |
| 160802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160803 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160805 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160806 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160809 | GIR_RootConstrainSelectedInstOperands, |
| 160810 | // GIR_Coverage, 4375, |
| 160811 | GIR_EraseRootFromParent_Done, |
| 160812 | // Label 7551: @509990 |
| 160813 | GIM_Try, /*On fail goto*//*Label 7552*/ GIMT_Encode4(510059), // Rule ID 4379 // |
| 160814 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160815 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160816 | // MIs[0] offset |
| 160817 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160818 | // MIs[0] auxiliary |
| 160819 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160820 | // MIs[0] Operand 7 |
| 160821 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160822 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160823 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET), |
| 160825 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160826 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160828 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160830 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160832 | GIR_RootConstrainSelectedInstOperands, |
| 160833 | // GIR_Coverage, 4379, |
| 160834 | GIR_EraseRootFromParent_Done, |
| 160835 | // Label 7552: @510059 |
| 160836 | GIM_Try, /*On fail goto*//*Label 7553*/ GIMT_Encode4(510131), // Rule ID 4383 // |
| 160837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160838 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160839 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160840 | // MIs[0] offset |
| 160841 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160842 | // MIs[0] auxiliary |
| 160843 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160844 | // MIs[0] Operand 7 |
| 160845 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160847 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFSET), |
| 160849 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160850 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160852 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160853 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160855 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160856 | GIR_RootConstrainSelectedInstOperands, |
| 160857 | // GIR_Coverage, 4383, |
| 160858 | GIR_EraseRootFromParent_Done, |
| 160859 | // Label 7553: @510131 |
| 160860 | GIM_Try, /*On fail goto*//*Label 7554*/ GIMT_Encode4(510200), // Rule ID 4387 // |
| 160861 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160862 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160863 | // MIs[0] offset |
| 160864 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160865 | // MIs[0] auxiliary |
| 160866 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160867 | // MIs[0] Operand 7 |
| 160868 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160870 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET), |
| 160872 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160873 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160875 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160876 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160877 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160878 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160879 | GIR_RootConstrainSelectedInstOperands, |
| 160880 | // GIR_Coverage, 4387, |
| 160881 | GIR_EraseRootFromParent_Done, |
| 160882 | // Label 7554: @510200 |
| 160883 | GIM_Try, /*On fail goto*//*Label 7555*/ GIMT_Encode4(510270), // Rule ID 4376 // |
| 160884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160885 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160886 | // MIs[0] offset |
| 160887 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160888 | // MIs[0] auxiliary |
| 160889 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160890 | // MIs[0] Operand 7 |
| 160891 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160893 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN), |
| 160895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160896 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160897 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160899 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160903 | GIR_RootConstrainSelectedInstOperands, |
| 160904 | // GIR_Coverage, 4376, |
| 160905 | GIR_EraseRootFromParent_Done, |
| 160906 | // Label 7555: @510270 |
| 160907 | GIM_Try, /*On fail goto*//*Label 7556*/ GIMT_Encode4(510337), // Rule ID 4380 // |
| 160908 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160909 | // MIs[0] offset |
| 160910 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160911 | // MIs[0] auxiliary |
| 160912 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160913 | // MIs[0] Operand 7 |
| 160914 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160916 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN), |
| 160918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160919 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160920 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160922 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160923 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160925 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160926 | GIR_RootConstrainSelectedInstOperands, |
| 160927 | // GIR_Coverage, 4380, |
| 160928 | GIR_EraseRootFromParent_Done, |
| 160929 | // Label 7556: @510337 |
| 160930 | GIM_Try, /*On fail goto*//*Label 7557*/ GIMT_Encode4(510407), // Rule ID 4384 // |
| 160931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160932 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160933 | // MIs[0] offset |
| 160934 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160935 | // MIs[0] auxiliary |
| 160936 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160937 | // MIs[0] Operand 7 |
| 160938 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160940 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_OFFEN), |
| 160942 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160943 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160944 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160946 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160947 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160950 | GIR_RootConstrainSelectedInstOperands, |
| 160951 | // GIR_Coverage, 4384, |
| 160952 | GIR_EraseRootFromParent_Done, |
| 160953 | // Label 7557: @510407 |
| 160954 | GIM_Try, /*On fail goto*//*Label 7558*/ GIMT_Encode4(510474), // Rule ID 4388 // |
| 160955 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 160956 | // MIs[0] offset |
| 160957 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160958 | // MIs[0] auxiliary |
| 160959 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160960 | // MIs[0] Operand 7 |
| 160961 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 160962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160963 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN), |
| 160965 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160966 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 160967 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160969 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160970 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160972 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160973 | GIR_RootConstrainSelectedInstOperands, |
| 160974 | // GIR_Coverage, 4388, |
| 160975 | GIR_EraseRootFromParent_Done, |
| 160976 | // Label 7558: @510474 |
| 160977 | GIM_Try, /*On fail goto*//*Label 7559*/ GIMT_Encode4(510536), // Rule ID 4377 // |
| 160978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 160979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 160980 | // MIs[0] offset |
| 160981 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 160982 | // MIs[0] auxiliary |
| 160983 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 160984 | // MIs[0] Operand 7 |
| 160985 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 160986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 160987 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 160988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN), |
| 160989 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 160990 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 160991 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 160992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 160993 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 160994 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 160995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 160996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 160997 | GIR_RootConstrainSelectedInstOperands, |
| 160998 | // GIR_Coverage, 4377, |
| 160999 | GIR_EraseRootFromParent_Done, |
| 161000 | // Label 7559: @510536 |
| 161001 | GIM_Try, /*On fail goto*//*Label 7560*/ GIMT_Encode4(510595), // Rule ID 4381 // |
| 161002 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161003 | // MIs[0] offset |
| 161004 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161005 | // MIs[0] auxiliary |
| 161006 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161007 | // MIs[0] Operand 7 |
| 161008 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161010 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN), |
| 161012 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161013 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161014 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161016 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161017 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161020 | GIR_RootConstrainSelectedInstOperands, |
| 161021 | // GIR_Coverage, 4381, |
| 161022 | GIR_EraseRootFromParent_Done, |
| 161023 | // Label 7560: @510595 |
| 161024 | GIM_Try, /*On fail goto*//*Label 7561*/ GIMT_Encode4(510657), // Rule ID 4385 // |
| 161025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161026 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161027 | // MIs[0] offset |
| 161028 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161029 | // MIs[0] auxiliary |
| 161030 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161031 | // MIs[0] Operand 7 |
| 161032 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161034 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_IDXEN), |
| 161036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161037 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161038 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161040 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161041 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161044 | GIR_RootConstrainSelectedInstOperands, |
| 161045 | // GIR_Coverage, 4385, |
| 161046 | GIR_EraseRootFromParent_Done, |
| 161047 | // Label 7561: @510657 |
| 161048 | GIM_Try, /*On fail goto*//*Label 7562*/ GIMT_Encode4(510716), // Rule ID 4389 // |
| 161049 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161050 | // MIs[0] offset |
| 161051 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161052 | // MIs[0] auxiliary |
| 161053 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161054 | // MIs[0] Operand 7 |
| 161055 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161057 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN), |
| 161059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161060 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161061 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161063 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161066 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161067 | GIR_RootConstrainSelectedInstOperands, |
| 161068 | // GIR_Coverage, 4389, |
| 161069 | GIR_EraseRootFromParent_Done, |
| 161070 | // Label 7562: @510716 |
| 161071 | GIM_Try, /*On fail goto*//*Label 7563*/ GIMT_Encode4(510816), // Rule ID 4378 // |
| 161072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161073 | // MIs[0] offset |
| 161074 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161075 | // MIs[0] auxiliary |
| 161076 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161077 | // MIs[0] Operand 7 |
| 161078 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161079 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161080 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161084 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161085 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161086 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161087 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161088 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161089 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161090 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN), |
| 161092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161094 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161096 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161098 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161099 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161100 | GIR_RootConstrainSelectedInstOperands, |
| 161101 | // GIR_Coverage, 4378, |
| 161102 | GIR_EraseRootFromParent_Done, |
| 161103 | // Label 7563: @510816 |
| 161104 | GIM_Try, /*On fail goto*//*Label 7564*/ GIMT_Encode4(510913), // Rule ID 4382 // |
| 161105 | // MIs[0] offset |
| 161106 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161107 | // MIs[0] auxiliary |
| 161108 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161109 | // MIs[0] Operand 7 |
| 161110 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161112 | // (SIbuffer_load_format:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161116 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161117 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161118 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161119 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161120 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161121 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161122 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN), |
| 161124 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161126 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161128 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161129 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161130 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161132 | GIR_RootConstrainSelectedInstOperands, |
| 161133 | // GIR_Coverage, 4382, |
| 161134 | GIR_EraseRootFromParent_Done, |
| 161135 | // Label 7564: @510913 |
| 161136 | GIM_Try, /*On fail goto*//*Label 7565*/ GIMT_Encode4(511013), // Rule ID 4386 // |
| 161137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161138 | // MIs[0] offset |
| 161139 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161140 | // MIs[0] auxiliary |
| 161141 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161142 | // MIs[0] Operand 7 |
| 161143 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161145 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161146 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161147 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161148 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161149 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161150 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161151 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161152 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161153 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161154 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161155 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_BOTHEN), |
| 161157 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161159 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161161 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161162 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161163 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161165 | GIR_RootConstrainSelectedInstOperands, |
| 161166 | // GIR_Coverage, 4386, |
| 161167 | GIR_EraseRootFromParent_Done, |
| 161168 | // Label 7565: @511013 |
| 161169 | GIM_Try, /*On fail goto*//*Label 7566*/ GIMT_Encode4(511110), // Rule ID 4390 // |
| 161170 | // MIs[0] offset |
| 161171 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161172 | // MIs[0] auxiliary |
| 161173 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161174 | // MIs[0] Operand 7 |
| 161175 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161177 | // (SIbuffer_load_format:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161178 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161179 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161180 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161181 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161182 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161183 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161184 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161185 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161186 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161187 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN), |
| 161189 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161191 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161193 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161194 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161196 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161197 | GIR_RootConstrainSelectedInstOperands, |
| 161198 | // GIR_Coverage, 4390, |
| 161199 | GIR_EraseRootFromParent_Done, |
| 161200 | // Label 7566: @511110 |
| 161201 | GIM_Reject, |
| 161202 | // Label 7550: @511111 |
| 161203 | GIM_Reject, |
| 161204 | // Label 7530: @511112 |
| 161205 | GIM_Try, /*On fail goto*//*Label 7567*/ GIMT_Encode4(512326), |
| 161206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 161207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 161208 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 161209 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 161210 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 161211 | GIM_Try, /*On fail goto*//*Label 7568*/ GIMT_Encode4(511205), // Rule ID 4391 // |
| 161212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161213 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161214 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161215 | // MIs[0] offset |
| 161216 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161217 | // MIs[0] auxiliary |
| 161218 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161219 | // MIs[0] Operand 7 |
| 161220 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161221 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161222 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161223 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET), |
| 161224 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161225 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161226 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161227 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161228 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161229 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161230 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161231 | GIR_RootConstrainSelectedInstOperands, |
| 161232 | // GIR_Coverage, 4391, |
| 161233 | GIR_EraseRootFromParent_Done, |
| 161234 | // Label 7568: @511205 |
| 161235 | GIM_Try, /*On fail goto*//*Label 7569*/ GIMT_Encode4(511274), // Rule ID 4395 // |
| 161236 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161237 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161238 | // MIs[0] offset |
| 161239 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161240 | // MIs[0] auxiliary |
| 161241 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161242 | // MIs[0] Operand 7 |
| 161243 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161245 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET), |
| 161247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161248 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161250 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161252 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161254 | GIR_RootConstrainSelectedInstOperands, |
| 161255 | // GIR_Coverage, 4395, |
| 161256 | GIR_EraseRootFromParent_Done, |
| 161257 | // Label 7569: @511274 |
| 161258 | GIM_Try, /*On fail goto*//*Label 7570*/ GIMT_Encode4(511346), // Rule ID 4399 // |
| 161259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161262 | // MIs[0] offset |
| 161263 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161264 | // MIs[0] auxiliary |
| 161265 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161266 | // MIs[0] Operand 7 |
| 161267 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161269 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFSET), |
| 161271 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161272 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161274 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161278 | GIR_RootConstrainSelectedInstOperands, |
| 161279 | // GIR_Coverage, 4399, |
| 161280 | GIR_EraseRootFromParent_Done, |
| 161281 | // Label 7570: @511346 |
| 161282 | GIM_Try, /*On fail goto*//*Label 7571*/ GIMT_Encode4(511415), // Rule ID 4403 // |
| 161283 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161284 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161285 | // MIs[0] offset |
| 161286 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161287 | // MIs[0] auxiliary |
| 161288 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161289 | // MIs[0] Operand 7 |
| 161290 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161292 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET), |
| 161294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161295 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161297 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161300 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161301 | GIR_RootConstrainSelectedInstOperands, |
| 161302 | // GIR_Coverage, 4403, |
| 161303 | GIR_EraseRootFromParent_Done, |
| 161304 | // Label 7571: @511415 |
| 161305 | GIM_Try, /*On fail goto*//*Label 7572*/ GIMT_Encode4(511485), // Rule ID 4392 // |
| 161306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161307 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161308 | // MIs[0] offset |
| 161309 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161310 | // MIs[0] auxiliary |
| 161311 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161312 | // MIs[0] Operand 7 |
| 161313 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161315 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN), |
| 161317 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161318 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161319 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161321 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161322 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161324 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161325 | GIR_RootConstrainSelectedInstOperands, |
| 161326 | // GIR_Coverage, 4392, |
| 161327 | GIR_EraseRootFromParent_Done, |
| 161328 | // Label 7572: @511485 |
| 161329 | GIM_Try, /*On fail goto*//*Label 7573*/ GIMT_Encode4(511552), // Rule ID 4396 // |
| 161330 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161331 | // MIs[0] offset |
| 161332 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161333 | // MIs[0] auxiliary |
| 161334 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161335 | // MIs[0] Operand 7 |
| 161336 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161338 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN), |
| 161340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161341 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161342 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161344 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161346 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161348 | GIR_RootConstrainSelectedInstOperands, |
| 161349 | // GIR_Coverage, 4396, |
| 161350 | GIR_EraseRootFromParent_Done, |
| 161351 | // Label 7573: @511552 |
| 161352 | GIM_Try, /*On fail goto*//*Label 7574*/ GIMT_Encode4(511622), // Rule ID 4400 // |
| 161353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161354 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161355 | // MIs[0] offset |
| 161356 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161357 | // MIs[0] auxiliary |
| 161358 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161359 | // MIs[0] Operand 7 |
| 161360 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161362 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_OFFEN), |
| 161364 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161365 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161366 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161368 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161370 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161372 | GIR_RootConstrainSelectedInstOperands, |
| 161373 | // GIR_Coverage, 4400, |
| 161374 | GIR_EraseRootFromParent_Done, |
| 161375 | // Label 7574: @511622 |
| 161376 | GIM_Try, /*On fail goto*//*Label 7575*/ GIMT_Encode4(511689), // Rule ID 4404 // |
| 161377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161378 | // MIs[0] offset |
| 161379 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161380 | // MIs[0] auxiliary |
| 161381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161382 | // MIs[0] Operand 7 |
| 161383 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161385 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN), |
| 161387 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161388 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161389 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161391 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161392 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161393 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161395 | GIR_RootConstrainSelectedInstOperands, |
| 161396 | // GIR_Coverage, 4404, |
| 161397 | GIR_EraseRootFromParent_Done, |
| 161398 | // Label 7575: @511689 |
| 161399 | GIM_Try, /*On fail goto*//*Label 7576*/ GIMT_Encode4(511751), // Rule ID 4393 // |
| 161400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161401 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161402 | // MIs[0] offset |
| 161403 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161404 | // MIs[0] auxiliary |
| 161405 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161406 | // MIs[0] Operand 7 |
| 161407 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161409 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN), |
| 161411 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161412 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161413 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161415 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161418 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161419 | GIR_RootConstrainSelectedInstOperands, |
| 161420 | // GIR_Coverage, 4393, |
| 161421 | GIR_EraseRootFromParent_Done, |
| 161422 | // Label 7576: @511751 |
| 161423 | GIM_Try, /*On fail goto*//*Label 7577*/ GIMT_Encode4(511810), // Rule ID 4397 // |
| 161424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161425 | // MIs[0] offset |
| 161426 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161427 | // MIs[0] auxiliary |
| 161428 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161429 | // MIs[0] Operand 7 |
| 161430 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161432 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN), |
| 161434 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161435 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161436 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161438 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161440 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161442 | GIR_RootConstrainSelectedInstOperands, |
| 161443 | // GIR_Coverage, 4397, |
| 161444 | GIR_EraseRootFromParent_Done, |
| 161445 | // Label 7577: @511810 |
| 161446 | GIM_Try, /*On fail goto*//*Label 7578*/ GIMT_Encode4(511872), // Rule ID 4401 // |
| 161447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161449 | // MIs[0] offset |
| 161450 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161451 | // MIs[0] auxiliary |
| 161452 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161453 | // MIs[0] Operand 7 |
| 161454 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161456 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_IDXEN), |
| 161458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161459 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161460 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161462 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161466 | GIR_RootConstrainSelectedInstOperands, |
| 161467 | // GIR_Coverage, 4401, |
| 161468 | GIR_EraseRootFromParent_Done, |
| 161469 | // Label 7578: @511872 |
| 161470 | GIM_Try, /*On fail goto*//*Label 7579*/ GIMT_Encode4(511931), // Rule ID 4405 // |
| 161471 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161472 | // MIs[0] offset |
| 161473 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161474 | // MIs[0] auxiliary |
| 161475 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161476 | // MIs[0] Operand 7 |
| 161477 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161479 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN), |
| 161481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161482 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161483 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161485 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161486 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161487 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161489 | GIR_RootConstrainSelectedInstOperands, |
| 161490 | // GIR_Coverage, 4405, |
| 161491 | GIR_EraseRootFromParent_Done, |
| 161492 | // Label 7579: @511931 |
| 161493 | GIM_Try, /*On fail goto*//*Label 7580*/ GIMT_Encode4(512031), // Rule ID 4394 // |
| 161494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161495 | // MIs[0] offset |
| 161496 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161497 | // MIs[0] auxiliary |
| 161498 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161499 | // MIs[0] Operand 7 |
| 161500 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161501 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161502 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161503 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161504 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161505 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161506 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161507 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161508 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161509 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161510 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161511 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161512 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN), |
| 161514 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161515 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161516 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161518 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161519 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161520 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161522 | GIR_RootConstrainSelectedInstOperands, |
| 161523 | // GIR_Coverage, 4394, |
| 161524 | GIR_EraseRootFromParent_Done, |
| 161525 | // Label 7580: @512031 |
| 161526 | GIM_Try, /*On fail goto*//*Label 7581*/ GIMT_Encode4(512128), // Rule ID 4398 // |
| 161527 | // MIs[0] offset |
| 161528 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161529 | // MIs[0] auxiliary |
| 161530 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161531 | // MIs[0] Operand 7 |
| 161532 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161533 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161534 | // (SIbuffer_load_format:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161535 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161536 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161537 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161538 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161539 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161540 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161541 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161542 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161543 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161544 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161545 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN), |
| 161546 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161547 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161548 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161549 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161550 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161551 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161552 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161553 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161554 | GIR_RootConstrainSelectedInstOperands, |
| 161555 | // GIR_Coverage, 4398, |
| 161556 | GIR_EraseRootFromParent_Done, |
| 161557 | // Label 7581: @512128 |
| 161558 | GIM_Try, /*On fail goto*//*Label 7582*/ GIMT_Encode4(512228), // Rule ID 4402 // |
| 161559 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161560 | // MIs[0] offset |
| 161561 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161562 | // MIs[0] auxiliary |
| 161563 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161564 | // MIs[0] Operand 7 |
| 161565 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161566 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161567 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161568 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161569 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161570 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161571 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161572 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161573 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161574 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161575 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161576 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161577 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161578 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_BOTHEN), |
| 161579 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161580 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161581 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161582 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161583 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161584 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161585 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161586 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161587 | GIR_RootConstrainSelectedInstOperands, |
| 161588 | // GIR_Coverage, 4402, |
| 161589 | GIR_EraseRootFromParent_Done, |
| 161590 | // Label 7582: @512228 |
| 161591 | GIM_Try, /*On fail goto*//*Label 7583*/ GIMT_Encode4(512325), // Rule ID 4406 // |
| 161592 | // MIs[0] offset |
| 161593 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161594 | // MIs[0] auxiliary |
| 161595 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161596 | // MIs[0] Operand 7 |
| 161597 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161599 | // (SIbuffer_load_format:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161600 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161601 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161602 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161603 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161604 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161605 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161606 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161607 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161608 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161609 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN), |
| 161611 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161612 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161613 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161615 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161616 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161618 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161619 | GIR_RootConstrainSelectedInstOperands, |
| 161620 | // GIR_Coverage, 4406, |
| 161621 | GIR_EraseRootFromParent_Done, |
| 161622 | // Label 7583: @512325 |
| 161623 | GIM_Reject, |
| 161624 | // Label 7567: @512326 |
| 161625 | GIM_Reject, |
| 161626 | // Label 7531: @512327 |
| 161627 | GIM_Try, /*On fail goto*//*Label 7584*/ GIMT_Encode4(513541), |
| 161628 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 161629 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 161630 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 161631 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 161632 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 161633 | GIM_Try, /*On fail goto*//*Label 7585*/ GIMT_Encode4(512420), // Rule ID 4407 // |
| 161634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161635 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161636 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161637 | // MIs[0] offset |
| 161638 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161639 | // MIs[0] auxiliary |
| 161640 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161641 | // MIs[0] Operand 7 |
| 161642 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161643 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161644 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161645 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET), |
| 161646 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161647 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161649 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161650 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161651 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161652 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161653 | GIR_RootConstrainSelectedInstOperands, |
| 161654 | // GIR_Coverage, 4407, |
| 161655 | GIR_EraseRootFromParent_Done, |
| 161656 | // Label 7585: @512420 |
| 161657 | GIM_Try, /*On fail goto*//*Label 7586*/ GIMT_Encode4(512489), // Rule ID 4411 // |
| 161658 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161659 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161660 | // MIs[0] offset |
| 161661 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161662 | // MIs[0] auxiliary |
| 161663 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161664 | // MIs[0] Operand 7 |
| 161665 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161667 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET), |
| 161669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161670 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161671 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161672 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161673 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161674 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161675 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161676 | GIR_RootConstrainSelectedInstOperands, |
| 161677 | // GIR_Coverage, 4411, |
| 161678 | GIR_EraseRootFromParent_Done, |
| 161679 | // Label 7586: @512489 |
| 161680 | GIM_Try, /*On fail goto*//*Label 7587*/ GIMT_Encode4(512561), // Rule ID 4415 // |
| 161681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161682 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161683 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161684 | // MIs[0] offset |
| 161685 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161686 | // MIs[0] auxiliary |
| 161687 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161688 | // MIs[0] Operand 7 |
| 161689 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161690 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161691 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161692 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFSET), |
| 161693 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161694 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161696 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161697 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161698 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161699 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161700 | GIR_RootConstrainSelectedInstOperands, |
| 161701 | // GIR_Coverage, 4415, |
| 161702 | GIR_EraseRootFromParent_Done, |
| 161703 | // Label 7587: @512561 |
| 161704 | GIM_Try, /*On fail goto*//*Label 7588*/ GIMT_Encode4(512630), // Rule ID 4419 // |
| 161705 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161706 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161707 | // MIs[0] offset |
| 161708 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161709 | // MIs[0] auxiliary |
| 161710 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161711 | // MIs[0] Operand 7 |
| 161712 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161713 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161714 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161715 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET), |
| 161716 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161717 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161718 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161719 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161720 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161721 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161722 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161723 | GIR_RootConstrainSelectedInstOperands, |
| 161724 | // GIR_Coverage, 4419, |
| 161725 | GIR_EraseRootFromParent_Done, |
| 161726 | // Label 7588: @512630 |
| 161727 | GIM_Try, /*On fail goto*//*Label 7589*/ GIMT_Encode4(512700), // Rule ID 4408 // |
| 161728 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161729 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161730 | // MIs[0] offset |
| 161731 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161732 | // MIs[0] auxiliary |
| 161733 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161734 | // MIs[0] Operand 7 |
| 161735 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161736 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161737 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161738 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN), |
| 161739 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161740 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161741 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161742 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161743 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161744 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161745 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161746 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161747 | GIR_RootConstrainSelectedInstOperands, |
| 161748 | // GIR_Coverage, 4408, |
| 161749 | GIR_EraseRootFromParent_Done, |
| 161750 | // Label 7589: @512700 |
| 161751 | GIM_Try, /*On fail goto*//*Label 7590*/ GIMT_Encode4(512767), // Rule ID 4412 // |
| 161752 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161753 | // MIs[0] offset |
| 161754 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161755 | // MIs[0] auxiliary |
| 161756 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161757 | // MIs[0] Operand 7 |
| 161758 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161759 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161760 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN), |
| 161762 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161763 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161764 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161765 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161766 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161767 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161768 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161769 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161770 | GIR_RootConstrainSelectedInstOperands, |
| 161771 | // GIR_Coverage, 4412, |
| 161772 | GIR_EraseRootFromParent_Done, |
| 161773 | // Label 7590: @512767 |
| 161774 | GIM_Try, /*On fail goto*//*Label 7591*/ GIMT_Encode4(512837), // Rule ID 4416 // |
| 161775 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161776 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161777 | // MIs[0] offset |
| 161778 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161779 | // MIs[0] auxiliary |
| 161780 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161781 | // MIs[0] Operand 7 |
| 161782 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161783 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161784 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161785 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_OFFEN), |
| 161786 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161787 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161788 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161789 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161790 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161791 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161794 | GIR_RootConstrainSelectedInstOperands, |
| 161795 | // GIR_Coverage, 4416, |
| 161796 | GIR_EraseRootFromParent_Done, |
| 161797 | // Label 7591: @512837 |
| 161798 | GIM_Try, /*On fail goto*//*Label 7592*/ GIMT_Encode4(512904), // Rule ID 4420 // |
| 161799 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 161800 | // MIs[0] offset |
| 161801 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161802 | // MIs[0] auxiliary |
| 161803 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161804 | // MIs[0] Operand 7 |
| 161805 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 161806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161807 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN), |
| 161809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161810 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 161811 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161813 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161814 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161815 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161817 | GIR_RootConstrainSelectedInstOperands, |
| 161818 | // GIR_Coverage, 4420, |
| 161819 | GIR_EraseRootFromParent_Done, |
| 161820 | // Label 7592: @512904 |
| 161821 | GIM_Try, /*On fail goto*//*Label 7593*/ GIMT_Encode4(512966), // Rule ID 4409 // |
| 161822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161824 | // MIs[0] offset |
| 161825 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161826 | // MIs[0] auxiliary |
| 161827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161828 | // MIs[0] Operand 7 |
| 161829 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161831 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN), |
| 161833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161834 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161835 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161837 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161839 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161841 | GIR_RootConstrainSelectedInstOperands, |
| 161842 | // GIR_Coverage, 4409, |
| 161843 | GIR_EraseRootFromParent_Done, |
| 161844 | // Label 7593: @512966 |
| 161845 | GIM_Try, /*On fail goto*//*Label 7594*/ GIMT_Encode4(513025), // Rule ID 4413 // |
| 161846 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161847 | // MIs[0] offset |
| 161848 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161849 | // MIs[0] auxiliary |
| 161850 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161851 | // MIs[0] Operand 7 |
| 161852 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161854 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN), |
| 161856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161857 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161858 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161860 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161861 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161864 | GIR_RootConstrainSelectedInstOperands, |
| 161865 | // GIR_Coverage, 4413, |
| 161866 | GIR_EraseRootFromParent_Done, |
| 161867 | // Label 7594: @513025 |
| 161868 | GIM_Try, /*On fail goto*//*Label 7595*/ GIMT_Encode4(513087), // Rule ID 4417 // |
| 161869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161870 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161871 | // MIs[0] offset |
| 161872 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161873 | // MIs[0] auxiliary |
| 161874 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161875 | // MIs[0] Operand 7 |
| 161876 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161877 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161878 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161879 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_IDXEN), |
| 161880 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161881 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161882 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161884 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161885 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161886 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161887 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161888 | GIR_RootConstrainSelectedInstOperands, |
| 161889 | // GIR_Coverage, 4417, |
| 161890 | GIR_EraseRootFromParent_Done, |
| 161891 | // Label 7595: @513087 |
| 161892 | GIM_Try, /*On fail goto*//*Label 7596*/ GIMT_Encode4(513146), // Rule ID 4421 // |
| 161893 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 161894 | // MIs[0] offset |
| 161895 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161896 | // MIs[0] auxiliary |
| 161897 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161898 | // MIs[0] Operand 7 |
| 161899 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161900 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161901 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN), |
| 161903 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161904 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 161905 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161907 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161908 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161909 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161910 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161911 | GIR_RootConstrainSelectedInstOperands, |
| 161912 | // GIR_Coverage, 4421, |
| 161913 | GIR_EraseRootFromParent_Done, |
| 161914 | // Label 7596: @513146 |
| 161915 | GIM_Try, /*On fail goto*//*Label 7597*/ GIMT_Encode4(513246), // Rule ID 4410 // |
| 161916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161917 | // MIs[0] offset |
| 161918 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161919 | // MIs[0] auxiliary |
| 161920 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161921 | // MIs[0] Operand 7 |
| 161922 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161923 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161924 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161925 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161926 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161927 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161928 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161929 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161930 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161931 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161932 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161933 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161934 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN), |
| 161936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161937 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161938 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161940 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161942 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161944 | GIR_RootConstrainSelectedInstOperands, |
| 161945 | // GIR_Coverage, 4410, |
| 161946 | GIR_EraseRootFromParent_Done, |
| 161947 | // Label 7597: @513246 |
| 161948 | GIM_Try, /*On fail goto*//*Label 7598*/ GIMT_Encode4(513343), // Rule ID 4414 // |
| 161949 | // MIs[0] offset |
| 161950 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161951 | // MIs[0] auxiliary |
| 161952 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161953 | // MIs[0] Operand 7 |
| 161954 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161955 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161956 | // (SIbuffer_load_format:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161957 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161958 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161959 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161960 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161961 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161962 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161963 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161964 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161965 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161966 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161967 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN), |
| 161968 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 161969 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 161970 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 161971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 161972 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 161973 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 161974 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 161975 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 161976 | GIR_RootConstrainSelectedInstOperands, |
| 161977 | // GIR_Coverage, 4414, |
| 161978 | GIR_EraseRootFromParent_Done, |
| 161979 | // Label 7598: @513343 |
| 161980 | GIM_Try, /*On fail goto*//*Label 7599*/ GIMT_Encode4(513443), // Rule ID 4418 // |
| 161981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 161982 | // MIs[0] offset |
| 161983 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 161984 | // MIs[0] auxiliary |
| 161985 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 161986 | // MIs[0] Operand 7 |
| 161987 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 161988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 161989 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 161990 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 161991 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 161992 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 161993 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 161994 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 161995 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 161996 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 161997 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 161998 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 161999 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_BOTHEN), |
| 162001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162002 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162003 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162005 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162006 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162007 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162008 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162009 | GIR_RootConstrainSelectedInstOperands, |
| 162010 | // GIR_Coverage, 4418, |
| 162011 | GIR_EraseRootFromParent_Done, |
| 162012 | // Label 7599: @513443 |
| 162013 | GIM_Try, /*On fail goto*//*Label 7600*/ GIMT_Encode4(513540), // Rule ID 4422 // |
| 162014 | // MIs[0] offset |
| 162015 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162016 | // MIs[0] auxiliary |
| 162017 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162018 | // MIs[0] Operand 7 |
| 162019 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162020 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162021 | // (SIbuffer_load_format:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162022 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162023 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162024 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162025 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162026 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162027 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162028 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162029 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162030 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162031 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN), |
| 162033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162034 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162035 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162037 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162038 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162039 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162041 | GIR_RootConstrainSelectedInstOperands, |
| 162042 | // GIR_Coverage, 4422, |
| 162043 | GIR_EraseRootFromParent_Done, |
| 162044 | // Label 7600: @513540 |
| 162045 | GIM_Reject, |
| 162046 | // Label 7584: @513541 |
| 162047 | GIM_Reject, |
| 162048 | // Label 7532: @513542 |
| 162049 | GIM_Reject, |
| 162050 | // Label 127: @513543 |
| 162051 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 7608*/ GIMT_Encode4(521287), |
| 162052 | /*GILLT_s16*//*Label 7601*/ GIMT_Encode4(513594), |
| 162053 | /*GILLT_s32*//*Label 7602*/ GIMT_Encode4(515441), GIMT_Encode4(0), |
| 162054 | /*GILLT_v2s16*//*Label 7603*/ GIMT_Encode4(516376), |
| 162055 | /*GILLT_v2s32*//*Label 7604*/ GIMT_Encode4(517615), GIMT_Encode4(0), |
| 162056 | /*GILLT_v3s32*//*Label 7605*/ GIMT_Encode4(517942), GIMT_Encode4(0), |
| 162057 | /*GILLT_v4s16*//*Label 7606*/ GIMT_Encode4(518269), |
| 162058 | /*GILLT_v4s32*//*Label 7607*/ GIMT_Encode4(520960), |
| 162059 | // Label 7601: @513594 |
| 162060 | GIM_Try, /*On fail goto*//*Label 7609*/ GIMT_Encode4(515440), |
| 162061 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 162062 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 162063 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 162064 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 162065 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 162066 | GIM_Try, /*On fail goto*//*Label 7610*/ GIMT_Encode4(513687), // Rule ID 4455 // |
| 162067 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162068 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162069 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162070 | // MIs[0] offset |
| 162071 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162072 | // MIs[0] auxiliary |
| 162073 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162074 | // MIs[0] Operand 7 |
| 162075 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162077 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET), |
| 162079 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162080 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162082 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162083 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162084 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162085 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162086 | GIR_RootConstrainSelectedInstOperands, |
| 162087 | // GIR_Coverage, 4455, |
| 162088 | GIR_EraseRootFromParent_Done, |
| 162089 | // Label 7610: @513687 |
| 162090 | GIM_Try, /*On fail goto*//*Label 7611*/ GIMT_Encode4(513759), // Rule ID 4459 // |
| 162091 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162092 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162093 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162094 | // MIs[0] offset |
| 162095 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162096 | // MIs[0] auxiliary |
| 162097 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162098 | // MIs[0] Operand 7 |
| 162099 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162101 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET), |
| 162103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162104 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162106 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162107 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162108 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162109 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162110 | GIR_RootConstrainSelectedInstOperands, |
| 162111 | // GIR_Coverage, 4459, |
| 162112 | GIR_EraseRootFromParent_Done, |
| 162113 | // Label 7611: @513759 |
| 162114 | GIM_Try, /*On fail goto*//*Label 7612*/ GIMT_Encode4(513831), // Rule ID 4479 // |
| 162115 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162116 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162118 | // MIs[0] offset |
| 162119 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162120 | // MIs[0] auxiliary |
| 162121 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162122 | // MIs[0] Operand 7 |
| 162123 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162125 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET), |
| 162127 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162128 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162130 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162131 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162132 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162134 | GIR_RootConstrainSelectedInstOperands, |
| 162135 | // GIR_Coverage, 4479, |
| 162136 | GIR_EraseRootFromParent_Done, |
| 162137 | // Label 7612: @513831 |
| 162138 | GIM_Try, /*On fail goto*//*Label 7613*/ GIMT_Encode4(513903), // Rule ID 4483 // |
| 162139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162140 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162142 | // MIs[0] offset |
| 162143 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162144 | // MIs[0] auxiliary |
| 162145 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162146 | // MIs[0] Operand 7 |
| 162147 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162149 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET), |
| 162151 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162152 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162154 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162155 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162158 | GIR_RootConstrainSelectedInstOperands, |
| 162159 | // GIR_Coverage, 4483, |
| 162160 | GIR_EraseRootFromParent_Done, |
| 162161 | // Label 7613: @513903 |
| 162162 | GIM_Try, /*On fail goto*//*Label 7614*/ GIMT_Encode4(513975), // Rule ID 4487 // |
| 162163 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162165 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162166 | // MIs[0] offset |
| 162167 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162168 | // MIs[0] auxiliary |
| 162169 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162170 | // MIs[0] Operand 7 |
| 162171 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162173 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET), |
| 162175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162176 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162178 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162181 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162182 | GIR_RootConstrainSelectedInstOperands, |
| 162183 | // GIR_Coverage, 4487, |
| 162184 | GIR_EraseRootFromParent_Done, |
| 162185 | // Label 7614: @513975 |
| 162186 | GIM_Try, /*On fail goto*//*Label 7615*/ GIMT_Encode4(514047), // Rule ID 4491 // |
| 162187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162188 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162189 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162190 | // MIs[0] offset |
| 162191 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162192 | // MIs[0] auxiliary |
| 162193 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162194 | // MIs[0] Operand 7 |
| 162195 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162197 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162198 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET), |
| 162199 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162200 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162202 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162203 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162204 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162206 | GIR_RootConstrainSelectedInstOperands, |
| 162207 | // GIR_Coverage, 4491, |
| 162208 | GIR_EraseRootFromParent_Done, |
| 162209 | // Label 7615: @514047 |
| 162210 | GIM_Try, /*On fail goto*//*Label 7616*/ GIMT_Encode4(514117), // Rule ID 4456 // |
| 162211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162212 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162213 | // MIs[0] offset |
| 162214 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162215 | // MIs[0] auxiliary |
| 162216 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162217 | // MIs[0] Operand 7 |
| 162218 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162219 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162220 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162221 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN), |
| 162222 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162223 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162224 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162226 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162228 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162230 | GIR_RootConstrainSelectedInstOperands, |
| 162231 | // GIR_Coverage, 4456, |
| 162232 | GIR_EraseRootFromParent_Done, |
| 162233 | // Label 7616: @514117 |
| 162234 | GIM_Try, /*On fail goto*//*Label 7617*/ GIMT_Encode4(514187), // Rule ID 4460 // |
| 162235 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162236 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162237 | // MIs[0] offset |
| 162238 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162239 | // MIs[0] auxiliary |
| 162240 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162241 | // MIs[0] Operand 7 |
| 162242 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162244 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN), |
| 162246 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162247 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162248 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162250 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162252 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162253 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162254 | GIR_RootConstrainSelectedInstOperands, |
| 162255 | // GIR_Coverage, 4460, |
| 162256 | GIR_EraseRootFromParent_Done, |
| 162257 | // Label 7617: @514187 |
| 162258 | GIM_Try, /*On fail goto*//*Label 7618*/ GIMT_Encode4(514257), // Rule ID 4480 // |
| 162259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162261 | // MIs[0] offset |
| 162262 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162263 | // MIs[0] auxiliary |
| 162264 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162265 | // MIs[0] Operand 7 |
| 162266 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162268 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN), |
| 162270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162271 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162272 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162274 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162278 | GIR_RootConstrainSelectedInstOperands, |
| 162279 | // GIR_Coverage, 4480, |
| 162280 | GIR_EraseRootFromParent_Done, |
| 162281 | // Label 7618: @514257 |
| 162282 | GIM_Try, /*On fail goto*//*Label 7619*/ GIMT_Encode4(514327), // Rule ID 4484 // |
| 162283 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162284 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162285 | // MIs[0] offset |
| 162286 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162287 | // MIs[0] auxiliary |
| 162288 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162289 | // MIs[0] Operand 7 |
| 162290 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162292 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN), |
| 162294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162295 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162296 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162298 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162302 | GIR_RootConstrainSelectedInstOperands, |
| 162303 | // GIR_Coverage, 4484, |
| 162304 | GIR_EraseRootFromParent_Done, |
| 162305 | // Label 7619: @514327 |
| 162306 | GIM_Try, /*On fail goto*//*Label 7620*/ GIMT_Encode4(514397), // Rule ID 4488 // |
| 162307 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162308 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162309 | // MIs[0] offset |
| 162310 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162311 | // MIs[0] auxiliary |
| 162312 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162313 | // MIs[0] Operand 7 |
| 162314 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162316 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN), |
| 162318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162319 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162320 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162322 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162324 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162325 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162326 | GIR_RootConstrainSelectedInstOperands, |
| 162327 | // GIR_Coverage, 4488, |
| 162328 | GIR_EraseRootFromParent_Done, |
| 162329 | // Label 7620: @514397 |
| 162330 | GIM_Try, /*On fail goto*//*Label 7621*/ GIMT_Encode4(514467), // Rule ID 4492 // |
| 162331 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162332 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162333 | // MIs[0] offset |
| 162334 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162335 | // MIs[0] auxiliary |
| 162336 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162337 | // MIs[0] Operand 7 |
| 162338 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162340 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN), |
| 162342 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162343 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162344 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162345 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162346 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162348 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162349 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162350 | GIR_RootConstrainSelectedInstOperands, |
| 162351 | // GIR_Coverage, 4492, |
| 162352 | GIR_EraseRootFromParent_Done, |
| 162353 | // Label 7621: @514467 |
| 162354 | GIM_Try, /*On fail goto*//*Label 7622*/ GIMT_Encode4(514529), // Rule ID 4457 // |
| 162355 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162356 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162357 | // MIs[0] offset |
| 162358 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162359 | // MIs[0] auxiliary |
| 162360 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162361 | // MIs[0] Operand 7 |
| 162362 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162364 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN), |
| 162366 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162367 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162368 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162369 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162370 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162371 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162372 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162373 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162374 | GIR_RootConstrainSelectedInstOperands, |
| 162375 | // GIR_Coverage, 4457, |
| 162376 | GIR_EraseRootFromParent_Done, |
| 162377 | // Label 7622: @514529 |
| 162378 | GIM_Try, /*On fail goto*//*Label 7623*/ GIMT_Encode4(514591), // Rule ID 4461 // |
| 162379 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162380 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162381 | // MIs[0] offset |
| 162382 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162383 | // MIs[0] auxiliary |
| 162384 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162385 | // MIs[0] Operand 7 |
| 162386 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162388 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN), |
| 162390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162391 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162392 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162394 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162395 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162396 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162398 | GIR_RootConstrainSelectedInstOperands, |
| 162399 | // GIR_Coverage, 4461, |
| 162400 | GIR_EraseRootFromParent_Done, |
| 162401 | // Label 7623: @514591 |
| 162402 | GIM_Try, /*On fail goto*//*Label 7624*/ GIMT_Encode4(514653), // Rule ID 4481 // |
| 162403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162404 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162405 | // MIs[0] offset |
| 162406 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162407 | // MIs[0] auxiliary |
| 162408 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162409 | // MIs[0] Operand 7 |
| 162410 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162412 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN), |
| 162414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162415 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162416 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162418 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162419 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162420 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162421 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162422 | GIR_RootConstrainSelectedInstOperands, |
| 162423 | // GIR_Coverage, 4481, |
| 162424 | GIR_EraseRootFromParent_Done, |
| 162425 | // Label 7624: @514653 |
| 162426 | GIM_Try, /*On fail goto*//*Label 7625*/ GIMT_Encode4(514715), // Rule ID 4485 // |
| 162427 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162428 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162429 | // MIs[0] offset |
| 162430 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162431 | // MIs[0] auxiliary |
| 162432 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162433 | // MIs[0] Operand 7 |
| 162434 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162435 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162436 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162437 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN), |
| 162438 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162439 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162440 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162441 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162442 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162444 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162445 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162446 | GIR_RootConstrainSelectedInstOperands, |
| 162447 | // GIR_Coverage, 4485, |
| 162448 | GIR_EraseRootFromParent_Done, |
| 162449 | // Label 7625: @514715 |
| 162450 | GIM_Try, /*On fail goto*//*Label 7626*/ GIMT_Encode4(514777), // Rule ID 4489 // |
| 162451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162453 | // MIs[0] offset |
| 162454 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162455 | // MIs[0] auxiliary |
| 162456 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162457 | // MIs[0] Operand 7 |
| 162458 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162459 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162460 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN), |
| 162462 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162463 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162464 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162466 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162469 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162470 | GIR_RootConstrainSelectedInstOperands, |
| 162471 | // GIR_Coverage, 4489, |
| 162472 | GIR_EraseRootFromParent_Done, |
| 162473 | // Label 7626: @514777 |
| 162474 | GIM_Try, /*On fail goto*//*Label 7627*/ GIMT_Encode4(514839), // Rule ID 4493 // |
| 162475 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162476 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162477 | // MIs[0] offset |
| 162478 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162479 | // MIs[0] auxiliary |
| 162480 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162481 | // MIs[0] Operand 7 |
| 162482 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162483 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162484 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162485 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN), |
| 162486 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162487 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162488 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162490 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162491 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162492 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162493 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162494 | GIR_RootConstrainSelectedInstOperands, |
| 162495 | // GIR_Coverage, 4493, |
| 162496 | GIR_EraseRootFromParent_Done, |
| 162497 | // Label 7627: @514839 |
| 162498 | GIM_Try, /*On fail goto*//*Label 7628*/ GIMT_Encode4(514939), // Rule ID 4458 // |
| 162499 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162500 | // MIs[0] offset |
| 162501 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162502 | // MIs[0] auxiliary |
| 162503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162504 | // MIs[0] Operand 7 |
| 162505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162507 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162508 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162509 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162510 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162511 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162512 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162513 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162514 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162515 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162516 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162517 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162518 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN), |
| 162519 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162520 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162521 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162522 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162523 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162524 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162525 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162526 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162527 | GIR_RootConstrainSelectedInstOperands, |
| 162528 | // GIR_Coverage, 4458, |
| 162529 | GIR_EraseRootFromParent_Done, |
| 162530 | // Label 7628: @514939 |
| 162531 | GIM_Try, /*On fail goto*//*Label 7629*/ GIMT_Encode4(515039), // Rule ID 4462 // |
| 162532 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162533 | // MIs[0] offset |
| 162534 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162535 | // MIs[0] auxiliary |
| 162536 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162537 | // MIs[0] Operand 7 |
| 162538 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162540 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162541 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162542 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162543 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162544 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162545 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162546 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162547 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162548 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162549 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162550 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN), |
| 162552 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162553 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162554 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162556 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162557 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162558 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162559 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162560 | GIR_RootConstrainSelectedInstOperands, |
| 162561 | // GIR_Coverage, 4462, |
| 162562 | GIR_EraseRootFromParent_Done, |
| 162563 | // Label 7629: @515039 |
| 162564 | GIM_Try, /*On fail goto*//*Label 7630*/ GIMT_Encode4(515139), // Rule ID 4482 // |
| 162565 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162566 | // MIs[0] offset |
| 162567 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162568 | // MIs[0] auxiliary |
| 162569 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162570 | // MIs[0] Operand 7 |
| 162571 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162572 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162573 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162574 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162575 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162576 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162577 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162578 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162579 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162580 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162582 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162583 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN), |
| 162585 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162586 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162587 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162589 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162591 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162592 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162593 | GIR_RootConstrainSelectedInstOperands, |
| 162594 | // GIR_Coverage, 4482, |
| 162595 | GIR_EraseRootFromParent_Done, |
| 162596 | // Label 7630: @515139 |
| 162597 | GIM_Try, /*On fail goto*//*Label 7631*/ GIMT_Encode4(515239), // Rule ID 4486 // |
| 162598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162599 | // MIs[0] offset |
| 162600 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162601 | // MIs[0] auxiliary |
| 162602 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162603 | // MIs[0] Operand 7 |
| 162604 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162606 | // (SIbuffer_load_format_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162607 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162608 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162609 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162610 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162611 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162612 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162613 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162614 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162616 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162617 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN), |
| 162618 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162619 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162620 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162621 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162622 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162623 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162624 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162625 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162626 | GIR_RootConstrainSelectedInstOperands, |
| 162627 | // GIR_Coverage, 4486, |
| 162628 | GIR_EraseRootFromParent_Done, |
| 162629 | // Label 7631: @515239 |
| 162630 | GIM_Try, /*On fail goto*//*Label 7632*/ GIMT_Encode4(515339), // Rule ID 4490 // |
| 162631 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162632 | // MIs[0] offset |
| 162633 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162634 | // MIs[0] auxiliary |
| 162635 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162636 | // MIs[0] Operand 7 |
| 162637 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162638 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162639 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162640 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162641 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162642 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162643 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162644 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162645 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162646 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162647 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162648 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162649 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN), |
| 162651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162652 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162653 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162655 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162656 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162659 | GIR_RootConstrainSelectedInstOperands, |
| 162660 | // GIR_Coverage, 4490, |
| 162661 | GIR_EraseRootFromParent_Done, |
| 162662 | // Label 7632: @515339 |
| 162663 | GIM_Try, /*On fail goto*//*Label 7633*/ GIMT_Encode4(515439), // Rule ID 4494 // |
| 162664 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162665 | // MIs[0] offset |
| 162666 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162667 | // MIs[0] auxiliary |
| 162668 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162669 | // MIs[0] Operand 7 |
| 162670 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162671 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162672 | // (SIbuffer_load_format_d16:{ *:[i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162673 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162674 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162675 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162676 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162677 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162678 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162679 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162680 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162681 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162682 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162683 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN), |
| 162684 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162685 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162686 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162687 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162688 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162689 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162690 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162691 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162692 | GIR_RootConstrainSelectedInstOperands, |
| 162693 | // GIR_Coverage, 4494, |
| 162694 | GIR_EraseRootFromParent_Done, |
| 162695 | // Label 7633: @515439 |
| 162696 | GIM_Reject, |
| 162697 | // Label 7609: @515440 |
| 162698 | GIM_Reject, |
| 162699 | // Label 7602: @515441 |
| 162700 | GIM_Try, /*On fail goto*//*Label 7634*/ GIMT_Encode4(516375), |
| 162701 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 162702 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 162703 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 162704 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 162705 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 162706 | GIM_Try, /*On fail goto*//*Label 7635*/ GIMT_Encode4(515534), // Rule ID 4463 // |
| 162707 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162708 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162709 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162710 | // MIs[0] offset |
| 162711 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162712 | // MIs[0] auxiliary |
| 162713 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162714 | // MIs[0] Operand 7 |
| 162715 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162716 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162717 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET), |
| 162719 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162720 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162722 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162723 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162726 | GIR_RootConstrainSelectedInstOperands, |
| 162727 | // GIR_Coverage, 4463, |
| 162728 | GIR_EraseRootFromParent_Done, |
| 162729 | // Label 7635: @515534 |
| 162730 | GIM_Try, /*On fail goto*//*Label 7636*/ GIMT_Encode4(515606), // Rule ID 4495 // |
| 162731 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162732 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162733 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162734 | // MIs[0] offset |
| 162735 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162736 | // MIs[0] auxiliary |
| 162737 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162738 | // MIs[0] Operand 7 |
| 162739 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162741 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFSET), |
| 162743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162744 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162746 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162747 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162748 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162749 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162750 | GIR_RootConstrainSelectedInstOperands, |
| 162751 | // GIR_Coverage, 4495, |
| 162752 | GIR_EraseRootFromParent_Done, |
| 162753 | // Label 7636: @515606 |
| 162754 | GIM_Try, /*On fail goto*//*Label 7637*/ GIMT_Encode4(515678), // Rule ID 4499 // |
| 162755 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162756 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162758 | // MIs[0] offset |
| 162759 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162760 | // MIs[0] auxiliary |
| 162761 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162762 | // MIs[0] Operand 7 |
| 162763 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162765 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162766 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET), |
| 162767 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162768 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162769 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162770 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162771 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162772 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162773 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162774 | GIR_RootConstrainSelectedInstOperands, |
| 162775 | // GIR_Coverage, 4499, |
| 162776 | GIR_EraseRootFromParent_Done, |
| 162777 | // Label 7637: @515678 |
| 162778 | GIM_Try, /*On fail goto*//*Label 7638*/ GIMT_Encode4(515748), // Rule ID 4464 // |
| 162779 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162780 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162781 | // MIs[0] offset |
| 162782 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162783 | // MIs[0] auxiliary |
| 162784 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162785 | // MIs[0] Operand 7 |
| 162786 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162787 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162788 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162789 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN), |
| 162790 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162791 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162792 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162793 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162794 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162795 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162796 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162797 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162798 | GIR_RootConstrainSelectedInstOperands, |
| 162799 | // GIR_Coverage, 4464, |
| 162800 | GIR_EraseRootFromParent_Done, |
| 162801 | // Label 7638: @515748 |
| 162802 | GIM_Try, /*On fail goto*//*Label 7639*/ GIMT_Encode4(515818), // Rule ID 4496 // |
| 162803 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162804 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162805 | // MIs[0] offset |
| 162806 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162807 | // MIs[0] auxiliary |
| 162808 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162809 | // MIs[0] Operand 7 |
| 162810 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162812 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_OFFEN), |
| 162814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162815 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162816 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162818 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162819 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162821 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162822 | GIR_RootConstrainSelectedInstOperands, |
| 162823 | // GIR_Coverage, 4496, |
| 162824 | GIR_EraseRootFromParent_Done, |
| 162825 | // Label 7639: @515818 |
| 162826 | GIM_Try, /*On fail goto*//*Label 7640*/ GIMT_Encode4(515888), // Rule ID 4500 // |
| 162827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162828 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 162829 | // MIs[0] offset |
| 162830 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162831 | // MIs[0] auxiliary |
| 162832 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162833 | // MIs[0] Operand 7 |
| 162834 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 162835 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162836 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162837 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN), |
| 162838 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162839 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 162840 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162842 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162843 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162844 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162845 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162846 | GIR_RootConstrainSelectedInstOperands, |
| 162847 | // GIR_Coverage, 4500, |
| 162848 | GIR_EraseRootFromParent_Done, |
| 162849 | // Label 7640: @515888 |
| 162850 | GIM_Try, /*On fail goto*//*Label 7641*/ GIMT_Encode4(515950), // Rule ID 4465 // |
| 162851 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162852 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162853 | // MIs[0] offset |
| 162854 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162855 | // MIs[0] auxiliary |
| 162856 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162857 | // MIs[0] Operand 7 |
| 162858 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162860 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN), |
| 162862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162863 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162864 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162866 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162867 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162868 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162869 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162870 | GIR_RootConstrainSelectedInstOperands, |
| 162871 | // GIR_Coverage, 4465, |
| 162872 | GIR_EraseRootFromParent_Done, |
| 162873 | // Label 7641: @515950 |
| 162874 | GIM_Try, /*On fail goto*//*Label 7642*/ GIMT_Encode4(516012), // Rule ID 4497 // |
| 162875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162876 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162877 | // MIs[0] offset |
| 162878 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162879 | // MIs[0] auxiliary |
| 162880 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162881 | // MIs[0] Operand 7 |
| 162882 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162884 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_IDXEN), |
| 162886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162887 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162888 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162890 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162891 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162892 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162893 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162894 | GIR_RootConstrainSelectedInstOperands, |
| 162895 | // GIR_Coverage, 4497, |
| 162896 | GIR_EraseRootFromParent_Done, |
| 162897 | // Label 7642: @516012 |
| 162898 | GIM_Try, /*On fail goto*//*Label 7643*/ GIMT_Encode4(516074), // Rule ID 4501 // |
| 162899 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162900 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 162901 | // MIs[0] offset |
| 162902 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162903 | // MIs[0] auxiliary |
| 162904 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162905 | // MIs[0] Operand 7 |
| 162906 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162908 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN), |
| 162910 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162911 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 162912 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162914 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162915 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162916 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162918 | GIR_RootConstrainSelectedInstOperands, |
| 162919 | // GIR_Coverage, 4501, |
| 162920 | GIR_EraseRootFromParent_Done, |
| 162921 | // Label 7643: @516074 |
| 162922 | GIM_Try, /*On fail goto*//*Label 7644*/ GIMT_Encode4(516174), // Rule ID 4466 // |
| 162923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 162924 | // MIs[0] offset |
| 162925 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162926 | // MIs[0] auxiliary |
| 162927 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162928 | // MIs[0] Operand 7 |
| 162929 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162931 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162932 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162934 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162935 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162936 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162937 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162938 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162939 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162940 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162941 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN), |
| 162943 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162945 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162947 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162949 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162951 | GIR_RootConstrainSelectedInstOperands, |
| 162952 | // GIR_Coverage, 4466, |
| 162953 | GIR_EraseRootFromParent_Done, |
| 162954 | // Label 7644: @516174 |
| 162955 | GIM_Try, /*On fail goto*//*Label 7645*/ GIMT_Encode4(516274), // Rule ID 4498 // |
| 162956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 162957 | // MIs[0] offset |
| 162958 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162959 | // MIs[0] auxiliary |
| 162960 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162961 | // MIs[0] Operand 7 |
| 162962 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162964 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162965 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162966 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 162967 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 162968 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 162969 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 162970 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 162971 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 162972 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 162973 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162974 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 162975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_BOTHEN), |
| 162976 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 162977 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 162978 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 162979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 162980 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 162981 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 162982 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 162983 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 162984 | GIR_RootConstrainSelectedInstOperands, |
| 162985 | // GIR_Coverage, 4498, |
| 162986 | GIR_EraseRootFromParent_Done, |
| 162987 | // Label 7645: @516274 |
| 162988 | GIM_Try, /*On fail goto*//*Label 7646*/ GIMT_Encode4(516374), // Rule ID 4502 // |
| 162989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 162990 | // MIs[0] offset |
| 162991 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 162992 | // MIs[0] auxiliary |
| 162993 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 162994 | // MIs[0] Operand 7 |
| 162995 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 162996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 162997 | // (SIbuffer_load_format_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 162998 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 162999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163002 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163003 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163004 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163006 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163007 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN), |
| 163009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163011 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163013 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163017 | GIR_RootConstrainSelectedInstOperands, |
| 163018 | // GIR_Coverage, 4502, |
| 163019 | GIR_EraseRootFromParent_Done, |
| 163020 | // Label 7646: @516374 |
| 163021 | GIM_Reject, |
| 163022 | // Label 7634: @516375 |
| 163023 | GIM_Reject, |
| 163024 | // Label 7603: @516376 |
| 163025 | GIM_Try, /*On fail goto*//*Label 7647*/ GIMT_Encode4(517614), |
| 163026 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 163027 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 163028 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 163029 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 163030 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 163031 | GIM_Try, /*On fail goto*//*Label 7648*/ GIMT_Encode4(516469), // Rule ID 4503 // |
| 163032 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163033 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163034 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163035 | // MIs[0] offset |
| 163036 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163037 | // MIs[0] auxiliary |
| 163038 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163039 | // MIs[0] Operand 7 |
| 163040 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163042 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET), |
| 163044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163045 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163047 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163048 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163049 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163050 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163051 | GIR_RootConstrainSelectedInstOperands, |
| 163052 | // GIR_Coverage, 4503, |
| 163053 | GIR_EraseRootFromParent_Done, |
| 163054 | // Label 7648: @516469 |
| 163055 | GIM_Try, /*On fail goto*//*Label 7649*/ GIMT_Encode4(516541), // Rule ID 4507 // |
| 163056 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163057 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163058 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163059 | // MIs[0] offset |
| 163060 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163061 | // MIs[0] auxiliary |
| 163062 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163063 | // MIs[0] Operand 7 |
| 163064 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163065 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163066 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET), |
| 163068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163069 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163071 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163072 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163073 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163074 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163075 | GIR_RootConstrainSelectedInstOperands, |
| 163076 | // GIR_Coverage, 4507, |
| 163077 | GIR_EraseRootFromParent_Done, |
| 163078 | // Label 7649: @516541 |
| 163079 | GIM_Try, /*On fail goto*//*Label 7650*/ GIMT_Encode4(516613), // Rule ID 4511 // |
| 163080 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163081 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163082 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163083 | // MIs[0] offset |
| 163084 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163085 | // MIs[0] auxiliary |
| 163086 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163087 | // MIs[0] Operand 7 |
| 163088 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163089 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163090 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFSET), |
| 163092 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163093 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163094 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163095 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163096 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163098 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163099 | GIR_RootConstrainSelectedInstOperands, |
| 163100 | // GIR_Coverage, 4511, |
| 163101 | GIR_EraseRootFromParent_Done, |
| 163102 | // Label 7650: @516613 |
| 163103 | GIM_Try, /*On fail goto*//*Label 7651*/ GIMT_Encode4(516685), // Rule ID 4515 // |
| 163104 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163105 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163106 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163107 | // MIs[0] offset |
| 163108 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163109 | // MIs[0] auxiliary |
| 163110 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163111 | // MIs[0] Operand 7 |
| 163112 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163114 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET), |
| 163116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163117 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163118 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163119 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163120 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163121 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163123 | GIR_RootConstrainSelectedInstOperands, |
| 163124 | // GIR_Coverage, 4515, |
| 163125 | GIR_EraseRootFromParent_Done, |
| 163126 | // Label 7651: @516685 |
| 163127 | GIM_Try, /*On fail goto*//*Label 7652*/ GIMT_Encode4(516755), // Rule ID 4504 // |
| 163128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163129 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163130 | // MIs[0] offset |
| 163131 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163132 | // MIs[0] auxiliary |
| 163133 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163134 | // MIs[0] Operand 7 |
| 163135 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163136 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163137 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN), |
| 163139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163140 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163141 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163143 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163144 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163145 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163146 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163147 | GIR_RootConstrainSelectedInstOperands, |
| 163148 | // GIR_Coverage, 4504, |
| 163149 | GIR_EraseRootFromParent_Done, |
| 163150 | // Label 7652: @516755 |
| 163151 | GIM_Try, /*On fail goto*//*Label 7653*/ GIMT_Encode4(516825), // Rule ID 4508 // |
| 163152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163153 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163154 | // MIs[0] offset |
| 163155 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163156 | // MIs[0] auxiliary |
| 163157 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163158 | // MIs[0] Operand 7 |
| 163159 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163160 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163161 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN), |
| 163163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163164 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163165 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163167 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163168 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163169 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163170 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163171 | GIR_RootConstrainSelectedInstOperands, |
| 163172 | // GIR_Coverage, 4508, |
| 163173 | GIR_EraseRootFromParent_Done, |
| 163174 | // Label 7653: @516825 |
| 163175 | GIM_Try, /*On fail goto*//*Label 7654*/ GIMT_Encode4(516895), // Rule ID 4512 // |
| 163176 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163177 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163178 | // MIs[0] offset |
| 163179 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163180 | // MIs[0] auxiliary |
| 163181 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163182 | // MIs[0] Operand 7 |
| 163183 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163185 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_OFFEN), |
| 163187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163188 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163189 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163190 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163191 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163192 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163193 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163195 | GIR_RootConstrainSelectedInstOperands, |
| 163196 | // GIR_Coverage, 4512, |
| 163197 | GIR_EraseRootFromParent_Done, |
| 163198 | // Label 7654: @516895 |
| 163199 | GIM_Try, /*On fail goto*//*Label 7655*/ GIMT_Encode4(516965), // Rule ID 4516 // |
| 163200 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163201 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163202 | // MIs[0] offset |
| 163203 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163204 | // MIs[0] auxiliary |
| 163205 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163206 | // MIs[0] Operand 7 |
| 163207 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163208 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163209 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163210 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN), |
| 163211 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163212 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163213 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163214 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163215 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163216 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163217 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163218 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163219 | GIR_RootConstrainSelectedInstOperands, |
| 163220 | // GIR_Coverage, 4516, |
| 163221 | GIR_EraseRootFromParent_Done, |
| 163222 | // Label 7655: @516965 |
| 163223 | GIM_Try, /*On fail goto*//*Label 7656*/ GIMT_Encode4(517027), // Rule ID 4505 // |
| 163224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163225 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163226 | // MIs[0] offset |
| 163227 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163228 | // MIs[0] auxiliary |
| 163229 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163230 | // MIs[0] Operand 7 |
| 163231 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163232 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163233 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163234 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN), |
| 163235 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163236 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163237 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163238 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163239 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163240 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163241 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163242 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163243 | GIR_RootConstrainSelectedInstOperands, |
| 163244 | // GIR_Coverage, 4505, |
| 163245 | GIR_EraseRootFromParent_Done, |
| 163246 | // Label 7656: @517027 |
| 163247 | GIM_Try, /*On fail goto*//*Label 7657*/ GIMT_Encode4(517089), // Rule ID 4509 // |
| 163248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163249 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163250 | // MIs[0] offset |
| 163251 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163252 | // MIs[0] auxiliary |
| 163253 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163254 | // MIs[0] Operand 7 |
| 163255 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163256 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163257 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163258 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN), |
| 163259 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163260 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163261 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163262 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163263 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163264 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163265 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163266 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163267 | GIR_RootConstrainSelectedInstOperands, |
| 163268 | // GIR_Coverage, 4509, |
| 163269 | GIR_EraseRootFromParent_Done, |
| 163270 | // Label 7657: @517089 |
| 163271 | GIM_Try, /*On fail goto*//*Label 7658*/ GIMT_Encode4(517151), // Rule ID 4513 // |
| 163272 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163273 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163274 | // MIs[0] offset |
| 163275 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163276 | // MIs[0] auxiliary |
| 163277 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163278 | // MIs[0] Operand 7 |
| 163279 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163281 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_IDXEN), |
| 163283 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163284 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163285 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163287 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163288 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163289 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163291 | GIR_RootConstrainSelectedInstOperands, |
| 163292 | // GIR_Coverage, 4513, |
| 163293 | GIR_EraseRootFromParent_Done, |
| 163294 | // Label 7658: @517151 |
| 163295 | GIM_Try, /*On fail goto*//*Label 7659*/ GIMT_Encode4(517213), // Rule ID 4517 // |
| 163296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163297 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163298 | // MIs[0] offset |
| 163299 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163300 | // MIs[0] auxiliary |
| 163301 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163302 | // MIs[0] Operand 7 |
| 163303 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163305 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN), |
| 163307 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163308 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163309 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163311 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163312 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163313 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163315 | GIR_RootConstrainSelectedInstOperands, |
| 163316 | // GIR_Coverage, 4517, |
| 163317 | GIR_EraseRootFromParent_Done, |
| 163318 | // Label 7659: @517213 |
| 163319 | GIM_Try, /*On fail goto*//*Label 7660*/ GIMT_Encode4(517313), // Rule ID 4506 // |
| 163320 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163321 | // MIs[0] offset |
| 163322 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163323 | // MIs[0] auxiliary |
| 163324 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163325 | // MIs[0] Operand 7 |
| 163326 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163328 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163329 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163330 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163331 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163332 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163333 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163334 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163335 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163336 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163337 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163338 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN), |
| 163340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163341 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163342 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163344 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163346 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163348 | GIR_RootConstrainSelectedInstOperands, |
| 163349 | // GIR_Coverage, 4506, |
| 163350 | GIR_EraseRootFromParent_Done, |
| 163351 | // Label 7660: @517313 |
| 163352 | GIM_Try, /*On fail goto*//*Label 7661*/ GIMT_Encode4(517413), // Rule ID 4510 // |
| 163353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163354 | // MIs[0] offset |
| 163355 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163356 | // MIs[0] auxiliary |
| 163357 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163358 | // MIs[0] Operand 7 |
| 163359 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163361 | // (SIbuffer_load_format_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163362 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163363 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163364 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163365 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163366 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163367 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163368 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163369 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163370 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163371 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN), |
| 163373 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163374 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163375 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163377 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163378 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163379 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163381 | GIR_RootConstrainSelectedInstOperands, |
| 163382 | // GIR_Coverage, 4510, |
| 163383 | GIR_EraseRootFromParent_Done, |
| 163384 | // Label 7661: @517413 |
| 163385 | GIM_Try, /*On fail goto*//*Label 7662*/ GIMT_Encode4(517513), // Rule ID 4514 // |
| 163386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163387 | // MIs[0] offset |
| 163388 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163389 | // MIs[0] auxiliary |
| 163390 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163391 | // MIs[0] Operand 7 |
| 163392 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163393 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163394 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163395 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163396 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163397 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163398 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163399 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163400 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163401 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163402 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163403 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163404 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163405 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_BOTHEN), |
| 163406 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163407 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163408 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163409 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163410 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163411 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163412 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163414 | GIR_RootConstrainSelectedInstOperands, |
| 163415 | // GIR_Coverage, 4514, |
| 163416 | GIR_EraseRootFromParent_Done, |
| 163417 | // Label 7662: @517513 |
| 163418 | GIM_Try, /*On fail goto*//*Label 7663*/ GIMT_Encode4(517613), // Rule ID 4518 // |
| 163419 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163420 | // MIs[0] offset |
| 163421 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163422 | // MIs[0] auxiliary |
| 163423 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163424 | // MIs[0] Operand 7 |
| 163425 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163426 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163427 | // (SIbuffer_load_format_d16:{ *:[v2i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163428 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163429 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163430 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163431 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163432 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163433 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163434 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163435 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163436 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163437 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163438 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN), |
| 163439 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163440 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163441 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163442 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163443 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163444 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163445 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163446 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163447 | GIR_RootConstrainSelectedInstOperands, |
| 163448 | // GIR_Coverage, 4518, |
| 163449 | GIR_EraseRootFromParent_Done, |
| 163450 | // Label 7663: @517613 |
| 163451 | GIM_Reject, |
| 163452 | // Label 7647: @517614 |
| 163453 | GIM_Reject, |
| 163454 | // Label 7604: @517615 |
| 163455 | GIM_Try, /*On fail goto*//*Label 7664*/ GIMT_Encode4(517941), |
| 163456 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 163457 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 163458 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 163459 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 163460 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163461 | GIM_Try, /*On fail goto*//*Label 7665*/ GIMT_Encode4(517708), // Rule ID 4467 // |
| 163462 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163463 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163464 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163465 | // MIs[0] offset |
| 163466 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163467 | // MIs[0] auxiliary |
| 163468 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163469 | // MIs[0] Operand 7 |
| 163470 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163471 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163472 | // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET), |
| 163474 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163475 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163477 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163478 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163480 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163481 | GIR_RootConstrainSelectedInstOperands, |
| 163482 | // GIR_Coverage, 4467, |
| 163483 | GIR_EraseRootFromParent_Done, |
| 163484 | // Label 7665: @517708 |
| 163485 | GIM_Try, /*On fail goto*//*Label 7666*/ GIMT_Encode4(517778), // Rule ID 4468 // |
| 163486 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163487 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163488 | // MIs[0] offset |
| 163489 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163490 | // MIs[0] auxiliary |
| 163491 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163492 | // MIs[0] Operand 7 |
| 163493 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163495 | // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN), |
| 163497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163498 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163499 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163501 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163502 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163503 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163504 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163505 | GIR_RootConstrainSelectedInstOperands, |
| 163506 | // GIR_Coverage, 4468, |
| 163507 | GIR_EraseRootFromParent_Done, |
| 163508 | // Label 7666: @517778 |
| 163509 | GIM_Try, /*On fail goto*//*Label 7667*/ GIMT_Encode4(517840), // Rule ID 4469 // |
| 163510 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163511 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163512 | // MIs[0] offset |
| 163513 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163514 | // MIs[0] auxiliary |
| 163515 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163516 | // MIs[0] Operand 7 |
| 163517 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163518 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163519 | // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN), |
| 163521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163522 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163523 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163525 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163526 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163527 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163529 | GIR_RootConstrainSelectedInstOperands, |
| 163530 | // GIR_Coverage, 4469, |
| 163531 | GIR_EraseRootFromParent_Done, |
| 163532 | // Label 7667: @517840 |
| 163533 | GIM_Try, /*On fail goto*//*Label 7668*/ GIMT_Encode4(517940), // Rule ID 4470 // |
| 163534 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163535 | // MIs[0] offset |
| 163536 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163537 | // MIs[0] auxiliary |
| 163538 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163539 | // MIs[0] Operand 7 |
| 163540 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163542 | // (SIbuffer_load_format_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163546 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163547 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163548 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163549 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163550 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163551 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163552 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN), |
| 163554 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163556 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163558 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163559 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163560 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163561 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163562 | GIR_RootConstrainSelectedInstOperands, |
| 163563 | // GIR_Coverage, 4470, |
| 163564 | GIR_EraseRootFromParent_Done, |
| 163565 | // Label 7668: @517940 |
| 163566 | GIM_Reject, |
| 163567 | // Label 7664: @517941 |
| 163568 | GIM_Reject, |
| 163569 | // Label 7605: @517942 |
| 163570 | GIM_Try, /*On fail goto*//*Label 7669*/ GIMT_Encode4(518268), |
| 163571 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 163572 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 163573 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 163574 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 163575 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 163576 | GIM_Try, /*On fail goto*//*Label 7670*/ GIMT_Encode4(518035), // Rule ID 4471 // |
| 163577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163578 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163580 | // MIs[0] offset |
| 163581 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163582 | // MIs[0] auxiliary |
| 163583 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163584 | // MIs[0] Operand 7 |
| 163585 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163587 | // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163588 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET), |
| 163589 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163590 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163592 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163596 | GIR_RootConstrainSelectedInstOperands, |
| 163597 | // GIR_Coverage, 4471, |
| 163598 | GIR_EraseRootFromParent_Done, |
| 163599 | // Label 7670: @518035 |
| 163600 | GIM_Try, /*On fail goto*//*Label 7671*/ GIMT_Encode4(518105), // Rule ID 4472 // |
| 163601 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163602 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163603 | // MIs[0] offset |
| 163604 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163605 | // MIs[0] auxiliary |
| 163606 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163607 | // MIs[0] Operand 7 |
| 163608 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163609 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163610 | // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163611 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN), |
| 163612 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163613 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163614 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163616 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163618 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163620 | GIR_RootConstrainSelectedInstOperands, |
| 163621 | // GIR_Coverage, 4472, |
| 163622 | GIR_EraseRootFromParent_Done, |
| 163623 | // Label 7671: @518105 |
| 163624 | GIM_Try, /*On fail goto*//*Label 7672*/ GIMT_Encode4(518167), // Rule ID 4473 // |
| 163625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163626 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163627 | // MIs[0] offset |
| 163628 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163629 | // MIs[0] auxiliary |
| 163630 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163631 | // MIs[0] Operand 7 |
| 163632 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163634 | // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN), |
| 163636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163637 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 163638 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163640 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163641 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163642 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163643 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163644 | GIR_RootConstrainSelectedInstOperands, |
| 163645 | // GIR_Coverage, 4473, |
| 163646 | GIR_EraseRootFromParent_Done, |
| 163647 | // Label 7672: @518167 |
| 163648 | GIM_Try, /*On fail goto*//*Label 7673*/ GIMT_Encode4(518267), // Rule ID 4474 // |
| 163649 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 163650 | // MIs[0] offset |
| 163651 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163652 | // MIs[0] auxiliary |
| 163653 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163654 | // MIs[0] Operand 7 |
| 163655 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 163656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163657 | // (SIbuffer_load_format_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163658 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 163659 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 163660 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 163661 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 163662 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 163663 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 163664 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 163665 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 163666 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163667 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 163668 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN), |
| 163669 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163670 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 163671 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163673 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163674 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163675 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163676 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163677 | GIR_RootConstrainSelectedInstOperands, |
| 163678 | // GIR_Coverage, 4474, |
| 163679 | GIR_EraseRootFromParent_Done, |
| 163680 | // Label 7673: @518267 |
| 163681 | GIM_Reject, |
| 163682 | // Label 7669: @518268 |
| 163683 | GIM_Reject, |
| 163684 | // Label 7606: @518269 |
| 163685 | GIM_Try, /*On fail goto*//*Label 7674*/ GIMT_Encode4(520959), |
| 163686 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 163687 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 163688 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 163689 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 163690 | GIM_Try, /*On fail goto*//*Label 7675*/ GIMT_Encode4(518369), // Rule ID 4519 // |
| 163691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163692 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163693 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163694 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163696 | // MIs[0] offset |
| 163697 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163698 | // MIs[0] auxiliary |
| 163699 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163700 | // MIs[0] Operand 7 |
| 163701 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163703 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET), |
| 163705 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163706 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163707 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163708 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163709 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163710 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163711 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163712 | GIR_RootConstrainSelectedInstOperands, |
| 163713 | // GIR_Coverage, 4519, |
| 163714 | GIR_EraseRootFromParent_Done, |
| 163715 | // Label 7675: @518369 |
| 163716 | GIM_Try, /*On fail goto*//*Label 7676*/ GIMT_Encode4(518452), // Rule ID 4523 // |
| 163717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163718 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163719 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163720 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163721 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163722 | // MIs[0] offset |
| 163723 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163724 | // MIs[0] auxiliary |
| 163725 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163726 | // MIs[0] Operand 7 |
| 163727 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163728 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163729 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET), |
| 163731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163732 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163734 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163735 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163736 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163737 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163738 | GIR_RootConstrainSelectedInstOperands, |
| 163739 | // GIR_Coverage, 4523, |
| 163740 | GIR_EraseRootFromParent_Done, |
| 163741 | // Label 7676: @518452 |
| 163742 | GIM_Try, /*On fail goto*//*Label 7677*/ GIMT_Encode4(518535), // Rule ID 4527 // |
| 163743 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163744 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163746 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163747 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163748 | // MIs[0] offset |
| 163749 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163750 | // MIs[0] auxiliary |
| 163751 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163752 | // MIs[0] Operand 7 |
| 163753 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163754 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163755 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFSET), |
| 163757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163758 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163759 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163760 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163761 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163762 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163763 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163764 | GIR_RootConstrainSelectedInstOperands, |
| 163765 | // GIR_Coverage, 4527, |
| 163766 | GIR_EraseRootFromParent_Done, |
| 163767 | // Label 7677: @518535 |
| 163768 | GIM_Try, /*On fail goto*//*Label 7678*/ GIMT_Encode4(518618), // Rule ID 4531 // |
| 163769 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163770 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163771 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163772 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163773 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163774 | // MIs[0] offset |
| 163775 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163776 | // MIs[0] auxiliary |
| 163777 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163778 | // MIs[0] Operand 7 |
| 163779 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163780 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163781 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163782 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET), |
| 163783 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163784 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163785 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163786 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163787 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163788 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163789 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163790 | GIR_RootConstrainSelectedInstOperands, |
| 163791 | // GIR_Coverage, 4531, |
| 163792 | GIR_EraseRootFromParent_Done, |
| 163793 | // Label 7678: @518618 |
| 163794 | GIM_Try, /*On fail goto*//*Label 7679*/ GIMT_Encode4(518694), // Rule ID 4535 // |
| 163795 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163796 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163797 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163798 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163799 | // MIs[0] offset |
| 163800 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163801 | // MIs[0] auxiliary |
| 163802 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163803 | // MIs[0] Operand 7 |
| 163804 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163805 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163806 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163807 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET), |
| 163808 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163809 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163810 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163811 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163812 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163813 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163814 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163815 | GIR_RootConstrainSelectedInstOperands, |
| 163816 | // GIR_Coverage, 4535, |
| 163817 | GIR_EraseRootFromParent_Done, |
| 163818 | // Label 7679: @518694 |
| 163819 | GIM_Try, /*On fail goto*//*Label 7680*/ GIMT_Encode4(518770), // Rule ID 4539 // |
| 163820 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163821 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163822 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163824 | // MIs[0] offset |
| 163825 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163826 | // MIs[0] auxiliary |
| 163827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163828 | // MIs[0] Operand 7 |
| 163829 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163831 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET), |
| 163833 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163834 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163836 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163837 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163840 | GIR_RootConstrainSelectedInstOperands, |
| 163841 | // GIR_Coverage, 4539, |
| 163842 | GIR_EraseRootFromParent_Done, |
| 163843 | // Label 7680: @518770 |
| 163844 | GIM_Try, /*On fail goto*//*Label 7681*/ GIMT_Encode4(518846), // Rule ID 4543 // |
| 163845 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163846 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163848 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163849 | // MIs[0] offset |
| 163850 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163851 | // MIs[0] auxiliary |
| 163852 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163853 | // MIs[0] Operand 7 |
| 163854 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163855 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163856 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFSET), |
| 163858 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163859 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163861 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163863 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163864 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163865 | GIR_RootConstrainSelectedInstOperands, |
| 163866 | // GIR_Coverage, 4543, |
| 163867 | GIR_EraseRootFromParent_Done, |
| 163868 | // Label 7681: @518846 |
| 163869 | GIM_Try, /*On fail goto*//*Label 7682*/ GIMT_Encode4(518922), // Rule ID 4547 // |
| 163870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163871 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163872 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163873 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 163874 | // MIs[0] offset |
| 163875 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163876 | // MIs[0] auxiliary |
| 163877 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163878 | // MIs[0] Operand 7 |
| 163879 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163881 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4i16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET), |
| 163883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163884 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163886 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163887 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163888 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163889 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163890 | GIR_RootConstrainSelectedInstOperands, |
| 163891 | // GIR_Coverage, 4547, |
| 163892 | GIR_EraseRootFromParent_Done, |
| 163893 | // Label 7682: @518922 |
| 163894 | GIM_Try, /*On fail goto*//*Label 7683*/ GIMT_Encode4(519003), // Rule ID 4520 // |
| 163895 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163896 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163897 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163898 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163899 | // MIs[0] offset |
| 163900 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163901 | // MIs[0] auxiliary |
| 163902 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163903 | // MIs[0] Operand 7 |
| 163904 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163906 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN), |
| 163908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163909 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163910 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163912 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163913 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163914 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163915 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163916 | GIR_RootConstrainSelectedInstOperands, |
| 163917 | // GIR_Coverage, 4520, |
| 163918 | GIR_EraseRootFromParent_Done, |
| 163919 | // Label 7683: @519003 |
| 163920 | GIM_Try, /*On fail goto*//*Label 7684*/ GIMT_Encode4(519084), // Rule ID 4524 // |
| 163921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163922 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163923 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163924 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163925 | // MIs[0] offset |
| 163926 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163927 | // MIs[0] auxiliary |
| 163928 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163929 | // MIs[0] Operand 7 |
| 163930 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163931 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163932 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163933 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN), |
| 163934 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163935 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163936 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163937 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163938 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163939 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163940 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163941 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163942 | GIR_RootConstrainSelectedInstOperands, |
| 163943 | // GIR_Coverage, 4524, |
| 163944 | GIR_EraseRootFromParent_Done, |
| 163945 | // Label 7684: @519084 |
| 163946 | GIM_Try, /*On fail goto*//*Label 7685*/ GIMT_Encode4(519165), // Rule ID 4528 // |
| 163947 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 163948 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163949 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163950 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163951 | // MIs[0] offset |
| 163952 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163953 | // MIs[0] auxiliary |
| 163954 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163955 | // MIs[0] Operand 7 |
| 163956 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163957 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163958 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_OFFEN), |
| 163960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163961 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163962 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163964 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163968 | GIR_RootConstrainSelectedInstOperands, |
| 163969 | // GIR_Coverage, 4528, |
| 163970 | GIR_EraseRootFromParent_Done, |
| 163971 | // Label 7685: @519165 |
| 163972 | GIM_Try, /*On fail goto*//*Label 7686*/ GIMT_Encode4(519246), // Rule ID 4532 // |
| 163973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 163974 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 163975 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 163976 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 163977 | // MIs[0] offset |
| 163978 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 163979 | // MIs[0] auxiliary |
| 163980 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 163981 | // MIs[0] Operand 7 |
| 163982 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 163983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 163984 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 163985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN), |
| 163986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 163987 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 163988 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 163989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 163990 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 163991 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 163992 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 163993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 163994 | GIR_RootConstrainSelectedInstOperands, |
| 163995 | // GIR_Coverage, 4532, |
| 163996 | GIR_EraseRootFromParent_Done, |
| 163997 | // Label 7686: @519246 |
| 163998 | GIM_Try, /*On fail goto*//*Label 7687*/ GIMT_Encode4(519320), // Rule ID 4536 // |
| 163999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164000 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164001 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164002 | // MIs[0] offset |
| 164003 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164004 | // MIs[0] auxiliary |
| 164005 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164006 | // MIs[0] Operand 7 |
| 164007 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164009 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN), |
| 164011 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164012 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164013 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164014 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164015 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164016 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164017 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164018 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164019 | GIR_RootConstrainSelectedInstOperands, |
| 164020 | // GIR_Coverage, 4536, |
| 164021 | GIR_EraseRootFromParent_Done, |
| 164022 | // Label 7687: @519320 |
| 164023 | GIM_Try, /*On fail goto*//*Label 7688*/ GIMT_Encode4(519394), // Rule ID 4540 // |
| 164024 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164025 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164026 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164027 | // MIs[0] offset |
| 164028 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164029 | // MIs[0] auxiliary |
| 164030 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164031 | // MIs[0] Operand 7 |
| 164032 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164034 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN), |
| 164036 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164037 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164038 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164040 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164041 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164044 | GIR_RootConstrainSelectedInstOperands, |
| 164045 | // GIR_Coverage, 4540, |
| 164046 | GIR_EraseRootFromParent_Done, |
| 164047 | // Label 7688: @519394 |
| 164048 | GIM_Try, /*On fail goto*//*Label 7689*/ GIMT_Encode4(519468), // Rule ID 4544 // |
| 164049 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164050 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164051 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164052 | // MIs[0] offset |
| 164053 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164054 | // MIs[0] auxiliary |
| 164055 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164056 | // MIs[0] Operand 7 |
| 164057 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164058 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164059 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_OFFEN), |
| 164061 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164062 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164063 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164065 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164067 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164068 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164069 | GIR_RootConstrainSelectedInstOperands, |
| 164070 | // GIR_Coverage, 4544, |
| 164071 | GIR_EraseRootFromParent_Done, |
| 164072 | // Label 7689: @519468 |
| 164073 | GIM_Try, /*On fail goto*//*Label 7690*/ GIMT_Encode4(519542), // Rule ID 4548 // |
| 164074 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164075 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164076 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164077 | // MIs[0] offset |
| 164078 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164079 | // MIs[0] auxiliary |
| 164080 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164081 | // MIs[0] Operand 7 |
| 164082 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164084 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN), |
| 164086 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164087 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164088 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164090 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164091 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164092 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164094 | GIR_RootConstrainSelectedInstOperands, |
| 164095 | // GIR_Coverage, 4548, |
| 164096 | GIR_EraseRootFromParent_Done, |
| 164097 | // Label 7690: @519542 |
| 164098 | GIM_Try, /*On fail goto*//*Label 7691*/ GIMT_Encode4(519615), // Rule ID 4521 // |
| 164099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164100 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164101 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164102 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164103 | // MIs[0] offset |
| 164104 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164105 | // MIs[0] auxiliary |
| 164106 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164107 | // MIs[0] Operand 7 |
| 164108 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164109 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164110 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164111 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN), |
| 164112 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164113 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164114 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164115 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164116 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164117 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164118 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164119 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164120 | GIR_RootConstrainSelectedInstOperands, |
| 164121 | // GIR_Coverage, 4521, |
| 164122 | GIR_EraseRootFromParent_Done, |
| 164123 | // Label 7691: @519615 |
| 164124 | GIM_Try, /*On fail goto*//*Label 7692*/ GIMT_Encode4(519688), // Rule ID 4525 // |
| 164125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164126 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164127 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164128 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164129 | // MIs[0] offset |
| 164130 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164131 | // MIs[0] auxiliary |
| 164132 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164133 | // MIs[0] Operand 7 |
| 164134 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164135 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164136 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN), |
| 164138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164139 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164140 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164142 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164143 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164144 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164145 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164146 | GIR_RootConstrainSelectedInstOperands, |
| 164147 | // GIR_Coverage, 4525, |
| 164148 | GIR_EraseRootFromParent_Done, |
| 164149 | // Label 7692: @519688 |
| 164150 | GIM_Try, /*On fail goto*//*Label 7693*/ GIMT_Encode4(519761), // Rule ID 4529 // |
| 164151 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164152 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164153 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164154 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164155 | // MIs[0] offset |
| 164156 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164157 | // MIs[0] auxiliary |
| 164158 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164159 | // MIs[0] Operand 7 |
| 164160 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164162 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164163 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_IDXEN), |
| 164164 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164165 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164166 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164167 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164168 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164169 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164170 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164172 | GIR_RootConstrainSelectedInstOperands, |
| 164173 | // GIR_Coverage, 4529, |
| 164174 | GIR_EraseRootFromParent_Done, |
| 164175 | // Label 7693: @519761 |
| 164176 | GIM_Try, /*On fail goto*//*Label 7694*/ GIMT_Encode4(519834), // Rule ID 4533 // |
| 164177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164178 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164179 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164180 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164181 | // MIs[0] offset |
| 164182 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164183 | // MIs[0] auxiliary |
| 164184 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164185 | // MIs[0] Operand 7 |
| 164186 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164188 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN), |
| 164190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164191 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164192 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164194 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164196 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164198 | GIR_RootConstrainSelectedInstOperands, |
| 164199 | // GIR_Coverage, 4533, |
| 164200 | GIR_EraseRootFromParent_Done, |
| 164201 | // Label 7694: @519834 |
| 164202 | GIM_Try, /*On fail goto*//*Label 7695*/ GIMT_Encode4(519900), // Rule ID 4537 // |
| 164203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164204 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164205 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164206 | // MIs[0] offset |
| 164207 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164208 | // MIs[0] auxiliary |
| 164209 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164210 | // MIs[0] Operand 7 |
| 164211 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164212 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164213 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN), |
| 164215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164216 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164217 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164218 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164219 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164220 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164221 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164222 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164223 | GIR_RootConstrainSelectedInstOperands, |
| 164224 | // GIR_Coverage, 4537, |
| 164225 | GIR_EraseRootFromParent_Done, |
| 164226 | // Label 7695: @519900 |
| 164227 | GIM_Try, /*On fail goto*//*Label 7696*/ GIMT_Encode4(519966), // Rule ID 4541 // |
| 164228 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164229 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164230 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164231 | // MIs[0] offset |
| 164232 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164233 | // MIs[0] auxiliary |
| 164234 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164235 | // MIs[0] Operand 7 |
| 164236 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164237 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164238 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN), |
| 164240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164241 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164242 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164243 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164244 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164245 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164248 | GIR_RootConstrainSelectedInstOperands, |
| 164249 | // GIR_Coverage, 4541, |
| 164250 | GIR_EraseRootFromParent_Done, |
| 164251 | // Label 7696: @519966 |
| 164252 | GIM_Try, /*On fail goto*//*Label 7697*/ GIMT_Encode4(520032), // Rule ID 4545 // |
| 164253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164254 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164255 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164256 | // MIs[0] offset |
| 164257 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164258 | // MIs[0] auxiliary |
| 164259 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164260 | // MIs[0] Operand 7 |
| 164261 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164262 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164263 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164264 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_IDXEN), |
| 164265 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164266 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164267 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164269 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164270 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164273 | GIR_RootConstrainSelectedInstOperands, |
| 164274 | // GIR_Coverage, 4545, |
| 164275 | GIR_EraseRootFromParent_Done, |
| 164276 | // Label 7697: @520032 |
| 164277 | GIM_Try, /*On fail goto*//*Label 7698*/ GIMT_Encode4(520098), // Rule ID 4549 // |
| 164278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164279 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164280 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164281 | // MIs[0] offset |
| 164282 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164283 | // MIs[0] auxiliary |
| 164284 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164285 | // MIs[0] Operand 7 |
| 164286 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164288 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4i16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN), |
| 164290 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164291 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164292 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164294 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164295 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164296 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164298 | GIR_RootConstrainSelectedInstOperands, |
| 164299 | // GIR_Coverage, 4549, |
| 164300 | GIR_EraseRootFromParent_Done, |
| 164301 | // Label 7698: @520098 |
| 164302 | GIM_Try, /*On fail goto*//*Label 7699*/ GIMT_Encode4(520209), // Rule ID 4522 // |
| 164303 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164304 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164305 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164306 | // MIs[0] offset |
| 164307 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164308 | // MIs[0] auxiliary |
| 164309 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164310 | // MIs[0] Operand 7 |
| 164311 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164312 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164313 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164314 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164315 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164316 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164317 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164318 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164319 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164320 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164321 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164322 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164323 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164324 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN), |
| 164325 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164326 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164327 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164329 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164330 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164331 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164332 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164333 | GIR_RootConstrainSelectedInstOperands, |
| 164334 | // GIR_Coverage, 4522, |
| 164335 | GIR_EraseRootFromParent_Done, |
| 164336 | // Label 7699: @520209 |
| 164337 | GIM_Try, /*On fail goto*//*Label 7700*/ GIMT_Encode4(520320), // Rule ID 4526 // |
| 164338 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164339 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164340 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164341 | // MIs[0] offset |
| 164342 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164343 | // MIs[0] auxiliary |
| 164344 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164345 | // MIs[0] Operand 7 |
| 164346 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164347 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164348 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32972>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164349 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164350 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164351 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164352 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164353 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164354 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164355 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164356 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164357 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164358 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164359 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN), |
| 164360 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164361 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164362 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164363 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164364 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164365 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164366 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164367 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164368 | GIR_RootConstrainSelectedInstOperands, |
| 164369 | // GIR_Coverage, 4526, |
| 164370 | GIR_EraseRootFromParent_Done, |
| 164371 | // Label 7700: @520320 |
| 164372 | GIM_Try, /*On fail goto*//*Label 7701*/ GIMT_Encode4(520431), // Rule ID 4530 // |
| 164373 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164374 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164375 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164376 | // MIs[0] offset |
| 164377 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164378 | // MIs[0] auxiliary |
| 164379 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164380 | // MIs[0] Operand 7 |
| 164381 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164383 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164387 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164388 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164389 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164390 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164391 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164392 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164393 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN), |
| 164395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164396 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164397 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164399 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164400 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164401 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164402 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164403 | GIR_RootConstrainSelectedInstOperands, |
| 164404 | // GIR_Coverage, 4530, |
| 164405 | GIR_EraseRootFromParent_Done, |
| 164406 | // Label 7701: @520431 |
| 164407 | GIM_Try, /*On fail goto*//*Label 7702*/ GIMT_Encode4(520542), // Rule ID 4534 // |
| 164408 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164409 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 164410 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164411 | // MIs[0] offset |
| 164412 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164413 | // MIs[0] auxiliary |
| 164414 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164415 | // MIs[0] Operand 7 |
| 164416 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164417 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164418 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_32982>> => (BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164419 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164420 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164421 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164422 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164423 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164424 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164425 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164426 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164427 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164428 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164429 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN), |
| 164430 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164431 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164432 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164433 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164434 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164435 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164436 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164437 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164438 | GIR_RootConstrainSelectedInstOperands, |
| 164439 | // GIR_Coverage, 4534, |
| 164440 | GIR_EraseRootFromParent_Done, |
| 164441 | // Label 7702: @520542 |
| 164442 | GIM_Try, /*On fail goto*//*Label 7703*/ GIMT_Encode4(520646), // Rule ID 4538 // |
| 164443 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164444 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164445 | // MIs[0] offset |
| 164446 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164447 | // MIs[0] auxiliary |
| 164448 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164449 | // MIs[0] Operand 7 |
| 164450 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164451 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164452 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164453 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164454 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164455 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164457 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164458 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164459 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164460 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164461 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164462 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN), |
| 164464 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164465 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164466 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164467 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164468 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164469 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164470 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164471 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164472 | GIR_RootConstrainSelectedInstOperands, |
| 164473 | // GIR_Coverage, 4538, |
| 164474 | GIR_EraseRootFromParent_Done, |
| 164475 | // Label 7703: @520646 |
| 164476 | GIM_Try, /*On fail goto*//*Label 7704*/ GIMT_Encode4(520750), // Rule ID 4542 // |
| 164477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164478 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164479 | // MIs[0] offset |
| 164480 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164481 | // MIs[0] auxiliary |
| 164482 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164483 | // MIs[0] Operand 7 |
| 164484 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164486 | // (SIbuffer_load_format_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164487 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164488 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164489 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164490 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164491 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164492 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164493 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164494 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164495 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164496 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164497 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN), |
| 164498 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164499 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164500 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164502 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164503 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164504 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164505 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164506 | GIR_RootConstrainSelectedInstOperands, |
| 164507 | // GIR_Coverage, 4542, |
| 164508 | GIR_EraseRootFromParent_Done, |
| 164509 | // Label 7704: @520750 |
| 164510 | GIM_Try, /*On fail goto*//*Label 7705*/ GIMT_Encode4(520854), // Rule ID 4546 // |
| 164511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 164512 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164513 | // MIs[0] offset |
| 164514 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164515 | // MIs[0] auxiliary |
| 164516 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164517 | // MIs[0] Operand 7 |
| 164518 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164519 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164520 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164521 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164522 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164523 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164524 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164525 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164526 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164527 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164528 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164529 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164530 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164531 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN), |
| 164532 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164533 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164534 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164535 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164536 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164537 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164538 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164539 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164540 | GIR_RootConstrainSelectedInstOperands, |
| 164541 | // GIR_Coverage, 4546, |
| 164542 | GIR_EraseRootFromParent_Done, |
| 164543 | // Label 7705: @520854 |
| 164544 | GIM_Try, /*On fail goto*//*Label 7706*/ GIMT_Encode4(520958), // Rule ID 4550 // |
| 164545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 164546 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164547 | // MIs[0] offset |
| 164548 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164549 | // MIs[0] auxiliary |
| 164550 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164551 | // MIs[0] Operand 7 |
| 164552 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164554 | // (SIbuffer_load_format_d16:{ *:[v4i16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4i16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164557 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164558 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164559 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164560 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164561 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164562 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164563 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164564 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN), |
| 164566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164568 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164570 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164574 | GIR_RootConstrainSelectedInstOperands, |
| 164575 | // GIR_Coverage, 4550, |
| 164576 | GIR_EraseRootFromParent_Done, |
| 164577 | // Label 7706: @520958 |
| 164578 | GIM_Reject, |
| 164579 | // Label 7674: @520959 |
| 164580 | GIM_Reject, |
| 164581 | // Label 7607: @520960 |
| 164582 | GIM_Try, /*On fail goto*//*Label 7707*/ GIMT_Encode4(521286), |
| 164583 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 164584 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 164585 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 164586 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 164587 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 164588 | GIM_Try, /*On fail goto*//*Label 7708*/ GIMT_Encode4(521053), // Rule ID 4475 // |
| 164589 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 164590 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164591 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164592 | // MIs[0] offset |
| 164593 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164594 | // MIs[0] auxiliary |
| 164595 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164596 | // MIs[0] Operand 7 |
| 164597 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164598 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164599 | // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164600 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET), |
| 164601 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164602 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164603 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164604 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164605 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164606 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164608 | GIR_RootConstrainSelectedInstOperands, |
| 164609 | // GIR_Coverage, 4475, |
| 164610 | GIR_EraseRootFromParent_Done, |
| 164611 | // Label 7708: @521053 |
| 164612 | GIM_Try, /*On fail goto*//*Label 7709*/ GIMT_Encode4(521123), // Rule ID 4476 // |
| 164613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 164614 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164615 | // MIs[0] offset |
| 164616 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164617 | // MIs[0] auxiliary |
| 164618 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164619 | // MIs[0] Operand 7 |
| 164620 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164621 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164622 | // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164623 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN), |
| 164624 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164625 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164626 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164628 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164629 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164630 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164631 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164632 | GIR_RootConstrainSelectedInstOperands, |
| 164633 | // GIR_Coverage, 4476, |
| 164634 | GIR_EraseRootFromParent_Done, |
| 164635 | // Label 7709: @521123 |
| 164636 | GIM_Try, /*On fail goto*//*Label 7710*/ GIMT_Encode4(521185), // Rule ID 4477 // |
| 164637 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 164638 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164639 | // MIs[0] offset |
| 164640 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164641 | // MIs[0] auxiliary |
| 164642 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164643 | // MIs[0] Operand 7 |
| 164644 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164645 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164646 | // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164647 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN), |
| 164648 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164649 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164650 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164651 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164652 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164653 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164654 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164655 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164656 | GIR_RootConstrainSelectedInstOperands, |
| 164657 | // GIR_Coverage, 4477, |
| 164658 | GIR_EraseRootFromParent_Done, |
| 164659 | // Label 7710: @521185 |
| 164660 | GIM_Try, /*On fail goto*//*Label 7711*/ GIMT_Encode4(521285), // Rule ID 4478 // |
| 164661 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 164662 | // MIs[0] offset |
| 164663 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164664 | // MIs[0] auxiliary |
| 164665 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164666 | // MIs[0] Operand 7 |
| 164667 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164668 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164669 | // (SIbuffer_load_format_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164670 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164671 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164672 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164673 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164674 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164675 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164676 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164677 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164678 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164679 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN), |
| 164681 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164682 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164683 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164685 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164686 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164687 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164689 | GIR_RootConstrainSelectedInstOperands, |
| 164690 | // GIR_Coverage, 4478, |
| 164691 | GIR_EraseRootFromParent_Done, |
| 164692 | // Label 7711: @521285 |
| 164693 | GIM_Reject, |
| 164694 | // Label 7707: @521286 |
| 164695 | GIM_Reject, |
| 164696 | // Label 7608: @521287 |
| 164697 | GIM_Reject, |
| 164698 | // Label 128: @521288 |
| 164699 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(20), /*)*//*default:*//*Label 7716*/ GIMT_Encode4(523807), |
| 164700 | /*GILLT_v2s32*//*Label 7712*/ GIMT_Encode4(521331), GIMT_Encode4(0), |
| 164701 | /*GILLT_v3s32*//*Label 7713*/ GIMT_Encode4(521950), GIMT_Encode4(0), GIMT_Encode4(0), |
| 164702 | /*GILLT_v4s32*//*Label 7714*/ GIMT_Encode4(522569), GIMT_Encode4(0), |
| 164703 | /*GILLT_v5s32*//*Label 7715*/ GIMT_Encode4(523188), |
| 164704 | // Label 7712: @521331 |
| 164705 | GIM_Try, /*On fail goto*//*Label 7717*/ GIMT_Encode4(521949), |
| 164706 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 164707 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 164708 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 164709 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 164710 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 164711 | GIM_Try, /*On fail goto*//*Label 7718*/ GIMT_Encode4(521424), // Rule ID 4423 // |
| 164712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164713 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164714 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164715 | // MIs[0] offset |
| 164716 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164717 | // MIs[0] auxiliary |
| 164718 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164719 | // MIs[0] Operand 7 |
| 164720 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164721 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164722 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164723 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFSET), |
| 164724 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164725 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164727 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164728 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164729 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164730 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164731 | GIR_RootConstrainSelectedInstOperands, |
| 164732 | // GIR_Coverage, 4423, |
| 164733 | GIR_EraseRootFromParent_Done, |
| 164734 | // Label 7718: @521424 |
| 164735 | GIM_Try, /*On fail goto*//*Label 7719*/ GIMT_Encode4(521493), // Rule ID 4427 // |
| 164736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164737 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164738 | // MIs[0] offset |
| 164739 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164740 | // MIs[0] auxiliary |
| 164741 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164742 | // MIs[0] Operand 7 |
| 164743 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164745 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164746 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFSET), |
| 164747 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164748 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164750 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164751 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164752 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164753 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164754 | GIR_RootConstrainSelectedInstOperands, |
| 164755 | // GIR_Coverage, 4427, |
| 164756 | GIR_EraseRootFromParent_Done, |
| 164757 | // Label 7719: @521493 |
| 164758 | GIM_Try, /*On fail goto*//*Label 7720*/ GIMT_Encode4(521563), // Rule ID 4424 // |
| 164759 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164760 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164761 | // MIs[0] offset |
| 164762 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164763 | // MIs[0] auxiliary |
| 164764 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164765 | // MIs[0] Operand 7 |
| 164766 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164767 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164768 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_OFFEN), |
| 164770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164771 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164772 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164773 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164774 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164775 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164776 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164778 | GIR_RootConstrainSelectedInstOperands, |
| 164779 | // GIR_Coverage, 4424, |
| 164780 | GIR_EraseRootFromParent_Done, |
| 164781 | // Label 7720: @521563 |
| 164782 | GIM_Try, /*On fail goto*//*Label 7721*/ GIMT_Encode4(521630), // Rule ID 4428 // |
| 164783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164784 | // MIs[0] offset |
| 164785 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164786 | // MIs[0] auxiliary |
| 164787 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164788 | // MIs[0] Operand 7 |
| 164789 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164791 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_OFFEN), |
| 164793 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164794 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164795 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164797 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164798 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164799 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164801 | GIR_RootConstrainSelectedInstOperands, |
| 164802 | // GIR_Coverage, 4428, |
| 164803 | GIR_EraseRootFromParent_Done, |
| 164804 | // Label 7721: @521630 |
| 164805 | GIM_Try, /*On fail goto*//*Label 7722*/ GIMT_Encode4(521692), // Rule ID 4425 // |
| 164806 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164807 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164808 | // MIs[0] offset |
| 164809 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164810 | // MIs[0] auxiliary |
| 164811 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164812 | // MIs[0] Operand 7 |
| 164813 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164815 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_IDXEN), |
| 164817 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164818 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164819 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164821 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164822 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164823 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164825 | GIR_RootConstrainSelectedInstOperands, |
| 164826 | // GIR_Coverage, 4425, |
| 164827 | GIR_EraseRootFromParent_Done, |
| 164828 | // Label 7722: @521692 |
| 164829 | GIM_Try, /*On fail goto*//*Label 7723*/ GIMT_Encode4(521751), // Rule ID 4429 // |
| 164830 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164831 | // MIs[0] offset |
| 164832 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164833 | // MIs[0] auxiliary |
| 164834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164835 | // MIs[0] Operand 7 |
| 164836 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164838 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_IDXEN), |
| 164840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164841 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 164842 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164844 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164845 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164846 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164847 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164848 | GIR_RootConstrainSelectedInstOperands, |
| 164849 | // GIR_Coverage, 4429, |
| 164850 | GIR_EraseRootFromParent_Done, |
| 164851 | // Label 7723: @521751 |
| 164852 | GIM_Try, /*On fail goto*//*Label 7724*/ GIMT_Encode4(521851), // Rule ID 4426 // |
| 164853 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164854 | // MIs[0] offset |
| 164855 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164856 | // MIs[0] auxiliary |
| 164857 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164858 | // MIs[0] Operand 7 |
| 164859 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164861 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164862 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164863 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164864 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164865 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164866 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164867 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164868 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164869 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164870 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164871 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_BOTHEN), |
| 164873 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164874 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164875 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164876 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164877 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164878 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164879 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164880 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164881 | GIR_RootConstrainSelectedInstOperands, |
| 164882 | // GIR_Coverage, 4426, |
| 164883 | GIR_EraseRootFromParent_Done, |
| 164884 | // Label 7724: @521851 |
| 164885 | GIM_Try, /*On fail goto*//*Label 7725*/ GIMT_Encode4(521948), // Rule ID 4430 // |
| 164886 | // MIs[0] offset |
| 164887 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164888 | // MIs[0] auxiliary |
| 164889 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164890 | // MIs[0] Operand 7 |
| 164891 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 164892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164893 | // (SIbuffer_load_format_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164894 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 164895 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 164896 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 164897 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 164898 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 164899 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 164900 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 164901 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 164902 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164903 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 164904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_X_TFE_VBUFFER_BOTHEN), |
| 164905 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164906 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 164907 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164909 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164910 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164911 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164912 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164913 | GIR_RootConstrainSelectedInstOperands, |
| 164914 | // GIR_Coverage, 4430, |
| 164915 | GIR_EraseRootFromParent_Done, |
| 164916 | // Label 7725: @521948 |
| 164917 | GIM_Reject, |
| 164918 | // Label 7717: @521949 |
| 164919 | GIM_Reject, |
| 164920 | // Label 7713: @521950 |
| 164921 | GIM_Try, /*On fail goto*//*Label 7726*/ GIMT_Encode4(522568), |
| 164922 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 164923 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 164924 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 164925 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 164926 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 164927 | GIM_Try, /*On fail goto*//*Label 7727*/ GIMT_Encode4(522043), // Rule ID 4431 // |
| 164928 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164929 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164930 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164931 | // MIs[0] offset |
| 164932 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164933 | // MIs[0] auxiliary |
| 164934 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164935 | // MIs[0] Operand 7 |
| 164936 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164937 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164938 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_TFE_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164939 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFSET), |
| 164940 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164941 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164942 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164943 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164944 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164945 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164946 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164947 | GIR_RootConstrainSelectedInstOperands, |
| 164948 | // GIR_Coverage, 4431, |
| 164949 | GIR_EraseRootFromParent_Done, |
| 164950 | // Label 7727: @522043 |
| 164951 | GIM_Try, /*On fail goto*//*Label 7728*/ GIMT_Encode4(522112), // Rule ID 4435 // |
| 164952 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164953 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 164954 | // MIs[0] offset |
| 164955 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164956 | // MIs[0] auxiliary |
| 164957 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164958 | // MIs[0] Operand 7 |
| 164959 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164961 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFSET), |
| 164963 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164964 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164966 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164967 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164969 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164970 | GIR_RootConstrainSelectedInstOperands, |
| 164971 | // GIR_Coverage, 4435, |
| 164972 | GIR_EraseRootFromParent_Done, |
| 164973 | // Label 7728: @522112 |
| 164974 | GIM_Try, /*On fail goto*//*Label 7729*/ GIMT_Encode4(522182), // Rule ID 4432 // |
| 164975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 164976 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 164977 | // MIs[0] offset |
| 164978 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 164979 | // MIs[0] auxiliary |
| 164980 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 164981 | // MIs[0] Operand 7 |
| 164982 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 164983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 164984 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_TFE_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 164985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_OFFEN), |
| 164986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 164987 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 164988 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 164989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 164990 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 164991 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 164992 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 164993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 164994 | GIR_RootConstrainSelectedInstOperands, |
| 164995 | // GIR_Coverage, 4432, |
| 164996 | GIR_EraseRootFromParent_Done, |
| 164997 | // Label 7729: @522182 |
| 164998 | GIM_Try, /*On fail goto*//*Label 7730*/ GIMT_Encode4(522249), // Rule ID 4436 // |
| 164999 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165000 | // MIs[0] offset |
| 165001 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165002 | // MIs[0] auxiliary |
| 165003 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165004 | // MIs[0] Operand 7 |
| 165005 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165007 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_OFFEN), |
| 165009 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165010 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165011 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165013 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165017 | GIR_RootConstrainSelectedInstOperands, |
| 165018 | // GIR_Coverage, 4436, |
| 165019 | GIR_EraseRootFromParent_Done, |
| 165020 | // Label 7730: @522249 |
| 165021 | GIM_Try, /*On fail goto*//*Label 7731*/ GIMT_Encode4(522311), // Rule ID 4433 // |
| 165022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165023 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165024 | // MIs[0] offset |
| 165025 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165026 | // MIs[0] auxiliary |
| 165027 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165028 | // MIs[0] Operand 7 |
| 165029 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165031 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_TFE_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_IDXEN), |
| 165033 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165034 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165035 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165037 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165038 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165039 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165041 | GIR_RootConstrainSelectedInstOperands, |
| 165042 | // GIR_Coverage, 4433, |
| 165043 | GIR_EraseRootFromParent_Done, |
| 165044 | // Label 7731: @522311 |
| 165045 | GIM_Try, /*On fail goto*//*Label 7732*/ GIMT_Encode4(522370), // Rule ID 4437 // |
| 165046 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165047 | // MIs[0] offset |
| 165048 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165049 | // MIs[0] auxiliary |
| 165050 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165051 | // MIs[0] Operand 7 |
| 165052 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165054 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_IDXEN), |
| 165056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165057 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165058 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165060 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165061 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165064 | GIR_RootConstrainSelectedInstOperands, |
| 165065 | // GIR_Coverage, 4437, |
| 165066 | GIR_EraseRootFromParent_Done, |
| 165067 | // Label 7732: @522370 |
| 165068 | GIM_Try, /*On fail goto*//*Label 7733*/ GIMT_Encode4(522470), // Rule ID 4434 // |
| 165069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165070 | // MIs[0] offset |
| 165071 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165072 | // MIs[0] auxiliary |
| 165073 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165074 | // MIs[0] Operand 7 |
| 165075 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165077 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165078 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165079 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165080 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165081 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165082 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165083 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165084 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165085 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165086 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165087 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165088 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_BOTHEN), |
| 165089 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165090 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165091 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165092 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165093 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165094 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165095 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165097 | GIR_RootConstrainSelectedInstOperands, |
| 165098 | // GIR_Coverage, 4434, |
| 165099 | GIR_EraseRootFromParent_Done, |
| 165100 | // Label 7733: @522470 |
| 165101 | GIM_Try, /*On fail goto*//*Label 7734*/ GIMT_Encode4(522567), // Rule ID 4438 // |
| 165102 | // MIs[0] offset |
| 165103 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165104 | // MIs[0] auxiliary |
| 165105 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165106 | // MIs[0] Operand 7 |
| 165107 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165108 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165109 | // (SIbuffer_load_format_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165110 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165111 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165112 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165113 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165114 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165115 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165116 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165117 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165118 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165119 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XY_TFE_VBUFFER_BOTHEN), |
| 165121 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165122 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165123 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165125 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165126 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165127 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165128 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165129 | GIR_RootConstrainSelectedInstOperands, |
| 165130 | // GIR_Coverage, 4438, |
| 165131 | GIR_EraseRootFromParent_Done, |
| 165132 | // Label 7734: @522567 |
| 165133 | GIM_Reject, |
| 165134 | // Label 7726: @522568 |
| 165135 | GIM_Reject, |
| 165136 | // Label 7714: @522569 |
| 165137 | GIM_Try, /*On fail goto*//*Label 7735*/ GIMT_Encode4(523187), |
| 165138 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 165139 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 165140 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 165141 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 165142 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 165143 | GIM_Try, /*On fail goto*//*Label 7736*/ GIMT_Encode4(522662), // Rule ID 4439 // |
| 165144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165145 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165146 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165147 | // MIs[0] offset |
| 165148 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165149 | // MIs[0] auxiliary |
| 165150 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165151 | // MIs[0] Operand 7 |
| 165152 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165153 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165154 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165155 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFSET), |
| 165156 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165157 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165159 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165160 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165161 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165162 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165163 | GIR_RootConstrainSelectedInstOperands, |
| 165164 | // GIR_Coverage, 4439, |
| 165165 | GIR_EraseRootFromParent_Done, |
| 165166 | // Label 7736: @522662 |
| 165167 | GIM_Try, /*On fail goto*//*Label 7737*/ GIMT_Encode4(522731), // Rule ID 4443 // |
| 165168 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165169 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165170 | // MIs[0] offset |
| 165171 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165172 | // MIs[0] auxiliary |
| 165173 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165174 | // MIs[0] Operand 7 |
| 165175 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165177 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165178 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFSET), |
| 165179 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165180 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165182 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165183 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165184 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165185 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165186 | GIR_RootConstrainSelectedInstOperands, |
| 165187 | // GIR_Coverage, 4443, |
| 165188 | GIR_EraseRootFromParent_Done, |
| 165189 | // Label 7737: @522731 |
| 165190 | GIM_Try, /*On fail goto*//*Label 7738*/ GIMT_Encode4(522801), // Rule ID 4440 // |
| 165191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165192 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165193 | // MIs[0] offset |
| 165194 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165195 | // MIs[0] auxiliary |
| 165196 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165197 | // MIs[0] Operand 7 |
| 165198 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165200 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_OFFEN), |
| 165202 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165203 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165204 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165206 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165207 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165208 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165210 | GIR_RootConstrainSelectedInstOperands, |
| 165211 | // GIR_Coverage, 4440, |
| 165212 | GIR_EraseRootFromParent_Done, |
| 165213 | // Label 7738: @522801 |
| 165214 | GIM_Try, /*On fail goto*//*Label 7739*/ GIMT_Encode4(522868), // Rule ID 4444 // |
| 165215 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165216 | // MIs[0] offset |
| 165217 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165218 | // MIs[0] auxiliary |
| 165219 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165220 | // MIs[0] Operand 7 |
| 165221 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165222 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165223 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_OFFEN), |
| 165225 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165226 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165227 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165229 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165230 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165231 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165232 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165233 | GIR_RootConstrainSelectedInstOperands, |
| 165234 | // GIR_Coverage, 4444, |
| 165235 | GIR_EraseRootFromParent_Done, |
| 165236 | // Label 7739: @522868 |
| 165237 | GIM_Try, /*On fail goto*//*Label 7740*/ GIMT_Encode4(522930), // Rule ID 4441 // |
| 165238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165239 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165240 | // MIs[0] offset |
| 165241 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165242 | // MIs[0] auxiliary |
| 165243 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165244 | // MIs[0] Operand 7 |
| 165245 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165246 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165247 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165248 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_IDXEN), |
| 165249 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165250 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165251 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165252 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165253 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165254 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165255 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165256 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165257 | GIR_RootConstrainSelectedInstOperands, |
| 165258 | // GIR_Coverage, 4441, |
| 165259 | GIR_EraseRootFromParent_Done, |
| 165260 | // Label 7740: @522930 |
| 165261 | GIM_Try, /*On fail goto*//*Label 7741*/ GIMT_Encode4(522989), // Rule ID 4445 // |
| 165262 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165263 | // MIs[0] offset |
| 165264 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165265 | // MIs[0] auxiliary |
| 165266 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165267 | // MIs[0] Operand 7 |
| 165268 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165269 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165270 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165271 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_IDXEN), |
| 165272 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165273 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165274 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165276 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165277 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165278 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165279 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165280 | GIR_RootConstrainSelectedInstOperands, |
| 165281 | // GIR_Coverage, 4445, |
| 165282 | GIR_EraseRootFromParent_Done, |
| 165283 | // Label 7741: @522989 |
| 165284 | GIM_Try, /*On fail goto*//*Label 7742*/ GIMT_Encode4(523089), // Rule ID 4442 // |
| 165285 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165286 | // MIs[0] offset |
| 165287 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165288 | // MIs[0] auxiliary |
| 165289 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165290 | // MIs[0] Operand 7 |
| 165291 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165292 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165293 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165294 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165295 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165296 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165297 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165298 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165299 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165300 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165301 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165302 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165303 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165304 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_BOTHEN), |
| 165305 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165306 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165307 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165308 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165309 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165310 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165311 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165313 | GIR_RootConstrainSelectedInstOperands, |
| 165314 | // GIR_Coverage, 4442, |
| 165315 | GIR_EraseRootFromParent_Done, |
| 165316 | // Label 7742: @523089 |
| 165317 | GIM_Try, /*On fail goto*//*Label 7743*/ GIMT_Encode4(523186), // Rule ID 4446 // |
| 165318 | // MIs[0] offset |
| 165319 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165320 | // MIs[0] auxiliary |
| 165321 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165322 | // MIs[0] Operand 7 |
| 165323 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165324 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165325 | // (SIbuffer_load_format_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165326 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165327 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165328 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165329 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165330 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165331 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165332 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165333 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165334 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165335 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165336 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZ_TFE_VBUFFER_BOTHEN), |
| 165337 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165338 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165339 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165340 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165341 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165342 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165343 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165345 | GIR_RootConstrainSelectedInstOperands, |
| 165346 | // GIR_Coverage, 4446, |
| 165347 | GIR_EraseRootFromParent_Done, |
| 165348 | // Label 7743: @523186 |
| 165349 | GIM_Reject, |
| 165350 | // Label 7735: @523187 |
| 165351 | GIM_Reject, |
| 165352 | // Label 7715: @523188 |
| 165353 | GIM_Try, /*On fail goto*//*Label 7744*/ GIMT_Encode4(523806), |
| 165354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 165355 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 165356 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 165357 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 165358 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_160RegClassID), |
| 165359 | GIM_Try, /*On fail goto*//*Label 7745*/ GIMT_Encode4(523281), // Rule ID 4447 // |
| 165360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165362 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165363 | // MIs[0] offset |
| 165364 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165365 | // MIs[0] auxiliary |
| 165366 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165367 | // MIs[0] Operand 7 |
| 165368 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165369 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165370 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165371 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFSET), |
| 165372 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165373 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165375 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165377 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165378 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165379 | GIR_RootConstrainSelectedInstOperands, |
| 165380 | // GIR_Coverage, 4447, |
| 165381 | GIR_EraseRootFromParent_Done, |
| 165382 | // Label 7745: @523281 |
| 165383 | GIM_Try, /*On fail goto*//*Label 7746*/ GIMT_Encode4(523350), // Rule ID 4451 // |
| 165384 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165385 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165386 | // MIs[0] offset |
| 165387 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165388 | // MIs[0] auxiliary |
| 165389 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165390 | // MIs[0] Operand 7 |
| 165391 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165392 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165393 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFSET), |
| 165395 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165396 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165398 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165400 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165402 | GIR_RootConstrainSelectedInstOperands, |
| 165403 | // GIR_Coverage, 4451, |
| 165404 | GIR_EraseRootFromParent_Done, |
| 165405 | // Label 7746: @523350 |
| 165406 | GIM_Try, /*On fail goto*//*Label 7747*/ GIMT_Encode4(523420), // Rule ID 4448 // |
| 165407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165408 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165409 | // MIs[0] offset |
| 165410 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165411 | // MIs[0] auxiliary |
| 165412 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165413 | // MIs[0] Operand 7 |
| 165414 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165416 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_OFFEN), |
| 165418 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165419 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165420 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165422 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165423 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165424 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165426 | GIR_RootConstrainSelectedInstOperands, |
| 165427 | // GIR_Coverage, 4448, |
| 165428 | GIR_EraseRootFromParent_Done, |
| 165429 | // Label 7747: @523420 |
| 165430 | GIM_Try, /*On fail goto*//*Label 7748*/ GIMT_Encode4(523487), // Rule ID 4452 // |
| 165431 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165432 | // MIs[0] offset |
| 165433 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165434 | // MIs[0] auxiliary |
| 165435 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165436 | // MIs[0] Operand 7 |
| 165437 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165438 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165439 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_OFFEN), |
| 165441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165442 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165443 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165445 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165446 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165447 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165449 | GIR_RootConstrainSelectedInstOperands, |
| 165450 | // GIR_Coverage, 4452, |
| 165451 | GIR_EraseRootFromParent_Done, |
| 165452 | // Label 7748: @523487 |
| 165453 | GIM_Try, /*On fail goto*//*Label 7749*/ GIMT_Encode4(523549), // Rule ID 4449 // |
| 165454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165455 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165456 | // MIs[0] offset |
| 165457 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165458 | // MIs[0] auxiliary |
| 165459 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165460 | // MIs[0] Operand 7 |
| 165461 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165462 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165463 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165464 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_IDXEN), |
| 165465 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165466 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165467 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165468 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165469 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165470 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165471 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165472 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165473 | GIR_RootConstrainSelectedInstOperands, |
| 165474 | // GIR_Coverage, 4449, |
| 165475 | GIR_EraseRootFromParent_Done, |
| 165476 | // Label 7749: @523549 |
| 165477 | GIM_Try, /*On fail goto*//*Label 7750*/ GIMT_Encode4(523608), // Rule ID 4453 // |
| 165478 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165479 | // MIs[0] offset |
| 165480 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165481 | // MIs[0] auxiliary |
| 165482 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165483 | // MIs[0] Operand 7 |
| 165484 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165485 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165486 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165487 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_IDXEN), |
| 165488 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165489 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165490 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165491 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165492 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165493 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165494 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165495 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165496 | GIR_RootConstrainSelectedInstOperands, |
| 165497 | // GIR_Coverage, 4453, |
| 165498 | GIR_EraseRootFromParent_Done, |
| 165499 | // Label 7750: @523608 |
| 165500 | GIM_Try, /*On fail goto*//*Label 7751*/ GIMT_Encode4(523708), // Rule ID 4450 // |
| 165501 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165502 | // MIs[0] offset |
| 165503 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165504 | // MIs[0] auxiliary |
| 165505 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165506 | // MIs[0] Operand 7 |
| 165507 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165509 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165510 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165511 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165512 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165513 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165514 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165515 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165516 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165517 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165518 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165519 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165520 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_BOTHEN), |
| 165521 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165522 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165523 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165524 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165525 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165526 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165527 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165528 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165529 | GIR_RootConstrainSelectedInstOperands, |
| 165530 | // GIR_Coverage, 4450, |
| 165531 | GIR_EraseRootFromParent_Done, |
| 165532 | // Label 7751: @523708 |
| 165533 | GIM_Try, /*On fail goto*//*Label 7752*/ GIMT_Encode4(523805), // Rule ID 4454 // |
| 165534 | // MIs[0] offset |
| 165535 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165536 | // MIs[0] auxiliary |
| 165537 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165538 | // MIs[0] Operand 7 |
| 165539 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165541 | // (SIbuffer_load_format_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165542 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165543 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165544 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165545 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165546 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165547 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165548 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165549 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165550 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165551 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165552 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_FORMAT_XYZW_TFE_VBUFFER_BOTHEN), |
| 165553 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165554 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165555 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165556 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165557 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165558 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165559 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165560 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165561 | GIR_RootConstrainSelectedInstOperands, |
| 165562 | // GIR_Coverage, 4454, |
| 165563 | GIR_EraseRootFromParent_Done, |
| 165564 | // Label 7752: @523805 |
| 165565 | GIM_Reject, |
| 165566 | // Label 7744: @523806 |
| 165567 | GIM_Reject, |
| 165568 | // Label 7716: @523807 |
| 165569 | GIM_Reject, |
| 165570 | // Label 129: @523808 |
| 165571 | GIM_Try, /*On fail goto*//*Label 7753*/ GIMT_Encode4(524413), |
| 165572 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 165573 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 165574 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 165575 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 165576 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 165577 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 165578 | GIM_Try, /*On fail goto*//*Label 7754*/ GIMT_Encode4(524104), |
| 165579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165580 | GIM_Try, /*On fail goto*//*Label 7755*/ GIMT_Encode4(523909), // Rule ID 4759 // |
| 165581 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165583 | // MIs[0] offset |
| 165584 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165585 | // MIs[0] auxiliary |
| 165586 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165587 | // MIs[0] Operand 7 |
| 165588 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165590 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFSET), |
| 165592 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165593 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165595 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165596 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165597 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165598 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165599 | GIR_RootConstrainSelectedInstOperands, |
| 165600 | // GIR_Coverage, 4759, |
| 165601 | GIR_EraseRootFromParent_Done, |
| 165602 | // Label 7755: @523909 |
| 165603 | GIM_Try, /*On fail goto*//*Label 7756*/ GIMT_Encode4(523974), // Rule ID 4763 // |
| 165604 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165605 | // MIs[0] offset |
| 165606 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165607 | // MIs[0] auxiliary |
| 165608 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165609 | // MIs[0] Operand 7 |
| 165610 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165611 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165612 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165613 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFSET), |
| 165614 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165615 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165617 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165618 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165619 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165620 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165621 | GIR_RootConstrainSelectedInstOperands, |
| 165622 | // GIR_Coverage, 4763, |
| 165623 | GIR_EraseRootFromParent_Done, |
| 165624 | // Label 7756: @523974 |
| 165625 | GIM_Try, /*On fail goto*//*Label 7757*/ GIMT_Encode4(524040), // Rule ID 4760 // |
| 165626 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165627 | // MIs[0] offset |
| 165628 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165629 | // MIs[0] auxiliary |
| 165630 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165631 | // MIs[0] Operand 7 |
| 165632 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165634 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_OFFEN), |
| 165636 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165637 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165638 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165640 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165641 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165642 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165643 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165644 | GIR_RootConstrainSelectedInstOperands, |
| 165645 | // GIR_Coverage, 4760, |
| 165646 | GIR_EraseRootFromParent_Done, |
| 165647 | // Label 7757: @524040 |
| 165648 | GIM_Try, /*On fail goto*//*Label 7758*/ GIMT_Encode4(524103), // Rule ID 4764 // |
| 165649 | // MIs[0] offset |
| 165650 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165651 | // MIs[0] auxiliary |
| 165652 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165653 | // MIs[0] Operand 7 |
| 165654 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165656 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_OFFEN), |
| 165658 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165659 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165660 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165662 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165663 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165664 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165666 | GIR_RootConstrainSelectedInstOperands, |
| 165667 | // GIR_Coverage, 4764, |
| 165668 | GIR_EraseRootFromParent_Done, |
| 165669 | // Label 7758: @524103 |
| 165670 | GIM_Reject, |
| 165671 | // Label 7754: @524104 |
| 165672 | GIM_Try, /*On fail goto*//*Label 7759*/ GIMT_Encode4(524218), |
| 165673 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165674 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165675 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165676 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165677 | GIM_Try, /*On fail goto*//*Label 7760*/ GIMT_Encode4(524171), // Rule ID 4761 // |
| 165678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165680 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_IDXEN), |
| 165682 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165683 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165684 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165686 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165687 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165688 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165690 | GIR_RootConstrainSelectedInstOperands, |
| 165691 | // GIR_Coverage, 4761, |
| 165692 | GIR_EraseRootFromParent_Done, |
| 165693 | // Label 7760: @524171 |
| 165694 | GIM_Try, /*On fail goto*//*Label 7761*/ GIMT_Encode4(524217), // Rule ID 4765 // |
| 165695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165696 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_IDXEN), |
| 165698 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165699 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165700 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165702 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165704 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165706 | GIR_RootConstrainSelectedInstOperands, |
| 165707 | // GIR_Coverage, 4765, |
| 165708 | GIR_EraseRootFromParent_Done, |
| 165709 | // Label 7761: @524217 |
| 165710 | GIM_Reject, |
| 165711 | // Label 7759: @524218 |
| 165712 | GIM_Try, /*On fail goto*//*Label 7762*/ GIMT_Encode4(524412), |
| 165713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165714 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165715 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165716 | GIM_Try, /*On fail goto*//*Label 7763*/ GIMT_Encode4(524323), // Rule ID 4762 // |
| 165717 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165719 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165720 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165721 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165722 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165723 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165724 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165725 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165726 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165727 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165728 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165729 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165730 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_BOTHEN), |
| 165731 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165732 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165733 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165734 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165735 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165736 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165737 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165738 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165739 | GIR_RootConstrainSelectedInstOperands, |
| 165740 | // GIR_Coverage, 4762, |
| 165741 | GIR_EraseRootFromParent_Done, |
| 165742 | // Label 7763: @524323 |
| 165743 | GIM_Try, /*On fail goto*//*Label 7764*/ GIMT_Encode4(524411), // Rule ID 4766 // |
| 165744 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165745 | // (SIbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165746 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165747 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165748 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165749 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165750 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165751 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165752 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165753 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165754 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165755 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165756 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_VBUFFER_BOTHEN), |
| 165757 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165758 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165759 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165760 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165761 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165762 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165763 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165764 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165765 | GIR_RootConstrainSelectedInstOperands, |
| 165766 | // GIR_Coverage, 4766, |
| 165767 | GIR_EraseRootFromParent_Done, |
| 165768 | // Label 7764: @524411 |
| 165769 | GIM_Reject, |
| 165770 | // Label 7762: @524412 |
| 165771 | GIM_Reject, |
| 165772 | // Label 7753: @524413 |
| 165773 | GIM_Reject, |
| 165774 | // Label 130: @524414 |
| 165775 | GIM_Try, /*On fail goto*//*Label 7765*/ GIMT_Encode4(525019), |
| 165776 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 165777 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 165778 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 165779 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 165780 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 165781 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 165782 | GIM_Try, /*On fail goto*//*Label 7766*/ GIMT_Encode4(524710), |
| 165783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165784 | GIM_Try, /*On fail goto*//*Label 7767*/ GIMT_Encode4(524515), // Rule ID 4823 // |
| 165785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165786 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165787 | // MIs[0] offset |
| 165788 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165789 | // MIs[0] auxiliary |
| 165790 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165791 | // MIs[0] Operand 7 |
| 165792 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165794 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFSET), |
| 165796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165797 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165799 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165800 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165802 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165803 | GIR_RootConstrainSelectedInstOperands, |
| 165804 | // GIR_Coverage, 4823, |
| 165805 | GIR_EraseRootFromParent_Done, |
| 165806 | // Label 7767: @524515 |
| 165807 | GIM_Try, /*On fail goto*//*Label 7768*/ GIMT_Encode4(524580), // Rule ID 4827 // |
| 165808 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165809 | // MIs[0] offset |
| 165810 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165811 | // MIs[0] auxiliary |
| 165812 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165813 | // MIs[0] Operand 7 |
| 165814 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165815 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165816 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165817 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFSET), |
| 165818 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165819 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165821 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165822 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165823 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165825 | GIR_RootConstrainSelectedInstOperands, |
| 165826 | // GIR_Coverage, 4827, |
| 165827 | GIR_EraseRootFromParent_Done, |
| 165828 | // Label 7768: @524580 |
| 165829 | GIM_Try, /*On fail goto*//*Label 7769*/ GIMT_Encode4(524646), // Rule ID 4824 // |
| 165830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165831 | // MIs[0] offset |
| 165832 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165833 | // MIs[0] auxiliary |
| 165834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165835 | // MIs[0] Operand 7 |
| 165836 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165838 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_OFFEN), |
| 165840 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165841 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165842 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165844 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165845 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165846 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165847 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165848 | GIR_RootConstrainSelectedInstOperands, |
| 165849 | // GIR_Coverage, 4824, |
| 165850 | GIR_EraseRootFromParent_Done, |
| 165851 | // Label 7769: @524646 |
| 165852 | GIM_Try, /*On fail goto*//*Label 7770*/ GIMT_Encode4(524709), // Rule ID 4828 // |
| 165853 | // MIs[0] offset |
| 165854 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165855 | // MIs[0] auxiliary |
| 165856 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165857 | // MIs[0] Operand 7 |
| 165858 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165860 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_OFFEN), |
| 165862 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165863 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 165864 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165866 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165867 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165868 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165869 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165870 | GIR_RootConstrainSelectedInstOperands, |
| 165871 | // GIR_Coverage, 4828, |
| 165872 | GIR_EraseRootFromParent_Done, |
| 165873 | // Label 7770: @524709 |
| 165874 | GIM_Reject, |
| 165875 | // Label 7766: @524710 |
| 165876 | GIM_Try, /*On fail goto*//*Label 7771*/ GIMT_Encode4(524824), |
| 165877 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165878 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165879 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165880 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165881 | GIM_Try, /*On fail goto*//*Label 7772*/ GIMT_Encode4(524777), // Rule ID 4825 // |
| 165882 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165883 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165884 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165885 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_IDXEN), |
| 165886 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165887 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165888 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165889 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165890 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165891 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165892 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165893 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165894 | GIR_RootConstrainSelectedInstOperands, |
| 165895 | // GIR_Coverage, 4825, |
| 165896 | GIR_EraseRootFromParent_Done, |
| 165897 | // Label 7772: @524777 |
| 165898 | GIM_Try, /*On fail goto*//*Label 7773*/ GIMT_Encode4(524823), // Rule ID 4829 // |
| 165899 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165900 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165901 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_IDXEN), |
| 165902 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165903 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 165904 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165905 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165906 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165907 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165908 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165909 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165910 | GIR_RootConstrainSelectedInstOperands, |
| 165911 | // GIR_Coverage, 4829, |
| 165912 | GIR_EraseRootFromParent_Done, |
| 165913 | // Label 7773: @524823 |
| 165914 | GIM_Reject, |
| 165915 | // Label 7771: @524824 |
| 165916 | GIM_Try, /*On fail goto*//*Label 7774*/ GIMT_Encode4(525018), |
| 165917 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165918 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165919 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 165920 | GIM_Try, /*On fail goto*//*Label 7775*/ GIMT_Encode4(524929), // Rule ID 4826 // |
| 165921 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165923 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165924 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165925 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165926 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165927 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165928 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165929 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165930 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165931 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165932 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165933 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_BOTHEN), |
| 165935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165936 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165937 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165939 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165940 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165943 | GIR_RootConstrainSelectedInstOperands, |
| 165944 | // GIR_Coverage, 4826, |
| 165945 | GIR_EraseRootFromParent_Done, |
| 165946 | // Label 7775: @524929 |
| 165947 | GIM_Try, /*On fail goto*//*Label 7776*/ GIMT_Encode4(525017), // Rule ID 4830 // |
| 165948 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165949 | // (SIbuffer_load_byte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165950 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 165951 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 165952 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 165953 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 165954 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 165955 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 165956 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 165957 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 165958 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165959 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 165960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SBYTE_TFE_VBUFFER_BOTHEN), |
| 165961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 165962 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 165963 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 165964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 165965 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 165966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 165967 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 165968 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 165969 | GIR_RootConstrainSelectedInstOperands, |
| 165970 | // GIR_Coverage, 4830, |
| 165971 | GIR_EraseRootFromParent_Done, |
| 165972 | // Label 7776: @525017 |
| 165973 | GIM_Reject, |
| 165974 | // Label 7774: @525018 |
| 165975 | GIM_Reject, |
| 165976 | // Label 7765: @525019 |
| 165977 | GIM_Reject, |
| 165978 | // Label 131: @525020 |
| 165979 | GIM_Try, /*On fail goto*//*Label 7777*/ GIMT_Encode4(525625), |
| 165980 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 165981 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 165982 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 165983 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 165984 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 165985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 165986 | GIM_Try, /*On fail goto*//*Label 7778*/ GIMT_Encode4(525316), |
| 165987 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 165988 | GIM_Try, /*On fail goto*//*Label 7779*/ GIMT_Encode4(525121), // Rule ID 4767 // |
| 165989 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 165990 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 165991 | // MIs[0] offset |
| 165992 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 165993 | // MIs[0] auxiliary |
| 165994 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 165995 | // MIs[0] Operand 7 |
| 165996 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 165997 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 165998 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 165999 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFSET), |
| 166000 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166001 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166002 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166003 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166004 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166005 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166006 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166007 | GIR_RootConstrainSelectedInstOperands, |
| 166008 | // GIR_Coverage, 4767, |
| 166009 | GIR_EraseRootFromParent_Done, |
| 166010 | // Label 7779: @525121 |
| 166011 | GIM_Try, /*On fail goto*//*Label 7780*/ GIMT_Encode4(525186), // Rule ID 4771 // |
| 166012 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166013 | // MIs[0] offset |
| 166014 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166015 | // MIs[0] auxiliary |
| 166016 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166017 | // MIs[0] Operand 7 |
| 166018 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166019 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166020 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166021 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFSET), |
| 166022 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166023 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166025 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166026 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166028 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166029 | GIR_RootConstrainSelectedInstOperands, |
| 166030 | // GIR_Coverage, 4771, |
| 166031 | GIR_EraseRootFromParent_Done, |
| 166032 | // Label 7780: @525186 |
| 166033 | GIM_Try, /*On fail goto*//*Label 7781*/ GIMT_Encode4(525252), // Rule ID 4768 // |
| 166034 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166035 | // MIs[0] offset |
| 166036 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166037 | // MIs[0] auxiliary |
| 166038 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166039 | // MIs[0] Operand 7 |
| 166040 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166041 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166042 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166043 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_OFFEN), |
| 166044 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166045 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166046 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166048 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166049 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166050 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166052 | GIR_RootConstrainSelectedInstOperands, |
| 166053 | // GIR_Coverage, 4768, |
| 166054 | GIR_EraseRootFromParent_Done, |
| 166055 | // Label 7781: @525252 |
| 166056 | GIM_Try, /*On fail goto*//*Label 7782*/ GIMT_Encode4(525315), // Rule ID 4772 // |
| 166057 | // MIs[0] offset |
| 166058 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166059 | // MIs[0] auxiliary |
| 166060 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166061 | // MIs[0] Operand 7 |
| 166062 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166063 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166064 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166065 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_OFFEN), |
| 166066 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166067 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166068 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166070 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166071 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166072 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166073 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166074 | GIR_RootConstrainSelectedInstOperands, |
| 166075 | // GIR_Coverage, 4772, |
| 166076 | GIR_EraseRootFromParent_Done, |
| 166077 | // Label 7782: @525315 |
| 166078 | GIM_Reject, |
| 166079 | // Label 7778: @525316 |
| 166080 | GIM_Try, /*On fail goto*//*Label 7783*/ GIMT_Encode4(525430), |
| 166081 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166082 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166083 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166084 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166085 | GIM_Try, /*On fail goto*//*Label 7784*/ GIMT_Encode4(525383), // Rule ID 4769 // |
| 166086 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166087 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166088 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166089 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_IDXEN), |
| 166090 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166091 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166092 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166093 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166094 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166095 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166096 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166097 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166098 | GIR_RootConstrainSelectedInstOperands, |
| 166099 | // GIR_Coverage, 4769, |
| 166100 | GIR_EraseRootFromParent_Done, |
| 166101 | // Label 7784: @525383 |
| 166102 | GIM_Try, /*On fail goto*//*Label 7785*/ GIMT_Encode4(525429), // Rule ID 4773 // |
| 166103 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166104 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_IDXEN), |
| 166106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166107 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166108 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166110 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166111 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166112 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166113 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166114 | GIR_RootConstrainSelectedInstOperands, |
| 166115 | // GIR_Coverage, 4773, |
| 166116 | GIR_EraseRootFromParent_Done, |
| 166117 | // Label 7785: @525429 |
| 166118 | GIM_Reject, |
| 166119 | // Label 7783: @525430 |
| 166120 | GIM_Try, /*On fail goto*//*Label 7786*/ GIMT_Encode4(525624), |
| 166121 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166122 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166123 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166124 | GIM_Try, /*On fail goto*//*Label 7787*/ GIMT_Encode4(525535), // Rule ID 4770 // |
| 166125 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166127 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166128 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166129 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166130 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166131 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166132 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166133 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166134 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166135 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166136 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166137 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166138 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_BOTHEN), |
| 166139 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166140 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166141 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166142 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166143 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166144 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166145 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166146 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166147 | GIR_RootConstrainSelectedInstOperands, |
| 166148 | // GIR_Coverage, 4770, |
| 166149 | GIR_EraseRootFromParent_Done, |
| 166150 | // Label 7787: @525535 |
| 166151 | GIM_Try, /*On fail goto*//*Label 7788*/ GIMT_Encode4(525623), // Rule ID 4774 // |
| 166152 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166153 | // (SIbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166154 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166155 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166156 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166157 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166158 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166159 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166160 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166161 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166162 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166163 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166164 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_VBUFFER_BOTHEN), |
| 166165 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166166 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166167 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166168 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166169 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166170 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166171 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166172 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166173 | GIR_RootConstrainSelectedInstOperands, |
| 166174 | // GIR_Coverage, 4774, |
| 166175 | GIR_EraseRootFromParent_Done, |
| 166176 | // Label 7788: @525623 |
| 166177 | GIM_Reject, |
| 166178 | // Label 7786: @525624 |
| 166179 | GIM_Reject, |
| 166180 | // Label 7777: @525625 |
| 166181 | GIM_Reject, |
| 166182 | // Label 132: @525626 |
| 166183 | GIM_Try, /*On fail goto*//*Label 7789*/ GIMT_Encode4(526231), |
| 166184 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 166185 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 166186 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 166187 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 166188 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 166189 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 166190 | GIM_Try, /*On fail goto*//*Label 7790*/ GIMT_Encode4(525922), |
| 166191 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166192 | GIM_Try, /*On fail goto*//*Label 7791*/ GIMT_Encode4(525727), // Rule ID 4831 // |
| 166193 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166194 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166195 | // MIs[0] offset |
| 166196 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166197 | // MIs[0] auxiliary |
| 166198 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166199 | // MIs[0] Operand 7 |
| 166200 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166201 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166202 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166203 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFSET), |
| 166204 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166205 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166207 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166208 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166209 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166210 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166211 | GIR_RootConstrainSelectedInstOperands, |
| 166212 | // GIR_Coverage, 4831, |
| 166213 | GIR_EraseRootFromParent_Done, |
| 166214 | // Label 7791: @525727 |
| 166215 | GIM_Try, /*On fail goto*//*Label 7792*/ GIMT_Encode4(525792), // Rule ID 4835 // |
| 166216 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166217 | // MIs[0] offset |
| 166218 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166219 | // MIs[0] auxiliary |
| 166220 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166221 | // MIs[0] Operand 7 |
| 166222 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166223 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166224 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166225 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFSET), |
| 166226 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166227 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166229 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166230 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166231 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166232 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166233 | GIR_RootConstrainSelectedInstOperands, |
| 166234 | // GIR_Coverage, 4835, |
| 166235 | GIR_EraseRootFromParent_Done, |
| 166236 | // Label 7792: @525792 |
| 166237 | GIM_Try, /*On fail goto*//*Label 7793*/ GIMT_Encode4(525858), // Rule ID 4832 // |
| 166238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166239 | // MIs[0] offset |
| 166240 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166241 | // MIs[0] auxiliary |
| 166242 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166243 | // MIs[0] Operand 7 |
| 166244 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166246 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166247 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_OFFEN), |
| 166248 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166249 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166250 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166251 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166252 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166253 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166254 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166255 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166256 | GIR_RootConstrainSelectedInstOperands, |
| 166257 | // GIR_Coverage, 4832, |
| 166258 | GIR_EraseRootFromParent_Done, |
| 166259 | // Label 7793: @525858 |
| 166260 | GIM_Try, /*On fail goto*//*Label 7794*/ GIMT_Encode4(525921), // Rule ID 4836 // |
| 166261 | // MIs[0] offset |
| 166262 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166263 | // MIs[0] auxiliary |
| 166264 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166265 | // MIs[0] Operand 7 |
| 166266 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166268 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_OFFEN), |
| 166270 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166271 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166272 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166274 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166278 | GIR_RootConstrainSelectedInstOperands, |
| 166279 | // GIR_Coverage, 4836, |
| 166280 | GIR_EraseRootFromParent_Done, |
| 166281 | // Label 7794: @525921 |
| 166282 | GIM_Reject, |
| 166283 | // Label 7790: @525922 |
| 166284 | GIM_Try, /*On fail goto*//*Label 7795*/ GIMT_Encode4(526036), |
| 166285 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166286 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166287 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166288 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166289 | GIM_Try, /*On fail goto*//*Label 7796*/ GIMT_Encode4(525989), // Rule ID 4833 // |
| 166290 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166292 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_IDXEN), |
| 166294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166295 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166296 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166298 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166300 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166301 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166302 | GIR_RootConstrainSelectedInstOperands, |
| 166303 | // GIR_Coverage, 4833, |
| 166304 | GIR_EraseRootFromParent_Done, |
| 166305 | // Label 7796: @525989 |
| 166306 | GIM_Try, /*On fail goto*//*Label 7797*/ GIMT_Encode4(526035), // Rule ID 4837 // |
| 166307 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166308 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166309 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_IDXEN), |
| 166310 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166311 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166312 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166313 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166314 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166315 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166316 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166317 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166318 | GIR_RootConstrainSelectedInstOperands, |
| 166319 | // GIR_Coverage, 4837, |
| 166320 | GIR_EraseRootFromParent_Done, |
| 166321 | // Label 7797: @526035 |
| 166322 | GIM_Reject, |
| 166323 | // Label 7795: @526036 |
| 166324 | GIM_Try, /*On fail goto*//*Label 7798*/ GIMT_Encode4(526230), |
| 166325 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166326 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166327 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166328 | GIM_Try, /*On fail goto*//*Label 7799*/ GIMT_Encode4(526141), // Rule ID 4834 // |
| 166329 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166330 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166331 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166332 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166333 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166334 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166335 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166336 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166337 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166338 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166339 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166340 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166341 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166342 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_BOTHEN), |
| 166343 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166344 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166345 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166346 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166347 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166348 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166349 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166350 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166351 | GIR_RootConstrainSelectedInstOperands, |
| 166352 | // GIR_Coverage, 4834, |
| 166353 | GIR_EraseRootFromParent_Done, |
| 166354 | // Label 7799: @526141 |
| 166355 | GIM_Try, /*On fail goto*//*Label 7800*/ GIMT_Encode4(526229), // Rule ID 4838 // |
| 166356 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166357 | // (SIbuffer_load_short_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166358 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166359 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166360 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166361 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166362 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166363 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166364 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166365 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166366 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166367 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166368 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_SSHORT_TFE_VBUFFER_BOTHEN), |
| 166369 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166370 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166371 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166372 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166373 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166374 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166375 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166376 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166377 | GIR_RootConstrainSelectedInstOperands, |
| 166378 | // GIR_Coverage, 4838, |
| 166379 | GIR_EraseRootFromParent_Done, |
| 166380 | // Label 7800: @526229 |
| 166381 | GIM_Reject, |
| 166382 | // Label 7798: @526230 |
| 166383 | GIM_Reject, |
| 166384 | // Label 7789: @526231 |
| 166385 | GIM_Reject, |
| 166386 | // Label 133: @526232 |
| 166387 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(12), GIMT_Encode2(20), /*)*//*default:*//*Label 7805*/ GIMT_Encode4(528751), |
| 166388 | /*GILLT_v2s32*//*Label 7801*/ GIMT_Encode4(526275), GIMT_Encode4(0), |
| 166389 | /*GILLT_v3s32*//*Label 7802*/ GIMT_Encode4(526894), GIMT_Encode4(0), GIMT_Encode4(0), |
| 166390 | /*GILLT_v4s32*//*Label 7803*/ GIMT_Encode4(527513), GIMT_Encode4(0), |
| 166391 | /*GILLT_v5s32*//*Label 7804*/ GIMT_Encode4(528132), |
| 166392 | // Label 7801: @526275 |
| 166393 | GIM_Try, /*On fail goto*//*Label 7806*/ GIMT_Encode4(526893), |
| 166394 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 166395 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 166396 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 166397 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 166398 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 166399 | GIM_Try, /*On fail goto*//*Label 7807*/ GIMT_Encode4(526368), // Rule ID 4791 // |
| 166400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166401 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166402 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166403 | // MIs[0] offset |
| 166404 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166405 | // MIs[0] auxiliary |
| 166406 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166407 | // MIs[0] Operand 7 |
| 166408 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166409 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166410 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFSET), |
| 166412 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166413 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166415 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166418 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166419 | GIR_RootConstrainSelectedInstOperands, |
| 166420 | // GIR_Coverage, 4791, |
| 166421 | GIR_EraseRootFromParent_Done, |
| 166422 | // Label 7807: @526368 |
| 166423 | GIM_Try, /*On fail goto*//*Label 7808*/ GIMT_Encode4(526437), // Rule ID 4795 // |
| 166424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166425 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166426 | // MIs[0] offset |
| 166427 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166428 | // MIs[0] auxiliary |
| 166429 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166430 | // MIs[0] Operand 7 |
| 166431 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166433 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166434 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFSET), |
| 166435 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166436 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166438 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166440 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166442 | GIR_RootConstrainSelectedInstOperands, |
| 166443 | // GIR_Coverage, 4795, |
| 166444 | GIR_EraseRootFromParent_Done, |
| 166445 | // Label 7808: @526437 |
| 166446 | GIM_Try, /*On fail goto*//*Label 7809*/ GIMT_Encode4(526507), // Rule ID 4792 // |
| 166447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166449 | // MIs[0] offset |
| 166450 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166451 | // MIs[0] auxiliary |
| 166452 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166453 | // MIs[0] Operand 7 |
| 166454 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166456 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_OFFEN), |
| 166458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166459 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166460 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166462 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166466 | GIR_RootConstrainSelectedInstOperands, |
| 166467 | // GIR_Coverage, 4792, |
| 166468 | GIR_EraseRootFromParent_Done, |
| 166469 | // Label 7809: @526507 |
| 166470 | GIM_Try, /*On fail goto*//*Label 7810*/ GIMT_Encode4(526574), // Rule ID 4796 // |
| 166471 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166472 | // MIs[0] offset |
| 166473 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166474 | // MIs[0] auxiliary |
| 166475 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166476 | // MIs[0] Operand 7 |
| 166477 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166479 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_OFFEN), |
| 166481 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166482 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166483 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166485 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166486 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166487 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166489 | GIR_RootConstrainSelectedInstOperands, |
| 166490 | // GIR_Coverage, 4796, |
| 166491 | GIR_EraseRootFromParent_Done, |
| 166492 | // Label 7810: @526574 |
| 166493 | GIM_Try, /*On fail goto*//*Label 7811*/ GIMT_Encode4(526636), // Rule ID 4793 // |
| 166494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166495 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166496 | // MIs[0] offset |
| 166497 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166498 | // MIs[0] auxiliary |
| 166499 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166500 | // MIs[0] Operand 7 |
| 166501 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166503 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_IDXEN), |
| 166505 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166506 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166507 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166509 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166510 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166513 | GIR_RootConstrainSelectedInstOperands, |
| 166514 | // GIR_Coverage, 4793, |
| 166515 | GIR_EraseRootFromParent_Done, |
| 166516 | // Label 7811: @526636 |
| 166517 | GIM_Try, /*On fail goto*//*Label 7812*/ GIMT_Encode4(526695), // Rule ID 4797 // |
| 166518 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166519 | // MIs[0] offset |
| 166520 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166521 | // MIs[0] auxiliary |
| 166522 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166523 | // MIs[0] Operand 7 |
| 166524 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166526 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_IDXEN), |
| 166528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166529 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166530 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166532 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166533 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166534 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166535 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166536 | GIR_RootConstrainSelectedInstOperands, |
| 166537 | // GIR_Coverage, 4797, |
| 166538 | GIR_EraseRootFromParent_Done, |
| 166539 | // Label 7812: @526695 |
| 166540 | GIM_Try, /*On fail goto*//*Label 7813*/ GIMT_Encode4(526795), // Rule ID 4794 // |
| 166541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166542 | // MIs[0] offset |
| 166543 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166544 | // MIs[0] auxiliary |
| 166545 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166546 | // MIs[0] Operand 7 |
| 166547 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166549 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166551 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166552 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166553 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166554 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166555 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166556 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166557 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166558 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166559 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_BOTHEN), |
| 166561 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166563 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166565 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166566 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166569 | GIR_RootConstrainSelectedInstOperands, |
| 166570 | // GIR_Coverage, 4794, |
| 166571 | GIR_EraseRootFromParent_Done, |
| 166572 | // Label 7813: @526795 |
| 166573 | GIM_Try, /*On fail goto*//*Label 7814*/ GIMT_Encode4(526892), // Rule ID 4798 // |
| 166574 | // MIs[0] offset |
| 166575 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166576 | // MIs[0] auxiliary |
| 166577 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166578 | // MIs[0] Operand 7 |
| 166579 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166581 | // (SIbuffer_load_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166582 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166584 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166585 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166586 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166587 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166588 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166589 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166590 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166591 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORD_TFE_VBUFFER_BOTHEN), |
| 166593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166595 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166597 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166598 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166600 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166601 | GIR_RootConstrainSelectedInstOperands, |
| 166602 | // GIR_Coverage, 4798, |
| 166603 | GIR_EraseRootFromParent_Done, |
| 166604 | // Label 7814: @526892 |
| 166605 | GIM_Reject, |
| 166606 | // Label 7806: @526893 |
| 166607 | GIM_Reject, |
| 166608 | // Label 7802: @526894 |
| 166609 | GIM_Try, /*On fail goto*//*Label 7815*/ GIMT_Encode4(527512), |
| 166610 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 166611 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 166612 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 166613 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 166614 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 166615 | GIM_Try, /*On fail goto*//*Label 7816*/ GIMT_Encode4(526987), // Rule ID 4799 // |
| 166616 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166617 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166618 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166619 | // MIs[0] offset |
| 166620 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166621 | // MIs[0] auxiliary |
| 166622 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166623 | // MIs[0] Operand 7 |
| 166624 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166626 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_TFE_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFSET), |
| 166628 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166629 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166631 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166633 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166634 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166635 | GIR_RootConstrainSelectedInstOperands, |
| 166636 | // GIR_Coverage, 4799, |
| 166637 | GIR_EraseRootFromParent_Done, |
| 166638 | // Label 7816: @526987 |
| 166639 | GIM_Try, /*On fail goto*//*Label 7817*/ GIMT_Encode4(527056), // Rule ID 4803 // |
| 166640 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166641 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166642 | // MIs[0] offset |
| 166643 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166644 | // MIs[0] auxiliary |
| 166645 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166646 | // MIs[0] Operand 7 |
| 166647 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166649 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166650 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFSET), |
| 166651 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166652 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166653 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166654 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166655 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166656 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166657 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166658 | GIR_RootConstrainSelectedInstOperands, |
| 166659 | // GIR_Coverage, 4803, |
| 166660 | GIR_EraseRootFromParent_Done, |
| 166661 | // Label 7817: @527056 |
| 166662 | GIM_Try, /*On fail goto*//*Label 7818*/ GIMT_Encode4(527126), // Rule ID 4800 // |
| 166663 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166664 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166665 | // MIs[0] offset |
| 166666 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166667 | // MIs[0] auxiliary |
| 166668 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166669 | // MIs[0] Operand 7 |
| 166670 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166671 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166672 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_TFE_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166673 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_OFFEN), |
| 166674 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166675 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166676 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166678 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166679 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166680 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166681 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166682 | GIR_RootConstrainSelectedInstOperands, |
| 166683 | // GIR_Coverage, 4800, |
| 166684 | GIR_EraseRootFromParent_Done, |
| 166685 | // Label 7818: @527126 |
| 166686 | GIM_Try, /*On fail goto*//*Label 7819*/ GIMT_Encode4(527193), // Rule ID 4804 // |
| 166687 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166688 | // MIs[0] offset |
| 166689 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166690 | // MIs[0] auxiliary |
| 166691 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166692 | // MIs[0] Operand 7 |
| 166693 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166694 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166695 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_OFFEN), |
| 166697 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166698 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166699 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166701 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166702 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166704 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166705 | GIR_RootConstrainSelectedInstOperands, |
| 166706 | // GIR_Coverage, 4804, |
| 166707 | GIR_EraseRootFromParent_Done, |
| 166708 | // Label 7819: @527193 |
| 166709 | GIM_Try, /*On fail goto*//*Label 7820*/ GIMT_Encode4(527255), // Rule ID 4801 // |
| 166710 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166712 | // MIs[0] offset |
| 166713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166714 | // MIs[0] auxiliary |
| 166715 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166716 | // MIs[0] Operand 7 |
| 166717 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166719 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_TFE_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_IDXEN), |
| 166721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166722 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166723 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166725 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166726 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166729 | GIR_RootConstrainSelectedInstOperands, |
| 166730 | // GIR_Coverage, 4801, |
| 166731 | GIR_EraseRootFromParent_Done, |
| 166732 | // Label 7820: @527255 |
| 166733 | GIM_Try, /*On fail goto*//*Label 7821*/ GIMT_Encode4(527314), // Rule ID 4805 // |
| 166734 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166735 | // MIs[0] offset |
| 166736 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166737 | // MIs[0] auxiliary |
| 166738 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166739 | // MIs[0] Operand 7 |
| 166740 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166741 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166742 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166743 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_IDXEN), |
| 166744 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166745 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166746 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166747 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166748 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166750 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166751 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166752 | GIR_RootConstrainSelectedInstOperands, |
| 166753 | // GIR_Coverage, 4805, |
| 166754 | GIR_EraseRootFromParent_Done, |
| 166755 | // Label 7821: @527314 |
| 166756 | GIM_Try, /*On fail goto*//*Label 7822*/ GIMT_Encode4(527414), // Rule ID 4802 // |
| 166757 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166758 | // MIs[0] offset |
| 166759 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166760 | // MIs[0] auxiliary |
| 166761 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166762 | // MIs[0] Operand 7 |
| 166763 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166764 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166765 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_TFE_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166766 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166767 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166768 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166769 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166770 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166771 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166772 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166773 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166774 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166775 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_BOTHEN), |
| 166777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166778 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166779 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166781 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166785 | GIR_RootConstrainSelectedInstOperands, |
| 166786 | // GIR_Coverage, 4802, |
| 166787 | GIR_EraseRootFromParent_Done, |
| 166788 | // Label 7822: @527414 |
| 166789 | GIM_Try, /*On fail goto*//*Label 7823*/ GIMT_Encode4(527511), // Rule ID 4806 // |
| 166790 | // MIs[0] offset |
| 166791 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166792 | // MIs[0] auxiliary |
| 166793 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166794 | // MIs[0] Operand 7 |
| 166795 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166797 | // (SIbuffer_load_tfe:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166798 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166799 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166800 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166801 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166802 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166803 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166804 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166805 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166806 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166807 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX2_TFE_VBUFFER_BOTHEN), |
| 166809 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166810 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166811 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166813 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166814 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166815 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166817 | GIR_RootConstrainSelectedInstOperands, |
| 166818 | // GIR_Coverage, 4806, |
| 166819 | GIR_EraseRootFromParent_Done, |
| 166820 | // Label 7823: @527511 |
| 166821 | GIM_Reject, |
| 166822 | // Label 7815: @527512 |
| 166823 | GIM_Reject, |
| 166824 | // Label 7803: @527513 |
| 166825 | GIM_Try, /*On fail goto*//*Label 7824*/ GIMT_Encode4(528131), |
| 166826 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 166827 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 166828 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 166829 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 166830 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 166831 | GIM_Try, /*On fail goto*//*Label 7825*/ GIMT_Encode4(527606), // Rule ID 4807 // |
| 166832 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166833 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166834 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166835 | // MIs[0] offset |
| 166836 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166837 | // MIs[0] auxiliary |
| 166838 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166839 | // MIs[0] Operand 7 |
| 166840 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166841 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166842 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_TFE_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166843 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFSET), |
| 166844 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166845 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166846 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166847 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166848 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166849 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166850 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166851 | GIR_RootConstrainSelectedInstOperands, |
| 166852 | // GIR_Coverage, 4807, |
| 166853 | GIR_EraseRootFromParent_Done, |
| 166854 | // Label 7825: @527606 |
| 166855 | GIM_Try, /*On fail goto*//*Label 7826*/ GIMT_Encode4(527675), // Rule ID 4811 // |
| 166856 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166857 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166858 | // MIs[0] offset |
| 166859 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166860 | // MIs[0] auxiliary |
| 166861 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166862 | // MIs[0] Operand 7 |
| 166863 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166864 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166865 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166866 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFSET), |
| 166867 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166868 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166869 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166870 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166871 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166872 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166873 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166874 | GIR_RootConstrainSelectedInstOperands, |
| 166875 | // GIR_Coverage, 4811, |
| 166876 | GIR_EraseRootFromParent_Done, |
| 166877 | // Label 7826: @527675 |
| 166878 | GIM_Try, /*On fail goto*//*Label 7827*/ GIMT_Encode4(527745), // Rule ID 4808 // |
| 166879 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166880 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166881 | // MIs[0] offset |
| 166882 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166883 | // MIs[0] auxiliary |
| 166884 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166885 | // MIs[0] Operand 7 |
| 166886 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166887 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166888 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_TFE_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166889 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_OFFEN), |
| 166890 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166891 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166892 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166893 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166894 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166895 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166896 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166897 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166898 | GIR_RootConstrainSelectedInstOperands, |
| 166899 | // GIR_Coverage, 4808, |
| 166900 | GIR_EraseRootFromParent_Done, |
| 166901 | // Label 7827: @527745 |
| 166902 | GIM_Try, /*On fail goto*//*Label 7828*/ GIMT_Encode4(527812), // Rule ID 4812 // |
| 166903 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 166904 | // MIs[0] offset |
| 166905 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166906 | // MIs[0] auxiliary |
| 166907 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166908 | // MIs[0] Operand 7 |
| 166909 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 166910 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166911 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166912 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_OFFEN), |
| 166913 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166914 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 166915 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166917 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166918 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166919 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166921 | GIR_RootConstrainSelectedInstOperands, |
| 166922 | // GIR_Coverage, 4812, |
| 166923 | GIR_EraseRootFromParent_Done, |
| 166924 | // Label 7828: @527812 |
| 166925 | GIM_Try, /*On fail goto*//*Label 7829*/ GIMT_Encode4(527874), // Rule ID 4809 // |
| 166926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166927 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166928 | // MIs[0] offset |
| 166929 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166930 | // MIs[0] auxiliary |
| 166931 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166932 | // MIs[0] Operand 7 |
| 166933 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166934 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166935 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_TFE_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166936 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_IDXEN), |
| 166937 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166938 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166939 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166940 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166941 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166942 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166943 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166944 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166945 | GIR_RootConstrainSelectedInstOperands, |
| 166946 | // GIR_Coverage, 4809, |
| 166947 | GIR_EraseRootFromParent_Done, |
| 166948 | // Label 7829: @527874 |
| 166949 | GIM_Try, /*On fail goto*//*Label 7830*/ GIMT_Encode4(527933), // Rule ID 4813 // |
| 166950 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 166951 | // MIs[0] offset |
| 166952 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166953 | // MIs[0] auxiliary |
| 166954 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166955 | // MIs[0] Operand 7 |
| 166956 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166957 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166958 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_IDXEN), |
| 166960 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166961 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 166962 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166964 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 166967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 166968 | GIR_RootConstrainSelectedInstOperands, |
| 166969 | // GIR_Coverage, 4813, |
| 166970 | GIR_EraseRootFromParent_Done, |
| 166971 | // Label 7830: @527933 |
| 166972 | GIM_Try, /*On fail goto*//*Label 7831*/ GIMT_Encode4(528033), // Rule ID 4810 // |
| 166973 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 166974 | // MIs[0] offset |
| 166975 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 166976 | // MIs[0] auxiliary |
| 166977 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 166978 | // MIs[0] Operand 7 |
| 166979 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 166980 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 166981 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_TFE_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 166982 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 166983 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 166984 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 166985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 166986 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 166987 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 166988 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 166989 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 166990 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166991 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 166992 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_BOTHEN), |
| 166993 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 166994 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 166995 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 166996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 166997 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 166998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 166999 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167000 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167001 | GIR_RootConstrainSelectedInstOperands, |
| 167002 | // GIR_Coverage, 4810, |
| 167003 | GIR_EraseRootFromParent_Done, |
| 167004 | // Label 7831: @528033 |
| 167005 | GIM_Try, /*On fail goto*//*Label 7832*/ GIMT_Encode4(528130), // Rule ID 4814 // |
| 167006 | // MIs[0] offset |
| 167007 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167008 | // MIs[0] auxiliary |
| 167009 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167010 | // MIs[0] Operand 7 |
| 167011 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167013 | // (SIbuffer_load_tfe:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167014 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167015 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167016 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167017 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167018 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167019 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167020 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167021 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167022 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167023 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167024 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX3_TFE_VBUFFER_BOTHEN), |
| 167025 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167026 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167027 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167029 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167033 | GIR_RootConstrainSelectedInstOperands, |
| 167034 | // GIR_Coverage, 4814, |
| 167035 | GIR_EraseRootFromParent_Done, |
| 167036 | // Label 7832: @528130 |
| 167037 | GIM_Reject, |
| 167038 | // Label 7824: @528131 |
| 167039 | GIM_Reject, |
| 167040 | // Label 7804: @528132 |
| 167041 | GIM_Try, /*On fail goto*//*Label 7833*/ GIMT_Encode4(528750), |
| 167042 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 167043 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 167044 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 167045 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 167046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_160RegClassID), |
| 167047 | GIM_Try, /*On fail goto*//*Label 7834*/ GIMT_Encode4(528225), // Rule ID 4815 // |
| 167048 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167049 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167050 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167051 | // MIs[0] offset |
| 167052 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167053 | // MIs[0] auxiliary |
| 167054 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167055 | // MIs[0] Operand 7 |
| 167056 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167058 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_TFE_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFSET), |
| 167060 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167061 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167063 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167066 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167067 | GIR_RootConstrainSelectedInstOperands, |
| 167068 | // GIR_Coverage, 4815, |
| 167069 | GIR_EraseRootFromParent_Done, |
| 167070 | // Label 7834: @528225 |
| 167071 | GIM_Try, /*On fail goto*//*Label 7835*/ GIMT_Encode4(528294), // Rule ID 4819 // |
| 167072 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167073 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167074 | // MIs[0] offset |
| 167075 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167076 | // MIs[0] auxiliary |
| 167077 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167078 | // MIs[0] Operand 7 |
| 167079 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167081 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET:{ *:[v5i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFSET), |
| 167083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167084 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167086 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167087 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167088 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167089 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167090 | GIR_RootConstrainSelectedInstOperands, |
| 167091 | // GIR_Coverage, 4819, |
| 167092 | GIR_EraseRootFromParent_Done, |
| 167093 | // Label 7835: @528294 |
| 167094 | GIM_Try, /*On fail goto*//*Label 7836*/ GIMT_Encode4(528364), // Rule ID 4816 // |
| 167095 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167096 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167097 | // MIs[0] offset |
| 167098 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167099 | // MIs[0] auxiliary |
| 167100 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167101 | // MIs[0] Operand 7 |
| 167102 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167103 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167104 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_TFE_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167105 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_OFFEN), |
| 167106 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167107 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167108 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167109 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167110 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167111 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167112 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167113 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167114 | GIR_RootConstrainSelectedInstOperands, |
| 167115 | // GIR_Coverage, 4816, |
| 167116 | GIR_EraseRootFromParent_Done, |
| 167117 | // Label 7836: @528364 |
| 167118 | GIM_Try, /*On fail goto*//*Label 7837*/ GIMT_Encode4(528431), // Rule ID 4820 // |
| 167119 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167120 | // MIs[0] offset |
| 167121 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167122 | // MIs[0] auxiliary |
| 167123 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167124 | // MIs[0] Operand 7 |
| 167125 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167126 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167127 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167128 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_OFFEN), |
| 167129 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167130 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167131 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167133 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167134 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167135 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167136 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167137 | GIR_RootConstrainSelectedInstOperands, |
| 167138 | // GIR_Coverage, 4820, |
| 167139 | GIR_EraseRootFromParent_Done, |
| 167140 | // Label 7837: @528431 |
| 167141 | GIM_Try, /*On fail goto*//*Label 7838*/ GIMT_Encode4(528493), // Rule ID 4817 // |
| 167142 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167143 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167144 | // MIs[0] offset |
| 167145 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167146 | // MIs[0] auxiliary |
| 167147 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167148 | // MIs[0] Operand 7 |
| 167149 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167150 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167151 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_TFE_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167152 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_IDXEN), |
| 167153 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167154 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167155 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167156 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167157 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167158 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167159 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167160 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167161 | GIR_RootConstrainSelectedInstOperands, |
| 167162 | // GIR_Coverage, 4817, |
| 167163 | GIR_EraseRootFromParent_Done, |
| 167164 | // Label 7838: @528493 |
| 167165 | GIM_Try, /*On fail goto*//*Label 7839*/ GIMT_Encode4(528552), // Rule ID 4821 // |
| 167166 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167167 | // MIs[0] offset |
| 167168 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167169 | // MIs[0] auxiliary |
| 167170 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167171 | // MIs[0] Operand 7 |
| 167172 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167174 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN:{ *:[v5i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_IDXEN), |
| 167176 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167177 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167178 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167180 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167182 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167184 | GIR_RootConstrainSelectedInstOperands, |
| 167185 | // GIR_Coverage, 4821, |
| 167186 | GIR_EraseRootFromParent_Done, |
| 167187 | // Label 7839: @528552 |
| 167188 | GIM_Try, /*On fail goto*//*Label 7840*/ GIMT_Encode4(528652), // Rule ID 4818 // |
| 167189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167190 | // MIs[0] offset |
| 167191 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167192 | // MIs[0] auxiliary |
| 167193 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167194 | // MIs[0] Operand 7 |
| 167195 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167197 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_TFE_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167203 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167204 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167206 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167207 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_BOTHEN), |
| 167209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167210 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167211 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167213 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167214 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167217 | GIR_RootConstrainSelectedInstOperands, |
| 167218 | // GIR_Coverage, 4818, |
| 167219 | GIR_EraseRootFromParent_Done, |
| 167220 | // Label 7840: @528652 |
| 167221 | GIM_Try, /*On fail goto*//*Label 7841*/ GIMT_Encode4(528749), // Rule ID 4822 // |
| 167222 | // MIs[0] offset |
| 167223 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167224 | // MIs[0] auxiliary |
| 167225 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167226 | // MIs[0] Operand 7 |
| 167227 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167229 | // (SIbuffer_load_tfe:{ *:[v5i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN:{ *:[v5i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167230 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167231 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167232 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167233 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167234 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167235 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167236 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167237 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167239 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167240 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_DWORDX4_TFE_VBUFFER_BOTHEN), |
| 167241 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167242 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167243 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167244 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167245 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167248 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167249 | GIR_RootConstrainSelectedInstOperands, |
| 167250 | // GIR_Coverage, 4822, |
| 167251 | GIR_EraseRootFromParent_Done, |
| 167252 | // Label 7841: @528749 |
| 167253 | GIM_Reject, |
| 167254 | // Label 7833: @528750 |
| 167255 | GIM_Reject, |
| 167256 | // Label 7805: @528751 |
| 167257 | GIM_Reject, |
| 167258 | // Label 134: @528752 |
| 167259 | GIM_Try, /*On fail goto*//*Label 7842*/ GIMT_Encode4(529357), |
| 167260 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 167261 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 167262 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 167263 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 167264 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 167265 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 167266 | GIM_Try, /*On fail goto*//*Label 7843*/ GIMT_Encode4(529048), |
| 167267 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167268 | GIM_Try, /*On fail goto*//*Label 7844*/ GIMT_Encode4(528853), // Rule ID 4775 // |
| 167269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167270 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167271 | // MIs[0] offset |
| 167272 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167273 | // MIs[0] auxiliary |
| 167274 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167275 | // MIs[0] Operand 7 |
| 167276 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167278 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFSET), |
| 167280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167281 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167282 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167283 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167284 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167285 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167286 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167287 | GIR_RootConstrainSelectedInstOperands, |
| 167288 | // GIR_Coverage, 4775, |
| 167289 | GIR_EraseRootFromParent_Done, |
| 167290 | // Label 7844: @528853 |
| 167291 | GIM_Try, /*On fail goto*//*Label 7845*/ GIMT_Encode4(528918), // Rule ID 4779 // |
| 167292 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167293 | // MIs[0] offset |
| 167294 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167295 | // MIs[0] auxiliary |
| 167296 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167297 | // MIs[0] Operand 7 |
| 167298 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167299 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167300 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167301 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFSET), |
| 167302 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167303 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167304 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167305 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167306 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167307 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167309 | GIR_RootConstrainSelectedInstOperands, |
| 167310 | // GIR_Coverage, 4779, |
| 167311 | GIR_EraseRootFromParent_Done, |
| 167312 | // Label 7845: @528918 |
| 167313 | GIM_Try, /*On fail goto*//*Label 7846*/ GIMT_Encode4(528984), // Rule ID 4776 // |
| 167314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167315 | // MIs[0] offset |
| 167316 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167317 | // MIs[0] auxiliary |
| 167318 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167319 | // MIs[0] Operand 7 |
| 167320 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167322 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_OFFEN), |
| 167324 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167325 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167326 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167328 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167329 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167330 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167331 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167332 | GIR_RootConstrainSelectedInstOperands, |
| 167333 | // GIR_Coverage, 4776, |
| 167334 | GIR_EraseRootFromParent_Done, |
| 167335 | // Label 7846: @528984 |
| 167336 | GIM_Try, /*On fail goto*//*Label 7847*/ GIMT_Encode4(529047), // Rule ID 4780 // |
| 167337 | // MIs[0] offset |
| 167338 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167339 | // MIs[0] auxiliary |
| 167340 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167341 | // MIs[0] Operand 7 |
| 167342 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167343 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167344 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167345 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_OFFEN), |
| 167346 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167347 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167348 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167350 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167351 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167354 | GIR_RootConstrainSelectedInstOperands, |
| 167355 | // GIR_Coverage, 4780, |
| 167356 | GIR_EraseRootFromParent_Done, |
| 167357 | // Label 7847: @529047 |
| 167358 | GIM_Reject, |
| 167359 | // Label 7843: @529048 |
| 167360 | GIM_Try, /*On fail goto*//*Label 7848*/ GIMT_Encode4(529162), |
| 167361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167362 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167363 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167364 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167365 | GIM_Try, /*On fail goto*//*Label 7849*/ GIMT_Encode4(529115), // Rule ID 4777 // |
| 167366 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167367 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167368 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_IDXEN), |
| 167370 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167371 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167372 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167374 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167375 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167378 | GIR_RootConstrainSelectedInstOperands, |
| 167379 | // GIR_Coverage, 4777, |
| 167380 | GIR_EraseRootFromParent_Done, |
| 167381 | // Label 7849: @529115 |
| 167382 | GIM_Try, /*On fail goto*//*Label 7850*/ GIMT_Encode4(529161), // Rule ID 4781 // |
| 167383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167384 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_IDXEN), |
| 167386 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167387 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167388 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167390 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167391 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167392 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167394 | GIR_RootConstrainSelectedInstOperands, |
| 167395 | // GIR_Coverage, 4781, |
| 167396 | GIR_EraseRootFromParent_Done, |
| 167397 | // Label 7850: @529161 |
| 167398 | GIM_Reject, |
| 167399 | // Label 7848: @529162 |
| 167400 | GIM_Try, /*On fail goto*//*Label 7851*/ GIMT_Encode4(529356), |
| 167401 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167402 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167403 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167404 | GIM_Try, /*On fail goto*//*Label 7852*/ GIMT_Encode4(529267), // Rule ID 4778 // |
| 167405 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167406 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167407 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167408 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167409 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167410 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167411 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167412 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167413 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167414 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167415 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167416 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167417 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167418 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_BOTHEN), |
| 167419 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167420 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167421 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167422 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167423 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167424 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167425 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167426 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167427 | GIR_RootConstrainSelectedInstOperands, |
| 167428 | // GIR_Coverage, 4778, |
| 167429 | GIR_EraseRootFromParent_Done, |
| 167430 | // Label 7852: @529267 |
| 167431 | GIM_Try, /*On fail goto*//*Label 7853*/ GIMT_Encode4(529355), // Rule ID 4782 // |
| 167432 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167433 | // (SIbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167434 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167435 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167436 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167437 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167438 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167439 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167440 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167441 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167442 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167443 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167444 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_VBUFFER_BOTHEN), |
| 167445 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167446 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167447 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167448 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167449 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167450 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167451 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167452 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167453 | GIR_RootConstrainSelectedInstOperands, |
| 167454 | // GIR_Coverage, 4782, |
| 167455 | GIR_EraseRootFromParent_Done, |
| 167456 | // Label 7853: @529355 |
| 167457 | GIM_Reject, |
| 167458 | // Label 7851: @529356 |
| 167459 | GIM_Reject, |
| 167460 | // Label 7842: @529357 |
| 167461 | GIM_Reject, |
| 167462 | // Label 135: @529358 |
| 167463 | GIM_Try, /*On fail goto*//*Label 7854*/ GIMT_Encode4(529963), |
| 167464 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 167465 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 167466 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 167467 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 167468 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 167469 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 167470 | GIM_Try, /*On fail goto*//*Label 7855*/ GIMT_Encode4(529654), |
| 167471 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167472 | GIM_Try, /*On fail goto*//*Label 7856*/ GIMT_Encode4(529459), // Rule ID 4839 // |
| 167473 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167474 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167475 | // MIs[0] offset |
| 167476 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167477 | // MIs[0] auxiliary |
| 167478 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167479 | // MIs[0] Operand 7 |
| 167480 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167482 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFSET), |
| 167484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167485 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167486 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167487 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167488 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167489 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167490 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167491 | GIR_RootConstrainSelectedInstOperands, |
| 167492 | // GIR_Coverage, 4839, |
| 167493 | GIR_EraseRootFromParent_Done, |
| 167494 | // Label 7856: @529459 |
| 167495 | GIM_Try, /*On fail goto*//*Label 7857*/ GIMT_Encode4(529524), // Rule ID 4843 // |
| 167496 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167497 | // MIs[0] offset |
| 167498 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167499 | // MIs[0] auxiliary |
| 167500 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167501 | // MIs[0] Operand 7 |
| 167502 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167503 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167504 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFSET), |
| 167506 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167507 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167509 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167510 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167513 | GIR_RootConstrainSelectedInstOperands, |
| 167514 | // GIR_Coverage, 4843, |
| 167515 | GIR_EraseRootFromParent_Done, |
| 167516 | // Label 7857: @529524 |
| 167517 | GIM_Try, /*On fail goto*//*Label 7858*/ GIMT_Encode4(529590), // Rule ID 4840 // |
| 167518 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167519 | // MIs[0] offset |
| 167520 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167521 | // MIs[0] auxiliary |
| 167522 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167523 | // MIs[0] Operand 7 |
| 167524 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167526 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_OFFEN), |
| 167528 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167529 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167530 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167532 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167533 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167534 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167535 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167536 | GIR_RootConstrainSelectedInstOperands, |
| 167537 | // GIR_Coverage, 4840, |
| 167538 | GIR_EraseRootFromParent_Done, |
| 167539 | // Label 7858: @529590 |
| 167540 | GIM_Try, /*On fail goto*//*Label 7859*/ GIMT_Encode4(529653), // Rule ID 4844 // |
| 167541 | // MIs[0] offset |
| 167542 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167543 | // MIs[0] auxiliary |
| 167544 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167545 | // MIs[0] Operand 7 |
| 167546 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167547 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167548 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167549 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_OFFEN), |
| 167550 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167551 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167552 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167553 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167554 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167555 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167556 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167557 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167558 | GIR_RootConstrainSelectedInstOperands, |
| 167559 | // GIR_Coverage, 4844, |
| 167560 | GIR_EraseRootFromParent_Done, |
| 167561 | // Label 7859: @529653 |
| 167562 | GIM_Reject, |
| 167563 | // Label 7855: @529654 |
| 167564 | GIM_Try, /*On fail goto*//*Label 7860*/ GIMT_Encode4(529768), |
| 167565 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167566 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167567 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167568 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167569 | GIM_Try, /*On fail goto*//*Label 7861*/ GIMT_Encode4(529721), // Rule ID 4841 // |
| 167570 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167572 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_IDXEN), |
| 167574 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167575 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167576 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167578 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167579 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167580 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167581 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167582 | GIR_RootConstrainSelectedInstOperands, |
| 167583 | // GIR_Coverage, 4841, |
| 167584 | GIR_EraseRootFromParent_Done, |
| 167585 | // Label 7861: @529721 |
| 167586 | GIM_Try, /*On fail goto*//*Label 7862*/ GIMT_Encode4(529767), // Rule ID 4845 // |
| 167587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167588 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_IDXEN), |
| 167590 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167591 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167592 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167593 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167594 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167595 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167596 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167597 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167598 | GIR_RootConstrainSelectedInstOperands, |
| 167599 | // GIR_Coverage, 4845, |
| 167600 | GIR_EraseRootFromParent_Done, |
| 167601 | // Label 7862: @529767 |
| 167602 | GIM_Reject, |
| 167603 | // Label 7860: @529768 |
| 167604 | GIM_Try, /*On fail goto*//*Label 7863*/ GIMT_Encode4(529962), |
| 167605 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167606 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167607 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167608 | GIM_Try, /*On fail goto*//*Label 7864*/ GIMT_Encode4(529873), // Rule ID 4842 // |
| 167609 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167611 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167612 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167613 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167614 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167615 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167616 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167617 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167618 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167619 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167620 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167621 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167622 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_BOTHEN), |
| 167623 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167624 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167625 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167626 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167627 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167628 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167629 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167630 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167631 | GIR_RootConstrainSelectedInstOperands, |
| 167632 | // GIR_Coverage, 4842, |
| 167633 | GIR_EraseRootFromParent_Done, |
| 167634 | // Label 7864: @529873 |
| 167635 | GIM_Try, /*On fail goto*//*Label 7865*/ GIMT_Encode4(529961), // Rule ID 4846 // |
| 167636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167637 | // (SIbuffer_load_ubyte_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167638 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167639 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167640 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167641 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167642 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167643 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167644 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167645 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167646 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167647 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167648 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_UBYTE_TFE_VBUFFER_BOTHEN), |
| 167649 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167650 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167651 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167652 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167653 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167654 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167655 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167656 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167657 | GIR_RootConstrainSelectedInstOperands, |
| 167658 | // GIR_Coverage, 4846, |
| 167659 | GIR_EraseRootFromParent_Done, |
| 167660 | // Label 7865: @529961 |
| 167661 | GIM_Reject, |
| 167662 | // Label 7863: @529962 |
| 167663 | GIM_Reject, |
| 167664 | // Label 7854: @529963 |
| 167665 | GIM_Reject, |
| 167666 | // Label 136: @529964 |
| 167667 | GIM_Try, /*On fail goto*//*Label 7866*/ GIMT_Encode4(530569), |
| 167668 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 167669 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 167670 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 167671 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 167672 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 167673 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 167674 | GIM_Try, /*On fail goto*//*Label 7867*/ GIMT_Encode4(530260), |
| 167675 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167676 | GIM_Try, /*On fail goto*//*Label 7868*/ GIMT_Encode4(530065), // Rule ID 4783 // |
| 167677 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167678 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167679 | // MIs[0] offset |
| 167680 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167681 | // MIs[0] auxiliary |
| 167682 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167683 | // MIs[0] Operand 7 |
| 167684 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167685 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167686 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFSET), |
| 167688 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167689 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167691 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167692 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167693 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167694 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167695 | GIR_RootConstrainSelectedInstOperands, |
| 167696 | // GIR_Coverage, 4783, |
| 167697 | GIR_EraseRootFromParent_Done, |
| 167698 | // Label 7868: @530065 |
| 167699 | GIM_Try, /*On fail goto*//*Label 7869*/ GIMT_Encode4(530130), // Rule ID 4787 // |
| 167700 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167701 | // MIs[0] offset |
| 167702 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167703 | // MIs[0] auxiliary |
| 167704 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167705 | // MIs[0] Operand 7 |
| 167706 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167707 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167708 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167709 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFSET), |
| 167710 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167711 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167712 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167713 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167714 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167715 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167716 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167717 | GIR_RootConstrainSelectedInstOperands, |
| 167718 | // GIR_Coverage, 4787, |
| 167719 | GIR_EraseRootFromParent_Done, |
| 167720 | // Label 7869: @530130 |
| 167721 | GIM_Try, /*On fail goto*//*Label 7870*/ GIMT_Encode4(530196), // Rule ID 4784 // |
| 167722 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167723 | // MIs[0] offset |
| 167724 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167725 | // MIs[0] auxiliary |
| 167726 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167727 | // MIs[0] Operand 7 |
| 167728 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167729 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167730 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_OFFEN), |
| 167732 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167733 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167734 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167736 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167737 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167738 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167739 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167740 | GIR_RootConstrainSelectedInstOperands, |
| 167741 | // GIR_Coverage, 4784, |
| 167742 | GIR_EraseRootFromParent_Done, |
| 167743 | // Label 7870: @530196 |
| 167744 | GIM_Try, /*On fail goto*//*Label 7871*/ GIMT_Encode4(530259), // Rule ID 4788 // |
| 167745 | // MIs[0] offset |
| 167746 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167747 | // MIs[0] auxiliary |
| 167748 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167749 | // MIs[0] Operand 7 |
| 167750 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167752 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_OFFEN), |
| 167754 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167755 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167756 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167757 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167758 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167759 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167760 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167761 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167762 | GIR_RootConstrainSelectedInstOperands, |
| 167763 | // GIR_Coverage, 4788, |
| 167764 | GIR_EraseRootFromParent_Done, |
| 167765 | // Label 7871: @530259 |
| 167766 | GIM_Reject, |
| 167767 | // Label 7867: @530260 |
| 167768 | GIM_Try, /*On fail goto*//*Label 7872*/ GIMT_Encode4(530374), |
| 167769 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167770 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167772 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167773 | GIM_Try, /*On fail goto*//*Label 7873*/ GIMT_Encode4(530327), // Rule ID 4785 // |
| 167774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167775 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167776 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167777 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_IDXEN), |
| 167778 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167779 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167780 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167781 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167782 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167784 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167785 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167786 | GIR_RootConstrainSelectedInstOperands, |
| 167787 | // GIR_Coverage, 4785, |
| 167788 | GIR_EraseRootFromParent_Done, |
| 167789 | // Label 7873: @530327 |
| 167790 | GIM_Try, /*On fail goto*//*Label 7874*/ GIMT_Encode4(530373), // Rule ID 4789 // |
| 167791 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167792 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167793 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_IDXEN), |
| 167794 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167795 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167796 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167797 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167798 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167799 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167800 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167801 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167802 | GIR_RootConstrainSelectedInstOperands, |
| 167803 | // GIR_Coverage, 4789, |
| 167804 | GIR_EraseRootFromParent_Done, |
| 167805 | // Label 7874: @530373 |
| 167806 | GIM_Reject, |
| 167807 | // Label 7872: @530374 |
| 167808 | GIM_Try, /*On fail goto*//*Label 7875*/ GIMT_Encode4(530568), |
| 167809 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167810 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167811 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167812 | GIM_Try, /*On fail goto*//*Label 7876*/ GIMT_Encode4(530479), // Rule ID 4786 // |
| 167813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167814 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167815 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167816 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167817 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167818 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167819 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167820 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167821 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167822 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167823 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167824 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167825 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167826 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_BOTHEN), |
| 167827 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167828 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167829 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167830 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167831 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167832 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167833 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167834 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167835 | GIR_RootConstrainSelectedInstOperands, |
| 167836 | // GIR_Coverage, 4786, |
| 167837 | GIR_EraseRootFromParent_Done, |
| 167838 | // Label 7876: @530479 |
| 167839 | GIM_Try, /*On fail goto*//*Label 7877*/ GIMT_Encode4(530567), // Rule ID 4790 // |
| 167840 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167841 | // (SIbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167842 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 167843 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 167844 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 167845 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 167846 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 167847 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 167848 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 167849 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 167850 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167851 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 167852 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_VBUFFER_BOTHEN), |
| 167853 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167854 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 167855 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167857 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167858 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167859 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167860 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167861 | GIR_RootConstrainSelectedInstOperands, |
| 167862 | // GIR_Coverage, 4790, |
| 167863 | GIR_EraseRootFromParent_Done, |
| 167864 | // Label 7877: @530567 |
| 167865 | GIM_Reject, |
| 167866 | // Label 7875: @530568 |
| 167867 | GIM_Reject, |
| 167868 | // Label 7866: @530569 |
| 167869 | GIM_Reject, |
| 167870 | // Label 137: @530570 |
| 167871 | GIM_Try, /*On fail goto*//*Label 7878*/ GIMT_Encode4(531175), |
| 167872 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s32, |
| 167873 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 167874 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 167875 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 167876 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 167877 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 167878 | GIM_Try, /*On fail goto*//*Label 7879*/ GIMT_Encode4(530866), |
| 167879 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 167880 | GIM_Try, /*On fail goto*//*Label 7880*/ GIMT_Encode4(530671), // Rule ID 4847 // |
| 167881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167883 | // MIs[0] offset |
| 167884 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167885 | // MIs[0] auxiliary |
| 167886 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167887 | // MIs[0] Operand 7 |
| 167888 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167890 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_TFE_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFSET), |
| 167892 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167893 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167895 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167896 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167897 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167898 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167899 | GIR_RootConstrainSelectedInstOperands, |
| 167900 | // GIR_Coverage, 4847, |
| 167901 | GIR_EraseRootFromParent_Done, |
| 167902 | // Label 7880: @530671 |
| 167903 | GIM_Try, /*On fail goto*//*Label 7881*/ GIMT_Encode4(530736), // Rule ID 4851 // |
| 167904 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167905 | // MIs[0] offset |
| 167906 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167907 | // MIs[0] auxiliary |
| 167908 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167909 | // MIs[0] Operand 7 |
| 167910 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167912 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFSET), |
| 167914 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167915 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167916 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167917 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167918 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167919 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167920 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167921 | GIR_RootConstrainSelectedInstOperands, |
| 167922 | // GIR_Coverage, 4851, |
| 167923 | GIR_EraseRootFromParent_Done, |
| 167924 | // Label 7881: @530736 |
| 167925 | GIM_Try, /*On fail goto*//*Label 7882*/ GIMT_Encode4(530802), // Rule ID 4848 // |
| 167926 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167927 | // MIs[0] offset |
| 167928 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167929 | // MIs[0] auxiliary |
| 167930 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167931 | // MIs[0] Operand 7 |
| 167932 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167934 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_TFE_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_OFFEN), |
| 167936 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167937 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167938 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167940 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167942 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167944 | GIR_RootConstrainSelectedInstOperands, |
| 167945 | // GIR_Coverage, 4848, |
| 167946 | GIR_EraseRootFromParent_Done, |
| 167947 | // Label 7882: @530802 |
| 167948 | GIM_Try, /*On fail goto*//*Label 7883*/ GIMT_Encode4(530865), // Rule ID 4852 // |
| 167949 | // MIs[0] offset |
| 167950 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167951 | // MIs[0] auxiliary |
| 167952 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167953 | // MIs[0] Operand 7 |
| 167954 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 167955 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167956 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_OFFEN), |
| 167958 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167959 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 167960 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167962 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167963 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167964 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167965 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167966 | GIR_RootConstrainSelectedInstOperands, |
| 167967 | // GIR_Coverage, 4852, |
| 167968 | GIR_EraseRootFromParent_Done, |
| 167969 | // Label 7883: @530865 |
| 167970 | GIM_Reject, |
| 167971 | // Label 7879: @530866 |
| 167972 | GIM_Try, /*On fail goto*//*Label 7884*/ GIMT_Encode4(530980), |
| 167973 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 167974 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 167975 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 167976 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 167977 | GIM_Try, /*On fail goto*//*Label 7885*/ GIMT_Encode4(530933), // Rule ID 4849 // |
| 167978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 167979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167980 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_TFE_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167981 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_IDXEN), |
| 167982 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167983 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 167984 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 167985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 167986 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 167987 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 167988 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 167989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 167990 | GIR_RootConstrainSelectedInstOperands, |
| 167991 | // GIR_Coverage, 4849, |
| 167992 | GIR_EraseRootFromParent_Done, |
| 167993 | // Label 7885: @530933 |
| 167994 | GIM_Try, /*On fail goto*//*Label 7886*/ GIMT_Encode4(530979), // Rule ID 4853 // |
| 167995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 167996 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 167997 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_IDXEN), |
| 167998 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 167999 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168000 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168001 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168002 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168003 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168004 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168005 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168006 | GIR_RootConstrainSelectedInstOperands, |
| 168007 | // GIR_Coverage, 4853, |
| 168008 | GIR_EraseRootFromParent_Done, |
| 168009 | // Label 7886: @530979 |
| 168010 | GIM_Reject, |
| 168011 | // Label 7884: @530980 |
| 168012 | GIM_Try, /*On fail goto*//*Label 7887*/ GIMT_Encode4(531174), |
| 168013 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168014 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168015 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168016 | GIM_Try, /*On fail goto*//*Label 7888*/ GIMT_Encode4(531085), // Rule ID 4850 // |
| 168017 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168018 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168019 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_TFE_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168020 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168021 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168022 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168023 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168024 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168025 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168026 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168027 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168028 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168029 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_BOTHEN), |
| 168031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 168032 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168033 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168035 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168036 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168037 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168038 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168039 | GIR_RootConstrainSelectedInstOperands, |
| 168040 | // GIR_Coverage, 4850, |
| 168041 | GIR_EraseRootFromParent_Done, |
| 168042 | // Label 7888: @531085 |
| 168043 | GIM_Try, /*On fail goto*//*Label 7889*/ GIMT_Encode4(531173), // Rule ID 4854 // |
| 168044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168045 | // (SIbuffer_load_ushort_tfe:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168049 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168050 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168051 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168052 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168053 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168055 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_LOAD_USHORT_TFE_VBUFFER_BOTHEN), |
| 168057 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 168058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168059 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168061 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168063 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168065 | GIR_RootConstrainSelectedInstOperands, |
| 168066 | // GIR_Coverage, 4854, |
| 168067 | GIR_EraseRootFromParent_Done, |
| 168068 | // Label 7889: @531173 |
| 168069 | GIM_Reject, |
| 168070 | // Label 7887: @531174 |
| 168071 | GIM_Reject, |
| 168072 | // Label 7878: @531175 |
| 168073 | GIM_Reject, |
| 168074 | // Label 138: @531176 |
| 168075 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(0), GIMT_Encode2(23), /*)*//*default:*//*Label 7904*/ GIMT_Encode4(547041), |
| 168076 | /*GILLT_p0s64*//*Label 7890*/ GIMT_Encode4(531279), GIMT_Encode4(0), |
| 168077 | /*GILLT_p2s32*//*Label 7891*/ GIMT_Encode4(531894), |
| 168078 | /*GILLT_p3s32*//*Label 7892*/ GIMT_Encode4(532509), GIMT_Encode4(0), |
| 168079 | /*GILLT_p5s32*//*Label 7893*/ GIMT_Encode4(533124), |
| 168080 | /*GILLT_p6s32*//*Label 7894*/ GIMT_Encode4(533739), GIMT_Encode4(0), GIMT_Encode4(0), |
| 168081 | /*GILLT_s32*//*Label 7895*/ GIMT_Encode4(534354), |
| 168082 | /*GILLT_s64*//*Label 7896*/ GIMT_Encode4(535565), |
| 168083 | /*GILLT_v2s16*//*Label 7897*/ GIMT_Encode4(536776), |
| 168084 | /*GILLT_v2s32*//*Label 7898*/ GIMT_Encode4(538583), |
| 168085 | /*GILLT_v2s64*//*Label 7899*/ GIMT_Encode4(539794), |
| 168086 | /*GILLT_v3s32*//*Label 7900*/ GIMT_Encode4(541005), GIMT_Encode4(0), |
| 168087 | /*GILLT_v4s16*//*Label 7901*/ GIMT_Encode4(542216), |
| 168088 | /*GILLT_v4s32*//*Label 7902*/ GIMT_Encode4(544023), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 168089 | /*GILLT_v8s16*//*Label 7903*/ GIMT_Encode4(545234), |
| 168090 | // Label 7890: @531279 |
| 168091 | GIM_Try, /*On fail goto*//*Label 7905*/ GIMT_Encode4(531893), |
| 168092 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 168093 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 168094 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 168095 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 168096 | GIM_Try, /*On fail goto*//*Label 7906*/ GIMT_Encode4(531368), // Rule ID 5127 // |
| 168097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168098 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168099 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168100 | // MIs[0] offset |
| 168101 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168102 | // MIs[0] auxiliary |
| 168103 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168104 | // MIs[0] Operand 7 |
| 168105 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168107 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 168109 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168110 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168111 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168112 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168113 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168114 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168115 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168116 | GIR_RootConstrainSelectedInstOperands, |
| 168117 | // GIR_Coverage, 5127, |
| 168118 | GIR_EraseRootFromParent_Done, |
| 168119 | // Label 7906: @531368 |
| 168120 | GIM_Try, /*On fail goto*//*Label 7907*/ GIMT_Encode4(531437), // Rule ID 5131 // |
| 168121 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168122 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168123 | // MIs[0] offset |
| 168124 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168125 | // MIs[0] auxiliary |
| 168126 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168127 | // MIs[0] Operand 7 |
| 168128 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168129 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168130 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168131 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 168132 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168133 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168134 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168135 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168136 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168137 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168139 | GIR_RootConstrainSelectedInstOperands, |
| 168140 | // GIR_Coverage, 5131, |
| 168141 | GIR_EraseRootFromParent_Done, |
| 168142 | // Label 7907: @531437 |
| 168143 | GIM_Try, /*On fail goto*//*Label 7908*/ GIMT_Encode4(531507), // Rule ID 5128 // |
| 168144 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168145 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168146 | // MIs[0] offset |
| 168147 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168148 | // MIs[0] auxiliary |
| 168149 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168150 | // MIs[0] Operand 7 |
| 168151 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168152 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168153 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168154 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 168155 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168156 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168157 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168158 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168159 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168160 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168161 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168162 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168163 | GIR_RootConstrainSelectedInstOperands, |
| 168164 | // GIR_Coverage, 5128, |
| 168165 | GIR_EraseRootFromParent_Done, |
| 168166 | // Label 7908: @531507 |
| 168167 | GIM_Try, /*On fail goto*//*Label 7909*/ GIMT_Encode4(531574), // Rule ID 5132 // |
| 168168 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168169 | // MIs[0] offset |
| 168170 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168171 | // MIs[0] auxiliary |
| 168172 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168173 | // MIs[0] Operand 7 |
| 168174 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168175 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168176 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168177 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 168178 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168179 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168180 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168181 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168182 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168183 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168184 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168185 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168186 | GIR_RootConstrainSelectedInstOperands, |
| 168187 | // GIR_Coverage, 5132, |
| 168188 | GIR_EraseRootFromParent_Done, |
| 168189 | // Label 7909: @531574 |
| 168190 | GIM_Try, /*On fail goto*//*Label 7910*/ GIMT_Encode4(531636), // Rule ID 5129 // |
| 168191 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168192 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168193 | // MIs[0] offset |
| 168194 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168195 | // MIs[0] auxiliary |
| 168196 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168197 | // MIs[0] Operand 7 |
| 168198 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168199 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168200 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168201 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 168202 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168203 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168204 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168205 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168206 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168207 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168208 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168210 | GIR_RootConstrainSelectedInstOperands, |
| 168211 | // GIR_Coverage, 5129, |
| 168212 | GIR_EraseRootFromParent_Done, |
| 168213 | // Label 7910: @531636 |
| 168214 | GIM_Try, /*On fail goto*//*Label 7911*/ GIMT_Encode4(531695), // Rule ID 5133 // |
| 168215 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168216 | // MIs[0] offset |
| 168217 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168218 | // MIs[0] auxiliary |
| 168219 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168220 | // MIs[0] Operand 7 |
| 168221 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168222 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168223 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168224 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 168225 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168226 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168227 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168228 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168229 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168230 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168231 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168232 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168233 | GIR_RootConstrainSelectedInstOperands, |
| 168234 | // GIR_Coverage, 5133, |
| 168235 | GIR_EraseRootFromParent_Done, |
| 168236 | // Label 7911: @531695 |
| 168237 | GIM_Try, /*On fail goto*//*Label 7912*/ GIMT_Encode4(531795), // Rule ID 5130 // |
| 168238 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168239 | // MIs[0] offset |
| 168240 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168241 | // MIs[0] auxiliary |
| 168242 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168243 | // MIs[0] Operand 7 |
| 168244 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168245 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168246 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168247 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168248 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168249 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168250 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168251 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168252 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168253 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168254 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168255 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168256 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168257 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 168258 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168259 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168260 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168261 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168262 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168263 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168264 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168265 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168266 | GIR_RootConstrainSelectedInstOperands, |
| 168267 | // GIR_Coverage, 5130, |
| 168268 | GIR_EraseRootFromParent_Done, |
| 168269 | // Label 7912: @531795 |
| 168270 | GIM_Try, /*On fail goto*//*Label 7913*/ GIMT_Encode4(531892), // Rule ID 5134 // |
| 168271 | // MIs[0] offset |
| 168272 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168273 | // MIs[0] auxiliary |
| 168274 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168275 | // MIs[0] Operand 7 |
| 168276 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168277 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168278 | // (SIbuffer_store p0:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168279 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168280 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168281 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168282 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168283 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168284 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168285 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168286 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168287 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168288 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168289 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 168290 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168291 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168292 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168293 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168294 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168295 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168296 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168297 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168298 | GIR_RootConstrainSelectedInstOperands, |
| 168299 | // GIR_Coverage, 5134, |
| 168300 | GIR_EraseRootFromParent_Done, |
| 168301 | // Label 7913: @531892 |
| 168302 | GIM_Reject, |
| 168303 | // Label 7905: @531893 |
| 168304 | GIM_Reject, |
| 168305 | // Label 7891: @531894 |
| 168306 | GIM_Try, /*On fail goto*//*Label 7914*/ GIMT_Encode4(532508), |
| 168307 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 168308 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 168309 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 168310 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 168311 | GIM_Try, /*On fail goto*//*Label 7915*/ GIMT_Encode4(531983), // Rule ID 5063 // |
| 168312 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168313 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168314 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168315 | // MIs[0] offset |
| 168316 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168317 | // MIs[0] auxiliary |
| 168318 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168319 | // MIs[0] Operand 7 |
| 168320 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168322 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 168324 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168325 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168326 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168327 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168328 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168329 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168330 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168331 | GIR_RootConstrainSelectedInstOperands, |
| 168332 | // GIR_Coverage, 5063, |
| 168333 | GIR_EraseRootFromParent_Done, |
| 168334 | // Label 7915: @531983 |
| 168335 | GIM_Try, /*On fail goto*//*Label 7916*/ GIMT_Encode4(532052), // Rule ID 5067 // |
| 168336 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168337 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168338 | // MIs[0] offset |
| 168339 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168340 | // MIs[0] auxiliary |
| 168341 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168342 | // MIs[0] Operand 7 |
| 168343 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168345 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 168347 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168348 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168350 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168351 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168354 | GIR_RootConstrainSelectedInstOperands, |
| 168355 | // GIR_Coverage, 5067, |
| 168356 | GIR_EraseRootFromParent_Done, |
| 168357 | // Label 7916: @532052 |
| 168358 | GIM_Try, /*On fail goto*//*Label 7917*/ GIMT_Encode4(532122), // Rule ID 5064 // |
| 168359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168360 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168361 | // MIs[0] offset |
| 168362 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168363 | // MIs[0] auxiliary |
| 168364 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168365 | // MIs[0] Operand 7 |
| 168366 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168367 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168368 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168369 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 168370 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168371 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168372 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168374 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168375 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168378 | GIR_RootConstrainSelectedInstOperands, |
| 168379 | // GIR_Coverage, 5064, |
| 168380 | GIR_EraseRootFromParent_Done, |
| 168381 | // Label 7917: @532122 |
| 168382 | GIM_Try, /*On fail goto*//*Label 7918*/ GIMT_Encode4(532189), // Rule ID 5068 // |
| 168383 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168384 | // MIs[0] offset |
| 168385 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168386 | // MIs[0] auxiliary |
| 168387 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168388 | // MIs[0] Operand 7 |
| 168389 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168390 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168391 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168392 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 168393 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168394 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168395 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168396 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168397 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168398 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168400 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168401 | GIR_RootConstrainSelectedInstOperands, |
| 168402 | // GIR_Coverage, 5068, |
| 168403 | GIR_EraseRootFromParent_Done, |
| 168404 | // Label 7918: @532189 |
| 168405 | GIM_Try, /*On fail goto*//*Label 7919*/ GIMT_Encode4(532251), // Rule ID 5065 // |
| 168406 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168407 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168408 | // MIs[0] offset |
| 168409 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168410 | // MIs[0] auxiliary |
| 168411 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168412 | // MIs[0] Operand 7 |
| 168413 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168415 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 168417 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168418 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168419 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168420 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168421 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168422 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168423 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168424 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168425 | GIR_RootConstrainSelectedInstOperands, |
| 168426 | // GIR_Coverage, 5065, |
| 168427 | GIR_EraseRootFromParent_Done, |
| 168428 | // Label 7919: @532251 |
| 168429 | GIM_Try, /*On fail goto*//*Label 7920*/ GIMT_Encode4(532310), // Rule ID 5069 // |
| 168430 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168431 | // MIs[0] offset |
| 168432 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168433 | // MIs[0] auxiliary |
| 168434 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168435 | // MIs[0] Operand 7 |
| 168436 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168437 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168438 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168439 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 168440 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168441 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168442 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168444 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168445 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168446 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168447 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168448 | GIR_RootConstrainSelectedInstOperands, |
| 168449 | // GIR_Coverage, 5069, |
| 168450 | GIR_EraseRootFromParent_Done, |
| 168451 | // Label 7920: @532310 |
| 168452 | GIM_Try, /*On fail goto*//*Label 7921*/ GIMT_Encode4(532410), // Rule ID 5066 // |
| 168453 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168454 | // MIs[0] offset |
| 168455 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168456 | // MIs[0] auxiliary |
| 168457 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168458 | // MIs[0] Operand 7 |
| 168459 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168460 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168461 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168462 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168463 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168464 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168465 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168466 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168467 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168468 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168469 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168470 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168471 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168472 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 168473 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168474 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168475 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168476 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168477 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168478 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168480 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168481 | GIR_RootConstrainSelectedInstOperands, |
| 168482 | // GIR_Coverage, 5066, |
| 168483 | GIR_EraseRootFromParent_Done, |
| 168484 | // Label 7921: @532410 |
| 168485 | GIM_Try, /*On fail goto*//*Label 7922*/ GIMT_Encode4(532507), // Rule ID 5070 // |
| 168486 | // MIs[0] offset |
| 168487 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168488 | // MIs[0] auxiliary |
| 168489 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168490 | // MIs[0] Operand 7 |
| 168491 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168492 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168493 | // (SIbuffer_store p2:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168494 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168495 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168496 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168497 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168498 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168499 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168500 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168501 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168502 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168503 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 168505 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168506 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168507 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168509 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168510 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168513 | GIR_RootConstrainSelectedInstOperands, |
| 168514 | // GIR_Coverage, 5070, |
| 168515 | GIR_EraseRootFromParent_Done, |
| 168516 | // Label 7922: @532507 |
| 168517 | GIM_Reject, |
| 168518 | // Label 7914: @532508 |
| 168519 | GIM_Reject, |
| 168520 | // Label 7892: @532509 |
| 168521 | GIM_Try, /*On fail goto*//*Label 7923*/ GIMT_Encode4(533123), |
| 168522 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 168523 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 168524 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 168525 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 168526 | GIM_Try, /*On fail goto*//*Label 7924*/ GIMT_Encode4(532598), // Rule ID 5071 // |
| 168527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168528 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168529 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168530 | // MIs[0] offset |
| 168531 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168532 | // MIs[0] auxiliary |
| 168533 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168534 | // MIs[0] Operand 7 |
| 168535 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168536 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168537 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 168539 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168540 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168542 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168543 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168546 | GIR_RootConstrainSelectedInstOperands, |
| 168547 | // GIR_Coverage, 5071, |
| 168548 | GIR_EraseRootFromParent_Done, |
| 168549 | // Label 7924: @532598 |
| 168550 | GIM_Try, /*On fail goto*//*Label 7925*/ GIMT_Encode4(532667), // Rule ID 5075 // |
| 168551 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168552 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168553 | // MIs[0] offset |
| 168554 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168555 | // MIs[0] auxiliary |
| 168556 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168557 | // MIs[0] Operand 7 |
| 168558 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168560 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 168562 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168563 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168565 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168566 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168569 | GIR_RootConstrainSelectedInstOperands, |
| 168570 | // GIR_Coverage, 5075, |
| 168571 | GIR_EraseRootFromParent_Done, |
| 168572 | // Label 7925: @532667 |
| 168573 | GIM_Try, /*On fail goto*//*Label 7926*/ GIMT_Encode4(532737), // Rule ID 5072 // |
| 168574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168575 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168576 | // MIs[0] offset |
| 168577 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168578 | // MIs[0] auxiliary |
| 168579 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168580 | // MIs[0] Operand 7 |
| 168581 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168582 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168583 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168584 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 168585 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168586 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168587 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168588 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168589 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168591 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168592 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168593 | GIR_RootConstrainSelectedInstOperands, |
| 168594 | // GIR_Coverage, 5072, |
| 168595 | GIR_EraseRootFromParent_Done, |
| 168596 | // Label 7926: @532737 |
| 168597 | GIM_Try, /*On fail goto*//*Label 7927*/ GIMT_Encode4(532804), // Rule ID 5076 // |
| 168598 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168599 | // MIs[0] offset |
| 168600 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168601 | // MIs[0] auxiliary |
| 168602 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168603 | // MIs[0] Operand 7 |
| 168604 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168605 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168606 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 168608 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168609 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168610 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168612 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168613 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168614 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168615 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168616 | GIR_RootConstrainSelectedInstOperands, |
| 168617 | // GIR_Coverage, 5076, |
| 168618 | GIR_EraseRootFromParent_Done, |
| 168619 | // Label 7927: @532804 |
| 168620 | GIM_Try, /*On fail goto*//*Label 7928*/ GIMT_Encode4(532866), // Rule ID 5073 // |
| 168621 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168622 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168623 | // MIs[0] offset |
| 168624 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168625 | // MIs[0] auxiliary |
| 168626 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168627 | // MIs[0] Operand 7 |
| 168628 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168629 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168630 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 168632 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168633 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168634 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168636 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168637 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168638 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168640 | GIR_RootConstrainSelectedInstOperands, |
| 168641 | // GIR_Coverage, 5073, |
| 168642 | GIR_EraseRootFromParent_Done, |
| 168643 | // Label 7928: @532866 |
| 168644 | GIM_Try, /*On fail goto*//*Label 7929*/ GIMT_Encode4(532925), // Rule ID 5077 // |
| 168645 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168646 | // MIs[0] offset |
| 168647 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168648 | // MIs[0] auxiliary |
| 168649 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168650 | // MIs[0] Operand 7 |
| 168651 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168652 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168653 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 168655 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168656 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168657 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168659 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168660 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168661 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168662 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168663 | GIR_RootConstrainSelectedInstOperands, |
| 168664 | // GIR_Coverage, 5077, |
| 168665 | GIR_EraseRootFromParent_Done, |
| 168666 | // Label 7929: @532925 |
| 168667 | GIM_Try, /*On fail goto*//*Label 7930*/ GIMT_Encode4(533025), // Rule ID 5074 // |
| 168668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168669 | // MIs[0] offset |
| 168670 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168671 | // MIs[0] auxiliary |
| 168672 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168673 | // MIs[0] Operand 7 |
| 168674 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168676 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168677 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168678 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168679 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168680 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168681 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168682 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168683 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168684 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168685 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168686 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168687 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 168688 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168689 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168690 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168691 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168692 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168693 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168694 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168696 | GIR_RootConstrainSelectedInstOperands, |
| 168697 | // GIR_Coverage, 5074, |
| 168698 | GIR_EraseRootFromParent_Done, |
| 168699 | // Label 7930: @533025 |
| 168700 | GIM_Try, /*On fail goto*//*Label 7931*/ GIMT_Encode4(533122), // Rule ID 5078 // |
| 168701 | // MIs[0] offset |
| 168702 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168703 | // MIs[0] auxiliary |
| 168704 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168705 | // MIs[0] Operand 7 |
| 168706 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168707 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168708 | // (SIbuffer_store p3:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168709 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168710 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168711 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168712 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168713 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168714 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168715 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168717 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168718 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168719 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 168720 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168721 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168722 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168724 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168725 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168726 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168727 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168728 | GIR_RootConstrainSelectedInstOperands, |
| 168729 | // GIR_Coverage, 5078, |
| 168730 | GIR_EraseRootFromParent_Done, |
| 168731 | // Label 7931: @533122 |
| 168732 | GIM_Reject, |
| 168733 | // Label 7923: @533123 |
| 168734 | GIM_Reject, |
| 168735 | // Label 7893: @533124 |
| 168736 | GIM_Try, /*On fail goto*//*Label 7932*/ GIMT_Encode4(533738), |
| 168737 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 168738 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 168739 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 168740 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 168741 | GIM_Try, /*On fail goto*//*Label 7933*/ GIMT_Encode4(533213), // Rule ID 5079 // |
| 168742 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168743 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168744 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168745 | // MIs[0] offset |
| 168746 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168747 | // MIs[0] auxiliary |
| 168748 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168749 | // MIs[0] Operand 7 |
| 168750 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168751 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168752 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168753 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 168754 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168755 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168757 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168758 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168759 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168760 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168761 | GIR_RootConstrainSelectedInstOperands, |
| 168762 | // GIR_Coverage, 5079, |
| 168763 | GIR_EraseRootFromParent_Done, |
| 168764 | // Label 7933: @533213 |
| 168765 | GIM_Try, /*On fail goto*//*Label 7934*/ GIMT_Encode4(533282), // Rule ID 5083 // |
| 168766 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168767 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168768 | // MIs[0] offset |
| 168769 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168770 | // MIs[0] auxiliary |
| 168771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168772 | // MIs[0] Operand 7 |
| 168773 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168775 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 168777 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168778 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168780 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168781 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168783 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168784 | GIR_RootConstrainSelectedInstOperands, |
| 168785 | // GIR_Coverage, 5083, |
| 168786 | GIR_EraseRootFromParent_Done, |
| 168787 | // Label 7934: @533282 |
| 168788 | GIM_Try, /*On fail goto*//*Label 7935*/ GIMT_Encode4(533352), // Rule ID 5080 // |
| 168789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168791 | // MIs[0] offset |
| 168792 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168793 | // MIs[0] auxiliary |
| 168794 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168795 | // MIs[0] Operand 7 |
| 168796 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168797 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168798 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 168800 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168801 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168802 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168804 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168805 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168806 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168807 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168808 | GIR_RootConstrainSelectedInstOperands, |
| 168809 | // GIR_Coverage, 5080, |
| 168810 | GIR_EraseRootFromParent_Done, |
| 168811 | // Label 7935: @533352 |
| 168812 | GIM_Try, /*On fail goto*//*Label 7936*/ GIMT_Encode4(533419), // Rule ID 5084 // |
| 168813 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168814 | // MIs[0] offset |
| 168815 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168816 | // MIs[0] auxiliary |
| 168817 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168818 | // MIs[0] Operand 7 |
| 168819 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168821 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 168823 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168824 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 168825 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168827 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168831 | GIR_RootConstrainSelectedInstOperands, |
| 168832 | // GIR_Coverage, 5084, |
| 168833 | GIR_EraseRootFromParent_Done, |
| 168834 | // Label 7936: @533419 |
| 168835 | GIM_Try, /*On fail goto*//*Label 7937*/ GIMT_Encode4(533481), // Rule ID 5081 // |
| 168836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168837 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168838 | // MIs[0] offset |
| 168839 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168840 | // MIs[0] auxiliary |
| 168841 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168842 | // MIs[0] Operand 7 |
| 168843 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168844 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168845 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168846 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 168847 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168848 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168849 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168850 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168851 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168852 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168853 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168854 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168855 | GIR_RootConstrainSelectedInstOperands, |
| 168856 | // GIR_Coverage, 5081, |
| 168857 | GIR_EraseRootFromParent_Done, |
| 168858 | // Label 7937: @533481 |
| 168859 | GIM_Try, /*On fail goto*//*Label 7938*/ GIMT_Encode4(533540), // Rule ID 5085 // |
| 168860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168861 | // MIs[0] offset |
| 168862 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168863 | // MIs[0] auxiliary |
| 168864 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168865 | // MIs[0] Operand 7 |
| 168866 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168868 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 168870 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168871 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 168872 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168874 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168875 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168876 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168877 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168878 | GIR_RootConstrainSelectedInstOperands, |
| 168879 | // GIR_Coverage, 5085, |
| 168880 | GIR_EraseRootFromParent_Done, |
| 168881 | // Label 7938: @533540 |
| 168882 | GIM_Try, /*On fail goto*//*Label 7939*/ GIMT_Encode4(533640), // Rule ID 5082 // |
| 168883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168884 | // MIs[0] offset |
| 168885 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168886 | // MIs[0] auxiliary |
| 168887 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168888 | // MIs[0] Operand 7 |
| 168889 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168890 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168891 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168892 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168893 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168894 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168895 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168896 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168897 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168898 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168899 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168900 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168901 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168902 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 168903 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168904 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168905 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168906 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168907 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168908 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168909 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168910 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168911 | GIR_RootConstrainSelectedInstOperands, |
| 168912 | // GIR_Coverage, 5082, |
| 168913 | GIR_EraseRootFromParent_Done, |
| 168914 | // Label 7939: @533640 |
| 168915 | GIM_Try, /*On fail goto*//*Label 7940*/ GIMT_Encode4(533737), // Rule ID 5086 // |
| 168916 | // MIs[0] offset |
| 168917 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168918 | // MIs[0] auxiliary |
| 168919 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168920 | // MIs[0] Operand 7 |
| 168921 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 168922 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168923 | // (SIbuffer_store p5:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168924 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 168925 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 168926 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 168927 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 168928 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 168929 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 168930 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 168931 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 168932 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168933 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 168934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 168935 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168936 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 168937 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168939 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168940 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168942 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168943 | GIR_RootConstrainSelectedInstOperands, |
| 168944 | // GIR_Coverage, 5086, |
| 168945 | GIR_EraseRootFromParent_Done, |
| 168946 | // Label 7940: @533737 |
| 168947 | GIM_Reject, |
| 168948 | // Label 7932: @533738 |
| 168949 | GIM_Reject, |
| 168950 | // Label 7894: @533739 |
| 168951 | GIM_Try, /*On fail goto*//*Label 7941*/ GIMT_Encode4(534353), |
| 168952 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 168953 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 168954 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 168955 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 168956 | GIM_Try, /*On fail goto*//*Label 7942*/ GIMT_Encode4(533828), // Rule ID 5087 // |
| 168957 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 168958 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168959 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168960 | // MIs[0] offset |
| 168961 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168962 | // MIs[0] auxiliary |
| 168963 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168964 | // MIs[0] Operand 7 |
| 168965 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168966 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168967 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168968 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 168969 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168970 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168971 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168972 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168973 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168974 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168975 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168976 | GIR_RootConstrainSelectedInstOperands, |
| 168977 | // GIR_Coverage, 5087, |
| 168978 | GIR_EraseRootFromParent_Done, |
| 168979 | // Label 7942: @533828 |
| 168980 | GIM_Try, /*On fail goto*//*Label 7943*/ GIMT_Encode4(533897), // Rule ID 5091 // |
| 168981 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 168982 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 168983 | // MIs[0] offset |
| 168984 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 168985 | // MIs[0] auxiliary |
| 168986 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 168987 | // MIs[0] Operand 7 |
| 168988 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 168989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 168990 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 168991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 168992 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 168993 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 168994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 168995 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 168996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 168997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 168998 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 168999 | GIR_RootConstrainSelectedInstOperands, |
| 169000 | // GIR_Coverage, 5091, |
| 169001 | GIR_EraseRootFromParent_Done, |
| 169002 | // Label 7943: @533897 |
| 169003 | GIM_Try, /*On fail goto*//*Label 7944*/ GIMT_Encode4(533967), // Rule ID 5088 // |
| 169004 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169005 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169006 | // MIs[0] offset |
| 169007 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169008 | // MIs[0] auxiliary |
| 169009 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169010 | // MIs[0] Operand 7 |
| 169011 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169013 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 169015 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169016 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169017 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169018 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169019 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169020 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169021 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169023 | GIR_RootConstrainSelectedInstOperands, |
| 169024 | // GIR_Coverage, 5088, |
| 169025 | GIR_EraseRootFromParent_Done, |
| 169026 | // Label 7944: @533967 |
| 169027 | GIM_Try, /*On fail goto*//*Label 7945*/ GIMT_Encode4(534034), // Rule ID 5092 // |
| 169028 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169029 | // MIs[0] offset |
| 169030 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169031 | // MIs[0] auxiliary |
| 169032 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169033 | // MIs[0] Operand 7 |
| 169034 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169036 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 169038 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169039 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169040 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169042 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169043 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169044 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169046 | GIR_RootConstrainSelectedInstOperands, |
| 169047 | // GIR_Coverage, 5092, |
| 169048 | GIR_EraseRootFromParent_Done, |
| 169049 | // Label 7945: @534034 |
| 169050 | GIM_Try, /*On fail goto*//*Label 7946*/ GIMT_Encode4(534096), // Rule ID 5089 // |
| 169051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169052 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169053 | // MIs[0] offset |
| 169054 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169055 | // MIs[0] auxiliary |
| 169056 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169057 | // MIs[0] Operand 7 |
| 169058 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169060 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 169062 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169063 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169064 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169066 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169067 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169068 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169070 | GIR_RootConstrainSelectedInstOperands, |
| 169071 | // GIR_Coverage, 5089, |
| 169072 | GIR_EraseRootFromParent_Done, |
| 169073 | // Label 7946: @534096 |
| 169074 | GIM_Try, /*On fail goto*//*Label 7947*/ GIMT_Encode4(534155), // Rule ID 5093 // |
| 169075 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169076 | // MIs[0] offset |
| 169077 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169078 | // MIs[0] auxiliary |
| 169079 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169080 | // MIs[0] Operand 7 |
| 169081 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169082 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169083 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169084 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 169085 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169086 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169087 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169089 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169090 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169091 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169092 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169093 | GIR_RootConstrainSelectedInstOperands, |
| 169094 | // GIR_Coverage, 5093, |
| 169095 | GIR_EraseRootFromParent_Done, |
| 169096 | // Label 7947: @534155 |
| 169097 | GIM_Try, /*On fail goto*//*Label 7948*/ GIMT_Encode4(534255), // Rule ID 5090 // |
| 169098 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169099 | // MIs[0] offset |
| 169100 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169101 | // MIs[0] auxiliary |
| 169102 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169103 | // MIs[0] Operand 7 |
| 169104 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169105 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169106 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169107 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169108 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169109 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169110 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169111 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169112 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169113 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169114 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169115 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169116 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 169118 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169119 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169120 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169122 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169123 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169125 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169126 | GIR_RootConstrainSelectedInstOperands, |
| 169127 | // GIR_Coverage, 5090, |
| 169128 | GIR_EraseRootFromParent_Done, |
| 169129 | // Label 7948: @534255 |
| 169130 | GIM_Try, /*On fail goto*//*Label 7949*/ GIMT_Encode4(534352), // Rule ID 5094 // |
| 169131 | // MIs[0] offset |
| 169132 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169133 | // MIs[0] auxiliary |
| 169134 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169135 | // MIs[0] Operand 7 |
| 169136 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169137 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169138 | // (SIbuffer_store p6:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169139 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169140 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169141 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169142 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169143 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169144 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169145 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169146 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169147 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169148 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 169150 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169151 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169152 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169154 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169155 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169158 | GIR_RootConstrainSelectedInstOperands, |
| 169159 | // GIR_Coverage, 5094, |
| 169160 | GIR_EraseRootFromParent_Done, |
| 169161 | // Label 7949: @534352 |
| 169162 | GIM_Reject, |
| 169163 | // Label 7941: @534353 |
| 169164 | GIM_Reject, |
| 169165 | // Label 7895: @534354 |
| 169166 | GIM_Try, /*On fail goto*//*Label 7950*/ GIMT_Encode4(535564), |
| 169167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 169168 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 169169 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 169170 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 169171 | GIM_Try, /*On fail goto*//*Label 7951*/ GIMT_Encode4(534443), // Rule ID 5023 // |
| 169172 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169173 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169174 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169175 | // MIs[0] offset |
| 169176 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169177 | // MIs[0] auxiliary |
| 169178 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169179 | // MIs[0] Operand 7 |
| 169180 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169181 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169182 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169183 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 169184 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169185 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169187 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169188 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169189 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169190 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169191 | GIR_RootConstrainSelectedInstOperands, |
| 169192 | // GIR_Coverage, 5023, |
| 169193 | GIR_EraseRootFromParent_Done, |
| 169194 | // Label 7951: @534443 |
| 169195 | GIM_Try, /*On fail goto*//*Label 7952*/ GIMT_Encode4(534512), // Rule ID 5027 // |
| 169196 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169197 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169198 | // MIs[0] offset |
| 169199 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169200 | // MIs[0] auxiliary |
| 169201 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169202 | // MIs[0] Operand 7 |
| 169203 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169204 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169205 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169206 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 169207 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169208 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169209 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169210 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169211 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169212 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169213 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169214 | GIR_RootConstrainSelectedInstOperands, |
| 169215 | // GIR_Coverage, 5027, |
| 169216 | GIR_EraseRootFromParent_Done, |
| 169217 | // Label 7952: @534512 |
| 169218 | GIM_Try, /*On fail goto*//*Label 7953*/ GIMT_Encode4(534584), // Rule ID 5031 // |
| 169219 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169220 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169221 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169222 | // MIs[0] offset |
| 169223 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169224 | // MIs[0] auxiliary |
| 169225 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169226 | // MIs[0] Operand 7 |
| 169227 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169228 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169229 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169230 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 169231 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169232 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169234 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169235 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169236 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169237 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169238 | GIR_RootConstrainSelectedInstOperands, |
| 169239 | // GIR_Coverage, 5031, |
| 169240 | GIR_EraseRootFromParent_Done, |
| 169241 | // Label 7953: @534584 |
| 169242 | GIM_Try, /*On fail goto*//*Label 7954*/ GIMT_Encode4(534653), // Rule ID 5035 // |
| 169243 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169244 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169245 | // MIs[0] offset |
| 169246 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169247 | // MIs[0] auxiliary |
| 169248 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169249 | // MIs[0] Operand 7 |
| 169250 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169251 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169252 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169253 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 169254 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169255 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169256 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169257 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169258 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169259 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169260 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169261 | GIR_RootConstrainSelectedInstOperands, |
| 169262 | // GIR_Coverage, 5035, |
| 169263 | GIR_EraseRootFromParent_Done, |
| 169264 | // Label 7954: @534653 |
| 169265 | GIM_Try, /*On fail goto*//*Label 7955*/ GIMT_Encode4(534723), // Rule ID 5024 // |
| 169266 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169267 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169268 | // MIs[0] offset |
| 169269 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169270 | // MIs[0] auxiliary |
| 169271 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169272 | // MIs[0] Operand 7 |
| 169273 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169274 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169275 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 169277 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169278 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169279 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169281 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169282 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169283 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169284 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169285 | GIR_RootConstrainSelectedInstOperands, |
| 169286 | // GIR_Coverage, 5024, |
| 169287 | GIR_EraseRootFromParent_Done, |
| 169288 | // Label 7955: @534723 |
| 169289 | GIM_Try, /*On fail goto*//*Label 7956*/ GIMT_Encode4(534790), // Rule ID 5028 // |
| 169290 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169291 | // MIs[0] offset |
| 169292 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169293 | // MIs[0] auxiliary |
| 169294 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169295 | // MIs[0] Operand 7 |
| 169296 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169297 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169298 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 169300 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169301 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169302 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169304 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169306 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169308 | GIR_RootConstrainSelectedInstOperands, |
| 169309 | // GIR_Coverage, 5028, |
| 169310 | GIR_EraseRootFromParent_Done, |
| 169311 | // Label 7956: @534790 |
| 169312 | GIM_Try, /*On fail goto*//*Label 7957*/ GIMT_Encode4(534860), // Rule ID 5032 // |
| 169313 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169314 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169315 | // MIs[0] offset |
| 169316 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169317 | // MIs[0] auxiliary |
| 169318 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169319 | // MIs[0] Operand 7 |
| 169320 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169321 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169322 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169323 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 169324 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169325 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169326 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169327 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169328 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169329 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169330 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169331 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169332 | GIR_RootConstrainSelectedInstOperands, |
| 169333 | // GIR_Coverage, 5032, |
| 169334 | GIR_EraseRootFromParent_Done, |
| 169335 | // Label 7957: @534860 |
| 169336 | GIM_Try, /*On fail goto*//*Label 7958*/ GIMT_Encode4(534927), // Rule ID 5036 // |
| 169337 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169338 | // MIs[0] offset |
| 169339 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169340 | // MIs[0] auxiliary |
| 169341 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169342 | // MIs[0] Operand 7 |
| 169343 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169345 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 169347 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169348 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169349 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169351 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169353 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169354 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169355 | GIR_RootConstrainSelectedInstOperands, |
| 169356 | // GIR_Coverage, 5036, |
| 169357 | GIR_EraseRootFromParent_Done, |
| 169358 | // Label 7958: @534927 |
| 169359 | GIM_Try, /*On fail goto*//*Label 7959*/ GIMT_Encode4(534989), // Rule ID 5025 // |
| 169360 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169362 | // MIs[0] offset |
| 169363 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169364 | // MIs[0] auxiliary |
| 169365 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169366 | // MIs[0] Operand 7 |
| 169367 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169369 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 169371 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169372 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169373 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169375 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169377 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169378 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169379 | GIR_RootConstrainSelectedInstOperands, |
| 169380 | // GIR_Coverage, 5025, |
| 169381 | GIR_EraseRootFromParent_Done, |
| 169382 | // Label 7959: @534989 |
| 169383 | GIM_Try, /*On fail goto*//*Label 7960*/ GIMT_Encode4(535048), // Rule ID 5029 // |
| 169384 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169385 | // MIs[0] offset |
| 169386 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169387 | // MIs[0] auxiliary |
| 169388 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169389 | // MIs[0] Operand 7 |
| 169390 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169391 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169392 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169393 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 169394 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169395 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169396 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169398 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169400 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169402 | GIR_RootConstrainSelectedInstOperands, |
| 169403 | // GIR_Coverage, 5029, |
| 169404 | GIR_EraseRootFromParent_Done, |
| 169405 | // Label 7960: @535048 |
| 169406 | GIM_Try, /*On fail goto*//*Label 7961*/ GIMT_Encode4(535110), // Rule ID 5033 // |
| 169407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169408 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169409 | // MIs[0] offset |
| 169410 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169411 | // MIs[0] auxiliary |
| 169412 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169413 | // MIs[0] Operand 7 |
| 169414 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169416 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 169418 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169419 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169420 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169422 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169423 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169424 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169426 | GIR_RootConstrainSelectedInstOperands, |
| 169427 | // GIR_Coverage, 5033, |
| 169428 | GIR_EraseRootFromParent_Done, |
| 169429 | // Label 7961: @535110 |
| 169430 | GIM_Try, /*On fail goto*//*Label 7962*/ GIMT_Encode4(535169), // Rule ID 5037 // |
| 169431 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169432 | // MIs[0] offset |
| 169433 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169434 | // MIs[0] auxiliary |
| 169435 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169436 | // MIs[0] Operand 7 |
| 169437 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169438 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169439 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 169441 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169442 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169443 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169444 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169445 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169446 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169447 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169448 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169449 | GIR_RootConstrainSelectedInstOperands, |
| 169450 | // GIR_Coverage, 5037, |
| 169451 | GIR_EraseRootFromParent_Done, |
| 169452 | // Label 7962: @535169 |
| 169453 | GIM_Try, /*On fail goto*//*Label 7963*/ GIMT_Encode4(535269), // Rule ID 5026 // |
| 169454 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169455 | // MIs[0] offset |
| 169456 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169457 | // MIs[0] auxiliary |
| 169458 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169459 | // MIs[0] Operand 7 |
| 169460 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169462 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169463 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169464 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169465 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169466 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169467 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169468 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169469 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169470 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169471 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169472 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169473 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 169474 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169475 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169476 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169477 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169478 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169479 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169480 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169481 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169482 | GIR_RootConstrainSelectedInstOperands, |
| 169483 | // GIR_Coverage, 5026, |
| 169484 | GIR_EraseRootFromParent_Done, |
| 169485 | // Label 7963: @535269 |
| 169486 | GIM_Try, /*On fail goto*//*Label 7964*/ GIMT_Encode4(535366), // Rule ID 5030 // |
| 169487 | // MIs[0] offset |
| 169488 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169489 | // MIs[0] auxiliary |
| 169490 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169491 | // MIs[0] Operand 7 |
| 169492 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169493 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169494 | // (SIbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169495 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169496 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169497 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169498 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169499 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169500 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169501 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169502 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169503 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169504 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169505 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 169506 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169507 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169508 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169509 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169510 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169512 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169514 | GIR_RootConstrainSelectedInstOperands, |
| 169515 | // GIR_Coverage, 5030, |
| 169516 | GIR_EraseRootFromParent_Done, |
| 169517 | // Label 7964: @535366 |
| 169518 | GIM_Try, /*On fail goto*//*Label 7965*/ GIMT_Encode4(535466), // Rule ID 5034 // |
| 169519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169520 | // MIs[0] offset |
| 169521 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169522 | // MIs[0] auxiliary |
| 169523 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169524 | // MIs[0] Operand 7 |
| 169525 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169526 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169527 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169528 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169529 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169530 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169531 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169532 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169533 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169534 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169535 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169536 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169537 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169538 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 169539 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169540 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169541 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169543 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169545 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169546 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169547 | GIR_RootConstrainSelectedInstOperands, |
| 169548 | // GIR_Coverage, 5034, |
| 169549 | GIR_EraseRootFromParent_Done, |
| 169550 | // Label 7965: @535466 |
| 169551 | GIM_Try, /*On fail goto*//*Label 7966*/ GIMT_Encode4(535563), // Rule ID 5038 // |
| 169552 | // MIs[0] offset |
| 169553 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169554 | // MIs[0] auxiliary |
| 169555 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169556 | // MIs[0] Operand 7 |
| 169557 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169558 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169559 | // (SIbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169560 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169561 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169562 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169563 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169564 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169565 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169566 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169567 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169568 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169569 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 169571 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169572 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169573 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169575 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169576 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169577 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169578 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169579 | GIR_RootConstrainSelectedInstOperands, |
| 169580 | // GIR_Coverage, 5038, |
| 169581 | GIR_EraseRootFromParent_Done, |
| 169582 | // Label 7966: @535563 |
| 169583 | GIM_Reject, |
| 169584 | // Label 7950: @535564 |
| 169585 | GIM_Reject, |
| 169586 | // Label 7896: @535565 |
| 169587 | GIM_Try, /*On fail goto*//*Label 7967*/ GIMT_Encode4(536775), |
| 169588 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 169589 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 169590 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 169591 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 169592 | GIM_Try, /*On fail goto*//*Label 7968*/ GIMT_Encode4(535654), // Rule ID 5095 // |
| 169593 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169594 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169595 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169596 | // MIs[0] offset |
| 169597 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169598 | // MIs[0] auxiliary |
| 169599 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169600 | // MIs[0] Operand 7 |
| 169601 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169602 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169603 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169604 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 169605 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169606 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169607 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169608 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169609 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169610 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169611 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169612 | GIR_RootConstrainSelectedInstOperands, |
| 169613 | // GIR_Coverage, 5095, |
| 169614 | GIR_EraseRootFromParent_Done, |
| 169615 | // Label 7968: @535654 |
| 169616 | GIM_Try, /*On fail goto*//*Label 7969*/ GIMT_Encode4(535723), // Rule ID 5099 // |
| 169617 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169618 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169619 | // MIs[0] offset |
| 169620 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169621 | // MIs[0] auxiliary |
| 169622 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169623 | // MIs[0] Operand 7 |
| 169624 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169626 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 169628 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169629 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169630 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169631 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169633 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169634 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169635 | GIR_RootConstrainSelectedInstOperands, |
| 169636 | // GIR_Coverage, 5099, |
| 169637 | GIR_EraseRootFromParent_Done, |
| 169638 | // Label 7969: @535723 |
| 169639 | GIM_Try, /*On fail goto*//*Label 7970*/ GIMT_Encode4(535795), // Rule ID 5103 // |
| 169640 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169641 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169643 | // MIs[0] offset |
| 169644 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169645 | // MIs[0] auxiliary |
| 169646 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169647 | // MIs[0] Operand 7 |
| 169648 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169650 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[f64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 169652 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169653 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169655 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169656 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169658 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169659 | GIR_RootConstrainSelectedInstOperands, |
| 169660 | // GIR_Coverage, 5103, |
| 169661 | GIR_EraseRootFromParent_Done, |
| 169662 | // Label 7970: @535795 |
| 169663 | GIM_Try, /*On fail goto*//*Label 7971*/ GIMT_Encode4(535864), // Rule ID 5107 // |
| 169664 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169665 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169666 | // MIs[0] offset |
| 169667 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169668 | // MIs[0] auxiliary |
| 169669 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169670 | // MIs[0] Operand 7 |
| 169671 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169673 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[f64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169674 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 169675 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169676 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169677 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169678 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169679 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169680 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169681 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169682 | GIR_RootConstrainSelectedInstOperands, |
| 169683 | // GIR_Coverage, 5107, |
| 169684 | GIR_EraseRootFromParent_Done, |
| 169685 | // Label 7971: @535864 |
| 169686 | GIM_Try, /*On fail goto*//*Label 7972*/ GIMT_Encode4(535934), // Rule ID 5096 // |
| 169687 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169688 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169689 | // MIs[0] offset |
| 169690 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169691 | // MIs[0] auxiliary |
| 169692 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169693 | // MIs[0] Operand 7 |
| 169694 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169696 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 169698 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169699 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169700 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169702 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169704 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169706 | GIR_RootConstrainSelectedInstOperands, |
| 169707 | // GIR_Coverage, 5096, |
| 169708 | GIR_EraseRootFromParent_Done, |
| 169709 | // Label 7972: @535934 |
| 169710 | GIM_Try, /*On fail goto*//*Label 7973*/ GIMT_Encode4(536001), // Rule ID 5100 // |
| 169711 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169712 | // MIs[0] offset |
| 169713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169714 | // MIs[0] auxiliary |
| 169715 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169716 | // MIs[0] Operand 7 |
| 169717 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169719 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 169721 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169722 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169723 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169725 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169726 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169728 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169729 | GIR_RootConstrainSelectedInstOperands, |
| 169730 | // GIR_Coverage, 5100, |
| 169731 | GIR_EraseRootFromParent_Done, |
| 169732 | // Label 7973: @536001 |
| 169733 | GIM_Try, /*On fail goto*//*Label 7974*/ GIMT_Encode4(536071), // Rule ID 5104 // |
| 169734 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169735 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169736 | // MIs[0] offset |
| 169737 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169738 | // MIs[0] auxiliary |
| 169739 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169740 | // MIs[0] Operand 7 |
| 169741 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169742 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169743 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[f64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169744 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 169745 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169746 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169747 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169748 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169749 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169750 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169751 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169753 | GIR_RootConstrainSelectedInstOperands, |
| 169754 | // GIR_Coverage, 5104, |
| 169755 | GIR_EraseRootFromParent_Done, |
| 169756 | // Label 7974: @536071 |
| 169757 | GIM_Try, /*On fail goto*//*Label 7975*/ GIMT_Encode4(536138), // Rule ID 5108 // |
| 169758 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 169759 | // MIs[0] offset |
| 169760 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169761 | // MIs[0] auxiliary |
| 169762 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169763 | // MIs[0] Operand 7 |
| 169764 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 169765 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169766 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[f64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169767 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 169768 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169769 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 169770 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169771 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169772 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169773 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169775 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169776 | GIR_RootConstrainSelectedInstOperands, |
| 169777 | // GIR_Coverage, 5108, |
| 169778 | GIR_EraseRootFromParent_Done, |
| 169779 | // Label 7975: @536138 |
| 169780 | GIM_Try, /*On fail goto*//*Label 7976*/ GIMT_Encode4(536200), // Rule ID 5097 // |
| 169781 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169782 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169783 | // MIs[0] offset |
| 169784 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169785 | // MIs[0] auxiliary |
| 169786 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169787 | // MIs[0] Operand 7 |
| 169788 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169789 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169790 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169791 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 169792 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169793 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169794 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169795 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169796 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169797 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169798 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169799 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169800 | GIR_RootConstrainSelectedInstOperands, |
| 169801 | // GIR_Coverage, 5097, |
| 169802 | GIR_EraseRootFromParent_Done, |
| 169803 | // Label 7976: @536200 |
| 169804 | GIM_Try, /*On fail goto*//*Label 7977*/ GIMT_Encode4(536259), // Rule ID 5101 // |
| 169805 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169806 | // MIs[0] offset |
| 169807 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169808 | // MIs[0] auxiliary |
| 169809 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169810 | // MIs[0] Operand 7 |
| 169811 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169812 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169813 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 169815 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169816 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169817 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169818 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169819 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169821 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169823 | GIR_RootConstrainSelectedInstOperands, |
| 169824 | // GIR_Coverage, 5101, |
| 169825 | GIR_EraseRootFromParent_Done, |
| 169826 | // Label 7977: @536259 |
| 169827 | GIM_Try, /*On fail goto*//*Label 7978*/ GIMT_Encode4(536321), // Rule ID 5105 // |
| 169828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169829 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169830 | // MIs[0] offset |
| 169831 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169832 | // MIs[0] auxiliary |
| 169833 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169834 | // MIs[0] Operand 7 |
| 169835 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169836 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169837 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[f64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 169839 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169840 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169841 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169843 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169844 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169845 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169846 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169847 | GIR_RootConstrainSelectedInstOperands, |
| 169848 | // GIR_Coverage, 5105, |
| 169849 | GIR_EraseRootFromParent_Done, |
| 169850 | // Label 7978: @536321 |
| 169851 | GIM_Try, /*On fail goto*//*Label 7979*/ GIMT_Encode4(536380), // Rule ID 5109 // |
| 169852 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 169853 | // MIs[0] offset |
| 169854 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169855 | // MIs[0] auxiliary |
| 169856 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169857 | // MIs[0] Operand 7 |
| 169858 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169859 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169860 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[f64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169861 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 169862 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169863 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 169864 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169865 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169866 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169867 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169868 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169869 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169870 | GIR_RootConstrainSelectedInstOperands, |
| 169871 | // GIR_Coverage, 5109, |
| 169872 | GIR_EraseRootFromParent_Done, |
| 169873 | // Label 7979: @536380 |
| 169874 | GIM_Try, /*On fail goto*//*Label 7980*/ GIMT_Encode4(536480), // Rule ID 5098 // |
| 169875 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169876 | // MIs[0] offset |
| 169877 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169878 | // MIs[0] auxiliary |
| 169879 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169880 | // MIs[0] Operand 7 |
| 169881 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169882 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169883 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169884 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169885 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169886 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169887 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169888 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169889 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169890 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169891 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169892 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169893 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 169895 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169896 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169897 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169899 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169903 | GIR_RootConstrainSelectedInstOperands, |
| 169904 | // GIR_Coverage, 5098, |
| 169905 | GIR_EraseRootFromParent_Done, |
| 169906 | // Label 7980: @536480 |
| 169907 | GIM_Try, /*On fail goto*//*Label 7981*/ GIMT_Encode4(536577), // Rule ID 5102 // |
| 169908 | // MIs[0] offset |
| 169909 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169910 | // MIs[0] auxiliary |
| 169911 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169912 | // MIs[0] Operand 7 |
| 169913 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169914 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169915 | // (SIbuffer_store i64:{ *:[i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169916 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169917 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169918 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169919 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169920 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169921 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169922 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169923 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169924 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169925 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169926 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 169927 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169928 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169929 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169930 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169931 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169932 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169933 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169934 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169935 | GIR_RootConstrainSelectedInstOperands, |
| 169936 | // GIR_Coverage, 5102, |
| 169937 | GIR_EraseRootFromParent_Done, |
| 169938 | // Label 7981: @536577 |
| 169939 | GIM_Try, /*On fail goto*//*Label 7982*/ GIMT_Encode4(536677), // Rule ID 5106 // |
| 169940 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 169941 | // MIs[0] offset |
| 169942 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169943 | // MIs[0] auxiliary |
| 169944 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169945 | // MIs[0] Operand 7 |
| 169946 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169947 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169948 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[f64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169949 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169950 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169951 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169952 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169953 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169954 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169955 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169956 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169957 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169958 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 169960 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169961 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169962 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169964 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 169968 | GIR_RootConstrainSelectedInstOperands, |
| 169969 | // GIR_Coverage, 5106, |
| 169970 | GIR_EraseRootFromParent_Done, |
| 169971 | // Label 7982: @536677 |
| 169972 | GIM_Try, /*On fail goto*//*Label 7983*/ GIMT_Encode4(536774), // Rule ID 5110 // |
| 169973 | // MIs[0] offset |
| 169974 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 169975 | // MIs[0] auxiliary |
| 169976 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 169977 | // MIs[0] Operand 7 |
| 169978 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 169979 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 169980 | // (SIbuffer_store f64:{ *:[f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[f64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 169981 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 169982 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 169983 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 169984 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 169985 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 169986 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 169987 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 169988 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 169989 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169990 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 169991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 169992 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 169993 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 169994 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 169995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 169996 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 169997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 169998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 169999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170000 | GIR_RootConstrainSelectedInstOperands, |
| 170001 | // GIR_Coverage, 5110, |
| 170002 | GIR_EraseRootFromParent_Done, |
| 170003 | // Label 7983: @536774 |
| 170004 | GIM_Reject, |
| 170005 | // Label 7967: @536775 |
| 170006 | GIM_Reject, |
| 170007 | // Label 7897: @536776 |
| 170008 | GIM_Try, /*On fail goto*//*Label 7984*/ GIMT_Encode4(538582), |
| 170009 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 170010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 170011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 170012 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 170013 | GIM_Try, /*On fail goto*//*Label 7985*/ GIMT_Encode4(536865), // Rule ID 5039 // |
| 170014 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170015 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170016 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170017 | // MIs[0] offset |
| 170018 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170019 | // MIs[0] auxiliary |
| 170020 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170021 | // MIs[0] Operand 7 |
| 170022 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170023 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170024 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170025 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 170026 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170027 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170028 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170029 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170030 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170033 | GIR_RootConstrainSelectedInstOperands, |
| 170034 | // GIR_Coverage, 5039, |
| 170035 | GIR_EraseRootFromParent_Done, |
| 170036 | // Label 7985: @536865 |
| 170037 | GIM_Try, /*On fail goto*//*Label 7986*/ GIMT_Encode4(536934), // Rule ID 5043 // |
| 170038 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170039 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170040 | // MIs[0] offset |
| 170041 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170042 | // MIs[0] auxiliary |
| 170043 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170044 | // MIs[0] Operand 7 |
| 170045 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170046 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170047 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170048 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 170049 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170050 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170051 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170052 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170053 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170054 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170055 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170056 | GIR_RootConstrainSelectedInstOperands, |
| 170057 | // GIR_Coverage, 5043, |
| 170058 | GIR_EraseRootFromParent_Done, |
| 170059 | // Label 7986: @536934 |
| 170060 | GIM_Try, /*On fail goto*//*Label 7987*/ GIMT_Encode4(537006), // Rule ID 5047 // |
| 170061 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170062 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170063 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170064 | // MIs[0] offset |
| 170065 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170066 | // MIs[0] auxiliary |
| 170067 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170068 | // MIs[0] Operand 7 |
| 170069 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170070 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170071 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170072 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 170073 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170074 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170075 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170076 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170077 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170078 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170079 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170080 | GIR_RootConstrainSelectedInstOperands, |
| 170081 | // GIR_Coverage, 5047, |
| 170082 | GIR_EraseRootFromParent_Done, |
| 170083 | // Label 7987: @537006 |
| 170084 | GIM_Try, /*On fail goto*//*Label 7988*/ GIMT_Encode4(537075), // Rule ID 5051 // |
| 170085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170087 | // MIs[0] offset |
| 170088 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170089 | // MIs[0] auxiliary |
| 170090 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170091 | // MIs[0] Operand 7 |
| 170092 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170093 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170094 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170095 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 170096 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170097 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170098 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170099 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170100 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170101 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170102 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170103 | GIR_RootConstrainSelectedInstOperands, |
| 170104 | // GIR_Coverage, 5051, |
| 170105 | GIR_EraseRootFromParent_Done, |
| 170106 | // Label 7988: @537075 |
| 170107 | GIM_Try, /*On fail goto*//*Label 7989*/ GIMT_Encode4(537147), // Rule ID 5055 // |
| 170108 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170109 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170110 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170111 | // MIs[0] offset |
| 170112 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170113 | // MIs[0] auxiliary |
| 170114 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170115 | // MIs[0] Operand 7 |
| 170116 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170117 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170118 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFSET_exact anonymous_15876:{ *:[v2bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFSET_exact), |
| 170120 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170121 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170123 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170125 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170126 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170127 | GIR_RootConstrainSelectedInstOperands, |
| 170128 | // GIR_Coverage, 5055, |
| 170129 | GIR_EraseRootFromParent_Done, |
| 170130 | // Label 7989: @537147 |
| 170131 | GIM_Try, /*On fail goto*//*Label 7990*/ GIMT_Encode4(537216), // Rule ID 5059 // |
| 170132 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170133 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170134 | // MIs[0] offset |
| 170135 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170136 | // MIs[0] auxiliary |
| 170137 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170138 | // MIs[0] Operand 7 |
| 170139 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170140 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170141 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFSET_exact), |
| 170143 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170144 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170146 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170149 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170150 | GIR_RootConstrainSelectedInstOperands, |
| 170151 | // GIR_Coverage, 5059, |
| 170152 | GIR_EraseRootFromParent_Done, |
| 170153 | // Label 7990: @537216 |
| 170154 | GIM_Try, /*On fail goto*//*Label 7991*/ GIMT_Encode4(537286), // Rule ID 5040 // |
| 170155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170156 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170157 | // MIs[0] offset |
| 170158 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170159 | // MIs[0] auxiliary |
| 170160 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170161 | // MIs[0] Operand 7 |
| 170162 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170164 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170165 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 170166 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170167 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170168 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170169 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170170 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170171 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170172 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170173 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170174 | GIR_RootConstrainSelectedInstOperands, |
| 170175 | // GIR_Coverage, 5040, |
| 170176 | GIR_EraseRootFromParent_Done, |
| 170177 | // Label 7991: @537286 |
| 170178 | GIM_Try, /*On fail goto*//*Label 7992*/ GIMT_Encode4(537353), // Rule ID 5044 // |
| 170179 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170180 | // MIs[0] offset |
| 170181 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170182 | // MIs[0] auxiliary |
| 170183 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170184 | // MIs[0] Operand 7 |
| 170185 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170186 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170187 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 170189 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170190 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170191 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170193 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170194 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170196 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170197 | GIR_RootConstrainSelectedInstOperands, |
| 170198 | // GIR_Coverage, 5044, |
| 170199 | GIR_EraseRootFromParent_Done, |
| 170200 | // Label 7992: @537353 |
| 170201 | GIM_Try, /*On fail goto*//*Label 7993*/ GIMT_Encode4(537423), // Rule ID 5048 // |
| 170202 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170203 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170204 | // MIs[0] offset |
| 170205 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170206 | // MIs[0] auxiliary |
| 170207 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170208 | // MIs[0] Operand 7 |
| 170209 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170211 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 170213 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170214 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170215 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170216 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170217 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170219 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170221 | GIR_RootConstrainSelectedInstOperands, |
| 170222 | // GIR_Coverage, 5048, |
| 170223 | GIR_EraseRootFromParent_Done, |
| 170224 | // Label 7993: @537423 |
| 170225 | GIM_Try, /*On fail goto*//*Label 7994*/ GIMT_Encode4(537490), // Rule ID 5052 // |
| 170226 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170227 | // MIs[0] offset |
| 170228 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170229 | // MIs[0] auxiliary |
| 170230 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170231 | // MIs[0] Operand 7 |
| 170232 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170233 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170234 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170235 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 170236 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170237 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170238 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170239 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170240 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170241 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170242 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170243 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170244 | GIR_RootConstrainSelectedInstOperands, |
| 170245 | // GIR_Coverage, 5052, |
| 170246 | GIR_EraseRootFromParent_Done, |
| 170247 | // Label 7994: @537490 |
| 170248 | GIM_Try, /*On fail goto*//*Label 7995*/ GIMT_Encode4(537560), // Rule ID 5056 // |
| 170249 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170250 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170251 | // MIs[0] offset |
| 170252 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170253 | // MIs[0] auxiliary |
| 170254 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170255 | // MIs[0] Operand 7 |
| 170256 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170257 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170258 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_OFFEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170259 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_OFFEN_exact), |
| 170260 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170261 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170262 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170263 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170264 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170265 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170266 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170267 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170268 | GIR_RootConstrainSelectedInstOperands, |
| 170269 | // GIR_Coverage, 5056, |
| 170270 | GIR_EraseRootFromParent_Done, |
| 170271 | // Label 7995: @537560 |
| 170272 | GIM_Try, /*On fail goto*//*Label 7996*/ GIMT_Encode4(537627), // Rule ID 5060 // |
| 170273 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170274 | // MIs[0] offset |
| 170275 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170276 | // MIs[0] auxiliary |
| 170277 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170278 | // MIs[0] Operand 7 |
| 170279 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170280 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170281 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170282 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_OFFEN_exact), |
| 170283 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170284 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170285 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170286 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170287 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170288 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170289 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170291 | GIR_RootConstrainSelectedInstOperands, |
| 170292 | // GIR_Coverage, 5060, |
| 170293 | GIR_EraseRootFromParent_Done, |
| 170294 | // Label 7996: @537627 |
| 170295 | GIM_Try, /*On fail goto*//*Label 7997*/ GIMT_Encode4(537689), // Rule ID 5041 // |
| 170296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170297 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170298 | // MIs[0] offset |
| 170299 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170300 | // MIs[0] auxiliary |
| 170301 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170302 | // MIs[0] Operand 7 |
| 170303 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170304 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170305 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170306 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 170307 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170308 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170309 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170311 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170312 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170313 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170314 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170315 | GIR_RootConstrainSelectedInstOperands, |
| 170316 | // GIR_Coverage, 5041, |
| 170317 | GIR_EraseRootFromParent_Done, |
| 170318 | // Label 7997: @537689 |
| 170319 | GIM_Try, /*On fail goto*//*Label 7998*/ GIMT_Encode4(537748), // Rule ID 5045 // |
| 170320 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170321 | // MIs[0] offset |
| 170322 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170323 | // MIs[0] auxiliary |
| 170324 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170325 | // MIs[0] Operand 7 |
| 170326 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170327 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170328 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170329 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 170330 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170331 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170332 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170333 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170334 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170335 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170336 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170337 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170338 | GIR_RootConstrainSelectedInstOperands, |
| 170339 | // GIR_Coverage, 5045, |
| 170340 | GIR_EraseRootFromParent_Done, |
| 170341 | // Label 7998: @537748 |
| 170342 | GIM_Try, /*On fail goto*//*Label 7999*/ GIMT_Encode4(537810), // Rule ID 5049 // |
| 170343 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170344 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170345 | // MIs[0] offset |
| 170346 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170347 | // MIs[0] auxiliary |
| 170348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170349 | // MIs[0] Operand 7 |
| 170350 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170352 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170353 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 170354 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170355 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170356 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170357 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170358 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170360 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170362 | GIR_RootConstrainSelectedInstOperands, |
| 170363 | // GIR_Coverage, 5049, |
| 170364 | GIR_EraseRootFromParent_Done, |
| 170365 | // Label 7999: @537810 |
| 170366 | GIM_Try, /*On fail goto*//*Label 8000*/ GIMT_Encode4(537869), // Rule ID 5053 // |
| 170367 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170368 | // MIs[0] offset |
| 170369 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170370 | // MIs[0] auxiliary |
| 170371 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170372 | // MIs[0] Operand 7 |
| 170373 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170374 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170375 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170376 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 170377 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170378 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170379 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170380 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170381 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170382 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170384 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170385 | GIR_RootConstrainSelectedInstOperands, |
| 170386 | // GIR_Coverage, 5053, |
| 170387 | GIR_EraseRootFromParent_Done, |
| 170388 | // Label 8000: @537869 |
| 170389 | GIM_Try, /*On fail goto*//*Label 8001*/ GIMT_Encode4(537931), // Rule ID 5057 // |
| 170390 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170391 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170392 | // MIs[0] offset |
| 170393 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170394 | // MIs[0] auxiliary |
| 170395 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170396 | // MIs[0] Operand 7 |
| 170397 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170398 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170399 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_IDXEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170400 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_IDXEN_exact), |
| 170401 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170402 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170403 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170404 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170405 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170406 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170407 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170408 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170409 | GIR_RootConstrainSelectedInstOperands, |
| 170410 | // GIR_Coverage, 5057, |
| 170411 | GIR_EraseRootFromParent_Done, |
| 170412 | // Label 8001: @537931 |
| 170413 | GIM_Try, /*On fail goto*//*Label 8002*/ GIMT_Encode4(537990), // Rule ID 5061 // |
| 170414 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170415 | // MIs[0] offset |
| 170416 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170417 | // MIs[0] auxiliary |
| 170418 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170419 | // MIs[0] Operand 7 |
| 170420 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170422 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_IDXEN_exact), |
| 170424 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170425 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170426 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170428 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170429 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170431 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170432 | GIR_RootConstrainSelectedInstOperands, |
| 170433 | // GIR_Coverage, 5061, |
| 170434 | GIR_EraseRootFromParent_Done, |
| 170435 | // Label 8002: @537990 |
| 170436 | GIM_Try, /*On fail goto*//*Label 8003*/ GIMT_Encode4(538090), // Rule ID 5042 // |
| 170437 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170438 | // MIs[0] offset |
| 170439 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170440 | // MIs[0] auxiliary |
| 170441 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170442 | // MIs[0] Operand 7 |
| 170443 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170444 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170445 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170446 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170447 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170448 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170449 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170450 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170451 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170452 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170453 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170454 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170455 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 170457 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170458 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170459 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170461 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170462 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170465 | GIR_RootConstrainSelectedInstOperands, |
| 170466 | // GIR_Coverage, 5042, |
| 170467 | GIR_EraseRootFromParent_Done, |
| 170468 | // Label 8003: @538090 |
| 170469 | GIM_Try, /*On fail goto*//*Label 8004*/ GIMT_Encode4(538187), // Rule ID 5046 // |
| 170470 | // MIs[0] offset |
| 170471 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170472 | // MIs[0] auxiliary |
| 170473 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170474 | // MIs[0] Operand 7 |
| 170475 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170477 | // (SIbuffer_store v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170478 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170479 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170480 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170481 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170482 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170483 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170484 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170485 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170486 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170487 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170488 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 170489 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170490 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170491 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170492 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170493 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170494 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170495 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170496 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170497 | GIR_RootConstrainSelectedInstOperands, |
| 170498 | // GIR_Coverage, 5046, |
| 170499 | GIR_EraseRootFromParent_Done, |
| 170500 | // Label 8004: @538187 |
| 170501 | GIM_Try, /*On fail goto*//*Label 8005*/ GIMT_Encode4(538287), // Rule ID 5050 // |
| 170502 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170503 | // MIs[0] offset |
| 170504 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170505 | // MIs[0] auxiliary |
| 170506 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170507 | // MIs[0] Operand 7 |
| 170508 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170510 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170511 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170512 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170513 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170514 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170515 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170516 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170517 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170518 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170519 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170520 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 170522 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170523 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170524 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170526 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170527 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170528 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170529 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170530 | GIR_RootConstrainSelectedInstOperands, |
| 170531 | // GIR_Coverage, 5050, |
| 170532 | GIR_EraseRootFromParent_Done, |
| 170533 | // Label 8005: @538287 |
| 170534 | GIM_Try, /*On fail goto*//*Label 8006*/ GIMT_Encode4(538384), // Rule ID 5054 // |
| 170535 | // MIs[0] offset |
| 170536 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170537 | // MIs[0] auxiliary |
| 170538 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170539 | // MIs[0] Operand 7 |
| 170540 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170542 | // (SIbuffer_store v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170543 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170544 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170545 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170546 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170547 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170548 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170549 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170550 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170551 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170552 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170553 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 170554 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170555 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170556 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170557 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170558 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170559 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170560 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170561 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170562 | GIR_RootConstrainSelectedInstOperands, |
| 170563 | // GIR_Coverage, 5054, |
| 170564 | GIR_EraseRootFromParent_Done, |
| 170565 | // Label 8006: @538384 |
| 170566 | GIM_Try, /*On fail goto*//*Label 8007*/ GIMT_Encode4(538484), // Rule ID 5058 // |
| 170567 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170568 | // MIs[0] offset |
| 170569 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170570 | // MIs[0] auxiliary |
| 170571 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170572 | // MIs[0] Operand 7 |
| 170573 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170574 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170575 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_BOTHEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170576 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170577 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170578 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170579 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170580 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170581 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170582 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170583 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170584 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170585 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170586 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_BOTHEN_exact), |
| 170587 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170588 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170589 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170590 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170591 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170592 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170594 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170595 | GIR_RootConstrainSelectedInstOperands, |
| 170596 | // GIR_Coverage, 5058, |
| 170597 | GIR_EraseRootFromParent_Done, |
| 170598 | // Label 8007: @538484 |
| 170599 | GIM_Try, /*On fail goto*//*Label 8008*/ GIMT_Encode4(538581), // Rule ID 5062 // |
| 170600 | // MIs[0] offset |
| 170601 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170602 | // MIs[0] auxiliary |
| 170603 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170604 | // MIs[0] Operand 7 |
| 170605 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170607 | // (SIbuffer_store v2bf16:{ *:[v2bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170611 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170612 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170613 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170614 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170616 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170617 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORD_VBUFFER_BOTHEN_exact), |
| 170619 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170621 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170623 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170624 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170625 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170627 | GIR_RootConstrainSelectedInstOperands, |
| 170628 | // GIR_Coverage, 5062, |
| 170629 | GIR_EraseRootFromParent_Done, |
| 170630 | // Label 8008: @538581 |
| 170631 | GIM_Reject, |
| 170632 | // Label 7984: @538582 |
| 170633 | GIM_Reject, |
| 170634 | // Label 7898: @538583 |
| 170635 | GIM_Try, /*On fail goto*//*Label 8009*/ GIMT_Encode4(539793), |
| 170636 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 170637 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 170638 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 170639 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 170640 | GIM_Try, /*On fail goto*//*Label 8010*/ GIMT_Encode4(538672), // Rule ID 5111 // |
| 170641 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170643 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170644 | // MIs[0] offset |
| 170645 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170646 | // MIs[0] auxiliary |
| 170647 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170648 | // MIs[0] Operand 7 |
| 170649 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170650 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170651 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170652 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 170653 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170654 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170656 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170658 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170659 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170660 | GIR_RootConstrainSelectedInstOperands, |
| 170661 | // GIR_Coverage, 5111, |
| 170662 | GIR_EraseRootFromParent_Done, |
| 170663 | // Label 8010: @538672 |
| 170664 | GIM_Try, /*On fail goto*//*Label 8011*/ GIMT_Encode4(538741), // Rule ID 5115 // |
| 170665 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170666 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170667 | // MIs[0] offset |
| 170668 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170669 | // MIs[0] auxiliary |
| 170670 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170671 | // MIs[0] Operand 7 |
| 170672 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170674 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170675 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 170676 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170677 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170678 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170679 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170680 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170681 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170682 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170683 | GIR_RootConstrainSelectedInstOperands, |
| 170684 | // GIR_Coverage, 5115, |
| 170685 | GIR_EraseRootFromParent_Done, |
| 170686 | // Label 8011: @538741 |
| 170687 | GIM_Try, /*On fail goto*//*Label 8012*/ GIMT_Encode4(538813), // Rule ID 5119 // |
| 170688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170689 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170690 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170691 | // MIs[0] offset |
| 170692 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170693 | // MIs[0] auxiliary |
| 170694 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170695 | // MIs[0] Operand 7 |
| 170696 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170697 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170698 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170699 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 170700 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170701 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170702 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170703 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170704 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170705 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170707 | GIR_RootConstrainSelectedInstOperands, |
| 170708 | // GIR_Coverage, 5119, |
| 170709 | GIR_EraseRootFromParent_Done, |
| 170710 | // Label 8012: @538813 |
| 170711 | GIM_Try, /*On fail goto*//*Label 8013*/ GIMT_Encode4(538882), // Rule ID 5123 // |
| 170712 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170713 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170714 | // MIs[0] offset |
| 170715 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170716 | // MIs[0] auxiliary |
| 170717 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170718 | // MIs[0] Operand 7 |
| 170719 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170721 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 170723 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170724 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170726 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170728 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170729 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170730 | GIR_RootConstrainSelectedInstOperands, |
| 170731 | // GIR_Coverage, 5123, |
| 170732 | GIR_EraseRootFromParent_Done, |
| 170733 | // Label 8013: @538882 |
| 170734 | GIM_Try, /*On fail goto*//*Label 8014*/ GIMT_Encode4(538952), // Rule ID 5112 // |
| 170735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170737 | // MIs[0] offset |
| 170738 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170739 | // MIs[0] auxiliary |
| 170740 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170741 | // MIs[0] Operand 7 |
| 170742 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170743 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170744 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170745 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 170746 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170747 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170748 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170749 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170750 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170751 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170752 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170753 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170754 | GIR_RootConstrainSelectedInstOperands, |
| 170755 | // GIR_Coverage, 5112, |
| 170756 | GIR_EraseRootFromParent_Done, |
| 170757 | // Label 8014: @538952 |
| 170758 | GIM_Try, /*On fail goto*//*Label 8015*/ GIMT_Encode4(539019), // Rule ID 5116 // |
| 170759 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170760 | // MIs[0] offset |
| 170761 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170762 | // MIs[0] auxiliary |
| 170763 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170764 | // MIs[0] Operand 7 |
| 170765 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170766 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170767 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170768 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 170769 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170770 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170771 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170773 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170775 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170776 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170777 | GIR_RootConstrainSelectedInstOperands, |
| 170778 | // GIR_Coverage, 5116, |
| 170779 | GIR_EraseRootFromParent_Done, |
| 170780 | // Label 8015: @539019 |
| 170781 | GIM_Try, /*On fail goto*//*Label 8016*/ GIMT_Encode4(539089), // Rule ID 5120 // |
| 170782 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170784 | // MIs[0] offset |
| 170785 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170786 | // MIs[0] auxiliary |
| 170787 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170788 | // MIs[0] Operand 7 |
| 170789 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170790 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170791 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170792 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 170793 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170794 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170795 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170796 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170797 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170798 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170799 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170800 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170801 | GIR_RootConstrainSelectedInstOperands, |
| 170802 | // GIR_Coverage, 5120, |
| 170803 | GIR_EraseRootFromParent_Done, |
| 170804 | // Label 8016: @539089 |
| 170805 | GIM_Try, /*On fail goto*//*Label 8017*/ GIMT_Encode4(539156), // Rule ID 5124 // |
| 170806 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 170807 | // MIs[0] offset |
| 170808 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170809 | // MIs[0] auxiliary |
| 170810 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170811 | // MIs[0] Operand 7 |
| 170812 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 170813 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170814 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 170816 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170817 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 170818 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170820 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170821 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170822 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170823 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170824 | GIR_RootConstrainSelectedInstOperands, |
| 170825 | // GIR_Coverage, 5124, |
| 170826 | GIR_EraseRootFromParent_Done, |
| 170827 | // Label 8017: @539156 |
| 170828 | GIM_Try, /*On fail goto*//*Label 8018*/ GIMT_Encode4(539218), // Rule ID 5113 // |
| 170829 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170830 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170831 | // MIs[0] offset |
| 170832 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170833 | // MIs[0] auxiliary |
| 170834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170835 | // MIs[0] Operand 7 |
| 170836 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170838 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170839 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 170840 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170841 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170842 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170843 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170844 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170845 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170846 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170847 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170848 | GIR_RootConstrainSelectedInstOperands, |
| 170849 | // GIR_Coverage, 5113, |
| 170850 | GIR_EraseRootFromParent_Done, |
| 170851 | // Label 8018: @539218 |
| 170852 | GIM_Try, /*On fail goto*//*Label 8019*/ GIMT_Encode4(539277), // Rule ID 5117 // |
| 170853 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170854 | // MIs[0] offset |
| 170855 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170856 | // MIs[0] auxiliary |
| 170857 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170858 | // MIs[0] Operand 7 |
| 170859 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170860 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170861 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170862 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 170863 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170864 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170865 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170866 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170867 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170868 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170869 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170870 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170871 | GIR_RootConstrainSelectedInstOperands, |
| 170872 | // GIR_Coverage, 5117, |
| 170873 | GIR_EraseRootFromParent_Done, |
| 170874 | // Label 8019: @539277 |
| 170875 | GIM_Try, /*On fail goto*//*Label 8020*/ GIMT_Encode4(539339), // Rule ID 5121 // |
| 170876 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170877 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170878 | // MIs[0] offset |
| 170879 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170880 | // MIs[0] auxiliary |
| 170881 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170882 | // MIs[0] Operand 7 |
| 170883 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170884 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170885 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170886 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 170887 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170888 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170889 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170890 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170891 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170892 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170893 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170894 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170895 | GIR_RootConstrainSelectedInstOperands, |
| 170896 | // GIR_Coverage, 5121, |
| 170897 | GIR_EraseRootFromParent_Done, |
| 170898 | // Label 8020: @539339 |
| 170899 | GIM_Try, /*On fail goto*//*Label 8021*/ GIMT_Encode4(539398), // Rule ID 5125 // |
| 170900 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 170901 | // MIs[0] offset |
| 170902 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170903 | // MIs[0] auxiliary |
| 170904 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170905 | // MIs[0] Operand 7 |
| 170906 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170908 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170909 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 170910 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170911 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 170912 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170913 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170914 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170915 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170916 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170917 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170918 | GIR_RootConstrainSelectedInstOperands, |
| 170919 | // GIR_Coverage, 5125, |
| 170920 | GIR_EraseRootFromParent_Done, |
| 170921 | // Label 8021: @539398 |
| 170922 | GIM_Try, /*On fail goto*//*Label 8022*/ GIMT_Encode4(539498), // Rule ID 5114 // |
| 170923 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170924 | // MIs[0] offset |
| 170925 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170926 | // MIs[0] auxiliary |
| 170927 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170928 | // MIs[0] Operand 7 |
| 170929 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170930 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170931 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170932 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170933 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170934 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170935 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170936 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170937 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170938 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170939 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170940 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170941 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 170943 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170944 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170945 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170947 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170949 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170951 | GIR_RootConstrainSelectedInstOperands, |
| 170952 | // GIR_Coverage, 5114, |
| 170953 | GIR_EraseRootFromParent_Done, |
| 170954 | // Label 8022: @539498 |
| 170955 | GIM_Try, /*On fail goto*//*Label 8023*/ GIMT_Encode4(539595), // Rule ID 5118 // |
| 170956 | // MIs[0] offset |
| 170957 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170958 | // MIs[0] auxiliary |
| 170959 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170960 | // MIs[0] Operand 7 |
| 170961 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170963 | // (SIbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170964 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170965 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170966 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 170967 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 170968 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 170969 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 170970 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 170971 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 170972 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170973 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 170974 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 170975 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 170976 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 170977 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 170978 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 170979 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 170980 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 170981 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 170982 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 170983 | GIR_RootConstrainSelectedInstOperands, |
| 170984 | // GIR_Coverage, 5118, |
| 170985 | GIR_EraseRootFromParent_Done, |
| 170986 | // Label 8023: @539595 |
| 170987 | GIM_Try, /*On fail goto*//*Label 8024*/ GIMT_Encode4(539695), // Rule ID 5122 // |
| 170988 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 170989 | // MIs[0] offset |
| 170990 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 170991 | // MIs[0] auxiliary |
| 170992 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 170993 | // MIs[0] Operand 7 |
| 170994 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 170995 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 170996 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 170997 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 170998 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 170999 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171000 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171001 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171002 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171003 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171004 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171006 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171007 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 171008 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171009 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171010 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171012 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171013 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171016 | GIR_RootConstrainSelectedInstOperands, |
| 171017 | // GIR_Coverage, 5122, |
| 171018 | GIR_EraseRootFromParent_Done, |
| 171019 | // Label 8024: @539695 |
| 171020 | GIM_Try, /*On fail goto*//*Label 8025*/ GIMT_Encode4(539792), // Rule ID 5126 // |
| 171021 | // MIs[0] offset |
| 171022 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171023 | // MIs[0] auxiliary |
| 171024 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171025 | // MIs[0] Operand 7 |
| 171026 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171027 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171028 | // (SIbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171029 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171030 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171031 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171032 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171033 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171034 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171035 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171036 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171037 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171038 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171039 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 171040 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171041 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171042 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171043 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171044 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171045 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171046 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171047 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171048 | GIR_RootConstrainSelectedInstOperands, |
| 171049 | // GIR_Coverage, 5126, |
| 171050 | GIR_EraseRootFromParent_Done, |
| 171051 | // Label 8025: @539792 |
| 171052 | GIM_Reject, |
| 171053 | // Label 8009: @539793 |
| 171054 | GIM_Reject, |
| 171055 | // Label 7899: @539794 |
| 171056 | GIM_Try, /*On fail goto*//*Label 8026*/ GIMT_Encode4(541004), |
| 171057 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 171058 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 171059 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 171060 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 171061 | GIM_Try, /*On fail goto*//*Label 8027*/ GIMT_Encode4(539883), // Rule ID 5191 // |
| 171062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171063 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171064 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171065 | // MIs[0] offset |
| 171066 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171067 | // MIs[0] auxiliary |
| 171068 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171069 | // MIs[0] Operand 7 |
| 171070 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171071 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171072 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v2i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171073 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 171074 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171075 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171076 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171077 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171078 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171079 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171080 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171081 | GIR_RootConstrainSelectedInstOperands, |
| 171082 | // GIR_Coverage, 5191, |
| 171083 | GIR_EraseRootFromParent_Done, |
| 171084 | // Label 8027: @539883 |
| 171085 | GIM_Try, /*On fail goto*//*Label 8028*/ GIMT_Encode4(539952), // Rule ID 5195 // |
| 171086 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171087 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171088 | // MIs[0] offset |
| 171089 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171090 | // MIs[0] auxiliary |
| 171091 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171092 | // MIs[0] Operand 7 |
| 171093 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171094 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171095 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v2i64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 171097 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171098 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171099 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171100 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171101 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171102 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171103 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171104 | GIR_RootConstrainSelectedInstOperands, |
| 171105 | // GIR_Coverage, 5195, |
| 171106 | GIR_EraseRootFromParent_Done, |
| 171107 | // Label 8028: @539952 |
| 171108 | GIM_Try, /*On fail goto*//*Label 8029*/ GIMT_Encode4(540024), // Rule ID 5199 // |
| 171109 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171110 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171111 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171112 | // MIs[0] offset |
| 171113 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171114 | // MIs[0] auxiliary |
| 171115 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171116 | // MIs[0] Operand 7 |
| 171117 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171118 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171119 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v2f64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171120 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 171121 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171122 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171124 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171125 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171126 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171127 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171128 | GIR_RootConstrainSelectedInstOperands, |
| 171129 | // GIR_Coverage, 5199, |
| 171130 | GIR_EraseRootFromParent_Done, |
| 171131 | // Label 8029: @540024 |
| 171132 | GIM_Try, /*On fail goto*//*Label 8030*/ GIMT_Encode4(540093), // Rule ID 5203 // |
| 171133 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171134 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171135 | // MIs[0] offset |
| 171136 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171137 | // MIs[0] auxiliary |
| 171138 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171139 | // MIs[0] Operand 7 |
| 171140 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171142 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v2f64] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 171144 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171145 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171147 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171149 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171151 | GIR_RootConstrainSelectedInstOperands, |
| 171152 | // GIR_Coverage, 5203, |
| 171153 | GIR_EraseRootFromParent_Done, |
| 171154 | // Label 8030: @540093 |
| 171155 | GIM_Try, /*On fail goto*//*Label 8031*/ GIMT_Encode4(540163), // Rule ID 5192 // |
| 171156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171157 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171158 | // MIs[0] offset |
| 171159 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171160 | // MIs[0] auxiliary |
| 171161 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171162 | // MIs[0] Operand 7 |
| 171163 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171165 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 171167 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171168 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171169 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171171 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171172 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171173 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171174 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171175 | GIR_RootConstrainSelectedInstOperands, |
| 171176 | // GIR_Coverage, 5192, |
| 171177 | GIR_EraseRootFromParent_Done, |
| 171178 | // Label 8031: @540163 |
| 171179 | GIM_Try, /*On fail goto*//*Label 8032*/ GIMT_Encode4(540230), // Rule ID 5196 // |
| 171180 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171181 | // MIs[0] offset |
| 171182 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171183 | // MIs[0] auxiliary |
| 171184 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171185 | // MIs[0] Operand 7 |
| 171186 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171188 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 171190 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171191 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171192 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171194 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171196 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171197 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171198 | GIR_RootConstrainSelectedInstOperands, |
| 171199 | // GIR_Coverage, 5196, |
| 171200 | GIR_EraseRootFromParent_Done, |
| 171201 | // Label 8032: @540230 |
| 171202 | GIM_Try, /*On fail goto*//*Label 8033*/ GIMT_Encode4(540300), // Rule ID 5200 // |
| 171203 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171204 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171205 | // MIs[0] offset |
| 171206 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171207 | // MIs[0] auxiliary |
| 171208 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171209 | // MIs[0] Operand 7 |
| 171210 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171211 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171212 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171213 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 171214 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171215 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171216 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171217 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171218 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171219 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171220 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171221 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171222 | GIR_RootConstrainSelectedInstOperands, |
| 171223 | // GIR_Coverage, 5200, |
| 171224 | GIR_EraseRootFromParent_Done, |
| 171225 | // Label 8033: @540300 |
| 171226 | GIM_Try, /*On fail goto*//*Label 8034*/ GIMT_Encode4(540367), // Rule ID 5204 // |
| 171227 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171228 | // MIs[0] offset |
| 171229 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171230 | // MIs[0] auxiliary |
| 171231 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171232 | // MIs[0] Operand 7 |
| 171233 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171235 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 171237 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171238 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171239 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171241 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171242 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171243 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171245 | GIR_RootConstrainSelectedInstOperands, |
| 171246 | // GIR_Coverage, 5204, |
| 171247 | GIR_EraseRootFromParent_Done, |
| 171248 | // Label 8034: @540367 |
| 171249 | GIM_Try, /*On fail goto*//*Label 8035*/ GIMT_Encode4(540429), // Rule ID 5193 // |
| 171250 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171251 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171252 | // MIs[0] offset |
| 171253 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171254 | // MIs[0] auxiliary |
| 171255 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171256 | // MIs[0] Operand 7 |
| 171257 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171258 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171259 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171260 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 171261 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171262 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171263 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171264 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171265 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171266 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171267 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171268 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171269 | GIR_RootConstrainSelectedInstOperands, |
| 171270 | // GIR_Coverage, 5193, |
| 171271 | GIR_EraseRootFromParent_Done, |
| 171272 | // Label 8035: @540429 |
| 171273 | GIM_Try, /*On fail goto*//*Label 8036*/ GIMT_Encode4(540488), // Rule ID 5197 // |
| 171274 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171275 | // MIs[0] offset |
| 171276 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171277 | // MIs[0] auxiliary |
| 171278 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171279 | // MIs[0] Operand 7 |
| 171280 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171281 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171282 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171283 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 171284 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171285 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171286 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171287 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171288 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171289 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171290 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171291 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171292 | GIR_RootConstrainSelectedInstOperands, |
| 171293 | // GIR_Coverage, 5197, |
| 171294 | GIR_EraseRootFromParent_Done, |
| 171295 | // Label 8036: @540488 |
| 171296 | GIM_Try, /*On fail goto*//*Label 8037*/ GIMT_Encode4(540550), // Rule ID 5201 // |
| 171297 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171298 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171299 | // MIs[0] offset |
| 171300 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171301 | // MIs[0] auxiliary |
| 171302 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171303 | // MIs[0] Operand 7 |
| 171304 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171306 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 171308 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171309 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171310 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171312 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171313 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171314 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171316 | GIR_RootConstrainSelectedInstOperands, |
| 171317 | // GIR_Coverage, 5201, |
| 171318 | GIR_EraseRootFromParent_Done, |
| 171319 | // Label 8037: @540550 |
| 171320 | GIM_Try, /*On fail goto*//*Label 8038*/ GIMT_Encode4(540609), // Rule ID 5205 // |
| 171321 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171322 | // MIs[0] offset |
| 171323 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171324 | // MIs[0] auxiliary |
| 171325 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171326 | // MIs[0] Operand 7 |
| 171327 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171328 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171329 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171330 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 171331 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171332 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171333 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171334 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171335 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171336 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171337 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171338 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171339 | GIR_RootConstrainSelectedInstOperands, |
| 171340 | // GIR_Coverage, 5205, |
| 171341 | GIR_EraseRootFromParent_Done, |
| 171342 | // Label 8038: @540609 |
| 171343 | GIM_Try, /*On fail goto*//*Label 8039*/ GIMT_Encode4(540709), // Rule ID 5194 // |
| 171344 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171345 | // MIs[0] offset |
| 171346 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171347 | // MIs[0] auxiliary |
| 171348 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171349 | // MIs[0] Operand 7 |
| 171350 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171351 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171352 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171353 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171354 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171355 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171356 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171357 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171358 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171359 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171360 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171361 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171362 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 171364 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171365 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171366 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171368 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171370 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171372 | GIR_RootConstrainSelectedInstOperands, |
| 171373 | // GIR_Coverage, 5194, |
| 171374 | GIR_EraseRootFromParent_Done, |
| 171375 | // Label 8039: @540709 |
| 171376 | GIM_Try, /*On fail goto*//*Label 8040*/ GIMT_Encode4(540806), // Rule ID 5198 // |
| 171377 | // MIs[0] offset |
| 171378 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171379 | // MIs[0] auxiliary |
| 171380 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171381 | // MIs[0] Operand 7 |
| 171382 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171384 | // (SIbuffer_store v2i64:{ *:[v2i64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v2i64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171385 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171386 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171387 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171388 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171389 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171390 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171391 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171392 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171393 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171394 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171395 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 171396 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171397 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171398 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171399 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171400 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171401 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171402 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171403 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171404 | GIR_RootConstrainSelectedInstOperands, |
| 171405 | // GIR_Coverage, 5198, |
| 171406 | GIR_EraseRootFromParent_Done, |
| 171407 | // Label 8040: @540806 |
| 171408 | GIM_Try, /*On fail goto*//*Label 8041*/ GIMT_Encode4(540906), // Rule ID 5202 // |
| 171409 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171410 | // MIs[0] offset |
| 171411 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171412 | // MIs[0] auxiliary |
| 171413 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171414 | // MIs[0] Operand 7 |
| 171415 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171416 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171417 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171418 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171419 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171420 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171421 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171422 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171423 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171424 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171425 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171426 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171427 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171428 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 171429 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171430 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171431 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171432 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171433 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171434 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171435 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171436 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171437 | GIR_RootConstrainSelectedInstOperands, |
| 171438 | // GIR_Coverage, 5202, |
| 171439 | GIR_EraseRootFromParent_Done, |
| 171440 | // Label 8041: @540906 |
| 171441 | GIM_Try, /*On fail goto*//*Label 8042*/ GIMT_Encode4(541003), // Rule ID 5206 // |
| 171442 | // MIs[0] offset |
| 171443 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171444 | // MIs[0] auxiliary |
| 171445 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171446 | // MIs[0] Operand 7 |
| 171447 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171449 | // (SIbuffer_store v2f64:{ *:[v2f64] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v2f64] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171450 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171451 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171452 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171453 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171454 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171455 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171456 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171457 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171458 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171459 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 171461 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171462 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171463 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171465 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171466 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171469 | GIR_RootConstrainSelectedInstOperands, |
| 171470 | // GIR_Coverage, 5206, |
| 171471 | GIR_EraseRootFromParent_Done, |
| 171472 | // Label 8042: @541003 |
| 171473 | GIM_Reject, |
| 171474 | // Label 8026: @541004 |
| 171475 | GIM_Reject, |
| 171476 | // Label 7900: @541005 |
| 171477 | GIM_Try, /*On fail goto*//*Label 8043*/ GIMT_Encode4(542215), |
| 171478 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 171479 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 171480 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 171481 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 171482 | GIM_Try, /*On fail goto*//*Label 8044*/ GIMT_Encode4(541094), // Rule ID 5159 // |
| 171483 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171484 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171485 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171486 | // MIs[0] offset |
| 171487 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171488 | // MIs[0] auxiliary |
| 171489 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171490 | // MIs[0] Operand 7 |
| 171491 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171492 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171493 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_exact), |
| 171495 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171496 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171497 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171498 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171499 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171500 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171501 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171502 | GIR_RootConstrainSelectedInstOperands, |
| 171503 | // GIR_Coverage, 5159, |
| 171504 | GIR_EraseRootFromParent_Done, |
| 171505 | // Label 8044: @541094 |
| 171506 | GIM_Try, /*On fail goto*//*Label 8045*/ GIMT_Encode4(541163), // Rule ID 5163 // |
| 171507 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171508 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171509 | // MIs[0] offset |
| 171510 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171511 | // MIs[0] auxiliary |
| 171512 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171513 | // MIs[0] Operand 7 |
| 171514 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171515 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171516 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171517 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact), |
| 171518 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171519 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171521 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171522 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171523 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171524 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171525 | GIR_RootConstrainSelectedInstOperands, |
| 171526 | // GIR_Coverage, 5163, |
| 171527 | GIR_EraseRootFromParent_Done, |
| 171528 | // Label 8045: @541163 |
| 171529 | GIM_Try, /*On fail goto*//*Label 8046*/ GIMT_Encode4(541235), // Rule ID 5167 // |
| 171530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171531 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171532 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171533 | // MIs[0] offset |
| 171534 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171535 | // MIs[0] auxiliary |
| 171536 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171537 | // MIs[0] Operand 7 |
| 171538 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171539 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171540 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171541 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFSET_exact), |
| 171542 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171543 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171545 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171546 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171547 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171548 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171549 | GIR_RootConstrainSelectedInstOperands, |
| 171550 | // GIR_Coverage, 5167, |
| 171551 | GIR_EraseRootFromParent_Done, |
| 171552 | // Label 8046: @541235 |
| 171553 | GIM_Try, /*On fail goto*//*Label 8047*/ GIMT_Encode4(541304), // Rule ID 5171 // |
| 171554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171555 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171556 | // MIs[0] offset |
| 171557 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171558 | // MIs[0] auxiliary |
| 171559 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171560 | // MIs[0] Operand 7 |
| 171561 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171563 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171564 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFSET_exact), |
| 171565 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171566 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171568 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171569 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171570 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171571 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171572 | GIR_RootConstrainSelectedInstOperands, |
| 171573 | // GIR_Coverage, 5171, |
| 171574 | GIR_EraseRootFromParent_Done, |
| 171575 | // Label 8047: @541304 |
| 171576 | GIM_Try, /*On fail goto*//*Label 8048*/ GIMT_Encode4(541374), // Rule ID 5160 // |
| 171577 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171578 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171579 | // MIs[0] offset |
| 171580 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171581 | // MIs[0] auxiliary |
| 171582 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171583 | // MIs[0] Operand 7 |
| 171584 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171585 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171586 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_exact), |
| 171588 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171589 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171590 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171592 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171595 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171596 | GIR_RootConstrainSelectedInstOperands, |
| 171597 | // GIR_Coverage, 5160, |
| 171598 | GIR_EraseRootFromParent_Done, |
| 171599 | // Label 8048: @541374 |
| 171600 | GIM_Try, /*On fail goto*//*Label 8049*/ GIMT_Encode4(541441), // Rule ID 5164 // |
| 171601 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171602 | // MIs[0] offset |
| 171603 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171604 | // MIs[0] auxiliary |
| 171605 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171606 | // MIs[0] Operand 7 |
| 171607 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171608 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171609 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171610 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact), |
| 171611 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171612 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171613 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171615 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171616 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171618 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171619 | GIR_RootConstrainSelectedInstOperands, |
| 171620 | // GIR_Coverage, 5164, |
| 171621 | GIR_EraseRootFromParent_Done, |
| 171622 | // Label 8049: @541441 |
| 171623 | GIM_Try, /*On fail goto*//*Label 8050*/ GIMT_Encode4(541511), // Rule ID 5168 // |
| 171624 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171625 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171626 | // MIs[0] offset |
| 171627 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171628 | // MIs[0] auxiliary |
| 171629 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171630 | // MIs[0] Operand 7 |
| 171631 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171632 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171633 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171634 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_OFFEN_exact), |
| 171635 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171636 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171637 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171638 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171639 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171640 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171641 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171642 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171643 | GIR_RootConstrainSelectedInstOperands, |
| 171644 | // GIR_Coverage, 5168, |
| 171645 | GIR_EraseRootFromParent_Done, |
| 171646 | // Label 8050: @541511 |
| 171647 | GIM_Try, /*On fail goto*//*Label 8051*/ GIMT_Encode4(541578), // Rule ID 5172 // |
| 171648 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171649 | // MIs[0] offset |
| 171650 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171651 | // MIs[0] auxiliary |
| 171652 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171653 | // MIs[0] Operand 7 |
| 171654 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171655 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171656 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_OFFEN_exact), |
| 171658 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171659 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 171660 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171662 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171663 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171664 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171666 | GIR_RootConstrainSelectedInstOperands, |
| 171667 | // GIR_Coverage, 5172, |
| 171668 | GIR_EraseRootFromParent_Done, |
| 171669 | // Label 8051: @541578 |
| 171670 | GIM_Try, /*On fail goto*//*Label 8052*/ GIMT_Encode4(541640), // Rule ID 5161 // |
| 171671 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171672 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171673 | // MIs[0] offset |
| 171674 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171675 | // MIs[0] auxiliary |
| 171676 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171677 | // MIs[0] Operand 7 |
| 171678 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171679 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171680 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171681 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_exact), |
| 171682 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171683 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171684 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171685 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171686 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171687 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171688 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171690 | GIR_RootConstrainSelectedInstOperands, |
| 171691 | // GIR_Coverage, 5161, |
| 171692 | GIR_EraseRootFromParent_Done, |
| 171693 | // Label 8052: @541640 |
| 171694 | GIM_Try, /*On fail goto*//*Label 8053*/ GIMT_Encode4(541699), // Rule ID 5165 // |
| 171695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171696 | // MIs[0] offset |
| 171697 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171698 | // MIs[0] auxiliary |
| 171699 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171700 | // MIs[0] Operand 7 |
| 171701 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171703 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact), |
| 171705 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171706 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171707 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171709 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171710 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171713 | GIR_RootConstrainSelectedInstOperands, |
| 171714 | // GIR_Coverage, 5165, |
| 171715 | GIR_EraseRootFromParent_Done, |
| 171716 | // Label 8053: @541699 |
| 171717 | GIM_Try, /*On fail goto*//*Label 8054*/ GIMT_Encode4(541761), // Rule ID 5169 // |
| 171718 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171719 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171720 | // MIs[0] offset |
| 171721 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171722 | // MIs[0] auxiliary |
| 171723 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171724 | // MIs[0] Operand 7 |
| 171725 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171726 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171727 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171728 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_IDXEN_exact), |
| 171729 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171730 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171731 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171732 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171733 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171734 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171735 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171736 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171737 | GIR_RootConstrainSelectedInstOperands, |
| 171738 | // GIR_Coverage, 5169, |
| 171739 | GIR_EraseRootFromParent_Done, |
| 171740 | // Label 8054: @541761 |
| 171741 | GIM_Try, /*On fail goto*//*Label 8055*/ GIMT_Encode4(541820), // Rule ID 5173 // |
| 171742 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171743 | // MIs[0] offset |
| 171744 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171745 | // MIs[0] auxiliary |
| 171746 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171747 | // MIs[0] Operand 7 |
| 171748 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171750 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_IDXEN_exact), |
| 171752 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171753 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 171754 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171755 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171756 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171757 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171758 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171760 | GIR_RootConstrainSelectedInstOperands, |
| 171761 | // GIR_Coverage, 5173, |
| 171762 | GIR_EraseRootFromParent_Done, |
| 171763 | // Label 8055: @541820 |
| 171764 | GIM_Try, /*On fail goto*//*Label 8056*/ GIMT_Encode4(541920), // Rule ID 5162 // |
| 171765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171766 | // MIs[0] offset |
| 171767 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171768 | // MIs[0] auxiliary |
| 171769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171770 | // MIs[0] Operand 7 |
| 171771 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171773 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171774 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171775 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171776 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171777 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171778 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171779 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171780 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171781 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171782 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171783 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_exact), |
| 171785 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171786 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171787 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171789 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171790 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171791 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171792 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171793 | GIR_RootConstrainSelectedInstOperands, |
| 171794 | // GIR_Coverage, 5162, |
| 171795 | GIR_EraseRootFromParent_Done, |
| 171796 | // Label 8056: @541920 |
| 171797 | GIM_Try, /*On fail goto*//*Label 8057*/ GIMT_Encode4(542017), // Rule ID 5166 // |
| 171798 | // MIs[0] offset |
| 171799 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171800 | // MIs[0] auxiliary |
| 171801 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171802 | // MIs[0] Operand 7 |
| 171803 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171804 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171805 | // (SIbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171806 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171807 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171808 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171809 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171810 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171811 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171812 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171813 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171814 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171815 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171816 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact), |
| 171817 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171818 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171819 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171820 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171821 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171822 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171823 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171824 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171825 | GIR_RootConstrainSelectedInstOperands, |
| 171826 | // GIR_Coverage, 5166, |
| 171827 | GIR_EraseRootFromParent_Done, |
| 171828 | // Label 8057: @542017 |
| 171829 | GIM_Try, /*On fail goto*//*Label 8058*/ GIMT_Encode4(542117), // Rule ID 5170 // |
| 171830 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171831 | // MIs[0] offset |
| 171832 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171833 | // MIs[0] auxiliary |
| 171834 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171835 | // MIs[0] Operand 7 |
| 171836 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171838 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171842 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171843 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171844 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171845 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171846 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171847 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171848 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_BOTHEN_exact), |
| 171850 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171851 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171852 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171854 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171856 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171857 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171858 | GIR_RootConstrainSelectedInstOperands, |
| 171859 | // GIR_Coverage, 5170, |
| 171860 | GIR_EraseRootFromParent_Done, |
| 171861 | // Label 8058: @542117 |
| 171862 | GIM_Try, /*On fail goto*//*Label 8059*/ GIMT_Encode4(542214), // Rule ID 5174 // |
| 171863 | // MIs[0] offset |
| 171864 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171865 | // MIs[0] auxiliary |
| 171866 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171867 | // MIs[0] Operand 7 |
| 171868 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 171869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171870 | // (SIbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171871 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 171872 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 171873 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 171874 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 171875 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 171876 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 171877 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 171878 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 171879 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171880 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 171881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX3_VBUFFER_BOTHEN_exact), |
| 171882 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171883 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 171884 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171886 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171887 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171888 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171889 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171890 | GIR_RootConstrainSelectedInstOperands, |
| 171891 | // GIR_Coverage, 5174, |
| 171892 | GIR_EraseRootFromParent_Done, |
| 171893 | // Label 8059: @542214 |
| 171894 | GIM_Reject, |
| 171895 | // Label 8043: @542215 |
| 171896 | GIM_Reject, |
| 171897 | // Label 7901: @542216 |
| 171898 | GIM_Try, /*On fail goto*//*Label 8060*/ GIMT_Encode4(544022), |
| 171899 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 171900 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 171901 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 171902 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 171903 | GIM_Try, /*On fail goto*//*Label 8061*/ GIMT_Encode4(542305), // Rule ID 5135 // |
| 171904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171905 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171906 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171907 | // MIs[0] offset |
| 171908 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171909 | // MIs[0] auxiliary |
| 171910 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171911 | // MIs[0] Operand 7 |
| 171912 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171913 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171914 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171915 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 171916 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171917 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171918 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171919 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171920 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171921 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171922 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171923 | GIR_RootConstrainSelectedInstOperands, |
| 171924 | // GIR_Coverage, 5135, |
| 171925 | GIR_EraseRootFromParent_Done, |
| 171926 | // Label 8061: @542305 |
| 171927 | GIM_Try, /*On fail goto*//*Label 8062*/ GIMT_Encode4(542374), // Rule ID 5139 // |
| 171928 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171929 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171930 | // MIs[0] offset |
| 171931 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171932 | // MIs[0] auxiliary |
| 171933 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171934 | // MIs[0] Operand 7 |
| 171935 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171936 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171937 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171938 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 171939 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171940 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171941 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171942 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171943 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171944 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171945 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171946 | GIR_RootConstrainSelectedInstOperands, |
| 171947 | // GIR_Coverage, 5139, |
| 171948 | GIR_EraseRootFromParent_Done, |
| 171949 | // Label 8062: @542374 |
| 171950 | GIM_Try, /*On fail goto*//*Label 8063*/ GIMT_Encode4(542446), // Rule ID 5143 // |
| 171951 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171952 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171953 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171954 | // MIs[0] offset |
| 171955 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171956 | // MIs[0] auxiliary |
| 171957 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171958 | // MIs[0] Operand 7 |
| 171959 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171960 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171961 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171962 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 171963 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171964 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171966 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171967 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171969 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171970 | GIR_RootConstrainSelectedInstOperands, |
| 171971 | // GIR_Coverage, 5143, |
| 171972 | GIR_EraseRootFromParent_Done, |
| 171973 | // Label 8063: @542446 |
| 171974 | GIM_Try, /*On fail goto*//*Label 8064*/ GIMT_Encode4(542515), // Rule ID 5147 // |
| 171975 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 171976 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 171977 | // MIs[0] offset |
| 171978 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 171979 | // MIs[0] auxiliary |
| 171980 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 171981 | // MIs[0] Operand 7 |
| 171982 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 171983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 171984 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 171985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 171986 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 171987 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 171988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 171989 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 171990 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 171991 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 171992 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 171993 | GIR_RootConstrainSelectedInstOperands, |
| 171994 | // GIR_Coverage, 5147, |
| 171995 | GIR_EraseRootFromParent_Done, |
| 171996 | // Label 8064: @542515 |
| 171997 | GIM_Try, /*On fail goto*//*Label 8065*/ GIMT_Encode4(542587), // Rule ID 5151 // |
| 171998 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 171999 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172000 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172001 | // MIs[0] offset |
| 172002 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172003 | // MIs[0] auxiliary |
| 172004 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172005 | // MIs[0] Operand 7 |
| 172006 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172007 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172008 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFSET_exact anonymous_15875:{ *:[v4bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172009 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFSET_exact), |
| 172010 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172011 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172013 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172017 | GIR_RootConstrainSelectedInstOperands, |
| 172018 | // GIR_Coverage, 5151, |
| 172019 | GIR_EraseRootFromParent_Done, |
| 172020 | // Label 8065: @542587 |
| 172021 | GIM_Try, /*On fail goto*//*Label 8066*/ GIMT_Encode4(542656), // Rule ID 5155 // |
| 172022 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172023 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172024 | // MIs[0] offset |
| 172025 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172026 | // MIs[0] auxiliary |
| 172027 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172028 | // MIs[0] Operand 7 |
| 172029 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172031 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172032 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFSET_exact), |
| 172033 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172034 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172035 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172036 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172037 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172038 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172039 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172040 | GIR_RootConstrainSelectedInstOperands, |
| 172041 | // GIR_Coverage, 5155, |
| 172042 | GIR_EraseRootFromParent_Done, |
| 172043 | // Label 8066: @542656 |
| 172044 | GIM_Try, /*On fail goto*//*Label 8067*/ GIMT_Encode4(542726), // Rule ID 5136 // |
| 172045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172046 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172047 | // MIs[0] offset |
| 172048 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172049 | // MIs[0] auxiliary |
| 172050 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172051 | // MIs[0] Operand 7 |
| 172052 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172054 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 172056 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172057 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172058 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172059 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172060 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172061 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172064 | GIR_RootConstrainSelectedInstOperands, |
| 172065 | // GIR_Coverage, 5136, |
| 172066 | GIR_EraseRootFromParent_Done, |
| 172067 | // Label 8067: @542726 |
| 172068 | GIM_Try, /*On fail goto*//*Label 8068*/ GIMT_Encode4(542793), // Rule ID 5140 // |
| 172069 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172070 | // MIs[0] offset |
| 172071 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172072 | // MIs[0] auxiliary |
| 172073 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172074 | // MIs[0] Operand 7 |
| 172075 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172076 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172077 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172078 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 172079 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172080 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172081 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172082 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172083 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172084 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172085 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172086 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172087 | GIR_RootConstrainSelectedInstOperands, |
| 172088 | // GIR_Coverage, 5140, |
| 172089 | GIR_EraseRootFromParent_Done, |
| 172090 | // Label 8068: @542793 |
| 172091 | GIM_Try, /*On fail goto*//*Label 8069*/ GIMT_Encode4(542863), // Rule ID 5144 // |
| 172092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172093 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172094 | // MIs[0] offset |
| 172095 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172096 | // MIs[0] auxiliary |
| 172097 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172098 | // MIs[0] Operand 7 |
| 172099 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172100 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172101 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 172103 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172104 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172105 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172107 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172108 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172110 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172111 | GIR_RootConstrainSelectedInstOperands, |
| 172112 | // GIR_Coverage, 5144, |
| 172113 | GIR_EraseRootFromParent_Done, |
| 172114 | // Label 8069: @542863 |
| 172115 | GIM_Try, /*On fail goto*//*Label 8070*/ GIMT_Encode4(542930), // Rule ID 5148 // |
| 172116 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172117 | // MIs[0] offset |
| 172118 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172119 | // MIs[0] auxiliary |
| 172120 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172121 | // MIs[0] Operand 7 |
| 172122 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172123 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172124 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172125 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 172126 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172127 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172128 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172129 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172130 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172131 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172132 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172133 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172134 | GIR_RootConstrainSelectedInstOperands, |
| 172135 | // GIR_Coverage, 5148, |
| 172136 | GIR_EraseRootFromParent_Done, |
| 172137 | // Label 8070: @542930 |
| 172138 | GIM_Try, /*On fail goto*//*Label 8071*/ GIMT_Encode4(543000), // Rule ID 5152 // |
| 172139 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172140 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172141 | // MIs[0] offset |
| 172142 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172143 | // MIs[0] auxiliary |
| 172144 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172145 | // MIs[0] Operand 7 |
| 172146 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172148 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_OFFEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_OFFEN_exact), |
| 172150 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172151 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172152 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172154 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172155 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172158 | GIR_RootConstrainSelectedInstOperands, |
| 172159 | // GIR_Coverage, 5152, |
| 172160 | GIR_EraseRootFromParent_Done, |
| 172161 | // Label 8071: @543000 |
| 172162 | GIM_Try, /*On fail goto*//*Label 8072*/ GIMT_Encode4(543067), // Rule ID 5156 // |
| 172163 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172164 | // MIs[0] offset |
| 172165 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172166 | // MIs[0] auxiliary |
| 172167 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172168 | // MIs[0] Operand 7 |
| 172169 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172170 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172171 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_OFFEN_exact), |
| 172173 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172174 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172175 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172177 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172178 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172180 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172181 | GIR_RootConstrainSelectedInstOperands, |
| 172182 | // GIR_Coverage, 5156, |
| 172183 | GIR_EraseRootFromParent_Done, |
| 172184 | // Label 8072: @543067 |
| 172185 | GIM_Try, /*On fail goto*//*Label 8073*/ GIMT_Encode4(543129), // Rule ID 5137 // |
| 172186 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172187 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172188 | // MIs[0] offset |
| 172189 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172190 | // MIs[0] auxiliary |
| 172191 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172192 | // MIs[0] Operand 7 |
| 172193 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172194 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172195 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172196 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 172197 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172198 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172199 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172200 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172201 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172202 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172203 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172204 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172205 | GIR_RootConstrainSelectedInstOperands, |
| 172206 | // GIR_Coverage, 5137, |
| 172207 | GIR_EraseRootFromParent_Done, |
| 172208 | // Label 8073: @543129 |
| 172209 | GIM_Try, /*On fail goto*//*Label 8074*/ GIMT_Encode4(543188), // Rule ID 5141 // |
| 172210 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172211 | // MIs[0] offset |
| 172212 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172213 | // MIs[0] auxiliary |
| 172214 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172215 | // MIs[0] Operand 7 |
| 172216 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172218 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 172220 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172221 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172222 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172224 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172225 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172226 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172227 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172228 | GIR_RootConstrainSelectedInstOperands, |
| 172229 | // GIR_Coverage, 5141, |
| 172230 | GIR_EraseRootFromParent_Done, |
| 172231 | // Label 8074: @543188 |
| 172232 | GIM_Try, /*On fail goto*//*Label 8075*/ GIMT_Encode4(543250), // Rule ID 5145 // |
| 172233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172234 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172235 | // MIs[0] offset |
| 172236 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172237 | // MIs[0] auxiliary |
| 172238 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172239 | // MIs[0] Operand 7 |
| 172240 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172242 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 172244 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172245 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172246 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172248 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172249 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172250 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172251 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172252 | GIR_RootConstrainSelectedInstOperands, |
| 172253 | // GIR_Coverage, 5145, |
| 172254 | GIR_EraseRootFromParent_Done, |
| 172255 | // Label 8075: @543250 |
| 172256 | GIM_Try, /*On fail goto*//*Label 8076*/ GIMT_Encode4(543309), // Rule ID 5149 // |
| 172257 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172258 | // MIs[0] offset |
| 172259 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172260 | // MIs[0] auxiliary |
| 172261 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172262 | // MIs[0] Operand 7 |
| 172263 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172265 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 172267 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172268 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172269 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172271 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172272 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172273 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172274 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172275 | GIR_RootConstrainSelectedInstOperands, |
| 172276 | // GIR_Coverage, 5149, |
| 172277 | GIR_EraseRootFromParent_Done, |
| 172278 | // Label 8076: @543309 |
| 172279 | GIM_Try, /*On fail goto*//*Label 8077*/ GIMT_Encode4(543371), // Rule ID 5153 // |
| 172280 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172281 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172282 | // MIs[0] offset |
| 172283 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172284 | // MIs[0] auxiliary |
| 172285 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172286 | // MIs[0] Operand 7 |
| 172287 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172288 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172289 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_IDXEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_IDXEN_exact), |
| 172291 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172292 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172293 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172295 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172296 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172298 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172299 | GIR_RootConstrainSelectedInstOperands, |
| 172300 | // GIR_Coverage, 5153, |
| 172301 | GIR_EraseRootFromParent_Done, |
| 172302 | // Label 8077: @543371 |
| 172303 | GIM_Try, /*On fail goto*//*Label 8078*/ GIMT_Encode4(543430), // Rule ID 5157 // |
| 172304 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172305 | // MIs[0] offset |
| 172306 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172307 | // MIs[0] auxiliary |
| 172308 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172309 | // MIs[0] Operand 7 |
| 172310 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172311 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172312 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_IDXEN_exact), |
| 172314 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172315 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172316 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172318 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172319 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172320 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172321 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172322 | GIR_RootConstrainSelectedInstOperands, |
| 172323 | // GIR_Coverage, 5157, |
| 172324 | GIR_EraseRootFromParent_Done, |
| 172325 | // Label 8078: @543430 |
| 172326 | GIM_Try, /*On fail goto*//*Label 8079*/ GIMT_Encode4(543530), // Rule ID 5138 // |
| 172327 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172328 | // MIs[0] offset |
| 172329 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172330 | // MIs[0] auxiliary |
| 172331 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172332 | // MIs[0] Operand 7 |
| 172333 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172334 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172335 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172336 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172337 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172338 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172339 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172340 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172341 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172342 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172343 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172344 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172345 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 172347 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172348 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172349 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172350 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172351 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172353 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172354 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172355 | GIR_RootConstrainSelectedInstOperands, |
| 172356 | // GIR_Coverage, 5138, |
| 172357 | GIR_EraseRootFromParent_Done, |
| 172358 | // Label 8079: @543530 |
| 172359 | GIM_Try, /*On fail goto*//*Label 8080*/ GIMT_Encode4(543627), // Rule ID 5142 // |
| 172360 | // MIs[0] offset |
| 172361 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172362 | // MIs[0] auxiliary |
| 172363 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172364 | // MIs[0] Operand 7 |
| 172365 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172366 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172367 | // (SIbuffer_store v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172368 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172369 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172370 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172371 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172372 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172373 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172374 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172375 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172376 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172377 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172378 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 172379 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172380 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172381 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172382 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172383 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172384 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172385 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172387 | GIR_RootConstrainSelectedInstOperands, |
| 172388 | // GIR_Coverage, 5142, |
| 172389 | GIR_EraseRootFromParent_Done, |
| 172390 | // Label 8080: @543627 |
| 172391 | GIM_Try, /*On fail goto*//*Label 8081*/ GIMT_Encode4(543727), // Rule ID 5146 // |
| 172392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172393 | // MIs[0] offset |
| 172394 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172395 | // MIs[0] auxiliary |
| 172396 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172397 | // MIs[0] Operand 7 |
| 172398 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172399 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172400 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172401 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172402 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172403 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172404 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172405 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172406 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172407 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172408 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172409 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172410 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172411 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 172412 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172413 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172414 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172415 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172416 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172418 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172420 | GIR_RootConstrainSelectedInstOperands, |
| 172421 | // GIR_Coverage, 5146, |
| 172422 | GIR_EraseRootFromParent_Done, |
| 172423 | // Label 8081: @543727 |
| 172424 | GIM_Try, /*On fail goto*//*Label 8082*/ GIMT_Encode4(543824), // Rule ID 5150 // |
| 172425 | // MIs[0] offset |
| 172426 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172427 | // MIs[0] auxiliary |
| 172428 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172429 | // MIs[0] Operand 7 |
| 172430 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172432 | // (SIbuffer_store v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172433 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172434 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172435 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172436 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172437 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172438 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172439 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172440 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172441 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172442 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172443 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 172444 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172445 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172446 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172447 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172448 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172449 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172450 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172452 | GIR_RootConstrainSelectedInstOperands, |
| 172453 | // GIR_Coverage, 5150, |
| 172454 | GIR_EraseRootFromParent_Done, |
| 172455 | // Label 8082: @543824 |
| 172456 | GIM_Try, /*On fail goto*//*Label 8083*/ GIMT_Encode4(543924), // Rule ID 5154 // |
| 172457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172458 | // MIs[0] offset |
| 172459 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172460 | // MIs[0] auxiliary |
| 172461 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172462 | // MIs[0] Operand 7 |
| 172463 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172464 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172465 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_BOTHEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172466 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172467 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172468 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172469 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172470 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172471 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172472 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172473 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172474 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172475 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_BOTHEN_exact), |
| 172477 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172478 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172479 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172481 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172482 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172483 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172484 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172485 | GIR_RootConstrainSelectedInstOperands, |
| 172486 | // GIR_Coverage, 5154, |
| 172487 | GIR_EraseRootFromParent_Done, |
| 172488 | // Label 8083: @543924 |
| 172489 | GIM_Try, /*On fail goto*//*Label 8084*/ GIMT_Encode4(544021), // Rule ID 5158 // |
| 172490 | // MIs[0] offset |
| 172491 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172492 | // MIs[0] auxiliary |
| 172493 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172494 | // MIs[0] Operand 7 |
| 172495 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172497 | // (SIbuffer_store v4bf16:{ *:[v4bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172498 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172499 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172500 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172501 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172502 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172503 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172504 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172505 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172506 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172507 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX2_VBUFFER_BOTHEN_exact), |
| 172509 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172510 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172511 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172513 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172514 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172515 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172517 | GIR_RootConstrainSelectedInstOperands, |
| 172518 | // GIR_Coverage, 5158, |
| 172519 | GIR_EraseRootFromParent_Done, |
| 172520 | // Label 8084: @544021 |
| 172521 | GIM_Reject, |
| 172522 | // Label 8060: @544022 |
| 172523 | GIM_Reject, |
| 172524 | // Label 7902: @544023 |
| 172525 | GIM_Try, /*On fail goto*//*Label 8085*/ GIMT_Encode4(545233), |
| 172526 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 172527 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 172528 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 172529 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 172530 | GIM_Try, /*On fail goto*//*Label 8086*/ GIMT_Encode4(544112), // Rule ID 5175 // |
| 172531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172532 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172533 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172534 | // MIs[0] offset |
| 172535 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172536 | // MIs[0] auxiliary |
| 172537 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172538 | // MIs[0] Operand 7 |
| 172539 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172540 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172541 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172542 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 172543 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172544 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172546 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172547 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172548 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172549 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172550 | GIR_RootConstrainSelectedInstOperands, |
| 172551 | // GIR_Coverage, 5175, |
| 172552 | GIR_EraseRootFromParent_Done, |
| 172553 | // Label 8086: @544112 |
| 172554 | GIM_Try, /*On fail goto*//*Label 8087*/ GIMT_Encode4(544181), // Rule ID 5179 // |
| 172555 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172556 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172557 | // MIs[0] offset |
| 172558 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172559 | // MIs[0] auxiliary |
| 172560 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172561 | // MIs[0] Operand 7 |
| 172562 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172564 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 172566 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172567 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172569 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172570 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172572 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172573 | GIR_RootConstrainSelectedInstOperands, |
| 172574 | // GIR_Coverage, 5179, |
| 172575 | GIR_EraseRootFromParent_Done, |
| 172576 | // Label 8087: @544181 |
| 172577 | GIM_Try, /*On fail goto*//*Label 8088*/ GIMT_Encode4(544253), // Rule ID 5183 // |
| 172578 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172579 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172581 | // MIs[0] offset |
| 172582 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172583 | // MIs[0] auxiliary |
| 172584 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172585 | // MIs[0] Operand 7 |
| 172586 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172587 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172588 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172589 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 172590 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172591 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172592 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172593 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172595 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172597 | GIR_RootConstrainSelectedInstOperands, |
| 172598 | // GIR_Coverage, 5183, |
| 172599 | GIR_EraseRootFromParent_Done, |
| 172600 | // Label 8088: @544253 |
| 172601 | GIM_Try, /*On fail goto*//*Label 8089*/ GIMT_Encode4(544322), // Rule ID 5187 // |
| 172602 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172603 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172604 | // MIs[0] offset |
| 172605 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172606 | // MIs[0] auxiliary |
| 172607 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172608 | // MIs[0] Operand 7 |
| 172609 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172611 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 172613 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172614 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172616 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172617 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172618 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172619 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172620 | GIR_RootConstrainSelectedInstOperands, |
| 172621 | // GIR_Coverage, 5187, |
| 172622 | GIR_EraseRootFromParent_Done, |
| 172623 | // Label 8089: @544322 |
| 172624 | GIM_Try, /*On fail goto*//*Label 8090*/ GIMT_Encode4(544392), // Rule ID 5176 // |
| 172625 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172626 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172627 | // MIs[0] offset |
| 172628 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172629 | // MIs[0] auxiliary |
| 172630 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172631 | // MIs[0] Operand 7 |
| 172632 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172633 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172634 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172635 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 172636 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172637 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172638 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172639 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172640 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172641 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172642 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172643 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172644 | GIR_RootConstrainSelectedInstOperands, |
| 172645 | // GIR_Coverage, 5176, |
| 172646 | GIR_EraseRootFromParent_Done, |
| 172647 | // Label 8090: @544392 |
| 172648 | GIM_Try, /*On fail goto*//*Label 8091*/ GIMT_Encode4(544459), // Rule ID 5180 // |
| 172649 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172650 | // MIs[0] offset |
| 172651 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172652 | // MIs[0] auxiliary |
| 172653 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172654 | // MIs[0] Operand 7 |
| 172655 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172656 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172657 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172658 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 172659 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172660 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172661 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172662 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172663 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172664 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172665 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172666 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172667 | GIR_RootConstrainSelectedInstOperands, |
| 172668 | // GIR_Coverage, 5180, |
| 172669 | GIR_EraseRootFromParent_Done, |
| 172670 | // Label 8091: @544459 |
| 172671 | GIM_Try, /*On fail goto*//*Label 8092*/ GIMT_Encode4(544529), // Rule ID 5184 // |
| 172672 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172673 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172674 | // MIs[0] offset |
| 172675 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172676 | // MIs[0] auxiliary |
| 172677 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172678 | // MIs[0] Operand 7 |
| 172679 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172680 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172681 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 172683 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172684 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172685 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172686 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172687 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172688 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172689 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172690 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172691 | GIR_RootConstrainSelectedInstOperands, |
| 172692 | // GIR_Coverage, 5184, |
| 172693 | GIR_EraseRootFromParent_Done, |
| 172694 | // Label 8092: @544529 |
| 172695 | GIM_Try, /*On fail goto*//*Label 8093*/ GIMT_Encode4(544596), // Rule ID 5188 // |
| 172696 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172697 | // MIs[0] offset |
| 172698 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172699 | // MIs[0] auxiliary |
| 172700 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172701 | // MIs[0] Operand 7 |
| 172702 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172703 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172704 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172705 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 172706 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172707 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 172708 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172710 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172712 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172714 | GIR_RootConstrainSelectedInstOperands, |
| 172715 | // GIR_Coverage, 5188, |
| 172716 | GIR_EraseRootFromParent_Done, |
| 172717 | // Label 8093: @544596 |
| 172718 | GIM_Try, /*On fail goto*//*Label 8094*/ GIMT_Encode4(544658), // Rule ID 5177 // |
| 172719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172720 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172721 | // MIs[0] offset |
| 172722 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172723 | // MIs[0] auxiliary |
| 172724 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172725 | // MIs[0] Operand 7 |
| 172726 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172727 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172728 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172729 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 172730 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172731 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172732 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172733 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172734 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172735 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172736 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172737 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172738 | GIR_RootConstrainSelectedInstOperands, |
| 172739 | // GIR_Coverage, 5177, |
| 172740 | GIR_EraseRootFromParent_Done, |
| 172741 | // Label 8094: @544658 |
| 172742 | GIM_Try, /*On fail goto*//*Label 8095*/ GIMT_Encode4(544717), // Rule ID 5181 // |
| 172743 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172744 | // MIs[0] offset |
| 172745 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172746 | // MIs[0] auxiliary |
| 172747 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172748 | // MIs[0] Operand 7 |
| 172749 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172750 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172751 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172752 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 172753 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172754 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172755 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172756 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172757 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172758 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172759 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172760 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172761 | GIR_RootConstrainSelectedInstOperands, |
| 172762 | // GIR_Coverage, 5181, |
| 172763 | GIR_EraseRootFromParent_Done, |
| 172764 | // Label 8095: @544717 |
| 172765 | GIM_Try, /*On fail goto*//*Label 8096*/ GIMT_Encode4(544779), // Rule ID 5185 // |
| 172766 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172767 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172768 | // MIs[0] offset |
| 172769 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172770 | // MIs[0] auxiliary |
| 172771 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172772 | // MIs[0] Operand 7 |
| 172773 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172775 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 172777 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172778 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172779 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172780 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172781 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172785 | GIR_RootConstrainSelectedInstOperands, |
| 172786 | // GIR_Coverage, 5185, |
| 172787 | GIR_EraseRootFromParent_Done, |
| 172788 | // Label 8096: @544779 |
| 172789 | GIM_Try, /*On fail goto*//*Label 8097*/ GIMT_Encode4(544838), // Rule ID 5189 // |
| 172790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172791 | // MIs[0] offset |
| 172792 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172793 | // MIs[0] auxiliary |
| 172794 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172795 | // MIs[0] Operand 7 |
| 172796 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172797 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172798 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172799 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 172800 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172801 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 172802 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172803 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172804 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172805 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172806 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172807 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172808 | GIR_RootConstrainSelectedInstOperands, |
| 172809 | // GIR_Coverage, 5189, |
| 172810 | GIR_EraseRootFromParent_Done, |
| 172811 | // Label 8097: @544838 |
| 172812 | GIM_Try, /*On fail goto*//*Label 8098*/ GIMT_Encode4(544938), // Rule ID 5178 // |
| 172813 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172814 | // MIs[0] offset |
| 172815 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172816 | // MIs[0] auxiliary |
| 172817 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172818 | // MIs[0] Operand 7 |
| 172819 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172821 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172822 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172823 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172824 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172825 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172826 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172827 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172828 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172830 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172831 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 172833 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172834 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172835 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172837 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172839 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172841 | GIR_RootConstrainSelectedInstOperands, |
| 172842 | // GIR_Coverage, 5178, |
| 172843 | GIR_EraseRootFromParent_Done, |
| 172844 | // Label 8098: @544938 |
| 172845 | GIM_Try, /*On fail goto*//*Label 8099*/ GIMT_Encode4(545035), // Rule ID 5182 // |
| 172846 | // MIs[0] offset |
| 172847 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172848 | // MIs[0] auxiliary |
| 172849 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172850 | // MIs[0] Operand 7 |
| 172851 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172852 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172853 | // (SIbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172854 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172855 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172856 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172857 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172858 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172859 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172860 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172861 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172862 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172863 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172864 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 172865 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172866 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172867 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172868 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172869 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172870 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172871 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172873 | GIR_RootConstrainSelectedInstOperands, |
| 172874 | // GIR_Coverage, 5182, |
| 172875 | GIR_EraseRootFromParent_Done, |
| 172876 | // Label 8099: @545035 |
| 172877 | GIM_Try, /*On fail goto*//*Label 8100*/ GIMT_Encode4(545135), // Rule ID 5186 // |
| 172878 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172879 | // MIs[0] offset |
| 172880 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172881 | // MIs[0] auxiliary |
| 172882 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172883 | // MIs[0] Operand 7 |
| 172884 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172885 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172886 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172887 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172888 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172889 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172890 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172891 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172892 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172893 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172894 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172895 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172896 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172897 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 172898 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172899 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172900 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172901 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172902 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172903 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172904 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172905 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172906 | GIR_RootConstrainSelectedInstOperands, |
| 172907 | // GIR_Coverage, 5186, |
| 172908 | GIR_EraseRootFromParent_Done, |
| 172909 | // Label 8100: @545135 |
| 172910 | GIM_Try, /*On fail goto*//*Label 8101*/ GIMT_Encode4(545232), // Rule ID 5190 // |
| 172911 | // MIs[0] offset |
| 172912 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172913 | // MIs[0] auxiliary |
| 172914 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172915 | // MIs[0] Operand 7 |
| 172916 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 172917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172918 | // (SIbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172919 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 172920 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 172921 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 172922 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 172923 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 172924 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 172925 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 172926 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 172927 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172928 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 172929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 172930 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172931 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 172932 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172933 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172934 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172935 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172936 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172938 | GIR_RootConstrainSelectedInstOperands, |
| 172939 | // GIR_Coverage, 5190, |
| 172940 | GIR_EraseRootFromParent_Done, |
| 172941 | // Label 8101: @545232 |
| 172942 | GIM_Reject, |
| 172943 | // Label 8085: @545233 |
| 172944 | GIM_Reject, |
| 172945 | // Label 7903: @545234 |
| 172946 | GIM_Try, /*On fail goto*//*Label 8102*/ GIMT_Encode4(547040), |
| 172947 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 172948 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 172949 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 172950 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 172951 | GIM_Try, /*On fail goto*//*Label 8103*/ GIMT_Encode4(545323), // Rule ID 5207 // |
| 172952 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 172953 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172954 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172955 | // MIs[0] offset |
| 172956 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172957 | // MIs[0] auxiliary |
| 172958 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172959 | // MIs[0] Operand 7 |
| 172960 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172961 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172962 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v8i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172963 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 172964 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172965 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172966 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172967 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172969 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172970 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172971 | GIR_RootConstrainSelectedInstOperands, |
| 172972 | // GIR_Coverage, 5207, |
| 172973 | GIR_EraseRootFromParent_Done, |
| 172974 | // Label 8103: @545323 |
| 172975 | GIM_Try, /*On fail goto*//*Label 8104*/ GIMT_Encode4(545392), // Rule ID 5211 // |
| 172976 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 172977 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 172978 | // MIs[0] offset |
| 172979 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 172980 | // MIs[0] auxiliary |
| 172981 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 172982 | // MIs[0] Operand 7 |
| 172983 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 172984 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 172985 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v8i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 172986 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 172987 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 172988 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 172989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 172990 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 172991 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 172992 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 172993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 172994 | GIR_RootConstrainSelectedInstOperands, |
| 172995 | // GIR_Coverage, 5211, |
| 172996 | GIR_EraseRootFromParent_Done, |
| 172997 | // Label 8104: @545392 |
| 172998 | GIM_Try, /*On fail goto*//*Label 8105*/ GIMT_Encode4(545464), // Rule ID 5215 // |
| 172999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173000 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173001 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173002 | // MIs[0] offset |
| 173003 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173004 | // MIs[0] auxiliary |
| 173005 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173006 | // MIs[0] Operand 7 |
| 173007 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173009 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v8f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173010 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 173011 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173012 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173013 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173014 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173016 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173017 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173018 | GIR_RootConstrainSelectedInstOperands, |
| 173019 | // GIR_Coverage, 5215, |
| 173020 | GIR_EraseRootFromParent_Done, |
| 173021 | // Label 8105: @545464 |
| 173022 | GIM_Try, /*On fail goto*//*Label 8106*/ GIMT_Encode4(545533), // Rule ID 5219 // |
| 173023 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173024 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173025 | // MIs[0] offset |
| 173026 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173027 | // MIs[0] auxiliary |
| 173028 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173029 | // MIs[0] Operand 7 |
| 173030 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173031 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173032 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v8f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173033 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 173034 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173035 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173036 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173037 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173038 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173039 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173040 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173041 | GIR_RootConstrainSelectedInstOperands, |
| 173042 | // GIR_Coverage, 5219, |
| 173043 | GIR_EraseRootFromParent_Done, |
| 173044 | // Label 8106: @545533 |
| 173045 | GIM_Try, /*On fail goto*//*Label 8107*/ GIMT_Encode4(545605), // Rule ID 5223 // |
| 173046 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173047 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173048 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173049 | // MIs[0] offset |
| 173050 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173051 | // MIs[0] auxiliary |
| 173052 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173053 | // MIs[0] Operand 7 |
| 173054 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173055 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173056 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFSET_exact anonymous_15873:{ *:[v8bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173057 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFSET_exact), |
| 173058 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173059 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173061 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173063 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173064 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173065 | GIR_RootConstrainSelectedInstOperands, |
| 173066 | // GIR_Coverage, 5223, |
| 173067 | GIR_EraseRootFromParent_Done, |
| 173068 | // Label 8107: @545605 |
| 173069 | GIM_Try, /*On fail goto*//*Label 8108*/ GIMT_Encode4(545674), // Rule ID 5227 // |
| 173070 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173071 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173072 | // MIs[0] offset |
| 173073 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173074 | // MIs[0] auxiliary |
| 173075 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173076 | // MIs[0] Operand 7 |
| 173077 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173078 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173079 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v8bf16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFSET_exact), |
| 173081 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173082 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173083 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173084 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173085 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173086 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173087 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173088 | GIR_RootConstrainSelectedInstOperands, |
| 173089 | // GIR_Coverage, 5227, |
| 173090 | GIR_EraseRootFromParent_Done, |
| 173091 | // Label 8108: @545674 |
| 173092 | GIM_Try, /*On fail goto*//*Label 8109*/ GIMT_Encode4(545744), // Rule ID 5208 // |
| 173093 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173094 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173095 | // MIs[0] offset |
| 173096 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173097 | // MIs[0] auxiliary |
| 173098 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173099 | // MIs[0] Operand 7 |
| 173100 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173102 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173103 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 173104 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173105 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173106 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173108 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173110 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173111 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173112 | GIR_RootConstrainSelectedInstOperands, |
| 173113 | // GIR_Coverage, 5208, |
| 173114 | GIR_EraseRootFromParent_Done, |
| 173115 | // Label 8109: @545744 |
| 173116 | GIM_Try, /*On fail goto*//*Label 8110*/ GIMT_Encode4(545811), // Rule ID 5212 // |
| 173117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173118 | // MIs[0] offset |
| 173119 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173120 | // MIs[0] auxiliary |
| 173121 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173122 | // MIs[0] Operand 7 |
| 173123 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173124 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173125 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173126 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 173127 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173128 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173129 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173130 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173131 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173132 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173133 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173134 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173135 | GIR_RootConstrainSelectedInstOperands, |
| 173136 | // GIR_Coverage, 5212, |
| 173137 | GIR_EraseRootFromParent_Done, |
| 173138 | // Label 8110: @545811 |
| 173139 | GIM_Try, /*On fail goto*//*Label 8111*/ GIMT_Encode4(545881), // Rule ID 5216 // |
| 173140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173141 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173142 | // MIs[0] offset |
| 173143 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173144 | // MIs[0] auxiliary |
| 173145 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173146 | // MIs[0] Operand 7 |
| 173147 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173148 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173149 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173150 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 173151 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173152 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173153 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173154 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173155 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173157 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173159 | GIR_RootConstrainSelectedInstOperands, |
| 173160 | // GIR_Coverage, 5216, |
| 173161 | GIR_EraseRootFromParent_Done, |
| 173162 | // Label 8111: @545881 |
| 173163 | GIM_Try, /*On fail goto*//*Label 8112*/ GIMT_Encode4(545948), // Rule ID 5220 // |
| 173164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173165 | // MIs[0] offset |
| 173166 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173167 | // MIs[0] auxiliary |
| 173168 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173169 | // MIs[0] Operand 7 |
| 173170 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173171 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173172 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 173174 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173175 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173176 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173178 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173181 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173182 | GIR_RootConstrainSelectedInstOperands, |
| 173183 | // GIR_Coverage, 5220, |
| 173184 | GIR_EraseRootFromParent_Done, |
| 173185 | // Label 8112: @545948 |
| 173186 | GIM_Try, /*On fail goto*//*Label 8113*/ GIMT_Encode4(546018), // Rule ID 5224 // |
| 173187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173188 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173189 | // MIs[0] offset |
| 173190 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173191 | // MIs[0] auxiliary |
| 173192 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173193 | // MIs[0] Operand 7 |
| 173194 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173195 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173196 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_OFFEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173197 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_OFFEN_exact), |
| 173198 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173199 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173200 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173201 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173202 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173203 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173204 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173205 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173206 | GIR_RootConstrainSelectedInstOperands, |
| 173207 | // GIR_Coverage, 5224, |
| 173208 | GIR_EraseRootFromParent_Done, |
| 173209 | // Label 8113: @546018 |
| 173210 | GIM_Try, /*On fail goto*//*Label 8114*/ GIMT_Encode4(546085), // Rule ID 5228 // |
| 173211 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173212 | // MIs[0] offset |
| 173213 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173214 | // MIs[0] auxiliary |
| 173215 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173216 | // MIs[0] Operand 7 |
| 173217 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173218 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173219 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173220 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_OFFEN_exact), |
| 173221 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173222 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173223 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173224 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173225 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173226 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173229 | GIR_RootConstrainSelectedInstOperands, |
| 173230 | // GIR_Coverage, 5228, |
| 173231 | GIR_EraseRootFromParent_Done, |
| 173232 | // Label 8114: @546085 |
| 173233 | GIM_Try, /*On fail goto*//*Label 8115*/ GIMT_Encode4(546147), // Rule ID 5209 // |
| 173234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173235 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173236 | // MIs[0] offset |
| 173237 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173238 | // MIs[0] auxiliary |
| 173239 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173240 | // MIs[0] Operand 7 |
| 173241 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173242 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173243 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173244 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 173245 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173246 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173247 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173249 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173250 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173253 | GIR_RootConstrainSelectedInstOperands, |
| 173254 | // GIR_Coverage, 5209, |
| 173255 | GIR_EraseRootFromParent_Done, |
| 173256 | // Label 8115: @546147 |
| 173257 | GIM_Try, /*On fail goto*//*Label 8116*/ GIMT_Encode4(546206), // Rule ID 5213 // |
| 173258 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173259 | // MIs[0] offset |
| 173260 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173261 | // MIs[0] auxiliary |
| 173262 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173263 | // MIs[0] Operand 7 |
| 173264 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173265 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173266 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173267 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 173268 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173269 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173270 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173271 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173272 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173273 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173274 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173275 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173276 | GIR_RootConstrainSelectedInstOperands, |
| 173277 | // GIR_Coverage, 5213, |
| 173278 | GIR_EraseRootFromParent_Done, |
| 173279 | // Label 8116: @546206 |
| 173280 | GIM_Try, /*On fail goto*//*Label 8117*/ GIMT_Encode4(546268), // Rule ID 5217 // |
| 173281 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173282 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173283 | // MIs[0] offset |
| 173284 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173285 | // MIs[0] auxiliary |
| 173286 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173287 | // MIs[0] Operand 7 |
| 173288 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173289 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173290 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 173292 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173293 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173294 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173296 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173300 | GIR_RootConstrainSelectedInstOperands, |
| 173301 | // GIR_Coverage, 5217, |
| 173302 | GIR_EraseRootFromParent_Done, |
| 173303 | // Label 8117: @546268 |
| 173304 | GIM_Try, /*On fail goto*//*Label 8118*/ GIMT_Encode4(546327), // Rule ID 5221 // |
| 173305 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173306 | // MIs[0] offset |
| 173307 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173308 | // MIs[0] auxiliary |
| 173309 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173310 | // MIs[0] Operand 7 |
| 173311 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173312 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173313 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173314 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 173315 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173316 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173317 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173318 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173319 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173320 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173321 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173323 | GIR_RootConstrainSelectedInstOperands, |
| 173324 | // GIR_Coverage, 5221, |
| 173325 | GIR_EraseRootFromParent_Done, |
| 173326 | // Label 8118: @546327 |
| 173327 | GIM_Try, /*On fail goto*//*Label 8119*/ GIMT_Encode4(546389), // Rule ID 5225 // |
| 173328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173329 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173330 | // MIs[0] offset |
| 173331 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173332 | // MIs[0] auxiliary |
| 173333 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173334 | // MIs[0] Operand 7 |
| 173335 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173336 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173337 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_IDXEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173338 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_IDXEN_exact), |
| 173339 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173340 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173341 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173343 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173344 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173347 | GIR_RootConstrainSelectedInstOperands, |
| 173348 | // GIR_Coverage, 5225, |
| 173349 | GIR_EraseRootFromParent_Done, |
| 173350 | // Label 8119: @546389 |
| 173351 | GIM_Try, /*On fail goto*//*Label 8120*/ GIMT_Encode4(546448), // Rule ID 5229 // |
| 173352 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173353 | // MIs[0] offset |
| 173354 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173355 | // MIs[0] auxiliary |
| 173356 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173357 | // MIs[0] Operand 7 |
| 173358 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173359 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173360 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_IDXEN_exact), |
| 173362 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173363 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173364 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173366 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173367 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173368 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173369 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173370 | GIR_RootConstrainSelectedInstOperands, |
| 173371 | // GIR_Coverage, 5229, |
| 173372 | GIR_EraseRootFromParent_Done, |
| 173373 | // Label 8120: @546448 |
| 173374 | GIM_Try, /*On fail goto*//*Label 8121*/ GIMT_Encode4(546548), // Rule ID 5210 // |
| 173375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173376 | // MIs[0] offset |
| 173377 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173378 | // MIs[0] auxiliary |
| 173379 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173380 | // MIs[0] Operand 7 |
| 173381 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173382 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173383 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173384 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173385 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173386 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173387 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173388 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173389 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173390 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173391 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173392 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173393 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 173395 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173396 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173397 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173398 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173399 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173400 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173401 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173402 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173403 | GIR_RootConstrainSelectedInstOperands, |
| 173404 | // GIR_Coverage, 5210, |
| 173405 | GIR_EraseRootFromParent_Done, |
| 173406 | // Label 8121: @546548 |
| 173407 | GIM_Try, /*On fail goto*//*Label 8122*/ GIMT_Encode4(546645), // Rule ID 5214 // |
| 173408 | // MIs[0] offset |
| 173409 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173410 | // MIs[0] auxiliary |
| 173411 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173412 | // MIs[0] Operand 7 |
| 173413 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173415 | // (SIbuffer_store v8i16:{ *:[v8i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v8i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173416 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173417 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173418 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173419 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173420 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173421 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173422 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173423 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173424 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173425 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173426 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 173427 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173428 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173429 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173431 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173433 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173435 | GIR_RootConstrainSelectedInstOperands, |
| 173436 | // GIR_Coverage, 5214, |
| 173437 | GIR_EraseRootFromParent_Done, |
| 173438 | // Label 8122: @546645 |
| 173439 | GIM_Try, /*On fail goto*//*Label 8123*/ GIMT_Encode4(546745), // Rule ID 5218 // |
| 173440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173441 | // MIs[0] offset |
| 173442 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173443 | // MIs[0] auxiliary |
| 173444 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173445 | // MIs[0] Operand 7 |
| 173446 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173447 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173448 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173449 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173450 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173451 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173452 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173453 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173454 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173455 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173456 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173457 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173458 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173459 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 173460 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173461 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173462 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173464 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173465 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173466 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173467 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173468 | GIR_RootConstrainSelectedInstOperands, |
| 173469 | // GIR_Coverage, 5218, |
| 173470 | GIR_EraseRootFromParent_Done, |
| 173471 | // Label 8123: @546745 |
| 173472 | GIM_Try, /*On fail goto*//*Label 8124*/ GIMT_Encode4(546842), // Rule ID 5222 // |
| 173473 | // MIs[0] offset |
| 173474 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173475 | // MIs[0] auxiliary |
| 173476 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173477 | // MIs[0] Operand 7 |
| 173478 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173479 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173480 | // (SIbuffer_store v8f16:{ *:[v8f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v8f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173481 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173482 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173483 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173484 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173485 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173486 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173487 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173488 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173489 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173490 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173491 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 173492 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173493 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173494 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173495 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173496 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173497 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173498 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173499 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173500 | GIR_RootConstrainSelectedInstOperands, |
| 173501 | // GIR_Coverage, 5222, |
| 173502 | GIR_EraseRootFromParent_Done, |
| 173503 | // Label 8124: @546842 |
| 173504 | GIM_Try, /*On fail goto*//*Label 8125*/ GIMT_Encode4(546942), // Rule ID 5226 // |
| 173505 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173506 | // MIs[0] offset |
| 173507 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173508 | // MIs[0] auxiliary |
| 173509 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173510 | // MIs[0] Operand 7 |
| 173511 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173512 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173513 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_BOTHEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173514 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173515 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173516 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173517 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173518 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173519 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173520 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173521 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173522 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173523 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_BOTHEN_exact), |
| 173525 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173526 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173527 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173529 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173530 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173531 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173532 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173533 | GIR_RootConstrainSelectedInstOperands, |
| 173534 | // GIR_Coverage, 5226, |
| 173535 | GIR_EraseRootFromParent_Done, |
| 173536 | // Label 8125: @546942 |
| 173537 | GIM_Try, /*On fail goto*//*Label 8126*/ GIMT_Encode4(547039), // Rule ID 5230 // |
| 173538 | // MIs[0] offset |
| 173539 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173540 | // MIs[0] auxiliary |
| 173541 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173542 | // MIs[0] Operand 7 |
| 173543 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173544 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173545 | // (SIbuffer_store v8bf16:{ *:[v8bf16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v8bf16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173546 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173547 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173548 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173549 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173550 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173551 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173552 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173553 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173554 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173555 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173556 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_DWORDX4_VBUFFER_BOTHEN_exact), |
| 173557 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173558 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173559 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173560 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173561 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173562 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173563 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173564 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173565 | GIR_RootConstrainSelectedInstOperands, |
| 173566 | // GIR_Coverage, 5230, |
| 173567 | GIR_EraseRootFromParent_Done, |
| 173568 | // Label 8126: @547039 |
| 173569 | GIM_Reject, |
| 173570 | // Label 8102: @547040 |
| 173571 | GIM_Reject, |
| 173572 | // Label 7904: @547041 |
| 173573 | GIM_Reject, |
| 173574 | // Label 139: @547042 |
| 173575 | GIM_Try, /*On fail goto*//*Label 8127*/ GIMT_Encode4(547643), |
| 173576 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 173577 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 173578 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 173579 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 173580 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 173581 | GIM_Try, /*On fail goto*//*Label 8128*/ GIMT_Encode4(547334), |
| 173582 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173583 | GIM_Try, /*On fail goto*//*Label 8129*/ GIMT_Encode4(547139), // Rule ID 5231 // |
| 173584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173585 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173586 | // MIs[0] offset |
| 173587 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173588 | // MIs[0] auxiliary |
| 173589 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173590 | // MIs[0] Operand 7 |
| 173591 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173592 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173593 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_BYTE_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173594 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFSET_exact), |
| 173595 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173596 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173598 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173600 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173601 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173602 | GIR_RootConstrainSelectedInstOperands, |
| 173603 | // GIR_Coverage, 5231, |
| 173604 | GIR_EraseRootFromParent_Done, |
| 173605 | // Label 8129: @547139 |
| 173606 | GIM_Try, /*On fail goto*//*Label 8130*/ GIMT_Encode4(547204), // Rule ID 5235 // |
| 173607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173608 | // MIs[0] offset |
| 173609 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173610 | // MIs[0] auxiliary |
| 173611 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173612 | // MIs[0] Operand 7 |
| 173613 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173615 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_BYTE_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFSET_exact), |
| 173617 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173618 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173620 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173621 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173622 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173623 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173624 | GIR_RootConstrainSelectedInstOperands, |
| 173625 | // GIR_Coverage, 5235, |
| 173626 | GIR_EraseRootFromParent_Done, |
| 173627 | // Label 8130: @547204 |
| 173628 | GIM_Try, /*On fail goto*//*Label 8131*/ GIMT_Encode4(547270), // Rule ID 5232 // |
| 173629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173630 | // MIs[0] offset |
| 173631 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173632 | // MIs[0] auxiliary |
| 173633 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173634 | // MIs[0] Operand 7 |
| 173635 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173637 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_BYTE_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_OFFEN_exact), |
| 173639 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173640 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173641 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173643 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173644 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173645 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173646 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173647 | GIR_RootConstrainSelectedInstOperands, |
| 173648 | // GIR_Coverage, 5232, |
| 173649 | GIR_EraseRootFromParent_Done, |
| 173650 | // Label 8131: @547270 |
| 173651 | GIM_Try, /*On fail goto*//*Label 8132*/ GIMT_Encode4(547333), // Rule ID 5236 // |
| 173652 | // MIs[0] offset |
| 173653 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173654 | // MIs[0] auxiliary |
| 173655 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173656 | // MIs[0] Operand 7 |
| 173657 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173658 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173659 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_BYTE_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_OFFEN_exact), |
| 173661 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173662 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173663 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173665 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173666 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173669 | GIR_RootConstrainSelectedInstOperands, |
| 173670 | // GIR_Coverage, 5236, |
| 173671 | GIR_EraseRootFromParent_Done, |
| 173672 | // Label 8132: @547333 |
| 173673 | GIM_Reject, |
| 173674 | // Label 8128: @547334 |
| 173675 | GIM_Try, /*On fail goto*//*Label 8133*/ GIMT_Encode4(547448), |
| 173676 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173677 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173678 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173679 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173680 | GIM_Try, /*On fail goto*//*Label 8134*/ GIMT_Encode4(547401), // Rule ID 5233 // |
| 173681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173682 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173683 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_BYTE_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_IDXEN_exact), |
| 173685 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173686 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173687 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173689 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173690 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173691 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173692 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173693 | GIR_RootConstrainSelectedInstOperands, |
| 173694 | // GIR_Coverage, 5233, |
| 173695 | GIR_EraseRootFromParent_Done, |
| 173696 | // Label 8134: @547401 |
| 173697 | GIM_Try, /*On fail goto*//*Label 8135*/ GIMT_Encode4(547447), // Rule ID 5237 // |
| 173698 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173699 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_BYTE_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173700 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_IDXEN_exact), |
| 173701 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173702 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173703 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173704 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173705 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173706 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173707 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173708 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173709 | GIR_RootConstrainSelectedInstOperands, |
| 173710 | // GIR_Coverage, 5237, |
| 173711 | GIR_EraseRootFromParent_Done, |
| 173712 | // Label 8135: @547447 |
| 173713 | GIM_Reject, |
| 173714 | // Label 8133: @547448 |
| 173715 | GIM_Try, /*On fail goto*//*Label 8136*/ GIMT_Encode4(547642), |
| 173716 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173717 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173718 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173719 | GIM_Try, /*On fail goto*//*Label 8137*/ GIMT_Encode4(547553), // Rule ID 5234 // |
| 173720 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173721 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173722 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_BYTE_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173723 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173724 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173725 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173726 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173727 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173728 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173729 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173730 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173731 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173732 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_BOTHEN_exact), |
| 173734 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173735 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173736 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173738 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173742 | GIR_RootConstrainSelectedInstOperands, |
| 173743 | // GIR_Coverage, 5234, |
| 173744 | GIR_EraseRootFromParent_Done, |
| 173745 | // Label 8137: @547553 |
| 173746 | GIM_Try, /*On fail goto*//*Label 8138*/ GIMT_Encode4(547641), // Rule ID 5238 // |
| 173747 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173748 | // (SIbuffer_store_byte i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173749 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 173750 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 173751 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 173752 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 173753 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 173754 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 173755 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 173756 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 173757 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173758 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 173759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_BYTE_VBUFFER_BOTHEN_exact), |
| 173760 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173761 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 173762 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173764 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173765 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173767 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173768 | GIR_RootConstrainSelectedInstOperands, |
| 173769 | // GIR_Coverage, 5238, |
| 173770 | GIR_EraseRootFromParent_Done, |
| 173771 | // Label 8138: @547641 |
| 173772 | GIM_Reject, |
| 173773 | // Label 8136: @547642 |
| 173774 | GIM_Reject, |
| 173775 | // Label 8127: @547643 |
| 173776 | GIM_Reject, |
| 173777 | // Label 140: @547644 |
| 173778 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 8143*/ GIMT_Encode4(553131), |
| 173779 | /*GILLT_s32*//*Label 8139*/ GIMT_Encode4(547691), GIMT_Encode4(0), GIMT_Encode4(0), |
| 173780 | /*GILLT_v2s32*//*Label 8140*/ GIMT_Encode4(548902), GIMT_Encode4(0), |
| 173781 | /*GILLT_v3s32*//*Label 8141*/ GIMT_Encode4(550709), GIMT_Encode4(0), GIMT_Encode4(0), |
| 173782 | /*GILLT_v4s32*//*Label 8142*/ GIMT_Encode4(551920), |
| 173783 | // Label 8139: @547691 |
| 173784 | GIM_Try, /*On fail goto*//*Label 8144*/ GIMT_Encode4(548901), |
| 173785 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 173786 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 173787 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 173788 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 173789 | GIM_Try, /*On fail goto*//*Label 8145*/ GIMT_Encode4(547780), // Rule ID 4855 // |
| 173790 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173792 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173793 | // MIs[0] offset |
| 173794 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173795 | // MIs[0] auxiliary |
| 173796 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173797 | // MIs[0] Operand 7 |
| 173798 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173800 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_exact), |
| 173802 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173803 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173804 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173805 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173806 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173808 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173809 | GIR_RootConstrainSelectedInstOperands, |
| 173810 | // GIR_Coverage, 4855, |
| 173811 | GIR_EraseRootFromParent_Done, |
| 173812 | // Label 8145: @547780 |
| 173813 | GIM_Try, /*On fail goto*//*Label 8146*/ GIMT_Encode4(547849), // Rule ID 4859 // |
| 173814 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173815 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173816 | // MIs[0] offset |
| 173817 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173818 | // MIs[0] auxiliary |
| 173819 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173820 | // MIs[0] Operand 7 |
| 173821 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173822 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173823 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173824 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact), |
| 173825 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173826 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173827 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173828 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173830 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173832 | GIR_RootConstrainSelectedInstOperands, |
| 173833 | // GIR_Coverage, 4859, |
| 173834 | GIR_EraseRootFromParent_Done, |
| 173835 | // Label 8146: @547849 |
| 173836 | GIM_Try, /*On fail goto*//*Label 8147*/ GIMT_Encode4(547921), // Rule ID 4863 // |
| 173837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173838 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173839 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173840 | // MIs[0] offset |
| 173841 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173842 | // MIs[0] auxiliary |
| 173843 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173844 | // MIs[0] Operand 7 |
| 173845 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173846 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173847 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFSET_exact), |
| 173849 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173850 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173852 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173853 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173855 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173856 | GIR_RootConstrainSelectedInstOperands, |
| 173857 | // GIR_Coverage, 4863, |
| 173858 | GIR_EraseRootFromParent_Done, |
| 173859 | // Label 8147: @547921 |
| 173860 | GIM_Try, /*On fail goto*//*Label 8148*/ GIMT_Encode4(547990), // Rule ID 4867 // |
| 173861 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173862 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173863 | // MIs[0] offset |
| 173864 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173865 | // MIs[0] auxiliary |
| 173866 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173867 | // MIs[0] Operand 7 |
| 173868 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173869 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173870 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173871 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact), |
| 173872 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173873 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173874 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173875 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173876 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173877 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173878 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173879 | GIR_RootConstrainSelectedInstOperands, |
| 173880 | // GIR_Coverage, 4867, |
| 173881 | GIR_EraseRootFromParent_Done, |
| 173882 | // Label 8148: @547990 |
| 173883 | GIM_Try, /*On fail goto*//*Label 8149*/ GIMT_Encode4(548060), // Rule ID 4856 // |
| 173884 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173885 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173886 | // MIs[0] offset |
| 173887 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173888 | // MIs[0] auxiliary |
| 173889 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173890 | // MIs[0] Operand 7 |
| 173891 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173893 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_exact), |
| 173895 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173896 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173897 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173898 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173899 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173903 | GIR_RootConstrainSelectedInstOperands, |
| 173904 | // GIR_Coverage, 4856, |
| 173905 | GIR_EraseRootFromParent_Done, |
| 173906 | // Label 8149: @548060 |
| 173907 | GIM_Try, /*On fail goto*//*Label 8150*/ GIMT_Encode4(548127), // Rule ID 4860 // |
| 173908 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173909 | // MIs[0] offset |
| 173910 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173911 | // MIs[0] auxiliary |
| 173912 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173913 | // MIs[0] Operand 7 |
| 173914 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173916 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact), |
| 173918 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173919 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173920 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173922 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173923 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173925 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173926 | GIR_RootConstrainSelectedInstOperands, |
| 173927 | // GIR_Coverage, 4860, |
| 173928 | GIR_EraseRootFromParent_Done, |
| 173929 | // Label 8150: @548127 |
| 173930 | GIM_Try, /*On fail goto*//*Label 8151*/ GIMT_Encode4(548197), // Rule ID 4864 // |
| 173931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173932 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173933 | // MIs[0] offset |
| 173934 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173935 | // MIs[0] auxiliary |
| 173936 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173937 | // MIs[0] Operand 7 |
| 173938 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173940 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_OFFEN_exact), |
| 173942 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173943 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173944 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173946 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173947 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173950 | GIR_RootConstrainSelectedInstOperands, |
| 173951 | // GIR_Coverage, 4864, |
| 173952 | GIR_EraseRootFromParent_Done, |
| 173953 | // Label 8151: @548197 |
| 173954 | GIM_Try, /*On fail goto*//*Label 8152*/ GIMT_Encode4(548264), // Rule ID 4868 // |
| 173955 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 173956 | // MIs[0] offset |
| 173957 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173958 | // MIs[0] auxiliary |
| 173959 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173960 | // MIs[0] Operand 7 |
| 173961 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 173962 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173963 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173964 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact), |
| 173965 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173966 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 173967 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173968 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173969 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173970 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173972 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173973 | GIR_RootConstrainSelectedInstOperands, |
| 173974 | // GIR_Coverage, 4868, |
| 173975 | GIR_EraseRootFromParent_Done, |
| 173976 | // Label 8152: @548264 |
| 173977 | GIM_Try, /*On fail goto*//*Label 8153*/ GIMT_Encode4(548326), // Rule ID 4857 // |
| 173978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 173979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 173980 | // MIs[0] offset |
| 173981 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 173982 | // MIs[0] auxiliary |
| 173983 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 173984 | // MIs[0] Operand 7 |
| 173985 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 173986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 173987 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 173988 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_exact), |
| 173989 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 173990 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 173991 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 173992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 173993 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 173994 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 173995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 173996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 173997 | GIR_RootConstrainSelectedInstOperands, |
| 173998 | // GIR_Coverage, 4857, |
| 173999 | GIR_EraseRootFromParent_Done, |
| 174000 | // Label 8153: @548326 |
| 174001 | GIM_Try, /*On fail goto*//*Label 8154*/ GIMT_Encode4(548385), // Rule ID 4861 // |
| 174002 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174003 | // MIs[0] offset |
| 174004 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174005 | // MIs[0] auxiliary |
| 174006 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174007 | // MIs[0] Operand 7 |
| 174008 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174009 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174010 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174011 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact), |
| 174012 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174013 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174014 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174016 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174017 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174020 | GIR_RootConstrainSelectedInstOperands, |
| 174021 | // GIR_Coverage, 4861, |
| 174022 | GIR_EraseRootFromParent_Done, |
| 174023 | // Label 8154: @548385 |
| 174024 | GIM_Try, /*On fail goto*//*Label 8155*/ GIMT_Encode4(548447), // Rule ID 4865 // |
| 174025 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174026 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174027 | // MIs[0] offset |
| 174028 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174029 | // MIs[0] auxiliary |
| 174030 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174031 | // MIs[0] Operand 7 |
| 174032 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174033 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174034 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174035 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_IDXEN_exact), |
| 174036 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174037 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174038 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174039 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174040 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174041 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174044 | GIR_RootConstrainSelectedInstOperands, |
| 174045 | // GIR_Coverage, 4865, |
| 174046 | GIR_EraseRootFromParent_Done, |
| 174047 | // Label 8155: @548447 |
| 174048 | GIM_Try, /*On fail goto*//*Label 8156*/ GIMT_Encode4(548506), // Rule ID 4869 // |
| 174049 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174050 | // MIs[0] offset |
| 174051 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174052 | // MIs[0] auxiliary |
| 174053 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174054 | // MIs[0] Operand 7 |
| 174055 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174057 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact), |
| 174059 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174060 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174061 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174063 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174066 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174067 | GIR_RootConstrainSelectedInstOperands, |
| 174068 | // GIR_Coverage, 4869, |
| 174069 | GIR_EraseRootFromParent_Done, |
| 174070 | // Label 8156: @548506 |
| 174071 | GIM_Try, /*On fail goto*//*Label 8157*/ GIMT_Encode4(548606), // Rule ID 4858 // |
| 174072 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174073 | // MIs[0] offset |
| 174074 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174075 | // MIs[0] auxiliary |
| 174076 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174077 | // MIs[0] Operand 7 |
| 174078 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174079 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174080 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174081 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174082 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174083 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174084 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174085 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174086 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174087 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174088 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174089 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174090 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174091 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_exact), |
| 174092 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174093 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174094 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174095 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174096 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174097 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174098 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174099 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174100 | GIR_RootConstrainSelectedInstOperands, |
| 174101 | // GIR_Coverage, 4858, |
| 174102 | GIR_EraseRootFromParent_Done, |
| 174103 | // Label 8157: @548606 |
| 174104 | GIM_Try, /*On fail goto*//*Label 8158*/ GIMT_Encode4(548703), // Rule ID 4862 // |
| 174105 | // MIs[0] offset |
| 174106 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174107 | // MIs[0] auxiliary |
| 174108 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174109 | // MIs[0] Operand 7 |
| 174110 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174112 | // (SIbuffer_store_format f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174113 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174114 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174115 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174116 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174117 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174118 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174119 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174120 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174121 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174122 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174123 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact), |
| 174124 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174125 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174126 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174128 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174129 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174130 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174132 | GIR_RootConstrainSelectedInstOperands, |
| 174133 | // GIR_Coverage, 4862, |
| 174134 | GIR_EraseRootFromParent_Done, |
| 174135 | // Label 8158: @548703 |
| 174136 | GIM_Try, /*On fail goto*//*Label 8159*/ GIMT_Encode4(548803), // Rule ID 4866 // |
| 174137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174138 | // MIs[0] offset |
| 174139 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174140 | // MIs[0] auxiliary |
| 174141 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174142 | // MIs[0] Operand 7 |
| 174143 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174145 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174146 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174147 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174148 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174149 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174150 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174151 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174152 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174153 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174154 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174155 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_BOTHEN_exact), |
| 174157 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174158 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174159 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174160 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174161 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174162 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174163 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174165 | GIR_RootConstrainSelectedInstOperands, |
| 174166 | // GIR_Coverage, 4866, |
| 174167 | GIR_EraseRootFromParent_Done, |
| 174168 | // Label 8159: @548803 |
| 174169 | GIM_Try, /*On fail goto*//*Label 8160*/ GIMT_Encode4(548900), // Rule ID 4870 // |
| 174170 | // MIs[0] offset |
| 174171 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174172 | // MIs[0] auxiliary |
| 174173 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174174 | // MIs[0] Operand 7 |
| 174175 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174176 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174177 | // (SIbuffer_store_format i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174178 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174179 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174180 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174181 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174182 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174183 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174184 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174185 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174186 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174187 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174188 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact), |
| 174189 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174190 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174191 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174192 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174193 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174194 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174196 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174197 | GIR_RootConstrainSelectedInstOperands, |
| 174198 | // GIR_Coverage, 4870, |
| 174199 | GIR_EraseRootFromParent_Done, |
| 174200 | // Label 8160: @548900 |
| 174201 | GIM_Reject, |
| 174202 | // Label 8144: @548901 |
| 174203 | GIM_Reject, |
| 174204 | // Label 8140: @548902 |
| 174205 | GIM_Try, /*On fail goto*//*Label 8161*/ GIMT_Encode4(550708), |
| 174206 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 174207 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 174208 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 174209 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 174210 | GIM_Try, /*On fail goto*//*Label 8162*/ GIMT_Encode4(548991), // Rule ID 4871 // |
| 174211 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174212 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174213 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174214 | // MIs[0] offset |
| 174215 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174216 | // MIs[0] auxiliary |
| 174217 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174218 | // MIs[0] Operand 7 |
| 174219 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174220 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174221 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174222 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_exact), |
| 174223 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174224 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174225 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174226 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174228 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174229 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174230 | GIR_RootConstrainSelectedInstOperands, |
| 174231 | // GIR_Coverage, 4871, |
| 174232 | GIR_EraseRootFromParent_Done, |
| 174233 | // Label 8162: @548991 |
| 174234 | GIM_Try, /*On fail goto*//*Label 8163*/ GIMT_Encode4(549060), // Rule ID 4875 // |
| 174235 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174236 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174237 | // MIs[0] offset |
| 174238 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174239 | // MIs[0] auxiliary |
| 174240 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174241 | // MIs[0] Operand 7 |
| 174242 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174244 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174245 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact), |
| 174246 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174247 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174248 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174249 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174250 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174253 | GIR_RootConstrainSelectedInstOperands, |
| 174254 | // GIR_Coverage, 4875, |
| 174255 | GIR_EraseRootFromParent_Done, |
| 174256 | // Label 8163: @549060 |
| 174257 | GIM_Try, /*On fail goto*//*Label 8164*/ GIMT_Encode4(549132), // Rule ID 4879 // |
| 174258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174259 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174261 | // MIs[0] offset |
| 174262 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174263 | // MIs[0] auxiliary |
| 174264 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174265 | // MIs[0] Operand 7 |
| 174266 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174268 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174269 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_exact), |
| 174270 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174271 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174272 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174273 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174274 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174276 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174277 | GIR_RootConstrainSelectedInstOperands, |
| 174278 | // GIR_Coverage, 4879, |
| 174279 | GIR_EraseRootFromParent_Done, |
| 174280 | // Label 8164: @549132 |
| 174281 | GIM_Try, /*On fail goto*//*Label 8165*/ GIMT_Encode4(549201), // Rule ID 4883 // |
| 174282 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174283 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174284 | // MIs[0] offset |
| 174285 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174286 | // MIs[0] auxiliary |
| 174287 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174288 | // MIs[0] Operand 7 |
| 174289 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174290 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174291 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact), |
| 174293 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174294 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174296 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174300 | GIR_RootConstrainSelectedInstOperands, |
| 174301 | // GIR_Coverage, 4883, |
| 174302 | GIR_EraseRootFromParent_Done, |
| 174303 | // Label 8165: @549201 |
| 174304 | GIM_Try, /*On fail goto*//*Label 8166*/ GIMT_Encode4(549273), // Rule ID 4887 // |
| 174305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174306 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174307 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174308 | // MIs[0] offset |
| 174309 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174310 | // MIs[0] auxiliary |
| 174311 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174312 | // MIs[0] Operand 7 |
| 174313 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174315 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174316 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFSET_exact), |
| 174317 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174318 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174320 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174321 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174322 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174323 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174324 | GIR_RootConstrainSelectedInstOperands, |
| 174325 | // GIR_Coverage, 4887, |
| 174326 | GIR_EraseRootFromParent_Done, |
| 174327 | // Label 8166: @549273 |
| 174328 | GIM_Try, /*On fail goto*//*Label 8167*/ GIMT_Encode4(549342), // Rule ID 4891 // |
| 174329 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174330 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174331 | // MIs[0] offset |
| 174332 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174333 | // MIs[0] auxiliary |
| 174334 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174335 | // MIs[0] Operand 7 |
| 174336 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174338 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact), |
| 174340 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174341 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174343 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174344 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174346 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174347 | GIR_RootConstrainSelectedInstOperands, |
| 174348 | // GIR_Coverage, 4891, |
| 174349 | GIR_EraseRootFromParent_Done, |
| 174350 | // Label 8167: @549342 |
| 174351 | GIM_Try, /*On fail goto*//*Label 8168*/ GIMT_Encode4(549412), // Rule ID 4872 // |
| 174352 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174353 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174354 | // MIs[0] offset |
| 174355 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174356 | // MIs[0] auxiliary |
| 174357 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174358 | // MIs[0] Operand 7 |
| 174359 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174360 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174361 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174362 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_exact), |
| 174363 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174364 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174365 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174366 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174367 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174368 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174371 | GIR_RootConstrainSelectedInstOperands, |
| 174372 | // GIR_Coverage, 4872, |
| 174373 | GIR_EraseRootFromParent_Done, |
| 174374 | // Label 8168: @549412 |
| 174375 | GIM_Try, /*On fail goto*//*Label 8169*/ GIMT_Encode4(549479), // Rule ID 4876 // |
| 174376 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174377 | // MIs[0] offset |
| 174378 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174379 | // MIs[0] auxiliary |
| 174380 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174381 | // MIs[0] Operand 7 |
| 174382 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174383 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174384 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174385 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact), |
| 174386 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174387 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174388 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174389 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174390 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174391 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174392 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174393 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174394 | GIR_RootConstrainSelectedInstOperands, |
| 174395 | // GIR_Coverage, 4876, |
| 174396 | GIR_EraseRootFromParent_Done, |
| 174397 | // Label 8169: @549479 |
| 174398 | GIM_Try, /*On fail goto*//*Label 8170*/ GIMT_Encode4(549549), // Rule ID 4880 // |
| 174399 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174400 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174401 | // MIs[0] offset |
| 174402 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174403 | // MIs[0] auxiliary |
| 174404 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174405 | // MIs[0] Operand 7 |
| 174406 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174408 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_exact), |
| 174410 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174411 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174412 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174413 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174414 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174415 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174418 | GIR_RootConstrainSelectedInstOperands, |
| 174419 | // GIR_Coverage, 4880, |
| 174420 | GIR_EraseRootFromParent_Done, |
| 174421 | // Label 8170: @549549 |
| 174422 | GIM_Try, /*On fail goto*//*Label 8171*/ GIMT_Encode4(549616), // Rule ID 4884 // |
| 174423 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174424 | // MIs[0] offset |
| 174425 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174426 | // MIs[0] auxiliary |
| 174427 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174428 | // MIs[0] Operand 7 |
| 174429 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174430 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174431 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174432 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact), |
| 174433 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174434 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174435 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174436 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174437 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174438 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174440 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174441 | GIR_RootConstrainSelectedInstOperands, |
| 174442 | // GIR_Coverage, 4884, |
| 174443 | GIR_EraseRootFromParent_Done, |
| 174444 | // Label 8171: @549616 |
| 174445 | GIM_Try, /*On fail goto*//*Label 8172*/ GIMT_Encode4(549686), // Rule ID 4888 // |
| 174446 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174447 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174448 | // MIs[0] offset |
| 174449 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174450 | // MIs[0] auxiliary |
| 174451 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174452 | // MIs[0] Operand 7 |
| 174453 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174454 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174455 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174456 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_OFFEN_exact), |
| 174457 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174458 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174459 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174460 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174461 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174462 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174464 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174465 | GIR_RootConstrainSelectedInstOperands, |
| 174466 | // GIR_Coverage, 4888, |
| 174467 | GIR_EraseRootFromParent_Done, |
| 174468 | // Label 8172: @549686 |
| 174469 | GIM_Try, /*On fail goto*//*Label 8173*/ GIMT_Encode4(549753), // Rule ID 4892 // |
| 174470 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174471 | // MIs[0] offset |
| 174472 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174473 | // MIs[0] auxiliary |
| 174474 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174475 | // MIs[0] Operand 7 |
| 174476 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174477 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174478 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174479 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact), |
| 174480 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174481 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174482 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174483 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174484 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174485 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174486 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174487 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174488 | GIR_RootConstrainSelectedInstOperands, |
| 174489 | // GIR_Coverage, 4892, |
| 174490 | GIR_EraseRootFromParent_Done, |
| 174491 | // Label 8173: @549753 |
| 174492 | GIM_Try, /*On fail goto*//*Label 8174*/ GIMT_Encode4(549815), // Rule ID 4873 // |
| 174493 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174494 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174495 | // MIs[0] offset |
| 174496 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174497 | // MIs[0] auxiliary |
| 174498 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174499 | // MIs[0] Operand 7 |
| 174500 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174501 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174502 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174503 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_exact), |
| 174504 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174505 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174506 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174507 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174508 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174509 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174510 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174511 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174512 | GIR_RootConstrainSelectedInstOperands, |
| 174513 | // GIR_Coverage, 4873, |
| 174514 | GIR_EraseRootFromParent_Done, |
| 174515 | // Label 8174: @549815 |
| 174516 | GIM_Try, /*On fail goto*//*Label 8175*/ GIMT_Encode4(549874), // Rule ID 4877 // |
| 174517 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174518 | // MIs[0] offset |
| 174519 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174520 | // MIs[0] auxiliary |
| 174521 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174522 | // MIs[0] Operand 7 |
| 174523 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174524 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174525 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174526 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact), |
| 174527 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174528 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174529 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174530 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174531 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174532 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174533 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174534 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174535 | GIR_RootConstrainSelectedInstOperands, |
| 174536 | // GIR_Coverage, 4877, |
| 174537 | GIR_EraseRootFromParent_Done, |
| 174538 | // Label 8175: @549874 |
| 174539 | GIM_Try, /*On fail goto*//*Label 8176*/ GIMT_Encode4(549936), // Rule ID 4881 // |
| 174540 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174541 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174542 | // MIs[0] offset |
| 174543 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174544 | // MIs[0] auxiliary |
| 174545 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174546 | // MIs[0] Operand 7 |
| 174547 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174549 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174550 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_exact), |
| 174551 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174552 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174553 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174554 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174555 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174556 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174557 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174558 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174559 | GIR_RootConstrainSelectedInstOperands, |
| 174560 | // GIR_Coverage, 4881, |
| 174561 | GIR_EraseRootFromParent_Done, |
| 174562 | // Label 8176: @549936 |
| 174563 | GIM_Try, /*On fail goto*//*Label 8177*/ GIMT_Encode4(549995), // Rule ID 4885 // |
| 174564 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174565 | // MIs[0] offset |
| 174566 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174567 | // MIs[0] auxiliary |
| 174568 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174569 | // MIs[0] Operand 7 |
| 174570 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174572 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174573 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact), |
| 174574 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174575 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174576 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174577 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174578 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174579 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174580 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174581 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174582 | GIR_RootConstrainSelectedInstOperands, |
| 174583 | // GIR_Coverage, 4885, |
| 174584 | GIR_EraseRootFromParent_Done, |
| 174585 | // Label 8177: @549995 |
| 174586 | GIM_Try, /*On fail goto*//*Label 8178*/ GIMT_Encode4(550057), // Rule ID 4889 // |
| 174587 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174588 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174589 | // MIs[0] offset |
| 174590 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174591 | // MIs[0] auxiliary |
| 174592 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174593 | // MIs[0] Operand 7 |
| 174594 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174596 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_IDXEN_exact), |
| 174598 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174599 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174600 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174602 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174603 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174604 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174605 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174606 | GIR_RootConstrainSelectedInstOperands, |
| 174607 | // GIR_Coverage, 4889, |
| 174608 | GIR_EraseRootFromParent_Done, |
| 174609 | // Label 8178: @550057 |
| 174610 | GIM_Try, /*On fail goto*//*Label 8179*/ GIMT_Encode4(550116), // Rule ID 4893 // |
| 174611 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174612 | // MIs[0] offset |
| 174613 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174614 | // MIs[0] auxiliary |
| 174615 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174616 | // MIs[0] Operand 7 |
| 174617 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174618 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174619 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174620 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact), |
| 174621 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174622 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 174623 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174624 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174625 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174626 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174627 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174628 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174629 | GIR_RootConstrainSelectedInstOperands, |
| 174630 | // GIR_Coverage, 4893, |
| 174631 | GIR_EraseRootFromParent_Done, |
| 174632 | // Label 8179: @550116 |
| 174633 | GIM_Try, /*On fail goto*//*Label 8180*/ GIMT_Encode4(550216), // Rule ID 4874 // |
| 174634 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174635 | // MIs[0] offset |
| 174636 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174637 | // MIs[0] auxiliary |
| 174638 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174639 | // MIs[0] Operand 7 |
| 174640 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174641 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174642 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174643 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174644 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174645 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174646 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174647 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174648 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174649 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174650 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174651 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174652 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_exact), |
| 174654 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174655 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174656 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174658 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174659 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174660 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174661 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174662 | GIR_RootConstrainSelectedInstOperands, |
| 174663 | // GIR_Coverage, 4874, |
| 174664 | GIR_EraseRootFromParent_Done, |
| 174665 | // Label 8180: @550216 |
| 174666 | GIM_Try, /*On fail goto*//*Label 8181*/ GIMT_Encode4(550313), // Rule ID 4878 // |
| 174667 | // MIs[0] offset |
| 174668 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174669 | // MIs[0] auxiliary |
| 174670 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174671 | // MIs[0] Operand 7 |
| 174672 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174673 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174674 | // (SIbuffer_store_format v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174675 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174676 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174677 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174678 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174679 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174680 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174681 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174682 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174683 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174684 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174685 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact), |
| 174686 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174687 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174688 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174689 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174690 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174691 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174692 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174693 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174694 | GIR_RootConstrainSelectedInstOperands, |
| 174695 | // GIR_Coverage, 4878, |
| 174696 | GIR_EraseRootFromParent_Done, |
| 174697 | // Label 8181: @550313 |
| 174698 | GIM_Try, /*On fail goto*//*Label 8182*/ GIMT_Encode4(550413), // Rule ID 4882 // |
| 174699 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174700 | // MIs[0] offset |
| 174701 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174702 | // MIs[0] auxiliary |
| 174703 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174704 | // MIs[0] Operand 7 |
| 174705 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174706 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174707 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174708 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174709 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174710 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174711 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174712 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174713 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174714 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174715 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174717 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174718 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_exact), |
| 174719 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174720 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174721 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174722 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174723 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174725 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174726 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174727 | GIR_RootConstrainSelectedInstOperands, |
| 174728 | // GIR_Coverage, 4882, |
| 174729 | GIR_EraseRootFromParent_Done, |
| 174730 | // Label 8182: @550413 |
| 174731 | GIM_Try, /*On fail goto*//*Label 8183*/ GIMT_Encode4(550510), // Rule ID 4886 // |
| 174732 | // MIs[0] offset |
| 174733 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174734 | // MIs[0] auxiliary |
| 174735 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174736 | // MIs[0] Operand 7 |
| 174737 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174738 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174739 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174740 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174741 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174742 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174743 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174744 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174745 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174746 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174747 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174748 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174749 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact), |
| 174751 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174752 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174753 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174755 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174756 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174757 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174759 | GIR_RootConstrainSelectedInstOperands, |
| 174760 | // GIR_Coverage, 4886, |
| 174761 | GIR_EraseRootFromParent_Done, |
| 174762 | // Label 8183: @550510 |
| 174763 | GIM_Try, /*On fail goto*//*Label 8184*/ GIMT_Encode4(550610), // Rule ID 4890 // |
| 174764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174765 | // MIs[0] offset |
| 174766 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174767 | // MIs[0] auxiliary |
| 174768 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174769 | // MIs[0] Operand 7 |
| 174770 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174771 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174772 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174773 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174774 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174775 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174776 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174777 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174778 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174779 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174780 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174781 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174782 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174783 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_BOTHEN_exact), |
| 174784 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174785 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174786 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174787 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174788 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174789 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174790 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174791 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174792 | GIR_RootConstrainSelectedInstOperands, |
| 174793 | // GIR_Coverage, 4890, |
| 174794 | GIR_EraseRootFromParent_Done, |
| 174795 | // Label 8184: @550610 |
| 174796 | GIM_Try, /*On fail goto*//*Label 8185*/ GIMT_Encode4(550707), // Rule ID 4894 // |
| 174797 | // MIs[0] offset |
| 174798 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174799 | // MIs[0] auxiliary |
| 174800 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174801 | // MIs[0] Operand 7 |
| 174802 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 174803 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174804 | // (SIbuffer_store_format v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174805 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 174806 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 174807 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 174808 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 174809 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 174810 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 174811 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 174812 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 174813 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174814 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 174815 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact), |
| 174816 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174817 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 174818 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174819 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174820 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174821 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174822 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174823 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174824 | GIR_RootConstrainSelectedInstOperands, |
| 174825 | // GIR_Coverage, 4894, |
| 174826 | GIR_EraseRootFromParent_Done, |
| 174827 | // Label 8185: @550707 |
| 174828 | GIM_Reject, |
| 174829 | // Label 8161: @550708 |
| 174830 | GIM_Reject, |
| 174831 | // Label 8141: @550709 |
| 174832 | GIM_Try, /*On fail goto*//*Label 8186*/ GIMT_Encode4(551919), |
| 174833 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 174834 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 174835 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 174836 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 174837 | GIM_Try, /*On fail goto*//*Label 8187*/ GIMT_Encode4(550798), // Rule ID 4895 // |
| 174838 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174839 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174840 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174841 | // MIs[0] offset |
| 174842 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174843 | // MIs[0] auxiliary |
| 174844 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174845 | // MIs[0] Operand 7 |
| 174846 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174848 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_exact), |
| 174850 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174851 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174853 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174857 | GIR_RootConstrainSelectedInstOperands, |
| 174858 | // GIR_Coverage, 4895, |
| 174859 | GIR_EraseRootFromParent_Done, |
| 174860 | // Label 8187: @550798 |
| 174861 | GIM_Try, /*On fail goto*//*Label 8188*/ GIMT_Encode4(550867), // Rule ID 4899 // |
| 174862 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174863 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174864 | // MIs[0] offset |
| 174865 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174866 | // MIs[0] auxiliary |
| 174867 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174868 | // MIs[0] Operand 7 |
| 174869 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174870 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174871 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174872 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact), |
| 174873 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174874 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174875 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174876 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174877 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174878 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174879 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174880 | GIR_RootConstrainSelectedInstOperands, |
| 174881 | // GIR_Coverage, 4899, |
| 174882 | GIR_EraseRootFromParent_Done, |
| 174883 | // Label 8188: @550867 |
| 174884 | GIM_Try, /*On fail goto*//*Label 8189*/ GIMT_Encode4(550939), // Rule ID 4903 // |
| 174885 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174886 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174887 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174888 | // MIs[0] offset |
| 174889 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174890 | // MIs[0] auxiliary |
| 174891 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174892 | // MIs[0] Operand 7 |
| 174893 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174894 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174895 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174896 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFSET_exact), |
| 174897 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174898 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174899 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174900 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174902 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174903 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174904 | GIR_RootConstrainSelectedInstOperands, |
| 174905 | // GIR_Coverage, 4903, |
| 174906 | GIR_EraseRootFromParent_Done, |
| 174907 | // Label 8189: @550939 |
| 174908 | GIM_Try, /*On fail goto*//*Label 8190*/ GIMT_Encode4(551008), // Rule ID 4907 // |
| 174909 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174910 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 174911 | // MIs[0] offset |
| 174912 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174913 | // MIs[0] auxiliary |
| 174914 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174915 | // MIs[0] Operand 7 |
| 174916 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174917 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174918 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact), |
| 174920 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174921 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174923 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174925 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174927 | GIR_RootConstrainSelectedInstOperands, |
| 174928 | // GIR_Coverage, 4907, |
| 174929 | GIR_EraseRootFromParent_Done, |
| 174930 | // Label 8190: @551008 |
| 174931 | GIM_Try, /*On fail goto*//*Label 8191*/ GIMT_Encode4(551078), // Rule ID 4896 // |
| 174932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174933 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174934 | // MIs[0] offset |
| 174935 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174936 | // MIs[0] auxiliary |
| 174937 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174938 | // MIs[0] Operand 7 |
| 174939 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174940 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174941 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174942 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_exact), |
| 174943 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174944 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174945 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174946 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174947 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174949 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174950 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174951 | GIR_RootConstrainSelectedInstOperands, |
| 174952 | // GIR_Coverage, 4896, |
| 174953 | GIR_EraseRootFromParent_Done, |
| 174954 | // Label 8191: @551078 |
| 174955 | GIM_Try, /*On fail goto*//*Label 8192*/ GIMT_Encode4(551145), // Rule ID 4900 // |
| 174956 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174957 | // MIs[0] offset |
| 174958 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174959 | // MIs[0] auxiliary |
| 174960 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174961 | // MIs[0] Operand 7 |
| 174962 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174964 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact), |
| 174966 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174967 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174968 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174970 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174972 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174974 | GIR_RootConstrainSelectedInstOperands, |
| 174975 | // GIR_Coverage, 4900, |
| 174976 | GIR_EraseRootFromParent_Done, |
| 174977 | // Label 8192: @551145 |
| 174978 | GIM_Try, /*On fail goto*//*Label 8193*/ GIMT_Encode4(551215), // Rule ID 4904 // |
| 174979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 174980 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 174981 | // MIs[0] offset |
| 174982 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 174983 | // MIs[0] auxiliary |
| 174984 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 174985 | // MIs[0] Operand 7 |
| 174986 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 174987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 174988 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 174989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_OFFEN_exact), |
| 174990 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 174991 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 174992 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 174993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 174994 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 174995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 174996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 174997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 174998 | GIR_RootConstrainSelectedInstOperands, |
| 174999 | // GIR_Coverage, 4904, |
| 175000 | GIR_EraseRootFromParent_Done, |
| 175001 | // Label 8193: @551215 |
| 175002 | GIM_Try, /*On fail goto*//*Label 8194*/ GIMT_Encode4(551282), // Rule ID 4908 // |
| 175003 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175004 | // MIs[0] offset |
| 175005 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175006 | // MIs[0] auxiliary |
| 175007 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175008 | // MIs[0] Operand 7 |
| 175009 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175010 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175011 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175012 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact), |
| 175013 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175014 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175015 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175016 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175017 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175019 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175020 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175021 | GIR_RootConstrainSelectedInstOperands, |
| 175022 | // GIR_Coverage, 4908, |
| 175023 | GIR_EraseRootFromParent_Done, |
| 175024 | // Label 8194: @551282 |
| 175025 | GIM_Try, /*On fail goto*//*Label 8195*/ GIMT_Encode4(551344), // Rule ID 4897 // |
| 175026 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175027 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175028 | // MIs[0] offset |
| 175029 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175030 | // MIs[0] auxiliary |
| 175031 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175032 | // MIs[0] Operand 7 |
| 175033 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175034 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175035 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175036 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_exact), |
| 175037 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175038 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175039 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175040 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175041 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175043 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175044 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175045 | GIR_RootConstrainSelectedInstOperands, |
| 175046 | // GIR_Coverage, 4897, |
| 175047 | GIR_EraseRootFromParent_Done, |
| 175048 | // Label 8195: @551344 |
| 175049 | GIM_Try, /*On fail goto*//*Label 8196*/ GIMT_Encode4(551403), // Rule ID 4901 // |
| 175050 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175051 | // MIs[0] offset |
| 175052 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175053 | // MIs[0] auxiliary |
| 175054 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175055 | // MIs[0] Operand 7 |
| 175056 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175057 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175058 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175059 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact), |
| 175060 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175061 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175062 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175063 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175064 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175067 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175068 | GIR_RootConstrainSelectedInstOperands, |
| 175069 | // GIR_Coverage, 4901, |
| 175070 | GIR_EraseRootFromParent_Done, |
| 175071 | // Label 8196: @551403 |
| 175072 | GIM_Try, /*On fail goto*//*Label 8197*/ GIMT_Encode4(551465), // Rule ID 4905 // |
| 175073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175074 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175075 | // MIs[0] offset |
| 175076 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175077 | // MIs[0] auxiliary |
| 175078 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175079 | // MIs[0] Operand 7 |
| 175080 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175082 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_IDXEN_exact), |
| 175084 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175085 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175086 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175088 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175089 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175090 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175091 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175092 | GIR_RootConstrainSelectedInstOperands, |
| 175093 | // GIR_Coverage, 4905, |
| 175094 | GIR_EraseRootFromParent_Done, |
| 175095 | // Label 8197: @551465 |
| 175096 | GIM_Try, /*On fail goto*//*Label 8198*/ GIMT_Encode4(551524), // Rule ID 4909 // |
| 175097 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175098 | // MIs[0] offset |
| 175099 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175100 | // MIs[0] auxiliary |
| 175101 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175102 | // MIs[0] Operand 7 |
| 175103 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175104 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175105 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175106 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact), |
| 175107 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175108 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175109 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175110 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175111 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175112 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175113 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175114 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175115 | GIR_RootConstrainSelectedInstOperands, |
| 175116 | // GIR_Coverage, 4909, |
| 175117 | GIR_EraseRootFromParent_Done, |
| 175118 | // Label 8198: @551524 |
| 175119 | GIM_Try, /*On fail goto*//*Label 8199*/ GIMT_Encode4(551624), // Rule ID 4898 // |
| 175120 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175121 | // MIs[0] offset |
| 175122 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175123 | // MIs[0] auxiliary |
| 175124 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175125 | // MIs[0] Operand 7 |
| 175126 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175128 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175129 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175130 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175131 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175132 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175133 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175134 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175135 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175136 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175137 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175138 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175139 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact), |
| 175140 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175141 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175142 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175143 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175144 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175145 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175146 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175147 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175148 | GIR_RootConstrainSelectedInstOperands, |
| 175149 | // GIR_Coverage, 4898, |
| 175150 | GIR_EraseRootFromParent_Done, |
| 175151 | // Label 8199: @551624 |
| 175152 | GIM_Try, /*On fail goto*//*Label 8200*/ GIMT_Encode4(551721), // Rule ID 4902 // |
| 175153 | // MIs[0] offset |
| 175154 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175155 | // MIs[0] auxiliary |
| 175156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175157 | // MIs[0] Operand 7 |
| 175158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175159 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175160 | // (SIbuffer_store_format v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175161 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175162 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175163 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175164 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175165 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175167 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175168 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175169 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175171 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact), |
| 175172 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175173 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175174 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175175 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175176 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175177 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175178 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175179 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175180 | GIR_RootConstrainSelectedInstOperands, |
| 175181 | // GIR_Coverage, 4902, |
| 175182 | GIR_EraseRootFromParent_Done, |
| 175183 | // Label 8200: @551721 |
| 175184 | GIM_Try, /*On fail goto*//*Label 8201*/ GIMT_Encode4(551821), // Rule ID 4906 // |
| 175185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175186 | // MIs[0] offset |
| 175187 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175188 | // MIs[0] auxiliary |
| 175189 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175190 | // MIs[0] Operand 7 |
| 175191 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175192 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175193 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175194 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175195 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175196 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175197 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175198 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175199 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175200 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175201 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175202 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175203 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175204 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_BOTHEN_exact), |
| 175205 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175206 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175207 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175208 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175209 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175210 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175211 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175212 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175213 | GIR_RootConstrainSelectedInstOperands, |
| 175214 | // GIR_Coverage, 4906, |
| 175215 | GIR_EraseRootFromParent_Done, |
| 175216 | // Label 8201: @551821 |
| 175217 | GIM_Try, /*On fail goto*//*Label 8202*/ GIMT_Encode4(551918), // Rule ID 4910 // |
| 175218 | // MIs[0] offset |
| 175219 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175220 | // MIs[0] auxiliary |
| 175221 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175222 | // MIs[0] Operand 7 |
| 175223 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175224 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175225 | // (SIbuffer_store_format v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175226 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175227 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175228 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175229 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175230 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175231 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175232 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175233 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175234 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175235 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact), |
| 175237 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175238 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175239 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175241 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175242 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175243 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175244 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175245 | GIR_RootConstrainSelectedInstOperands, |
| 175246 | // GIR_Coverage, 4910, |
| 175247 | GIR_EraseRootFromParent_Done, |
| 175248 | // Label 8202: @551918 |
| 175249 | GIM_Reject, |
| 175250 | // Label 8186: @551919 |
| 175251 | GIM_Reject, |
| 175252 | // Label 8142: @551920 |
| 175253 | GIM_Try, /*On fail goto*//*Label 8203*/ GIMT_Encode4(553130), |
| 175254 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 175255 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 175256 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 175257 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 175258 | GIM_Try, /*On fail goto*//*Label 8204*/ GIMT_Encode4(552009), // Rule ID 4911 // |
| 175259 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175262 | // MIs[0] offset |
| 175263 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175264 | // MIs[0] auxiliary |
| 175265 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175266 | // MIs[0] Operand 7 |
| 175267 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175268 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175269 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175270 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_exact), |
| 175271 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175272 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175273 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175274 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175275 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175276 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175277 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175278 | GIR_RootConstrainSelectedInstOperands, |
| 175279 | // GIR_Coverage, 4911, |
| 175280 | GIR_EraseRootFromParent_Done, |
| 175281 | // Label 8204: @552009 |
| 175282 | GIM_Try, /*On fail goto*//*Label 8205*/ GIMT_Encode4(552078), // Rule ID 4915 // |
| 175283 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175284 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175285 | // MIs[0] offset |
| 175286 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175287 | // MIs[0] auxiliary |
| 175288 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175289 | // MIs[0] Operand 7 |
| 175290 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175292 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact), |
| 175294 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175295 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175297 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175300 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175301 | GIR_RootConstrainSelectedInstOperands, |
| 175302 | // GIR_Coverage, 4915, |
| 175303 | GIR_EraseRootFromParent_Done, |
| 175304 | // Label 8205: @552078 |
| 175305 | GIM_Try, /*On fail goto*//*Label 8206*/ GIMT_Encode4(552150), // Rule ID 4919 // |
| 175306 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175307 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175308 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175309 | // MIs[0] offset |
| 175310 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175311 | // MIs[0] auxiliary |
| 175312 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175313 | // MIs[0] Operand 7 |
| 175314 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175316 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFSET_exact), |
| 175318 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175319 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175320 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175321 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175322 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175324 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175325 | GIR_RootConstrainSelectedInstOperands, |
| 175326 | // GIR_Coverage, 4919, |
| 175327 | GIR_EraseRootFromParent_Done, |
| 175328 | // Label 8206: @552150 |
| 175329 | GIM_Try, /*On fail goto*//*Label 8207*/ GIMT_Encode4(552219), // Rule ID 4923 // |
| 175330 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175332 | // MIs[0] offset |
| 175333 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175334 | // MIs[0] auxiliary |
| 175335 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175336 | // MIs[0] Operand 7 |
| 175337 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175339 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175340 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact), |
| 175341 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175342 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175344 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175345 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175346 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175347 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175348 | GIR_RootConstrainSelectedInstOperands, |
| 175349 | // GIR_Coverage, 4923, |
| 175350 | GIR_EraseRootFromParent_Done, |
| 175351 | // Label 8207: @552219 |
| 175352 | GIM_Try, /*On fail goto*//*Label 8208*/ GIMT_Encode4(552289), // Rule ID 4912 // |
| 175353 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175354 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175355 | // MIs[0] offset |
| 175356 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175357 | // MIs[0] auxiliary |
| 175358 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175359 | // MIs[0] Operand 7 |
| 175360 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175361 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175362 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175363 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_exact), |
| 175364 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175365 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175366 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175367 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175368 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175370 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175371 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175372 | GIR_RootConstrainSelectedInstOperands, |
| 175373 | // GIR_Coverage, 4912, |
| 175374 | GIR_EraseRootFromParent_Done, |
| 175375 | // Label 8208: @552289 |
| 175376 | GIM_Try, /*On fail goto*//*Label 8209*/ GIMT_Encode4(552356), // Rule ID 4916 // |
| 175377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175378 | // MIs[0] offset |
| 175379 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175380 | // MIs[0] auxiliary |
| 175381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175382 | // MIs[0] Operand 7 |
| 175383 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175384 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175385 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175386 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact), |
| 175387 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175388 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175389 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175390 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175391 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175392 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175393 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175394 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175395 | GIR_RootConstrainSelectedInstOperands, |
| 175396 | // GIR_Coverage, 4916, |
| 175397 | GIR_EraseRootFromParent_Done, |
| 175398 | // Label 8209: @552356 |
| 175399 | GIM_Try, /*On fail goto*//*Label 8210*/ GIMT_Encode4(552426), // Rule ID 4920 // |
| 175400 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175401 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175402 | // MIs[0] offset |
| 175403 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175404 | // MIs[0] auxiliary |
| 175405 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175406 | // MIs[0] Operand 7 |
| 175407 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175408 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175409 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175410 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_OFFEN_exact), |
| 175411 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175412 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175413 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175414 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175415 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175417 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175418 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175419 | GIR_RootConstrainSelectedInstOperands, |
| 175420 | // GIR_Coverage, 4920, |
| 175421 | GIR_EraseRootFromParent_Done, |
| 175422 | // Label 8210: @552426 |
| 175423 | GIM_Try, /*On fail goto*//*Label 8211*/ GIMT_Encode4(552493), // Rule ID 4924 // |
| 175424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175425 | // MIs[0] offset |
| 175426 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175427 | // MIs[0] auxiliary |
| 175428 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175429 | // MIs[0] Operand 7 |
| 175430 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175431 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175432 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175433 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact), |
| 175434 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175435 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175436 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175437 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175438 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175439 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175440 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175441 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175442 | GIR_RootConstrainSelectedInstOperands, |
| 175443 | // GIR_Coverage, 4924, |
| 175444 | GIR_EraseRootFromParent_Done, |
| 175445 | // Label 8211: @552493 |
| 175446 | GIM_Try, /*On fail goto*//*Label 8212*/ GIMT_Encode4(552555), // Rule ID 4913 // |
| 175447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175449 | // MIs[0] offset |
| 175450 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175451 | // MIs[0] auxiliary |
| 175452 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175453 | // MIs[0] Operand 7 |
| 175454 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175456 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_exact), |
| 175458 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175459 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175460 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175462 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175465 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175466 | GIR_RootConstrainSelectedInstOperands, |
| 175467 | // GIR_Coverage, 4913, |
| 175468 | GIR_EraseRootFromParent_Done, |
| 175469 | // Label 8212: @552555 |
| 175470 | GIM_Try, /*On fail goto*//*Label 8213*/ GIMT_Encode4(552614), // Rule ID 4917 // |
| 175471 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175472 | // MIs[0] offset |
| 175473 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175474 | // MIs[0] auxiliary |
| 175475 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175476 | // MIs[0] Operand 7 |
| 175477 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175478 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175479 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175480 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact), |
| 175481 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175482 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175483 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175484 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175485 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175486 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175487 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175488 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175489 | GIR_RootConstrainSelectedInstOperands, |
| 175490 | // GIR_Coverage, 4917, |
| 175491 | GIR_EraseRootFromParent_Done, |
| 175492 | // Label 8213: @552614 |
| 175493 | GIM_Try, /*On fail goto*//*Label 8214*/ GIMT_Encode4(552676), // Rule ID 4921 // |
| 175494 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175495 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175496 | // MIs[0] offset |
| 175497 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175498 | // MIs[0] auxiliary |
| 175499 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175500 | // MIs[0] Operand 7 |
| 175501 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175502 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175503 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175504 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_IDXEN_exact), |
| 175505 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175506 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175507 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175508 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175509 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175510 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175511 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175512 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175513 | GIR_RootConstrainSelectedInstOperands, |
| 175514 | // GIR_Coverage, 4921, |
| 175515 | GIR_EraseRootFromParent_Done, |
| 175516 | // Label 8214: @552676 |
| 175517 | GIM_Try, /*On fail goto*//*Label 8215*/ GIMT_Encode4(552735), // Rule ID 4925 // |
| 175518 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175519 | // MIs[0] offset |
| 175520 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175521 | // MIs[0] auxiliary |
| 175522 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175523 | // MIs[0] Operand 7 |
| 175524 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175525 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175526 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175527 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact), |
| 175528 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175529 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175530 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175531 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175532 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175533 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175534 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175535 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175536 | GIR_RootConstrainSelectedInstOperands, |
| 175537 | // GIR_Coverage, 4925, |
| 175538 | GIR_EraseRootFromParent_Done, |
| 175539 | // Label 8215: @552735 |
| 175540 | GIM_Try, /*On fail goto*//*Label 8216*/ GIMT_Encode4(552835), // Rule ID 4914 // |
| 175541 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175542 | // MIs[0] offset |
| 175543 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175544 | // MIs[0] auxiliary |
| 175545 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175546 | // MIs[0] Operand 7 |
| 175547 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175548 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175549 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175550 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175551 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175552 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175553 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175554 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175555 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175556 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175557 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175558 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175559 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175560 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact), |
| 175561 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175562 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175563 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175564 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175565 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175566 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175569 | GIR_RootConstrainSelectedInstOperands, |
| 175570 | // GIR_Coverage, 4914, |
| 175571 | GIR_EraseRootFromParent_Done, |
| 175572 | // Label 8216: @552835 |
| 175573 | GIM_Try, /*On fail goto*//*Label 8217*/ GIMT_Encode4(552932), // Rule ID 4918 // |
| 175574 | // MIs[0] offset |
| 175575 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175576 | // MIs[0] auxiliary |
| 175577 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175578 | // MIs[0] Operand 7 |
| 175579 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175580 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175581 | // (SIbuffer_store_format v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175582 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175583 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175584 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175585 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175586 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175587 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175588 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175589 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175590 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175591 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact), |
| 175593 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175594 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175595 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175597 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175598 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175600 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175601 | GIR_RootConstrainSelectedInstOperands, |
| 175602 | // GIR_Coverage, 4918, |
| 175603 | GIR_EraseRootFromParent_Done, |
| 175604 | // Label 8217: @552932 |
| 175605 | GIM_Try, /*On fail goto*//*Label 8218*/ GIMT_Encode4(553032), // Rule ID 4922 // |
| 175606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 175607 | // MIs[0] offset |
| 175608 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175609 | // MIs[0] auxiliary |
| 175610 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175611 | // MIs[0] Operand 7 |
| 175612 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175613 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175614 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175615 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175616 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175617 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175618 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175619 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175620 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175621 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175622 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175623 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175624 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175625 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_BOTHEN_exact), |
| 175626 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175627 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175628 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175629 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175630 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175631 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175633 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175634 | GIR_RootConstrainSelectedInstOperands, |
| 175635 | // GIR_Coverage, 4922, |
| 175636 | GIR_EraseRootFromParent_Done, |
| 175637 | // Label 8218: @553032 |
| 175638 | GIM_Try, /*On fail goto*//*Label 8219*/ GIMT_Encode4(553129), // Rule ID 4926 // |
| 175639 | // MIs[0] offset |
| 175640 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175641 | // MIs[0] auxiliary |
| 175642 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175643 | // MIs[0] Operand 7 |
| 175644 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175645 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175646 | // (SIbuffer_store_format v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175647 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 175648 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 175649 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 175650 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 175651 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 175652 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 175653 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 175654 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 175655 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175656 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 175657 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact), |
| 175658 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175659 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 175660 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175661 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175662 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175663 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175664 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175665 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175666 | GIR_RootConstrainSelectedInstOperands, |
| 175667 | // GIR_Coverage, 4926, |
| 175668 | GIR_EraseRootFromParent_Done, |
| 175669 | // Label 8219: @553129 |
| 175670 | GIM_Reject, |
| 175671 | // Label 8203: @553130 |
| 175672 | GIM_Reject, |
| 175673 | // Label 8143: @553131 |
| 175674 | GIM_Reject, |
| 175675 | // Label 141: @553132 |
| 175676 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 8227*/ GIMT_Encode4(559396), |
| 175677 | /*GILLT_s16*//*Label 8220*/ GIMT_Encode4(553183), |
| 175678 | /*GILLT_s32*//*Label 8221*/ GIMT_Encode4(555026), GIMT_Encode4(0), |
| 175679 | /*GILLT_v2s16*//*Label 8222*/ GIMT_Encode4(555957), |
| 175680 | /*GILLT_v2s32*//*Label 8223*/ GIMT_Encode4(557192), GIMT_Encode4(0), |
| 175681 | /*GILLT_v3s32*//*Label 8224*/ GIMT_Encode4(557515), GIMT_Encode4(0), |
| 175682 | /*GILLT_v4s16*//*Label 8225*/ GIMT_Encode4(557838), |
| 175683 | /*GILLT_v4s32*//*Label 8226*/ GIMT_Encode4(559073), |
| 175684 | // Label 8220: @553183 |
| 175685 | GIM_Try, /*On fail goto*//*Label 8228*/ GIMT_Encode4(555025), |
| 175686 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 175687 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 175688 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 175689 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 175690 | GIM_Try, /*On fail goto*//*Label 8229*/ GIMT_Encode4(553272), // Rule ID 4927 // |
| 175691 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 175692 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175693 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175694 | // MIs[0] offset |
| 175695 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175696 | // MIs[0] auxiliary |
| 175697 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175698 | // MIs[0] Operand 7 |
| 175699 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175700 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175701 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175702 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact), |
| 175703 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175704 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175705 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175706 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175707 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175708 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175709 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175710 | GIR_RootConstrainSelectedInstOperands, |
| 175711 | // GIR_Coverage, 4927, |
| 175712 | GIR_EraseRootFromParent_Done, |
| 175713 | // Label 8229: @553272 |
| 175714 | GIM_Try, /*On fail goto*//*Label 8230*/ GIMT_Encode4(553344), // Rule ID 4931 // |
| 175715 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 175716 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175717 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175718 | // MIs[0] offset |
| 175719 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175720 | // MIs[0] auxiliary |
| 175721 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175722 | // MIs[0] Operand 7 |
| 175723 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175724 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175725 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15876:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175726 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact), |
| 175727 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175728 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175729 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175730 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175731 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175732 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175734 | GIR_RootConstrainSelectedInstOperands, |
| 175735 | // GIR_Coverage, 4931, |
| 175736 | GIR_EraseRootFromParent_Done, |
| 175737 | // Label 8230: @553344 |
| 175738 | GIM_Try, /*On fail goto*//*Label 8231*/ GIMT_Encode4(553416), // Rule ID 4951 // |
| 175739 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 175740 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175741 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175742 | // MIs[0] offset |
| 175743 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175744 | // MIs[0] auxiliary |
| 175745 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175746 | // MIs[0] Operand 7 |
| 175747 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175749 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact), |
| 175751 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175752 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175753 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175754 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175755 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175756 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175757 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175758 | GIR_RootConstrainSelectedInstOperands, |
| 175759 | // GIR_Coverage, 4951, |
| 175760 | GIR_EraseRootFromParent_Done, |
| 175761 | // Label 8231: @553416 |
| 175762 | GIM_Try, /*On fail goto*//*Label 8232*/ GIMT_Encode4(553488), // Rule ID 4955 // |
| 175763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 175764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175765 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175766 | // MIs[0] offset |
| 175767 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175768 | // MIs[0] auxiliary |
| 175769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175770 | // MIs[0] Operand 7 |
| 175771 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175773 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact), |
| 175775 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175776 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175777 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175778 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175779 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175780 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175781 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175782 | GIR_RootConstrainSelectedInstOperands, |
| 175783 | // GIR_Coverage, 4955, |
| 175784 | GIR_EraseRootFromParent_Done, |
| 175785 | // Label 8232: @553488 |
| 175786 | GIM_Try, /*On fail goto*//*Label 8233*/ GIMT_Encode4(553560), // Rule ID 4959 // |
| 175787 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 175788 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175790 | // MIs[0] offset |
| 175791 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175792 | // MIs[0] auxiliary |
| 175793 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175794 | // MIs[0] Operand 7 |
| 175795 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175797 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15876:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact), |
| 175799 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175800 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175801 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175802 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175803 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175804 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175805 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175806 | GIR_RootConstrainSelectedInstOperands, |
| 175807 | // GIR_Coverage, 4959, |
| 175808 | GIR_EraseRootFromParent_Done, |
| 175809 | // Label 8233: @553560 |
| 175810 | GIM_Try, /*On fail goto*//*Label 8234*/ GIMT_Encode4(553632), // Rule ID 4963 // |
| 175811 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 175812 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175813 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175814 | // MIs[0] offset |
| 175815 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175816 | // MIs[0] auxiliary |
| 175817 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175818 | // MIs[0] Operand 7 |
| 175819 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175820 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175821 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175822 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact), |
| 175823 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175824 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175826 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175827 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175829 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175830 | GIR_RootConstrainSelectedInstOperands, |
| 175831 | // GIR_Coverage, 4963, |
| 175832 | GIR_EraseRootFromParent_Done, |
| 175833 | // Label 8234: @553632 |
| 175834 | GIM_Try, /*On fail goto*//*Label 8235*/ GIMT_Encode4(553702), // Rule ID 4928 // |
| 175835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 175836 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175837 | // MIs[0] offset |
| 175838 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175839 | // MIs[0] auxiliary |
| 175840 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175841 | // MIs[0] Operand 7 |
| 175842 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175843 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175844 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175845 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact), |
| 175846 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175847 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175848 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175849 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175850 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175851 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175852 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175853 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175854 | GIR_RootConstrainSelectedInstOperands, |
| 175855 | // GIR_Coverage, 4928, |
| 175856 | GIR_EraseRootFromParent_Done, |
| 175857 | // Label 8235: @553702 |
| 175858 | GIM_Try, /*On fail goto*//*Label 8236*/ GIMT_Encode4(553772), // Rule ID 4932 // |
| 175859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 175860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175861 | // MIs[0] offset |
| 175862 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175863 | // MIs[0] auxiliary |
| 175864 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175865 | // MIs[0] Operand 7 |
| 175866 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175868 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact), |
| 175870 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175871 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175872 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175873 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175874 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175875 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175876 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175877 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175878 | GIR_RootConstrainSelectedInstOperands, |
| 175879 | // GIR_Coverage, 4932, |
| 175880 | GIR_EraseRootFromParent_Done, |
| 175881 | // Label 8236: @553772 |
| 175882 | GIM_Try, /*On fail goto*//*Label 8237*/ GIMT_Encode4(553842), // Rule ID 4952 // |
| 175883 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 175884 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175885 | // MIs[0] offset |
| 175886 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175887 | // MIs[0] auxiliary |
| 175888 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175889 | // MIs[0] Operand 7 |
| 175890 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175892 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact), |
| 175894 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175895 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175896 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175898 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175899 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175902 | GIR_RootConstrainSelectedInstOperands, |
| 175903 | // GIR_Coverage, 4952, |
| 175904 | GIR_EraseRootFromParent_Done, |
| 175905 | // Label 8237: @553842 |
| 175906 | GIM_Try, /*On fail goto*//*Label 8238*/ GIMT_Encode4(553912), // Rule ID 4956 // |
| 175907 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 175908 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175909 | // MIs[0] offset |
| 175910 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175911 | // MIs[0] auxiliary |
| 175912 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175913 | // MIs[0] Operand 7 |
| 175914 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175916 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact), |
| 175918 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175919 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175920 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175921 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175922 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175923 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175925 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175926 | GIR_RootConstrainSelectedInstOperands, |
| 175927 | // GIR_Coverage, 4956, |
| 175928 | GIR_EraseRootFromParent_Done, |
| 175929 | // Label 8238: @553912 |
| 175930 | GIM_Try, /*On fail goto*//*Label 8239*/ GIMT_Encode4(553982), // Rule ID 4960 // |
| 175931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 175932 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175933 | // MIs[0] offset |
| 175934 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175935 | // MIs[0] auxiliary |
| 175936 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175937 | // MIs[0] Operand 7 |
| 175938 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175939 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175940 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175941 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact), |
| 175942 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175943 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175944 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175945 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175946 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175947 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175948 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175949 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175950 | GIR_RootConstrainSelectedInstOperands, |
| 175951 | // GIR_Coverage, 4960, |
| 175952 | GIR_EraseRootFromParent_Done, |
| 175953 | // Label 8239: @553982 |
| 175954 | GIM_Try, /*On fail goto*//*Label 8240*/ GIMT_Encode4(554052), // Rule ID 4964 // |
| 175955 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 175956 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 175957 | // MIs[0] offset |
| 175958 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175959 | // MIs[0] auxiliary |
| 175960 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175961 | // MIs[0] Operand 7 |
| 175962 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 175963 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175964 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175965 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact), |
| 175966 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175967 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 175968 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175969 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175970 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175971 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175972 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175973 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175974 | GIR_RootConstrainSelectedInstOperands, |
| 175975 | // GIR_Coverage, 4964, |
| 175976 | GIR_EraseRootFromParent_Done, |
| 175977 | // Label 8240: @554052 |
| 175978 | GIM_Try, /*On fail goto*//*Label 8241*/ GIMT_Encode4(554114), // Rule ID 4929 // |
| 175979 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 175980 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 175981 | // MIs[0] offset |
| 175982 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 175983 | // MIs[0] auxiliary |
| 175984 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 175985 | // MIs[0] Operand 7 |
| 175986 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 175987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 175988 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 175989 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact), |
| 175990 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 175991 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 175992 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 175993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 175994 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 175995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 175996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 175997 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 175998 | GIR_RootConstrainSelectedInstOperands, |
| 175999 | // GIR_Coverage, 4929, |
| 176000 | GIR_EraseRootFromParent_Done, |
| 176001 | // Label 8241: @554114 |
| 176002 | GIM_Try, /*On fail goto*//*Label 8242*/ GIMT_Encode4(554176), // Rule ID 4933 // |
| 176003 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176004 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176005 | // MIs[0] offset |
| 176006 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176007 | // MIs[0] auxiliary |
| 176008 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176009 | // MIs[0] Operand 7 |
| 176010 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176012 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact), |
| 176014 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176015 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176016 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176018 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176019 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176020 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176021 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176022 | GIR_RootConstrainSelectedInstOperands, |
| 176023 | // GIR_Coverage, 4933, |
| 176024 | GIR_EraseRootFromParent_Done, |
| 176025 | // Label 8242: @554176 |
| 176026 | GIM_Try, /*On fail goto*//*Label 8243*/ GIMT_Encode4(554238), // Rule ID 4953 // |
| 176027 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176028 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176029 | // MIs[0] offset |
| 176030 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176031 | // MIs[0] auxiliary |
| 176032 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176033 | // MIs[0] Operand 7 |
| 176034 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176035 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176036 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176037 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact), |
| 176038 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176039 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176040 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176041 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176042 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176043 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176044 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176046 | GIR_RootConstrainSelectedInstOperands, |
| 176047 | // GIR_Coverage, 4953, |
| 176048 | GIR_EraseRootFromParent_Done, |
| 176049 | // Label 8243: @554238 |
| 176050 | GIM_Try, /*On fail goto*//*Label 8244*/ GIMT_Encode4(554300), // Rule ID 4957 // |
| 176051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176052 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176053 | // MIs[0] offset |
| 176054 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176055 | // MIs[0] auxiliary |
| 176056 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176057 | // MIs[0] Operand 7 |
| 176058 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176059 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176060 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176061 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact), |
| 176062 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176063 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176064 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176065 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176066 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176067 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176068 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176070 | GIR_RootConstrainSelectedInstOperands, |
| 176071 | // GIR_Coverage, 4957, |
| 176072 | GIR_EraseRootFromParent_Done, |
| 176073 | // Label 8244: @554300 |
| 176074 | GIM_Try, /*On fail goto*//*Label 8245*/ GIMT_Encode4(554362), // Rule ID 4961 // |
| 176075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176076 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176077 | // MIs[0] offset |
| 176078 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176079 | // MIs[0] auxiliary |
| 176080 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176081 | // MIs[0] Operand 7 |
| 176082 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176083 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176084 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176085 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact), |
| 176086 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176087 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176088 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176089 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176090 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176091 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176092 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176093 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176094 | GIR_RootConstrainSelectedInstOperands, |
| 176095 | // GIR_Coverage, 4961, |
| 176096 | GIR_EraseRootFromParent_Done, |
| 176097 | // Label 8245: @554362 |
| 176098 | GIM_Try, /*On fail goto*//*Label 8246*/ GIMT_Encode4(554424), // Rule ID 4965 // |
| 176099 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176100 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176101 | // MIs[0] offset |
| 176102 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176103 | // MIs[0] auxiliary |
| 176104 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176105 | // MIs[0] Operand 7 |
| 176106 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176107 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176108 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176109 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact), |
| 176110 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176111 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176112 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176113 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176114 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176115 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176116 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176117 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176118 | GIR_RootConstrainSelectedInstOperands, |
| 176119 | // GIR_Coverage, 4965, |
| 176120 | GIR_EraseRootFromParent_Done, |
| 176121 | // Label 8246: @554424 |
| 176122 | GIM_Try, /*On fail goto*//*Label 8247*/ GIMT_Encode4(554524), // Rule ID 4930 // |
| 176123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176124 | // MIs[0] offset |
| 176125 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176126 | // MIs[0] auxiliary |
| 176127 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176128 | // MIs[0] Operand 7 |
| 176129 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176130 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176131 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176132 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176133 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176134 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176135 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176136 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176137 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176138 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176139 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176140 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176141 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176142 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact), |
| 176143 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176144 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176145 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176147 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176149 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176150 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176151 | GIR_RootConstrainSelectedInstOperands, |
| 176152 | // GIR_Coverage, 4930, |
| 176153 | GIR_EraseRootFromParent_Done, |
| 176154 | // Label 8247: @554524 |
| 176155 | GIM_Try, /*On fail goto*//*Label 8248*/ GIMT_Encode4(554624), // Rule ID 4934 // |
| 176156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176157 | // MIs[0] offset |
| 176158 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176159 | // MIs[0] auxiliary |
| 176160 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176161 | // MIs[0] Operand 7 |
| 176162 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176163 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176164 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15876:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176165 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176166 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176167 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176168 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176169 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176170 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176171 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176173 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176174 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact), |
| 176176 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176177 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176178 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176180 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176182 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176183 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176184 | GIR_RootConstrainSelectedInstOperands, |
| 176185 | // GIR_Coverage, 4934, |
| 176186 | GIR_EraseRootFromParent_Done, |
| 176187 | // Label 8248: @554624 |
| 176188 | GIM_Try, /*On fail goto*//*Label 8249*/ GIMT_Encode4(554724), // Rule ID 4954 // |
| 176189 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176190 | // MIs[0] offset |
| 176191 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176192 | // MIs[0] auxiliary |
| 176193 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176194 | // MIs[0] Operand 7 |
| 176195 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176197 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176203 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176204 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176206 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176207 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact), |
| 176209 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176210 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176211 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176213 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176214 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176216 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176217 | GIR_RootConstrainSelectedInstOperands, |
| 176218 | // GIR_Coverage, 4954, |
| 176219 | GIR_EraseRootFromParent_Done, |
| 176220 | // Label 8249: @554724 |
| 176221 | GIM_Try, /*On fail goto*//*Label 8250*/ GIMT_Encode4(554824), // Rule ID 4958 // |
| 176222 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176223 | // MIs[0] offset |
| 176224 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176225 | // MIs[0] auxiliary |
| 176226 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176227 | // MIs[0] Operand 7 |
| 176228 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176229 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176230 | // (SIbuffer_store_format_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176231 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176232 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176233 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176234 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176235 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176236 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176237 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176238 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176239 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176240 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176241 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact), |
| 176242 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176243 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176244 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176245 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176246 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176247 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176248 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176249 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176250 | GIR_RootConstrainSelectedInstOperands, |
| 176251 | // GIR_Coverage, 4958, |
| 176252 | GIR_EraseRootFromParent_Done, |
| 176253 | // Label 8250: @554824 |
| 176254 | GIM_Try, /*On fail goto*//*Label 8251*/ GIMT_Encode4(554924), // Rule ID 4962 // |
| 176255 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176256 | // MIs[0] offset |
| 176257 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176258 | // MIs[0] auxiliary |
| 176259 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176260 | // MIs[0] Operand 7 |
| 176261 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176262 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176263 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15876:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176264 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176265 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176266 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176267 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176268 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176269 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176270 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176271 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176272 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176273 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176274 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact), |
| 176275 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176276 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176277 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176278 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176279 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176280 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176281 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176282 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176283 | GIR_RootConstrainSelectedInstOperands, |
| 176284 | // GIR_Coverage, 4962, |
| 176285 | GIR_EraseRootFromParent_Done, |
| 176286 | // Label 8251: @554924 |
| 176287 | GIM_Try, /*On fail goto*//*Label 8252*/ GIMT_Encode4(555024), // Rule ID 4966 // |
| 176288 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176289 | // MIs[0] offset |
| 176290 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176291 | // MIs[0] auxiliary |
| 176292 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176293 | // MIs[0] Operand 7 |
| 176294 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176295 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176296 | // (SIbuffer_store_format_d16 i16:{ *:[i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176297 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176298 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176299 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176300 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176301 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176302 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176303 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176304 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176305 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176306 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact), |
| 176308 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176309 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176310 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176311 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176312 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176313 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176314 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176315 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176316 | GIR_RootConstrainSelectedInstOperands, |
| 176317 | // GIR_Coverage, 4966, |
| 176318 | GIR_EraseRootFromParent_Done, |
| 176319 | // Label 8252: @555024 |
| 176320 | GIM_Reject, |
| 176321 | // Label 8228: @555025 |
| 176322 | GIM_Reject, |
| 176323 | // Label 8221: @555026 |
| 176324 | GIM_Try, /*On fail goto*//*Label 8253*/ GIMT_Encode4(555956), |
| 176325 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 176326 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 176327 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 176328 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 176329 | GIM_Try, /*On fail goto*//*Label 8254*/ GIMT_Encode4(555115), // Rule ID 4935 // |
| 176330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176331 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176332 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176333 | // MIs[0] offset |
| 176334 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176335 | // MIs[0] auxiliary |
| 176336 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176337 | // MIs[0] Operand 7 |
| 176338 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176340 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176341 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact), |
| 176342 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176343 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176344 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176345 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176346 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176347 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176348 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176349 | GIR_RootConstrainSelectedInstOperands, |
| 176350 | // GIR_Coverage, 4935, |
| 176351 | GIR_EraseRootFromParent_Done, |
| 176352 | // Label 8254: @555115 |
| 176353 | GIM_Try, /*On fail goto*//*Label 8255*/ GIMT_Encode4(555187), // Rule ID 4967 // |
| 176354 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176355 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176356 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176357 | // MIs[0] offset |
| 176358 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176359 | // MIs[0] auxiliary |
| 176360 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176361 | // MIs[0] Operand 7 |
| 176362 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176363 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176364 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176365 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFSET_exact), |
| 176366 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176367 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176368 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176369 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176370 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176371 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176372 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176373 | GIR_RootConstrainSelectedInstOperands, |
| 176374 | // GIR_Coverage, 4967, |
| 176375 | GIR_EraseRootFromParent_Done, |
| 176376 | // Label 8255: @555187 |
| 176377 | GIM_Try, /*On fail goto*//*Label 8256*/ GIMT_Encode4(555259), // Rule ID 4971 // |
| 176378 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176379 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176380 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176381 | // MIs[0] offset |
| 176382 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176383 | // MIs[0] auxiliary |
| 176384 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176385 | // MIs[0] Operand 7 |
| 176386 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176388 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact), |
| 176390 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176391 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176393 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176395 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176397 | GIR_RootConstrainSelectedInstOperands, |
| 176398 | // GIR_Coverage, 4971, |
| 176399 | GIR_EraseRootFromParent_Done, |
| 176400 | // Label 8256: @555259 |
| 176401 | GIM_Try, /*On fail goto*//*Label 8257*/ GIMT_Encode4(555329), // Rule ID 4936 // |
| 176402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176403 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176404 | // MIs[0] offset |
| 176405 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176406 | // MIs[0] auxiliary |
| 176407 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176408 | // MIs[0] Operand 7 |
| 176409 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176410 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176411 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176412 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact), |
| 176413 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176414 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176415 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176417 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176418 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176419 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176420 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176421 | GIR_RootConstrainSelectedInstOperands, |
| 176422 | // GIR_Coverage, 4936, |
| 176423 | GIR_EraseRootFromParent_Done, |
| 176424 | // Label 8257: @555329 |
| 176425 | GIM_Try, /*On fail goto*//*Label 8258*/ GIMT_Encode4(555399), // Rule ID 4968 // |
| 176426 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176427 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176428 | // MIs[0] offset |
| 176429 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176430 | // MIs[0] auxiliary |
| 176431 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176432 | // MIs[0] Operand 7 |
| 176433 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176435 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_OFFEN_exact), |
| 176437 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176438 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176439 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176440 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176441 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176442 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176445 | GIR_RootConstrainSelectedInstOperands, |
| 176446 | // GIR_Coverage, 4968, |
| 176447 | GIR_EraseRootFromParent_Done, |
| 176448 | // Label 8258: @555399 |
| 176449 | GIM_Try, /*On fail goto*//*Label 8259*/ GIMT_Encode4(555469), // Rule ID 4972 // |
| 176450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176451 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176452 | // MIs[0] offset |
| 176453 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176454 | // MIs[0] auxiliary |
| 176455 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176456 | // MIs[0] Operand 7 |
| 176457 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176459 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact), |
| 176461 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176462 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176463 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176464 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176465 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176466 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176469 | GIR_RootConstrainSelectedInstOperands, |
| 176470 | // GIR_Coverage, 4972, |
| 176471 | GIR_EraseRootFromParent_Done, |
| 176472 | // Label 8259: @555469 |
| 176473 | GIM_Try, /*On fail goto*//*Label 8260*/ GIMT_Encode4(555531), // Rule ID 4937 // |
| 176474 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176475 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176476 | // MIs[0] offset |
| 176477 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176478 | // MIs[0] auxiliary |
| 176479 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176480 | // MIs[0] Operand 7 |
| 176481 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176482 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176483 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176484 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact), |
| 176485 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176486 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176487 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176488 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176489 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176490 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176491 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176493 | GIR_RootConstrainSelectedInstOperands, |
| 176494 | // GIR_Coverage, 4937, |
| 176495 | GIR_EraseRootFromParent_Done, |
| 176496 | // Label 8260: @555531 |
| 176497 | GIM_Try, /*On fail goto*//*Label 8261*/ GIMT_Encode4(555593), // Rule ID 4969 // |
| 176498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176500 | // MIs[0] offset |
| 176501 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176502 | // MIs[0] auxiliary |
| 176503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176504 | // MIs[0] Operand 7 |
| 176505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176506 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176507 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_IDXEN_exact), |
| 176509 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176510 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176511 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176512 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176513 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176514 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176515 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176516 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176517 | GIR_RootConstrainSelectedInstOperands, |
| 176518 | // GIR_Coverage, 4969, |
| 176519 | GIR_EraseRootFromParent_Done, |
| 176520 | // Label 8261: @555593 |
| 176521 | GIM_Try, /*On fail goto*//*Label 8262*/ GIMT_Encode4(555655), // Rule ID 4973 // |
| 176522 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176523 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176524 | // MIs[0] offset |
| 176525 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176526 | // MIs[0] auxiliary |
| 176527 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176528 | // MIs[0] Operand 7 |
| 176529 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176530 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176531 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176532 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact), |
| 176533 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176534 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176535 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176536 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176537 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176538 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176539 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176540 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176541 | GIR_RootConstrainSelectedInstOperands, |
| 176542 | // GIR_Coverage, 4973, |
| 176543 | GIR_EraseRootFromParent_Done, |
| 176544 | // Label 8262: @555655 |
| 176545 | GIM_Try, /*On fail goto*//*Label 8263*/ GIMT_Encode4(555755), // Rule ID 4938 // |
| 176546 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 176547 | // MIs[0] offset |
| 176548 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176549 | // MIs[0] auxiliary |
| 176550 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176551 | // MIs[0] Operand 7 |
| 176552 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176553 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176554 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176555 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176556 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176557 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176558 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176559 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176560 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176561 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176562 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176563 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176564 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact), |
| 176566 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176567 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176568 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176570 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176573 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176574 | GIR_RootConstrainSelectedInstOperands, |
| 176575 | // GIR_Coverage, 4938, |
| 176576 | GIR_EraseRootFromParent_Done, |
| 176577 | // Label 8263: @555755 |
| 176578 | GIM_Try, /*On fail goto*//*Label 8264*/ GIMT_Encode4(555855), // Rule ID 4970 // |
| 176579 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176580 | // MIs[0] offset |
| 176581 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176582 | // MIs[0] auxiliary |
| 176583 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176584 | // MIs[0] Operand 7 |
| 176585 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176586 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176587 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176588 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176589 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176590 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176591 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176592 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176593 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176594 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176595 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176596 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176597 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176598 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_BOTHEN_exact), |
| 176599 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176600 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176601 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176602 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176603 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176604 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176605 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176607 | GIR_RootConstrainSelectedInstOperands, |
| 176608 | // GIR_Coverage, 4970, |
| 176609 | GIR_EraseRootFromParent_Done, |
| 176610 | // Label 8264: @555855 |
| 176611 | GIM_Try, /*On fail goto*//*Label 8265*/ GIMT_Encode4(555955), // Rule ID 4974 // |
| 176612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176613 | // MIs[0] offset |
| 176614 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176615 | // MIs[0] auxiliary |
| 176616 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176617 | // MIs[0] Operand 7 |
| 176618 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176619 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176620 | // (SIbuffer_store_format_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176621 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176622 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176623 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176624 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176625 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176626 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176627 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176628 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176629 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176630 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176631 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact), |
| 176632 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176633 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176634 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176635 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176636 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176637 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176638 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176639 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176640 | GIR_RootConstrainSelectedInstOperands, |
| 176641 | // GIR_Coverage, 4974, |
| 176642 | GIR_EraseRootFromParent_Done, |
| 176643 | // Label 8265: @555955 |
| 176644 | GIM_Reject, |
| 176645 | // Label 8253: @555956 |
| 176646 | GIM_Reject, |
| 176647 | // Label 8222: @555957 |
| 176648 | GIM_Try, /*On fail goto*//*Label 8266*/ GIMT_Encode4(557191), |
| 176649 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 176650 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 176651 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 176652 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 176653 | GIM_Try, /*On fail goto*//*Label 8267*/ GIMT_Encode4(556046), // Rule ID 4975 // |
| 176654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176655 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176656 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176657 | // MIs[0] offset |
| 176658 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176659 | // MIs[0] auxiliary |
| 176660 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176661 | // MIs[0] Operand 7 |
| 176662 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176663 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176664 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176665 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact), |
| 176666 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176667 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176668 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176669 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176670 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176671 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176672 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176673 | GIR_RootConstrainSelectedInstOperands, |
| 176674 | // GIR_Coverage, 4975, |
| 176675 | GIR_EraseRootFromParent_Done, |
| 176676 | // Label 8267: @556046 |
| 176677 | GIM_Try, /*On fail goto*//*Label 8268*/ GIMT_Encode4(556118), // Rule ID 4979 // |
| 176678 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176679 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176680 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176681 | // MIs[0] offset |
| 176682 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176683 | // MIs[0] auxiliary |
| 176684 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176685 | // MIs[0] Operand 7 |
| 176686 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176687 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176688 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176689 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact), |
| 176690 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176691 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176692 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176693 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176694 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176695 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176696 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176697 | GIR_RootConstrainSelectedInstOperands, |
| 176698 | // GIR_Coverage, 4979, |
| 176699 | GIR_EraseRootFromParent_Done, |
| 176700 | // Label 8268: @556118 |
| 176701 | GIM_Try, /*On fail goto*//*Label 8269*/ GIMT_Encode4(556190), // Rule ID 4983 // |
| 176702 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176703 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176704 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176705 | // MIs[0] offset |
| 176706 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176707 | // MIs[0] auxiliary |
| 176708 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176709 | // MIs[0] Operand 7 |
| 176710 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176711 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176712 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15876:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176713 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFSET_exact), |
| 176714 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176715 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176716 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176717 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176718 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176719 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176720 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176721 | GIR_RootConstrainSelectedInstOperands, |
| 176722 | // GIR_Coverage, 4983, |
| 176723 | GIR_EraseRootFromParent_Done, |
| 176724 | // Label 8269: @556190 |
| 176725 | GIM_Try, /*On fail goto*//*Label 8270*/ GIMT_Encode4(556262), // Rule ID 4987 // |
| 176726 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176727 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176728 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176729 | // MIs[0] offset |
| 176730 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176731 | // MIs[0] auxiliary |
| 176732 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176733 | // MIs[0] Operand 7 |
| 176734 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176735 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176736 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176737 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact), |
| 176738 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176739 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176740 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176741 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176742 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176743 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176744 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176745 | GIR_RootConstrainSelectedInstOperands, |
| 176746 | // GIR_Coverage, 4987, |
| 176747 | GIR_EraseRootFromParent_Done, |
| 176748 | // Label 8270: @556262 |
| 176749 | GIM_Try, /*On fail goto*//*Label 8271*/ GIMT_Encode4(556332), // Rule ID 4976 // |
| 176750 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176751 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176752 | // MIs[0] offset |
| 176753 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176754 | // MIs[0] auxiliary |
| 176755 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176756 | // MIs[0] Operand 7 |
| 176757 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176759 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact), |
| 176761 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176762 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176763 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176765 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176767 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176769 | GIR_RootConstrainSelectedInstOperands, |
| 176770 | // GIR_Coverage, 4976, |
| 176771 | GIR_EraseRootFromParent_Done, |
| 176772 | // Label 8271: @556332 |
| 176773 | GIM_Try, /*On fail goto*//*Label 8272*/ GIMT_Encode4(556402), // Rule ID 4980 // |
| 176774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176775 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176776 | // MIs[0] offset |
| 176777 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176778 | // MIs[0] auxiliary |
| 176779 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176780 | // MIs[0] Operand 7 |
| 176781 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176783 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176784 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact), |
| 176785 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176786 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176787 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176788 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176789 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176790 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176791 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176792 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176793 | GIR_RootConstrainSelectedInstOperands, |
| 176794 | // GIR_Coverage, 4980, |
| 176795 | GIR_EraseRootFromParent_Done, |
| 176796 | // Label 8272: @556402 |
| 176797 | GIM_Try, /*On fail goto*//*Label 8273*/ GIMT_Encode4(556472), // Rule ID 4984 // |
| 176798 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176799 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176800 | // MIs[0] offset |
| 176801 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176802 | // MIs[0] auxiliary |
| 176803 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176804 | // MIs[0] Operand 7 |
| 176805 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176806 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176807 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176808 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_OFFEN_exact), |
| 176809 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176810 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176811 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176812 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176813 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176814 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176815 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176816 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176817 | GIR_RootConstrainSelectedInstOperands, |
| 176818 | // GIR_Coverage, 4984, |
| 176819 | GIR_EraseRootFromParent_Done, |
| 176820 | // Label 8273: @556472 |
| 176821 | GIM_Try, /*On fail goto*//*Label 8274*/ GIMT_Encode4(556542), // Rule ID 4988 // |
| 176822 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176823 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 176824 | // MIs[0] offset |
| 176825 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176826 | // MIs[0] auxiliary |
| 176827 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176828 | // MIs[0] Operand 7 |
| 176829 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 176830 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176831 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176832 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact), |
| 176833 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176834 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 176835 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176836 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176837 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176839 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176840 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176841 | GIR_RootConstrainSelectedInstOperands, |
| 176842 | // GIR_Coverage, 4988, |
| 176843 | GIR_EraseRootFromParent_Done, |
| 176844 | // Label 8274: @556542 |
| 176845 | GIM_Try, /*On fail goto*//*Label 8275*/ GIMT_Encode4(556604), // Rule ID 4977 // |
| 176846 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176847 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176848 | // MIs[0] offset |
| 176849 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176850 | // MIs[0] auxiliary |
| 176851 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176852 | // MIs[0] Operand 7 |
| 176853 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176854 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176855 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176856 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact), |
| 176857 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176858 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176859 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176860 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176861 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176863 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176864 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176865 | GIR_RootConstrainSelectedInstOperands, |
| 176866 | // GIR_Coverage, 4977, |
| 176867 | GIR_EraseRootFromParent_Done, |
| 176868 | // Label 8275: @556604 |
| 176869 | GIM_Try, /*On fail goto*//*Label 8276*/ GIMT_Encode4(556666), // Rule ID 4981 // |
| 176870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176871 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176872 | // MIs[0] offset |
| 176873 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176874 | // MIs[0] auxiliary |
| 176875 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176876 | // MIs[0] Operand 7 |
| 176877 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176879 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact), |
| 176881 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176882 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176883 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176884 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176885 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176886 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176887 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176888 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176889 | GIR_RootConstrainSelectedInstOperands, |
| 176890 | // GIR_Coverage, 4981, |
| 176891 | GIR_EraseRootFromParent_Done, |
| 176892 | // Label 8276: @556666 |
| 176893 | GIM_Try, /*On fail goto*//*Label 8277*/ GIMT_Encode4(556728), // Rule ID 4985 // |
| 176894 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176895 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176896 | // MIs[0] offset |
| 176897 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176898 | // MIs[0] auxiliary |
| 176899 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176900 | // MIs[0] Operand 7 |
| 176901 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176902 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176903 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176904 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_IDXEN_exact), |
| 176905 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176906 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176907 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176908 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176909 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176910 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176911 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176912 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176913 | GIR_RootConstrainSelectedInstOperands, |
| 176914 | // GIR_Coverage, 4985, |
| 176915 | GIR_EraseRootFromParent_Done, |
| 176916 | // Label 8277: @556728 |
| 176917 | GIM_Try, /*On fail goto*//*Label 8278*/ GIMT_Encode4(556790), // Rule ID 4989 // |
| 176918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 176920 | // MIs[0] offset |
| 176921 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176922 | // MIs[0] auxiliary |
| 176923 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176924 | // MIs[0] Operand 7 |
| 176925 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176926 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176927 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176928 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact), |
| 176929 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176930 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 176931 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176933 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176934 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176935 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176936 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176937 | GIR_RootConstrainSelectedInstOperands, |
| 176938 | // GIR_Coverage, 4989, |
| 176939 | GIR_EraseRootFromParent_Done, |
| 176940 | // Label 8278: @556790 |
| 176941 | GIM_Try, /*On fail goto*//*Label 8279*/ GIMT_Encode4(556890), // Rule ID 4978 // |
| 176942 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 176943 | // MIs[0] offset |
| 176944 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176945 | // MIs[0] auxiliary |
| 176946 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176947 | // MIs[0] Operand 7 |
| 176948 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176949 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176950 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176951 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176952 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176953 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176954 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176955 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176956 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176957 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176958 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176959 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176960 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact), |
| 176962 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176963 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176964 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176965 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176966 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 176967 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 176968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 176969 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 176970 | GIR_RootConstrainSelectedInstOperands, |
| 176971 | // GIR_Coverage, 4978, |
| 176972 | GIR_EraseRootFromParent_Done, |
| 176973 | // Label 8279: @556890 |
| 176974 | GIM_Try, /*On fail goto*//*Label 8280*/ GIMT_Encode4(556990), // Rule ID 4982 // |
| 176975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 176976 | // MIs[0] offset |
| 176977 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 176978 | // MIs[0] auxiliary |
| 176979 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 176980 | // MIs[0] Operand 7 |
| 176981 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 176982 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 176983 | // (SIbuffer_store_format_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 176984 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 176985 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 176986 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 176987 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 176988 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 176989 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 176990 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 176991 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 176992 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176993 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 176994 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact), |
| 176995 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 176996 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 176997 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 176998 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 176999 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177000 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177001 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177002 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177003 | GIR_RootConstrainSelectedInstOperands, |
| 177004 | // GIR_Coverage, 4982, |
| 177005 | GIR_EraseRootFromParent_Done, |
| 177006 | // Label 8280: @556990 |
| 177007 | GIM_Try, /*On fail goto*//*Label 8281*/ GIMT_Encode4(557090), // Rule ID 4986 // |
| 177008 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177009 | // MIs[0] offset |
| 177010 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177011 | // MIs[0] auxiliary |
| 177012 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177013 | // MIs[0] Operand 7 |
| 177014 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177016 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177017 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177018 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177019 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177020 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177021 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177022 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177023 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177024 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177025 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177026 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact), |
| 177028 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177029 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177030 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177032 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177033 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177034 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177035 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177036 | GIR_RootConstrainSelectedInstOperands, |
| 177037 | // GIR_Coverage, 4986, |
| 177038 | GIR_EraseRootFromParent_Done, |
| 177039 | // Label 8281: @557090 |
| 177040 | GIM_Try, /*On fail goto*//*Label 8282*/ GIMT_Encode4(557190), // Rule ID 4990 // |
| 177041 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177042 | // MIs[0] offset |
| 177043 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177044 | // MIs[0] auxiliary |
| 177045 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177046 | // MIs[0] Operand 7 |
| 177047 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177048 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177049 | // (SIbuffer_store_format_d16 v2i16:{ *:[v2i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177050 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177051 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177052 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177053 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177054 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177055 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177056 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177057 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177058 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177059 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact), |
| 177061 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177062 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177063 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177065 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177067 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177068 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177069 | GIR_RootConstrainSelectedInstOperands, |
| 177070 | // GIR_Coverage, 4990, |
| 177071 | GIR_EraseRootFromParent_Done, |
| 177072 | // Label 8282: @557190 |
| 177073 | GIM_Reject, |
| 177074 | // Label 8266: @557191 |
| 177075 | GIM_Reject, |
| 177076 | // Label 8223: @557192 |
| 177077 | GIM_Try, /*On fail goto*//*Label 8283*/ GIMT_Encode4(557514), |
| 177078 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 177079 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 177080 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 177081 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 177082 | GIM_Try, /*On fail goto*//*Label 8284*/ GIMT_Encode4(557281), // Rule ID 4939 // |
| 177083 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177084 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177086 | // MIs[0] offset |
| 177087 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177088 | // MIs[0] auxiliary |
| 177089 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177090 | // MIs[0] Operand 7 |
| 177091 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177092 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177093 | // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177094 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact), |
| 177095 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177096 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177097 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177098 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177099 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177100 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177102 | GIR_RootConstrainSelectedInstOperands, |
| 177103 | // GIR_Coverage, 4939, |
| 177104 | GIR_EraseRootFromParent_Done, |
| 177105 | // Label 8284: @557281 |
| 177106 | GIM_Try, /*On fail goto*//*Label 8285*/ GIMT_Encode4(557351), // Rule ID 4940 // |
| 177107 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177108 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177109 | // MIs[0] offset |
| 177110 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177111 | // MIs[0] auxiliary |
| 177112 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177113 | // MIs[0] Operand 7 |
| 177114 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177115 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177116 | // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177117 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact), |
| 177118 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177119 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177120 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177121 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177122 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177123 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177125 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177126 | GIR_RootConstrainSelectedInstOperands, |
| 177127 | // GIR_Coverage, 4940, |
| 177128 | GIR_EraseRootFromParent_Done, |
| 177129 | // Label 8285: @557351 |
| 177130 | GIM_Try, /*On fail goto*//*Label 8286*/ GIMT_Encode4(557413), // Rule ID 4941 // |
| 177131 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177132 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177133 | // MIs[0] offset |
| 177134 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177135 | // MIs[0] auxiliary |
| 177136 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177137 | // MIs[0] Operand 7 |
| 177138 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177139 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177140 | // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177141 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact), |
| 177142 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177143 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177144 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177146 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177149 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177150 | GIR_RootConstrainSelectedInstOperands, |
| 177151 | // GIR_Coverage, 4941, |
| 177152 | GIR_EraseRootFromParent_Done, |
| 177153 | // Label 8286: @557413 |
| 177154 | GIM_Try, /*On fail goto*//*Label 8287*/ GIMT_Encode4(557513), // Rule ID 4942 // |
| 177155 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177156 | // MIs[0] offset |
| 177157 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177158 | // MIs[0] auxiliary |
| 177159 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177160 | // MIs[0] Operand 7 |
| 177161 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177162 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177163 | // (SIbuffer_store_format_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177164 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177165 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177166 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177167 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177168 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177169 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177170 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177171 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177173 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact), |
| 177175 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177176 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177177 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177178 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177179 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177183 | GIR_RootConstrainSelectedInstOperands, |
| 177184 | // GIR_Coverage, 4942, |
| 177185 | GIR_EraseRootFromParent_Done, |
| 177186 | // Label 8287: @557513 |
| 177187 | GIM_Reject, |
| 177188 | // Label 8283: @557514 |
| 177189 | GIM_Reject, |
| 177190 | // Label 8224: @557515 |
| 177191 | GIM_Try, /*On fail goto*//*Label 8288*/ GIMT_Encode4(557837), |
| 177192 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 177193 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 177194 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 177195 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 177196 | GIM_Try, /*On fail goto*//*Label 8289*/ GIMT_Encode4(557604), // Rule ID 4943 // |
| 177197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177198 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177199 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177200 | // MIs[0] offset |
| 177201 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177202 | // MIs[0] auxiliary |
| 177203 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177204 | // MIs[0] Operand 7 |
| 177205 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177206 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177207 | // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact), |
| 177209 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177210 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177211 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177212 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177213 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177214 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177215 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177216 | GIR_RootConstrainSelectedInstOperands, |
| 177217 | // GIR_Coverage, 4943, |
| 177218 | GIR_EraseRootFromParent_Done, |
| 177219 | // Label 8289: @557604 |
| 177220 | GIM_Try, /*On fail goto*//*Label 8290*/ GIMT_Encode4(557674), // Rule ID 4944 // |
| 177221 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177222 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177223 | // MIs[0] offset |
| 177224 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177225 | // MIs[0] auxiliary |
| 177226 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177227 | // MIs[0] Operand 7 |
| 177228 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177229 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177230 | // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177231 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact), |
| 177232 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177233 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177234 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177235 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177236 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177237 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177238 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177239 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177240 | GIR_RootConstrainSelectedInstOperands, |
| 177241 | // GIR_Coverage, 4944, |
| 177242 | GIR_EraseRootFromParent_Done, |
| 177243 | // Label 8290: @557674 |
| 177244 | GIM_Try, /*On fail goto*//*Label 8291*/ GIMT_Encode4(557736), // Rule ID 4945 // |
| 177245 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177246 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177247 | // MIs[0] offset |
| 177248 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177249 | // MIs[0] auxiliary |
| 177250 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177251 | // MIs[0] Operand 7 |
| 177252 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177253 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177254 | // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact), |
| 177256 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177257 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177258 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177260 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177261 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177262 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177263 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177264 | GIR_RootConstrainSelectedInstOperands, |
| 177265 | // GIR_Coverage, 4945, |
| 177266 | GIR_EraseRootFromParent_Done, |
| 177267 | // Label 8291: @557736 |
| 177268 | GIM_Try, /*On fail goto*//*Label 8292*/ GIMT_Encode4(557836), // Rule ID 4946 // |
| 177269 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177270 | // MIs[0] offset |
| 177271 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177272 | // MIs[0] auxiliary |
| 177273 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177274 | // MIs[0] Operand 7 |
| 177275 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177276 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177277 | // (SIbuffer_store_format_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177278 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177281 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177282 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177283 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177284 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177285 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177286 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177287 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177288 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact), |
| 177289 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177290 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177291 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177292 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177293 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177294 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177295 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177296 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177297 | GIR_RootConstrainSelectedInstOperands, |
| 177298 | // GIR_Coverage, 4946, |
| 177299 | GIR_EraseRootFromParent_Done, |
| 177300 | // Label 8292: @557836 |
| 177301 | GIM_Reject, |
| 177302 | // Label 8288: @557837 |
| 177303 | GIM_Reject, |
| 177304 | // Label 8225: @557838 |
| 177305 | GIM_Try, /*On fail goto*//*Label 8293*/ GIMT_Encode4(559072), |
| 177306 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 177307 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 177308 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 177309 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 177310 | GIM_Try, /*On fail goto*//*Label 8294*/ GIMT_Encode4(557927), // Rule ID 5007 // |
| 177311 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177312 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177313 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177314 | // MIs[0] offset |
| 177315 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177316 | // MIs[0] auxiliary |
| 177317 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177318 | // MIs[0] Operand 7 |
| 177319 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177320 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177321 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177322 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact), |
| 177323 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177324 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177325 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177326 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177327 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177328 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177329 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177330 | GIR_RootConstrainSelectedInstOperands, |
| 177331 | // GIR_Coverage, 5007, |
| 177332 | GIR_EraseRootFromParent_Done, |
| 177333 | // Label 8294: @557927 |
| 177334 | GIM_Try, /*On fail goto*//*Label 8295*/ GIMT_Encode4(557999), // Rule ID 5011 // |
| 177335 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177336 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177337 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177338 | // MIs[0] offset |
| 177339 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177340 | // MIs[0] auxiliary |
| 177341 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177342 | // MIs[0] Operand 7 |
| 177343 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177344 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177345 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177346 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact), |
| 177347 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177348 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177349 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177350 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177351 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177354 | GIR_RootConstrainSelectedInstOperands, |
| 177355 | // GIR_Coverage, 5011, |
| 177356 | GIR_EraseRootFromParent_Done, |
| 177357 | // Label 8295: @557999 |
| 177358 | GIM_Try, /*On fail goto*//*Label 8296*/ GIMT_Encode4(558071), // Rule ID 5015 // |
| 177359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177360 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177362 | // MIs[0] offset |
| 177363 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177364 | // MIs[0] auxiliary |
| 177365 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177366 | // MIs[0] Operand 7 |
| 177367 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177369 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15875:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact), |
| 177371 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177372 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177373 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177374 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177375 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177377 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177378 | GIR_RootConstrainSelectedInstOperands, |
| 177379 | // GIR_Coverage, 5015, |
| 177380 | GIR_EraseRootFromParent_Done, |
| 177381 | // Label 8296: @558071 |
| 177382 | GIM_Try, /*On fail goto*//*Label 8297*/ GIMT_Encode4(558143), // Rule ID 5019 // |
| 177383 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177384 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177385 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177386 | // MIs[0] offset |
| 177387 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177388 | // MIs[0] auxiliary |
| 177389 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177390 | // MIs[0] Operand 7 |
| 177391 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177392 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177393 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4i16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177394 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact), |
| 177395 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177396 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177397 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177398 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177399 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177400 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177401 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177402 | GIR_RootConstrainSelectedInstOperands, |
| 177403 | // GIR_Coverage, 5019, |
| 177404 | GIR_EraseRootFromParent_Done, |
| 177405 | // Label 8297: @558143 |
| 177406 | GIM_Try, /*On fail goto*//*Label 8298*/ GIMT_Encode4(558213), // Rule ID 5008 // |
| 177407 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177408 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177409 | // MIs[0] offset |
| 177410 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177411 | // MIs[0] auxiliary |
| 177412 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177413 | // MIs[0] Operand 7 |
| 177414 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177415 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177416 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177417 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact), |
| 177418 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177419 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177420 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177421 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177422 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177423 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177424 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177425 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177426 | GIR_RootConstrainSelectedInstOperands, |
| 177427 | // GIR_Coverage, 5008, |
| 177428 | GIR_EraseRootFromParent_Done, |
| 177429 | // Label 8298: @558213 |
| 177430 | GIM_Try, /*On fail goto*//*Label 8299*/ GIMT_Encode4(558283), // Rule ID 5012 // |
| 177431 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177432 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177433 | // MIs[0] offset |
| 177434 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177435 | // MIs[0] auxiliary |
| 177436 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177437 | // MIs[0] Operand 7 |
| 177438 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177440 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact), |
| 177442 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177443 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177444 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177446 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177447 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177448 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177449 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177450 | GIR_RootConstrainSelectedInstOperands, |
| 177451 | // GIR_Coverage, 5012, |
| 177452 | GIR_EraseRootFromParent_Done, |
| 177453 | // Label 8299: @558283 |
| 177454 | GIM_Try, /*On fail goto*//*Label 8300*/ GIMT_Encode4(558353), // Rule ID 5016 // |
| 177455 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177456 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177457 | // MIs[0] offset |
| 177458 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177459 | // MIs[0] auxiliary |
| 177460 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177461 | // MIs[0] Operand 7 |
| 177462 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177463 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177464 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177465 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact), |
| 177466 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177467 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177468 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177469 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177470 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177471 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177472 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177474 | GIR_RootConstrainSelectedInstOperands, |
| 177475 | // GIR_Coverage, 5016, |
| 177476 | GIR_EraseRootFromParent_Done, |
| 177477 | // Label 8300: @558353 |
| 177478 | GIM_Try, /*On fail goto*//*Label 8301*/ GIMT_Encode4(558423), // Rule ID 5020 // |
| 177479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177480 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177481 | // MIs[0] offset |
| 177482 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177483 | // MIs[0] auxiliary |
| 177484 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177485 | // MIs[0] Operand 7 |
| 177486 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177488 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact), |
| 177490 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177491 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177492 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177494 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177495 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177496 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177497 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177498 | GIR_RootConstrainSelectedInstOperands, |
| 177499 | // GIR_Coverage, 5020, |
| 177500 | GIR_EraseRootFromParent_Done, |
| 177501 | // Label 8301: @558423 |
| 177502 | GIM_Try, /*On fail goto*//*Label 8302*/ GIMT_Encode4(558485), // Rule ID 5009 // |
| 177503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177504 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177505 | // MIs[0] offset |
| 177506 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177507 | // MIs[0] auxiliary |
| 177508 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177509 | // MIs[0] Operand 7 |
| 177510 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177512 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact), |
| 177514 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177515 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177516 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177518 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177519 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177520 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177522 | GIR_RootConstrainSelectedInstOperands, |
| 177523 | // GIR_Coverage, 5009, |
| 177524 | GIR_EraseRootFromParent_Done, |
| 177525 | // Label 8302: @558485 |
| 177526 | GIM_Try, /*On fail goto*//*Label 8303*/ GIMT_Encode4(558547), // Rule ID 5013 // |
| 177527 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177528 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177529 | // MIs[0] offset |
| 177530 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177531 | // MIs[0] auxiliary |
| 177532 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177533 | // MIs[0] Operand 7 |
| 177534 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177536 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177537 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact), |
| 177538 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177539 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177540 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177542 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177543 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177546 | GIR_RootConstrainSelectedInstOperands, |
| 177547 | // GIR_Coverage, 5013, |
| 177548 | GIR_EraseRootFromParent_Done, |
| 177549 | // Label 8303: @558547 |
| 177550 | GIM_Try, /*On fail goto*//*Label 8304*/ GIMT_Encode4(558609), // Rule ID 5017 // |
| 177551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177552 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177553 | // MIs[0] offset |
| 177554 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177555 | // MIs[0] auxiliary |
| 177556 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177557 | // MIs[0] Operand 7 |
| 177558 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177559 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177560 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177561 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact), |
| 177562 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177563 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177564 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177565 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177566 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177568 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177569 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177570 | GIR_RootConstrainSelectedInstOperands, |
| 177571 | // GIR_Coverage, 5017, |
| 177572 | GIR_EraseRootFromParent_Done, |
| 177573 | // Label 8304: @558609 |
| 177574 | GIM_Try, /*On fail goto*//*Label 8305*/ GIMT_Encode4(558671), // Rule ID 5021 // |
| 177575 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177576 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177577 | // MIs[0] offset |
| 177578 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177579 | // MIs[0] auxiliary |
| 177580 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177581 | // MIs[0] Operand 7 |
| 177582 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177584 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177585 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact), |
| 177586 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177587 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177588 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177589 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177590 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177591 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177592 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177593 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177594 | GIR_RootConstrainSelectedInstOperands, |
| 177595 | // GIR_Coverage, 5021, |
| 177596 | GIR_EraseRootFromParent_Done, |
| 177597 | // Label 8305: @558671 |
| 177598 | GIM_Try, /*On fail goto*//*Label 8306*/ GIMT_Encode4(558771), // Rule ID 5010 // |
| 177599 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177600 | // MIs[0] offset |
| 177601 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177602 | // MIs[0] auxiliary |
| 177603 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177604 | // MIs[0] Operand 7 |
| 177605 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177607 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177611 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177612 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177613 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177614 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177616 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177617 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact), |
| 177619 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177621 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177623 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177624 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177625 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177626 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177627 | GIR_RootConstrainSelectedInstOperands, |
| 177628 | // GIR_Coverage, 5010, |
| 177629 | GIR_EraseRootFromParent_Done, |
| 177630 | // Label 8306: @558771 |
| 177631 | GIM_Try, /*On fail goto*//*Label 8307*/ GIMT_Encode4(558871), // Rule ID 5014 // |
| 177632 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177633 | // MIs[0] offset |
| 177634 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177635 | // MIs[0] auxiliary |
| 177636 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177637 | // MIs[0] Operand 7 |
| 177638 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177639 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177640 | // (SIbuffer_store_format_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177641 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177642 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177643 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177644 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177645 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177646 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177647 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177648 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177649 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177650 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact), |
| 177652 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177653 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177654 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177655 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177656 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177658 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177659 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177660 | GIR_RootConstrainSelectedInstOperands, |
| 177661 | // GIR_Coverage, 5014, |
| 177662 | GIR_EraseRootFromParent_Done, |
| 177663 | // Label 8307: @558871 |
| 177664 | GIM_Try, /*On fail goto*//*Label 8308*/ GIMT_Encode4(558971), // Rule ID 5018 // |
| 177665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 177666 | // MIs[0] offset |
| 177667 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177668 | // MIs[0] auxiliary |
| 177669 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177670 | // MIs[0] Operand 7 |
| 177671 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177672 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177673 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177674 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177675 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177676 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177677 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177678 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177679 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177680 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177681 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177682 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177683 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177684 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact), |
| 177685 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177686 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177687 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177688 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177689 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177690 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177691 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177692 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177693 | GIR_RootConstrainSelectedInstOperands, |
| 177694 | // GIR_Coverage, 5018, |
| 177695 | GIR_EraseRootFromParent_Done, |
| 177696 | // Label 8308: @558971 |
| 177697 | GIM_Try, /*On fail goto*//*Label 8309*/ GIMT_Encode4(559071), // Rule ID 5022 // |
| 177698 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 177699 | // MIs[0] offset |
| 177700 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177701 | // MIs[0] auxiliary |
| 177702 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177703 | // MIs[0] Operand 7 |
| 177704 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177706 | // (SIbuffer_store_format_d16 v4i16:{ *:[v4i16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4i16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177707 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177708 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177709 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177710 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177711 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177712 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177713 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177714 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177715 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177716 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177717 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact), |
| 177718 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177719 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177720 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177721 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177722 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177723 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177726 | GIR_RootConstrainSelectedInstOperands, |
| 177727 | // GIR_Coverage, 5022, |
| 177728 | GIR_EraseRootFromParent_Done, |
| 177729 | // Label 8309: @559071 |
| 177730 | GIM_Reject, |
| 177731 | // Label 8293: @559072 |
| 177732 | GIM_Reject, |
| 177733 | // Label 8226: @559073 |
| 177734 | GIM_Try, /*On fail goto*//*Label 8310*/ GIMT_Encode4(559395), |
| 177735 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 177736 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 177737 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 177738 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 177739 | GIM_Try, /*On fail goto*//*Label 8311*/ GIMT_Encode4(559162), // Rule ID 4947 // |
| 177740 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177741 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177742 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177743 | // MIs[0] offset |
| 177744 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177745 | // MIs[0] auxiliary |
| 177746 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177747 | // MIs[0] Operand 7 |
| 177748 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177749 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177750 | // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177751 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact), |
| 177752 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177753 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177755 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177756 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177757 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177758 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177759 | GIR_RootConstrainSelectedInstOperands, |
| 177760 | // GIR_Coverage, 4947, |
| 177761 | GIR_EraseRootFromParent_Done, |
| 177762 | // Label 8311: @559162 |
| 177763 | GIM_Try, /*On fail goto*//*Label 8312*/ GIMT_Encode4(559232), // Rule ID 4948 // |
| 177764 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177765 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177766 | // MIs[0] offset |
| 177767 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177768 | // MIs[0] auxiliary |
| 177769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177770 | // MIs[0] Operand 7 |
| 177771 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177773 | // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact), |
| 177775 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177776 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177777 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177779 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177780 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177781 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177782 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177783 | GIR_RootConstrainSelectedInstOperands, |
| 177784 | // GIR_Coverage, 4948, |
| 177785 | GIR_EraseRootFromParent_Done, |
| 177786 | // Label 8312: @559232 |
| 177787 | GIM_Try, /*On fail goto*//*Label 8313*/ GIMT_Encode4(559294), // Rule ID 4949 // |
| 177788 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177789 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177790 | // MIs[0] offset |
| 177791 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177792 | // MIs[0] auxiliary |
| 177793 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177794 | // MIs[0] Operand 7 |
| 177795 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177796 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177797 | // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177798 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact), |
| 177799 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177800 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177801 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177802 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177803 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177804 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177805 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177806 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177807 | GIR_RootConstrainSelectedInstOperands, |
| 177808 | // GIR_Coverage, 4949, |
| 177809 | GIR_EraseRootFromParent_Done, |
| 177810 | // Label 8313: @559294 |
| 177811 | GIM_Try, /*On fail goto*//*Label 8314*/ GIMT_Encode4(559394), // Rule ID 4950 // |
| 177812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 177813 | // MIs[0] offset |
| 177814 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177815 | // MIs[0] auxiliary |
| 177816 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177817 | // MIs[0] Operand 7 |
| 177818 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177819 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177820 | // (SIbuffer_store_format_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177821 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177822 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 177823 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 177824 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 177825 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 177826 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 177827 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 177828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 177829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177830 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 177831 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact), |
| 177832 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177833 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 177834 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177835 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177836 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177837 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177840 | GIR_RootConstrainSelectedInstOperands, |
| 177841 | // GIR_Coverage, 4950, |
| 177842 | GIR_EraseRootFromParent_Done, |
| 177843 | // Label 8314: @559394 |
| 177844 | GIM_Reject, |
| 177845 | // Label 8310: @559395 |
| 177846 | GIM_Reject, |
| 177847 | // Label 8227: @559396 |
| 177848 | GIM_Reject, |
| 177849 | // Label 142: @559397 |
| 177850 | GIM_Try, /*On fail goto*//*Label 8315*/ GIMT_Encode4(559998), |
| 177851 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 177852 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 177853 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 177854 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 177855 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 177856 | GIM_Try, /*On fail goto*//*Label 8316*/ GIMT_Encode4(559689), |
| 177857 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 177858 | GIM_Try, /*On fail goto*//*Label 8317*/ GIMT_Encode4(559494), // Rule ID 5239 // |
| 177859 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 177860 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177861 | // MIs[0] offset |
| 177862 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177863 | // MIs[0] auxiliary |
| 177864 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177865 | // MIs[0] Operand 7 |
| 177866 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177867 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177868 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_SHORT_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177869 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFSET_exact), |
| 177870 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177871 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177872 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177873 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177874 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177875 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177876 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177877 | GIR_RootConstrainSelectedInstOperands, |
| 177878 | // GIR_Coverage, 5239, |
| 177879 | GIR_EraseRootFromParent_Done, |
| 177880 | // Label 8317: @559494 |
| 177881 | GIM_Try, /*On fail goto*//*Label 8318*/ GIMT_Encode4(559559), // Rule ID 5243 // |
| 177882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177883 | // MIs[0] offset |
| 177884 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177885 | // MIs[0] auxiliary |
| 177886 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177887 | // MIs[0] Operand 7 |
| 177888 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177889 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177890 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_SHORT_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177891 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFSET_exact), |
| 177892 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177893 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177894 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177895 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177896 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177897 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177898 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177899 | GIR_RootConstrainSelectedInstOperands, |
| 177900 | // GIR_Coverage, 5243, |
| 177901 | GIR_EraseRootFromParent_Done, |
| 177902 | // Label 8318: @559559 |
| 177903 | GIM_Try, /*On fail goto*//*Label 8319*/ GIMT_Encode4(559625), // Rule ID 5240 // |
| 177904 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 177905 | // MIs[0] offset |
| 177906 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177907 | // MIs[0] auxiliary |
| 177908 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177909 | // MIs[0] Operand 7 |
| 177910 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177911 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177912 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_SHORT_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177913 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_OFFEN_exact), |
| 177914 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177915 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177916 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177917 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177918 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177919 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177920 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177921 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177922 | GIR_RootConstrainSelectedInstOperands, |
| 177923 | // GIR_Coverage, 5240, |
| 177924 | GIR_EraseRootFromParent_Done, |
| 177925 | // Label 8319: @559625 |
| 177926 | GIM_Try, /*On fail goto*//*Label 8320*/ GIMT_Encode4(559688), // Rule ID 5244 // |
| 177927 | // MIs[0] offset |
| 177928 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177929 | // MIs[0] auxiliary |
| 177930 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177931 | // MIs[0] Operand 7 |
| 177932 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/7, GIMT_Encode8(0), |
| 177933 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177934 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177935 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_OFFEN_exact), |
| 177936 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177937 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 177938 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177939 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177940 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177942 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177944 | GIR_RootConstrainSelectedInstOperands, |
| 177945 | // GIR_Coverage, 5244, |
| 177946 | GIR_EraseRootFromParent_Done, |
| 177947 | // Label 8320: @559688 |
| 177948 | GIM_Reject, |
| 177949 | // Label 8316: @559689 |
| 177950 | GIM_Try, /*On fail goto*//*Label 8321*/ GIMT_Encode4(559803), |
| 177951 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 177952 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177953 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177954 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177955 | GIM_Try, /*On fail goto*//*Label 8322*/ GIMT_Encode4(559756), // Rule ID 5241 // |
| 177956 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 177957 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177958 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_SHORT_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177959 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_IDXEN_exact), |
| 177960 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177961 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177962 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177963 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177964 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177968 | GIR_RootConstrainSelectedInstOperands, |
| 177969 | // GIR_Coverage, 5241, |
| 177970 | GIR_EraseRootFromParent_Done, |
| 177971 | // Label 8322: @559756 |
| 177972 | GIM_Try, /*On fail goto*//*Label 8323*/ GIMT_Encode4(559802), // Rule ID 5245 // |
| 177973 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177974 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_SHORT_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177975 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_IDXEN_exact), |
| 177976 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 177977 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 177978 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 177979 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 177980 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 177981 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 177982 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 177983 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 177984 | GIR_RootConstrainSelectedInstOperands, |
| 177985 | // GIR_Coverage, 5245, |
| 177986 | GIR_EraseRootFromParent_Done, |
| 177987 | // Label 8323: @559802 |
| 177988 | GIM_Reject, |
| 177989 | // Label 8321: @559803 |
| 177990 | GIM_Try, /*On fail goto*//*Label 8324*/ GIMT_Encode4(559997), |
| 177991 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 177992 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 177993 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 177994 | GIM_Try, /*On fail goto*//*Label 8325*/ GIMT_Encode4(559908), // Rule ID 5242 // |
| 177995 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 177996 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 177997 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_SHORT_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 177998 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 177999 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 178000 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178001 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 178002 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 178003 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 178004 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 178005 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 178006 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178007 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_BOTHEN_exact), |
| 178009 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 178010 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 178011 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 178012 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178013 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 178014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 178015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 178016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178017 | GIR_RootConstrainSelectedInstOperands, |
| 178018 | // GIR_Coverage, 5242, |
| 178019 | GIR_EraseRootFromParent_Done, |
| 178020 | // Label 8325: @559908 |
| 178021 | GIM_Try, /*On fail goto*//*Label 8326*/ GIMT_Encode4(559996), // Rule ID 5246 // |
| 178022 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 178023 | // (SIbuffer_store_short i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 178024 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 178025 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 178026 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178027 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 178028 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 178029 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 178030 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 178031 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 178032 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178033 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::BUFFER_STORE_SHORT_VBUFFER_BOTHEN_exact), |
| 178035 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 178036 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 178037 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 178038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178039 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 178040 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 178041 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 178042 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178043 | GIR_RootConstrainSelectedInstOperands, |
| 178044 | // GIR_Coverage, 5246, |
| 178045 | GIR_EraseRootFromParent_Done, |
| 178046 | // Label 8326: @559996 |
| 178047 | GIM_Reject, |
| 178048 | // Label 8324: @559997 |
| 178049 | GIM_Reject, |
| 178050 | // Label 8315: @559998 |
| 178051 | GIM_Reject, |
| 178052 | // Label 143: @559999 |
| 178053 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(12), /*)*//*default:*//*Label 8331*/ GIMT_Encode4(560937), |
| 178054 | /*GILLT_s16*//*Label 8327*/ GIMT_Encode4(560026), |
| 178055 | /*GILLT_s32*//*Label 8328*/ GIMT_Encode4(560195), |
| 178056 | /*GILLT_s64*//*Label 8329*/ GIMT_Encode4(560248), |
| 178057 | /*GILLT_v2s16*//*Label 8330*/ GIMT_Encode4(560358), |
| 178058 | // Label 8327: @560026 |
| 178059 | GIM_Try, /*On fail goto*//*Label 8332*/ GIMT_Encode4(560194), |
| 178060 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 178061 | GIM_Try, /*On fail goto*//*Label 8333*/ GIMT_Encode4(560086), // Rule ID 7004 // |
| 178062 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_NotHasTrue16BitInsts), |
| 178063 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178065 | // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_e64), |
| 178067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178068 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178069 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178071 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178072 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178073 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178074 | GIR_RootConstrainSelectedInstOperands, |
| 178075 | // GIR_Coverage, 7004, |
| 178076 | GIR_EraseRootFromParent_Done, |
| 178077 | // Label 8333: @560086 |
| 178078 | GIM_Try, /*On fail goto*//*Label 8334*/ GIMT_Encode4(560141), // Rule ID 7005 // |
| 178079 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseRealTrue16Insts), |
| 178080 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_16RegClassID), |
| 178081 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178082 | // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_F16_t16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178083 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_t16_e64), |
| 178084 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178086 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178087 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178088 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178089 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178090 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178091 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178092 | GIR_RootConstrainSelectedInstOperands, |
| 178093 | // GIR_Coverage, 7005, |
| 178094 | GIR_EraseRootFromParent_Done, |
| 178095 | // Label 8334: @560141 |
| 178096 | GIM_Try, /*On fail goto*//*Label 8335*/ GIMT_Encode4(560193), // Rule ID 7006 // |
| 178097 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_UseFakeTrue16Insts), |
| 178098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178099 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178100 | // (AMDGPUclamp:{ *:[f16] } (VOP3Mods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_F16_fake16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178101 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F16_fake16_e64), |
| 178102 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178103 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178104 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178105 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178107 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178108 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178109 | GIR_RootConstrainSelectedInstOperands, |
| 178110 | // GIR_Coverage, 7006, |
| 178111 | GIR_EraseRootFromParent_Done, |
| 178112 | // Label 8335: @560193 |
| 178113 | GIM_Reject, |
| 178114 | // Label 8332: @560194 |
| 178115 | GIM_Reject, |
| 178116 | // Label 8328: @560195 |
| 178117 | GIM_Try, /*On fail goto*//*Label 8336*/ GIMT_Encode4(560247), // Rule ID 7001 // |
| 178118 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178119 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178121 | // (AMDGPUclamp:{ *:[f32] } (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F32_e64), |
| 178123 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178124 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178125 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178127 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178128 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178129 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178130 | GIR_RootConstrainSelectedInstOperands, |
| 178131 | // GIR_Coverage, 7001, |
| 178132 | GIR_EraseRootFromParent_Done, |
| 178133 | // Label 8336: @560247 |
| 178134 | GIM_Reject, |
| 178135 | // Label 8329: @560248 |
| 178136 | GIM_Try, /*On fail goto*//*Label 8337*/ GIMT_Encode4(560357), |
| 178137 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s64, |
| 178138 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 178139 | GIM_Try, /*On fail goto*//*Label 8338*/ GIMT_Encode4(560308), // Rule ID 7002 // |
| 178140 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX12Plus), |
| 178141 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178142 | // (AMDGPUclamp:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178143 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_F64_e64), |
| 178144 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178145 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178146 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178147 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178149 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178150 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178151 | GIR_RootConstrainSelectedInstOperands, |
| 178152 | // GIR_Coverage, 7002, |
| 178153 | GIR_EraseRootFromParent_Done, |
| 178154 | // Label 8338: @560308 |
| 178155 | GIM_Try, /*On fail goto*//*Label 8339*/ GIMT_Encode4(560356), // Rule ID 7003 // |
| 178156 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 178157 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods), |
| 178158 | // (AMDGPUclamp:{ *:[f64] } (VOP3Mods:{ *:[f64] } f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_MAX_NUM_F64_e64:{ *:[f64] } i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, i32:{ *:[i32] }:$src0_modifiers, f64:{ *:[f64] }:$src0, 1:{ *:[i1] }, 0:{ *:[i32] }) |
| 178159 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_NUM_F64_e64), |
| 178160 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178161 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178162 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178164 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178165 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178166 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178167 | GIR_RootConstrainSelectedInstOperands, |
| 178168 | // GIR_Coverage, 7003, |
| 178169 | GIR_EraseRootFromParent_Done, |
| 178170 | // Label 8339: @560356 |
| 178171 | GIM_Reject, |
| 178172 | // Label 8337: @560357 |
| 178173 | GIM_Reject, |
| 178174 | // Label 8330: @560358 |
| 178175 | GIM_Try, /*On fail goto*//*Label 8340*/ GIMT_Encode4(560936), |
| 178176 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v2s16, |
| 178177 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178178 | GIM_Try, /*On fail goto*//*Label 8341*/ GIMT_Encode4(560624), // Rule ID 2318 // |
| 178179 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasFmaMixInsts), |
| 178180 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 178181 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), |
| 178182 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 178183 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 178184 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 178185 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 178186 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 178187 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 178188 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 178189 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMA), |
| 178190 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 178191 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 178192 | GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32, |
| 178193 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4] |
| 178194 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 178195 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 178196 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] |
| 178197 | GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_FMA), |
| 178198 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32, |
| 178199 | GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32, |
| 178200 | GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32, |
| 178201 | GIM_CheckIsSafeToFold, /*NumInsns*/5, |
| 178202 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178203 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178204 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178205 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/1, /*Renderer*/GIMT_Encode2(3), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178206 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/2, /*Renderer*/GIMT_Encode2(4), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178207 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/3, /*Renderer*/GIMT_Encode2(5), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178208 | // (AMDGPUclamp:{ *:[v2f16] } (build_vector:{ *:[v2f16] } (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src0, i32:{ *:[i32] }:$lo_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src1, i32:{ *:[i32] }:$lo_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src2, i32:{ *:[i32] }:$lo_src2_modifiers))), (fpround:{ *:[f16] } (fma:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src0, i32:{ *:[i32] }:$hi_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src1, i32:{ *:[i32] }:$hi_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src2, i32:{ *:[i32] }:$hi_src2_modifiers))))) => (V_FMA_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$hi_src0_modifiers, ?:{ *:[f16] }:$hi_src0, ?:{ *:[i32] }:$hi_src1_modifiers, ?:{ *:[f16] }:$hi_src1, ?:{ *:[i32] }:$hi_src2_modifiers, ?:{ *:[f16] }:$hi_src2, 1:{ *:[i1] }, (V_FMA_MIXLO_F16:{ *:[i16] } ?:{ *:[i32] }:$lo_src0_modifiers, ?:{ *:[f16] }:$lo_src0, ?:{ *:[i32] }:$lo_src1_modifiers, ?:{ *:[f16] }:$lo_src1, ?:{ *:[i32] }:$lo_src2_modifiers, ?:{ *:[f16] }:$lo_src2, 1:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))) |
| 178209 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 178210 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 178211 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 178212 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178213 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 178214 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXLO_F16), |
| 178215 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178216 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // lo_src0_modifiers |
| 178217 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // lo_src0 |
| 178218 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // lo_src1_modifiers |
| 178219 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // lo_src1 |
| 178220 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // lo_src2_modifiers |
| 178221 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // lo_src2 |
| 178222 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 178223 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 178224 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 178225 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 178226 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 178227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FMA_MIXHI_F16), |
| 178228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178229 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/1, // hi_src0_modifiers |
| 178230 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/0, // hi_src0 |
| 178231 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/1, // hi_src1_modifiers |
| 178232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/0, // hi_src1 |
| 178233 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/1, // hi_src2_modifiers |
| 178234 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/0, // hi_src2 |
| 178235 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178236 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 178237 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178238 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178239 | GIR_RootConstrainSelectedInstOperands, |
| 178240 | // GIR_Coverage, 2318, |
| 178241 | GIR_EraseRootFromParent_Done, |
| 178242 | // Label 8341: @560624 |
| 178243 | GIM_Try, /*On fail goto*//*Label 8342*/ GIMT_Encode4(560878), // Rule ID 2309 // |
| 178244 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasMadMixInsts_NoFP32Denormals), |
| 178245 | GIM_RecordInsn, /*DefineMI*/1, /*MI*/0, /*OpIdx*/1, // MIs[1] |
| 178246 | GIM_CheckOpcode, /*MI*/1, GIMT_Encode2(TargetOpcode::G_BUILD_VECTOR), |
| 178247 | GIM_CheckNumOperands, /*MI*/1, /*Expected*/3, |
| 178248 | GIM_CheckType, /*MI*/1, /*Op*/1, /*Type*/GILLT_s16, |
| 178249 | GIM_CheckType, /*MI*/1, /*Op*/2, /*Type*/GILLT_s16, |
| 178250 | GIM_RecordInsn, /*DefineMI*/2, /*MI*/1, /*OpIdx*/1, // MIs[2] |
| 178251 | GIM_CheckOpcode, /*MI*/2, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 178252 | GIM_CheckType, /*MI*/2, /*Op*/1, /*Type*/GILLT_s32, |
| 178253 | GIM_RecordInsn, /*DefineMI*/3, /*MI*/2, /*OpIdx*/1, // MIs[3] |
| 178254 | GIM_CheckOpcode, /*MI*/3, GIMT_Encode2(TargetOpcode::G_FMAD), |
| 178255 | GIM_CheckType, /*MI*/3, /*Op*/1, /*Type*/GILLT_s32, |
| 178256 | GIM_CheckType, /*MI*/3, /*Op*/2, /*Type*/GILLT_s32, |
| 178257 | GIM_CheckType, /*MI*/3, /*Op*/3, /*Type*/GILLT_s32, |
| 178258 | GIM_RecordInsn, /*DefineMI*/4, /*MI*/1, /*OpIdx*/2, // MIs[4] |
| 178259 | GIM_CheckOpcode, /*MI*/4, GIMT_Encode2(TargetOpcode::G_FPTRUNC), |
| 178260 | GIM_CheckType, /*MI*/4, /*Op*/1, /*Type*/GILLT_s32, |
| 178261 | GIM_RecordInsn, /*DefineMI*/5, /*MI*/4, /*OpIdx*/1, // MIs[5] |
| 178262 | GIM_CheckOpcode, /*MI*/5, GIMT_Encode2(TargetOpcode::G_FMAD), |
| 178263 | GIM_CheckType, /*MI*/5, /*Op*/1, /*Type*/GILLT_s32, |
| 178264 | GIM_CheckType, /*MI*/5, /*Op*/2, /*Type*/GILLT_s32, |
| 178265 | GIM_CheckType, /*MI*/5, /*Op*/3, /*Type*/GILLT_s32, |
| 178266 | GIM_CheckIsSafeToFold, /*NumInsns*/5, |
| 178267 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178268 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178269 | GIM_CheckComplexPattern, /*MI*/3, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178270 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/1, /*Renderer*/GIMT_Encode2(3), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178271 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/2, /*Renderer*/GIMT_Encode2(4), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178272 | GIM_CheckComplexPattern, /*MI*/5, /*Op*/3, /*Renderer*/GIMT_Encode2(5), GIMT_Encode2(GICP_gi_vop3_mad_mix_mods), |
| 178273 | // (AMDGPUclamp:{ *:[v2f16] } (build_vector:{ *:[v2f16] } (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src0, i32:{ *:[i32] }:$lo_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src1, i32:{ *:[i32] }:$lo_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$lo_src2, i32:{ *:[i32] }:$lo_src2_modifiers))), (fpround:{ *:[f16] } (fmad:{ *:[f32] } (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src0, i32:{ *:[i32] }:$hi_src0_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src1, i32:{ *:[i32] }:$hi_src1_modifiers), (VOP3PMadMixMods:{ *:[f32] } f16:{ *:[f16] }:$hi_src2, i32:{ *:[i32] }:$hi_src2_modifiers))))) => (V_MAD_MIXHI_F16:{ *:[v2f16] } ?:{ *:[i32] }:$hi_src0_modifiers, ?:{ *:[f16] }:$hi_src0, ?:{ *:[i32] }:$hi_src1_modifiers, ?:{ *:[f16] }:$hi_src1, ?:{ *:[i32] }:$hi_src2_modifiers, ?:{ *:[f16] }:$hi_src2, 1:{ *:[i1] }, (V_MAD_MIXLO_F16:{ *:[i16] } ?:{ *:[i32] }:$lo_src0_modifiers, ?:{ *:[f16] }:$lo_src0, ?:{ *:[i32] }:$lo_src1_modifiers, ?:{ *:[f16] }:$lo_src1, ?:{ *:[i32] }:$lo_src2_modifiers, ?:{ *:[f16] }:$lo_src2, 1:{ *:[i1] }, (IMPLICIT_DEF:{ *:[i32] }))) |
| 178274 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s16, |
| 178275 | GIR_MakeTempReg, /*TempRegID*/1, /*TypeID*/GILLT_s32, |
| 178276 | GIR_BuildMI, /*InsnID*/2, /*Opcode*/GIMT_Encode2(TargetOpcode::IMPLICIT_DEF), |
| 178277 | GIR_AddTempRegister, /*InsnID*/2, /*TempRegID*/1, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178278 | GIR_ConstrainSelectedInstOperands, /*InsnID*/2, |
| 178279 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXLO_F16), |
| 178280 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 178281 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // lo_src0_modifiers |
| 178282 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // lo_src0 |
| 178283 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // lo_src1_modifiers |
| 178284 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // lo_src1 |
| 178285 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // lo_src2_modifiers |
| 178286 | GIR_ComplexSubOperandRenderer, /*InsnID*/1, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // lo_src2 |
| 178287 | GIR_AddImm8, /*InsnID*/1, /*Imm*/1, |
| 178288 | GIR_AddSimpleTempRegister, /*InsnID*/1, /*TempRegID*/1, |
| 178289 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 178290 | GIR_AddImm8, /*InsnID*/1, /*Imm*/0, |
| 178291 | GIR_ConstrainSelectedInstOperands, /*InsnID*/1, |
| 178292 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAD_MIXHI_F16), |
| 178293 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/1, // hi_src0_modifiers |
| 178295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(3), /*SubOperand*/0, // hi_src0 |
| 178296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/1, // hi_src1_modifiers |
| 178297 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(4), /*SubOperand*/0, // hi_src1 |
| 178298 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/1, // hi_src2_modifiers |
| 178299 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(5), /*SubOperand*/0, // hi_src2 |
| 178300 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 178302 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178303 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178304 | GIR_RootConstrainSelectedInstOperands, |
| 178305 | // GIR_Coverage, 2309, |
| 178306 | GIR_EraseRootFromParent_Done, |
| 178307 | // Label 8342: @560878 |
| 178308 | GIM_Try, /*On fail goto*//*Label 8343*/ GIMT_Encode4(560935), // Rule ID 7007 // |
| 178309 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasVOP3PInsts), |
| 178310 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3pmods), |
| 178311 | // (AMDGPUclamp:{ *:[v2f16] } (VOP3PMods:{ *:[v2f16] } v2f16:{ *:[v2f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers)) => (V_PK_MAX_F16:{ *:[v2f16] } ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2f16] }:$src0, ?:{ *:[i32] }:$src0_modifiers, ?:{ *:[v2f16] }:$src0, 1:{ *:[i1] }) |
| 178312 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_PK_MAX_F16), |
| 178313 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178314 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178315 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178316 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178318 | GIR_AddImm8, /*InsnID*/0, /*Imm*/1, |
| 178319 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178320 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178321 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178322 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178323 | GIR_RootConstrainSelectedInstOperands, |
| 178324 | // GIR_Coverage, 7007, |
| 178325 | GIR_EraseRootFromParent_Done, |
| 178326 | // Label 8343: @560935 |
| 178327 | GIM_Reject, |
| 178328 | // Label 8340: @560936 |
| 178329 | GIM_Reject, |
| 178330 | // Label 8331: @560937 |
| 178331 | GIM_Reject, |
| 178332 | // Label 144: @560938 |
| 178333 | GIM_Try, /*On fail goto*//*Label 8344*/ GIMT_Encode4(560982), // Rule ID 594 // |
| 178334 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178335 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178336 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178337 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178338 | // (AMDGPUcvt_f32_ubyte0:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_UBYTE0_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178339 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE0_e64), |
| 178340 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178341 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178342 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 178343 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 178344 | GIR_RootConstrainSelectedInstOperands, |
| 178345 | // GIR_Coverage, 594, |
| 178346 | GIR_EraseRootFromParent_Done, |
| 178347 | // Label 8344: @560982 |
| 178348 | GIM_Reject, |
| 178349 | // Label 145: @560983 |
| 178350 | GIM_Try, /*On fail goto*//*Label 8345*/ GIMT_Encode4(561027), // Rule ID 595 // |
| 178351 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178352 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178353 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178354 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178355 | // (AMDGPUcvt_f32_ubyte1:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_UBYTE1_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178356 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE1_e64), |
| 178357 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178358 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178359 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 178360 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 178361 | GIR_RootConstrainSelectedInstOperands, |
| 178362 | // GIR_Coverage, 595, |
| 178363 | GIR_EraseRootFromParent_Done, |
| 178364 | // Label 8345: @561027 |
| 178365 | GIM_Reject, |
| 178366 | // Label 146: @561028 |
| 178367 | GIM_Try, /*On fail goto*//*Label 8346*/ GIMT_Encode4(561072), // Rule ID 596 // |
| 178368 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178370 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178371 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178372 | // (AMDGPUcvt_f32_ubyte2:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_UBYTE2_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178373 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE2_e64), |
| 178374 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178376 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 178377 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 178378 | GIR_RootConstrainSelectedInstOperands, |
| 178379 | // GIR_Coverage, 596, |
| 178380 | GIR_EraseRootFromParent_Done, |
| 178381 | // Label 8346: @561072 |
| 178382 | GIM_Reject, |
| 178383 | // Label 147: @561073 |
| 178384 | GIM_Try, /*On fail goto*//*Label 8347*/ GIMT_Encode4(561117), // Rule ID 597 // |
| 178385 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178386 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178387 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178388 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178389 | // (AMDGPUcvt_f32_ubyte3:{ *:[f32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_CVT_F32_UBYTE3_e64:{ *:[f32] } i32:{ *:[i32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178390 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_F32_UBYTE3_e64), |
| 178391 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178393 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // clamp |
| 178394 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // omod |
| 178395 | GIR_RootConstrainSelectedInstOperands, |
| 178396 | // GIR_Coverage, 597, |
| 178397 | GIR_EraseRootFromParent_Done, |
| 178398 | // Label 8347: @561117 |
| 178399 | GIM_Reject, |
| 178400 | // Label 148: @561118 |
| 178401 | GIM_Try, /*On fail goto*//*Label 8348*/ GIMT_Encode4(561147), // Rule ID 768 // |
| 178402 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_v2s16, |
| 178403 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178404 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178405 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178406 | // (AMDGPUpk_i16_i32_impl:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) => (V_CVT_PK_I16_I32_e64:{ *:[v2i16] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1) |
| 178407 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::V_CVT_PK_I16_I32_e64), |
| 178408 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 178409 | GIR_RootConstrainSelectedInstOperands, |
| 178410 | // GIR_Coverage, 768, |
| 178411 | GIR_Done, |
| 178412 | // Label 8348: @561147 |
| 178413 | GIM_Reject, |
| 178414 | // Label 149: @561148 |
| 178415 | GIM_Try, /*On fail goto*//*Label 8349*/ GIMT_Encode4(561249), |
| 178416 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178417 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 8352*/ GIMT_Encode4(561217), |
| 178418 | /*GILLT_s32*//*Label 8350*/ GIMT_Encode4(561175), |
| 178419 | /*GILLT_s64*//*Label 8351*/ GIMT_Encode4(561196), |
| 178420 | // Label 8350: @561175 |
| 178421 | GIM_Try, /*On fail goto*//*Label 8353*/ GIMT_Encode4(561195), // Rule ID 13 // |
| 178422 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 178423 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18482), |
| 178424 | // (AMDGPUffbh_u32_impl:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18482>> => (S_FLBIT_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 178425 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B32), |
| 178426 | GIR_RootConstrainSelectedInstOperands, |
| 178427 | // GIR_Coverage, 13, |
| 178428 | GIR_Done, |
| 178429 | // Label 8353: @561195 |
| 178430 | GIM_Reject, |
| 178431 | // Label 8351: @561196 |
| 178432 | GIM_Try, /*On fail goto*//*Label 8354*/ GIMT_Encode4(561216), // Rule ID 15 // |
| 178433 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 178434 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18482), |
| 178435 | // (AMDGPUffbh_u32_impl:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18482>> => (S_FLBIT_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0) |
| 178436 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FLBIT_I32_B64), |
| 178437 | GIR_RootConstrainSelectedInstOperands, |
| 178438 | // GIR_Coverage, 15, |
| 178439 | GIR_Done, |
| 178440 | // Label 8354: @561216 |
| 178441 | GIM_Reject, |
| 178442 | // Label 8352: @561217 |
| 178443 | GIM_Try, /*On fail goto*//*Label 8355*/ GIMT_Encode4(561248), // Rule ID 625 // |
| 178444 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178445 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178446 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178447 | // (AMDGPUffbh_u32_impl:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_FFBH_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 178448 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBH_U32_e64), |
| 178449 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178450 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178451 | GIR_RootConstrainSelectedInstOperands, |
| 178452 | // GIR_Coverage, 625, |
| 178453 | GIR_EraseRootFromParent_Done, |
| 178454 | // Label 8355: @561248 |
| 178455 | GIM_Reject, |
| 178456 | // Label 8349: @561249 |
| 178457 | GIM_Reject, |
| 178458 | // Label 150: @561250 |
| 178459 | GIM_Try, /*On fail goto*//*Label 8356*/ GIMT_Encode4(561348), |
| 178460 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178461 | GIM_SwitchType, /*MI*/0, /*Op*/1, /*[*/GIMT_Encode2(9), GIMT_Encode2(11), /*)*//*default:*//*Label 8359*/ GIMT_Encode4(561347), |
| 178462 | /*GILLT_s32*//*Label 8357*/ GIMT_Encode4(561277), |
| 178463 | /*GILLT_s64*//*Label 8358*/ GIMT_Encode4(561326), |
| 178464 | // Label 8357: @561277 |
| 178465 | GIM_Try, /*On fail goto*//*Label 8360*/ GIMT_Encode4(561297), // Rule ID 11 // |
| 178466 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 178467 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18481), |
| 178468 | // (AMDGPUffbl_b32_impl:{ *:[i32] } i32:{ *:[i32] }:$src0)<<P:Predicate_anonymous_18481>> => (S_FF1_I32_B32:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 178469 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B32), |
| 178470 | GIR_RootConstrainSelectedInstOperands, |
| 178471 | // GIR_Coverage, 11, |
| 178472 | GIR_Done, |
| 178473 | // Label 8360: @561297 |
| 178474 | GIM_Try, /*On fail goto*//*Label 8361*/ GIMT_Encode4(561325), // Rule ID 627 // |
| 178475 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178476 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178477 | // (AMDGPUffbl_b32_impl:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0)) => (V_FFBL_B32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0) |
| 178478 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_FFBL_B32_e64), |
| 178479 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178481 | GIR_RootConstrainSelectedInstOperands, |
| 178482 | // GIR_Coverage, 627, |
| 178483 | GIR_EraseRootFromParent_Done, |
| 178484 | // Label 8361: @561325 |
| 178485 | GIM_Reject, |
| 178486 | // Label 8358: @561326 |
| 178487 | GIM_Try, /*On fail goto*//*Label 8362*/ GIMT_Encode4(561346), // Rule ID 9 // |
| 178488 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32RegClassID), |
| 178489 | GIM_CheckCxxInsnPredicate, /*MI*/0, /*FnId*/GIMT_Encode2(GICXXPred_MI_Predicate_anonymous_18481), |
| 178490 | // (AMDGPUffbl_b32_impl:{ *:[i32] } i64:{ *:[i64] }:$src0)<<P:Predicate_anonymous_18481>> => (S_FF1_I32_B64:{ *:[i32] } i64:{ *:[i64] }:$src0) |
| 178491 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::S_FF1_I32_B64), |
| 178492 | GIR_RootConstrainSelectedInstOperands, |
| 178493 | // GIR_Coverage, 9, |
| 178494 | GIR_Done, |
| 178495 | // Label 8362: @561346 |
| 178496 | GIM_Reject, |
| 178497 | // Label 8359: @561347 |
| 178498 | GIM_Reject, |
| 178499 | // Label 8356: @561348 |
| 178500 | GIM_Reject, |
| 178501 | // Label 151: @561349 |
| 178502 | GIM_Try, /*On fail goto*//*Label 8363*/ GIMT_Encode4(561421), // Rule ID 770 // |
| 178503 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 178504 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178505 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178506 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178507 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178509 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 178510 | // (AMDGPUfmax_legacy:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MAX_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178511 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MAX_LEGACY_F32_e64), |
| 178512 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178513 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178515 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 178516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 178517 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 178518 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 178519 | GIR_RootConstrainSelectedInstOperands, |
| 178520 | // GIR_Coverage, 770, |
| 178521 | GIR_EraseRootFromParent_Done, |
| 178522 | // Label 8363: @561421 |
| 178523 | GIM_Reject, |
| 178524 | // Label 152: @561422 |
| 178525 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 8366*/ GIMT_Encode4(561617), |
| 178526 | /*GILLT_s16*//*Label 8364*/ GIMT_Encode4(561441), |
| 178527 | /*GILLT_s32*//*Label 8365*/ GIMT_Encode4(561530), |
| 178528 | // Label 8364: @561441 |
| 178529 | GIM_Try, /*On fail goto*//*Label 8367*/ GIMT_Encode4(561529), // Rule ID 929 // |
| 178530 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178531 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 178532 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 178533 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 178534 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178536 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178537 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178538 | // (AMDGPUfmed3_impl:{ *:[f16] } (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[f16] } f16:{ *:[f16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_F16_e64:{ *:[f16] } i32:{ *:[i32] }:$src0_modifiers, f16:{ *:[f16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f16:{ *:[f16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f16:{ *:[f16] }:$src2) |
| 178539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F16_e64), |
| 178540 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178541 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178543 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 178544 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 178545 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 178546 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 178547 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178548 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178549 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178550 | GIR_RootConstrainSelectedInstOperands, |
| 178551 | // GIR_Coverage, 929, |
| 178552 | GIR_EraseRootFromParent_Done, |
| 178553 | // Label 8367: @561529 |
| 178554 | GIM_Reject, |
| 178555 | // Label 8365: @561530 |
| 178556 | GIM_Try, /*On fail goto*//*Label 8368*/ GIMT_Encode4(561616), // Rule ID 890 // |
| 178557 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178558 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178559 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 178560 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178562 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 178563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3mods), |
| 178564 | // (AMDGPUfmed3_impl:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src2_modifiers, f32:{ *:[f32] }:$src2, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_F32_e64), |
| 178566 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178567 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178568 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 178570 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 178571 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 178572 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 178573 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 178574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 178575 | GIR_RootConstrainSelectedInstOperands, |
| 178576 | // GIR_Coverage, 890, |
| 178577 | GIR_EraseRootFromParent_Done, |
| 178578 | // Label 8368: @561616 |
| 178579 | GIM_Reject, |
| 178580 | // Label 8366: @561617 |
| 178581 | GIM_Reject, |
| 178582 | // Label 153: @561618 |
| 178583 | GIM_Try, /*On fail goto*//*Label 8369*/ GIMT_Encode4(561690), // Rule ID 769 // |
| 178584 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX6GFX7), |
| 178585 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178586 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178587 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178588 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178590 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3mods), |
| 178591 | // (AMDGPUfmin_legacy:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod), (VOP3Mods:{ *:[f32] } f32:{ *:[f32] }:$src1, i32:{ *:[i32] }:$src1_modifiers)) => (V_MIN_LEGACY_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src1_modifiers, f32:{ *:[f32] }:$src1, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178592 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MIN_LEGACY_F32_e64), |
| 178593 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178594 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178596 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 178597 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 178598 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 178599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 178600 | GIR_RootConstrainSelectedInstOperands, |
| 178601 | // GIR_Coverage, 769, |
| 178602 | GIR_EraseRootFromParent_Done, |
| 178603 | // Label 8369: @561690 |
| 178604 | GIM_Reject, |
| 178605 | // Label 154: @561691 |
| 178606 | GIM_Try, /*On fail goto*//*Label 8370*/ GIMT_Encode4(561740), // Rule ID 610 // |
| 178607 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 178608 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178609 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178610 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178611 | // (AMDGPUrcp_iflag:{ *:[f32] } (VOP3Mods0:{ *:[f32] } f32:{ *:[f32] }:$src0, i32:{ *:[i32] }:$src0_modifiers, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod)) => (V_RCP_IFLAG_F32_e64:{ *:[f32] } i32:{ *:[i32] }:$src0_modifiers, f32:{ *:[f32] }:$src0, i1:{ *:[i1] }:$clamp, i32:{ *:[i32] }:$omod) |
| 178612 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_RCP_IFLAG_F32_e64), |
| 178613 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178614 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178615 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178616 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/2, // clamp |
| 178617 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/3, // omod |
| 178618 | GIR_RootConstrainSelectedInstOperands, |
| 178619 | // GIR_Coverage, 610, |
| 178620 | GIR_EraseRootFromParent_Done, |
| 178621 | // Label 8370: @561740 |
| 178622 | GIM_Reject, |
| 178623 | // Label 155: @561741 |
| 178624 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 8373*/ GIMT_Encode4(561888), |
| 178625 | /*GILLT_s16*//*Label 8371*/ GIMT_Encode4(561760), |
| 178626 | /*GILLT_s32*//*Label 8372*/ GIMT_Encode4(561846), |
| 178627 | // Label 8371: @561760 |
| 178628 | GIM_Try, /*On fail goto*//*Label 8374*/ GIMT_Encode4(561845), // Rule ID 930 // |
| 178629 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178630 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 178631 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 178632 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 178633 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178634 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178635 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178636 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 178637 | // (AMDGPUsmed3:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_I16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2) |
| 178638 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I16_e64), |
| 178639 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178640 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 178641 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178642 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 178643 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 178644 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 178645 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 178646 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178647 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178648 | GIR_RootConstrainSelectedInstOperands, |
| 178649 | // GIR_Coverage, 930, |
| 178650 | GIR_EraseRootFromParent_Done, |
| 178651 | // Label 8374: @561845 |
| 178652 | GIM_Reject, |
| 178653 | // Label 8372: @561846 |
| 178654 | GIM_Try, /*On fail goto*//*Label 8375*/ GIMT_Encode4(561887), // Rule ID 885 // |
| 178655 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 178656 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178657 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 178658 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 178659 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 178660 | // (AMDGPUsmed3:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_MED3_I32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 178661 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_I32_e64), |
| 178662 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 178663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 178664 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 178665 | GIR_RootToRootCopy, /*OpIdx*/3, // src2 |
| 178666 | GIR_RootConstrainSelectedInstOperands, |
| 178667 | // GIR_Coverage, 885, |
| 178668 | GIR_EraseRootFromParent_Done, |
| 178669 | // Label 8375: @561887 |
| 178670 | GIM_Reject, |
| 178671 | // Label 8373: @561888 |
| 178672 | GIM_Reject, |
| 178673 | // Label 156: @561889 |
| 178674 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(31), /*)*//*default:*//*Label 8382*/ GIMT_Encode4(564190), |
| 178675 | /*GILLT_s32*//*Label 8376*/ GIMT_Encode4(561988), GIMT_Encode4(0), GIMT_Encode4(0), |
| 178676 | /*GILLT_v2s32*//*Label 8377*/ GIMT_Encode4(562368), GIMT_Encode4(0), |
| 178677 | /*GILLT_v3s32*//*Label 8378*/ GIMT_Encode4(562748), GIMT_Encode4(0), GIMT_Encode4(0), |
| 178678 | /*GILLT_v4s32*//*Label 8379*/ GIMT_Encode4(563050), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 178679 | /*GILLT_v8s32*//*Label 8380*/ GIMT_Encode4(563430), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), GIMT_Encode4(0), |
| 178680 | /*GILLT_v16s32*//*Label 8381*/ GIMT_Encode4(563810), |
| 178681 | // Label 8376: @561988 |
| 178682 | GIM_Try, /*On fail goto*//*Label 8383*/ GIMT_Encode4(562367), |
| 178683 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 178684 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178685 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 178686 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 178687 | GIM_Try, /*On fail goto*//*Label 8384*/ GIMT_Encode4(562050), // Rule ID 2469 // |
| 178688 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178689 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178690 | // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178691 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM), |
| 178692 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178693 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178694 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178695 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 178696 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178697 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178698 | GIR_RootConstrainSelectedInstOperands, |
| 178699 | // GIR_Coverage, 2469, |
| 178700 | GIR_EraseRootFromParent_Done, |
| 178701 | // Label 8384: @562050 |
| 178702 | GIM_Try, /*On fail goto*//*Label 8385*/ GIMT_Encode4(562094), // Rule ID 3154 // |
| 178703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178705 | // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM), |
| 178707 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178708 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178709 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 178711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178712 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178713 | GIR_RootConstrainSelectedInstOperands, |
| 178714 | // GIR_Coverage, 3154, |
| 178715 | GIR_EraseRootFromParent_Done, |
| 178716 | // Label 8385: @562094 |
| 178717 | GIM_Try, /*On fail goto*//*Label 8386*/ GIMT_Encode4(562130), // Rule ID 2465 // |
| 178718 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 178719 | // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178720 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM), |
| 178721 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178722 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178723 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178724 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178725 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178726 | GIR_RootConstrainSelectedInstOperands, |
| 178727 | // GIR_Coverage, 2465, |
| 178728 | GIR_EraseRootFromParent_Done, |
| 178729 | // Label 8386: @562130 |
| 178730 | GIM_Try, /*On fail goto*//*Label 8387*/ GIMT_Encode4(562166), // Rule ID 3150 // |
| 178731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 178732 | // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM), |
| 178734 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178735 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178737 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178738 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178739 | GIR_RootConstrainSelectedInstOperands, |
| 178740 | // GIR_Coverage, 3150, |
| 178741 | GIR_EraseRootFromParent_Done, |
| 178742 | // Label 8387: @562166 |
| 178743 | GIM_Try, /*On fail goto*//*Label 8388*/ GIMT_Encode4(562205), // Rule ID 2466 // |
| 178744 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 178745 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 178746 | // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_IMM_ci:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci), |
| 178748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178749 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178750 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178751 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178752 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178753 | GIR_RootConstrainSelectedInstOperands, |
| 178754 | // GIR_Coverage, 2466, |
| 178755 | GIR_EraseRootFromParent_Done, |
| 178756 | // Label 8388: @562205 |
| 178757 | GIM_Try, /*On fail goto*//*Label 8389*/ GIMT_Encode4(562244), // Rule ID 3151 // |
| 178758 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 178759 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 178760 | // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_IMM_ci:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178761 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_IMM_ci), |
| 178762 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178763 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178764 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178765 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178766 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178767 | GIR_RootConstrainSelectedInstOperands, |
| 178768 | // GIR_Coverage, 3151, |
| 178769 | GIR_EraseRootFromParent_Done, |
| 178770 | // Label 8389: @562244 |
| 178771 | GIM_Try, /*On fail goto*//*Label 8390*/ GIMT_Encode4(562273), // Rule ID 2467 // |
| 178772 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 178773 | // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), |
| 178775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178776 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178777 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178778 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178779 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178780 | GIR_RootConstrainSelectedInstOperands, |
| 178781 | // GIR_Coverage, 2467, |
| 178782 | GIR_EraseRootFromParent_Done, |
| 178783 | // Label 8390: @562273 |
| 178784 | GIM_Try, /*On fail goto*//*Label 8391*/ GIMT_Encode4(562305), // Rule ID 2468 // |
| 178785 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178786 | // (SIsbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178787 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM), |
| 178788 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178789 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178790 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178791 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178793 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178794 | GIR_RootConstrainSelectedInstOperands, |
| 178795 | // GIR_Coverage, 2468, |
| 178796 | GIR_EraseRootFromParent_Done, |
| 178797 | // Label 8391: @562305 |
| 178798 | GIM_Try, /*On fail goto*//*Label 8392*/ GIMT_Encode4(562334), // Rule ID 3152 // |
| 178799 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 178800 | // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR), |
| 178802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178803 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178804 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178805 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178806 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178807 | GIR_RootConstrainSelectedInstOperands, |
| 178808 | // GIR_Coverage, 3152, |
| 178809 | GIR_EraseRootFromParent_Done, |
| 178810 | // Label 8392: @562334 |
| 178811 | GIM_Try, /*On fail goto*//*Label 8393*/ GIMT_Encode4(562366), // Rule ID 3153 // |
| 178812 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178813 | // (SIsbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORD_SGPR_IMM:{ *:[f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178814 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORD_SGPR_IMM), |
| 178815 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178816 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178817 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178818 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178819 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178820 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178821 | GIR_RootConstrainSelectedInstOperands, |
| 178822 | // GIR_Coverage, 3153, |
| 178823 | GIR_EraseRootFromParent_Done, |
| 178824 | // Label 8393: @562366 |
| 178825 | GIM_Reject, |
| 178826 | // Label 8383: @562367 |
| 178827 | GIM_Reject, |
| 178828 | // Label 8377: @562368 |
| 178829 | GIM_Try, /*On fail goto*//*Label 8394*/ GIMT_Encode4(562747), |
| 178830 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 178831 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178832 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_64_XEXECRegClassID), |
| 178833 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 178834 | GIM_Try, /*On fail goto*//*Label 8395*/ GIMT_Encode4(562430), // Rule ID 3130 // |
| 178835 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178836 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178837 | // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178838 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM), |
| 178839 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178840 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178841 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178842 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 178843 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178844 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178845 | GIR_RootConstrainSelectedInstOperands, |
| 178846 | // GIR_Coverage, 3130, |
| 178847 | GIR_EraseRootFromParent_Done, |
| 178848 | // Label 8395: @562430 |
| 178849 | GIM_Try, /*On fail goto*//*Label 8396*/ GIMT_Encode4(562474), // Rule ID 3159 // |
| 178850 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178851 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178852 | // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178853 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM), |
| 178854 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178855 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178856 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178857 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 178858 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178859 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178860 | GIR_RootConstrainSelectedInstOperands, |
| 178861 | // GIR_Coverage, 3159, |
| 178862 | GIR_EraseRootFromParent_Done, |
| 178863 | // Label 8396: @562474 |
| 178864 | GIM_Try, /*On fail goto*//*Label 8397*/ GIMT_Encode4(562510), // Rule ID 3126 // |
| 178865 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 178866 | // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM), |
| 178868 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178869 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178871 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178872 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178873 | GIR_RootConstrainSelectedInstOperands, |
| 178874 | // GIR_Coverage, 3126, |
| 178875 | GIR_EraseRootFromParent_Done, |
| 178876 | // Label 8397: @562510 |
| 178877 | GIM_Try, /*On fail goto*//*Label 8398*/ GIMT_Encode4(562546), // Rule ID 3155 // |
| 178878 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 178879 | // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178880 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM), |
| 178881 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178882 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178883 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178884 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178885 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178886 | GIR_RootConstrainSelectedInstOperands, |
| 178887 | // GIR_Coverage, 3155, |
| 178888 | GIR_EraseRootFromParent_Done, |
| 178889 | // Label 8398: @562546 |
| 178890 | GIM_Try, /*On fail goto*//*Label 8399*/ GIMT_Encode4(562585), // Rule ID 3127 // |
| 178891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 178892 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 178893 | // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_IMM_ci:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178894 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci), |
| 178895 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178896 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178898 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178899 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178900 | GIR_RootConstrainSelectedInstOperands, |
| 178901 | // GIR_Coverage, 3127, |
| 178902 | GIR_EraseRootFromParent_Done, |
| 178903 | // Label 8399: @562585 |
| 178904 | GIM_Try, /*On fail goto*//*Label 8400*/ GIMT_Encode4(562624), // Rule ID 3156 // |
| 178905 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 178906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 178907 | // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_IMM_ci:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178908 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_IMM_ci), |
| 178909 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178910 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 178912 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178913 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178914 | GIR_RootConstrainSelectedInstOperands, |
| 178915 | // GIR_Coverage, 3156, |
| 178916 | GIR_EraseRootFromParent_Done, |
| 178917 | // Label 8400: @562624 |
| 178918 | GIM_Try, /*On fail goto*//*Label 8401*/ GIMT_Encode4(562653), // Rule ID 3128 // |
| 178919 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 178920 | // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178921 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR), |
| 178922 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178923 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178924 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178925 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178926 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178927 | GIR_RootConstrainSelectedInstOperands, |
| 178928 | // GIR_Coverage, 3128, |
| 178929 | GIR_EraseRootFromParent_Done, |
| 178930 | // Label 8401: @562653 |
| 178931 | GIM_Try, /*On fail goto*//*Label 8402*/ GIMT_Encode4(562685), // Rule ID 3129 // |
| 178932 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178933 | // (SIsbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM), |
| 178935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178936 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178937 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178938 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178939 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178940 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178941 | GIR_RootConstrainSelectedInstOperands, |
| 178942 | // GIR_Coverage, 3129, |
| 178943 | GIR_EraseRootFromParent_Done, |
| 178944 | // Label 8402: @562685 |
| 178945 | GIM_Try, /*On fail goto*//*Label 8403*/ GIMT_Encode4(562714), // Rule ID 3157 // |
| 178946 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 178947 | // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178948 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR), |
| 178949 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178950 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178951 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178952 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178954 | GIR_RootConstrainSelectedInstOperands, |
| 178955 | // GIR_Coverage, 3157, |
| 178956 | GIR_EraseRootFromParent_Done, |
| 178957 | // Label 8403: @562714 |
| 178958 | GIM_Try, /*On fail goto*//*Label 8404*/ GIMT_Encode4(562746), // Rule ID 3158 // |
| 178959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178960 | // (SIsbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX2_SGPR_IMM:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178961 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX2_SGPR_IMM), |
| 178962 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178963 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178964 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 178965 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 178966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178967 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178968 | GIR_RootConstrainSelectedInstOperands, |
| 178969 | // GIR_Coverage, 3158, |
| 178970 | GIR_EraseRootFromParent_Done, |
| 178971 | // Label 8404: @562746 |
| 178972 | GIM_Reject, |
| 178973 | // Label 8394: @562747 |
| 178974 | GIM_Reject, |
| 178975 | // Label 8378: @562748 |
| 178976 | GIM_Try, /*On fail goto*//*Label 8405*/ GIMT_Encode4(563049), |
| 178977 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 178978 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 178979 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_96RegClassID), |
| 178980 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 178981 | GIM_Try, /*On fail goto*//*Label 8406*/ GIMT_Encode4(562810), // Rule ID 3134 // |
| 178982 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178983 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178984 | // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 178985 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM), |
| 178986 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 178987 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 178988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 178989 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 178990 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 178991 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 178992 | GIR_RootConstrainSelectedInstOperands, |
| 178993 | // GIR_Coverage, 3134, |
| 178994 | GIR_EraseRootFromParent_Done, |
| 178995 | // Label 8406: @562810 |
| 178996 | GIM_Try, /*On fail goto*//*Label 8407*/ GIMT_Encode4(562854), // Rule ID 3163 // |
| 178997 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 178998 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 178999 | // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179000 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM), |
| 179001 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179002 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179003 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179004 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179005 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179006 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179007 | GIR_RootConstrainSelectedInstOperands, |
| 179008 | // GIR_Coverage, 3163, |
| 179009 | GIR_EraseRootFromParent_Done, |
| 179010 | // Label 8407: @562854 |
| 179011 | GIM_Try, /*On fail goto*//*Label 8408*/ GIMT_Encode4(562890), // Rule ID 3131 // |
| 179012 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179013 | // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179014 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM), |
| 179015 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179016 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179018 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179019 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179020 | GIR_RootConstrainSelectedInstOperands, |
| 179021 | // GIR_Coverage, 3131, |
| 179022 | GIR_EraseRootFromParent_Done, |
| 179023 | // Label 8408: @562890 |
| 179024 | GIM_Try, /*On fail goto*//*Label 8409*/ GIMT_Encode4(562926), // Rule ID 3160 // |
| 179025 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179026 | // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179027 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_IMM), |
| 179028 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179029 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179030 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179031 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179032 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179033 | GIR_RootConstrainSelectedInstOperands, |
| 179034 | // GIR_Coverage, 3160, |
| 179035 | GIR_EraseRootFromParent_Done, |
| 179036 | // Label 8409: @562926 |
| 179037 | GIM_Try, /*On fail goto*//*Label 8410*/ GIMT_Encode4(562955), // Rule ID 3132 // |
| 179038 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179039 | // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR), |
| 179041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179042 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179043 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179044 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179045 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179046 | GIR_RootConstrainSelectedInstOperands, |
| 179047 | // GIR_Coverage, 3132, |
| 179048 | GIR_EraseRootFromParent_Done, |
| 179049 | // Label 8410: @562955 |
| 179050 | GIM_Try, /*On fail goto*//*Label 8411*/ GIMT_Encode4(562987), // Rule ID 3133 // |
| 179051 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179052 | // (SIsbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179053 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM), |
| 179054 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179055 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179056 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179057 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179058 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179059 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179060 | GIR_RootConstrainSelectedInstOperands, |
| 179061 | // GIR_Coverage, 3133, |
| 179062 | GIR_EraseRootFromParent_Done, |
| 179063 | // Label 8411: @562987 |
| 179064 | GIM_Try, /*On fail goto*//*Label 8412*/ GIMT_Encode4(563016), // Rule ID 3161 // |
| 179065 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179066 | // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179067 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR), |
| 179068 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179069 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179070 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179071 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179072 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179073 | GIR_RootConstrainSelectedInstOperands, |
| 179074 | // GIR_Coverage, 3161, |
| 179075 | GIR_EraseRootFromParent_Done, |
| 179076 | // Label 8412: @563016 |
| 179077 | GIM_Try, /*On fail goto*//*Label 8413*/ GIMT_Encode4(563048), // Rule ID 3162 // |
| 179078 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179079 | // (SIsbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX3_SGPR_IMM:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179080 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX3_SGPR_IMM), |
| 179081 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179082 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179083 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179084 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179085 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179086 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179087 | GIR_RootConstrainSelectedInstOperands, |
| 179088 | // GIR_Coverage, 3162, |
| 179089 | GIR_EraseRootFromParent_Done, |
| 179090 | // Label 8413: @563048 |
| 179091 | GIM_Reject, |
| 179092 | // Label 8405: @563049 |
| 179093 | GIM_Reject, |
| 179094 | // Label 8379: @563050 |
| 179095 | GIM_Try, /*On fail goto*//*Label 8414*/ GIMT_Encode4(563429), |
| 179096 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179097 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179098 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_128RegClassID), |
| 179099 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179100 | GIM_Try, /*On fail goto*//*Label 8415*/ GIMT_Encode4(563112), // Rule ID 3139 // |
| 179101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179102 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179103 | // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179104 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM), |
| 179105 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179106 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179107 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179108 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179110 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179111 | GIR_RootConstrainSelectedInstOperands, |
| 179112 | // GIR_Coverage, 3139, |
| 179113 | GIR_EraseRootFromParent_Done, |
| 179114 | // Label 8415: @563112 |
| 179115 | GIM_Try, /*On fail goto*//*Label 8416*/ GIMT_Encode4(563156), // Rule ID 3168 // |
| 179116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179117 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179118 | // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179119 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM), |
| 179120 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179121 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179122 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179123 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179124 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179125 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179126 | GIR_RootConstrainSelectedInstOperands, |
| 179127 | // GIR_Coverage, 3168, |
| 179128 | GIR_EraseRootFromParent_Done, |
| 179129 | // Label 8416: @563156 |
| 179130 | GIM_Try, /*On fail goto*//*Label 8417*/ GIMT_Encode4(563192), // Rule ID 3135 // |
| 179131 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179132 | // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179133 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM), |
| 179134 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179135 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179136 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179137 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179138 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179139 | GIR_RootConstrainSelectedInstOperands, |
| 179140 | // GIR_Coverage, 3135, |
| 179141 | GIR_EraseRootFromParent_Done, |
| 179142 | // Label 8417: @563192 |
| 179143 | GIM_Try, /*On fail goto*//*Label 8418*/ GIMT_Encode4(563228), // Rule ID 3164 // |
| 179144 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179145 | // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179146 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM), |
| 179147 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179148 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179149 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179150 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179151 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179152 | GIR_RootConstrainSelectedInstOperands, |
| 179153 | // GIR_Coverage, 3164, |
| 179154 | GIR_EraseRootFromParent_Done, |
| 179155 | // Label 8418: @563228 |
| 179156 | GIM_Try, /*On fail goto*//*Label 8419*/ GIMT_Encode4(563267), // Rule ID 3136 // |
| 179157 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179158 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179159 | // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_IMM_ci:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179160 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci), |
| 179161 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179162 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179163 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179164 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179165 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179166 | GIR_RootConstrainSelectedInstOperands, |
| 179167 | // GIR_Coverage, 3136, |
| 179168 | GIR_EraseRootFromParent_Done, |
| 179169 | // Label 8419: @563267 |
| 179170 | GIM_Try, /*On fail goto*//*Label 8420*/ GIMT_Encode4(563306), // Rule ID 3165 // |
| 179171 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179172 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179173 | // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_IMM_ci:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179174 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_IMM_ci), |
| 179175 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179176 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179178 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179179 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179180 | GIR_RootConstrainSelectedInstOperands, |
| 179181 | // GIR_Coverage, 3165, |
| 179182 | GIR_EraseRootFromParent_Done, |
| 179183 | // Label 8420: @563306 |
| 179184 | GIM_Try, /*On fail goto*//*Label 8421*/ GIMT_Encode4(563335), // Rule ID 3137 // |
| 179185 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179186 | // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179187 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR), |
| 179188 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179189 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179190 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179191 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179192 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179193 | GIR_RootConstrainSelectedInstOperands, |
| 179194 | // GIR_Coverage, 3137, |
| 179195 | GIR_EraseRootFromParent_Done, |
| 179196 | // Label 8421: @563335 |
| 179197 | GIM_Try, /*On fail goto*//*Label 8422*/ GIMT_Encode4(563367), // Rule ID 3138 // |
| 179198 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179199 | // (SIsbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM), |
| 179201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179202 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179203 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179204 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179205 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179206 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179207 | GIR_RootConstrainSelectedInstOperands, |
| 179208 | // GIR_Coverage, 3138, |
| 179209 | GIR_EraseRootFromParent_Done, |
| 179210 | // Label 8422: @563367 |
| 179211 | GIM_Try, /*On fail goto*//*Label 8423*/ GIMT_Encode4(563396), // Rule ID 3166 // |
| 179212 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179213 | // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179214 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR), |
| 179215 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179216 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179217 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179219 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179220 | GIR_RootConstrainSelectedInstOperands, |
| 179221 | // GIR_Coverage, 3166, |
| 179222 | GIR_EraseRootFromParent_Done, |
| 179223 | // Label 8423: @563396 |
| 179224 | GIM_Try, /*On fail goto*//*Label 8424*/ GIMT_Encode4(563428), // Rule ID 3167 // |
| 179225 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179226 | // (SIsbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX4_SGPR_IMM:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179227 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX4_SGPR_IMM), |
| 179228 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179229 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179230 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179231 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179232 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179233 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179234 | GIR_RootConstrainSelectedInstOperands, |
| 179235 | // GIR_Coverage, 3167, |
| 179236 | GIR_EraseRootFromParent_Done, |
| 179237 | // Label 8424: @563428 |
| 179238 | GIM_Reject, |
| 179239 | // Label 8414: @563429 |
| 179240 | GIM_Reject, |
| 179241 | // Label 8380: @563430 |
| 179242 | GIM_Try, /*On fail goto*//*Label 8425*/ GIMT_Encode4(563809), |
| 179243 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179244 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179245 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_256RegClassID), |
| 179246 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179247 | GIM_Try, /*On fail goto*//*Label 8426*/ GIMT_Encode4(563492), // Rule ID 3144 // |
| 179248 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179249 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179250 | // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179251 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM), |
| 179252 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179253 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179254 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179255 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179256 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179257 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179258 | GIR_RootConstrainSelectedInstOperands, |
| 179259 | // GIR_Coverage, 3144, |
| 179260 | GIR_EraseRootFromParent_Done, |
| 179261 | // Label 8426: @563492 |
| 179262 | GIM_Try, /*On fail goto*//*Label 8427*/ GIMT_Encode4(563536), // Rule ID 3173 // |
| 179263 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179265 | // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179266 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM), |
| 179267 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179268 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179269 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179270 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179273 | GIR_RootConstrainSelectedInstOperands, |
| 179274 | // GIR_Coverage, 3173, |
| 179275 | GIR_EraseRootFromParent_Done, |
| 179276 | // Label 8427: @563536 |
| 179277 | GIM_Try, /*On fail goto*//*Label 8428*/ GIMT_Encode4(563572), // Rule ID 3140 // |
| 179278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179279 | // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179280 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM), |
| 179281 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179282 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179284 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179285 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179286 | GIR_RootConstrainSelectedInstOperands, |
| 179287 | // GIR_Coverage, 3140, |
| 179288 | GIR_EraseRootFromParent_Done, |
| 179289 | // Label 8428: @563572 |
| 179290 | GIM_Try, /*On fail goto*//*Label 8429*/ GIMT_Encode4(563608), // Rule ID 3169 // |
| 179291 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179292 | // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179293 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM), |
| 179294 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179295 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179296 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179298 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179299 | GIR_RootConstrainSelectedInstOperands, |
| 179300 | // GIR_Coverage, 3169, |
| 179301 | GIR_EraseRootFromParent_Done, |
| 179302 | // Label 8429: @563608 |
| 179303 | GIM_Try, /*On fail goto*//*Label 8430*/ GIMT_Encode4(563647), // Rule ID 3141 // |
| 179304 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179306 | // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_IMM_ci:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179307 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci), |
| 179308 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179309 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179310 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179311 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179312 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179313 | GIR_RootConstrainSelectedInstOperands, |
| 179314 | // GIR_Coverage, 3141, |
| 179315 | GIR_EraseRootFromParent_Done, |
| 179316 | // Label 8430: @563647 |
| 179317 | GIM_Try, /*On fail goto*//*Label 8431*/ GIMT_Encode4(563686), // Rule ID 3170 // |
| 179318 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179319 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179320 | // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_IMM_ci:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179321 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_IMM_ci), |
| 179322 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179323 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179324 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179325 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179327 | GIR_RootConstrainSelectedInstOperands, |
| 179328 | // GIR_Coverage, 3170, |
| 179329 | GIR_EraseRootFromParent_Done, |
| 179330 | // Label 8431: @563686 |
| 179331 | GIM_Try, /*On fail goto*//*Label 8432*/ GIMT_Encode4(563715), // Rule ID 3142 // |
| 179332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179333 | // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179334 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR), |
| 179335 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179336 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179337 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179338 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179339 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179340 | GIR_RootConstrainSelectedInstOperands, |
| 179341 | // GIR_Coverage, 3142, |
| 179342 | GIR_EraseRootFromParent_Done, |
| 179343 | // Label 8432: @563715 |
| 179344 | GIM_Try, /*On fail goto*//*Label 8433*/ GIMT_Encode4(563747), // Rule ID 3143 // |
| 179345 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179346 | // (SIsbuffer_load:{ *:[v8i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179347 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM), |
| 179348 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179349 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179350 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179351 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179354 | GIR_RootConstrainSelectedInstOperands, |
| 179355 | // GIR_Coverage, 3143, |
| 179356 | GIR_EraseRootFromParent_Done, |
| 179357 | // Label 8433: @563747 |
| 179358 | GIM_Try, /*On fail goto*//*Label 8434*/ GIMT_Encode4(563776), // Rule ID 3171 // |
| 179359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179360 | // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR), |
| 179362 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179363 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179364 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179365 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179366 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179367 | GIR_RootConstrainSelectedInstOperands, |
| 179368 | // GIR_Coverage, 3171, |
| 179369 | GIR_EraseRootFromParent_Done, |
| 179370 | // Label 8434: @563776 |
| 179371 | GIM_Try, /*On fail goto*//*Label 8435*/ GIMT_Encode4(563808), // Rule ID 3172 // |
| 179372 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179373 | // (SIsbuffer_load:{ *:[v8f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX8_SGPR_IMM:{ *:[v8f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179374 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX8_SGPR_IMM), |
| 179375 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179376 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179377 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179378 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179379 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179381 | GIR_RootConstrainSelectedInstOperands, |
| 179382 | // GIR_Coverage, 3172, |
| 179383 | GIR_EraseRootFromParent_Done, |
| 179384 | // Label 8435: @563808 |
| 179385 | GIM_Reject, |
| 179386 | // Label 8425: @563809 |
| 179387 | GIM_Reject, |
| 179388 | // Label 8381: @563810 |
| 179389 | GIM_Try, /*On fail goto*//*Label 8436*/ GIMT_Encode4(564189), |
| 179390 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179391 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179392 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_512RegClassID), |
| 179393 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179394 | GIM_Try, /*On fail goto*//*Label 8437*/ GIMT_Encode4(563872), // Rule ID 3149 // |
| 179395 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179397 | // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM), |
| 179399 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179400 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179403 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179404 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179405 | GIR_RootConstrainSelectedInstOperands, |
| 179406 | // GIR_Coverage, 3149, |
| 179407 | GIR_EraseRootFromParent_Done, |
| 179408 | // Label 8437: @563872 |
| 179409 | GIM_Try, /*On fail goto*//*Label 8438*/ GIMT_Encode4(563916), // Rule ID 3178 // |
| 179410 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179412 | // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179413 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM), |
| 179414 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179415 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179416 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179417 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179418 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179419 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179420 | GIR_RootConstrainSelectedInstOperands, |
| 179421 | // GIR_Coverage, 3178, |
| 179422 | GIR_EraseRootFromParent_Done, |
| 179423 | // Label 8438: @563916 |
| 179424 | GIM_Try, /*On fail goto*//*Label 8439*/ GIMT_Encode4(563952), // Rule ID 3145 // |
| 179425 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179426 | // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179427 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM), |
| 179428 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179429 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179430 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179433 | GIR_RootConstrainSelectedInstOperands, |
| 179434 | // GIR_Coverage, 3145, |
| 179435 | GIR_EraseRootFromParent_Done, |
| 179436 | // Label 8439: @563952 |
| 179437 | GIM_Try, /*On fail goto*//*Label 8440*/ GIMT_Encode4(563988), // Rule ID 3174 // |
| 179438 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179439 | // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179440 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM), |
| 179441 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179442 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179443 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179444 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179445 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179446 | GIR_RootConstrainSelectedInstOperands, |
| 179447 | // GIR_Coverage, 3174, |
| 179448 | GIR_EraseRootFromParent_Done, |
| 179449 | // Label 8440: @563988 |
| 179450 | GIM_Try, /*On fail goto*//*Label 8441*/ GIMT_Encode4(564027), // Rule ID 3146 // |
| 179451 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179452 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179453 | // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_IMM_ci:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179454 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci), |
| 179455 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179456 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179457 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179458 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179459 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179460 | GIR_RootConstrainSelectedInstOperands, |
| 179461 | // GIR_Coverage, 3146, |
| 179462 | GIR_EraseRootFromParent_Done, |
| 179463 | // Label 8441: @564027 |
| 179464 | GIM_Try, /*On fail goto*//*Label 8442*/ GIMT_Encode4(564066), // Rule ID 3175 // |
| 179465 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX7Only), |
| 179466 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm32), |
| 179467 | // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm32:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_IMM_ci:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, smrd_literal_offset:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179468 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_IMM_ci), |
| 179469 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179470 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179471 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179472 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179473 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179474 | GIR_RootConstrainSelectedInstOperands, |
| 179475 | // GIR_Coverage, 3175, |
| 179476 | GIR_EraseRootFromParent_Done, |
| 179477 | // Label 8442: @564066 |
| 179478 | GIM_Try, /*On fail goto*//*Label 8443*/ GIMT_Encode4(564095), // Rule ID 3147 // |
| 179479 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179480 | // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179481 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR), |
| 179482 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179483 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179484 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179485 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179487 | GIR_RootConstrainSelectedInstOperands, |
| 179488 | // GIR_Coverage, 3147, |
| 179489 | GIR_EraseRootFromParent_Done, |
| 179490 | // Label 8443: @564095 |
| 179491 | GIM_Try, /*On fail goto*//*Label 8444*/ GIMT_Encode4(564127), // Rule ID 3148 // |
| 179492 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179493 | // (SIsbuffer_load:{ *:[v16i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179494 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM), |
| 179495 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179496 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179497 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179498 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179499 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179500 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179501 | GIR_RootConstrainSelectedInstOperands, |
| 179502 | // GIR_Coverage, 3148, |
| 179503 | GIR_EraseRootFromParent_Done, |
| 179504 | // Label 8444: @564127 |
| 179505 | GIM_Try, /*On fail goto*//*Label 8445*/ GIMT_Encode4(564156), // Rule ID 3176 // |
| 179506 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isNotGFX9Plus), |
| 179507 | // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179508 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR), |
| 179509 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179510 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179511 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179512 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179513 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179514 | GIR_RootConstrainSelectedInstOperands, |
| 179515 | // GIR_Coverage, 3176, |
| 179516 | GIR_EraseRootFromParent_Done, |
| 179517 | // Label 8445: @564156 |
| 179518 | GIM_Try, /*On fail goto*//*Label 8446*/ GIMT_Encode4(564188), // Rule ID 3177 // |
| 179519 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 179520 | // (SIsbuffer_load:{ *:[v16f32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_DWORDX16_SGPR_IMM:{ *:[v16f32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179521 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_DWORDX16_SGPR_IMM), |
| 179522 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179523 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179524 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179525 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179526 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179527 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179528 | GIR_RootConstrainSelectedInstOperands, |
| 179529 | // GIR_Coverage, 3177, |
| 179530 | GIR_EraseRootFromParent_Done, |
| 179531 | // Label 8446: @564188 |
| 179532 | GIM_Reject, |
| 179533 | // Label 8436: @564189 |
| 179534 | GIM_Reject, |
| 179535 | // Label 8382: @564190 |
| 179536 | GIM_Reject, |
| 179537 | // Label 157: @564191 |
| 179538 | GIM_Try, /*On fail goto*//*Label 8447*/ GIMT_Encode4(564328), |
| 179539 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 179540 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179541 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179542 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 179543 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179544 | GIM_Try, /*On fail goto*//*Label 8448*/ GIMT_Encode4(564256), // Rule ID 2476 // |
| 179545 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179547 | // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM), |
| 179549 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179550 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179552 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179553 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179554 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179555 | GIR_RootConstrainSelectedInstOperands, |
| 179556 | // GIR_Coverage, 2476, |
| 179557 | GIR_EraseRootFromParent_Done, |
| 179558 | // Label 8448: @564256 |
| 179559 | GIM_Try, /*On fail goto*//*Label 8449*/ GIMT_Encode4(564295), // Rule ID 2474 // |
| 179560 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179561 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179562 | // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I8_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179563 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_IMM), |
| 179564 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179565 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179566 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179569 | GIR_RootConstrainSelectedInstOperands, |
| 179570 | // GIR_Coverage, 2474, |
| 179571 | GIR_EraseRootFromParent_Done, |
| 179572 | // Label 8449: @564295 |
| 179573 | GIM_Try, /*On fail goto*//*Label 8450*/ GIMT_Encode4(564327), // Rule ID 2475 // |
| 179574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179575 | // (SIsbuffer_load_byte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179576 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I8_SGPR_IMM), |
| 179577 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179578 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179579 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179580 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179581 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179582 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179583 | GIR_RootConstrainSelectedInstOperands, |
| 179584 | // GIR_Coverage, 2475, |
| 179585 | GIR_EraseRootFromParent_Done, |
| 179586 | // Label 8450: @564327 |
| 179587 | GIM_Reject, |
| 179588 | // Label 8447: @564328 |
| 179589 | GIM_Reject, |
| 179590 | // Label 158: @564329 |
| 179591 | GIM_Try, /*On fail goto*//*Label 8451*/ GIMT_Encode4(564466), |
| 179592 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 179593 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179594 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179595 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 179596 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179597 | GIM_Try, /*On fail goto*//*Label 8452*/ GIMT_Encode4(564394), // Rule ID 2502 // |
| 179598 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179600 | // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM), |
| 179602 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179603 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179605 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179606 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179607 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179608 | GIR_RootConstrainSelectedInstOperands, |
| 179609 | // GIR_Coverage, 2502, |
| 179610 | GIR_EraseRootFromParent_Done, |
| 179611 | // Label 8452: @564394 |
| 179612 | GIM_Try, /*On fail goto*//*Label 8453*/ GIMT_Encode4(564433), // Rule ID 2500 // |
| 179613 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179614 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179615 | // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I16_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179616 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_IMM), |
| 179617 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179618 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179619 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179620 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179621 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179622 | GIR_RootConstrainSelectedInstOperands, |
| 179623 | // GIR_Coverage, 2500, |
| 179624 | GIR_EraseRootFromParent_Done, |
| 179625 | // Label 8453: @564433 |
| 179626 | GIM_Try, /*On fail goto*//*Label 8454*/ GIMT_Encode4(564465), // Rule ID 2501 // |
| 179627 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179628 | // (SIsbuffer_load_short:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_I16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179629 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_I16_SGPR_IMM), |
| 179630 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179631 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179632 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179633 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179634 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179635 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179636 | GIR_RootConstrainSelectedInstOperands, |
| 179637 | // GIR_Coverage, 2501, |
| 179638 | GIR_EraseRootFromParent_Done, |
| 179639 | // Label 8454: @564465 |
| 179640 | GIM_Reject, |
| 179641 | // Label 8451: @564466 |
| 179642 | GIM_Reject, |
| 179643 | // Label 159: @564467 |
| 179644 | GIM_Try, /*On fail goto*//*Label 8455*/ GIMT_Encode4(564604), |
| 179645 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 179646 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179647 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179648 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 179649 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179650 | GIM_Try, /*On fail goto*//*Label 8456*/ GIMT_Encode4(564532), // Rule ID 2499 // |
| 179651 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179652 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179653 | // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179654 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM), |
| 179655 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179656 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179658 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179659 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179660 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179661 | GIR_RootConstrainSelectedInstOperands, |
| 179662 | // GIR_Coverage, 2499, |
| 179663 | GIR_EraseRootFromParent_Done, |
| 179664 | // Label 8456: @564532 |
| 179665 | GIM_Try, /*On fail goto*//*Label 8457*/ GIMT_Encode4(564571), // Rule ID 2497 // |
| 179666 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179667 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179668 | // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U8_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179669 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_IMM), |
| 179670 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179671 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179672 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179673 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179674 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179675 | GIR_RootConstrainSelectedInstOperands, |
| 179676 | // GIR_Coverage, 2497, |
| 179677 | GIR_EraseRootFromParent_Done, |
| 179678 | // Label 8457: @564571 |
| 179679 | GIM_Try, /*On fail goto*//*Label 8458*/ GIMT_Encode4(564603), // Rule ID 2498 // |
| 179680 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179681 | // (SIsbuffer_load_ubyte:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U8_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179682 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U8_SGPR_IMM), |
| 179683 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179684 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179685 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179686 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179687 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179688 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179689 | GIR_RootConstrainSelectedInstOperands, |
| 179690 | // GIR_Coverage, 2498, |
| 179691 | GIR_EraseRootFromParent_Done, |
| 179692 | // Label 8458: @564603 |
| 179693 | GIM_Reject, |
| 179694 | // Label 8455: @564604 |
| 179695 | GIM_Reject, |
| 179696 | // Label 160: @564605 |
| 179697 | GIM_Try, /*On fail goto*//*Label 8459*/ GIMT_Encode4(564742), |
| 179698 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s32, |
| 179699 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179700 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::SReg_32_XM0_XEXECRegClassID), |
| 179702 | GIM_CheckIsImm, /*MI*/0, /*Op*/3, |
| 179703 | GIM_Try, /*On fail goto*//*Label 8460*/ GIMT_Encode4(564670), // Rule ID 2505 // |
| 179704 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179705 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_sgpr_imm), |
| 179706 | // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferSgprImm:{ *:[i32] } i32:{ *:[i32] }:$soffset, i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179707 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM), |
| 179708 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179709 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179711 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // offset |
| 179712 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179714 | GIR_RootConstrainSelectedInstOperands, |
| 179715 | // GIR_Coverage, 2505, |
| 179716 | GIR_EraseRootFromParent_Done, |
| 179717 | // Label 8460: @564670 |
| 179718 | GIM_Try, /*On fail goto*//*Label 8461*/ GIMT_Encode4(564709), // Rule ID 2503 // |
| 179719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_smrd_buffer_imm), |
| 179721 | // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, (SMRDBufferImm:{ *:[i32] } i32:{ *:[i32] }:$offset), (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U16_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, i32imm:{ *:[i32] }:$offset, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_IMM), |
| 179723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179724 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179725 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // offset |
| 179726 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179727 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179728 | GIR_RootConstrainSelectedInstOperands, |
| 179729 | // GIR_Coverage, 2503, |
| 179730 | GIR_EraseRootFromParent_Done, |
| 179731 | // Label 8461: @564709 |
| 179732 | GIM_Try, /*On fail goto*//*Label 8462*/ GIMT_Encode4(564741), // Rule ID 2504 // |
| 179733 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX12Plus), |
| 179734 | // (SIsbuffer_load_ushort:{ *:[i32] } v4i32:{ *:[v4i32] }:$sbase, i32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$cachepolicy) => (S_BUFFER_LOAD_U16_SGPR_IMM:{ *:[i32] } SReg_128:{ *:[v4i32] }:$sbase, SReg_32:{ *:[i32] }:$soffset, 0:{ *:[i32] }, (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$cachepolicy)) |
| 179735 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::S_BUFFER_LOAD_U16_SGPR_IMM), |
| 179736 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[sdst] |
| 179737 | GIR_RootToRootCopy, /*OpIdx*/1, // sbase |
| 179738 | GIR_RootToRootCopy, /*OpIdx*/2, // soffset |
| 179739 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 179740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/3, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // cachepolicy |
| 179741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179742 | GIR_RootConstrainSelectedInstOperands, |
| 179743 | // GIR_Coverage, 2504, |
| 179744 | GIR_EraseRootFromParent_Done, |
| 179745 | // Label 8462: @564741 |
| 179746 | GIM_Reject, |
| 179747 | // Label 8459: @564742 |
| 179748 | GIM_Reject, |
| 179749 | // Label 161: @564743 |
| 179750 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 8467*/ GIMT_Encode4(570226), |
| 179751 | /*GILLT_s32*//*Label 8463*/ GIMT_Encode4(564790), GIMT_Encode4(0), GIMT_Encode4(0), |
| 179752 | /*GILLT_v2s32*//*Label 8464*/ GIMT_Encode4(566149), GIMT_Encode4(0), |
| 179753 | /*GILLT_v3s32*//*Label 8465*/ GIMT_Encode4(567508), GIMT_Encode4(0), GIMT_Encode4(0), |
| 179754 | /*GILLT_v4s32*//*Label 8466*/ GIMT_Encode4(568867), |
| 179755 | // Label 8463: @564790 |
| 179756 | GIM_Try, /*On fail goto*//*Label 8468*/ GIMT_Encode4(566148), |
| 179757 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 179758 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 179759 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 179760 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 179761 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 179762 | GIM_Try, /*On fail goto*//*Label 8469*/ GIMT_Encode4(564892), // Rule ID 6351 // |
| 179763 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 179764 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179765 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 179766 | // MIs[0] offset |
| 179767 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179768 | // MIs[0] format |
| 179769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179770 | // MIs[0] auxiliary |
| 179771 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179772 | // MIs[0] Operand 8 |
| 179773 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179775 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179776 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET), |
| 179777 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179778 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179779 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179780 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179781 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179783 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179784 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179785 | GIR_RootConstrainSelectedInstOperands, |
| 179786 | // GIR_Coverage, 6351, |
| 179787 | GIR_EraseRootFromParent_Done, |
| 179788 | // Label 8469: @564892 |
| 179789 | GIM_Try, /*On fail goto*//*Label 8470*/ GIMT_Encode4(564970), // Rule ID 6355 // |
| 179790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179791 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 179792 | // MIs[0] offset |
| 179793 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179794 | // MIs[0] format |
| 179795 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179796 | // MIs[0] auxiliary |
| 179797 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179798 | // MIs[0] Operand 8 |
| 179799 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179800 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179801 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179802 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET), |
| 179803 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179804 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179806 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179808 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179809 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179810 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179811 | GIR_RootConstrainSelectedInstOperands, |
| 179812 | // GIR_Coverage, 6355, |
| 179813 | GIR_EraseRootFromParent_Done, |
| 179814 | // Label 8470: @564970 |
| 179815 | GIM_Try, /*On fail goto*//*Label 8471*/ GIMT_Encode4(565051), // Rule ID 6383 // |
| 179816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 179817 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179818 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 179819 | // MIs[0] offset |
| 179820 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179821 | // MIs[0] format |
| 179822 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179823 | // MIs[0] auxiliary |
| 179824 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179825 | // MIs[0] Operand 8 |
| 179826 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179827 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179828 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179829 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFSET), |
| 179830 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179831 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179833 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179834 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179835 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179836 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179838 | GIR_RootConstrainSelectedInstOperands, |
| 179839 | // GIR_Coverage, 6383, |
| 179840 | GIR_EraseRootFromParent_Done, |
| 179841 | // Label 8471: @565051 |
| 179842 | GIM_Try, /*On fail goto*//*Label 8472*/ GIMT_Encode4(565129), // Rule ID 6387 // |
| 179843 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179844 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 179845 | // MIs[0] offset |
| 179846 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179847 | // MIs[0] format |
| 179848 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179849 | // MIs[0] auxiliary |
| 179850 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179851 | // MIs[0] Operand 8 |
| 179852 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179854 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET:{ *:[f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFSET), |
| 179856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179857 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179858 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179859 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179860 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179861 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179863 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179864 | GIR_RootConstrainSelectedInstOperands, |
| 179865 | // GIR_Coverage, 6387, |
| 179866 | GIR_EraseRootFromParent_Done, |
| 179867 | // Label 8472: @565129 |
| 179868 | GIM_Try, /*On fail goto*//*Label 8473*/ GIMT_Encode4(565208), // Rule ID 6353 // |
| 179869 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 179870 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179871 | // MIs[0] offset |
| 179872 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179873 | // MIs[0] format |
| 179874 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179875 | // MIs[0] auxiliary |
| 179876 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179877 | // MIs[0] Operand 8 |
| 179878 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179879 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179880 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179881 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN), |
| 179882 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179883 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 179884 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179885 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179886 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179887 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179888 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179890 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179891 | GIR_RootConstrainSelectedInstOperands, |
| 179892 | // GIR_Coverage, 6353, |
| 179893 | GIR_EraseRootFromParent_Done, |
| 179894 | // Label 8473: @565208 |
| 179895 | GIM_Try, /*On fail goto*//*Label 8474*/ GIMT_Encode4(565284), // Rule ID 6357 // |
| 179896 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179897 | // MIs[0] offset |
| 179898 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179899 | // MIs[0] format |
| 179900 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179901 | // MIs[0] auxiliary |
| 179902 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179903 | // MIs[0] Operand 8 |
| 179904 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179905 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179906 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179907 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN), |
| 179908 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179909 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 179910 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179911 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179912 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179913 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179914 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179915 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179916 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179917 | GIR_RootConstrainSelectedInstOperands, |
| 179918 | // GIR_Coverage, 6357, |
| 179919 | GIR_EraseRootFromParent_Done, |
| 179920 | // Label 8474: @565284 |
| 179921 | GIM_Try, /*On fail goto*//*Label 8475*/ GIMT_Encode4(565363), // Rule ID 6385 // |
| 179922 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 179923 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179924 | // MIs[0] offset |
| 179925 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179926 | // MIs[0] format |
| 179927 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179928 | // MIs[0] auxiliary |
| 179929 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179930 | // MIs[0] Operand 8 |
| 179931 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179932 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179933 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179934 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_OFFEN), |
| 179935 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179936 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 179937 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179938 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179939 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179940 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179941 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179942 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179943 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179944 | GIR_RootConstrainSelectedInstOperands, |
| 179945 | // GIR_Coverage, 6385, |
| 179946 | GIR_EraseRootFromParent_Done, |
| 179947 | // Label 8475: @565363 |
| 179948 | GIM_Try, /*On fail goto*//*Label 8476*/ GIMT_Encode4(565439), // Rule ID 6389 // |
| 179949 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 179950 | // MIs[0] offset |
| 179951 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179952 | // MIs[0] format |
| 179953 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179954 | // MIs[0] auxiliary |
| 179955 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179956 | // MIs[0] Operand 8 |
| 179957 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 179958 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179959 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179960 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_OFFEN), |
| 179961 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179962 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 179963 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179964 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179965 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179966 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179967 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179968 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179969 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179970 | GIR_RootConstrainSelectedInstOperands, |
| 179971 | // GIR_Coverage, 6389, |
| 179972 | GIR_EraseRootFromParent_Done, |
| 179973 | // Label 8476: @565439 |
| 179974 | GIM_Try, /*On fail goto*//*Label 8477*/ GIMT_Encode4(565510), // Rule ID 6352 // |
| 179975 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 179976 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 179977 | // MIs[0] offset |
| 179978 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 179979 | // MIs[0] format |
| 179980 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 179981 | // MIs[0] auxiliary |
| 179982 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 179983 | // MIs[0] Operand 8 |
| 179984 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 179985 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 179986 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 179987 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN), |
| 179988 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 179989 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 179990 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 179991 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 179992 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 179993 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 179994 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 179995 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 179996 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 179997 | GIR_RootConstrainSelectedInstOperands, |
| 179998 | // GIR_Coverage, 6352, |
| 179999 | GIR_EraseRootFromParent_Done, |
| 180000 | // Label 8477: @565510 |
| 180001 | GIM_Try, /*On fail goto*//*Label 8478*/ GIMT_Encode4(565578), // Rule ID 6356 // |
| 180002 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180003 | // MIs[0] offset |
| 180004 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180005 | // MIs[0] format |
| 180006 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180007 | // MIs[0] auxiliary |
| 180008 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180009 | // MIs[0] Operand 8 |
| 180010 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180012 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN), |
| 180014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180015 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180016 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180017 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180018 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180019 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180020 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180021 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180022 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180023 | GIR_RootConstrainSelectedInstOperands, |
| 180024 | // GIR_Coverage, 6356, |
| 180025 | GIR_EraseRootFromParent_Done, |
| 180026 | // Label 8478: @565578 |
| 180027 | GIM_Try, /*On fail goto*//*Label 8479*/ GIMT_Encode4(565649), // Rule ID 6384 // |
| 180028 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180029 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180030 | // MIs[0] offset |
| 180031 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180032 | // MIs[0] format |
| 180033 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180034 | // MIs[0] auxiliary |
| 180035 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180036 | // MIs[0] Operand 8 |
| 180037 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180038 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180039 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180040 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_IDXEN), |
| 180041 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180042 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180043 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180044 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180045 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180046 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180047 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180048 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180049 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180050 | GIR_RootConstrainSelectedInstOperands, |
| 180051 | // GIR_Coverage, 6384, |
| 180052 | GIR_EraseRootFromParent_Done, |
| 180053 | // Label 8479: @565649 |
| 180054 | GIM_Try, /*On fail goto*//*Label 8480*/ GIMT_Encode4(565717), // Rule ID 6388 // |
| 180055 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180056 | // MIs[0] offset |
| 180057 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180058 | // MIs[0] format |
| 180059 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180060 | // MIs[0] auxiliary |
| 180061 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180062 | // MIs[0] Operand 8 |
| 180063 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180064 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180065 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN:{ *:[f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180066 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_IDXEN), |
| 180067 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180068 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180069 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180070 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180071 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180072 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180073 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180074 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180075 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180076 | GIR_RootConstrainSelectedInstOperands, |
| 180077 | // GIR_Coverage, 6388, |
| 180078 | GIR_EraseRootFromParent_Done, |
| 180079 | // Label 8480: @565717 |
| 180080 | GIM_Try, /*On fail goto*//*Label 8481*/ GIMT_Encode4(565826), // Rule ID 6354 // |
| 180081 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180082 | // MIs[0] offset |
| 180083 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180084 | // MIs[0] format |
| 180085 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180086 | // MIs[0] auxiliary |
| 180087 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180088 | // MIs[0] Operand 8 |
| 180089 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180090 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180091 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180092 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180093 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180094 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180095 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180096 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180097 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180098 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180099 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180100 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180101 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180102 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN), |
| 180103 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180104 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180105 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180106 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180107 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180108 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180109 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180110 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180111 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180112 | GIR_RootConstrainSelectedInstOperands, |
| 180113 | // GIR_Coverage, 6354, |
| 180114 | GIR_EraseRootFromParent_Done, |
| 180115 | // Label 8481: @565826 |
| 180116 | GIM_Try, /*On fail goto*//*Label 8482*/ GIMT_Encode4(565932), // Rule ID 6358 // |
| 180117 | // MIs[0] offset |
| 180118 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180119 | // MIs[0] format |
| 180120 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180121 | // MIs[0] auxiliary |
| 180122 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180123 | // MIs[0] Operand 8 |
| 180124 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180125 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180126 | // (SItbuffer_load:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180127 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180128 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180129 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180130 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180131 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180132 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180133 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180134 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180135 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180136 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180137 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN), |
| 180138 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180139 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180140 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180141 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180142 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180143 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180144 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180145 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180146 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180147 | GIR_RootConstrainSelectedInstOperands, |
| 180148 | // GIR_Coverage, 6358, |
| 180149 | GIR_EraseRootFromParent_Done, |
| 180150 | // Label 8482: @565932 |
| 180151 | GIM_Try, /*On fail goto*//*Label 8483*/ GIMT_Encode4(566041), // Rule ID 6386 // |
| 180152 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180153 | // MIs[0] offset |
| 180154 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180155 | // MIs[0] format |
| 180156 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180157 | // MIs[0] auxiliary |
| 180158 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180159 | // MIs[0] Operand 8 |
| 180160 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180161 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180162 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180163 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180164 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180165 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180166 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180167 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180168 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180169 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180170 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180171 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180172 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180173 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_BOTHEN), |
| 180174 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180175 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180176 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180177 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180178 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180182 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180183 | GIR_RootConstrainSelectedInstOperands, |
| 180184 | // GIR_Coverage, 6386, |
| 180185 | GIR_EraseRootFromParent_Done, |
| 180186 | // Label 8483: @566041 |
| 180187 | GIM_Try, /*On fail goto*//*Label 8484*/ GIMT_Encode4(566147), // Rule ID 6390 // |
| 180188 | // MIs[0] offset |
| 180189 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180190 | // MIs[0] format |
| 180191 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180192 | // MIs[0] auxiliary |
| 180193 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180194 | // MIs[0] Operand 8 |
| 180195 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180196 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180197 | // (SItbuffer_load:{ *:[f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN:{ *:[f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180198 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180199 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180200 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180201 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180202 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180203 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180204 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180205 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180206 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180207 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180208 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_X_VBUFFER_BOTHEN), |
| 180209 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180210 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180211 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180212 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180213 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180214 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180216 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180217 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180218 | GIR_RootConstrainSelectedInstOperands, |
| 180219 | // GIR_Coverage, 6390, |
| 180220 | GIR_EraseRootFromParent_Done, |
| 180221 | // Label 8484: @566147 |
| 180222 | GIM_Reject, |
| 180223 | // Label 8468: @566148 |
| 180224 | GIM_Reject, |
| 180225 | // Label 8464: @566149 |
| 180226 | GIM_Try, /*On fail goto*//*Label 8485*/ GIMT_Encode4(567507), |
| 180227 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 180228 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 180229 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 180230 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 180231 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 180232 | GIM_Try, /*On fail goto*//*Label 8486*/ GIMT_Encode4(566251), // Rule ID 6359 // |
| 180233 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180234 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180235 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180236 | // MIs[0] offset |
| 180237 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180238 | // MIs[0] format |
| 180239 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180240 | // MIs[0] auxiliary |
| 180241 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180242 | // MIs[0] Operand 8 |
| 180243 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180244 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180245 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180246 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET), |
| 180247 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180248 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180249 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180250 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180252 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180253 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180254 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180255 | GIR_RootConstrainSelectedInstOperands, |
| 180256 | // GIR_Coverage, 6359, |
| 180257 | GIR_EraseRootFromParent_Done, |
| 180258 | // Label 8486: @566251 |
| 180259 | GIM_Try, /*On fail goto*//*Label 8487*/ GIMT_Encode4(566329), // Rule ID 6363 // |
| 180260 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180261 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180262 | // MIs[0] offset |
| 180263 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180264 | // MIs[0] format |
| 180265 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180266 | // MIs[0] auxiliary |
| 180267 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180268 | // MIs[0] Operand 8 |
| 180269 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180270 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180271 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180272 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET), |
| 180273 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180274 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180275 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180276 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180277 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180278 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180279 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180280 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180281 | GIR_RootConstrainSelectedInstOperands, |
| 180282 | // GIR_Coverage, 6363, |
| 180283 | GIR_EraseRootFromParent_Done, |
| 180284 | // Label 8487: @566329 |
| 180285 | GIM_Try, /*On fail goto*//*Label 8488*/ GIMT_Encode4(566410), // Rule ID 6391 // |
| 180286 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180287 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180288 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180289 | // MIs[0] offset |
| 180290 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180291 | // MIs[0] format |
| 180292 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180293 | // MIs[0] auxiliary |
| 180294 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180295 | // MIs[0] Operand 8 |
| 180296 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180297 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180298 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFSET), |
| 180300 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180301 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180302 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180303 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180304 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180306 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180307 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180308 | GIR_RootConstrainSelectedInstOperands, |
| 180309 | // GIR_Coverage, 6391, |
| 180310 | GIR_EraseRootFromParent_Done, |
| 180311 | // Label 8488: @566410 |
| 180312 | GIM_Try, /*On fail goto*//*Label 8489*/ GIMT_Encode4(566488), // Rule ID 6395 // |
| 180313 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180314 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180315 | // MIs[0] offset |
| 180316 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180317 | // MIs[0] format |
| 180318 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180319 | // MIs[0] auxiliary |
| 180320 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180321 | // MIs[0] Operand 8 |
| 180322 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180324 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET:{ *:[v2f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180325 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFSET), |
| 180326 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180327 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180328 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180329 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180330 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180331 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180332 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180333 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180334 | GIR_RootConstrainSelectedInstOperands, |
| 180335 | // GIR_Coverage, 6395, |
| 180336 | GIR_EraseRootFromParent_Done, |
| 180337 | // Label 8489: @566488 |
| 180338 | GIM_Try, /*On fail goto*//*Label 8490*/ GIMT_Encode4(566567), // Rule ID 6361 // |
| 180339 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180340 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180341 | // MIs[0] offset |
| 180342 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180343 | // MIs[0] format |
| 180344 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180345 | // MIs[0] auxiliary |
| 180346 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180347 | // MIs[0] Operand 8 |
| 180348 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180350 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN), |
| 180352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180353 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180354 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180356 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180357 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180358 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180360 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180361 | GIR_RootConstrainSelectedInstOperands, |
| 180362 | // GIR_Coverage, 6361, |
| 180363 | GIR_EraseRootFromParent_Done, |
| 180364 | // Label 8490: @566567 |
| 180365 | GIM_Try, /*On fail goto*//*Label 8491*/ GIMT_Encode4(566643), // Rule ID 6365 // |
| 180366 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180367 | // MIs[0] offset |
| 180368 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180369 | // MIs[0] format |
| 180370 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180371 | // MIs[0] auxiliary |
| 180372 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180373 | // MIs[0] Operand 8 |
| 180374 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180375 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180376 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180377 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN), |
| 180378 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180379 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180380 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180381 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180382 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180383 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180384 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180385 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180386 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180387 | GIR_RootConstrainSelectedInstOperands, |
| 180388 | // GIR_Coverage, 6365, |
| 180389 | GIR_EraseRootFromParent_Done, |
| 180390 | // Label 8491: @566643 |
| 180391 | GIM_Try, /*On fail goto*//*Label 8492*/ GIMT_Encode4(566722), // Rule ID 6393 // |
| 180392 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180393 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180394 | // MIs[0] offset |
| 180395 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180396 | // MIs[0] format |
| 180397 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180398 | // MIs[0] auxiliary |
| 180399 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180400 | // MIs[0] Operand 8 |
| 180401 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180402 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180403 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180404 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_OFFEN), |
| 180405 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180406 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180407 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180408 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180409 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180410 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180411 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180412 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180413 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180414 | GIR_RootConstrainSelectedInstOperands, |
| 180415 | // GIR_Coverage, 6393, |
| 180416 | GIR_EraseRootFromParent_Done, |
| 180417 | // Label 8492: @566722 |
| 180418 | GIM_Try, /*On fail goto*//*Label 8493*/ GIMT_Encode4(566798), // Rule ID 6397 // |
| 180419 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180420 | // MIs[0] offset |
| 180421 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180422 | // MIs[0] format |
| 180423 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180424 | // MIs[0] auxiliary |
| 180425 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180426 | // MIs[0] Operand 8 |
| 180427 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180428 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180429 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180430 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_OFFEN), |
| 180431 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180432 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180433 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180434 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180435 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180436 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180437 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180438 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180439 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180440 | GIR_RootConstrainSelectedInstOperands, |
| 180441 | // GIR_Coverage, 6397, |
| 180442 | GIR_EraseRootFromParent_Done, |
| 180443 | // Label 8493: @566798 |
| 180444 | GIM_Try, /*On fail goto*//*Label 8494*/ GIMT_Encode4(566869), // Rule ID 6360 // |
| 180445 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180446 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180447 | // MIs[0] offset |
| 180448 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180449 | // MIs[0] format |
| 180450 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180451 | // MIs[0] auxiliary |
| 180452 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180453 | // MIs[0] Operand 8 |
| 180454 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180455 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180456 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180457 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN), |
| 180458 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180459 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180460 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180461 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180462 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180463 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180464 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180465 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180466 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180467 | GIR_RootConstrainSelectedInstOperands, |
| 180468 | // GIR_Coverage, 6360, |
| 180469 | GIR_EraseRootFromParent_Done, |
| 180470 | // Label 8494: @566869 |
| 180471 | GIM_Try, /*On fail goto*//*Label 8495*/ GIMT_Encode4(566937), // Rule ID 6364 // |
| 180472 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180473 | // MIs[0] offset |
| 180474 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180475 | // MIs[0] format |
| 180476 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180477 | // MIs[0] auxiliary |
| 180478 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180479 | // MIs[0] Operand 8 |
| 180480 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180481 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180482 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180483 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN), |
| 180484 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180485 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180486 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180487 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180488 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180489 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180490 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180491 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180492 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180493 | GIR_RootConstrainSelectedInstOperands, |
| 180494 | // GIR_Coverage, 6364, |
| 180495 | GIR_EraseRootFromParent_Done, |
| 180496 | // Label 8495: @566937 |
| 180497 | GIM_Try, /*On fail goto*//*Label 8496*/ GIMT_Encode4(567008), // Rule ID 6392 // |
| 180498 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180499 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180500 | // MIs[0] offset |
| 180501 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180502 | // MIs[0] format |
| 180503 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180504 | // MIs[0] auxiliary |
| 180505 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180506 | // MIs[0] Operand 8 |
| 180507 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180508 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180509 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180510 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_IDXEN), |
| 180511 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180512 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180513 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180514 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180515 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180516 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180517 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180518 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180519 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180520 | GIR_RootConstrainSelectedInstOperands, |
| 180521 | // GIR_Coverage, 6392, |
| 180522 | GIR_EraseRootFromParent_Done, |
| 180523 | // Label 8496: @567008 |
| 180524 | GIM_Try, /*On fail goto*//*Label 8497*/ GIMT_Encode4(567076), // Rule ID 6396 // |
| 180525 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180526 | // MIs[0] offset |
| 180527 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180528 | // MIs[0] format |
| 180529 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180530 | // MIs[0] auxiliary |
| 180531 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180532 | // MIs[0] Operand 8 |
| 180533 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180534 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180535 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN:{ *:[v2f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180536 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_IDXEN), |
| 180537 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180538 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180539 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180540 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180541 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180542 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180543 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180545 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180546 | GIR_RootConstrainSelectedInstOperands, |
| 180547 | // GIR_Coverage, 6396, |
| 180548 | GIR_EraseRootFromParent_Done, |
| 180549 | // Label 8497: @567076 |
| 180550 | GIM_Try, /*On fail goto*//*Label 8498*/ GIMT_Encode4(567185), // Rule ID 6362 // |
| 180551 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180552 | // MIs[0] offset |
| 180553 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180554 | // MIs[0] format |
| 180555 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180556 | // MIs[0] auxiliary |
| 180557 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180558 | // MIs[0] Operand 8 |
| 180559 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180560 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180561 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180562 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180563 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180564 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180565 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180566 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180567 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180568 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180569 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180570 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180571 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180572 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN), |
| 180573 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180574 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180575 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180576 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180577 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180578 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180579 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180580 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180581 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180582 | GIR_RootConstrainSelectedInstOperands, |
| 180583 | // GIR_Coverage, 6362, |
| 180584 | GIR_EraseRootFromParent_Done, |
| 180585 | // Label 8498: @567185 |
| 180586 | GIM_Try, /*On fail goto*//*Label 8499*/ GIMT_Encode4(567291), // Rule ID 6366 // |
| 180587 | // MIs[0] offset |
| 180588 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180589 | // MIs[0] format |
| 180590 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180591 | // MIs[0] auxiliary |
| 180592 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180593 | // MIs[0] Operand 8 |
| 180594 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180596 | // (SItbuffer_load:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180597 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180598 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180599 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180600 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180601 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180602 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180603 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180604 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180605 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180606 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180607 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN), |
| 180608 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180609 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180610 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180611 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180612 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180613 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180614 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180615 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180616 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180617 | GIR_RootConstrainSelectedInstOperands, |
| 180618 | // GIR_Coverage, 6366, |
| 180619 | GIR_EraseRootFromParent_Done, |
| 180620 | // Label 8499: @567291 |
| 180621 | GIM_Try, /*On fail goto*//*Label 8500*/ GIMT_Encode4(567400), // Rule ID 6394 // |
| 180622 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180623 | // MIs[0] offset |
| 180624 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180625 | // MIs[0] format |
| 180626 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180627 | // MIs[0] auxiliary |
| 180628 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180629 | // MIs[0] Operand 8 |
| 180630 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180632 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180633 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180634 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180635 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180636 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180637 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180638 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180639 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180640 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180641 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180642 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180643 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_BOTHEN), |
| 180644 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180645 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180646 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180647 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180648 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180649 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180650 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180651 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180652 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180653 | GIR_RootConstrainSelectedInstOperands, |
| 180654 | // GIR_Coverage, 6394, |
| 180655 | GIR_EraseRootFromParent_Done, |
| 180656 | // Label 8500: @567400 |
| 180657 | GIM_Try, /*On fail goto*//*Label 8501*/ GIMT_Encode4(567506), // Rule ID 6398 // |
| 180658 | // MIs[0] offset |
| 180659 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180660 | // MIs[0] format |
| 180661 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180662 | // MIs[0] auxiliary |
| 180663 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180664 | // MIs[0] Operand 8 |
| 180665 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180666 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180667 | // (SItbuffer_load:{ *:[v2f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN:{ *:[v2f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180668 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 180669 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 180670 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 180671 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 180672 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 180673 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 180674 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 180675 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 180676 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180677 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 180678 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XY_VBUFFER_BOTHEN), |
| 180679 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180680 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 180681 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180682 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180683 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180684 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180685 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180686 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180687 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180688 | GIR_RootConstrainSelectedInstOperands, |
| 180689 | // GIR_Coverage, 6398, |
| 180690 | GIR_EraseRootFromParent_Done, |
| 180691 | // Label 8501: @567506 |
| 180692 | GIM_Reject, |
| 180693 | // Label 8485: @567507 |
| 180694 | GIM_Reject, |
| 180695 | // Label 8465: @567508 |
| 180696 | GIM_Try, /*On fail goto*//*Label 8502*/ GIMT_Encode4(568866), |
| 180697 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 180698 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 180699 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 180700 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 180701 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 180702 | GIM_Try, /*On fail goto*//*Label 8503*/ GIMT_Encode4(567610), // Rule ID 6367 // |
| 180703 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180704 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180705 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180706 | // MIs[0] offset |
| 180707 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180708 | // MIs[0] format |
| 180709 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180710 | // MIs[0] auxiliary |
| 180711 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180712 | // MIs[0] Operand 8 |
| 180713 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180714 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180715 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180716 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET), |
| 180717 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180718 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180719 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180720 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180721 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180722 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180723 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180724 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180725 | GIR_RootConstrainSelectedInstOperands, |
| 180726 | // GIR_Coverage, 6367, |
| 180727 | GIR_EraseRootFromParent_Done, |
| 180728 | // Label 8503: @567610 |
| 180729 | GIM_Try, /*On fail goto*//*Label 8504*/ GIMT_Encode4(567688), // Rule ID 6371 // |
| 180730 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180731 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180732 | // MIs[0] offset |
| 180733 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180734 | // MIs[0] format |
| 180735 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180736 | // MIs[0] auxiliary |
| 180737 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180738 | // MIs[0] Operand 8 |
| 180739 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180740 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180741 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180742 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET), |
| 180743 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180744 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180745 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180746 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180747 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180748 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180749 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180750 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180751 | GIR_RootConstrainSelectedInstOperands, |
| 180752 | // GIR_Coverage, 6371, |
| 180753 | GIR_EraseRootFromParent_Done, |
| 180754 | // Label 8504: @567688 |
| 180755 | GIM_Try, /*On fail goto*//*Label 8505*/ GIMT_Encode4(567769), // Rule ID 6399 // |
| 180756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180758 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180759 | // MIs[0] offset |
| 180760 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180761 | // MIs[0] format |
| 180762 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180763 | // MIs[0] auxiliary |
| 180764 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180765 | // MIs[0] Operand 8 |
| 180766 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180767 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180768 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFSET), |
| 180770 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180771 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180773 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180775 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180776 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180778 | GIR_RootConstrainSelectedInstOperands, |
| 180779 | // GIR_Coverage, 6399, |
| 180780 | GIR_EraseRootFromParent_Done, |
| 180781 | // Label 8505: @567769 |
| 180782 | GIM_Try, /*On fail goto*//*Label 8506*/ GIMT_Encode4(567847), // Rule ID 6403 // |
| 180783 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180784 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180785 | // MIs[0] offset |
| 180786 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180787 | // MIs[0] format |
| 180788 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180789 | // MIs[0] auxiliary |
| 180790 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180791 | // MIs[0] Operand 8 |
| 180792 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180793 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180794 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET:{ *:[v3f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180795 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFSET), |
| 180796 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180797 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180799 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180800 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180802 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180803 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180804 | GIR_RootConstrainSelectedInstOperands, |
| 180805 | // GIR_Coverage, 6403, |
| 180806 | GIR_EraseRootFromParent_Done, |
| 180807 | // Label 8506: @567847 |
| 180808 | GIM_Try, /*On fail goto*//*Label 8507*/ GIMT_Encode4(567926), // Rule ID 6369 // |
| 180809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180810 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180811 | // MIs[0] offset |
| 180812 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180813 | // MIs[0] format |
| 180814 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180815 | // MIs[0] auxiliary |
| 180816 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180817 | // MIs[0] Operand 8 |
| 180818 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180819 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180820 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN), |
| 180822 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180823 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180824 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180826 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180827 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180831 | GIR_RootConstrainSelectedInstOperands, |
| 180832 | // GIR_Coverage, 6369, |
| 180833 | GIR_EraseRootFromParent_Done, |
| 180834 | // Label 8507: @567926 |
| 180835 | GIM_Try, /*On fail goto*//*Label 8508*/ GIMT_Encode4(568002), // Rule ID 6373 // |
| 180836 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180837 | // MIs[0] offset |
| 180838 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180839 | // MIs[0] format |
| 180840 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180841 | // MIs[0] auxiliary |
| 180842 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180843 | // MIs[0] Operand 8 |
| 180844 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180845 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180846 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180847 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN), |
| 180848 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180849 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180850 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180851 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180852 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180853 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180856 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180857 | GIR_RootConstrainSelectedInstOperands, |
| 180858 | // GIR_Coverage, 6373, |
| 180859 | GIR_EraseRootFromParent_Done, |
| 180860 | // Label 8508: @568002 |
| 180861 | GIM_Try, /*On fail goto*//*Label 8509*/ GIMT_Encode4(568081), // Rule ID 6401 // |
| 180862 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180863 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180864 | // MIs[0] offset |
| 180865 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180866 | // MIs[0] format |
| 180867 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180868 | // MIs[0] auxiliary |
| 180869 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180870 | // MIs[0] Operand 8 |
| 180871 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180872 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180873 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180874 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_OFFEN), |
| 180875 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180876 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180877 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180878 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180879 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180880 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180881 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180882 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180883 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180884 | GIR_RootConstrainSelectedInstOperands, |
| 180885 | // GIR_Coverage, 6401, |
| 180886 | GIR_EraseRootFromParent_Done, |
| 180887 | // Label 8509: @568081 |
| 180888 | GIM_Try, /*On fail goto*//*Label 8510*/ GIMT_Encode4(568157), // Rule ID 6405 // |
| 180889 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 180890 | // MIs[0] offset |
| 180891 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180892 | // MIs[0] format |
| 180893 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180894 | // MIs[0] auxiliary |
| 180895 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180896 | // MIs[0] Operand 8 |
| 180897 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 180898 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180899 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180900 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_OFFEN), |
| 180901 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180902 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 180903 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180904 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180905 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180906 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180907 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180908 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180909 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180910 | GIR_RootConstrainSelectedInstOperands, |
| 180911 | // GIR_Coverage, 6405, |
| 180912 | GIR_EraseRootFromParent_Done, |
| 180913 | // Label 8510: @568157 |
| 180914 | GIM_Try, /*On fail goto*//*Label 8511*/ GIMT_Encode4(568228), // Rule ID 6368 // |
| 180915 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180916 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180917 | // MIs[0] offset |
| 180918 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180919 | // MIs[0] format |
| 180920 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180921 | // MIs[0] auxiliary |
| 180922 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180923 | // MIs[0] Operand 8 |
| 180924 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180925 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180926 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180927 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN), |
| 180928 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180929 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180930 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180931 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180932 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180933 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180934 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180935 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180936 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180937 | GIR_RootConstrainSelectedInstOperands, |
| 180938 | // GIR_Coverage, 6368, |
| 180939 | GIR_EraseRootFromParent_Done, |
| 180940 | // Label 8511: @568228 |
| 180941 | GIM_Try, /*On fail goto*//*Label 8512*/ GIMT_Encode4(568296), // Rule ID 6372 // |
| 180942 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180943 | // MIs[0] offset |
| 180944 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180945 | // MIs[0] format |
| 180946 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180947 | // MIs[0] auxiliary |
| 180948 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180949 | // MIs[0] Operand 8 |
| 180950 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180951 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180952 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180953 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN), |
| 180954 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180955 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180956 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180957 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180958 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180959 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180962 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180963 | GIR_RootConstrainSelectedInstOperands, |
| 180964 | // GIR_Coverage, 6372, |
| 180965 | GIR_EraseRootFromParent_Done, |
| 180966 | // Label 8512: @568296 |
| 180967 | GIM_Try, /*On fail goto*//*Label 8513*/ GIMT_Encode4(568367), // Rule ID 6400 // |
| 180968 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 180969 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180970 | // MIs[0] offset |
| 180971 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180972 | // MIs[0] format |
| 180973 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 180974 | // MIs[0] auxiliary |
| 180975 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 180976 | // MIs[0] Operand 8 |
| 180977 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 180978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 180979 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 180980 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_IDXEN), |
| 180981 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 180982 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 180983 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 180984 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 180985 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 180986 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 180987 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 180988 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 180989 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 180990 | GIR_RootConstrainSelectedInstOperands, |
| 180991 | // GIR_Coverage, 6400, |
| 180992 | GIR_EraseRootFromParent_Done, |
| 180993 | // Label 8513: @568367 |
| 180994 | GIM_Try, /*On fail goto*//*Label 8514*/ GIMT_Encode4(568435), // Rule ID 6404 // |
| 180995 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 180996 | // MIs[0] offset |
| 180997 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 180998 | // MIs[0] format |
| 180999 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181000 | // MIs[0] auxiliary |
| 181001 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181002 | // MIs[0] Operand 8 |
| 181003 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181004 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181005 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN:{ *:[v3f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181006 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_IDXEN), |
| 181007 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181008 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181009 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181010 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181011 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181012 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181013 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181015 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181016 | GIR_RootConstrainSelectedInstOperands, |
| 181017 | // GIR_Coverage, 6404, |
| 181018 | GIR_EraseRootFromParent_Done, |
| 181019 | // Label 8514: @568435 |
| 181020 | GIM_Try, /*On fail goto*//*Label 8515*/ GIMT_Encode4(568544), // Rule ID 6370 // |
| 181021 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181022 | // MIs[0] offset |
| 181023 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181024 | // MIs[0] format |
| 181025 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181026 | // MIs[0] auxiliary |
| 181027 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181028 | // MIs[0] Operand 8 |
| 181029 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181030 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181031 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181032 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181033 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181034 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181035 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181036 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181037 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181038 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181039 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181040 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181041 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181042 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN), |
| 181043 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181044 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181045 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181046 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181047 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181048 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181049 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181050 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181051 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181052 | GIR_RootConstrainSelectedInstOperands, |
| 181053 | // GIR_Coverage, 6370, |
| 181054 | GIR_EraseRootFromParent_Done, |
| 181055 | // Label 8515: @568544 |
| 181056 | GIM_Try, /*On fail goto*//*Label 8516*/ GIMT_Encode4(568650), // Rule ID 6374 // |
| 181057 | // MIs[0] offset |
| 181058 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181059 | // MIs[0] format |
| 181060 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181061 | // MIs[0] auxiliary |
| 181062 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181063 | // MIs[0] Operand 8 |
| 181064 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181065 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181066 | // (SItbuffer_load:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181067 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181068 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181069 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181070 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181071 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181072 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181073 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181074 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181075 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181076 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181077 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN), |
| 181078 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181079 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181080 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181081 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181082 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181083 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181084 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181085 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181086 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181087 | GIR_RootConstrainSelectedInstOperands, |
| 181088 | // GIR_Coverage, 6374, |
| 181089 | GIR_EraseRootFromParent_Done, |
| 181090 | // Label 8516: @568650 |
| 181091 | GIM_Try, /*On fail goto*//*Label 8517*/ GIMT_Encode4(568759), // Rule ID 6402 // |
| 181092 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181093 | // MIs[0] offset |
| 181094 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181095 | // MIs[0] format |
| 181096 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181097 | // MIs[0] auxiliary |
| 181098 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181099 | // MIs[0] Operand 8 |
| 181100 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181101 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181102 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181103 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181104 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181105 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181106 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181107 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181108 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181109 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181110 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181111 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181112 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_BOTHEN), |
| 181114 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181115 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181116 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181118 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181119 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181120 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181121 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181123 | GIR_RootConstrainSelectedInstOperands, |
| 181124 | // GIR_Coverage, 6402, |
| 181125 | GIR_EraseRootFromParent_Done, |
| 181126 | // Label 8517: @568759 |
| 181127 | GIM_Try, /*On fail goto*//*Label 8518*/ GIMT_Encode4(568865), // Rule ID 6406 // |
| 181128 | // MIs[0] offset |
| 181129 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181130 | // MIs[0] format |
| 181131 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181132 | // MIs[0] auxiliary |
| 181133 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181134 | // MIs[0] Operand 8 |
| 181135 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181136 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181137 | // (SItbuffer_load:{ *:[v3f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN:{ *:[v3f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181138 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181139 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181140 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181141 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181142 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181143 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181144 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181145 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181146 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181147 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181148 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZ_VBUFFER_BOTHEN), |
| 181149 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181150 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181151 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181152 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181153 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181154 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181155 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181157 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181158 | GIR_RootConstrainSelectedInstOperands, |
| 181159 | // GIR_Coverage, 6406, |
| 181160 | GIR_EraseRootFromParent_Done, |
| 181161 | // Label 8518: @568865 |
| 181162 | GIM_Reject, |
| 181163 | // Label 8502: @568866 |
| 181164 | GIM_Reject, |
| 181165 | // Label 8466: @568867 |
| 181166 | GIM_Try, /*On fail goto*//*Label 8519*/ GIMT_Encode4(570225), |
| 181167 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 181168 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 181169 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 181170 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 181171 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 181172 | GIM_Try, /*On fail goto*//*Label 8520*/ GIMT_Encode4(568969), // Rule ID 6375 // |
| 181173 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181174 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181175 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181176 | // MIs[0] offset |
| 181177 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181178 | // MIs[0] format |
| 181179 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181180 | // MIs[0] auxiliary |
| 181181 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181182 | // MIs[0] Operand 8 |
| 181183 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181184 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181185 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181186 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET), |
| 181187 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181188 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181189 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181190 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181191 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181192 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181193 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181194 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181195 | GIR_RootConstrainSelectedInstOperands, |
| 181196 | // GIR_Coverage, 6375, |
| 181197 | GIR_EraseRootFromParent_Done, |
| 181198 | // Label 8520: @568969 |
| 181199 | GIM_Try, /*On fail goto*//*Label 8521*/ GIMT_Encode4(569047), // Rule ID 6379 // |
| 181200 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181201 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181202 | // MIs[0] offset |
| 181203 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181204 | // MIs[0] format |
| 181205 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181206 | // MIs[0] auxiliary |
| 181207 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181208 | // MIs[0] Operand 8 |
| 181209 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181210 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181211 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181212 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET), |
| 181213 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181214 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181215 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181216 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181217 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181218 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181219 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181220 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181221 | GIR_RootConstrainSelectedInstOperands, |
| 181222 | // GIR_Coverage, 6379, |
| 181223 | GIR_EraseRootFromParent_Done, |
| 181224 | // Label 8521: @569047 |
| 181225 | GIM_Try, /*On fail goto*//*Label 8522*/ GIMT_Encode4(569128), // Rule ID 6407 // |
| 181226 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181227 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181228 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181229 | // MIs[0] offset |
| 181230 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181231 | // MIs[0] format |
| 181232 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181233 | // MIs[0] auxiliary |
| 181234 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181235 | // MIs[0] Operand 8 |
| 181236 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181237 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181238 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181239 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFSET), |
| 181240 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181241 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181243 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181244 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181245 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181248 | GIR_RootConstrainSelectedInstOperands, |
| 181249 | // GIR_Coverage, 6407, |
| 181250 | GIR_EraseRootFromParent_Done, |
| 181251 | // Label 8522: @569128 |
| 181252 | GIM_Try, /*On fail goto*//*Label 8523*/ GIMT_Encode4(569206), // Rule ID 6411 // |
| 181253 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181254 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181255 | // MIs[0] offset |
| 181256 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181257 | // MIs[0] format |
| 181258 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181259 | // MIs[0] auxiliary |
| 181260 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181261 | // MIs[0] Operand 8 |
| 181262 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181263 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181264 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET:{ *:[v4f32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181265 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFSET), |
| 181266 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181267 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181268 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181269 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181270 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181272 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181273 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181274 | GIR_RootConstrainSelectedInstOperands, |
| 181275 | // GIR_Coverage, 6411, |
| 181276 | GIR_EraseRootFromParent_Done, |
| 181277 | // Label 8523: @569206 |
| 181278 | GIM_Try, /*On fail goto*//*Label 8524*/ GIMT_Encode4(569285), // Rule ID 6377 // |
| 181279 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181280 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181281 | // MIs[0] offset |
| 181282 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181283 | // MIs[0] format |
| 181284 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181285 | // MIs[0] auxiliary |
| 181286 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181287 | // MIs[0] Operand 8 |
| 181288 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181289 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181290 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181291 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN), |
| 181292 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181293 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181294 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181295 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181296 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181299 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181300 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181301 | GIR_RootConstrainSelectedInstOperands, |
| 181302 | // GIR_Coverage, 6377, |
| 181303 | GIR_EraseRootFromParent_Done, |
| 181304 | // Label 8524: @569285 |
| 181305 | GIM_Try, /*On fail goto*//*Label 8525*/ GIMT_Encode4(569361), // Rule ID 6381 // |
| 181306 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181307 | // MIs[0] offset |
| 181308 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181309 | // MIs[0] format |
| 181310 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181311 | // MIs[0] auxiliary |
| 181312 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181313 | // MIs[0] Operand 8 |
| 181314 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181315 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181316 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN), |
| 181318 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181319 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181320 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181322 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181324 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181325 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181327 | GIR_RootConstrainSelectedInstOperands, |
| 181328 | // GIR_Coverage, 6381, |
| 181329 | GIR_EraseRootFromParent_Done, |
| 181330 | // Label 8525: @569361 |
| 181331 | GIM_Try, /*On fail goto*//*Label 8526*/ GIMT_Encode4(569440), // Rule ID 6409 // |
| 181332 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181333 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181334 | // MIs[0] offset |
| 181335 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181336 | // MIs[0] format |
| 181337 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181338 | // MIs[0] auxiliary |
| 181339 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181340 | // MIs[0] Operand 8 |
| 181341 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181342 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181343 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181344 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_OFFEN), |
| 181345 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181346 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181347 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181348 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181349 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181350 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181351 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181352 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181353 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181354 | GIR_RootConstrainSelectedInstOperands, |
| 181355 | // GIR_Coverage, 6409, |
| 181356 | GIR_EraseRootFromParent_Done, |
| 181357 | // Label 8526: @569440 |
| 181358 | GIM_Try, /*On fail goto*//*Label 8527*/ GIMT_Encode4(569516), // Rule ID 6413 // |
| 181359 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181360 | // MIs[0] offset |
| 181361 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181362 | // MIs[0] format |
| 181363 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181364 | // MIs[0] auxiliary |
| 181365 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181366 | // MIs[0] Operand 8 |
| 181367 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181368 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181369 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181370 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_OFFEN), |
| 181371 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181372 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181373 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181374 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181375 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181376 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181377 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181378 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181379 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181380 | GIR_RootConstrainSelectedInstOperands, |
| 181381 | // GIR_Coverage, 6413, |
| 181382 | GIR_EraseRootFromParent_Done, |
| 181383 | // Label 8527: @569516 |
| 181384 | GIM_Try, /*On fail goto*//*Label 8528*/ GIMT_Encode4(569587), // Rule ID 6376 // |
| 181385 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181386 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181387 | // MIs[0] offset |
| 181388 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181389 | // MIs[0] format |
| 181390 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181391 | // MIs[0] auxiliary |
| 181392 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181393 | // MIs[0] Operand 8 |
| 181394 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181395 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181396 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181397 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN), |
| 181398 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181399 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181400 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181401 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181402 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181403 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181404 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181405 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181406 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181407 | GIR_RootConstrainSelectedInstOperands, |
| 181408 | // GIR_Coverage, 6376, |
| 181409 | GIR_EraseRootFromParent_Done, |
| 181410 | // Label 8528: @569587 |
| 181411 | GIM_Try, /*On fail goto*//*Label 8529*/ GIMT_Encode4(569655), // Rule ID 6380 // |
| 181412 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181413 | // MIs[0] offset |
| 181414 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181415 | // MIs[0] format |
| 181416 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181417 | // MIs[0] auxiliary |
| 181418 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181419 | // MIs[0] Operand 8 |
| 181420 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181421 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181422 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN), |
| 181424 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181425 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181426 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181428 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181429 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181433 | GIR_RootConstrainSelectedInstOperands, |
| 181434 | // GIR_Coverage, 6380, |
| 181435 | GIR_EraseRootFromParent_Done, |
| 181436 | // Label 8529: @569655 |
| 181437 | GIM_Try, /*On fail goto*//*Label 8530*/ GIMT_Encode4(569726), // Rule ID 6408 // |
| 181438 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181439 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181440 | // MIs[0] offset |
| 181441 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181442 | // MIs[0] format |
| 181443 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181444 | // MIs[0] auxiliary |
| 181445 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181446 | // MIs[0] Operand 8 |
| 181447 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181448 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181449 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181450 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_IDXEN), |
| 181451 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181452 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181453 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181454 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181455 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181456 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181457 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181458 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181459 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181460 | GIR_RootConstrainSelectedInstOperands, |
| 181461 | // GIR_Coverage, 6408, |
| 181462 | GIR_EraseRootFromParent_Done, |
| 181463 | // Label 8530: @569726 |
| 181464 | GIM_Try, /*On fail goto*//*Label 8531*/ GIMT_Encode4(569794), // Rule ID 6412 // |
| 181465 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181466 | // MIs[0] offset |
| 181467 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181468 | // MIs[0] format |
| 181469 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181470 | // MIs[0] auxiliary |
| 181471 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181472 | // MIs[0] Operand 8 |
| 181473 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181474 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181475 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN:{ *:[v4f32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181476 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_IDXEN), |
| 181477 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181478 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181479 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181480 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181481 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181482 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181483 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181484 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181485 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181486 | GIR_RootConstrainSelectedInstOperands, |
| 181487 | // GIR_Coverage, 6412, |
| 181488 | GIR_EraseRootFromParent_Done, |
| 181489 | // Label 8531: @569794 |
| 181490 | GIM_Try, /*On fail goto*//*Label 8532*/ GIMT_Encode4(569903), // Rule ID 6378 // |
| 181491 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181492 | // MIs[0] offset |
| 181493 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181494 | // MIs[0] format |
| 181495 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181496 | // MIs[0] auxiliary |
| 181497 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181498 | // MIs[0] Operand 8 |
| 181499 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181500 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181501 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181502 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181503 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181504 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181505 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181506 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181507 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181508 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181509 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181510 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181511 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181512 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN), |
| 181513 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181514 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181515 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181517 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181518 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181519 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181520 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181522 | GIR_RootConstrainSelectedInstOperands, |
| 181523 | // GIR_Coverage, 6378, |
| 181524 | GIR_EraseRootFromParent_Done, |
| 181525 | // Label 8532: @569903 |
| 181526 | GIM_Try, /*On fail goto*//*Label 8533*/ GIMT_Encode4(570009), // Rule ID 6382 // |
| 181527 | // MIs[0] offset |
| 181528 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181529 | // MIs[0] format |
| 181530 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181531 | // MIs[0] auxiliary |
| 181532 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181533 | // MIs[0] Operand 8 |
| 181534 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181535 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181536 | // (SItbuffer_load:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181537 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181538 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181539 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181540 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181541 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181542 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181543 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181544 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181545 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181546 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181547 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN), |
| 181548 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181549 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181550 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181552 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181553 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181554 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181555 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181557 | GIR_RootConstrainSelectedInstOperands, |
| 181558 | // GIR_Coverage, 6382, |
| 181559 | GIR_EraseRootFromParent_Done, |
| 181560 | // Label 8533: @570009 |
| 181561 | GIM_Try, /*On fail goto*//*Label 8534*/ GIMT_Encode4(570118), // Rule ID 6410 // |
| 181562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 181563 | // MIs[0] offset |
| 181564 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181565 | // MIs[0] format |
| 181566 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181567 | // MIs[0] auxiliary |
| 181568 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181569 | // MIs[0] Operand 8 |
| 181570 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181571 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181572 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181573 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181574 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181575 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181576 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181577 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181578 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181579 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181580 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181581 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181582 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181583 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_BOTHEN), |
| 181584 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181585 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181586 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181587 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181588 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181589 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181590 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181591 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181592 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181593 | GIR_RootConstrainSelectedInstOperands, |
| 181594 | // GIR_Coverage, 6410, |
| 181595 | GIR_EraseRootFromParent_Done, |
| 181596 | // Label 8534: @570118 |
| 181597 | GIM_Try, /*On fail goto*//*Label 8535*/ GIMT_Encode4(570224), // Rule ID 6414 // |
| 181598 | // MIs[0] offset |
| 181599 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181600 | // MIs[0] format |
| 181601 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181602 | // MIs[0] auxiliary |
| 181603 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181604 | // MIs[0] Operand 8 |
| 181605 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181606 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181607 | // (SItbuffer_load:{ *:[v4f32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN:{ *:[v4f32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181608 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181609 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181610 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181611 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181612 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181613 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181614 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181615 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181616 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181617 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_XYZW_VBUFFER_BOTHEN), |
| 181619 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181620 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181621 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181623 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181624 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181625 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181626 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181628 | GIR_RootConstrainSelectedInstOperands, |
| 181629 | // GIR_Coverage, 6414, |
| 181630 | GIR_EraseRootFromParent_Done, |
| 181631 | // Label 8535: @570224 |
| 181632 | GIM_Reject, |
| 181633 | // Label 8519: @570225 |
| 181634 | GIM_Reject, |
| 181635 | // Label 8467: @570226 |
| 181636 | GIM_Reject, |
| 181637 | // Label 162: @570227 |
| 181638 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 8543*/ GIMT_Encode4(575655), |
| 181639 | /*GILLT_s16*//*Label 8536*/ GIMT_Encode4(570278), |
| 181640 | /*GILLT_s32*//*Label 8537*/ GIMT_Encode4(571321), GIMT_Encode4(0), |
| 181641 | /*GILLT_v2s16*//*Label 8538*/ GIMT_Encode4(572364), |
| 181642 | /*GILLT_v2s32*//*Label 8539*/ GIMT_Encode4(573067), GIMT_Encode4(0), |
| 181643 | /*GILLT_v3s32*//*Label 8540*/ GIMT_Encode4(573430), GIMT_Encode4(0), |
| 181644 | /*GILLT_v4s16*//*Label 8541*/ GIMT_Encode4(573793), |
| 181645 | /*GILLT_v4s32*//*Label 8542*/ GIMT_Encode4(575292), |
| 181646 | // Label 8536: @570278 |
| 181647 | GIM_Try, /*On fail goto*//*Label 8544*/ GIMT_Encode4(571320), |
| 181648 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 181649 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 181650 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 181651 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 181652 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 181653 | GIM_Try, /*On fail goto*//*Label 8545*/ GIMT_Encode4(570380), // Rule ID 6415 // |
| 181654 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 181655 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181656 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181657 | // MIs[0] offset |
| 181658 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181659 | // MIs[0] format |
| 181660 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181661 | // MIs[0] auxiliary |
| 181662 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181663 | // MIs[0] Operand 8 |
| 181664 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181665 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181666 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181667 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET), |
| 181668 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181669 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181670 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181671 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181672 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181673 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181674 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181675 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181676 | GIR_RootConstrainSelectedInstOperands, |
| 181677 | // GIR_Coverage, 6415, |
| 181678 | GIR_EraseRootFromParent_Done, |
| 181679 | // Label 8545: @570380 |
| 181680 | GIM_Try, /*On fail goto*//*Label 8546*/ GIMT_Encode4(570461), // Rule ID 6435 // |
| 181681 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 181682 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181683 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181684 | // MIs[0] offset |
| 181685 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181686 | // MIs[0] format |
| 181687 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181688 | // MIs[0] auxiliary |
| 181689 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181690 | // MIs[0] Operand 8 |
| 181691 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181692 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181693 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181694 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET), |
| 181695 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181696 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181697 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181698 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181699 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181700 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181701 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181702 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181703 | GIR_RootConstrainSelectedInstOperands, |
| 181704 | // GIR_Coverage, 6435, |
| 181705 | GIR_EraseRootFromParent_Done, |
| 181706 | // Label 8546: @570461 |
| 181707 | GIM_Try, /*On fail goto*//*Label 8547*/ GIMT_Encode4(570542), // Rule ID 6439 // |
| 181708 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 181709 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181710 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181711 | // MIs[0] offset |
| 181712 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181713 | // MIs[0] format |
| 181714 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181715 | // MIs[0] auxiliary |
| 181716 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181717 | // MIs[0] Operand 8 |
| 181718 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181719 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181720 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181721 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET), |
| 181722 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181723 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181724 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181725 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181726 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181727 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181728 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181729 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181730 | GIR_RootConstrainSelectedInstOperands, |
| 181731 | // GIR_Coverage, 6439, |
| 181732 | GIR_EraseRootFromParent_Done, |
| 181733 | // Label 8547: @570542 |
| 181734 | GIM_Try, /*On fail goto*//*Label 8548*/ GIMT_Encode4(570621), // Rule ID 6417 // |
| 181735 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 181736 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181737 | // MIs[0] offset |
| 181738 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181739 | // MIs[0] format |
| 181740 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181741 | // MIs[0] auxiliary |
| 181742 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181743 | // MIs[0] Operand 8 |
| 181744 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181745 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181746 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181747 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN), |
| 181748 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181749 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181750 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181751 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181752 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181753 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181754 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181755 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181756 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181757 | GIR_RootConstrainSelectedInstOperands, |
| 181758 | // GIR_Coverage, 6417, |
| 181759 | GIR_EraseRootFromParent_Done, |
| 181760 | // Label 8548: @570621 |
| 181761 | GIM_Try, /*On fail goto*//*Label 8549*/ GIMT_Encode4(570700), // Rule ID 6437 // |
| 181762 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 181763 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181764 | // MIs[0] offset |
| 181765 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181766 | // MIs[0] format |
| 181767 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181768 | // MIs[0] auxiliary |
| 181769 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181770 | // MIs[0] Operand 8 |
| 181771 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181772 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181773 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181774 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN), |
| 181775 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181776 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181777 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181778 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181779 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181780 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181781 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181782 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181783 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181784 | GIR_RootConstrainSelectedInstOperands, |
| 181785 | // GIR_Coverage, 6437, |
| 181786 | GIR_EraseRootFromParent_Done, |
| 181787 | // Label 8549: @570700 |
| 181788 | GIM_Try, /*On fail goto*//*Label 8550*/ GIMT_Encode4(570779), // Rule ID 6441 // |
| 181789 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 181790 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 181791 | // MIs[0] offset |
| 181792 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181793 | // MIs[0] format |
| 181794 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181795 | // MIs[0] auxiliary |
| 181796 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181797 | // MIs[0] Operand 8 |
| 181798 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 181799 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181800 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181801 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN), |
| 181802 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181803 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 181804 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181805 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181806 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181807 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181808 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181809 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181810 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181811 | GIR_RootConstrainSelectedInstOperands, |
| 181812 | // GIR_Coverage, 6441, |
| 181813 | GIR_EraseRootFromParent_Done, |
| 181814 | // Label 8550: @570779 |
| 181815 | GIM_Try, /*On fail goto*//*Label 8551*/ GIMT_Encode4(570850), // Rule ID 6416 // |
| 181816 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 181817 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181818 | // MIs[0] offset |
| 181819 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181820 | // MIs[0] format |
| 181821 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181822 | // MIs[0] auxiliary |
| 181823 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181824 | // MIs[0] Operand 8 |
| 181825 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181826 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181827 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181828 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN), |
| 181829 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181830 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181831 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181832 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181833 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181834 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181835 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181836 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181837 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181838 | GIR_RootConstrainSelectedInstOperands, |
| 181839 | // GIR_Coverage, 6416, |
| 181840 | GIR_EraseRootFromParent_Done, |
| 181841 | // Label 8551: @570850 |
| 181842 | GIM_Try, /*On fail goto*//*Label 8552*/ GIMT_Encode4(570921), // Rule ID 6436 // |
| 181843 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 181844 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181845 | // MIs[0] offset |
| 181846 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181847 | // MIs[0] format |
| 181848 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181849 | // MIs[0] auxiliary |
| 181850 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181851 | // MIs[0] Operand 8 |
| 181852 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181853 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181854 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181855 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN), |
| 181856 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181857 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181858 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181859 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181860 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181861 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181862 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181863 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181864 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181865 | GIR_RootConstrainSelectedInstOperands, |
| 181866 | // GIR_Coverage, 6436, |
| 181867 | GIR_EraseRootFromParent_Done, |
| 181868 | // Label 8552: @570921 |
| 181869 | GIM_Try, /*On fail goto*//*Label 8553*/ GIMT_Encode4(570992), // Rule ID 6440 // |
| 181870 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 181871 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 181872 | // MIs[0] offset |
| 181873 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181874 | // MIs[0] format |
| 181875 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181876 | // MIs[0] auxiliary |
| 181877 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181878 | // MIs[0] Operand 8 |
| 181879 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181881 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181882 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN), |
| 181883 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181884 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 181885 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181886 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181887 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181888 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181890 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181891 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181892 | GIR_RootConstrainSelectedInstOperands, |
| 181893 | // GIR_Coverage, 6440, |
| 181894 | GIR_EraseRootFromParent_Done, |
| 181895 | // Label 8553: @570992 |
| 181896 | GIM_Try, /*On fail goto*//*Label 8554*/ GIMT_Encode4(571101), // Rule ID 6418 // |
| 181897 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 181898 | // MIs[0] offset |
| 181899 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181900 | // MIs[0] format |
| 181901 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181902 | // MIs[0] auxiliary |
| 181903 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181904 | // MIs[0] Operand 8 |
| 181905 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181906 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181907 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181908 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181909 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181910 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181911 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181912 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181913 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181914 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181915 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181916 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181917 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181918 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN), |
| 181919 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181920 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181921 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181922 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181923 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181925 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181926 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181927 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181928 | GIR_RootConstrainSelectedInstOperands, |
| 181929 | // GIR_Coverage, 6418, |
| 181930 | GIR_EraseRootFromParent_Done, |
| 181931 | // Label 8554: @571101 |
| 181932 | GIM_Try, /*On fail goto*//*Label 8555*/ GIMT_Encode4(571210), // Rule ID 6438 // |
| 181933 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 181934 | // MIs[0] offset |
| 181935 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181936 | // MIs[0] format |
| 181937 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181938 | // MIs[0] auxiliary |
| 181939 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181940 | // MIs[0] Operand 8 |
| 181941 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181943 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181947 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181948 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181950 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181951 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181952 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181953 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN), |
| 181955 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181956 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181957 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181959 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181962 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 181964 | GIR_RootConstrainSelectedInstOperands, |
| 181965 | // GIR_Coverage, 6438, |
| 181966 | GIR_EraseRootFromParent_Done, |
| 181967 | // Label 8555: @571210 |
| 181968 | GIM_Try, /*On fail goto*//*Label 8556*/ GIMT_Encode4(571319), // Rule ID 6442 // |
| 181969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 181970 | // MIs[0] offset |
| 181971 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 181972 | // MIs[0] format |
| 181973 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 181974 | // MIs[0] auxiliary |
| 181975 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 181976 | // MIs[0] Operand 8 |
| 181977 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 181978 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 181979 | // (SItbuffer_load_d16:{ *:[f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 181980 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 181981 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 181982 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 181983 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 181984 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 181985 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 181986 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 181987 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 181988 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181989 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 181990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN), |
| 181991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 181992 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 181993 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 181994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 181995 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 181996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 181997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 181998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 181999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182000 | GIR_RootConstrainSelectedInstOperands, |
| 182001 | // GIR_Coverage, 6442, |
| 182002 | GIR_EraseRootFromParent_Done, |
| 182003 | // Label 8556: @571319 |
| 182004 | GIM_Reject, |
| 182005 | // Label 8544: @571320 |
| 182006 | GIM_Reject, |
| 182007 | // Label 8537: @571321 |
| 182008 | GIM_Try, /*On fail goto*//*Label 8557*/ GIMT_Encode4(572363), |
| 182009 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 182010 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 182011 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 182012 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 182013 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 182014 | GIM_Try, /*On fail goto*//*Label 8558*/ GIMT_Encode4(571423), // Rule ID 6419 // |
| 182015 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182016 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182017 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182018 | // MIs[0] offset |
| 182019 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182020 | // MIs[0] format |
| 182021 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182022 | // MIs[0] auxiliary |
| 182023 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182024 | // MIs[0] Operand 8 |
| 182025 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182026 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182027 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182028 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFSET), |
| 182029 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182030 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182031 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182032 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182033 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182034 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182035 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182036 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182037 | GIR_RootConstrainSelectedInstOperands, |
| 182038 | // GIR_Coverage, 6419, |
| 182039 | GIR_EraseRootFromParent_Done, |
| 182040 | // Label 8558: @571423 |
| 182041 | GIM_Try, /*On fail goto*//*Label 8559*/ GIMT_Encode4(571504), // Rule ID 6443 // |
| 182042 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182043 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182044 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182045 | // MIs[0] offset |
| 182046 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182047 | // MIs[0] format |
| 182048 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182049 | // MIs[0] auxiliary |
| 182050 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182051 | // MIs[0] Operand 8 |
| 182052 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182053 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182054 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182055 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFSET), |
| 182056 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182057 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182058 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182059 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182060 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182061 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182063 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182064 | GIR_RootConstrainSelectedInstOperands, |
| 182065 | // GIR_Coverage, 6443, |
| 182066 | GIR_EraseRootFromParent_Done, |
| 182067 | // Label 8559: @571504 |
| 182068 | GIM_Try, /*On fail goto*//*Label 8560*/ GIMT_Encode4(571585), // Rule ID 6447 // |
| 182069 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182070 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182071 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182072 | // MIs[0] offset |
| 182073 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182074 | // MIs[0] format |
| 182075 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182076 | // MIs[0] auxiliary |
| 182077 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182078 | // MIs[0] Operand 8 |
| 182079 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182081 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET:{ *:[i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182082 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFSET), |
| 182083 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182084 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182085 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182086 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182087 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182088 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182089 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182090 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182091 | GIR_RootConstrainSelectedInstOperands, |
| 182092 | // GIR_Coverage, 6447, |
| 182093 | GIR_EraseRootFromParent_Done, |
| 182094 | // Label 8560: @571585 |
| 182095 | GIM_Try, /*On fail goto*//*Label 8561*/ GIMT_Encode4(571664), // Rule ID 6421 // |
| 182096 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182097 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182098 | // MIs[0] offset |
| 182099 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182100 | // MIs[0] format |
| 182101 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182102 | // MIs[0] auxiliary |
| 182103 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182104 | // MIs[0] Operand 8 |
| 182105 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182106 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182107 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182108 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_OFFEN), |
| 182109 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182110 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182111 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182112 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182113 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182114 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182115 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182116 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182117 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182118 | GIR_RootConstrainSelectedInstOperands, |
| 182119 | // GIR_Coverage, 6421, |
| 182120 | GIR_EraseRootFromParent_Done, |
| 182121 | // Label 8561: @571664 |
| 182122 | GIM_Try, /*On fail goto*//*Label 8562*/ GIMT_Encode4(571743), // Rule ID 6445 // |
| 182123 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182124 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182125 | // MIs[0] offset |
| 182126 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182127 | // MIs[0] format |
| 182128 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182129 | // MIs[0] auxiliary |
| 182130 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182131 | // MIs[0] Operand 8 |
| 182132 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182133 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182134 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182135 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_OFFEN), |
| 182136 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182137 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182138 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182139 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182140 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182141 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182142 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182143 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182144 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182145 | GIR_RootConstrainSelectedInstOperands, |
| 182146 | // GIR_Coverage, 6445, |
| 182147 | GIR_EraseRootFromParent_Done, |
| 182148 | // Label 8562: @571743 |
| 182149 | GIM_Try, /*On fail goto*//*Label 8563*/ GIMT_Encode4(571822), // Rule ID 6449 // |
| 182150 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182151 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182152 | // MIs[0] offset |
| 182153 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182154 | // MIs[0] format |
| 182155 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182156 | // MIs[0] auxiliary |
| 182157 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182158 | // MIs[0] Operand 8 |
| 182159 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182160 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182161 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182162 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_OFFEN), |
| 182163 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182164 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182165 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182166 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182167 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182168 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182169 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182170 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182171 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182172 | GIR_RootConstrainSelectedInstOperands, |
| 182173 | // GIR_Coverage, 6449, |
| 182174 | GIR_EraseRootFromParent_Done, |
| 182175 | // Label 8563: @571822 |
| 182176 | GIM_Try, /*On fail goto*//*Label 8564*/ GIMT_Encode4(571893), // Rule ID 6420 // |
| 182177 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182178 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182179 | // MIs[0] offset |
| 182180 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182181 | // MIs[0] format |
| 182182 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182183 | // MIs[0] auxiliary |
| 182184 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182185 | // MIs[0] Operand 8 |
| 182186 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182187 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182188 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182189 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_IDXEN), |
| 182190 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182191 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182192 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182193 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182194 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182195 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182196 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182197 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182198 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182199 | GIR_RootConstrainSelectedInstOperands, |
| 182200 | // GIR_Coverage, 6420, |
| 182201 | GIR_EraseRootFromParent_Done, |
| 182202 | // Label 8564: @571893 |
| 182203 | GIM_Try, /*On fail goto*//*Label 8565*/ GIMT_Encode4(571964), // Rule ID 6444 // |
| 182204 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182205 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182206 | // MIs[0] offset |
| 182207 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182208 | // MIs[0] format |
| 182209 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182210 | // MIs[0] auxiliary |
| 182211 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182212 | // MIs[0] Operand 8 |
| 182213 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182214 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182215 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182216 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_IDXEN), |
| 182217 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182218 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182219 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182220 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182221 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182222 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182223 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182224 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182225 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182226 | GIR_RootConstrainSelectedInstOperands, |
| 182227 | // GIR_Coverage, 6444, |
| 182228 | GIR_EraseRootFromParent_Done, |
| 182229 | // Label 8565: @571964 |
| 182230 | GIM_Try, /*On fail goto*//*Label 8566*/ GIMT_Encode4(572035), // Rule ID 6448 // |
| 182231 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182232 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182233 | // MIs[0] offset |
| 182234 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182235 | // MIs[0] format |
| 182236 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182237 | // MIs[0] auxiliary |
| 182238 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182239 | // MIs[0] Operand 8 |
| 182240 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182241 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182242 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN:{ *:[i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182243 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_IDXEN), |
| 182244 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182245 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182246 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182247 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182248 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182249 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182250 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182251 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182252 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182253 | GIR_RootConstrainSelectedInstOperands, |
| 182254 | // GIR_Coverage, 6448, |
| 182255 | GIR_EraseRootFromParent_Done, |
| 182256 | // Label 8566: @572035 |
| 182257 | GIM_Try, /*On fail goto*//*Label 8567*/ GIMT_Encode4(572144), // Rule ID 6422 // |
| 182258 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182259 | // MIs[0] offset |
| 182260 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182261 | // MIs[0] format |
| 182262 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182263 | // MIs[0] auxiliary |
| 182264 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182265 | // MIs[0] Operand 8 |
| 182266 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182267 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182268 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182269 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182270 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182271 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182272 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182273 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182274 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182275 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182276 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182277 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182278 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182279 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_gfx80_BOTHEN), |
| 182280 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182281 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182282 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182283 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182284 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182285 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182286 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182287 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182288 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182289 | GIR_RootConstrainSelectedInstOperands, |
| 182290 | // GIR_Coverage, 6422, |
| 182291 | GIR_EraseRootFromParent_Done, |
| 182292 | // Label 8567: @572144 |
| 182293 | GIM_Try, /*On fail goto*//*Label 8568*/ GIMT_Encode4(572253), // Rule ID 6446 // |
| 182294 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182295 | // MIs[0] offset |
| 182296 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182297 | // MIs[0] format |
| 182298 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182299 | // MIs[0] auxiliary |
| 182300 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182301 | // MIs[0] Operand 8 |
| 182302 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182303 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182304 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182305 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182306 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182307 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182308 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182309 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182310 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182311 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182312 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182313 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182314 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182315 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_BOTHEN), |
| 182316 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182317 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182318 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182319 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182320 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182321 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182322 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182324 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182325 | GIR_RootConstrainSelectedInstOperands, |
| 182326 | // GIR_Coverage, 6446, |
| 182327 | GIR_EraseRootFromParent_Done, |
| 182328 | // Label 8568: @572253 |
| 182329 | GIM_Try, /*On fail goto*//*Label 8569*/ GIMT_Encode4(572362), // Rule ID 6450 // |
| 182330 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182331 | // MIs[0] offset |
| 182332 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182333 | // MIs[0] format |
| 182334 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182335 | // MIs[0] auxiliary |
| 182336 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182337 | // MIs[0] Operand 8 |
| 182338 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182339 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182340 | // (SItbuffer_load_d16:{ *:[i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN:{ *:[i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182341 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182342 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182343 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182344 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182345 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182346 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182347 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182348 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182349 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182350 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182351 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_X_VBUFFER_BOTHEN), |
| 182352 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182353 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182354 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182355 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182356 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182357 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182358 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182360 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182361 | GIR_RootConstrainSelectedInstOperands, |
| 182362 | // GIR_Coverage, 6450, |
| 182363 | GIR_EraseRootFromParent_Done, |
| 182364 | // Label 8569: @572362 |
| 182365 | GIM_Reject, |
| 182366 | // Label 8557: @572363 |
| 182367 | GIM_Reject, |
| 182368 | // Label 8538: @572364 |
| 182369 | GIM_Try, /*On fail goto*//*Label 8570*/ GIMT_Encode4(573066), |
| 182370 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 182371 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 182372 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 182373 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 182374 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_32RegClassID), |
| 182375 | GIM_Try, /*On fail goto*//*Label 8571*/ GIMT_Encode4(572466), // Rule ID 6451 // |
| 182376 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182378 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182379 | // MIs[0] offset |
| 182380 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182381 | // MIs[0] format |
| 182382 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182383 | // MIs[0] auxiliary |
| 182384 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182385 | // MIs[0] Operand 8 |
| 182386 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182387 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182388 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182389 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFSET), |
| 182390 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182391 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182393 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182395 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182396 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182398 | GIR_RootConstrainSelectedInstOperands, |
| 182399 | // GIR_Coverage, 6451, |
| 182400 | GIR_EraseRootFromParent_Done, |
| 182401 | // Label 8571: @572466 |
| 182402 | GIM_Try, /*On fail goto*//*Label 8572*/ GIMT_Encode4(572547), // Rule ID 6455 // |
| 182403 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182404 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182405 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182406 | // MIs[0] offset |
| 182407 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182408 | // MIs[0] format |
| 182409 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182410 | // MIs[0] auxiliary |
| 182411 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182412 | // MIs[0] Operand 8 |
| 182413 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182414 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182415 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET:{ *:[v2f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182416 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFSET), |
| 182417 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182418 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182419 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182420 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182421 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182422 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182423 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182424 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182425 | GIR_RootConstrainSelectedInstOperands, |
| 182426 | // GIR_Coverage, 6455, |
| 182427 | GIR_EraseRootFromParent_Done, |
| 182428 | // Label 8572: @572547 |
| 182429 | GIM_Try, /*On fail goto*//*Label 8573*/ GIMT_Encode4(572626), // Rule ID 6453 // |
| 182430 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182431 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182432 | // MIs[0] offset |
| 182433 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182434 | // MIs[0] format |
| 182435 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182436 | // MIs[0] auxiliary |
| 182437 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182438 | // MIs[0] Operand 8 |
| 182439 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182440 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182441 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182442 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_OFFEN), |
| 182443 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182444 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182445 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182446 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182447 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182448 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182449 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182450 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182451 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182452 | GIR_RootConstrainSelectedInstOperands, |
| 182453 | // GIR_Coverage, 6453, |
| 182454 | GIR_EraseRootFromParent_Done, |
| 182455 | // Label 8573: @572626 |
| 182456 | GIM_Try, /*On fail goto*//*Label 8574*/ GIMT_Encode4(572705), // Rule ID 6457 // |
| 182457 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182458 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182459 | // MIs[0] offset |
| 182460 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182461 | // MIs[0] format |
| 182462 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182463 | // MIs[0] auxiliary |
| 182464 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182465 | // MIs[0] Operand 8 |
| 182466 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182467 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182468 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182469 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_OFFEN), |
| 182470 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182471 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182472 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182473 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182474 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182475 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182476 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182477 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182478 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182479 | GIR_RootConstrainSelectedInstOperands, |
| 182480 | // GIR_Coverage, 6457, |
| 182481 | GIR_EraseRootFromParent_Done, |
| 182482 | // Label 8574: @572705 |
| 182483 | GIM_Try, /*On fail goto*//*Label 8575*/ GIMT_Encode4(572776), // Rule ID 6452 // |
| 182484 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182485 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182486 | // MIs[0] offset |
| 182487 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182488 | // MIs[0] format |
| 182489 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182490 | // MIs[0] auxiliary |
| 182491 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182492 | // MIs[0] Operand 8 |
| 182493 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182494 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182495 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182496 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_IDXEN), |
| 182497 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182498 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182499 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182500 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182501 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182502 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182503 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182504 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182505 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182506 | GIR_RootConstrainSelectedInstOperands, |
| 182507 | // GIR_Coverage, 6452, |
| 182508 | GIR_EraseRootFromParent_Done, |
| 182509 | // Label 8575: @572776 |
| 182510 | GIM_Try, /*On fail goto*//*Label 8576*/ GIMT_Encode4(572847), // Rule ID 6456 // |
| 182511 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182512 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182513 | // MIs[0] offset |
| 182514 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182515 | // MIs[0] format |
| 182516 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182517 | // MIs[0] auxiliary |
| 182518 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182519 | // MIs[0] Operand 8 |
| 182520 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182521 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182522 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN:{ *:[v2f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182523 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_IDXEN), |
| 182524 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182525 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182526 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182527 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182528 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182529 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182530 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182531 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182532 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182533 | GIR_RootConstrainSelectedInstOperands, |
| 182534 | // GIR_Coverage, 6456, |
| 182535 | GIR_EraseRootFromParent_Done, |
| 182536 | // Label 8576: @572847 |
| 182537 | GIM_Try, /*On fail goto*//*Label 8577*/ GIMT_Encode4(572956), // Rule ID 6454 // |
| 182538 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182539 | // MIs[0] offset |
| 182540 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182541 | // MIs[0] format |
| 182542 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182543 | // MIs[0] auxiliary |
| 182544 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182545 | // MIs[0] Operand 8 |
| 182546 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182547 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182548 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182549 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182550 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182551 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182552 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182553 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182554 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182555 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182556 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182557 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182558 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182559 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_BOTHEN), |
| 182560 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182561 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182562 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182563 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182564 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182565 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182566 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182567 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182568 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182569 | GIR_RootConstrainSelectedInstOperands, |
| 182570 | // GIR_Coverage, 6454, |
| 182571 | GIR_EraseRootFromParent_Done, |
| 182572 | // Label 8577: @572956 |
| 182573 | GIM_Try, /*On fail goto*//*Label 8578*/ GIMT_Encode4(573065), // Rule ID 6458 // |
| 182574 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182575 | // MIs[0] offset |
| 182576 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182577 | // MIs[0] format |
| 182578 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182579 | // MIs[0] auxiliary |
| 182580 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182581 | // MIs[0] Operand 8 |
| 182582 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182583 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182584 | // (SItbuffer_load_d16:{ *:[v2f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN:{ *:[v2f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182585 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182586 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182587 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182588 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182589 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182590 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182591 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182592 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182593 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182594 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182595 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_VBUFFER_BOTHEN), |
| 182596 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182597 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182598 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182599 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182600 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182601 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182602 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182603 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182604 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182605 | GIR_RootConstrainSelectedInstOperands, |
| 182606 | // GIR_Coverage, 6458, |
| 182607 | GIR_EraseRootFromParent_Done, |
| 182608 | // Label 8578: @573065 |
| 182609 | GIM_Reject, |
| 182610 | // Label 8570: @573066 |
| 182611 | GIM_Reject, |
| 182612 | // Label 8539: @573067 |
| 182613 | GIM_Try, /*On fail goto*//*Label 8579*/ GIMT_Encode4(573429), |
| 182614 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 182615 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 182616 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 182617 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 182618 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182619 | GIM_Try, /*On fail goto*//*Label 8580*/ GIMT_Encode4(573169), // Rule ID 6423 // |
| 182620 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182621 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182622 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182623 | // MIs[0] offset |
| 182624 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182625 | // MIs[0] format |
| 182626 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182627 | // MIs[0] auxiliary |
| 182628 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182629 | // MIs[0] Operand 8 |
| 182630 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182631 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182632 | // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET:{ *:[v2i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182633 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFSET), |
| 182634 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182635 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182636 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182637 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182638 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182639 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182640 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182641 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182642 | GIR_RootConstrainSelectedInstOperands, |
| 182643 | // GIR_Coverage, 6423, |
| 182644 | GIR_EraseRootFromParent_Done, |
| 182645 | // Label 8580: @573169 |
| 182646 | GIM_Try, /*On fail goto*//*Label 8581*/ GIMT_Encode4(573248), // Rule ID 6425 // |
| 182647 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182648 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182649 | // MIs[0] offset |
| 182650 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182651 | // MIs[0] format |
| 182652 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182653 | // MIs[0] auxiliary |
| 182654 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182655 | // MIs[0] Operand 8 |
| 182656 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182657 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182658 | // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182659 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_OFFEN), |
| 182660 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182661 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182662 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182663 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182664 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182665 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182666 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182668 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182669 | GIR_RootConstrainSelectedInstOperands, |
| 182670 | // GIR_Coverage, 6425, |
| 182671 | GIR_EraseRootFromParent_Done, |
| 182672 | // Label 8581: @573248 |
| 182673 | GIM_Try, /*On fail goto*//*Label 8582*/ GIMT_Encode4(573319), // Rule ID 6424 // |
| 182674 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182675 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182676 | // MIs[0] offset |
| 182677 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182678 | // MIs[0] format |
| 182679 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182680 | // MIs[0] auxiliary |
| 182681 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182682 | // MIs[0] Operand 8 |
| 182683 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182685 | // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN:{ *:[v2i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182686 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_IDXEN), |
| 182687 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182688 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182689 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182690 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182691 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182692 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182693 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182694 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182695 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182696 | GIR_RootConstrainSelectedInstOperands, |
| 182697 | // GIR_Coverage, 6424, |
| 182698 | GIR_EraseRootFromParent_Done, |
| 182699 | // Label 8582: @573319 |
| 182700 | GIM_Try, /*On fail goto*//*Label 8583*/ GIMT_Encode4(573428), // Rule ID 6426 // |
| 182701 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182702 | // MIs[0] offset |
| 182703 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182704 | // MIs[0] format |
| 182705 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182706 | // MIs[0] auxiliary |
| 182707 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182708 | // MIs[0] Operand 8 |
| 182709 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182710 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182711 | // (SItbuffer_load_d16:{ *:[v2i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN:{ *:[v2i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182712 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182713 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182714 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182715 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182716 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182717 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182718 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182719 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182720 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182721 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182722 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XY_gfx80_BOTHEN), |
| 182723 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182724 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182725 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182726 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182727 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182728 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182729 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182730 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182731 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182732 | GIR_RootConstrainSelectedInstOperands, |
| 182733 | // GIR_Coverage, 6426, |
| 182734 | GIR_EraseRootFromParent_Done, |
| 182735 | // Label 8583: @573428 |
| 182736 | GIM_Reject, |
| 182737 | // Label 8579: @573429 |
| 182738 | GIM_Reject, |
| 182739 | // Label 8540: @573430 |
| 182740 | GIM_Try, /*On fail goto*//*Label 8584*/ GIMT_Encode4(573792), |
| 182741 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 182742 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 182743 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 182744 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 182745 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_96RegClassID), |
| 182746 | GIM_Try, /*On fail goto*//*Label 8585*/ GIMT_Encode4(573532), // Rule ID 6427 // |
| 182747 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182748 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182749 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182750 | // MIs[0] offset |
| 182751 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182752 | // MIs[0] format |
| 182753 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182754 | // MIs[0] auxiliary |
| 182755 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182756 | // MIs[0] Operand 8 |
| 182757 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182758 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182759 | // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET:{ *:[v3i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182760 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFSET), |
| 182761 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182762 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182764 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182765 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182767 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182769 | GIR_RootConstrainSelectedInstOperands, |
| 182770 | // GIR_Coverage, 6427, |
| 182771 | GIR_EraseRootFromParent_Done, |
| 182772 | // Label 8585: @573532 |
| 182773 | GIM_Try, /*On fail goto*//*Label 8586*/ GIMT_Encode4(573611), // Rule ID 6429 // |
| 182774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182775 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182776 | // MIs[0] offset |
| 182777 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182778 | // MIs[0] format |
| 182779 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182780 | // MIs[0] auxiliary |
| 182781 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182782 | // MIs[0] Operand 8 |
| 182783 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182785 | // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_OFFEN), |
| 182787 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182788 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 182789 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182791 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182793 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182794 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182796 | GIR_RootConstrainSelectedInstOperands, |
| 182797 | // GIR_Coverage, 6429, |
| 182798 | GIR_EraseRootFromParent_Done, |
| 182799 | // Label 8586: @573611 |
| 182800 | GIM_Try, /*On fail goto*//*Label 8587*/ GIMT_Encode4(573682), // Rule ID 6428 // |
| 182801 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182802 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182803 | // MIs[0] offset |
| 182804 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182805 | // MIs[0] format |
| 182806 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182807 | // MIs[0] auxiliary |
| 182808 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182809 | // MIs[0] Operand 8 |
| 182810 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182811 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182812 | // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN:{ *:[v3i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182813 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_IDXEN), |
| 182814 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182815 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 182816 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182817 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182818 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182819 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182821 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182822 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182823 | GIR_RootConstrainSelectedInstOperands, |
| 182824 | // GIR_Coverage, 6428, |
| 182825 | GIR_EraseRootFromParent_Done, |
| 182826 | // Label 8587: @573682 |
| 182827 | GIM_Try, /*On fail goto*//*Label 8588*/ GIMT_Encode4(573791), // Rule ID 6430 // |
| 182828 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 182829 | // MIs[0] offset |
| 182830 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182831 | // MIs[0] format |
| 182832 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182833 | // MIs[0] auxiliary |
| 182834 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182835 | // MIs[0] Operand 8 |
| 182836 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 182837 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182838 | // (SItbuffer_load_d16:{ *:[v3i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN:{ *:[v3i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182839 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 182840 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 182841 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 182842 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 182843 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 182844 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 182845 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 182846 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 182847 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182848 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 182849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_gfx80_BOTHEN), |
| 182850 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182851 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 182852 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182854 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182856 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182857 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182859 | GIR_RootConstrainSelectedInstOperands, |
| 182860 | // GIR_Coverage, 6430, |
| 182861 | GIR_EraseRootFromParent_Done, |
| 182862 | // Label 8588: @573791 |
| 182863 | GIM_Reject, |
| 182864 | // Label 8584: @573792 |
| 182865 | GIM_Reject, |
| 182866 | // Label 8541: @573793 |
| 182867 | GIM_Try, /*On fail goto*//*Label 8589*/ GIMT_Encode4(575291), |
| 182868 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 182869 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 182870 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 182871 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 182872 | GIM_Try, /*On fail goto*//*Label 8590*/ GIMT_Encode4(573902), // Rule ID 6459 // |
| 182873 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182874 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 182875 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182876 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182877 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182878 | // MIs[0] offset |
| 182879 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182880 | // MIs[0] format |
| 182881 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182882 | // MIs[0] auxiliary |
| 182883 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182884 | // MIs[0] Operand 8 |
| 182885 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182886 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182887 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182888 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFSET), |
| 182889 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182890 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182891 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182892 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182893 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182894 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182895 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182896 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182897 | GIR_RootConstrainSelectedInstOperands, |
| 182898 | // GIR_Coverage, 6459, |
| 182899 | GIR_EraseRootFromParent_Done, |
| 182900 | // Label 8590: @573902 |
| 182901 | GIM_Try, /*On fail goto*//*Label 8591*/ GIMT_Encode4(573994), // Rule ID 6463 // |
| 182902 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182903 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 182904 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182905 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182906 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182907 | // MIs[0] offset |
| 182908 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182909 | // MIs[0] format |
| 182910 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182911 | // MIs[0] auxiliary |
| 182912 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182913 | // MIs[0] Operand 8 |
| 182914 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182915 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182916 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182917 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFSET), |
| 182918 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182919 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182920 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182921 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182922 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182923 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182924 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182925 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182926 | GIR_RootConstrainSelectedInstOperands, |
| 182927 | // GIR_Coverage, 6463, |
| 182928 | GIR_EraseRootFromParent_Done, |
| 182929 | // Label 8591: @573994 |
| 182930 | GIM_Try, /*On fail goto*//*Label 8592*/ GIMT_Encode4(574079), // Rule ID 6467 // |
| 182931 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182932 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182933 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182934 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182935 | // MIs[0] offset |
| 182936 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182937 | // MIs[0] format |
| 182938 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182939 | // MIs[0] auxiliary |
| 182940 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182941 | // MIs[0] Operand 8 |
| 182942 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182943 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182944 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182945 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFSET), |
| 182946 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182947 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182948 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182949 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182950 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182951 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182952 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182953 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182954 | GIR_RootConstrainSelectedInstOperands, |
| 182955 | // GIR_Coverage, 6467, |
| 182956 | GIR_EraseRootFromParent_Done, |
| 182957 | // Label 8592: @574079 |
| 182958 | GIM_Try, /*On fail goto*//*Label 8593*/ GIMT_Encode4(574164), // Rule ID 6471 // |
| 182959 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 182960 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182961 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182962 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 182963 | // MIs[0] offset |
| 182964 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182965 | // MIs[0] format |
| 182966 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182967 | // MIs[0] auxiliary |
| 182968 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182969 | // MIs[0] Operand 8 |
| 182970 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182971 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 182972 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET:{ *:[v4f16] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 182973 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFSET), |
| 182974 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 182975 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 182976 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 182977 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 182978 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 182979 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 182980 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 182981 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 182982 | GIR_RootConstrainSelectedInstOperands, |
| 182983 | // GIR_Coverage, 6471, |
| 182984 | GIR_EraseRootFromParent_Done, |
| 182985 | // Label 8593: @574164 |
| 182986 | GIM_Try, /*On fail goto*//*Label 8594*/ GIMT_Encode4(574254), // Rule ID 6461 // |
| 182987 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 182988 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 182989 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 182990 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 182991 | // MIs[0] offset |
| 182992 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 182993 | // MIs[0] format |
| 182994 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 182995 | // MIs[0] auxiliary |
| 182996 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 182997 | // MIs[0] Operand 8 |
| 182998 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 182999 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183000 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183001 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_OFFEN), |
| 183002 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183003 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183004 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183005 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183006 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183007 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183008 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183009 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183010 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183011 | GIR_RootConstrainSelectedInstOperands, |
| 183012 | // GIR_Coverage, 6461, |
| 183013 | GIR_EraseRootFromParent_Done, |
| 183014 | // Label 8594: @574254 |
| 183015 | GIM_Try, /*On fail goto*//*Label 8595*/ GIMT_Encode4(574344), // Rule ID 6465 // |
| 183016 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183017 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 183018 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183019 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183020 | // MIs[0] offset |
| 183021 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183022 | // MIs[0] format |
| 183023 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183024 | // MIs[0] auxiliary |
| 183025 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183026 | // MIs[0] Operand 8 |
| 183027 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183028 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183029 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] })<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183030 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_OFFEN), |
| 183031 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183032 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183033 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183034 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183035 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183036 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183037 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183038 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183039 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183040 | GIR_RootConstrainSelectedInstOperands, |
| 183041 | // GIR_Coverage, 6465, |
| 183042 | GIR_EraseRootFromParent_Done, |
| 183043 | // Label 8595: @574344 |
| 183044 | GIM_Try, /*On fail goto*//*Label 8596*/ GIMT_Encode4(574427), // Rule ID 6469 // |
| 183045 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 183046 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183047 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183048 | // MIs[0] offset |
| 183049 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183050 | // MIs[0] format |
| 183051 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183052 | // MIs[0] auxiliary |
| 183053 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183054 | // MIs[0] Operand 8 |
| 183055 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183056 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183057 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183058 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_OFFEN), |
| 183059 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183060 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183061 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183062 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183063 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183065 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183067 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183068 | GIR_RootConstrainSelectedInstOperands, |
| 183069 | // GIR_Coverage, 6469, |
| 183070 | GIR_EraseRootFromParent_Done, |
| 183071 | // Label 8596: @574427 |
| 183072 | GIM_Try, /*On fail goto*//*Label 8597*/ GIMT_Encode4(574510), // Rule ID 6473 // |
| 183073 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183074 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183075 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183076 | // MIs[0] offset |
| 183077 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183078 | // MIs[0] format |
| 183079 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183080 | // MIs[0] auxiliary |
| 183081 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183082 | // MIs[0] Operand 8 |
| 183083 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183084 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183085 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183086 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_OFFEN), |
| 183087 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183088 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183089 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183090 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183091 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183092 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183093 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183094 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183095 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183096 | GIR_RootConstrainSelectedInstOperands, |
| 183097 | // GIR_Coverage, 6473, |
| 183098 | GIR_EraseRootFromParent_Done, |
| 183099 | // Label 8597: @574510 |
| 183100 | GIM_Try, /*On fail goto*//*Label 8598*/ GIMT_Encode4(574592), // Rule ID 6460 // |
| 183101 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 183102 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 183103 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183104 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183105 | // MIs[0] offset |
| 183106 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183107 | // MIs[0] format |
| 183108 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183109 | // MIs[0] auxiliary |
| 183110 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183111 | // MIs[0] Operand 8 |
| 183112 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183113 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183114 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183115 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_IDXEN), |
| 183116 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183117 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183118 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183119 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183120 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183121 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183122 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183123 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183124 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183125 | GIR_RootConstrainSelectedInstOperands, |
| 183126 | // GIR_Coverage, 6460, |
| 183127 | GIR_EraseRootFromParent_Done, |
| 183128 | // Label 8598: @574592 |
| 183129 | GIM_Try, /*On fail goto*//*Label 8599*/ GIMT_Encode4(574674), // Rule ID 6464 // |
| 183130 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183131 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 183132 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183133 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183134 | // MIs[0] offset |
| 183135 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183136 | // MIs[0] format |
| 183137 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183138 | // MIs[0] auxiliary |
| 183139 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183140 | // MIs[0] Operand 8 |
| 183141 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183142 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183143 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183144 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_IDXEN), |
| 183145 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183146 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183147 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183148 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183149 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183150 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183151 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183152 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183153 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183154 | GIR_RootConstrainSelectedInstOperands, |
| 183155 | // GIR_Coverage, 6464, |
| 183156 | GIR_EraseRootFromParent_Done, |
| 183157 | // Label 8599: @574674 |
| 183158 | GIM_Try, /*On fail goto*//*Label 8600*/ GIMT_Encode4(574749), // Rule ID 6468 // |
| 183159 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 183160 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183161 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183162 | // MIs[0] offset |
| 183163 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183164 | // MIs[0] format |
| 183165 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183166 | // MIs[0] auxiliary |
| 183167 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183168 | // MIs[0] Operand 8 |
| 183169 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183170 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183171 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183172 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_IDXEN), |
| 183173 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183174 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183175 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183176 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183177 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183178 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183179 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183180 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183181 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183182 | GIR_RootConstrainSelectedInstOperands, |
| 183183 | // GIR_Coverage, 6468, |
| 183184 | GIR_EraseRootFromParent_Done, |
| 183185 | // Label 8600: @574749 |
| 183186 | GIM_Try, /*On fail goto*//*Label 8601*/ GIMT_Encode4(574824), // Rule ID 6472 // |
| 183187 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183188 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183189 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183190 | // MIs[0] offset |
| 183191 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183192 | // MIs[0] format |
| 183193 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183194 | // MIs[0] auxiliary |
| 183195 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183196 | // MIs[0] Operand 8 |
| 183197 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183198 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183199 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN:{ *:[v4f16] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183200 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_IDXEN), |
| 183201 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183202 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183203 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183204 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183205 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183206 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183207 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183208 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183209 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183210 | GIR_RootConstrainSelectedInstOperands, |
| 183211 | // GIR_Coverage, 6472, |
| 183212 | GIR_EraseRootFromParent_Done, |
| 183213 | // Label 8601: @574824 |
| 183214 | GIM_Try, /*On fail goto*//*Label 8602*/ GIMT_Encode4(574944), // Rule ID 6462 // |
| 183215 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 183216 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 183217 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183218 | // MIs[0] offset |
| 183219 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183220 | // MIs[0] format |
| 183221 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183222 | // MIs[0] auxiliary |
| 183223 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183224 | // MIs[0] Operand 8 |
| 183225 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183227 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183228 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183229 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183230 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183231 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183232 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183233 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183234 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183235 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183236 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183237 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183238 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_BOTHEN), |
| 183239 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183240 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183241 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183242 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183243 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183244 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183245 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183246 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183247 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183248 | GIR_RootConstrainSelectedInstOperands, |
| 183249 | // GIR_Coverage, 6462, |
| 183250 | GIR_EraseRootFromParent_Done, |
| 183251 | // Label 8602: @574944 |
| 183252 | GIM_Try, /*On fail goto*//*Label 8603*/ GIMT_Encode4(575064), // Rule ID 6466 // |
| 183253 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183254 | GIM_CheckMemorySizeEqualTo, /*MI*/0, /*MMO*/0, /*Size*/GIMT_Encode4(6), |
| 183255 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183256 | // MIs[0] offset |
| 183257 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183258 | // MIs[0] format |
| 183259 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183260 | // MIs[0] auxiliary |
| 183261 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183262 | // MIs[0] Operand 8 |
| 183263 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183264 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183265 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] }))<<P:Predicate_anonymous_35125>> => (TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183266 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183267 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183268 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183269 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183270 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183271 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183272 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183273 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183274 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183275 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183276 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZ_VBUFFER_BOTHEN), |
| 183277 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183278 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183279 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183280 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183281 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183282 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183283 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183284 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183285 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183286 | GIR_RootConstrainSelectedInstOperands, |
| 183287 | // GIR_Coverage, 6466, |
| 183288 | GIR_EraseRootFromParent_Done, |
| 183289 | // Label 8603: @575064 |
| 183290 | GIM_Try, /*On fail goto*//*Label 8604*/ GIMT_Encode4(575177), // Rule ID 6470 // |
| 183291 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 183292 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183293 | // MIs[0] offset |
| 183294 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183295 | // MIs[0] format |
| 183296 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183297 | // MIs[0] auxiliary |
| 183298 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183299 | // MIs[0] Operand 8 |
| 183300 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183301 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183302 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183303 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183304 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183305 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183306 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183307 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183308 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183309 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183310 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183311 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183312 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183313 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_BOTHEN), |
| 183314 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183315 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183316 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183317 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183318 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183319 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183320 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183321 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183322 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183323 | GIR_RootConstrainSelectedInstOperands, |
| 183324 | // GIR_Coverage, 6470, |
| 183325 | GIR_EraseRootFromParent_Done, |
| 183326 | // Label 8604: @575177 |
| 183327 | GIM_Try, /*On fail goto*//*Label 8605*/ GIMT_Encode4(575290), // Rule ID 6474 // |
| 183328 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 183329 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_64RegClassID), |
| 183330 | // MIs[0] offset |
| 183331 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183332 | // MIs[0] format |
| 183333 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183334 | // MIs[0] auxiliary |
| 183335 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183336 | // MIs[0] Operand 8 |
| 183337 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183338 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183339 | // (SItbuffer_load_d16:{ *:[v4f16] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN:{ *:[v4f16] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183340 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183341 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183342 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183343 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183344 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183345 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183346 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183347 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183348 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183349 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183350 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_VBUFFER_BOTHEN), |
| 183351 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183352 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183353 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183354 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183355 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183356 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183357 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183358 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183359 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183360 | GIR_RootConstrainSelectedInstOperands, |
| 183361 | // GIR_Coverage, 6474, |
| 183362 | GIR_EraseRootFromParent_Done, |
| 183363 | // Label 8605: @575290 |
| 183364 | GIM_Reject, |
| 183365 | // Label 8589: @575291 |
| 183366 | GIM_Reject, |
| 183367 | // Label 8542: @575292 |
| 183368 | GIM_Try, /*On fail goto*//*Label 8606*/ GIMT_Encode4(575654), |
| 183369 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 183370 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 183371 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 183372 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 183373 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::AV_128RegClassID), |
| 183374 | GIM_Try, /*On fail goto*//*Label 8607*/ GIMT_Encode4(575394), // Rule ID 6431 // |
| 183375 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 183376 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183377 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183378 | // MIs[0] offset |
| 183379 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183380 | // MIs[0] format |
| 183381 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183382 | // MIs[0] auxiliary |
| 183383 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183384 | // MIs[0] Operand 8 |
| 183385 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183386 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183387 | // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET:{ *:[v4i32] } SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFSET), |
| 183389 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183390 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183391 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183392 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183393 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183395 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183396 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183397 | GIR_RootConstrainSelectedInstOperands, |
| 183398 | // GIR_Coverage, 6431, |
| 183399 | GIR_EraseRootFromParent_Done, |
| 183400 | // Label 8607: @575394 |
| 183401 | GIM_Try, /*On fail goto*//*Label 8608*/ GIMT_Encode4(575473), // Rule ID 6433 // |
| 183402 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 183403 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183404 | // MIs[0] offset |
| 183405 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183406 | // MIs[0] format |
| 183407 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183408 | // MIs[0] auxiliary |
| 183409 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183410 | // MIs[0] Operand 8 |
| 183411 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183412 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183413 | // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183414 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_OFFEN), |
| 183415 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183416 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183417 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183418 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183419 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183420 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183421 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183422 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183423 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183424 | GIR_RootConstrainSelectedInstOperands, |
| 183425 | // GIR_Coverage, 6433, |
| 183426 | GIR_EraseRootFromParent_Done, |
| 183427 | // Label 8608: @575473 |
| 183428 | GIM_Try, /*On fail goto*//*Label 8609*/ GIMT_Encode4(575544), // Rule ID 6432 // |
| 183429 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 183430 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183431 | // MIs[0] offset |
| 183432 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183433 | // MIs[0] format |
| 183434 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183435 | // MIs[0] auxiliary |
| 183436 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183437 | // MIs[0] Operand 8 |
| 183438 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183439 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183440 | // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN:{ *:[v4i32] } VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183441 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_IDXEN), |
| 183442 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183443 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183444 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183445 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183446 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183447 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183448 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183449 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183450 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183451 | GIR_RootConstrainSelectedInstOperands, |
| 183452 | // GIR_Coverage, 6432, |
| 183453 | GIR_EraseRootFromParent_Done, |
| 183454 | // Label 8609: @575544 |
| 183455 | GIM_Try, /*On fail goto*//*Label 8610*/ GIMT_Encode4(575653), // Rule ID 6434 // |
| 183456 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 183457 | // MIs[0] offset |
| 183458 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183459 | // MIs[0] format |
| 183460 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183461 | // MIs[0] auxiliary |
| 183462 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183463 | // MIs[0] Operand 8 |
| 183464 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183465 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183466 | // (SItbuffer_load_d16:{ *:[v4i32] } v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN:{ *:[v4i32] } (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183467 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183468 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183469 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183470 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183471 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183472 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183473 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183474 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183475 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183476 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183477 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_LOAD_FORMAT_D16_XYZW_gfx80_BOTHEN), |
| 183478 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdata] |
| 183479 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183480 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183481 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183482 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183483 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183484 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183485 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183486 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183487 | GIR_RootConstrainSelectedInstOperands, |
| 183488 | // GIR_Coverage, 6434, |
| 183489 | GIR_EraseRootFromParent_Done, |
| 183490 | // Label 8610: @575653 |
| 183491 | GIM_Reject, |
| 183492 | // Label 8606: @575654 |
| 183493 | GIM_Reject, |
| 183494 | // Label 8543: @575655 |
| 183495 | GIM_Reject, |
| 183496 | // Label 163: @575656 |
| 183497 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(9), GIMT_Encode2(18), /*)*//*default:*//*Label 8615*/ GIMT_Encode4(581123), |
| 183498 | /*GILLT_s32*//*Label 8611*/ GIMT_Encode4(575703), GIMT_Encode4(0), GIMT_Encode4(0), |
| 183499 | /*GILLT_v2s32*//*Label 8612*/ GIMT_Encode4(577058), GIMT_Encode4(0), |
| 183500 | /*GILLT_v3s32*//*Label 8613*/ GIMT_Encode4(578413), GIMT_Encode4(0), GIMT_Encode4(0), |
| 183501 | /*GILLT_v4s32*//*Label 8614*/ GIMT_Encode4(579768), |
| 183502 | // Label 8611: @575703 |
| 183503 | GIM_Try, /*On fail goto*//*Label 8616*/ GIMT_Encode4(577057), |
| 183504 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 183505 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 183506 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 183507 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 183508 | GIM_Try, /*On fail goto*//*Label 8617*/ GIMT_Encode4(575801), // Rule ID 6475 // |
| 183509 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183510 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183511 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183512 | // MIs[0] offset |
| 183513 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183514 | // MIs[0] format |
| 183515 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183516 | // MIs[0] auxiliary |
| 183517 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183518 | // MIs[0] Operand 8 |
| 183519 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183520 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183521 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183522 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact), |
| 183523 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183524 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183525 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183526 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183527 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183528 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183529 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183530 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183531 | GIR_RootConstrainSelectedInstOperands, |
| 183532 | // GIR_Coverage, 6475, |
| 183533 | GIR_EraseRootFromParent_Done, |
| 183534 | // Label 8617: @575801 |
| 183535 | GIM_Try, /*On fail goto*//*Label 8618*/ GIMT_Encode4(575879), // Rule ID 6479 // |
| 183536 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183537 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183538 | // MIs[0] offset |
| 183539 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183540 | // MIs[0] format |
| 183541 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183542 | // MIs[0] auxiliary |
| 183543 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183544 | // MIs[0] Operand 8 |
| 183545 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183546 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183547 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183548 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact), |
| 183549 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183550 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183551 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183552 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183553 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183554 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183555 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183556 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183557 | GIR_RootConstrainSelectedInstOperands, |
| 183558 | // GIR_Coverage, 6479, |
| 183559 | GIR_EraseRootFromParent_Done, |
| 183560 | // Label 8618: @575879 |
| 183561 | GIM_Try, /*On fail goto*//*Label 8619*/ GIMT_Encode4(575960), // Rule ID 6507 // |
| 183562 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183563 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183564 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183565 | // MIs[0] offset |
| 183566 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183567 | // MIs[0] format |
| 183568 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183569 | // MIs[0] auxiliary |
| 183570 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183571 | // MIs[0] Operand 8 |
| 183572 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183573 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183574 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183575 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFSET_exact), |
| 183576 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183577 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183578 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183579 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183580 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183581 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183582 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183583 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183584 | GIR_RootConstrainSelectedInstOperands, |
| 183585 | // GIR_Coverage, 6507, |
| 183586 | GIR_EraseRootFromParent_Done, |
| 183587 | // Label 8619: @575960 |
| 183588 | GIM_Try, /*On fail goto*//*Label 8620*/ GIMT_Encode4(576038), // Rule ID 6511 // |
| 183589 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183590 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183591 | // MIs[0] offset |
| 183592 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183593 | // MIs[0] format |
| 183594 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183595 | // MIs[0] auxiliary |
| 183596 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183597 | // MIs[0] Operand 8 |
| 183598 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183599 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183600 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183601 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFSET_exact), |
| 183602 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183603 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183604 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183605 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183606 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183607 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183608 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183609 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183610 | GIR_RootConstrainSelectedInstOperands, |
| 183611 | // GIR_Coverage, 6511, |
| 183612 | GIR_EraseRootFromParent_Done, |
| 183613 | // Label 8620: @576038 |
| 183614 | GIM_Try, /*On fail goto*//*Label 8621*/ GIMT_Encode4(576117), // Rule ID 6477 // |
| 183615 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183616 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183617 | // MIs[0] offset |
| 183618 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183619 | // MIs[0] format |
| 183620 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183621 | // MIs[0] auxiliary |
| 183622 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183623 | // MIs[0] Operand 8 |
| 183624 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183625 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183626 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183627 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact), |
| 183628 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183629 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183630 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183631 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183632 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183633 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183634 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183635 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183636 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183637 | GIR_RootConstrainSelectedInstOperands, |
| 183638 | // GIR_Coverage, 6477, |
| 183639 | GIR_EraseRootFromParent_Done, |
| 183640 | // Label 8621: @576117 |
| 183641 | GIM_Try, /*On fail goto*//*Label 8622*/ GIMT_Encode4(576193), // Rule ID 6481 // |
| 183642 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183643 | // MIs[0] offset |
| 183644 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183645 | // MIs[0] format |
| 183646 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183647 | // MIs[0] auxiliary |
| 183648 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183649 | // MIs[0] Operand 8 |
| 183650 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183651 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183652 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183653 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact), |
| 183654 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183655 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183656 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183657 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183658 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183659 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183660 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183661 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183662 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183663 | GIR_RootConstrainSelectedInstOperands, |
| 183664 | // GIR_Coverage, 6481, |
| 183665 | GIR_EraseRootFromParent_Done, |
| 183666 | // Label 8622: @576193 |
| 183667 | GIM_Try, /*On fail goto*//*Label 8623*/ GIMT_Encode4(576272), // Rule ID 6509 // |
| 183668 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183669 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183670 | // MIs[0] offset |
| 183671 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183672 | // MIs[0] format |
| 183673 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183674 | // MIs[0] auxiliary |
| 183675 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183676 | // MIs[0] Operand 8 |
| 183677 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183678 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183679 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183680 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_OFFEN_exact), |
| 183681 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183682 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183683 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183684 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183685 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183686 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183687 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183688 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183689 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183690 | GIR_RootConstrainSelectedInstOperands, |
| 183691 | // GIR_Coverage, 6509, |
| 183692 | GIR_EraseRootFromParent_Done, |
| 183693 | // Label 8623: @576272 |
| 183694 | GIM_Try, /*On fail goto*//*Label 8624*/ GIMT_Encode4(576348), // Rule ID 6513 // |
| 183695 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183696 | // MIs[0] offset |
| 183697 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183698 | // MIs[0] format |
| 183699 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183700 | // MIs[0] auxiliary |
| 183701 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183702 | // MIs[0] Operand 8 |
| 183703 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183704 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183705 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183706 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_OFFEN_exact), |
| 183707 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183708 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 183709 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183710 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183711 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183712 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183713 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183714 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183715 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183716 | GIR_RootConstrainSelectedInstOperands, |
| 183717 | // GIR_Coverage, 6513, |
| 183718 | GIR_EraseRootFromParent_Done, |
| 183719 | // Label 8624: @576348 |
| 183720 | GIM_Try, /*On fail goto*//*Label 8625*/ GIMT_Encode4(576419), // Rule ID 6476 // |
| 183721 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183722 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183723 | // MIs[0] offset |
| 183724 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183725 | // MIs[0] format |
| 183726 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183727 | // MIs[0] auxiliary |
| 183728 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183729 | // MIs[0] Operand 8 |
| 183730 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183731 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183732 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183733 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_exact), |
| 183734 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183735 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183736 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183737 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183738 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183741 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183742 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183743 | GIR_RootConstrainSelectedInstOperands, |
| 183744 | // GIR_Coverage, 6476, |
| 183745 | GIR_EraseRootFromParent_Done, |
| 183746 | // Label 8625: @576419 |
| 183747 | GIM_Try, /*On fail goto*//*Label 8626*/ GIMT_Encode4(576487), // Rule ID 6480 // |
| 183748 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183749 | // MIs[0] offset |
| 183750 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183751 | // MIs[0] format |
| 183752 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183753 | // MIs[0] auxiliary |
| 183754 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183755 | // MIs[0] Operand 8 |
| 183756 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183757 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183758 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183759 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact), |
| 183760 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183761 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183762 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183763 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183764 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183765 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183767 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183768 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183769 | GIR_RootConstrainSelectedInstOperands, |
| 183770 | // GIR_Coverage, 6480, |
| 183771 | GIR_EraseRootFromParent_Done, |
| 183772 | // Label 8626: @576487 |
| 183773 | GIM_Try, /*On fail goto*//*Label 8627*/ GIMT_Encode4(576558), // Rule ID 6508 // |
| 183774 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183775 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183776 | // MIs[0] offset |
| 183777 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183778 | // MIs[0] format |
| 183779 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183780 | // MIs[0] auxiliary |
| 183781 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183782 | // MIs[0] Operand 8 |
| 183783 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183784 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183785 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_IDXEN_exact), |
| 183787 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183788 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183789 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183791 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183793 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183794 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183796 | GIR_RootConstrainSelectedInstOperands, |
| 183797 | // GIR_Coverage, 6508, |
| 183798 | GIR_EraseRootFromParent_Done, |
| 183799 | // Label 8627: @576558 |
| 183800 | GIM_Try, /*On fail goto*//*Label 8628*/ GIMT_Encode4(576626), // Rule ID 6512 // |
| 183801 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183802 | // MIs[0] offset |
| 183803 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183804 | // MIs[0] format |
| 183805 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183806 | // MIs[0] auxiliary |
| 183807 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183808 | // MIs[0] Operand 8 |
| 183809 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183810 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183811 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183812 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_IDXEN_exact), |
| 183813 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183814 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 183815 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183816 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183817 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183818 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183819 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183820 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183821 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183822 | GIR_RootConstrainSelectedInstOperands, |
| 183823 | // GIR_Coverage, 6512, |
| 183824 | GIR_EraseRootFromParent_Done, |
| 183825 | // Label 8628: @576626 |
| 183826 | GIM_Try, /*On fail goto*//*Label 8629*/ GIMT_Encode4(576735), // Rule ID 6478 // |
| 183827 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183828 | // MIs[0] offset |
| 183829 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183830 | // MIs[0] format |
| 183831 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183832 | // MIs[0] auxiliary |
| 183833 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183834 | // MIs[0] Operand 8 |
| 183835 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183836 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183837 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183838 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183839 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183840 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183841 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183842 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183843 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183844 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183845 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183846 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183847 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183848 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_exact), |
| 183849 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183850 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183851 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183852 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183853 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183854 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183856 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183857 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183858 | GIR_RootConstrainSelectedInstOperands, |
| 183859 | // GIR_Coverage, 6478, |
| 183860 | GIR_EraseRootFromParent_Done, |
| 183861 | // Label 8629: @576735 |
| 183862 | GIM_Try, /*On fail goto*//*Label 8630*/ GIMT_Encode4(576841), // Rule ID 6482 // |
| 183863 | // MIs[0] offset |
| 183864 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183865 | // MIs[0] format |
| 183866 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183867 | // MIs[0] auxiliary |
| 183868 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183869 | // MIs[0] Operand 8 |
| 183870 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183871 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183872 | // (SItbuffer_store i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183873 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183874 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183875 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183876 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183877 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183878 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183879 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183880 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183881 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183882 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183883 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact), |
| 183884 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183885 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183886 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183887 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183888 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183889 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183890 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183891 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183892 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183893 | GIR_RootConstrainSelectedInstOperands, |
| 183894 | // GIR_Coverage, 6482, |
| 183895 | GIR_EraseRootFromParent_Done, |
| 183896 | // Label 8630: @576841 |
| 183897 | GIM_Try, /*On fail goto*//*Label 8631*/ GIMT_Encode4(576950), // Rule ID 6510 // |
| 183898 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183899 | // MIs[0] offset |
| 183900 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183901 | // MIs[0] format |
| 183902 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183903 | // MIs[0] auxiliary |
| 183904 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183905 | // MIs[0] Operand 8 |
| 183906 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183907 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183908 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183909 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183910 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183911 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183912 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183913 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183914 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183915 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183916 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183917 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183918 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183919 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_BOTHEN_exact), |
| 183920 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183921 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183922 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183923 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183924 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183925 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183926 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183927 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183928 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183929 | GIR_RootConstrainSelectedInstOperands, |
| 183930 | // GIR_Coverage, 6510, |
| 183931 | GIR_EraseRootFromParent_Done, |
| 183932 | // Label 8631: @576950 |
| 183933 | GIM_Try, /*On fail goto*//*Label 8632*/ GIMT_Encode4(577056), // Rule ID 6514 // |
| 183934 | // MIs[0] offset |
| 183935 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183936 | // MIs[0] format |
| 183937 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183938 | // MIs[0] auxiliary |
| 183939 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183940 | // MIs[0] Operand 8 |
| 183941 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 183942 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183943 | // (SItbuffer_store f32:{ *:[f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183944 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 183945 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 183946 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 183947 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 183948 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 183949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 183950 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 183951 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 183952 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183953 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 183954 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_X_VBUFFER_BOTHEN_exact), |
| 183955 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183956 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 183957 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183959 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183962 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 183964 | GIR_RootConstrainSelectedInstOperands, |
| 183965 | // GIR_Coverage, 6514, |
| 183966 | GIR_EraseRootFromParent_Done, |
| 183967 | // Label 8632: @577056 |
| 183968 | GIM_Reject, |
| 183969 | // Label 8616: @577057 |
| 183970 | GIM_Reject, |
| 183971 | // Label 8612: @577058 |
| 183972 | GIM_Try, /*On fail goto*//*Label 8633*/ GIMT_Encode4(578412), |
| 183973 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 183974 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 183975 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 183976 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 183977 | GIM_Try, /*On fail goto*//*Label 8634*/ GIMT_Encode4(577156), // Rule ID 6483 // |
| 183978 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 183979 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 183980 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 183981 | // MIs[0] offset |
| 183982 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 183983 | // MIs[0] format |
| 183984 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 183985 | // MIs[0] auxiliary |
| 183986 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 183987 | // MIs[0] Operand 8 |
| 183988 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 183989 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 183990 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 183991 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_exact), |
| 183992 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 183993 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 183994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 183995 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 183996 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 183997 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 183998 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 183999 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184000 | GIR_RootConstrainSelectedInstOperands, |
| 184001 | // GIR_Coverage, 6483, |
| 184002 | GIR_EraseRootFromParent_Done, |
| 184003 | // Label 8634: @577156 |
| 184004 | GIM_Try, /*On fail goto*//*Label 8635*/ GIMT_Encode4(577234), // Rule ID 6487 // |
| 184005 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184006 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184007 | // MIs[0] offset |
| 184008 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184009 | // MIs[0] format |
| 184010 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184011 | // MIs[0] auxiliary |
| 184012 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184013 | // MIs[0] Operand 8 |
| 184014 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184015 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184016 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184017 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact), |
| 184018 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184019 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184020 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184021 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184022 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184023 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184024 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184025 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184026 | GIR_RootConstrainSelectedInstOperands, |
| 184027 | // GIR_Coverage, 6487, |
| 184028 | GIR_EraseRootFromParent_Done, |
| 184029 | // Label 8635: @577234 |
| 184030 | GIM_Try, /*On fail goto*//*Label 8636*/ GIMT_Encode4(577315), // Rule ID 6515 // |
| 184031 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184032 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184033 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184034 | // MIs[0] offset |
| 184035 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184036 | // MIs[0] format |
| 184037 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184038 | // MIs[0] auxiliary |
| 184039 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184040 | // MIs[0] Operand 8 |
| 184041 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184042 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184043 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184044 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFSET_exact), |
| 184045 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184046 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184047 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184048 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184049 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184050 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184051 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184052 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184053 | GIR_RootConstrainSelectedInstOperands, |
| 184054 | // GIR_Coverage, 6515, |
| 184055 | GIR_EraseRootFromParent_Done, |
| 184056 | // Label 8636: @577315 |
| 184057 | GIM_Try, /*On fail goto*//*Label 8637*/ GIMT_Encode4(577393), // Rule ID 6519 // |
| 184058 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184059 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184060 | // MIs[0] offset |
| 184061 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184062 | // MIs[0] format |
| 184063 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184064 | // MIs[0] auxiliary |
| 184065 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184066 | // MIs[0] Operand 8 |
| 184067 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184068 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184069 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v2f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184070 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFSET_exact), |
| 184071 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184072 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184073 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184074 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184075 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184076 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184077 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184078 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184079 | GIR_RootConstrainSelectedInstOperands, |
| 184080 | // GIR_Coverage, 6519, |
| 184081 | GIR_EraseRootFromParent_Done, |
| 184082 | // Label 8637: @577393 |
| 184083 | GIM_Try, /*On fail goto*//*Label 8638*/ GIMT_Encode4(577472), // Rule ID 6485 // |
| 184084 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184085 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184086 | // MIs[0] offset |
| 184087 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184088 | // MIs[0] format |
| 184089 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184090 | // MIs[0] auxiliary |
| 184091 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184092 | // MIs[0] Operand 8 |
| 184093 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184094 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184095 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184096 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_exact), |
| 184097 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184098 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184099 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184100 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184101 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184102 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184103 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184104 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184105 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184106 | GIR_RootConstrainSelectedInstOperands, |
| 184107 | // GIR_Coverage, 6485, |
| 184108 | GIR_EraseRootFromParent_Done, |
| 184109 | // Label 8638: @577472 |
| 184110 | GIM_Try, /*On fail goto*//*Label 8639*/ GIMT_Encode4(577548), // Rule ID 6489 // |
| 184111 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184112 | // MIs[0] offset |
| 184113 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184114 | // MIs[0] format |
| 184115 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184116 | // MIs[0] auxiliary |
| 184117 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184118 | // MIs[0] Operand 8 |
| 184119 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184120 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184121 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184122 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact), |
| 184123 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184124 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184125 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184126 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184127 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184128 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184129 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184130 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184131 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184132 | GIR_RootConstrainSelectedInstOperands, |
| 184133 | // GIR_Coverage, 6489, |
| 184134 | GIR_EraseRootFromParent_Done, |
| 184135 | // Label 8639: @577548 |
| 184136 | GIM_Try, /*On fail goto*//*Label 8640*/ GIMT_Encode4(577627), // Rule ID 6517 // |
| 184137 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184138 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184139 | // MIs[0] offset |
| 184140 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184141 | // MIs[0] format |
| 184142 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184143 | // MIs[0] auxiliary |
| 184144 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184145 | // MIs[0] Operand 8 |
| 184146 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184147 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184148 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184149 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_OFFEN_exact), |
| 184150 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184151 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184152 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184153 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184154 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184155 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184156 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184157 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184158 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184159 | GIR_RootConstrainSelectedInstOperands, |
| 184160 | // GIR_Coverage, 6517, |
| 184161 | GIR_EraseRootFromParent_Done, |
| 184162 | // Label 8640: @577627 |
| 184163 | GIM_Try, /*On fail goto*//*Label 8641*/ GIMT_Encode4(577703), // Rule ID 6521 // |
| 184164 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184165 | // MIs[0] offset |
| 184166 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184167 | // MIs[0] format |
| 184168 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184169 | // MIs[0] auxiliary |
| 184170 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184171 | // MIs[0] Operand 8 |
| 184172 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184173 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184174 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184175 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_OFFEN_exact), |
| 184176 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184177 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184178 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184179 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184180 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184181 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184182 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184183 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184184 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184185 | GIR_RootConstrainSelectedInstOperands, |
| 184186 | // GIR_Coverage, 6521, |
| 184187 | GIR_EraseRootFromParent_Done, |
| 184188 | // Label 8641: @577703 |
| 184189 | GIM_Try, /*On fail goto*//*Label 8642*/ GIMT_Encode4(577774), // Rule ID 6484 // |
| 184190 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184191 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184192 | // MIs[0] offset |
| 184193 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184194 | // MIs[0] format |
| 184195 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184196 | // MIs[0] auxiliary |
| 184197 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184198 | // MIs[0] Operand 8 |
| 184199 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184200 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184201 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184202 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_exact), |
| 184203 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184204 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184205 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184206 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184207 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184208 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184209 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184210 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184211 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184212 | GIR_RootConstrainSelectedInstOperands, |
| 184213 | // GIR_Coverage, 6484, |
| 184214 | GIR_EraseRootFromParent_Done, |
| 184215 | // Label 8642: @577774 |
| 184216 | GIM_Try, /*On fail goto*//*Label 8643*/ GIMT_Encode4(577842), // Rule ID 6488 // |
| 184217 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184218 | // MIs[0] offset |
| 184219 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184220 | // MIs[0] format |
| 184221 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184222 | // MIs[0] auxiliary |
| 184223 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184224 | // MIs[0] Operand 8 |
| 184225 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184226 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184227 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184228 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact), |
| 184229 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184230 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184231 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184232 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184233 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184234 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184235 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184236 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184237 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184238 | GIR_RootConstrainSelectedInstOperands, |
| 184239 | // GIR_Coverage, 6488, |
| 184240 | GIR_EraseRootFromParent_Done, |
| 184241 | // Label 8643: @577842 |
| 184242 | GIM_Try, /*On fail goto*//*Label 8644*/ GIMT_Encode4(577913), // Rule ID 6516 // |
| 184243 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184244 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184245 | // MIs[0] offset |
| 184246 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184247 | // MIs[0] format |
| 184248 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184249 | // MIs[0] auxiliary |
| 184250 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184251 | // MIs[0] Operand 8 |
| 184252 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184253 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184254 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_IDXEN_exact), |
| 184256 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184257 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184258 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184260 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184261 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184262 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184263 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184264 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184265 | GIR_RootConstrainSelectedInstOperands, |
| 184266 | // GIR_Coverage, 6516, |
| 184267 | GIR_EraseRootFromParent_Done, |
| 184268 | // Label 8644: @577913 |
| 184269 | GIM_Try, /*On fail goto*//*Label 8645*/ GIMT_Encode4(577981), // Rule ID 6520 // |
| 184270 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184271 | // MIs[0] offset |
| 184272 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184273 | // MIs[0] format |
| 184274 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184275 | // MIs[0] auxiliary |
| 184276 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184277 | // MIs[0] Operand 8 |
| 184278 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184279 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184280 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184281 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_IDXEN_exact), |
| 184282 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184283 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184284 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184285 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184286 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184287 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184288 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184289 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184290 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184291 | GIR_RootConstrainSelectedInstOperands, |
| 184292 | // GIR_Coverage, 6520, |
| 184293 | GIR_EraseRootFromParent_Done, |
| 184294 | // Label 8645: @577981 |
| 184295 | GIM_Try, /*On fail goto*//*Label 8646*/ GIMT_Encode4(578090), // Rule ID 6486 // |
| 184296 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184297 | // MIs[0] offset |
| 184298 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184299 | // MIs[0] format |
| 184300 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184301 | // MIs[0] auxiliary |
| 184302 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184303 | // MIs[0] Operand 8 |
| 184304 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184305 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184306 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184307 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184308 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184309 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184310 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184311 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184312 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184313 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184314 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184315 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184316 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184317 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_exact), |
| 184318 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184319 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184320 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184321 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184322 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184323 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184324 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184325 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184326 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184327 | GIR_RootConstrainSelectedInstOperands, |
| 184328 | // GIR_Coverage, 6486, |
| 184329 | GIR_EraseRootFromParent_Done, |
| 184330 | // Label 8646: @578090 |
| 184331 | GIM_Try, /*On fail goto*//*Label 8647*/ GIMT_Encode4(578196), // Rule ID 6490 // |
| 184332 | // MIs[0] offset |
| 184333 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184334 | // MIs[0] format |
| 184335 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184336 | // MIs[0] auxiliary |
| 184337 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184338 | // MIs[0] Operand 8 |
| 184339 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184340 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184341 | // (SItbuffer_store v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184342 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184343 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184344 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184345 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184346 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184347 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184348 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184349 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184350 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184351 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184352 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact), |
| 184353 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184354 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184355 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184356 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184357 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184358 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184359 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184360 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184361 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184362 | GIR_RootConstrainSelectedInstOperands, |
| 184363 | // GIR_Coverage, 6490, |
| 184364 | GIR_EraseRootFromParent_Done, |
| 184365 | // Label 8647: @578196 |
| 184366 | GIM_Try, /*On fail goto*//*Label 8648*/ GIMT_Encode4(578305), // Rule ID 6518 // |
| 184367 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184368 | // MIs[0] offset |
| 184369 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184370 | // MIs[0] format |
| 184371 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184372 | // MIs[0] auxiliary |
| 184373 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184374 | // MIs[0] Operand 8 |
| 184375 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184376 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184377 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184378 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184379 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184380 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184381 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184382 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184383 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184384 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184385 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184386 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184387 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184388 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_BOTHEN_exact), |
| 184389 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184390 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184391 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184392 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184393 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184394 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184395 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184396 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184397 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184398 | GIR_RootConstrainSelectedInstOperands, |
| 184399 | // GIR_Coverage, 6518, |
| 184400 | GIR_EraseRootFromParent_Done, |
| 184401 | // Label 8648: @578305 |
| 184402 | GIM_Try, /*On fail goto*//*Label 8649*/ GIMT_Encode4(578411), // Rule ID 6522 // |
| 184403 | // MIs[0] offset |
| 184404 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184405 | // MIs[0] format |
| 184406 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184407 | // MIs[0] auxiliary |
| 184408 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184409 | // MIs[0] Operand 8 |
| 184410 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184411 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184412 | // (SItbuffer_store v2f32:{ *:[v2f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v2f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184413 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184414 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184415 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184416 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184417 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184418 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184419 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184420 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184421 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184422 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184423 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XY_VBUFFER_BOTHEN_exact), |
| 184424 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184425 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184426 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184427 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184428 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184429 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184430 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184432 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184433 | GIR_RootConstrainSelectedInstOperands, |
| 184434 | // GIR_Coverage, 6522, |
| 184435 | GIR_EraseRootFromParent_Done, |
| 184436 | // Label 8649: @578411 |
| 184437 | GIM_Reject, |
| 184438 | // Label 8633: @578412 |
| 184439 | GIM_Reject, |
| 184440 | // Label 8613: @578413 |
| 184441 | GIM_Try, /*On fail goto*//*Label 8650*/ GIMT_Encode4(579767), |
| 184442 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 184443 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 184444 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 184445 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 184446 | GIM_Try, /*On fail goto*//*Label 8651*/ GIMT_Encode4(578511), // Rule ID 6491 // |
| 184447 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184448 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184449 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184450 | // MIs[0] offset |
| 184451 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184452 | // MIs[0] format |
| 184453 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184454 | // MIs[0] auxiliary |
| 184455 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184456 | // MIs[0] Operand 8 |
| 184457 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184458 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184459 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184460 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact), |
| 184461 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184462 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184463 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184464 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184465 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184466 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184468 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184469 | GIR_RootConstrainSelectedInstOperands, |
| 184470 | // GIR_Coverage, 6491, |
| 184471 | GIR_EraseRootFromParent_Done, |
| 184472 | // Label 8651: @578511 |
| 184473 | GIM_Try, /*On fail goto*//*Label 8652*/ GIMT_Encode4(578589), // Rule ID 6495 // |
| 184474 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184475 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184476 | // MIs[0] offset |
| 184477 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184478 | // MIs[0] format |
| 184479 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184480 | // MIs[0] auxiliary |
| 184481 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184482 | // MIs[0] Operand 8 |
| 184483 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184484 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184485 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184486 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact), |
| 184487 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184488 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184489 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184490 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184491 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184492 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184493 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184494 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184495 | GIR_RootConstrainSelectedInstOperands, |
| 184496 | // GIR_Coverage, 6495, |
| 184497 | GIR_EraseRootFromParent_Done, |
| 184498 | // Label 8652: @578589 |
| 184499 | GIM_Try, /*On fail goto*//*Label 8653*/ GIMT_Encode4(578670), // Rule ID 6523 // |
| 184500 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184501 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184502 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184503 | // MIs[0] offset |
| 184504 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184505 | // MIs[0] format |
| 184506 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184507 | // MIs[0] auxiliary |
| 184508 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184509 | // MIs[0] Operand 8 |
| 184510 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184511 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184512 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184513 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFSET_exact), |
| 184514 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184515 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184516 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184517 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184518 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184519 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184520 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184521 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184522 | GIR_RootConstrainSelectedInstOperands, |
| 184523 | // GIR_Coverage, 6523, |
| 184524 | GIR_EraseRootFromParent_Done, |
| 184525 | // Label 8653: @578670 |
| 184526 | GIM_Try, /*On fail goto*//*Label 8654*/ GIMT_Encode4(578748), // Rule ID 6527 // |
| 184527 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184528 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184529 | // MIs[0] offset |
| 184530 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184531 | // MIs[0] format |
| 184532 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184533 | // MIs[0] auxiliary |
| 184534 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184535 | // MIs[0] Operand 8 |
| 184536 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184537 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184538 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact anonymous_15874:{ *:[v3f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184539 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFSET_exact), |
| 184540 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184541 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184542 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184543 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184544 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184545 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184546 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184547 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184548 | GIR_RootConstrainSelectedInstOperands, |
| 184549 | // GIR_Coverage, 6527, |
| 184550 | GIR_EraseRootFromParent_Done, |
| 184551 | // Label 8654: @578748 |
| 184552 | GIM_Try, /*On fail goto*//*Label 8655*/ GIMT_Encode4(578827), // Rule ID 6493 // |
| 184553 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184554 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184555 | // MIs[0] offset |
| 184556 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184557 | // MIs[0] format |
| 184558 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184559 | // MIs[0] auxiliary |
| 184560 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184561 | // MIs[0] Operand 8 |
| 184562 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184563 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184564 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184565 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact), |
| 184566 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184567 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184568 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184569 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184570 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184571 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184572 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184573 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184574 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184575 | GIR_RootConstrainSelectedInstOperands, |
| 184576 | // GIR_Coverage, 6493, |
| 184577 | GIR_EraseRootFromParent_Done, |
| 184578 | // Label 8655: @578827 |
| 184579 | GIM_Try, /*On fail goto*//*Label 8656*/ GIMT_Encode4(578903), // Rule ID 6497 // |
| 184580 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184581 | // MIs[0] offset |
| 184582 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184583 | // MIs[0] format |
| 184584 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184585 | // MIs[0] auxiliary |
| 184586 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184587 | // MIs[0] Operand 8 |
| 184588 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184589 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184590 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184591 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact), |
| 184592 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184593 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184594 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184595 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184596 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184597 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184598 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184599 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184600 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184601 | GIR_RootConstrainSelectedInstOperands, |
| 184602 | // GIR_Coverage, 6497, |
| 184603 | GIR_EraseRootFromParent_Done, |
| 184604 | // Label 8656: @578903 |
| 184605 | GIM_Try, /*On fail goto*//*Label 8657*/ GIMT_Encode4(578982), // Rule ID 6525 // |
| 184606 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184607 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184608 | // MIs[0] offset |
| 184609 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184610 | // MIs[0] format |
| 184611 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184612 | // MIs[0] auxiliary |
| 184613 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184614 | // MIs[0] Operand 8 |
| 184615 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184616 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184617 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184618 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_OFFEN_exact), |
| 184619 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184620 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184621 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184622 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184623 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184624 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184625 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184626 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184627 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184628 | GIR_RootConstrainSelectedInstOperands, |
| 184629 | // GIR_Coverage, 6525, |
| 184630 | GIR_EraseRootFromParent_Done, |
| 184631 | // Label 8657: @578982 |
| 184632 | GIM_Try, /*On fail goto*//*Label 8658*/ GIMT_Encode4(579058), // Rule ID 6529 // |
| 184633 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184634 | // MIs[0] offset |
| 184635 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184636 | // MIs[0] format |
| 184637 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184638 | // MIs[0] auxiliary |
| 184639 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184640 | // MIs[0] Operand 8 |
| 184641 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184642 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184643 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184644 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_OFFEN_exact), |
| 184645 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184646 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 184647 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184648 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184649 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184650 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184651 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184652 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184653 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184654 | GIR_RootConstrainSelectedInstOperands, |
| 184655 | // GIR_Coverage, 6529, |
| 184656 | GIR_EraseRootFromParent_Done, |
| 184657 | // Label 8658: @579058 |
| 184658 | GIM_Try, /*On fail goto*//*Label 8659*/ GIMT_Encode4(579129), // Rule ID 6492 // |
| 184659 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184660 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184661 | // MIs[0] offset |
| 184662 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184663 | // MIs[0] format |
| 184664 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184665 | // MIs[0] auxiliary |
| 184666 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184667 | // MIs[0] Operand 8 |
| 184668 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184669 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184670 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184671 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact), |
| 184672 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184673 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184674 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184675 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184676 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184677 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184678 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184679 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184680 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184681 | GIR_RootConstrainSelectedInstOperands, |
| 184682 | // GIR_Coverage, 6492, |
| 184683 | GIR_EraseRootFromParent_Done, |
| 184684 | // Label 8659: @579129 |
| 184685 | GIM_Try, /*On fail goto*//*Label 8660*/ GIMT_Encode4(579197), // Rule ID 6496 // |
| 184686 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184687 | // MIs[0] offset |
| 184688 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184689 | // MIs[0] format |
| 184690 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184691 | // MIs[0] auxiliary |
| 184692 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184693 | // MIs[0] Operand 8 |
| 184694 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184695 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184696 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184697 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact), |
| 184698 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184699 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184700 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184701 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184702 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184704 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184705 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184706 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184707 | GIR_RootConstrainSelectedInstOperands, |
| 184708 | // GIR_Coverage, 6496, |
| 184709 | GIR_EraseRootFromParent_Done, |
| 184710 | // Label 8660: @579197 |
| 184711 | GIM_Try, /*On fail goto*//*Label 8661*/ GIMT_Encode4(579268), // Rule ID 6524 // |
| 184712 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184713 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184714 | // MIs[0] offset |
| 184715 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184716 | // MIs[0] format |
| 184717 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184718 | // MIs[0] auxiliary |
| 184719 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184720 | // MIs[0] Operand 8 |
| 184721 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184722 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184723 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184724 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_IDXEN_exact), |
| 184725 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184726 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184727 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184728 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184729 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184730 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184731 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184732 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184733 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184734 | GIR_RootConstrainSelectedInstOperands, |
| 184735 | // GIR_Coverage, 6524, |
| 184736 | GIR_EraseRootFromParent_Done, |
| 184737 | // Label 8661: @579268 |
| 184738 | GIM_Try, /*On fail goto*//*Label 8662*/ GIMT_Encode4(579336), // Rule ID 6528 // |
| 184739 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184740 | // MIs[0] offset |
| 184741 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184742 | // MIs[0] format |
| 184743 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184744 | // MIs[0] auxiliary |
| 184745 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184746 | // MIs[0] Operand 8 |
| 184747 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184748 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184749 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184750 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_IDXEN_exact), |
| 184751 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184752 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 184753 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184754 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184755 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184756 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184757 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184758 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184759 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184760 | GIR_RootConstrainSelectedInstOperands, |
| 184761 | // GIR_Coverage, 6528, |
| 184762 | GIR_EraseRootFromParent_Done, |
| 184763 | // Label 8662: @579336 |
| 184764 | GIM_Try, /*On fail goto*//*Label 8663*/ GIMT_Encode4(579445), // Rule ID 6494 // |
| 184765 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184766 | // MIs[0] offset |
| 184767 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184768 | // MIs[0] format |
| 184769 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184770 | // MIs[0] auxiliary |
| 184771 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184772 | // MIs[0] Operand 8 |
| 184773 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184774 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184775 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184776 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184777 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184778 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184779 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184780 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184781 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184782 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184783 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184784 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184785 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184786 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact), |
| 184787 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184788 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184789 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184790 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184791 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184792 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184793 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184794 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184795 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184796 | GIR_RootConstrainSelectedInstOperands, |
| 184797 | // GIR_Coverage, 6494, |
| 184798 | GIR_EraseRootFromParent_Done, |
| 184799 | // Label 8663: @579445 |
| 184800 | GIM_Try, /*On fail goto*//*Label 8664*/ GIMT_Encode4(579551), // Rule ID 6498 // |
| 184801 | // MIs[0] offset |
| 184802 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184803 | // MIs[0] format |
| 184804 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184805 | // MIs[0] auxiliary |
| 184806 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184807 | // MIs[0] Operand 8 |
| 184808 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184809 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184810 | // (SItbuffer_store v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184811 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184812 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184813 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184814 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184815 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184816 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184817 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184818 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184819 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184820 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184821 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact), |
| 184822 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184823 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184824 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184825 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184826 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184827 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184830 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184831 | GIR_RootConstrainSelectedInstOperands, |
| 184832 | // GIR_Coverage, 6498, |
| 184833 | GIR_EraseRootFromParent_Done, |
| 184834 | // Label 8664: @579551 |
| 184835 | GIM_Try, /*On fail goto*//*Label 8665*/ GIMT_Encode4(579660), // Rule ID 6526 // |
| 184836 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184837 | // MIs[0] offset |
| 184838 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184839 | // MIs[0] format |
| 184840 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184841 | // MIs[0] auxiliary |
| 184842 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184843 | // MIs[0] Operand 8 |
| 184844 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184845 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184846 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184847 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184848 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184849 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184850 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184851 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184852 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184853 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184854 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184855 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184856 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184857 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_BOTHEN_exact), |
| 184858 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184859 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184860 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184861 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184862 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184863 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184864 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184865 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184866 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184867 | GIR_RootConstrainSelectedInstOperands, |
| 184868 | // GIR_Coverage, 6526, |
| 184869 | GIR_EraseRootFromParent_Done, |
| 184870 | // Label 8665: @579660 |
| 184871 | GIM_Try, /*On fail goto*//*Label 8666*/ GIMT_Encode4(579766), // Rule ID 6530 // |
| 184872 | // MIs[0] offset |
| 184873 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184874 | // MIs[0] format |
| 184875 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184876 | // MIs[0] auxiliary |
| 184877 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184878 | // MIs[0] Operand 8 |
| 184879 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 184880 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184881 | // (SItbuffer_store v3f32:{ *:[v3f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact anonymous_15874:{ *:[v3f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184882 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 184883 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 184884 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 184885 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 184886 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 184887 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 184888 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 184889 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 184890 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184891 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 184892 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZ_VBUFFER_BOTHEN_exact), |
| 184893 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184894 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 184895 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184896 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184897 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184898 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184899 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184901 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184902 | GIR_RootConstrainSelectedInstOperands, |
| 184903 | // GIR_Coverage, 6530, |
| 184904 | GIR_EraseRootFromParent_Done, |
| 184905 | // Label 8666: @579766 |
| 184906 | GIM_Reject, |
| 184907 | // Label 8650: @579767 |
| 184908 | GIM_Reject, |
| 184909 | // Label 8614: @579768 |
| 184910 | GIM_Try, /*On fail goto*//*Label 8667*/ GIMT_Encode4(581122), |
| 184911 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 184912 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 184913 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 184914 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 184915 | GIM_Try, /*On fail goto*//*Label 8668*/ GIMT_Encode4(579866), // Rule ID 6499 // |
| 184916 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184917 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184918 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184919 | // MIs[0] offset |
| 184920 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184921 | // MIs[0] format |
| 184922 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184923 | // MIs[0] auxiliary |
| 184924 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184925 | // MIs[0] Operand 8 |
| 184926 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184927 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184928 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184929 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact), |
| 184930 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184931 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184932 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184933 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184934 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184935 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184936 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184937 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184938 | GIR_RootConstrainSelectedInstOperands, |
| 184939 | // GIR_Coverage, 6499, |
| 184940 | GIR_EraseRootFromParent_Done, |
| 184941 | // Label 8668: @579866 |
| 184942 | GIM_Try, /*On fail goto*//*Label 8669*/ GIMT_Encode4(579944), // Rule ID 6503 // |
| 184943 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184944 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184945 | // MIs[0] offset |
| 184946 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184947 | // MIs[0] format |
| 184948 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184949 | // MIs[0] auxiliary |
| 184950 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184951 | // MIs[0] Operand 8 |
| 184952 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184953 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184954 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184955 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact), |
| 184956 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184957 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184958 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184959 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184960 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184961 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184962 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184963 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184964 | GIR_RootConstrainSelectedInstOperands, |
| 184965 | // GIR_Coverage, 6503, |
| 184966 | GIR_EraseRootFromParent_Done, |
| 184967 | // Label 8669: @579944 |
| 184968 | GIM_Try, /*On fail goto*//*Label 8670*/ GIMT_Encode4(580025), // Rule ID 6531 // |
| 184969 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 184970 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184971 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184972 | // MIs[0] offset |
| 184973 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 184974 | // MIs[0] format |
| 184975 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 184976 | // MIs[0] auxiliary |
| 184977 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 184978 | // MIs[0] Operand 8 |
| 184979 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 184980 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 184981 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 184982 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFSET_exact), |
| 184983 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 184984 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 184985 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 184986 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 184987 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 184988 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 184989 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 184990 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 184991 | GIR_RootConstrainSelectedInstOperands, |
| 184992 | // GIR_Coverage, 6531, |
| 184993 | GIR_EraseRootFromParent_Done, |
| 184994 | // Label 8670: @580025 |
| 184995 | GIM_Try, /*On fail goto*//*Label 8671*/ GIMT_Encode4(580103), // Rule ID 6535 // |
| 184996 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 184997 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 184998 | // MIs[0] offset |
| 184999 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185000 | // MIs[0] format |
| 185001 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185002 | // MIs[0] auxiliary |
| 185003 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185004 | // MIs[0] Operand 8 |
| 185005 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185006 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185007 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact anonymous_15873:{ *:[v4f32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185008 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFSET_exact), |
| 185009 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185010 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185011 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185012 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185013 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185014 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185015 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185016 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185017 | GIR_RootConstrainSelectedInstOperands, |
| 185018 | // GIR_Coverage, 6535, |
| 185019 | GIR_EraseRootFromParent_Done, |
| 185020 | // Label 8671: @580103 |
| 185021 | GIM_Try, /*On fail goto*//*Label 8672*/ GIMT_Encode4(580182), // Rule ID 6501 // |
| 185022 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185023 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185024 | // MIs[0] offset |
| 185025 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185026 | // MIs[0] format |
| 185027 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185028 | // MIs[0] auxiliary |
| 185029 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185030 | // MIs[0] Operand 8 |
| 185031 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185032 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185033 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185034 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact), |
| 185035 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185036 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185037 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185038 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185039 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185040 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185041 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185042 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185043 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185044 | GIR_RootConstrainSelectedInstOperands, |
| 185045 | // GIR_Coverage, 6501, |
| 185046 | GIR_EraseRootFromParent_Done, |
| 185047 | // Label 8672: @580182 |
| 185048 | GIM_Try, /*On fail goto*//*Label 8673*/ GIMT_Encode4(580258), // Rule ID 6505 // |
| 185049 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185050 | // MIs[0] offset |
| 185051 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185052 | // MIs[0] format |
| 185053 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185054 | // MIs[0] auxiliary |
| 185055 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185056 | // MIs[0] Operand 8 |
| 185057 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185058 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185059 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185060 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact), |
| 185061 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185062 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185063 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185064 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185065 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185066 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185067 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185068 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185069 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185070 | GIR_RootConstrainSelectedInstOperands, |
| 185071 | // GIR_Coverage, 6505, |
| 185072 | GIR_EraseRootFromParent_Done, |
| 185073 | // Label 8673: @580258 |
| 185074 | GIM_Try, /*On fail goto*//*Label 8674*/ GIMT_Encode4(580337), // Rule ID 6533 // |
| 185075 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185076 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185077 | // MIs[0] offset |
| 185078 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185079 | // MIs[0] format |
| 185080 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185081 | // MIs[0] auxiliary |
| 185082 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185083 | // MIs[0] Operand 8 |
| 185084 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185085 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185086 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185087 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_OFFEN_exact), |
| 185088 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185089 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185090 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185091 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185092 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185093 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185094 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185095 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185096 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185097 | GIR_RootConstrainSelectedInstOperands, |
| 185098 | // GIR_Coverage, 6533, |
| 185099 | GIR_EraseRootFromParent_Done, |
| 185100 | // Label 8674: @580337 |
| 185101 | GIM_Try, /*On fail goto*//*Label 8675*/ GIMT_Encode4(580413), // Rule ID 6537 // |
| 185102 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185103 | // MIs[0] offset |
| 185104 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185105 | // MIs[0] format |
| 185106 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185107 | // MIs[0] auxiliary |
| 185108 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185109 | // MIs[0] Operand 8 |
| 185110 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185111 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185112 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185113 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_OFFEN_exact), |
| 185114 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185115 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185116 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185117 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185118 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185119 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185120 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185121 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185122 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185123 | GIR_RootConstrainSelectedInstOperands, |
| 185124 | // GIR_Coverage, 6537, |
| 185125 | GIR_EraseRootFromParent_Done, |
| 185126 | // Label 8675: @580413 |
| 185127 | GIM_Try, /*On fail goto*//*Label 8676*/ GIMT_Encode4(580484), // Rule ID 6500 // |
| 185128 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185129 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185130 | // MIs[0] offset |
| 185131 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185132 | // MIs[0] format |
| 185133 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185134 | // MIs[0] auxiliary |
| 185135 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185136 | // MIs[0] Operand 8 |
| 185137 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185138 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185139 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185140 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact), |
| 185141 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185142 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185143 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185144 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185145 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185146 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185147 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185148 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185149 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185150 | GIR_RootConstrainSelectedInstOperands, |
| 185151 | // GIR_Coverage, 6500, |
| 185152 | GIR_EraseRootFromParent_Done, |
| 185153 | // Label 8676: @580484 |
| 185154 | GIM_Try, /*On fail goto*//*Label 8677*/ GIMT_Encode4(580552), // Rule ID 6504 // |
| 185155 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185156 | // MIs[0] offset |
| 185157 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185158 | // MIs[0] format |
| 185159 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185160 | // MIs[0] auxiliary |
| 185161 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185162 | // MIs[0] Operand 8 |
| 185163 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185164 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185165 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185166 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact), |
| 185167 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185168 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185169 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185170 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185171 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185172 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185173 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185174 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185175 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185176 | GIR_RootConstrainSelectedInstOperands, |
| 185177 | // GIR_Coverage, 6504, |
| 185178 | GIR_EraseRootFromParent_Done, |
| 185179 | // Label 8677: @580552 |
| 185180 | GIM_Try, /*On fail goto*//*Label 8678*/ GIMT_Encode4(580623), // Rule ID 6532 // |
| 185181 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185182 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185183 | // MIs[0] offset |
| 185184 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185185 | // MIs[0] format |
| 185186 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185187 | // MIs[0] auxiliary |
| 185188 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185189 | // MIs[0] Operand 8 |
| 185190 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185191 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185192 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185193 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_IDXEN_exact), |
| 185194 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185195 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185196 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185197 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185198 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185199 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185200 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185201 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185202 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185203 | GIR_RootConstrainSelectedInstOperands, |
| 185204 | // GIR_Coverage, 6532, |
| 185205 | GIR_EraseRootFromParent_Done, |
| 185206 | // Label 8678: @580623 |
| 185207 | GIM_Try, /*On fail goto*//*Label 8679*/ GIMT_Encode4(580691), // Rule ID 6536 // |
| 185208 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185209 | // MIs[0] offset |
| 185210 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185211 | // MIs[0] format |
| 185212 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185213 | // MIs[0] auxiliary |
| 185214 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185215 | // MIs[0] Operand 8 |
| 185216 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185217 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185218 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185219 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_IDXEN_exact), |
| 185220 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185221 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185222 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185223 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185224 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185225 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185226 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185227 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185228 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185229 | GIR_RootConstrainSelectedInstOperands, |
| 185230 | // GIR_Coverage, 6536, |
| 185231 | GIR_EraseRootFromParent_Done, |
| 185232 | // Label 8679: @580691 |
| 185233 | GIM_Try, /*On fail goto*//*Label 8680*/ GIMT_Encode4(580800), // Rule ID 6502 // |
| 185234 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185235 | // MIs[0] offset |
| 185236 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185237 | // MIs[0] format |
| 185238 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185239 | // MIs[0] auxiliary |
| 185240 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185241 | // MIs[0] Operand 8 |
| 185242 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185243 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185244 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185245 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185246 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185247 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185248 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185249 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185250 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185251 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185252 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185253 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185254 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185255 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact), |
| 185256 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185257 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185258 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185259 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185260 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185261 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185262 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185263 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185264 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185265 | GIR_RootConstrainSelectedInstOperands, |
| 185266 | // GIR_Coverage, 6502, |
| 185267 | GIR_EraseRootFromParent_Done, |
| 185268 | // Label 8680: @580800 |
| 185269 | GIM_Try, /*On fail goto*//*Label 8681*/ GIMT_Encode4(580906), // Rule ID 6506 // |
| 185270 | // MIs[0] offset |
| 185271 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185272 | // MIs[0] format |
| 185273 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185274 | // MIs[0] auxiliary |
| 185275 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185276 | // MIs[0] Operand 8 |
| 185277 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185278 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185279 | // (SItbuffer_store v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185280 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185281 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185282 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185283 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185284 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185285 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185286 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185287 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185288 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185289 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185290 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact), |
| 185291 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185292 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185293 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185294 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185295 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185296 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185297 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185298 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185299 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185300 | GIR_RootConstrainSelectedInstOperands, |
| 185301 | // GIR_Coverage, 6506, |
| 185302 | GIR_EraseRootFromParent_Done, |
| 185303 | // Label 8681: @580906 |
| 185304 | GIM_Try, /*On fail goto*//*Label 8682*/ GIMT_Encode4(581015), // Rule ID 6534 // |
| 185305 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnrestrictedSOffset), |
| 185306 | // MIs[0] offset |
| 185307 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185308 | // MIs[0] format |
| 185309 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185310 | // MIs[0] auxiliary |
| 185311 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185312 | // MIs[0] Operand 8 |
| 185313 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185314 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185315 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185316 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185317 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185318 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185319 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185320 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185321 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185322 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185323 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185324 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185325 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185326 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_BOTHEN_exact), |
| 185327 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185328 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185329 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185330 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185331 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185332 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185333 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185334 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185335 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185336 | GIR_RootConstrainSelectedInstOperands, |
| 185337 | // GIR_Coverage, 6534, |
| 185338 | GIR_EraseRootFromParent_Done, |
| 185339 | // Label 8682: @581015 |
| 185340 | GIM_Try, /*On fail goto*//*Label 8683*/ GIMT_Encode4(581121), // Rule ID 6538 // |
| 185341 | // MIs[0] offset |
| 185342 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185343 | // MIs[0] format |
| 185344 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185345 | // MIs[0] auxiliary |
| 185346 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185347 | // MIs[0] Operand 8 |
| 185348 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185349 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185350 | // (SItbuffer_store v4f32:{ *:[v4f32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact anonymous_15873:{ *:[v4f32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185351 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185352 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185353 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185354 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185355 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185356 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185357 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185358 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185359 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185360 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185361 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_XYZW_VBUFFER_BOTHEN_exact), |
| 185362 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185363 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185364 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185365 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185366 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185367 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185368 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185369 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185370 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185371 | GIR_RootConstrainSelectedInstOperands, |
| 185372 | // GIR_Coverage, 6538, |
| 185373 | GIR_EraseRootFromParent_Done, |
| 185374 | // Label 8683: @581121 |
| 185375 | GIM_Reject, |
| 185376 | // Label 8667: @581122 |
| 185377 | GIM_Reject, |
| 185378 | // Label 8615: @581123 |
| 185379 | GIM_Reject, |
| 185380 | // Label 164: @581124 |
| 185381 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(18), /*)*//*default:*//*Label 8691*/ GIMT_Encode4(585728), |
| 185382 | /*GILLT_s16*//*Label 8684*/ GIMT_Encode4(581175), |
| 185383 | /*GILLT_s32*//*Label 8685*/ GIMT_Encode4(582214), GIMT_Encode4(0), |
| 185384 | /*GILLT_v2s16*//*Label 8686*/ GIMT_Encode4(583253), |
| 185385 | /*GILLT_v2s32*//*Label 8687*/ GIMT_Encode4(583952), GIMT_Encode4(0), |
| 185386 | /*GILLT_v3s32*//*Label 8688*/ GIMT_Encode4(584311), GIMT_Encode4(0), |
| 185387 | /*GILLT_v4s16*//*Label 8689*/ GIMT_Encode4(584670), |
| 185388 | /*GILLT_v4s32*//*Label 8690*/ GIMT_Encode4(585369), |
| 185389 | // Label 8684: @581175 |
| 185390 | GIM_Try, /*On fail goto*//*Label 8692*/ GIMT_Encode4(582213), |
| 185391 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 185392 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 185393 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 185394 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 185395 | GIM_Try, /*On fail goto*//*Label 8693*/ GIMT_Encode4(581273), // Rule ID 6539 // |
| 185396 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185397 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185398 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185399 | // MIs[0] offset |
| 185400 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185401 | // MIs[0] format |
| 185402 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185403 | // MIs[0] auxiliary |
| 185404 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185405 | // MIs[0] Operand 8 |
| 185406 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185407 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185408 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185409 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact), |
| 185410 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185411 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185412 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185413 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185414 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185415 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185416 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185417 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185418 | GIR_RootConstrainSelectedInstOperands, |
| 185419 | // GIR_Coverage, 6539, |
| 185420 | GIR_EraseRootFromParent_Done, |
| 185421 | // Label 8693: @581273 |
| 185422 | GIM_Try, /*On fail goto*//*Label 8694*/ GIMT_Encode4(581354), // Rule ID 6559 // |
| 185423 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185424 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185425 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185426 | // MIs[0] offset |
| 185427 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185428 | // MIs[0] format |
| 185429 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185430 | // MIs[0] auxiliary |
| 185431 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185432 | // MIs[0] Operand 8 |
| 185433 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185434 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185435 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185436 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact), |
| 185437 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185438 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185439 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185440 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185441 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185442 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185443 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185444 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185445 | GIR_RootConstrainSelectedInstOperands, |
| 185446 | // GIR_Coverage, 6559, |
| 185447 | GIR_EraseRootFromParent_Done, |
| 185448 | // Label 8694: @581354 |
| 185449 | GIM_Try, /*On fail goto*//*Label 8695*/ GIMT_Encode4(581435), // Rule ID 6563 // |
| 185450 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185451 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185452 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185453 | // MIs[0] offset |
| 185454 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185455 | // MIs[0] format |
| 185456 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185457 | // MIs[0] auxiliary |
| 185458 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185459 | // MIs[0] Operand 8 |
| 185460 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185461 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185462 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185463 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact), |
| 185464 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185465 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185466 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185467 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185469 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185470 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185471 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185472 | GIR_RootConstrainSelectedInstOperands, |
| 185473 | // GIR_Coverage, 6563, |
| 185474 | GIR_EraseRootFromParent_Done, |
| 185475 | // Label 8695: @581435 |
| 185476 | GIM_Try, /*On fail goto*//*Label 8696*/ GIMT_Encode4(581514), // Rule ID 6541 // |
| 185477 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185478 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185479 | // MIs[0] offset |
| 185480 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185481 | // MIs[0] format |
| 185482 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185483 | // MIs[0] auxiliary |
| 185484 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185485 | // MIs[0] Operand 8 |
| 185486 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185487 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185488 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185489 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact), |
| 185490 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185491 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185492 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185493 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185494 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185495 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185496 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185497 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185498 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185499 | GIR_RootConstrainSelectedInstOperands, |
| 185500 | // GIR_Coverage, 6541, |
| 185501 | GIR_EraseRootFromParent_Done, |
| 185502 | // Label 8696: @581514 |
| 185503 | GIM_Try, /*On fail goto*//*Label 8697*/ GIMT_Encode4(581593), // Rule ID 6561 // |
| 185504 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185505 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185506 | // MIs[0] offset |
| 185507 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185508 | // MIs[0] format |
| 185509 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185510 | // MIs[0] auxiliary |
| 185511 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185512 | // MIs[0] Operand 8 |
| 185513 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185514 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185515 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185516 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact), |
| 185517 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185518 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185519 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185520 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185521 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185522 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185523 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185524 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185525 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185526 | GIR_RootConstrainSelectedInstOperands, |
| 185527 | // GIR_Coverage, 6561, |
| 185528 | GIR_EraseRootFromParent_Done, |
| 185529 | // Label 8697: @581593 |
| 185530 | GIM_Try, /*On fail goto*//*Label 8698*/ GIMT_Encode4(581672), // Rule ID 6565 // |
| 185531 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185532 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185533 | // MIs[0] offset |
| 185534 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185535 | // MIs[0] format |
| 185536 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185537 | // MIs[0] auxiliary |
| 185538 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185539 | // MIs[0] Operand 8 |
| 185540 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185541 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185542 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185543 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact), |
| 185544 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185545 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185546 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185547 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185548 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185549 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185550 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185551 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185552 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185553 | GIR_RootConstrainSelectedInstOperands, |
| 185554 | // GIR_Coverage, 6565, |
| 185555 | GIR_EraseRootFromParent_Done, |
| 185556 | // Label 8698: @581672 |
| 185557 | GIM_Try, /*On fail goto*//*Label 8699*/ GIMT_Encode4(581743), // Rule ID 6540 // |
| 185558 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185559 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185560 | // MIs[0] offset |
| 185561 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185562 | // MIs[0] format |
| 185563 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185564 | // MIs[0] auxiliary |
| 185565 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185566 | // MIs[0] Operand 8 |
| 185567 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185568 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185569 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185570 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact), |
| 185571 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185572 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185573 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185574 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185575 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185576 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185577 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185578 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185579 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185580 | GIR_RootConstrainSelectedInstOperands, |
| 185581 | // GIR_Coverage, 6540, |
| 185582 | GIR_EraseRootFromParent_Done, |
| 185583 | // Label 8699: @581743 |
| 185584 | GIM_Try, /*On fail goto*//*Label 8700*/ GIMT_Encode4(581814), // Rule ID 6560 // |
| 185585 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185586 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185587 | // MIs[0] offset |
| 185588 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185589 | // MIs[0] format |
| 185590 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185591 | // MIs[0] auxiliary |
| 185592 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185593 | // MIs[0] Operand 8 |
| 185594 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185595 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185596 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185597 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact), |
| 185598 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185599 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185600 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185601 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185602 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185603 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185604 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185605 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185606 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185607 | GIR_RootConstrainSelectedInstOperands, |
| 185608 | // GIR_Coverage, 6560, |
| 185609 | GIR_EraseRootFromParent_Done, |
| 185610 | // Label 8700: @581814 |
| 185611 | GIM_Try, /*On fail goto*//*Label 8701*/ GIMT_Encode4(581885), // Rule ID 6564 // |
| 185612 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185613 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185614 | // MIs[0] offset |
| 185615 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185616 | // MIs[0] format |
| 185617 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185618 | // MIs[0] auxiliary |
| 185619 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185620 | // MIs[0] Operand 8 |
| 185621 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185623 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact), |
| 185625 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185626 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185627 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185628 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185629 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185630 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185631 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185632 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185633 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185634 | GIR_RootConstrainSelectedInstOperands, |
| 185635 | // GIR_Coverage, 6564, |
| 185636 | GIR_EraseRootFromParent_Done, |
| 185637 | // Label 8701: @581885 |
| 185638 | GIM_Try, /*On fail goto*//*Label 8702*/ GIMT_Encode4(581994), // Rule ID 6542 // |
| 185639 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185640 | // MIs[0] offset |
| 185641 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185642 | // MIs[0] format |
| 185643 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185644 | // MIs[0] auxiliary |
| 185645 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185646 | // MIs[0] Operand 8 |
| 185647 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185648 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185649 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185650 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185651 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185652 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185653 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185654 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185655 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185656 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185657 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185658 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185659 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185660 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact), |
| 185661 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185662 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185663 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185664 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185665 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185666 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185667 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185668 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185669 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185670 | GIR_RootConstrainSelectedInstOperands, |
| 185671 | // GIR_Coverage, 6542, |
| 185672 | GIR_EraseRootFromParent_Done, |
| 185673 | // Label 8702: @581994 |
| 185674 | GIM_Try, /*On fail goto*//*Label 8703*/ GIMT_Encode4(582103), // Rule ID 6562 // |
| 185675 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185676 | // MIs[0] offset |
| 185677 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185678 | // MIs[0] format |
| 185679 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185680 | // MIs[0] auxiliary |
| 185681 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185682 | // MIs[0] Operand 8 |
| 185683 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185684 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185685 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185686 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185687 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185688 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185689 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185690 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185691 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185692 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185693 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185694 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185695 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185696 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact), |
| 185697 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185698 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185699 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185700 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185701 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185702 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185703 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185704 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185705 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185706 | GIR_RootConstrainSelectedInstOperands, |
| 185707 | // GIR_Coverage, 6562, |
| 185708 | GIR_EraseRootFromParent_Done, |
| 185709 | // Label 8703: @582103 |
| 185710 | GIM_Try, /*On fail goto*//*Label 8704*/ GIMT_Encode4(582212), // Rule ID 6566 // |
| 185711 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185712 | // MIs[0] offset |
| 185713 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185714 | // MIs[0] format |
| 185715 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185716 | // MIs[0] auxiliary |
| 185717 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185718 | // MIs[0] Operand 8 |
| 185719 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185720 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185721 | // (SItbuffer_store_d16 f16:{ *:[f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185722 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 185723 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 185724 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 185725 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 185726 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 185727 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 185728 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 185729 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 185730 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185731 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 185732 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact), |
| 185733 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185734 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 185735 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185736 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185737 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185738 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185740 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185741 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185742 | GIR_RootConstrainSelectedInstOperands, |
| 185743 | // GIR_Coverage, 6566, |
| 185744 | GIR_EraseRootFromParent_Done, |
| 185745 | // Label 8704: @582212 |
| 185746 | GIM_Reject, |
| 185747 | // Label 8692: @582213 |
| 185748 | GIM_Reject, |
| 185749 | // Label 8685: @582214 |
| 185750 | GIM_Try, /*On fail goto*//*Label 8705*/ GIMT_Encode4(583252), |
| 185751 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 185752 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 185753 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 185754 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 185755 | GIM_Try, /*On fail goto*//*Label 8706*/ GIMT_Encode4(582312), // Rule ID 6543 // |
| 185756 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185757 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185758 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185759 | // MIs[0] offset |
| 185760 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185761 | // MIs[0] format |
| 185762 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185763 | // MIs[0] auxiliary |
| 185764 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185765 | // MIs[0] Operand 8 |
| 185766 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185767 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185768 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185769 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFSET_exact), |
| 185770 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185771 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185772 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185773 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185774 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185775 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185776 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185777 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185778 | GIR_RootConstrainSelectedInstOperands, |
| 185779 | // GIR_Coverage, 6543, |
| 185780 | GIR_EraseRootFromParent_Done, |
| 185781 | // Label 8706: @582312 |
| 185782 | GIM_Try, /*On fail goto*//*Label 8707*/ GIMT_Encode4(582393), // Rule ID 6567 // |
| 185783 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185784 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185785 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185786 | // MIs[0] offset |
| 185787 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185788 | // MIs[0] format |
| 185789 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185790 | // MIs[0] auxiliary |
| 185791 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185792 | // MIs[0] Operand 8 |
| 185793 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185794 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185795 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185796 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFSET_exact), |
| 185797 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185798 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185799 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185800 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185802 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185803 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185804 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185805 | GIR_RootConstrainSelectedInstOperands, |
| 185806 | // GIR_Coverage, 6567, |
| 185807 | GIR_EraseRootFromParent_Done, |
| 185808 | // Label 8707: @582393 |
| 185809 | GIM_Try, /*On fail goto*//*Label 8708*/ GIMT_Encode4(582474), // Rule ID 6571 // |
| 185810 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185811 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185812 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185813 | // MIs[0] offset |
| 185814 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185815 | // MIs[0] format |
| 185816 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185817 | // MIs[0] auxiliary |
| 185818 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185819 | // MIs[0] Operand 8 |
| 185820 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185821 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185822 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact anonymous_15876:{ *:[i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185823 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFSET_exact), |
| 185824 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185825 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185826 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185827 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185828 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185829 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185830 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185831 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185832 | GIR_RootConstrainSelectedInstOperands, |
| 185833 | // GIR_Coverage, 6571, |
| 185834 | GIR_EraseRootFromParent_Done, |
| 185835 | // Label 8708: @582474 |
| 185836 | GIM_Try, /*On fail goto*//*Label 8709*/ GIMT_Encode4(582553), // Rule ID 6545 // |
| 185837 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185838 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185839 | // MIs[0] offset |
| 185840 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185841 | // MIs[0] format |
| 185842 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185843 | // MIs[0] auxiliary |
| 185844 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185845 | // MIs[0] Operand 8 |
| 185846 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185847 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185848 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185849 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_OFFEN_exact), |
| 185850 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185851 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185852 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185853 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185854 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185855 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185856 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185857 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185858 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185859 | GIR_RootConstrainSelectedInstOperands, |
| 185860 | // GIR_Coverage, 6545, |
| 185861 | GIR_EraseRootFromParent_Done, |
| 185862 | // Label 8709: @582553 |
| 185863 | GIM_Try, /*On fail goto*//*Label 8710*/ GIMT_Encode4(582632), // Rule ID 6569 // |
| 185864 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185865 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185866 | // MIs[0] offset |
| 185867 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185868 | // MIs[0] format |
| 185869 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185870 | // MIs[0] auxiliary |
| 185871 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185872 | // MIs[0] Operand 8 |
| 185873 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185874 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185875 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185876 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_OFFEN_exact), |
| 185877 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185878 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185879 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185880 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185881 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185882 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185883 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185884 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185885 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185886 | GIR_RootConstrainSelectedInstOperands, |
| 185887 | // GIR_Coverage, 6569, |
| 185888 | GIR_EraseRootFromParent_Done, |
| 185889 | // Label 8710: @582632 |
| 185890 | GIM_Try, /*On fail goto*//*Label 8711*/ GIMT_Encode4(582711), // Rule ID 6573 // |
| 185891 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185892 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 185893 | // MIs[0] offset |
| 185894 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185895 | // MIs[0] format |
| 185896 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185897 | // MIs[0] auxiliary |
| 185898 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185899 | // MIs[0] Operand 8 |
| 185900 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 185901 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185902 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185903 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_OFFEN_exact), |
| 185904 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185905 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 185906 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185907 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185908 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185909 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185910 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185911 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185912 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185913 | GIR_RootConstrainSelectedInstOperands, |
| 185914 | // GIR_Coverage, 6573, |
| 185915 | GIR_EraseRootFromParent_Done, |
| 185916 | // Label 8711: @582711 |
| 185917 | GIM_Try, /*On fail goto*//*Label 8712*/ GIMT_Encode4(582782), // Rule ID 6544 // |
| 185918 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 185919 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185920 | // MIs[0] offset |
| 185921 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185922 | // MIs[0] format |
| 185923 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185924 | // MIs[0] auxiliary |
| 185925 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185926 | // MIs[0] Operand 8 |
| 185927 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185928 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185929 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185930 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_IDXEN_exact), |
| 185931 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185932 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185933 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185934 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185935 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185936 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185937 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185938 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185939 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185940 | GIR_RootConstrainSelectedInstOperands, |
| 185941 | // GIR_Coverage, 6544, |
| 185942 | GIR_EraseRootFromParent_Done, |
| 185943 | // Label 8712: @582782 |
| 185944 | GIM_Try, /*On fail goto*//*Label 8713*/ GIMT_Encode4(582853), // Rule ID 6568 // |
| 185945 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 185946 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185947 | // MIs[0] offset |
| 185948 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185949 | // MIs[0] format |
| 185950 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185951 | // MIs[0] auxiliary |
| 185952 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185953 | // MIs[0] Operand 8 |
| 185954 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185955 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185956 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185957 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_IDXEN_exact), |
| 185958 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185959 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185960 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185961 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185962 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185963 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185964 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185965 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185966 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185967 | GIR_RootConstrainSelectedInstOperands, |
| 185968 | // GIR_Coverage, 6568, |
| 185969 | GIR_EraseRootFromParent_Done, |
| 185970 | // Label 8713: @582853 |
| 185971 | GIM_Try, /*On fail goto*//*Label 8714*/ GIMT_Encode4(582924), // Rule ID 6572 // |
| 185972 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 185973 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 185974 | // MIs[0] offset |
| 185975 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 185976 | // MIs[0] format |
| 185977 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 185978 | // MIs[0] auxiliary |
| 185979 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 185980 | // MIs[0] Operand 8 |
| 185981 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 185982 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 185983 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact anonymous_15876:{ *:[i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 185984 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_IDXEN_exact), |
| 185985 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 185986 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 185987 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 185988 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 185989 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 185990 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 185991 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 185992 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 185993 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 185994 | GIR_RootConstrainSelectedInstOperands, |
| 185995 | // GIR_Coverage, 6572, |
| 185996 | GIR_EraseRootFromParent_Done, |
| 185997 | // Label 8714: @582924 |
| 185998 | GIM_Try, /*On fail goto*//*Label 8715*/ GIMT_Encode4(583033), // Rule ID 6546 // |
| 185999 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186000 | // MIs[0] offset |
| 186001 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186002 | // MIs[0] format |
| 186003 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186004 | // MIs[0] auxiliary |
| 186005 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186006 | // MIs[0] Operand 8 |
| 186007 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186008 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186009 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186010 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186011 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186012 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186013 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186014 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186015 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186016 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186017 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186018 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186019 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186020 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_gfx80_BOTHEN_exact), |
| 186021 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186022 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186023 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186024 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186025 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186026 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186027 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186028 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186029 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186030 | GIR_RootConstrainSelectedInstOperands, |
| 186031 | // GIR_Coverage, 6546, |
| 186032 | GIR_EraseRootFromParent_Done, |
| 186033 | // Label 8715: @583033 |
| 186034 | GIM_Try, /*On fail goto*//*Label 8716*/ GIMT_Encode4(583142), // Rule ID 6570 // |
| 186035 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186036 | // MIs[0] offset |
| 186037 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186038 | // MIs[0] format |
| 186039 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186040 | // MIs[0] auxiliary |
| 186041 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186042 | // MIs[0] Operand 8 |
| 186043 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186044 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186045 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186046 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186047 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186048 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186049 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186050 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186051 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186052 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186053 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186054 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186055 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186056 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_BOTHEN_exact), |
| 186057 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186058 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186059 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186060 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186061 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186062 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186063 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186064 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186065 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186066 | GIR_RootConstrainSelectedInstOperands, |
| 186067 | // GIR_Coverage, 6570, |
| 186068 | GIR_EraseRootFromParent_Done, |
| 186069 | // Label 8716: @583142 |
| 186070 | GIM_Try, /*On fail goto*//*Label 8717*/ GIMT_Encode4(583251), // Rule ID 6574 // |
| 186071 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186072 | // MIs[0] offset |
| 186073 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186074 | // MIs[0] format |
| 186075 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186076 | // MIs[0] auxiliary |
| 186077 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186078 | // MIs[0] Operand 8 |
| 186079 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186080 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186081 | // (SItbuffer_store_d16 i32:{ *:[i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186082 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186083 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186084 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186085 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186086 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186087 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186088 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186089 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186090 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186091 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186092 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_X_VBUFFER_BOTHEN_exact), |
| 186093 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186094 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186095 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186096 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186097 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186098 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186099 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186100 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186101 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186102 | GIR_RootConstrainSelectedInstOperands, |
| 186103 | // GIR_Coverage, 6574, |
| 186104 | GIR_EraseRootFromParent_Done, |
| 186105 | // Label 8717: @583251 |
| 186106 | GIM_Reject, |
| 186107 | // Label 8705: @583252 |
| 186108 | GIM_Reject, |
| 186109 | // Label 8686: @583253 |
| 186110 | GIM_Try, /*On fail goto*//*Label 8718*/ GIMT_Encode4(583951), |
| 186111 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 186112 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 186113 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 186114 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 186115 | GIM_Try, /*On fail goto*//*Label 8719*/ GIMT_Encode4(583351), // Rule ID 6575 // |
| 186116 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186117 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186118 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186119 | // MIs[0] offset |
| 186120 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186121 | // MIs[0] format |
| 186122 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186123 | // MIs[0] auxiliary |
| 186124 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186125 | // MIs[0] Operand 8 |
| 186126 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186127 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186128 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186129 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFSET_exact), |
| 186130 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186131 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186132 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186133 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186134 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186135 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186136 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186137 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186138 | GIR_RootConstrainSelectedInstOperands, |
| 186139 | // GIR_Coverage, 6575, |
| 186140 | GIR_EraseRootFromParent_Done, |
| 186141 | // Label 8719: @583351 |
| 186142 | GIM_Try, /*On fail goto*//*Label 8720*/ GIMT_Encode4(583432), // Rule ID 6579 // |
| 186143 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186144 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186145 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186146 | // MIs[0] offset |
| 186147 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186148 | // MIs[0] format |
| 186149 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186150 | // MIs[0] auxiliary |
| 186151 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186152 | // MIs[0] Operand 8 |
| 186153 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186154 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186155 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact anonymous_15876:{ *:[v2f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186156 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFSET_exact), |
| 186157 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186158 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186159 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186160 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186161 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186162 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186163 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186164 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186165 | GIR_RootConstrainSelectedInstOperands, |
| 186166 | // GIR_Coverage, 6579, |
| 186167 | GIR_EraseRootFromParent_Done, |
| 186168 | // Label 8720: @583432 |
| 186169 | GIM_Try, /*On fail goto*//*Label 8721*/ GIMT_Encode4(583511), // Rule ID 6577 // |
| 186170 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186171 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186172 | // MIs[0] offset |
| 186173 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186174 | // MIs[0] format |
| 186175 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186176 | // MIs[0] auxiliary |
| 186177 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186178 | // MIs[0] Operand 8 |
| 186179 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186180 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186181 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186182 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_OFFEN_exact), |
| 186183 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186184 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186185 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186186 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186187 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186188 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186189 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186190 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186191 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186192 | GIR_RootConstrainSelectedInstOperands, |
| 186193 | // GIR_Coverage, 6577, |
| 186194 | GIR_EraseRootFromParent_Done, |
| 186195 | // Label 8721: @583511 |
| 186196 | GIM_Try, /*On fail goto*//*Label 8722*/ GIMT_Encode4(583590), // Rule ID 6581 // |
| 186197 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186198 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186199 | // MIs[0] offset |
| 186200 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186201 | // MIs[0] format |
| 186202 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186203 | // MIs[0] auxiliary |
| 186204 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186205 | // MIs[0] Operand 8 |
| 186206 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186207 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186208 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186209 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_OFFEN_exact), |
| 186210 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186211 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186212 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186213 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186214 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186215 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186216 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186217 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186218 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186219 | GIR_RootConstrainSelectedInstOperands, |
| 186220 | // GIR_Coverage, 6581, |
| 186221 | GIR_EraseRootFromParent_Done, |
| 186222 | // Label 8722: @583590 |
| 186223 | GIM_Try, /*On fail goto*//*Label 8723*/ GIMT_Encode4(583661), // Rule ID 6576 // |
| 186224 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186225 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186226 | // MIs[0] offset |
| 186227 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186228 | // MIs[0] format |
| 186229 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186230 | // MIs[0] auxiliary |
| 186231 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186232 | // MIs[0] Operand 8 |
| 186233 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186234 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186235 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186236 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_IDXEN_exact), |
| 186237 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186238 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186239 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186240 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186241 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186242 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186243 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186244 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186245 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186246 | GIR_RootConstrainSelectedInstOperands, |
| 186247 | // GIR_Coverage, 6576, |
| 186248 | GIR_EraseRootFromParent_Done, |
| 186249 | // Label 8723: @583661 |
| 186250 | GIM_Try, /*On fail goto*//*Label 8724*/ GIMT_Encode4(583732), // Rule ID 6580 // |
| 186251 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186252 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186253 | // MIs[0] offset |
| 186254 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186255 | // MIs[0] format |
| 186256 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186257 | // MIs[0] auxiliary |
| 186258 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186259 | // MIs[0] Operand 8 |
| 186260 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186261 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186262 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186263 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_IDXEN_exact), |
| 186264 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186265 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186266 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186267 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186268 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186269 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186270 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186271 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186272 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186273 | GIR_RootConstrainSelectedInstOperands, |
| 186274 | // GIR_Coverage, 6580, |
| 186275 | GIR_EraseRootFromParent_Done, |
| 186276 | // Label 8724: @583732 |
| 186277 | GIM_Try, /*On fail goto*//*Label 8725*/ GIMT_Encode4(583841), // Rule ID 6578 // |
| 186278 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186279 | // MIs[0] offset |
| 186280 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186281 | // MIs[0] format |
| 186282 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186283 | // MIs[0] auxiliary |
| 186284 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186285 | // MIs[0] Operand 8 |
| 186286 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186287 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186288 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186289 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186290 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186291 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186292 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186293 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186294 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186295 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186296 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186297 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186298 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186299 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_BOTHEN_exact), |
| 186300 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186301 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186302 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186303 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186304 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186305 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186306 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186307 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186308 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186309 | GIR_RootConstrainSelectedInstOperands, |
| 186310 | // GIR_Coverage, 6578, |
| 186311 | GIR_EraseRootFromParent_Done, |
| 186312 | // Label 8725: @583841 |
| 186313 | GIM_Try, /*On fail goto*//*Label 8726*/ GIMT_Encode4(583950), // Rule ID 6582 // |
| 186314 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186315 | // MIs[0] offset |
| 186316 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186317 | // MIs[0] format |
| 186318 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186319 | // MIs[0] auxiliary |
| 186320 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186321 | // MIs[0] Operand 8 |
| 186322 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186323 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186324 | // (SItbuffer_store_d16 v2f16:{ *:[v2f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact anonymous_15876:{ *:[v2f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186325 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186326 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186327 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186328 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186329 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186330 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186331 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186332 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186333 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186334 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186335 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_VBUFFER_BOTHEN_exact), |
| 186336 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186337 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186338 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186339 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186340 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186341 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186342 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186343 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186344 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186345 | GIR_RootConstrainSelectedInstOperands, |
| 186346 | // GIR_Coverage, 6582, |
| 186347 | GIR_EraseRootFromParent_Done, |
| 186348 | // Label 8726: @583950 |
| 186349 | GIM_Reject, |
| 186350 | // Label 8718: @583951 |
| 186351 | GIM_Reject, |
| 186352 | // Label 8687: @583952 |
| 186353 | GIM_Try, /*On fail goto*//*Label 8727*/ GIMT_Encode4(584310), |
| 186354 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 186355 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 186356 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 186357 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 186358 | GIM_Try, /*On fail goto*//*Label 8728*/ GIMT_Encode4(584050), // Rule ID 6547 // |
| 186359 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186360 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186361 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186362 | // MIs[0] offset |
| 186363 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186364 | // MIs[0] format |
| 186365 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186366 | // MIs[0] auxiliary |
| 186367 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186368 | // MIs[0] Operand 8 |
| 186369 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186370 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186371 | // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact anonymous_15875:{ *:[v2i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186372 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFSET_exact), |
| 186373 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186374 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186375 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186376 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186377 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186378 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186379 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186380 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186381 | GIR_RootConstrainSelectedInstOperands, |
| 186382 | // GIR_Coverage, 6547, |
| 186383 | GIR_EraseRootFromParent_Done, |
| 186384 | // Label 8728: @584050 |
| 186385 | GIM_Try, /*On fail goto*//*Label 8729*/ GIMT_Encode4(584129), // Rule ID 6549 // |
| 186386 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186387 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186388 | // MIs[0] offset |
| 186389 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186390 | // MIs[0] format |
| 186391 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186392 | // MIs[0] auxiliary |
| 186393 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186394 | // MIs[0] Operand 8 |
| 186395 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186396 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186397 | // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186398 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_OFFEN_exact), |
| 186399 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186400 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186401 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186402 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186403 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186404 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186405 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186406 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186407 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186408 | GIR_RootConstrainSelectedInstOperands, |
| 186409 | // GIR_Coverage, 6549, |
| 186410 | GIR_EraseRootFromParent_Done, |
| 186411 | // Label 8729: @584129 |
| 186412 | GIM_Try, /*On fail goto*//*Label 8730*/ GIMT_Encode4(584200), // Rule ID 6548 // |
| 186413 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186414 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186415 | // MIs[0] offset |
| 186416 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186417 | // MIs[0] format |
| 186418 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186419 | // MIs[0] auxiliary |
| 186420 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186421 | // MIs[0] Operand 8 |
| 186422 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186423 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186424 | // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186425 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_IDXEN_exact), |
| 186426 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186427 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186428 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186429 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186430 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186431 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186432 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186433 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186434 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186435 | GIR_RootConstrainSelectedInstOperands, |
| 186436 | // GIR_Coverage, 6548, |
| 186437 | GIR_EraseRootFromParent_Done, |
| 186438 | // Label 8730: @584200 |
| 186439 | GIM_Try, /*On fail goto*//*Label 8731*/ GIMT_Encode4(584309), // Rule ID 6550 // |
| 186440 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186441 | // MIs[0] offset |
| 186442 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186443 | // MIs[0] format |
| 186444 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186445 | // MIs[0] auxiliary |
| 186446 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186447 | // MIs[0] Operand 8 |
| 186448 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186449 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186450 | // (SItbuffer_store_d16 v2i32:{ *:[v2i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact anonymous_15875:{ *:[v2i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186451 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186452 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186453 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186454 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186455 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186456 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186457 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186458 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186459 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186460 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186461 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XY_gfx80_BOTHEN_exact), |
| 186462 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186463 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186464 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186465 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186466 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186467 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186468 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186469 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186470 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186471 | GIR_RootConstrainSelectedInstOperands, |
| 186472 | // GIR_Coverage, 6550, |
| 186473 | GIR_EraseRootFromParent_Done, |
| 186474 | // Label 8731: @584309 |
| 186475 | GIM_Reject, |
| 186476 | // Label 8727: @584310 |
| 186477 | GIM_Reject, |
| 186478 | // Label 8688: @584311 |
| 186479 | GIM_Try, /*On fail goto*//*Label 8732*/ GIMT_Encode4(584669), |
| 186480 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 186481 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 186482 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 186483 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 186484 | GIM_Try, /*On fail goto*//*Label 8733*/ GIMT_Encode4(584409), // Rule ID 6551 // |
| 186485 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186486 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186487 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186488 | // MIs[0] offset |
| 186489 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186490 | // MIs[0] format |
| 186491 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186492 | // MIs[0] auxiliary |
| 186493 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186494 | // MIs[0] Operand 8 |
| 186495 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186496 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186497 | // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact anonymous_15874:{ *:[v3i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186498 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFSET_exact), |
| 186499 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186500 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186501 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186502 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186503 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186504 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186505 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186506 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186507 | GIR_RootConstrainSelectedInstOperands, |
| 186508 | // GIR_Coverage, 6551, |
| 186509 | GIR_EraseRootFromParent_Done, |
| 186510 | // Label 8733: @584409 |
| 186511 | GIM_Try, /*On fail goto*//*Label 8734*/ GIMT_Encode4(584488), // Rule ID 6553 // |
| 186512 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186513 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186514 | // MIs[0] offset |
| 186515 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186516 | // MIs[0] format |
| 186517 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186518 | // MIs[0] auxiliary |
| 186519 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186520 | // MIs[0] Operand 8 |
| 186521 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186522 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186523 | // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186524 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_OFFEN_exact), |
| 186525 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186526 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186527 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186528 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186529 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186530 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186531 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186532 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186533 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186534 | GIR_RootConstrainSelectedInstOperands, |
| 186535 | // GIR_Coverage, 6553, |
| 186536 | GIR_EraseRootFromParent_Done, |
| 186537 | // Label 8734: @584488 |
| 186538 | GIM_Try, /*On fail goto*//*Label 8735*/ GIMT_Encode4(584559), // Rule ID 6552 // |
| 186539 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186540 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186541 | // MIs[0] offset |
| 186542 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186543 | // MIs[0] format |
| 186544 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186545 | // MIs[0] auxiliary |
| 186546 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186547 | // MIs[0] Operand 8 |
| 186548 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186549 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186550 | // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186551 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_IDXEN_exact), |
| 186552 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186553 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186554 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186555 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186556 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186557 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186558 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186559 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186560 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186561 | GIR_RootConstrainSelectedInstOperands, |
| 186562 | // GIR_Coverage, 6552, |
| 186563 | GIR_EraseRootFromParent_Done, |
| 186564 | // Label 8735: @584559 |
| 186565 | GIM_Try, /*On fail goto*//*Label 8736*/ GIMT_Encode4(584668), // Rule ID 6554 // |
| 186566 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186567 | // MIs[0] offset |
| 186568 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186569 | // MIs[0] format |
| 186570 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186571 | // MIs[0] auxiliary |
| 186572 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186573 | // MIs[0] Operand 8 |
| 186574 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186575 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186576 | // (SItbuffer_store_d16 v3i32:{ *:[v3i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact anonymous_15874:{ *:[v3i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186577 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186578 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186579 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186580 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186581 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186582 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186583 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186584 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186585 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186586 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186587 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZ_gfx80_BOTHEN_exact), |
| 186588 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186589 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186590 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186591 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186592 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186593 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186594 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186595 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186596 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186597 | GIR_RootConstrainSelectedInstOperands, |
| 186598 | // GIR_Coverage, 6554, |
| 186599 | GIR_EraseRootFromParent_Done, |
| 186600 | // Label 8736: @584668 |
| 186601 | GIM_Reject, |
| 186602 | // Label 8732: @584669 |
| 186603 | GIM_Reject, |
| 186604 | // Label 8689: @584670 |
| 186605 | GIM_Try, /*On fail goto*//*Label 8737*/ GIMT_Encode4(585368), |
| 186606 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 186607 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 186608 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 186609 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 186610 | GIM_Try, /*On fail goto*//*Label 8738*/ GIMT_Encode4(584768), // Rule ID 6591 // |
| 186611 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186612 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186613 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186614 | // MIs[0] offset |
| 186615 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186616 | // MIs[0] format |
| 186617 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186618 | // MIs[0] auxiliary |
| 186619 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186620 | // MIs[0] Operand 8 |
| 186621 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186622 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186623 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186624 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFSET_exact), |
| 186625 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186626 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186627 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186628 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186629 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186630 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186631 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186632 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186633 | GIR_RootConstrainSelectedInstOperands, |
| 186634 | // GIR_Coverage, 6591, |
| 186635 | GIR_EraseRootFromParent_Done, |
| 186636 | // Label 8738: @584768 |
| 186637 | GIM_Try, /*On fail goto*//*Label 8739*/ GIMT_Encode4(584849), // Rule ID 6595 // |
| 186638 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186639 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186640 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186641 | // MIs[0] offset |
| 186642 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186643 | // MIs[0] format |
| 186644 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186645 | // MIs[0] auxiliary |
| 186646 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186647 | // MIs[0] Operand 8 |
| 186648 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186649 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186650 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact anonymous_15875:{ *:[v4f16] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186651 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFSET_exact), |
| 186652 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186653 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186654 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186655 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186656 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186657 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186658 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186659 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186660 | GIR_RootConstrainSelectedInstOperands, |
| 186661 | // GIR_Coverage, 6595, |
| 186662 | GIR_EraseRootFromParent_Done, |
| 186663 | // Label 8739: @584849 |
| 186664 | GIM_Try, /*On fail goto*//*Label 8740*/ GIMT_Encode4(584928), // Rule ID 6593 // |
| 186665 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186666 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186667 | // MIs[0] offset |
| 186668 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186669 | // MIs[0] format |
| 186670 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186671 | // MIs[0] auxiliary |
| 186672 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186673 | // MIs[0] Operand 8 |
| 186674 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186675 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186676 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186677 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_OFFEN_exact), |
| 186678 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186679 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186680 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186681 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186682 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186683 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186684 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186685 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186686 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186687 | GIR_RootConstrainSelectedInstOperands, |
| 186688 | // GIR_Coverage, 6593, |
| 186689 | GIR_EraseRootFromParent_Done, |
| 186690 | // Label 8740: @584928 |
| 186691 | GIM_Try, /*On fail goto*//*Label 8741*/ GIMT_Encode4(585007), // Rule ID 6597 // |
| 186692 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186693 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186694 | // MIs[0] offset |
| 186695 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186696 | // MIs[0] format |
| 186697 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186698 | // MIs[0] auxiliary |
| 186699 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186700 | // MIs[0] Operand 8 |
| 186701 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186702 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186703 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186704 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_OFFEN_exact), |
| 186705 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186706 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186707 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186708 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186709 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186710 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186711 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186712 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186713 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186714 | GIR_RootConstrainSelectedInstOperands, |
| 186715 | // GIR_Coverage, 6597, |
| 186716 | GIR_EraseRootFromParent_Done, |
| 186717 | // Label 8741: @585007 |
| 186718 | GIM_Try, /*On fail goto*//*Label 8742*/ GIMT_Encode4(585078), // Rule ID 6592 // |
| 186719 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186720 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186721 | // MIs[0] offset |
| 186722 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186723 | // MIs[0] format |
| 186724 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186725 | // MIs[0] auxiliary |
| 186726 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186727 | // MIs[0] Operand 8 |
| 186728 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186729 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186730 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186731 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_IDXEN_exact), |
| 186732 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186733 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186734 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186735 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186736 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186737 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186738 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186739 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186740 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186741 | GIR_RootConstrainSelectedInstOperands, |
| 186742 | // GIR_Coverage, 6592, |
| 186743 | GIR_EraseRootFromParent_Done, |
| 186744 | // Label 8742: @585078 |
| 186745 | GIM_Try, /*On fail goto*//*Label 8743*/ GIMT_Encode4(585149), // Rule ID 6596 // |
| 186746 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186747 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186748 | // MIs[0] offset |
| 186749 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186750 | // MIs[0] format |
| 186751 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186752 | // MIs[0] auxiliary |
| 186753 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186754 | // MIs[0] Operand 8 |
| 186755 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186756 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186757 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186758 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_IDXEN_exact), |
| 186759 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186760 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186761 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186762 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186763 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186764 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186765 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186766 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186767 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186768 | GIR_RootConstrainSelectedInstOperands, |
| 186769 | // GIR_Coverage, 6596, |
| 186770 | GIR_EraseRootFromParent_Done, |
| 186771 | // Label 8743: @585149 |
| 186772 | GIM_Try, /*On fail goto*//*Label 8744*/ GIMT_Encode4(585258), // Rule ID 6594 // |
| 186773 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem_HasUnrestrictedSOffset), |
| 186774 | // MIs[0] offset |
| 186775 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186776 | // MIs[0] format |
| 186777 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186778 | // MIs[0] auxiliary |
| 186779 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186780 | // MIs[0] Operand 8 |
| 186781 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186782 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186783 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186784 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186785 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186786 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186787 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186788 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186789 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186790 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186791 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186792 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186793 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186794 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_BOTHEN_exact), |
| 186795 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186796 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186797 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186798 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186799 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186800 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186801 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186802 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186803 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186804 | GIR_RootConstrainSelectedInstOperands, |
| 186805 | // GIR_Coverage, 6594, |
| 186806 | GIR_EraseRootFromParent_Done, |
| 186807 | // Label 8744: @585258 |
| 186808 | GIM_Try, /*On fail goto*//*Label 8745*/ GIMT_Encode4(585367), // Rule ID 6598 // |
| 186809 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasPackedD16VMem), |
| 186810 | // MIs[0] offset |
| 186811 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186812 | // MIs[0] format |
| 186813 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186814 | // MIs[0] auxiliary |
| 186815 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186816 | // MIs[0] Operand 8 |
| 186817 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186818 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186819 | // (SItbuffer_store_d16 v4f16:{ *:[v4f16] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact anonymous_15875:{ *:[v4f16] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186820 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186821 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186822 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186823 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186824 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186825 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186826 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186827 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186828 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186829 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186830 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_VBUFFER_BOTHEN_exact), |
| 186831 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186832 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186833 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186834 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186835 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186836 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186837 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186838 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186839 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186840 | GIR_RootConstrainSelectedInstOperands, |
| 186841 | // GIR_Coverage, 6598, |
| 186842 | GIR_EraseRootFromParent_Done, |
| 186843 | // Label 8745: @585367 |
| 186844 | GIM_Reject, |
| 186845 | // Label 8737: @585368 |
| 186846 | GIM_Reject, |
| 186847 | // Label 8690: @585369 |
| 186848 | GIM_Try, /*On fail goto*//*Label 8746*/ GIMT_Encode4(585727), |
| 186849 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_v4s32, |
| 186850 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 186851 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 186852 | GIM_RootCheckType, /*Op*/4, /*Type*/GILLT_s32, |
| 186853 | GIM_Try, /*On fail goto*//*Label 8747*/ GIMT_Encode4(585467), // Rule ID 6555 // |
| 186854 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186855 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186856 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186857 | // MIs[0] offset |
| 186858 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186859 | // MIs[0] format |
| 186860 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186861 | // MIs[0] auxiliary |
| 186862 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186863 | // MIs[0] Operand 8 |
| 186864 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186865 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186866 | // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact anonymous_15873:{ *:[v4i32] }:$vdata, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186867 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFSET_exact), |
| 186868 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186869 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186870 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186871 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186872 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186873 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186874 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186875 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186876 | GIR_RootConstrainSelectedInstOperands, |
| 186877 | // GIR_Coverage, 6555, |
| 186878 | GIR_EraseRootFromParent_Done, |
| 186879 | // Label 8747: @585467 |
| 186880 | GIM_Try, /*On fail goto*//*Label 8748*/ GIMT_Encode4(585546), // Rule ID 6557 // |
| 186881 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186882 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/2, 0, |
| 186883 | // MIs[0] offset |
| 186884 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186885 | // MIs[0] format |
| 186886 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186887 | // MIs[0] auxiliary |
| 186888 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186889 | // MIs[0] Operand 8 |
| 186890 | GIM_CheckLiteralInt, /*MI*/0, /*Op*/8, GIMT_Encode8(0), |
| 186891 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186892 | // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, 0:{ *:[i32] }, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, 0:{ *:[i1] }) => (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$voffset, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186893 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_OFFEN_exact), |
| 186894 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186895 | GIR_RootToRootCopy, /*OpIdx*/3, // voffset |
| 186896 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186897 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186898 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186899 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186900 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186901 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186902 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186903 | GIR_RootConstrainSelectedInstOperands, |
| 186904 | // GIR_Coverage, 6557, |
| 186905 | GIR_EraseRootFromParent_Done, |
| 186906 | // Label 8748: @585546 |
| 186907 | GIM_Try, /*On fail goto*//*Label 8749*/ GIMT_Encode4(585617), // Rule ID 6556 // |
| 186908 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186909 | GIM_CheckConstantInt8, /*MI*/0, /*Op*/3, 0, |
| 186910 | // MIs[0] offset |
| 186911 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186912 | // MIs[0] format |
| 186913 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186914 | // MIs[0] auxiliary |
| 186915 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186916 | // MIs[0] Operand 8 |
| 186917 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186918 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186919 | // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, 0:{ *:[i32] }, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, VGPR_32:{ *:[i32] }:$vindex, SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186920 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_IDXEN_exact), |
| 186921 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186922 | GIR_RootToRootCopy, /*OpIdx*/2, // vindex |
| 186923 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186924 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186925 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186926 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186927 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186928 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186929 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186930 | GIR_RootConstrainSelectedInstOperands, |
| 186931 | // GIR_Coverage, 6556, |
| 186932 | GIR_EraseRootFromParent_Done, |
| 186933 | // Label 8749: @585617 |
| 186934 | GIM_Try, /*On fail goto*//*Label 8750*/ GIMT_Encode4(585726), // Rule ID 6558 // |
| 186935 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_HasUnpackedD16VMem), |
| 186936 | // MIs[0] offset |
| 186937 | GIM_CheckIsImm, /*MI*/0, /*Op*/5, |
| 186938 | // MIs[0] format |
| 186939 | GIM_CheckIsImm, /*MI*/0, /*Op*/6, |
| 186940 | // MIs[0] auxiliary |
| 186941 | GIM_CheckIsImm, /*MI*/0, /*Op*/7, |
| 186942 | // MIs[0] Operand 8 |
| 186943 | GIM_CheckIsImm, /*MI*/0, /*Op*/8, |
| 186944 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/4, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_buf_soffset), |
| 186945 | // (SItbuffer_store_d16 v4i32:{ *:[v4i32] }:$vdata, v4i32:{ *:[v4i32] }:$rsrc, i32:{ *:[i32] }:$vindex, i32:{ *:[i32] }:$voffset, (BUFSOffset:{ *:[i32] } i32:{ *:[i32] }:$soffset), (timm:{ *:[i32] }):$offset, (timm:{ *:[i32] }):$format, (timm:{ *:[i32] }):$auxiliary, (timm:{ *:[i1] })) => (TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact anonymous_15873:{ *:[v4i32] }:$vdata, (REG_SEQUENCE:{ *:[i64] } VReg_64:{ *:[i32] }, VGPR_32:{ *:[i32] }:$vindex, sub0:{ *:[i32] }, VGPR_32:{ *:[i32] }:$voffset, sub1:{ *:[i32] }), SReg_128:{ *:[v4i32] }:$rsrc, SCSrc_b32:{ *:[i32] }:$soffset, (timm:{ *:[i32] }):$offset, (as_i8timm:{ *:[i8] } ?:{ *:[i32] }:$format), (extract_cpol:{ *:[i32] } ?:{ *:[i32] }:$auxiliary), (extract_swz:{ *:[i1] } ?:{ *:[i32] }:$auxiliary)) |
| 186946 | GIR_MakeTempReg, /*TempRegID*/0, /*TypeID*/GILLT_s64, |
| 186947 | GIR_BuildMI, /*InsnID*/1, /*Opcode*/GIMT_Encode2(TargetOpcode::REG_SEQUENCE), |
| 186948 | GIR_AddTempRegister, /*InsnID*/1, /*TempRegID*/0, /*TempRegFlags*/GIMT_Encode2(RegState::Define), |
| 186949 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/2, // vindex |
| 186950 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/3, |
| 186951 | GIR_Copy, /*NewInsnID*/1, /*OldInsnID*/0, /*OpIdx*/3, // voffset |
| 186952 | GIR_AddImm8, /*InsnID*/1, /*SubRegIndex*/11, |
| 186953 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/0, GIMT_Encode2(AMDGPU::VReg_64RegClassID), |
| 186954 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/1, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186955 | GIR_ConstrainOperandRC, /*InsnID*/1, /*Op*/3, GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186956 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::TBUFFER_STORE_FORMAT_D16_XYZW_gfx80_BOTHEN_exact), |
| 186957 | GIR_RootToRootCopy, /*OpIdx*/0, // vdata |
| 186958 | GIR_AddSimpleTempRegister, /*InsnID*/0, /*TempRegID*/0, |
| 186959 | GIR_RootToRootCopy, /*OpIdx*/1, // rsrc |
| 186960 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // soffset |
| 186961 | GIR_RootToRootCopy, /*OpIdx*/5, // offset |
| 186962 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/6, /*OperandRenderer*/GIMT_Encode2(GICR_renderTruncTImm), // format |
| 186963 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractCPol), // auxiliary |
| 186964 | GIR_CustomOperandRenderer, /*InsnID*/0, /*OldInsnID*/0, /*OpIdx*/7, /*OperandRenderer*/GIMT_Encode2(GICR_renderExtractSWZ), // auxiliary |
| 186965 | GIR_MergeMemOperands, /*InsnID*/0, /*NumInsns*/1, /*MergeInsnID's*/0, |
| 186966 | GIR_RootConstrainSelectedInstOperands, |
| 186967 | // GIR_Coverage, 6558, |
| 186968 | GIR_EraseRootFromParent_Done, |
| 186969 | // Label 8750: @585726 |
| 186970 | GIM_Reject, |
| 186971 | // Label 8746: @585727 |
| 186972 | GIM_Reject, |
| 186973 | // Label 8691: @585728 |
| 186974 | GIM_Reject, |
| 186975 | // Label 165: @585729 |
| 186976 | GIM_SwitchType, /*MI*/0, /*Op*/0, /*[*/GIMT_Encode2(8), GIMT_Encode2(10), /*)*//*default:*//*Label 8753*/ GIMT_Encode4(585876), |
| 186977 | /*GILLT_s16*//*Label 8751*/ GIMT_Encode4(585748), |
| 186978 | /*GILLT_s32*//*Label 8752*/ GIMT_Encode4(585834), |
| 186979 | // Label 8751: @585748 |
| 186980 | GIM_Try, /*On fail goto*//*Label 8754*/ GIMT_Encode4(585833), // Rule ID 931 // |
| 186981 | GIM_CheckFeatures, GIMT_Encode2(GIFBS_isGFX9Plus), |
| 186982 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s16, |
| 186983 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s16, |
| 186984 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s16, |
| 186985 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 186986 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 186987 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/2, /*Renderer*/GIMT_Encode2(1), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 186988 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/3, /*Renderer*/GIMT_Encode2(2), GIMT_Encode2(GICP_gi_vop3opselmods), |
| 186989 | // (AMDGPUumed3:{ *:[i16] } (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src0_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src1_modifiers), (VOP3OpSelMods:{ *:[i16] } i16:{ *:[i16] }:$src2, i32:{ *:[i32] }:$src2_modifiers)) => (V_MED3_U16_e64:{ *:[i16] } i32:{ *:[i32] }:$src0_modifiers, i16:{ *:[i16] }:$src0, i32:{ *:[i32] }:$src1_modifiers, i16:{ *:[i16] }:$src1, i32:{ *:[i32] }:$src2_modifiers, i16:{ *:[i16] }:$src2) |
| 186990 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U16_e64), |
| 186991 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 186992 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/1, // src0_modifiers |
| 186993 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 186994 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/1, // src1_modifiers |
| 186995 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(1), /*SubOperand*/0, // src1 |
| 186996 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/1, // src2_modifiers |
| 186997 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(2), /*SubOperand*/0, // src2 |
| 186998 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 186999 | GIR_AddImm8, /*InsnID*/0, /*Imm*/0, |
| 187000 | GIR_RootConstrainSelectedInstOperands, |
| 187001 | // GIR_Coverage, 931, |
| 187002 | GIR_EraseRootFromParent_Done, |
| 187003 | // Label 8754: @585833 |
| 187004 | GIM_Reject, |
| 187005 | // Label 8752: @585834 |
| 187006 | GIM_Try, /*On fail goto*//*Label 8755*/ GIMT_Encode4(585875), // Rule ID 886 // |
| 187007 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 187008 | GIM_RootCheckType, /*Op*/2, /*Type*/GILLT_s32, |
| 187009 | GIM_RootCheckType, /*Op*/3, /*Type*/GILLT_s32, |
| 187010 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 187011 | GIM_CheckComplexPattern, /*MI*/0, /*Op*/1, /*Renderer*/GIMT_Encode2(0), GIMT_Encode2(GICP_gi_vop3mods0), |
| 187012 | // (AMDGPUumed3:{ *:[i32] } (VOP3Mods0:{ *:[i32] } i32:{ *:[i32] }:$src0), i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) => (V_MED3_U32_e64:{ *:[i32] } i32:{ *:[i32] }:$src0, i32:{ *:[i32] }:$src1, i32:{ *:[i32] }:$src2) |
| 187013 | GIR_BuildRootMI, /*Opcode*/GIMT_Encode2(AMDGPU::V_MED3_U32_e64), |
| 187014 | GIR_RootToRootCopy, /*OpIdx*/0, // DstI[vdst] |
| 187015 | GIR_ComplexSubOperandRenderer, /*InsnID*/0, /*RendererID*/GIMT_Encode2(0), /*SubOperand*/0, // src0 |
| 187016 | GIR_RootToRootCopy, /*OpIdx*/2, // src1 |
| 187017 | GIR_RootToRootCopy, /*OpIdx*/3, // src2 |
| 187018 | GIR_RootConstrainSelectedInstOperands, |
| 187019 | // GIR_Coverage, 886, |
| 187020 | GIR_EraseRootFromParent_Done, |
| 187021 | // Label 8755: @585875 |
| 187022 | GIM_Reject, |
| 187023 | // Label 8753: @585876 |
| 187024 | GIM_Reject, |
| 187025 | // Label 166: @585877 |
| 187026 | GIM_Try, /*On fail goto*//*Label 8756*/ GIMT_Encode4(585907), // Rule ID 1111 // |
| 187027 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 187028 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 187029 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 187030 | // (SIfptrunc_round_downward:{ *:[f16] } f32:{ *:[f32] }:$src0) => (FPTRUNC_DOWNWARD_PSEUDO:{ *:[f16] } f32:{ *:[f32] }:$src0) |
| 187031 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_DOWNWARD_PSEUDO), |
| 187032 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 187033 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 187034 | GIR_RootConstrainSelectedInstOperands, |
| 187035 | // GIR_Coverage, 1111, |
| 187036 | GIR_Done, |
| 187037 | // Label 8756: @585907 |
| 187038 | GIM_Reject, |
| 187039 | // Label 167: @585908 |
| 187040 | GIM_Try, /*On fail goto*//*Label 8757*/ GIMT_Encode4(585938), // Rule ID 1110 // |
| 187041 | GIM_RootCheckType, /*Op*/0, /*Type*/GILLT_s16, |
| 187042 | GIM_RootCheckType, /*Op*/1, /*Type*/GILLT_s32, |
| 187043 | GIM_RootCheckRegBankForClass, /*Op*/0, /*RC*/GIMT_Encode2(AMDGPU::VGPR_32RegClassID), |
| 187044 | // (SIfptrunc_round_upward:{ *:[f16] } f32:{ *:[f32] }:$src0) => (FPTRUNC_UPWARD_PSEUDO:{ *:[f16] } f32:{ *:[f32] }:$src0) |
| 187045 | GIR_MutateOpcode, /*InsnID*/0, /*RecycleInsnID*/0, /*Opcode*/GIMT_Encode2(AMDGPU::FPTRUNC_UPWARD_PSEUDO), |
| 187046 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::MODE), |
| 187047 | GIR_AddImplicitUse, /*InsnID*/0, GIMT_Encode2(AMDGPU::EXEC), |
| 187048 | GIR_RootConstrainSelectedInstOperands, |
| 187049 | // GIR_Coverage, 1110, |
| 187050 | GIR_Done, |
| 187051 | // Label 8757: @585938 |
| 187052 | GIM_Reject, |
| 187053 | // Label 168: @585939 |
| 187054 | GIM_Reject, |
| 187055 | }; // Size: 585940 bytes |
| 187056 | return MatchTable0; |
| 187057 | } |
| 187058 | #undef GIMT_Encode2 |
| 187059 | #undef GIMT_Encode4 |
| 187060 | #undef GIMT_Encode8 |
| 187061 | |
| 187062 | #endif // ifdef GET_GLOBALISEL_IMPL |
| 187063 | |
| 187064 | #ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 187065 | PredicateBitset AvailableModuleFeatures; |
| 187066 | mutable PredicateBitset AvailableFunctionFeatures; |
| 187067 | PredicateBitset getAvailableFeatures() const { |
| 187068 | return AvailableModuleFeatures | AvailableFunctionFeatures; |
| 187069 | } |
| 187070 | PredicateBitset |
| 187071 | computeAvailableModuleFeatures(const AMDGPUSubtarget *Subtarget) const; |
| 187072 | PredicateBitset |
| 187073 | computeAvailableFunctionFeatures(const AMDGPUSubtarget *Subtarget, |
| 187074 | const MachineFunction *MF) const; |
| 187075 | void setupGeneratedPerFunctionState(MachineFunction &MF) override; |
| 187076 | #endif // ifdef GET_GLOBALISEL_PREDICATES_DECL |
| 187077 | #ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 187078 | AvailableModuleFeatures(computeAvailableModuleFeatures(&STI)), |
| 187079 | AvailableFunctionFeatures() |
| 187080 | #endif // ifdef GET_GLOBALISEL_PREDICATES_INIT |
| 187081 |
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